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#define | TMS570_EMIF_AWCC_WP1 BSP_BIT32(29) |
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#define | TMS570_EMIF_AWCC_WP0 BSP_BIT32(28) |
| #define | TMS570_EMIF_AWCC_CS5_WAIT(val) |
| #define | TMS570_EMIF_AWCC_CS5_WAIT_GET(reg) |
| #define | TMS570_EMIF_AWCC_CS5_WAIT_SET(reg, val) |
| #define | TMS570_EMIF_AWCC_CS4_WAIT(val) |
| #define | TMS570_EMIF_AWCC_CS4_WAIT_GET(reg) |
| #define | TMS570_EMIF_AWCC_CS4_WAIT_SET(reg, val) |
| #define | TMS570_EMIF_AWCC_CS3_WAIT(val) |
| #define | TMS570_EMIF_AWCC_CS3_WAIT_GET(reg) |
| #define | TMS570_EMIF_AWCC_CS3_WAIT_SET(reg, val) |
| #define | TMS570_EMIF_AWCC_CS2_WAIT(val) |
| #define | TMS570_EMIF_AWCC_CS2_WAIT_GET(reg) |
| #define | TMS570_EMIF_AWCC_CS2_WAIT_SET(reg, val) |
| #define | TMS570_EMIF_AWCC_MAX_EXT_WAIT(val) |
| #define | TMS570_EMIF_AWCC_MAX_EXT_WAIT_GET(reg) |
| #define | TMS570_EMIF_AWCC_MAX_EXT_WAIT_SET(reg, val) |
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#define | TMS570_EMIF_SDCR_SR BSP_BIT32(31) |
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#define | TMS570_EMIF_SDCR_PD BSP_BIT32(30) |
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#define | TMS570_EMIF_SDCR_PDWR BSP_BIT32(29) |
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#define | TMS570_EMIF_SDCR_NM BSP_BIT32(14) |
| #define | TMS570_EMIF_SDCR_CL(val) |
| #define | TMS570_EMIF_SDCR_CL_GET(reg) |
| #define | TMS570_EMIF_SDCR_CL_SET(reg, val) |
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#define | TMS570_EMIF_SDCR_BIT11_9LOCK BSP_BIT32(8) |
| #define | TMS570_EMIF_SDCR_IBANK(val) |
| #define | TMS570_EMIF_SDCR_IBANK_GET(reg) |
| #define | TMS570_EMIF_SDCR_IBANK_SET(reg, val) |
| #define | TMS570_EMIF_SDCR_PAGESIZE(val) |
| #define | TMS570_EMIF_SDCR_PAGESIZE_GET(reg) |
| #define | TMS570_EMIF_SDCR_PAGESIZE_SET(reg, val) |
| #define | TMS570_EMIF_SDRCR_RR(val) |
| #define | TMS570_EMIF_SDRCR_RR_GET(reg) |
| #define | TMS570_EMIF_SDRCR_RR_SET(reg, val) |
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#define | TMS570_EMIF_CE2CFG_SS BSP_BIT32(31) |
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#define | TMS570_EMIF_CE2CFG_EW BSP_BIT32(30) |
| #define | TMS570_EMIF_CE2CFG_W_SETUP(val) |
| #define | TMS570_EMIF_CE2CFG_W_SETUP_GET(reg) |
| #define | TMS570_EMIF_CE2CFG_W_SETUP_SET(reg, val) |
| #define | TMS570_EMIF_CE2CFG_W_STROBE(val) |
| #define | TMS570_EMIF_CE2CFG_W_STROBE_GET(reg) |
| #define | TMS570_EMIF_CE2CFG_W_STROBE_SET(reg, val) |
| #define | TMS570_EMIF_CE2CFG_W_HOLD(val) |
| #define | TMS570_EMIF_CE2CFG_W_HOLD_GET(reg) |
| #define | TMS570_EMIF_CE2CFG_W_HOLD_SET(reg, val) |
| #define | TMS570_EMIF_CE2CFG_R_SETUP(val) |
| #define | TMS570_EMIF_CE2CFG_R_SETUP_GET(reg) |
| #define | TMS570_EMIF_CE2CFG_R_SETUP_SET(reg, val) |
| #define | TMS570_EMIF_CE2CFG_R_STROBE(val) |
| #define | TMS570_EMIF_CE2CFG_R_STROBE_GET(reg) |
| #define | TMS570_EMIF_CE2CFG_R_STROBE_SET(reg, val) |
| #define | TMS570_EMIF_CE2CFG_R_HOLD(val) |
| #define | TMS570_EMIF_CE2CFG_R_HOLD_GET(reg) |
| #define | TMS570_EMIF_CE2CFG_R_HOLD_SET(reg, val) |
| #define | TMS570_EMIF_CE2CFG_TA(val) |
| #define | TMS570_EMIF_CE2CFG_TA_GET(reg) |
| #define | TMS570_EMIF_CE2CFG_TA_SET(reg, val) |
| #define | TMS570_EMIF_CE2CFG_ASIZE(val) |
| #define | TMS570_EMIF_CE2CFG_ASIZE_GET(reg) |
| #define | TMS570_EMIF_CE2CFG_ASIZE_SET(reg, val) |
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#define | TMS570_EMIF_CE3CFG_SS BSP_BIT32(31) |
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#define | TMS570_EMIF_CE3CFG_EW BSP_BIT32(30) |
| #define | TMS570_EMIF_CE3CFG_W_SETUP(val) |
| #define | TMS570_EMIF_CE3CFG_W_SETUP_GET(reg) |
| #define | TMS570_EMIF_CE3CFG_W_SETUP_SET(reg, val) |
| #define | TMS570_EMIF_CE3CFG_W_STROBE(val) |
| #define | TMS570_EMIF_CE3CFG_W_STROBE_GET(reg) |
| #define | TMS570_EMIF_CE3CFG_W_STROBE_SET(reg, val) |
| #define | TMS570_EMIF_CE3CFG_W_HOLD(val) |
| #define | TMS570_EMIF_CE3CFG_W_HOLD_GET(reg) |
| #define | TMS570_EMIF_CE3CFG_W_HOLD_SET(reg, val) |
| #define | TMS570_EMIF_CE3CFG_R_SETUP(val) |
| #define | TMS570_EMIF_CE3CFG_R_SETUP_GET(reg) |
| #define | TMS570_EMIF_CE3CFG_R_SETUP_SET(reg, val) |
| #define | TMS570_EMIF_CE3CFG_R_STROBE(val) |
| #define | TMS570_EMIF_CE3CFG_R_STROBE_GET(reg) |
| #define | TMS570_EMIF_CE3CFG_R_STROBE_SET(reg, val) |
| #define | TMS570_EMIF_CE3CFG_R_HOLD(val) |
| #define | TMS570_EMIF_CE3CFG_R_HOLD_GET(reg) |
| #define | TMS570_EMIF_CE3CFG_R_HOLD_SET(reg, val) |
| #define | TMS570_EMIF_CE3CFG_TA(val) |
| #define | TMS570_EMIF_CE3CFG_TA_GET(reg) |
| #define | TMS570_EMIF_CE3CFG_TA_SET(reg, val) |
| #define | TMS570_EMIF_CE3CFG_ASIZE(val) |
| #define | TMS570_EMIF_CE3CFG_ASIZE_GET(reg) |
| #define | TMS570_EMIF_CE3CFG_ASIZE_SET(reg, val) |
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#define | TMS570_EMIF_CE4CFG_SS BSP_BIT32(31) |
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#define | TMS570_EMIF_CE4CFG_EW BSP_BIT32(30) |
| #define | TMS570_EMIF_CE4CFG_W_SETUP(val) |
| #define | TMS570_EMIF_CE4CFG_W_SETUP_GET(reg) |
| #define | TMS570_EMIF_CE4CFG_W_SETUP_SET(reg, val) |
| #define | TMS570_EMIF_CE4CFG_W_STROBE(val) |
| #define | TMS570_EMIF_CE4CFG_W_STROBE_GET(reg) |
| #define | TMS570_EMIF_CE4CFG_W_STROBE_SET(reg, val) |
| #define | TMS570_EMIF_CE4CFG_W_HOLD(val) |
| #define | TMS570_EMIF_CE4CFG_W_HOLD_GET(reg) |
| #define | TMS570_EMIF_CE4CFG_W_HOLD_SET(reg, val) |
| #define | TMS570_EMIF_CE4CFG_R_SETUP(val) |
| #define | TMS570_EMIF_CE4CFG_R_SETUP_GET(reg) |
| #define | TMS570_EMIF_CE4CFG_R_SETUP_SET(reg, val) |
| #define | TMS570_EMIF_CE4CFG_R_STROBE(val) |
| #define | TMS570_EMIF_CE4CFG_R_STROBE_GET(reg) |
| #define | TMS570_EMIF_CE4CFG_R_STROBE_SET(reg, val) |
| #define | TMS570_EMIF_CE4CFG_R_HOLD(val) |
| #define | TMS570_EMIF_CE4CFG_R_HOLD_GET(reg) |
| #define | TMS570_EMIF_CE4CFG_R_HOLD_SET(reg, val) |
| #define | TMS570_EMIF_CE4CFG_TA(val) |
| #define | TMS570_EMIF_CE4CFG_TA_GET(reg) |
| #define | TMS570_EMIF_CE4CFG_TA_SET(reg, val) |
| #define | TMS570_EMIF_CE4CFG_ASIZE(val) |
| #define | TMS570_EMIF_CE4CFG_ASIZE_GET(reg) |
| #define | TMS570_EMIF_CE4CFG_ASIZE_SET(reg, val) |
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#define | TMS570_EMIF_CE5CFG_SS BSP_BIT32(31) |
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#define | TMS570_EMIF_CE5CFG_EW BSP_BIT32(30) |
| #define | TMS570_EMIF_CE5CFG_W_SETUP(val) |
| #define | TMS570_EMIF_CE5CFG_W_SETUP_GET(reg) |
| #define | TMS570_EMIF_CE5CFG_W_SETUP_SET(reg, val) |
| #define | TMS570_EMIF_CE5CFG_W_STROBE(val) |
| #define | TMS570_EMIF_CE5CFG_W_STROBE_GET(reg) |
| #define | TMS570_EMIF_CE5CFG_W_STROBE_SET(reg, val) |
| #define | TMS570_EMIF_CE5CFG_W_HOLD(val) |
| #define | TMS570_EMIF_CE5CFG_W_HOLD_GET(reg) |
| #define | TMS570_EMIF_CE5CFG_W_HOLD_SET(reg, val) |
| #define | TMS570_EMIF_CE5CFG_R_SETUP(val) |
| #define | TMS570_EMIF_CE5CFG_R_SETUP_GET(reg) |
| #define | TMS570_EMIF_CE5CFG_R_SETUP_SET(reg, val) |
| #define | TMS570_EMIF_CE5CFG_R_STROBE(val) |
| #define | TMS570_EMIF_CE5CFG_R_STROBE_GET(reg) |
| #define | TMS570_EMIF_CE5CFG_R_STROBE_SET(reg, val) |
| #define | TMS570_EMIF_CE5CFG_R_HOLD(val) |
| #define | TMS570_EMIF_CE5CFG_R_HOLD_GET(reg) |
| #define | TMS570_EMIF_CE5CFG_R_HOLD_SET(reg, val) |
| #define | TMS570_EMIF_CE5CFG_TA(val) |
| #define | TMS570_EMIF_CE5CFG_TA_GET(reg) |
| #define | TMS570_EMIF_CE5CFG_TA_SET(reg, val) |
| #define | TMS570_EMIF_CE5CFG_ASIZE(val) |
| #define | TMS570_EMIF_CE5CFG_ASIZE_GET(reg) |
| #define | TMS570_EMIF_CE5CFG_ASIZE_SET(reg, val) |
| #define | TMS570_EMIF_SDTIMR_T_RFC(val) |
| #define | TMS570_EMIF_SDTIMR_T_RFC_GET(reg) |
| #define | TMS570_EMIF_SDTIMR_T_RFC_SET(reg, val) |
| #define | TMS570_EMIF_SDTIMR_T_RP(val) |
| #define | TMS570_EMIF_SDTIMR_T_RP_GET(reg) |
| #define | TMS570_EMIF_SDTIMR_T_RP_SET(reg, val) |
| #define | TMS570_EMIF_SDTIMR_T_RCD(val) |
| #define | TMS570_EMIF_SDTIMR_T_RCD_GET(reg) |
| #define | TMS570_EMIF_SDTIMR_T_RCD_SET(reg, val) |
| #define | TMS570_EMIF_SDTIMR_T_WR(val) |
| #define | TMS570_EMIF_SDTIMR_T_WR_GET(reg) |
| #define | TMS570_EMIF_SDTIMR_T_WR_SET(reg, val) |
| #define | TMS570_EMIF_SDTIMR_T_RAS(val) |
| #define | TMS570_EMIF_SDTIMR_T_RAS_GET(reg) |
| #define | TMS570_EMIF_SDTIMR_T_RAS_SET(reg, val) |
| #define | TMS570_EMIF_SDTIMR_T_RC(val) |
| #define | TMS570_EMIF_SDTIMR_T_RC_GET(reg) |
| #define | TMS570_EMIF_SDTIMR_T_RC_SET(reg, val) |
| #define | TMS570_EMIF_SDTIMR_T_RRD(val) |
| #define | TMS570_EMIF_SDTIMR_T_RRD_GET(reg) |
| #define | TMS570_EMIF_SDTIMR_T_RRD_SET(reg, val) |
| #define | TMS570_EMIF_SDSRETR_T_XS(val) |
| #define | TMS570_EMIF_SDSRETR_T_XS_GET(reg) |
| #define | TMS570_EMIF_SDSRETR_T_XS_SET(reg, val) |
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#define | TMS570_EMIF_INTRAW_WR BSP_BIT32(2) |
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#define | TMS570_EMIF_INTRAW_LT BSP_BIT32(1) |
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#define | TMS570_EMIF_INTRAW_AT BSP_BIT32(0) |
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#define | TMS570_EMIF_INTMSK_WR_MASKED BSP_BIT32(2) |
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#define | TMS570_EMIF_INTMSK_LT_MASKED BSP_BIT32(1) |
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#define | TMS570_EMIF_INTMSK_AT_MASKED BSP_BIT32(0) |
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#define | TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_BIT32(2) |
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#define | TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_BIT32(1) |
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#define | TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_BIT32(0) |
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#define | TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_BIT32(2) |
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#define | TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_BIT32(1) |
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#define | TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_BIT32(0) |
| #define | TMS570_EMIF_PMCR_CS5_PG_DEL(val) |
| #define | TMS570_EMIF_PMCR_CS5_PG_DEL_GET(reg) |
| #define | TMS570_EMIF_PMCR_CS5_PG_DEL_SET(reg, val) |
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#define | TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_BIT32(25) |
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#define | TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_BIT32(24) |
| #define | TMS570_EMIF_PMCR_CS4_PG_DEL(val) |
| #define | TMS570_EMIF_PMCR_CS4_PG_DEL_GET(reg) |
| #define | TMS570_EMIF_PMCR_CS4_PG_DEL_SET(reg, val) |
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#define | TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_BIT32(17) |
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#define | TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_BIT32(16) |
| #define | TMS570_EMIF_PMCR_CS3_PG_DEL(val) |
| #define | TMS570_EMIF_PMCR_CS3_PG_DEL_GET(reg) |
| #define | TMS570_EMIF_PMCR_CS3_PG_DEL_SET(reg, val) |
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#define | TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_BIT32(9) |
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#define | TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_BIT32(8) |
| #define | TMS570_EMIF_PMCR_CS2_PG_DEL(val) |
| #define | TMS570_EMIF_PMCR_CS2_PG_DEL_GET(reg) |
| #define | TMS570_EMIF_PMCR_CS2_PG_DEL_SET(reg, val) |
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#define | TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_BIT32(1) |
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#define | TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_BIT32(0) |
This header file provides EMIF interfaces.