RTEMS
6.3
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bsps
arm
gumstix
include
pxa255.h
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/*
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* By Yang Xi <hiyangxi@gmail.com>.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef __PXA_255_H__
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#define __PXA_255_H__
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typedef
unsigned
int
word_t;
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/*Interrupt*/
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#define PRIMARY_IRQS 32
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#define GPIO_IRQS (85 - 2)
/* The first two IRQs have level
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one interrupts */
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#define GPIO_IRQ 10
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#define IRQS (PRIMARY_IRQS + GPIO_IRQS)
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/* Interrupt Controller */
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#define INTERRUPT_OFFSET 0xd00000
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#define XSCALE_IRQ_OS_TIMER 26
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#define XSCALE_IRQ_PMU 12
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#define XSCALE_IRQ_STUART 20
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#define XSCALE_IRQ_NETWORK 16
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#define PMU_IRQ 12
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#define CCNT_IRQ_ENABLE 1UL << 6
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#define PMN1_IRQ_ENABLE 1UL << 5
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#define PMN0_IRQ_ENABLE 1UL << 4
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#define IODEVICE_VADDR 0x40000000
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#define XSCALE_INT (IODEVICE_VADDR + INTERRUPT_OFFSET)
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#define XSCALE_INT_ICMR (*(volatile word_t *)(XSCALE_INT + 0x04))
/* Mask register */
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#define XSCALE_INT_ICLR (*(volatile word_t *)(XSCALE_INT + 0x08))
/* FIQ / IRQ selection */
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#define XSCALE_INT_ICCR (*(volatile word_t *)(XSCALE_INT + 0x14))
/* Control register */
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#define XSCALE_INT_ICIP (*(volatile word_t *)(XSCALE_INT + 0x00))
/* IRQ pending */
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#define XSCALE_INT_ICFP (*(volatile word_t *)(XSCALE_INT + 0x0c))
/* FIQ pending */
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#define XSCALE_INT_ICPR (*(volatile word_t *)(XSCALE_INT + 0x10))
/* Pending (unmasked) */
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/* GPIO */
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#define GPIO_OFFSET 0xe00000
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#define PXA_GPIO (IODEVICE_VADDR + GPIO_OFFSET)
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#define PXA_GEDR0 (*(volatile word_t *)(PXA_GPIO + 0x48))
/* GPIO edge detect 0 */
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#define PXA_GEDR1 (*(volatile word_t *)(PXA_GPIO + 0x4C))
/* GPIO edge detect 1 */
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#define PXA_GEDR2 (*(volatile word_t *)(PXA_GPIO + 0x50))
/* GPIO edge detect 2 */
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/* PXA2XX Timer */
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#define TIMER_OFFSET 0x0a00000
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#define CLOCKS_OFFSET 0x1300000
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/*I change the TIMER_RATE to 36864,because when I use 3686400, the period will be calculate
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to 30000*/
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#define TIMER_RATE 36864
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#define XSCALE_TIMERS (IODEVICE_VADDR + TIMER_OFFSET)
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/* Match registers */
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#define XSCALE_OS_TIMER_MR0 (*(volatile word_t *)(XSCALE_TIMERS + 0x00))
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#define XSCALE_OS_TIMER_MR1 (*(volatile word_t *)(XSCALE_TIMERS + 0x04))
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#define XSCALE_OS_TIMER_MR2 (*(volatile word_t *)(XSCALE_TIMERS + 0x08))
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#define XSCALE_OS_TIMER_MR3 (*(volatile word_t *)(XSCALE_TIMERS + 0x0c))
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/* Interrupt enable register */
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#define XSCALE_OS_TIMER_IER (*(volatile word_t *)(XSCALE_TIMERS + 0x1c))
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/* Watchdog match enable register */
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#define XSCALE_OS_TIMER_WMER (*(volatile word_t *)(XSCALE_TIMERS + 0x18))
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/* Timer count register */
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#define XSCALE_OS_TIMER_TCR (*(volatile word_t *)(XSCALE_TIMERS + 0x10))
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/* Timer status register */
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#define XSCALE_OS_TIMER_TSR (*(volatile word_t *)(XSCALE_TIMERS + 0x14))
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#define XSCALE_CLOCKS (IODEVICE_VADDR + CLOCKS_VOFFSET)
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#define XSCALE_CLOCKS_CCCR (*(volatile word_t *)(XSCALE_CLOCKS + 0x00))
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/*Use ffuart port as the console*/
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#define FFUART_BASE 0x40100000
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/*Write to SKYEYE_MAGIC_ADDRESS to make SKYEYE exit*/
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#define SKYEYE_MAGIC_ADDRESS (*(volatile word_t *)(0xb0000000))
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#define SKYEYE_MAGIC_NUMBER (0xf0f0f0f0)
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/*PMC*/
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#define PMC_PMNC 0
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#define PMC_CCNT 1
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#define PMC_INTEN 2
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#define PMC_FLAG 3
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#define PMC_EVTSEL 4
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#define PMC_PMN0 5
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#define PMC_PMN1 6
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#define PMC_PMN2 7
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#define PMC_PMN3 8
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#define PMC_PMNC_E (0x01)
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#define PMC_PMNC_PCR (0x01 << 1)
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#define PMC_PMNC_CCR (0x01 << 2)
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#define PMC_PMNC_CCD (0x01 << 3)
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#define PMC_PMNC_PCD (0x01 << 4)
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/*LCD*/
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#define LCCR0 (*(volatile word_t *)(0x44000000))
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#define LCCR1 (*(volatile word_t *)(0x44000004))
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#define LCCR2 (*(volatile word_t *)(0x44000008))
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#define LCCR3 (*(volatile word_t *)(0x4400000C))
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#define FDADR0 (*(volatile word_t *)(0x44000200))
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#define FSADR0 (*(volatile word_t *)(0x44000204))
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#define FIDR0 (*(volatile word_t *)(0x44000208))
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#define LDCMD0 (*(volatile word_t *)(0x4400020C))
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#define FDADR1 (*(volatile word_t *)(0x44000210))
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#define FSADR1 (*(volatile word_t *)(0x44000214))
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#define FIDR1 (*(volatile word_t *)(0x44000218))
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#define LDCMD1 (*(volatile word_t *)(0x4400021C))
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#define LCCR0_ENB 0x00000001
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#define LCCR1_PPL 0x000003FF
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#define LCCR2_LPP 0x000003FF
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#define LCCR3_BPP 0x07000000
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#endif
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