RTEMS 6.3
Loading...
Searching...
No Matches
pgtable.h
1/*
2 * pgtable.h
3 *
4 * PowerPC memory management structures
5 *
6 * It is a stripped down version of linux ppc file...
7 *
8 * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
9 * Canon Centre Recherche France.
10 *
11 * The license and distribution terms for this file may be
12 * found in the file LICENSE in this distribution or at
13 * http://www.rtems.org/license/LICENSE.
14 */
15
16#ifndef _LIBCPU_PGTABLE_H
17#define _LIBCPU_PGTABLE_H
18
19/*
20 * The PowerPC MMU uses a hash table containing PTEs, together with
21 * a set of 16 segment registers (on 32-bit implementations), to define
22 * the virtual to physical address mapping.
23 *
24 * We use the hash table as an extended TLB, i.e. a cache of currently
25 * active mappings. We maintain a two-level page table tree, much like
26 * that used by the i386, for the sake of the Linux memory management code.
27 * Low-level assembler code in head.S (procedure hash_page) is responsible
28 * for extracting ptes from the tree and putting them into the hash table
29 * when necessary, and updating the accessed and modified bits in the
30 * page table tree.
31 *
32 * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
33 * We also use the two level tables, but we can put the real bits in them
34 * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
35 * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
36 * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
37 * based upon user/super access. The TLB does not have accessed nor write
38 * protect. We assume that if the TLB get loaded with an entry it is
39 * accessed, and overload the changed bit for write protect. We use
40 * two bits in the software pte that are supposed to be set to zero in
41 * the TLB entry (24 and 25) for these indicators. Although the level 1
42 * descriptor contains the guarded and writethrough/copyback bits, we can
43 * set these at the page level since they get copied from the Mx_TWC
44 * register when the TLB entry is loaded. We will use bit 27 for guard, since
45 * that is where it exists in the MD_TWC, and bit 26 for writethrough.
46 * These will get masked from the level 2 descriptor at TLB load time, and
47 * copied to the MD_TWC before it gets loaded.
48 */
49
50/* PMD_SHIFT determines the size of the area mapped by the second-level page tables */
51#define PMD_SHIFT 22
52#define PMD_SIZE (1UL << PMD_SHIFT)
53#define PMD_MASK (~(PMD_SIZE-1))
54
55/* PGDIR_SHIFT determines what a third-level page table entry can map */
56#define PGDIR_SHIFT 22
57#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
58#define PGDIR_MASK (~(PGDIR_SIZE-1))
59
60/*
61 * entries per page directory level: our page-table tree is two-level, so
62 * we don't really have any PMD directory.
63 */
64#define PTRS_PER_PTE 1024
65#define PTRS_PER_PMD 1
66#define PTRS_PER_PGD 1024
67#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
68
69/* Just any arbitrary offset to the start of the vmalloc VM area: the
70 * current 64MB value just means that there will be a 64MB "hole" after the
71 * physical memory until the kernel virtual memory starts. That means that
72 * any out-of-bounds memory accesses will hopefully be caught.
73 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
74 * area for the same reason. ;)
75 *
76 * We no longer map larger than phys RAM with the BATs so we don't have
77 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry
78 * about clashes between our early calls to ioremap() that start growing down
79 * from ioremap_base being run into the VM area allocations (growing upwards
80 * from VMALLOC_START). For this reason we have ioremap_bot to check when
81 * we actually run into our mappings setup in the early boot with the VM
82 * system. This really does become a problem for machines with good amounts
83 * of RAM. -- Cort
84 */
85#define VMALLOC_OFFSET (0x4000000) /* 64M */
86#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
87#define VMALLOC_VMADDR(x) ((unsigned long)(x))
88#define VMALLOC_END ioremap_bot
89
90/*
91 * Bits in a linux-style PTE. These match the bits in the
92 * (hardware-defined) PowerPC PTE as closely as possible.
93 */
94#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
95#define _PAGE_USER 0x002 /* matches one of the PP bits */
96#define _PAGE_RW 0x004 /* software: user write access allowed */
97#define _PAGE_GUARDED 0x008
98#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
99#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
100#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
101#define _PAGE_DIRTY 0x080 /* C: page changed */
102#define _PAGE_ACCESSED 0x100 /* R: page referenced */
103#define _PAGE_HWWRITE 0x200 /* software: _PAGE_RW & _PAGE_DIRTY */
104#define _PAGE_SHARED 0
105
106#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
107
108#define _PAGE_BASE _PAGE_PRESENT | _PAGE_ACCESSED
109#define _PAGE_WRENABLE _PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE
110
111#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
112
113#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | \
114 _PAGE_SHARED)
115#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
116#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
117#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED)
118#define PAGE_KERNEL_CI __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | \
119 _PAGE_NO_CACHE )
120
121/*
122 * The PowerPC can only do execute protection on a segment (256MB) basis,
123 * not on a page basis. So we consider execute permission the same as read.
124 * Also, write permissions imply read permissions.
125 * This is the closest we can get..
126 */
127#define __P000 PAGE_NONE
128#define __P001 PAGE_READONLY
129#define __P010 PAGE_COPY
130#define __P011 PAGE_COPY
131#define __P100 PAGE_READONLY
132#define __P101 PAGE_READONLY
133#define __P110 PAGE_COPY
134#define __P111 PAGE_COPY
135
136#define __S000 PAGE_NONE
137#define __S001 PAGE_READONLY
138#define __S010 PAGE_SHARED
139#define __S011 PAGE_SHARED
140#define __S100 PAGE_READONLY
141#define __S101 PAGE_READONLY
142#define __S110 PAGE_SHARED
143#define __S111 PAGE_SHARED
144#endif /* _LIBCPU_PGTABLE_H */
Generated by doxygen 1.18.0