RTEMS
6.3
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bsps
arm
atsam
include
libchip
include
mpu.h
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) 2015, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _MPU_H_
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#define _MPU_H_
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#ifdef __rtems__
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#include <bsp.h>
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#endif
/* __rtems__ */
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/*----------------------------------------------------------------------------
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* Definitions
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*----------------------------------------------------------------------------*/
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#define ARM_MODE_USR 0x10
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#define PRIVILEGE_MODE 0
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#define USER_MODE 1
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#define MPU_DEFAULT_ITCM_REGION (1)
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#define MPU_DEFAULT_IFLASH_REGION (2)
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#define MPU_DEFAULT_DTCM_REGION (3)
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#define MPU_DEFAULT_SRAM_REGION_1 (4)
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#define MPU_DEFAULT_SRAM_REGION_2 (5)
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#define MPU_PERIPHERALS_REGION (6)
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#define MPU_EXT_EBI_REGION (7)
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#define MPU_DEFAULT_SDRAM_REGION (8)
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#define MPU_QSPIMEM_REGION (9)
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#define MPU_USBHSRAM_REGION (10)
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#if defined MPU_HAS_NOCACHE_REGION
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#define MPU_NOCACHE_SRAM_REGION (11)
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#endif
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#define MPU_SYSTEM_REGION (12)
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#ifdef __rtems__
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#define MPU_NULL_REGION (13)
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/* Reserve the region with highest priority for user applications */
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#define MPU_USER_DEFINED_REGION (15)
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#endif
/* __rtems__ */
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#define MPU_REGION_VALID (0x10)
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#define MPU_REGION_ENABLE (0x01)
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#define MPU_REGION_DISABLE (0x0)
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#define MPU_ENABLE (0x1 << MPU_CTRL_ENABLE_Pos)
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#define MPU_HFNMIENA (0x1 << MPU_CTRL_HFNMIENA_Pos)
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#define MPU_PRIVDEFENA (0x1 << MPU_CTRL_PRIVDEFENA_Pos)
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#define MPU_REGION_BUFFERABLE (0x01 << MPU_RASR_B_Pos)
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#define MPU_REGION_CACHEABLE (0x01 << MPU_RASR_C_Pos)
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#define MPU_REGION_SHAREABLE (0x01 << MPU_RASR_S_Pos)
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#define MPU_REGION_EXECUTE_NEVER (0x01 << MPU_RASR_XN_Pos)
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#define MPU_AP_NO_ACCESS (0x00 << MPU_RASR_AP_Pos)
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#define MPU_AP_PRIVILEGED_READ_WRITE (0x01 << MPU_RASR_AP_Pos)
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#define MPU_AP_UNPRIVILEGED_READONLY (0x02 << MPU_RASR_AP_Pos)
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#define MPU_AP_FULL_ACCESS (0x03 << MPU_RASR_AP_Pos)
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#define MPU_AP_RES (0x04 << MPU_RASR_AP_Pos)
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#define MPU_AP_PRIVILEGED_READONLY (0x05 << MPU_RASR_AP_Pos)
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#define MPU_AP_READONLY (0x06 << MPU_RASR_AP_Pos)
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#define MPU_AP_READONLY2 (0x07 << MPU_RASR_AP_Pos)
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#define MPU_TEX_B000 (0x01 << MPU_RASR_TEX_Pos)
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#define MPU_TEX_B001 (0x01 << MPU_RASR_TEX_Pos)
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#define MPU_TEX_B010 (0x01 << MPU_RASR_TEX_Pos)
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#define MPU_TEX_B011 (0x01 << MPU_RASR_TEX_Pos)
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#define MPU_TEX_B100 (0x01 << MPU_RASR_TEX_Pos)
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#define MPU_TEX_B101 (0x01 << MPU_RASR_TEX_Pos)
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#define MPU_TEX_B110 (0x01 << MPU_RASR_TEX_Pos)
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#define MPU_TEX_B111 (0x01 << MPU_RASR_TEX_Pos)
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/* Default memory map
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Address range Memory region Memory type Shareability Cache policy
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0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT
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0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA
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0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable -
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0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA
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0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT
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0xA0000000- 0xBFFFFFFF Device Device Shareable
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0xC0000000- 0xDFFFFFFF Device Device Non Shareable
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0xE0000000- 0xFFFFFFFF System - -
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*/
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/********* IFLASH memory macros *********************/
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#ifdef __rtems__
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#define ITCM_START_ADDRESS ((uintptr_t) atsam_memory_itcm_begin)
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#define ITCM_END_ADDRESS ((uintptr_t) atsam_memory_itcm_end - 1)
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#define IFLASH_START_ADDRESS ((uintptr_t) atsam_memory_intflash_begin)
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#define IFLASH_END_ADDRESS ((uintptr_t) atsam_memory_intflash_end - 1)
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#else
/* !__rtems__ */
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#define ITCM_START_ADDRESS 0x00000000UL
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#define ITCM_END_ADDRESS 0x003FFFFFUL
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#define IFLASH_START_ADDRESS 0x00400000UL
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#define IFLASH_END_ADDRESS 0x005FFFFFUL
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#endif
/* __rtems__ */
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#define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS)
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#define IFLASH_PRIVILEGE_END_ADDRESS (IFLASH_START_ADDRESS + 0xFFF)
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#define IFLASH_UNPRIVILEGE_START_ADDRESS (IFLASH_PRIVILEGE_END_ADDRESS + 1)
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#define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS)
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/**************** DTCM *******************************/
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#ifdef __rtems__
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#define DTCM_START_ADDRESS ((uintptr_t) atsam_memory_dtcm_begin)
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#define DTCM_END_ADDRESS ((uintptr_t) atsam_memory_dtcm_end - 1)
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#else
/* !__rtems__ */
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#define DTCM_START_ADDRESS 0x20000000UL
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#define DTCM_END_ADDRESS 0x203FFFFFUL
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#endif
/* __rtems__ */
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/******* SRAM memory macros ***************************/
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#ifdef __rtems__
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#define SRAM_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin)
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#define SRAM_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1)
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#else
/* !__rtems__ */
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#define SRAM_START_ADDRESS 0x20400000UL
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#define SRAM_END_ADDRESS 0x2045FFFFUL
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#endif
/* __rtems__ */
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#ifndef __rtems__
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#if defined MPU_HAS_NOCACHE_REGION
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#define NOCACHE_SRAM_REGION_SIZE 0x1000
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#endif
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#endif
/* __rtems__ */
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/* Regions should be a 2^(N+1) where 4 < N < 31 */
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#ifdef __rtems__
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#define SRAM_FIRST_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin)
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#define SRAM_FIRST_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1)
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#else
/* !__rtems__ */
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#define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS)
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#define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF)
// (2^18) 256 KB
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#endif
/* __rtems__ */
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#if defined MPU_HAS_NOCACHE_REGION
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#ifdef __rtems__
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#define SRAM_NOCACHE_START_ADDRESS ((uintptr_t) atsam_memory_nocache_begin)
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#define SRAM_NOCACHE_END_ADDRESS ((uintptr_t) atsam_memory_nocache_end - 1)
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#define NOCACHE_SRAM_REGION_SIZE (SRAM_NOCACHE_END_ADDRESS - SRAM_NOCACHE_START_ADDRESS)
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#else
/* !__rtems__ */
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#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1)
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#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE)
// (2^17) 128 - 0x1000 KB
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#define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1)
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#define SRAM_NOCACHE_END_ADDRESS (SRAM_END_ADDRESS)
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#endif
/* __rtems__ */
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#else
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#ifndef __rtems__
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#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS + 1)
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#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS)
// (2^17) 128 KB
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#endif
/* __rtems__ */
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#endif
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/************** Peripherals memory region macros ********/
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#define PERIPHERALS_START_ADDRESS 0x40000000UL
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#define PERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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#ifdef __rtems__
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#define SYSTEM_START_ADDRESS 0xE0000000UL
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#define SYSTEM_END_ADDRESS 0xFFFFFFFFUL
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#endif
/* __rtems__ */
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/******* Ext EBI memory macros ***************************/
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#define EXT_EBI_START_ADDRESS 0x60000000UL
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#define EXT_EBI_END_ADDRESS 0x6FFFFFFFUL
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/******* Ext-SRAM memory macros ***************************/
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#ifdef __rtems__
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#define SDRAM_START_ADDRESS ((uintptr_t) atsam_memory_sdram_begin)
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#define SDRAM_END_ADDRESS ((uintptr_t) atsam_memory_sdram_end - 1)
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#else
/* !__rtems__ */
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#define SDRAM_START_ADDRESS 0x70000000UL
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#define SDRAM_END_ADDRESS 0x7FFFFFFFUL
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#endif
/* __rtems__ */
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/******* QSPI macros ***************************/
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#ifdef __rtems__
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#define QSPI_START_ADDRESS ((uintptr_t) atsam_memory_qspiflash_begin)
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#define QSPI_END_ADDRESS ((uintptr_t) atsam_memory_qspiflash_end - 1)
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#else
/* !__rtems__ */
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#define QSPI_START_ADDRESS 0x80000000UL
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#define QSPI_END_ADDRESS 0x9FFFFFFFUL
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#endif
/* __rtems__ */
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/************** USBHS_RAM region macros ******************/
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#define USBHSRAM_START_ADDRESS 0xA0100000UL
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#define USBHSRAM_END_ADDRESS 0xA01FFFFFUL
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/*----------------------------------------------------------------------------
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* Export functions
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*----------------------------------------------------------------------------*/
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void
MPU_Enable
(uint32_t dwMPUEnable);
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void
MPU_SetRegion
(uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr);
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void
MPU_SetRegionNum
(uint32_t dwRegionNum);
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void
MPU_DisableRegion
(
void
);
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uint32_t
MPU_CalMPURegionSize
(uint32_t dwActualSizeInBytes);
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void
MPU_UpdateRegions
(uint32_t dwRegionNum, uint32_t dwRegionBaseAddr,
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uint32_t dwRegionAttr);
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#endif
/* #ifndef _MMU_ */
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MPU_Enable
void MPU_Enable(uint32_t dwMPUEnable)
Enables the MPU module.
Definition
mpu.c:78
MPU_SetRegion
void MPU_SetRegion(uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr)
Setup a memory region.
Definition
mpu.c:107
MPU_CalMPURegionSize
uint32_t MPU_CalMPURegionSize(uint32_t dwActualSizeInBytes)
Calculate region size for the RASR.
Definition
mpu.c:117
MPU_SetRegionNum
void MPU_SetRegionNum(uint32_t dwRegionNum)
Set active memory region.
Definition
mpu.c:88
MPU_UpdateRegions
void MPU_UpdateRegions(uint32_t dwRegionNum, uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr)
Update MPU regions.
Definition
mpu.c:140
MPU_DisableRegion
void MPU_DisableRegion(void)
Disable the current active region.
Definition
mpu.c:96
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