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bsps
include
grlib
mmctrl-regs.h
Go to the documentation of this file.
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) 2021 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This file is part of the RTEMS quality process and was automatically
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* generated. If you find something that needs to be fixed or
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* worded better please post a report or patch to an RTEMS mailing list
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* or raise a bug report:
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*
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* https://www.rtems.org/bugs.html
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*
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* For information on updating and regenerating please refer to the How-To
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* section in the Software Requirements Engineering chapter of the
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* RTEMS Software Engineering manual. The manual is provided as a part of
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* a release. For development sources please refer to the online
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* documentation at:
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*
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* https://docs.rtems.org
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*/
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/* Generated from spec:/dev/grlib/if/mmctrl-header */
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#ifndef _GRLIB_MMCTRL_REGS_H
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#define _GRLIB_MMCTRL_REGS_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/* Generated from spec:/dev/grlib/if/mmctrl */
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#define MMCTRL_SDCFG1_RF 0x80000000U
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#define MMCTRL_SDCFG1_TRP 0x40000000U
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#define MMCTRL_SDCFG1_TRFC_SHIFT 27
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#define MMCTRL_SDCFG1_TRFC_MASK 0x38000000U
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#define MMCTRL_SDCFG1_TRFC_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_SDCFG1_TRFC_MASK ) >> \
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MMCTRL_SDCFG1_TRFC_SHIFT )
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#define MMCTRL_SDCFG1_TRFC_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_SDCFG1_TRFC_MASK ) | \
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( ( ( _val ) << MMCTRL_SDCFG1_TRFC_SHIFT ) & \
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MMCTRL_SDCFG1_TRFC_MASK ) )
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#define MMCTRL_SDCFG1_TRFC( _val ) \
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( ( ( _val ) << MMCTRL_SDCFG1_TRFC_SHIFT ) & \
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MMCTRL_SDCFG1_TRFC_MASK )
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#define MMCTRL_SDCFG1_TC 0x4000000U
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#define MMCTRL_SDCFG1_BANKSZ_SHIFT 23
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#define MMCTRL_SDCFG1_BANKSZ_MASK 0x3800000U
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#define MMCTRL_SDCFG1_BANKSZ_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_SDCFG1_BANKSZ_MASK ) >> \
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MMCTRL_SDCFG1_BANKSZ_SHIFT )
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#define MMCTRL_SDCFG1_BANKSZ_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_SDCFG1_BANKSZ_MASK ) | \
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( ( ( _val ) << MMCTRL_SDCFG1_BANKSZ_SHIFT ) & \
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MMCTRL_SDCFG1_BANKSZ_MASK ) )
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#define MMCTRL_SDCFG1_BANKSZ( _val ) \
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( ( ( _val ) << MMCTRL_SDCFG1_BANKSZ_SHIFT ) & \
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MMCTRL_SDCFG1_BANKSZ_MASK )
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#define MMCTRL_SDCFG1_COLSZ_SHIFT 21
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#define MMCTRL_SDCFG1_COLSZ_MASK 0x600000U
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#define MMCTRL_SDCFG1_COLSZ_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_SDCFG1_COLSZ_MASK ) >> \
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MMCTRL_SDCFG1_COLSZ_SHIFT )
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#define MMCTRL_SDCFG1_COLSZ_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_SDCFG1_COLSZ_MASK ) | \
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( ( ( _val ) << MMCTRL_SDCFG1_COLSZ_SHIFT ) & \
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MMCTRL_SDCFG1_COLSZ_MASK ) )
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#define MMCTRL_SDCFG1_COLSZ( _val ) \
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( ( ( _val ) << MMCTRL_SDCFG1_COLSZ_SHIFT ) & \
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MMCTRL_SDCFG1_COLSZ_MASK )
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#define MMCTRL_SDCFG1_COMMAND_SHIFT 18
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#define MMCTRL_SDCFG1_COMMAND_MASK 0x1c0000U
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#define MMCTRL_SDCFG1_COMMAND_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_SDCFG1_COMMAND_MASK ) >> \
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MMCTRL_SDCFG1_COMMAND_SHIFT )
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#define MMCTRL_SDCFG1_COMMAND_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_SDCFG1_COMMAND_MASK ) | \
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( ( ( _val ) << MMCTRL_SDCFG1_COMMAND_SHIFT ) & \
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MMCTRL_SDCFG1_COMMAND_MASK ) )
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#define MMCTRL_SDCFG1_COMMAND( _val ) \
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( ( ( _val ) << MMCTRL_SDCFG1_COMMAND_SHIFT ) & \
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MMCTRL_SDCFG1_COMMAND_MASK )
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#define MMCTRL_SDCFG1_MS 0x10000U
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#define MMCTRL_SDCFG1_64 0x8000U
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#define MMCTRL_SDCFG1_RFLOAD_SHIFT 0
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#define MMCTRL_SDCFG1_RFLOAD_MASK 0x7fffU
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#define MMCTRL_SDCFG1_RFLOAD_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_SDCFG1_RFLOAD_MASK ) >> \
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MMCTRL_SDCFG1_RFLOAD_SHIFT )
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#define MMCTRL_SDCFG1_RFLOAD_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_SDCFG1_RFLOAD_MASK ) | \
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( ( ( _val ) << MMCTRL_SDCFG1_RFLOAD_SHIFT ) & \
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MMCTRL_SDCFG1_RFLOAD_MASK ) )
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#define MMCTRL_SDCFG1_RFLOAD( _val ) \
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( ( ( _val ) << MMCTRL_SDCFG1_RFLOAD_SHIFT ) & \
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MMCTRL_SDCFG1_RFLOAD_MASK )
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#define MMCTRL_SDCFG2_CE 0x40000000U
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#define MMCTRL_SDCFG2_EN2T 0x8000U
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#define MMCTRL_SDCFG2_DCS 0x4000U
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#define MMCTRL_SDCFG2_BPARK 0x2000U
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#define MMCTRL_MUXCFG_ERRLOC_SHIFT 20
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#define MMCTRL_MUXCFG_ERRLOC_MASK 0xfff00000U
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#define MMCTRL_MUXCFG_ERRLOC_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_MUXCFG_ERRLOC_MASK ) >> \
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MMCTRL_MUXCFG_ERRLOC_SHIFT )
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#define MMCTRL_MUXCFG_ERRLOC_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_MUXCFG_ERRLOC_MASK ) | \
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( ( ( _val ) << MMCTRL_MUXCFG_ERRLOC_SHIFT ) & \
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MMCTRL_MUXCFG_ERRLOC_MASK ) )
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#define MMCTRL_MUXCFG_ERRLOC( _val ) \
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( ( ( _val ) << MMCTRL_MUXCFG_ERRLOC_SHIFT ) & \
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MMCTRL_MUXCFG_ERRLOC_MASK )
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#define MMCTRL_MUXCFG_DDERR 0x80000U
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#define MMCTRL_MUXCFG_DWIDTH_SHIFT 16
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#define MMCTRL_MUXCFG_DWIDTH_MASK 0x70000U
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#define MMCTRL_MUXCFG_DWIDTH_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_MUXCFG_DWIDTH_MASK ) >> \
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MMCTRL_MUXCFG_DWIDTH_SHIFT )
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#define MMCTRL_MUXCFG_DWIDTH_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_MUXCFG_DWIDTH_MASK ) | \
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( ( ( _val ) << MMCTRL_MUXCFG_DWIDTH_SHIFT ) & \
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MMCTRL_MUXCFG_DWIDTH_MASK ) )
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#define MMCTRL_MUXCFG_DWIDTH( _val ) \
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( ( ( _val ) << MMCTRL_MUXCFG_DWIDTH_SHIFT ) & \
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MMCTRL_MUXCFG_DWIDTH_MASK )
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#define MMCTRL_MUXCFG_BEID_SHIFT 12
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#define MMCTRL_MUXCFG_BEID_MASK 0xf000U
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#define MMCTRL_MUXCFG_BEID_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_MUXCFG_BEID_MASK ) >> \
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MMCTRL_MUXCFG_BEID_SHIFT )
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#define MMCTRL_MUXCFG_BEID_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_MUXCFG_BEID_MASK ) | \
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( ( ( _val ) << MMCTRL_MUXCFG_BEID_SHIFT ) & \
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MMCTRL_MUXCFG_BEID_MASK ) )
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#define MMCTRL_MUXCFG_BEID( _val ) \
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( ( ( _val ) << MMCTRL_MUXCFG_BEID_SHIFT ) & \
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MMCTRL_MUXCFG_BEID_MASK )
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#define MMCTRL_MUXCFG_DATAMUX_SHIFT 5
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#define MMCTRL_MUXCFG_DATAMUX_MASK 0xe0U
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#define MMCTRL_MUXCFG_DATAMUX_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_MUXCFG_DATAMUX_MASK ) >> \
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MMCTRL_MUXCFG_DATAMUX_SHIFT )
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#define MMCTRL_MUXCFG_DATAMUX_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_MUXCFG_DATAMUX_MASK ) | \
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( ( ( _val ) << MMCTRL_MUXCFG_DATAMUX_SHIFT ) & \
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MMCTRL_MUXCFG_DATAMUX_MASK ) )
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#define MMCTRL_MUXCFG_DATAMUX( _val ) \
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( ( ( _val ) << MMCTRL_MUXCFG_DATAMUX_SHIFT ) & \
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MMCTRL_MUXCFG_DATAMUX_MASK )
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#define MMCTRL_MUXCFG_CEN 0x10U
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#define MMCTRL_MUXCFG_BAUPD 0x8U
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#define MMCTRL_MUXCFG_BAEN 0x4U
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#define MMCTRL_MUXCFG_CODE 0x2U
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#define MMCTRL_MUXCFG_EDEN 0x1U
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#define MMCTRL_FTDA_FTDA_SHIFT 2
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#define MMCTRL_FTDA_FTDA_MASK 0xfffffffcU
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#define MMCTRL_FTDA_FTDA_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_FTDA_FTDA_MASK ) >> \
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MMCTRL_FTDA_FTDA_SHIFT )
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#define MMCTRL_FTDA_FTDA_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_FTDA_FTDA_MASK ) | \
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( ( ( _val ) << MMCTRL_FTDA_FTDA_SHIFT ) & \
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MMCTRL_FTDA_FTDA_MASK ) )
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#define MMCTRL_FTDA_FTDA( _val ) \
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( ( ( _val ) << MMCTRL_FTDA_FTDA_SHIFT ) & \
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MMCTRL_FTDA_FTDA_MASK )
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#define MMCTRL_FTDC_CBD_SHIFT 24
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#define MMCTRL_FTDC_CBD_MASK 0xff000000U
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#define MMCTRL_FTDC_CBD_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_FTDC_CBD_MASK ) >> \
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MMCTRL_FTDC_CBD_SHIFT )
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#define MMCTRL_FTDC_CBD_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_FTDC_CBD_MASK ) | \
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( ( ( _val ) << MMCTRL_FTDC_CBD_SHIFT ) & \
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MMCTRL_FTDC_CBD_MASK ) )
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#define MMCTRL_FTDC_CBD( _val ) \
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( ( ( _val ) << MMCTRL_FTDC_CBD_SHIFT ) & \
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MMCTRL_FTDC_CBD_MASK )
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#define MMCTRL_FTDC_CBC_SHIFT 16
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#define MMCTRL_FTDC_CBC_MASK 0xff0000U
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#define MMCTRL_FTDC_CBC_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_FTDC_CBC_MASK ) >> \
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MMCTRL_FTDC_CBC_SHIFT )
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#define MMCTRL_FTDC_CBC_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_FTDC_CBC_MASK ) | \
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( ( ( _val ) << MMCTRL_FTDC_CBC_SHIFT ) & \
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MMCTRL_FTDC_CBC_MASK ) )
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#define MMCTRL_FTDC_CBC( _val ) \
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( ( ( _val ) << MMCTRL_FTDC_CBC_SHIFT ) & \
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MMCTRL_FTDC_CBC_MASK )
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#define MMCTRL_FTDC_CBB_SHIFT 8
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#define MMCTRL_FTDC_CBB_MASK 0xff00U
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#define MMCTRL_FTDC_CBB_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_FTDC_CBB_MASK ) >> \
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MMCTRL_FTDC_CBB_SHIFT )
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#define MMCTRL_FTDC_CBB_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_FTDC_CBB_MASK ) | \
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( ( ( _val ) << MMCTRL_FTDC_CBB_SHIFT ) & \
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MMCTRL_FTDC_CBB_MASK ) )
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#define MMCTRL_FTDC_CBB( _val ) \
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( ( ( _val ) << MMCTRL_FTDC_CBB_SHIFT ) & \
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MMCTRL_FTDC_CBB_MASK )
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#define MMCTRL_FTDC_CBA_SHIFT 0
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#define MMCTRL_FTDC_CBA_MASK 0xffU
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#define MMCTRL_FTDC_CBA_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_FTDC_CBA_MASK ) >> \
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MMCTRL_FTDC_CBA_SHIFT )
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#define MMCTRL_FTDC_CBA_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_FTDC_CBA_MASK ) | \
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( ( ( _val ) << MMCTRL_FTDC_CBA_SHIFT ) & \
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MMCTRL_FTDC_CBA_MASK ) )
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#define MMCTRL_FTDC_CBA( _val ) \
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( ( ( _val ) << MMCTRL_FTDC_CBA_SHIFT ) & \
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MMCTRL_FTDC_CBA_MASK )
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#define MMCTRL_FTDD_DATA_SHIFT 0
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#define MMCTRL_FTDD_DATA_MASK 0xffffffffU
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#define MMCTRL_FTDD_DATA_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_FTDD_DATA_MASK ) >> \
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MMCTRL_FTDD_DATA_SHIFT )
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#define MMCTRL_FTDD_DATA_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_FTDD_DATA_MASK ) | \
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( ( ( _val ) << MMCTRL_FTDD_DATA_SHIFT ) & \
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MMCTRL_FTDD_DATA_MASK ) )
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#define MMCTRL_FTDD_DATA( _val ) \
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( ( ( _val ) << MMCTRL_FTDD_DATA_SHIFT ) & \
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MMCTRL_FTDD_DATA_MASK )
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#define MMCTRL_FTBND_FTBND_31_3_SHIFT 3
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#define MMCTRL_FTBND_FTBND_31_3_MASK 0xfffffff8U
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#define MMCTRL_FTBND_FTBND_31_3_GET( _reg ) \
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( ( ( _reg ) & MMCTRL_FTBND_FTBND_31_3_MASK ) >> \
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MMCTRL_FTBND_FTBND_31_3_SHIFT )
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#define MMCTRL_FTBND_FTBND_31_3_SET( _reg, _val ) \
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( ( ( _reg ) & ~MMCTRL_FTBND_FTBND_31_3_MASK ) | \
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( ( ( _val ) << MMCTRL_FTBND_FTBND_31_3_SHIFT ) & \
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MMCTRL_FTBND_FTBND_31_3_MASK ) )
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#define MMCTRL_FTBND_FTBND_31_3( _val ) \
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( ( ( _val ) << MMCTRL_FTBND_FTBND_31_3_SHIFT ) & \
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MMCTRL_FTBND_FTBND_31_3_MASK )
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typedef
struct
mmctrl
{
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uint32_t
sdcfg1
;
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uint32_t
sdcfg2
;
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uint32_t reserved_8_20[ 6 ];
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uint32_t
muxcfg
;
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uint32_t
ftda
;
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uint32_t
ftdc
;
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uint32_t
ftdd
;
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uint32_t
ftbnd
;
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}
mmctrl
;
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#ifdef __cplusplus
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}
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#endif
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#endif
/* _GRLIB_MMCTRL_REGS_H */
mmctrl
This structure defines the MMCTRL register block memory map.
Definition
mmctrl-regs.h:389
mmctrl::ftdc
uint32_t ftdc
See FT diagnostic checkbits register (FTDC).
Definition
mmctrl-regs.h:415
mmctrl::sdcfg1
uint32_t sdcfg1
See SDRAM configuration register 1 (SDCFG1).
Definition
mmctrl-regs.h:393
mmctrl::sdcfg2
uint32_t sdcfg2
See SDRAM configuration register 2 (SDCFG2).
Definition
mmctrl-regs.h:398
mmctrl::muxcfg
uint32_t muxcfg
See Mux configuration register (MUXCFG).
Definition
mmctrl-regs.h:405
mmctrl::ftbnd
uint32_t ftbnd
See FT boundary address register (FTBND).
Definition
mmctrl-regs.h:425
mmctrl::ftda
uint32_t ftda
See FT diagnostic address register (FTDA).
Definition
mmctrl-regs.h:410
mmctrl::ftdd
uint32_t ftdd
See FT diagnostic data register (FTDD).
Definition
mmctrl-regs.h:420
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