RTEMS 6.3
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iosh7032.h
1/*
2 * This include file contains information pertaining to the Hitachi SH
3 * processor.
4 *
5 * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
6 *
7 * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
8 * Bernd Becker (becker@faw.uni-ulm.de)
9 *
10 * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
11 * contained no copyright notice.
12 *
13 * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
18 *
19 *
20 * COPYRIGHT (c) 1998.
21 * On-Line Applications Research Corporation (OAR).
22 *
23 * The license and distribution terms for this file may be
24 * found in the file LICENSE in this distribution or at
25 * http://www.rtems.org/license/LICENSE.
26 */
27
28#ifndef __IOSH7030_H
29#define __IOSH7030_H
30
31/*
32 * After each line is explained whether the access is char short or long.
33 * The functions read/writeb, w, l, 8, 16, 32 can be found
34 * in exec/score/cpu/sh/sh_io.h
35 *
36 * 8 bit == char ( readb, writeb, read8, write8)
37 * 16 bit == short ( readw, writew, read16, write16 )
38 * 32 bit == long ( readl, writel, read32, write32 )
39 */
40
41#define SCI0_SMR 0x05fffec0 /* char */
42#define SCI0_BRR 0x05fffec1 /* char */
43#define SCI0_SCR 0x05fffec2 /* char */
44#define SCI0_TDR 0x05fffec3 /* char */
45#define SCI0_SSR 0x05fffec4 /* char */
46#define SCI0_RDR 0x05fffec5 /* char */
47
48#define SCI1_SMR 0x05fffec8 /* char */
49#define SCI1_BRR 0x05fffec9 /* char */
50#define SCI1_SCR 0x05fffeca /* char */
51#define SCI1_TDR 0x05fffecb /* char */
52#define SCI1_SSR 0x05fffecc /* char */
53#define SCI1_RDR 0x05fffecd /* char */
54
55
56#define ADDRAH 0x05fffee0 /* char */
57#define ADDRAL 0x05fffee1 /* char */
58#define ADDRBH 0x05fffee2 /* char */
59#define ADDRBL 0x05fffee3 /* char */
60#define ADDRCH 0x05fffee4 /* char */
61#define ADDRCL 0x05fffee5 /* char */
62#define ADDRDH 0x05fffee6 /* char */
63#define ADDRDL 0x05fffee7 /* char */
64#define AD_DRA 0x05fffee0 /* short */
65#define AD_DRB 0x05fffee2 /* short */
66#define AD_DRC 0x05fffee4 /* short */
67#define AD_DRD 0x05fffee6 /* short */
68#define ADCSR 0x05fffee8 /* char */
69#define ADCR 0x05fffee9 /* char */
70
71/*ITU SHARED*/
72#define ITU_TSTR 0x05ffff00 /* char */
73#define ITU_TSNC 0x05ffff01 /* char */
74#define ITU_TMDR 0x05ffff02 /* char */
75#define ITU_TFCR 0x05ffff03 /* char */
76
77/*ITU CHANNEL 0*/
78#define ITU_TCR0 0x05ffff04 /* char */
79#define ITU_TIOR0 0x05ffff05 /* char */
80#define ITU_TIER0 0x05ffff06 /* char */
81#define ITU_TSR0 0x05ffff07 /* char */
82#define ITU_TCNT0 0x05ffff08 /* short */
83#define ITU_GRA0 0x05ffff0a /* short */
84#define ITU_GRB0 0x05ffff0c /* short */
85
86 /*ITU CHANNEL 1*/
87#define ITU_TCR1 0x05ffff0E /* char */
88#define ITU_TIOR1 0x05ffff0F /* char */
89#define ITU_TIER1 0x05ffff10 /* char */
90#define ITU_TSR1 0x05ffff11 /* char */
91#define ITU_TCNT1 0x05ffff12 /* short */
92#define ITU_GRA1 0x05ffff14 /* short */
93#define ITU_GRB1 0x05ffff16 /* short */
94
95
96 /*ITU CHANNEL 2*/
97#define ITU_TCR2 0x05ffff18 /* char */
98#define ITU_TIOR2 0x05ffff19 /* char */
99#define ITU_TIER2 0x05ffff1A /* char */
100#define ITU_TSR2 0x05ffff1B /* char */
101#define ITU_TCNT2 0x05ffff1C /* short */
102#define ITU_GRA2 0x05ffff1E /* short */
103#define ITU_GRB2 0x05ffff20 /* short */
104
105 /*ITU CHANNEL 3*/
106#define ITU_TCR3 0x05ffff22 /* char */
107#define ITU_TIOR3 0x05ffff23 /* char */
108#define ITU_TIER3 0x05ffff24 /* char */
109#define ITU_TSR3 0x05ffff25 /* char */
110#define ITU_TCNT3 0x05ffff26 /* short */
111#define ITU_GRA3 0x05ffff28 /* short */
112#define ITU_GRB3 0x05ffff2A /* short */
113#define ITU_BRA3 0x05ffff2C /* short */
114#define ITU_BRB3 0x05ffff2E /* short */
115
116 /*ITU CHANNELS 0-4 SHARED*/
117#define ITU_TOCR 0x05ffff31 /* char */
118
119 /*ITU CHANNEL 4*/
120#define ITU_TCR4 0x05ffff32 /* char */
121#define ITU_TIOR4 0x05ffff33 /* char */
122#define ITU_TIER4 0x05ffff34 /* char */
123#define ITU_TSR4 0x05ffff35 /* char */
124#define ITU_TCNT4 0x05ffff36 /* short */
125#define ITU_GRA4 0x05ffff38 /* short */
126#define ITU_GRB4 0x05ffff3A /* short */
127#define ITU_BRA4 0x05ffff3C /* short */
128#define ITU_BRB4 0x05ffff3E /* short */
129
130 /*DMAC CHANNELS 0-3 SHARED*/
131#define DMAOR 0x05ffff48 /* short */
132
133 /*DMAC CHANNEL 0*/
134#define DMA_SAR0 0x05ffff40 /* long */
135#define DMA_DAR0 0x05ffff44 /* long */
136#define DMA_TCR0 0x05ffff4a /* short */
137#define DMA_CHCR0 0x05ffff4e /* short */
138
139 /*DMAC CHANNEL 1*/
140#define DMA_SAR1 0x05ffff50 /* long */
141#define DMA_DAR1 0x05ffff54 /* long */
142#define DMA_TCR1 0x05fffF5a /* short */
143#define DMA_CHCR1 0x05ffff5e /* short */
144
145 /*DMAC CHANNEL 3*/
146#define DMA_SAR3 0x05ffff60 /* long */
147#define DMA_DAR3 0x05ffff64 /* long */
148#define DMA_TCR3 0x05fffF6a /* short */
149#define DMA_CHCR3 0x05ffff6e /* short */
150
151/*DMAC CHANNEL 4*/
152#define DMA_SAR4 0x05ffff70 /* long */
153#define DMA_DAR4 0x05ffff74 /* long */
154#define DMA_TCR4 0x05fffF7a /* short */
155#define DMA_CHCR4 0x05ffff7e /* short */
156
157/*INTC*/
158#define INTC_IPRA 0x05ffff84 /* short */
159#define INTC_IPRB 0x05ffff86 /* short */
160#define INTC_IPRC 0x05ffff88 /* short */
161#define INTC_IPRD 0x05ffff8A /* short */
162#define INTC_IPRE 0x05ffff8C /* short */
163#define INTC_ICR 0x05ffff8E /* short */
164
165/*UBC*/
166#define UBC_BARH 0x05ffff90 /* short */
167#define UBC_BARL 0x05ffff92 /* short */
168#define UBC_BAMRH 0x05ffff94 /* short */
169#define UBC_BAMRL 0x05ffff96 /* short */
170#define UBC_BBR 0x05ffff98 /* short */
171
172/*BSC*/
173#define BSC_BCR 0x05ffffA0 /* short */
174#define BSC_WCR1 0x05ffffA2 /* short */
175#define BSC_WCR2 0x05ffffA4 /* short */
176#define BSC_WCR3 0x05ffffA6 /* short */
177#define BSC_DCR 0x05ffffA8 /* short */
178#define BSC_PCR 0x05ffffAA /* short */
179#define BSC_RCR 0x05ffffAC /* short */
180#define BSC_RTCSR 0x05ffffAE /* short */
181#define BSC_RTCNT 0x05ffffB0 /* short */
182#define BSC_RTCOR 0x05ffffB2 /* short */
183
184/*WDT*/
185#define WDT_TCSR 0x05ffffB8 /* char */
186#define WDT_TCNT 0x05ffffB9 /* char */
187#define WDT_RSTCSR 0x05ffffBB /* char */
188
189/*POWER DOWN STATE*/
190#define PDT_SBYCR 0x05ffffBC /* char */
191
192/*PORT A*/
193#define PADR 0x05ffffC0 /* short */
194
195/*PORT B*/
196#define PBDR 0x05ffffC2 /* short */
197
198 /*PORT C*/
199#define PCDR 0x05ffffD0 /* short */
200
201/*PFC*/
202#define PFC_PAIOR 0x05ffffC4 /* short */
203#define PFC_PBIOR 0x05ffffC6 /* short */
204#define PFC_PACR1 0x05ffffC8 /* short */
205#define PFC_PACR2 0x05ffffCA /* short */
206#define PFC_PBCR1 0x05ffffCC /* short */
207#define PFC_PBCR2 0x05ffffCE /* short */
208#define PFC_CASCR 0x05ffffEE /* short */
209
210/*TPC*/
211#define TPC_TPMR 0x05ffffF0 /* short */
212#define TPC_TPCR 0x05ffffF1 /* short */
213#define TPC_NDERH 0x05ffffF2 /* short */
214#define TPC_NDERL 0x05ffffF3 /* short */
215#define TPC_NDRB 0x05ffffF4 /* char */
216#define TPC_NDRA 0x05ffffF5 /* char */
217#define TPC_NDRB1 0x05ffffF6 /* char */
218#define TPC_NDRA1 0x05ffffF7 /* char */
219
220#endif
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