MISC0 - Miscellaneous Register 0
#define	XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U)
#define	XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U)
#define	XTALOSC24M_MISC0_REFTOP_PWD(x)
#define	XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
#define	XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
#define	XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x)
#define	XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U)
#define	XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U)
#define	XTALOSC24M_MISC0_REFTOP_VBGADJ(x)
#define	XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U)
#define	XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U)
#define	XTALOSC24M_MISC0_REFTOP_VBGUP(x)
#define	XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
#define	XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
#define	XTALOSC24M_MISC0_STOP_MODE_CONFIG(x)
#define	XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
#define	XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
#define	XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x)
#define	XTALOSC24M_MISC0_OSC_I_MASK (0x6000U)
#define	XTALOSC24M_MISC0_OSC_I_SHIFT (13U)
#define	XTALOSC24M_MISC0_OSC_I(x)
#define	XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U)
#define	XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U)
#define	XTALOSC24M_MISC0_OSC_XTALOK(x)
#define	XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
#define	XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U)
#define	XTALOSC24M_MISC0_OSC_XTALOK_EN(x)
#define	XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
#define	XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U)
#define	XTALOSC24M_MISC0_CLKGATE_CTRL(x)
#define	XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
#define	XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U)
#define	XTALOSC24M_MISC0_CLKGATE_DELAY(x)
#define	XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define	XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
#define	XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x)
#define	XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
#define	XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U)
#define	XTALOSC24M_MISC0_XTAL_24M_PWD(x)
#define	XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
#define	XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U)
#define	XTALOSC24M_MISC0_VID_PLL_PREDIV(x)

MISC0_SET - Miscellaneous Register 0
#define	XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U)
#define	XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U)
#define	XTALOSC24M_MISC0_SET_REFTOP_PWD(x)
#define	XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
#define	XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
#define	XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x)
#define	XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
#define	XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
#define	XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x)
#define	XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
#define	XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
#define	XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x)
#define	XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
#define	XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
#define	XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x)
#define	XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
#define	XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
#define	XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x)
#define	XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U)
#define	XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U)
#define	XTALOSC24M_MISC0_SET_OSC_I(x)
#define	XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
#define	XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U)
#define	XTALOSC24M_MISC0_SET_OSC_XTALOK(x)
#define	XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
#define	XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
#define	XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x)
#define	XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
#define	XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
#define	XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x)
#define	XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
#define	XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
#define	XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x)
#define	XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define	XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
#define	XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x)
#define	XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
#define	XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
#define	XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x)
#define	XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
#define	XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
#define	XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x)

MISC0_CLR - Miscellaneous Register 0
#define	XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
#define	XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
#define	XTALOSC24M_MISC0_CLR_REFTOP_PWD(x)
#define	XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
#define	XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
#define	XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x)
#define	XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
#define	XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
#define	XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x)
#define	XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
#define	XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
#define	XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x)
#define	XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
#define	XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
#define	XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x)
#define	XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
#define	XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
#define	XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x)
#define	XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U)
#define	XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U)
#define	XTALOSC24M_MISC0_CLR_OSC_I(x)
#define	XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
#define	XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
#define	XTALOSC24M_MISC0_CLR_OSC_XTALOK(x)
#define	XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
#define	XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
#define	XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x)
#define	XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
#define	XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
#define	XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x)
#define	XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
#define	XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
#define	XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x)
#define	XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define	XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
#define	XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x)
#define	XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
#define	XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
#define	XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x)
#define	XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
#define	XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
#define	XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x)

MISC0_TOG - Miscellaneous Register 0
#define	XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
#define	XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
#define	XTALOSC24M_MISC0_TOG_REFTOP_PWD(x)
#define	XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
#define	XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
#define	XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x)
#define	XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
#define	XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
#define	XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x)
#define	XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
#define	XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
#define	XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x)
#define	XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
#define	XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
#define	XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x)
#define	XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
#define	XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
#define	XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x)
#define	XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U)
#define	XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U)
#define	XTALOSC24M_MISC0_TOG_OSC_I(x)
#define	XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
#define	XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
#define	XTALOSC24M_MISC0_TOG_OSC_XTALOK(x)
#define	XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
#define	XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
#define	XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x)
#define	XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
#define	XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
#define	XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x)
#define	XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
#define	XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
#define	XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x)
#define	XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define	XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
#define	XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x)
#define	XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
#define	XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
#define	XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x)
#define	XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
#define	XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
#define	XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x)

LOWPWR_CTRL - XTAL OSC (LP) Control Register
#define	XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U)
#define	XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U)
#define	XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x)
#define	XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U)
#define	XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U)
#define	XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x)
#define	XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U)
#define	XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U)
#define	XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x)
#define	XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U)
#define	XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U)
#define	XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x)
#define	XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U)
#define	XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U)
#define	XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x)
#define	XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U)
#define	XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U)
#define	XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U)
#define	XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U)
#define	XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U)
#define	XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U)
#define	XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U)
#define	XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U)
#define	XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U)
#define	XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U)
#define	XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x)
#define	XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
#define	XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)
#define	XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x)
#define	XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)
#define	XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)
#define	XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x)
#define	XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U)
#define	XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)
#define	XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U)
#define	XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U)
#define	XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x)

LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register
#define	XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x)
#define	XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x)
#define	XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x)
#define	XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x)
#define	XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x)
#define	XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x)
#define	XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x)
#define	XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x)
#define	XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U)
#define	XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x)

LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register
#define	XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U)
#define	XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x)

LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register
#define	XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U)
#define	XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x)

OSC_CONFIG0 - XTAL OSC Configuration 0 Register
#define	XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U)
#define	XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U)
#define	XTALOSC24M_OSC_CONFIG0_START(x)
#define	XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U)
#define	XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U)
#define	XTALOSC24M_OSC_CONFIG0_ENABLE(x)
#define	XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U)
#define	XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U)
#define	XTALOSC24M_OSC_CONFIG0_BYPASS(x)
#define	XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U)
#define	XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U)
#define	XTALOSC24M_OSC_CONFIG0_INVERT(x)
#define	XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U)
#define	XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U)
#define	XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x)
#define	XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U)
#define	XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U)
#define	XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x)
#define	XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U)
#define	XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U)
#define	XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x)
#define	XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U)
#define	XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U)
#define	XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x)

OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register
#define	XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U)
#define	XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U)
#define	XTALOSC24M_OSC_CONFIG0_SET_START(x)
#define	XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U)
#define	XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U)
#define	XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x)
#define	XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U)
#define	XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U)
#define	XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x)
#define	XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U)
#define	XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U)
#define	XTALOSC24M_OSC_CONFIG0_SET_INVERT(x)
#define	XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U)
#define	XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U)
#define	XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x)
#define	XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U)
#define	XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U)
#define	XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x)
#define	XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U)
#define	XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U)
#define	XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x)
#define	XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U)
#define	XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U)
#define	XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x)

OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register
#define	XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_START(x)
#define	XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x)
#define	XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x)
#define	XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x)
#define	XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x)
#define	XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x)
#define	XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x)
#define	XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U)
#define	XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x)

OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register
#define	XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_START(x)
#define	XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x)
#define	XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x)
#define	XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x)
#define	XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x)
#define	XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x)
#define	XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x)
#define	XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U)
#define	XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x)

OSC_CONFIG1 - XTAL OSC Configuration 1 Register
#define	XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU)
#define	XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U)
#define	XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x)
#define	XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U)
#define	XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U)
#define	XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x)

OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register
#define	XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU)
#define	XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U)
#define	XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x)
#define	XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U)
#define	XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U)
#define	XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x)

OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register
#define	XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU)
#define	XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U)
#define	XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x)
#define	XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U)
#define	XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U)
#define	XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x)

OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register
#define	XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU)
#define	XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U)
#define	XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x)
#define	XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U)
#define	XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U)
#define	XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x)

OSC_CONFIG2 - XTAL OSC Configuration 2 Register
#define	XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU)
#define	XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U)
#define	XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x)
#define	XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U)
#define	XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U)
#define	XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x)
#define	XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U)
#define	XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U)
#define	XTALOSC24M_OSC_CONFIG2_MUX_1M(x)
#define	XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U)
#define	XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U)
#define	XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x)

OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register
#define	XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU)
#define	XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U)
#define	XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x)
#define	XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U)
#define	XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U)
#define	XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x)
#define	XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U)
#define	XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U)
#define	XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x)
#define	XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U)
#define	XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U)
#define	XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x)

OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register
#define	XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU)
#define	XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U)
#define	XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x)
#define	XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U)
#define	XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U)
#define	XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x)
#define	XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U)
#define	XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U)
#define	XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x)
#define	XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U)
#define	XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U)
#define	XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x)

OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register
#define	XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU)
#define	XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U)
#define	XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x)
#define	XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U)
#define	XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U)
#define	XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x)
#define	XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U)
#define	XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U)
#define	XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x)
#define	XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U)
#define	XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U)
#define	XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x)

Detailed Description

Macro Definition Documentation

◆ XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL

#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)

LPBG_SEL 0b0..Normal power bandgap 0b1..Low power bandgap

◆ XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST

#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL

#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)

OSC_SEL 0b0..XTAL OSC 0b1..RC OSC

◆ XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN

#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)

RC_OSC_EN 0b0..Use XTAL OSC to source the 24MHz clock 0b1..Use RC OSC

◆ XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE

#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF

#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY

#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)

XTALOSC_PWRUP_DELAY 0b00..0.25ms 0b01..0.5ms 0b10..1ms 0b11..2ms

◆ XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT

#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)

XTALOSC_PWRUP_STAT 0b0..Not stable 0b1..Stable and ready to use

◆ XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_LPBG_SEL

#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)

LPBG_SEL 0b0..Normal power bandgap 0b1..Low power bandgap

◆ XTALOSC24M_LOWPWR_CTRL_LPBG_TEST

#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_OSC_SEL

#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)

OSC_SEL 0b0..XTAL OSC 0b1..RC OSC

◆ XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN

#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)

RC_OSC_EN 0b0..Use XTAL OSC to source the 24MHz clock 0b1..Use RC OSC

◆ XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE

#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF

#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL

#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)

LPBG_SEL 0b0..Normal power bandgap 0b1..Low power bandgap

◆ XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST

#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL

#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)

OSC_SEL 0b0..XTAL OSC 0b1..RC OSC

◆ XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN

#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)

RC_OSC_EN 0b0..Use XTAL OSC to source the 24MHz clock 0b1..Use RC OSC

◆ XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE

#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF

#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY

#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)

XTALOSC_PWRUP_DELAY 0b00..0.25ms 0b01..0.5ms 0b10..1ms 0b11..2ms

◆ XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT

#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)

XTALOSC_PWRUP_STAT 0b0..Not stable 0b1..Stable and ready to use

◆ XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL

#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)

LPBG_SEL 0b0..Normal power bandgap 0b1..Low power bandgap

◆ XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST

#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE

#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL

#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)

OSC_SEL 0b0..XTAL OSC 0b1..RC OSC

◆ XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN

#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)

RC_OSC_EN 0b0..Use XTAL OSC to source the 24MHz clock 0b1..Use RC OSC

◆ XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE

#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF

#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK)

◆ XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY

#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)

XTALOSC_PWRUP_DELAY 0b00..0.25ms 0b01..0.5ms 0b10..1ms 0b11..2ms

◆ XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT

#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)

XTALOSC_PWRUP_STAT 0b0..Not stable 0b1..Stable and ready to use

◆ XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY

#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)

XTALOSC_PWRUP_DELAY 0b00..0.25ms 0b01..0.5ms 0b10..1ms 0b11..2ms

◆ XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT

#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)

XTALOSC_PWRUP_STAT 0b0..Not stable 0b1..Stable and ready to use

◆ XTALOSC24M_MISC0_CLKGATE_CTRL

#define XTALOSC24M_MISC0_CLKGATE_CTRL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ XTALOSC24M_MISC0_CLKGATE_DELAY

#define XTALOSC24M_MISC0_CLKGATE_DELAY ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ XTALOSC24M_MISC0_CLR_CLKGATE_CTRL

#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ XTALOSC24M_MISC0_CLR_CLKGATE_DELAY

#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS

#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ XTALOSC24M_MISC0_CLR_OSC_I

#define XTALOSC24M_MISC0_CLR_OSC_I ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ XTALOSC24M_MISC0_CLR_OSC_XTALOK

#define XTALOSC24M_MISC0_CLR_OSC_XTALOK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)

◆ XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN

#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)

◆ XTALOSC24M_MISC0_CLR_REFTOP_PWD

#define XTALOSC24M_MISC0_CLR_REFTOP_PWD ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)

◆ XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF

#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ

#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ XTALOSC24M_MISC0_CLR_REFTOP_VBGUP

#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)

◆ XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE

#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG

#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.

◆ XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV

#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

◆ XTALOSC24M_MISC0_CLR_XTAL_24M_PWD

#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)

◆ XTALOSC24M_MISC0_DISCON_HIGH_SNVS

#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ XTALOSC24M_MISC0_OSC_I

#define XTALOSC24M_MISC0_OSC_I ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ XTALOSC24M_MISC0_OSC_XTALOK

#define XTALOSC24M_MISC0_OSC_XTALOK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)

◆ XTALOSC24M_MISC0_OSC_XTALOK_EN

#define XTALOSC24M_MISC0_OSC_XTALOK_EN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)

◆ XTALOSC24M_MISC0_REFTOP_PWD

#define XTALOSC24M_MISC0_REFTOP_PWD ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)

◆ XTALOSC24M_MISC0_REFTOP_SELFBIASOFF

#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ XTALOSC24M_MISC0_REFTOP_VBGADJ

#define XTALOSC24M_MISC0_REFTOP_VBGADJ ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ XTALOSC24M_MISC0_REFTOP_VBGUP

#define XTALOSC24M_MISC0_REFTOP_VBGUP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)

◆ XTALOSC24M_MISC0_RTC_XTAL_SOURCE

#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ XTALOSC24M_MISC0_SET_CLKGATE_CTRL

#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ XTALOSC24M_MISC0_SET_CLKGATE_DELAY

#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS

#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ XTALOSC24M_MISC0_SET_OSC_I

#define XTALOSC24M_MISC0_SET_OSC_I ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ XTALOSC24M_MISC0_SET_OSC_XTALOK

#define XTALOSC24M_MISC0_SET_OSC_XTALOK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)

◆ XTALOSC24M_MISC0_SET_OSC_XTALOK_EN

#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)

◆ XTALOSC24M_MISC0_SET_REFTOP_PWD

#define XTALOSC24M_MISC0_SET_REFTOP_PWD ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)

◆ XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF

#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ XTALOSC24M_MISC0_SET_REFTOP_VBGADJ

#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ XTALOSC24M_MISC0_SET_REFTOP_VBGUP

#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)

◆ XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE

#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG

#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.

◆ XTALOSC24M_MISC0_SET_VID_PLL_PREDIV

#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

◆ XTALOSC24M_MISC0_SET_XTAL_24M_PWD

#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)

◆ XTALOSC24M_MISC0_STOP_MODE_CONFIG

#define XTALOSC24M_MISC0_STOP_MODE_CONFIG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.

◆ XTALOSC24M_MISC0_TOG_CLKGATE_CTRL

#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ XTALOSC24M_MISC0_TOG_CLKGATE_DELAY

#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS

#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ XTALOSC24M_MISC0_TOG_OSC_I

#define XTALOSC24M_MISC0_TOG_OSC_I ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ XTALOSC24M_MISC0_TOG_OSC_XTALOK

#define XTALOSC24M_MISC0_TOG_OSC_XTALOK ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)

◆ XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN

#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)

◆ XTALOSC24M_MISC0_TOG_REFTOP_PWD

#define XTALOSC24M_MISC0_TOG_REFTOP_PWD ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)

◆ XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF

#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ

#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ XTALOSC24M_MISC0_TOG_REFTOP_VBGUP

#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)

◆ XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE

#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG

#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.

◆ XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV

#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

◆ XTALOSC24M_MISC0_TOG_XTAL_24M_PWD

#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)

◆ XTALOSC24M_MISC0_VID_PLL_PREDIV

#define XTALOSC24M_MISC0_VID_PLL_PREDIV ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

◆ XTALOSC24M_MISC0_XTAL_24M_PWD

#define XTALOSC24M_MISC0_XTAL_24M_PWD ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)

◆ XTALOSC24M_OSC_CONFIG0_BYPASS

#define XTALOSC24M_OSC_CONFIG0_BYPASS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK)

◆ XTALOSC24M_OSC_CONFIG0_CLR_BYPASS

#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK)

◆ XTALOSC24M_OSC_CONFIG0_CLR_ENABLE

#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK)

◆ XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS

#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)

◆ XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS

#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)

◆ XTALOSC24M_OSC_CONFIG0_CLR_INVERT

#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK)

◆ XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG

#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)

◆ XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR

#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)

◆ XTALOSC24M_OSC_CONFIG0_CLR_START

#define XTALOSC24M_OSC_CONFIG0_CLR_START ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK)

◆ XTALOSC24M_OSC_CONFIG0_ENABLE

#define XTALOSC24M_OSC_CONFIG0_ENABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK)

◆ XTALOSC24M_OSC_CONFIG0_HYST_MINUS

#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)

◆ XTALOSC24M_OSC_CONFIG0_HYST_PLUS

#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)

◆ XTALOSC24M_OSC_CONFIG0_INVERT

#define XTALOSC24M_OSC_CONFIG0_INVERT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK)

◆ XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG

#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)

◆ XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR

#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)

◆ XTALOSC24M_OSC_CONFIG0_SET_BYPASS

#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK)

◆ XTALOSC24M_OSC_CONFIG0_SET_ENABLE

#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK)

◆ XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS

#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)

◆ XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS

#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)

◆ XTALOSC24M_OSC_CONFIG0_SET_INVERT

#define XTALOSC24M_OSC_CONFIG0_SET_INVERT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK)

◆ XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG

#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)

◆ XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR

#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)

◆ XTALOSC24M_OSC_CONFIG0_SET_START

#define XTALOSC24M_OSC_CONFIG0_SET_START ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK)

◆ XTALOSC24M_OSC_CONFIG0_START

#define XTALOSC24M_OSC_CONFIG0_START ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK)

◆ XTALOSC24M_OSC_CONFIG0_TOG_BYPASS

#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK)

◆ XTALOSC24M_OSC_CONFIG0_TOG_ENABLE

#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK)

◆ XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS

#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)

◆ XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS

#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)

◆ XTALOSC24M_OSC_CONFIG0_TOG_INVERT

#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK)

◆ XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG

#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)

◆ XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR

#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)

◆ XTALOSC24M_OSC_CONFIG0_TOG_START

#define XTALOSC24M_OSC_CONFIG0_TOG_START ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK)

◆ XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR

#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)

◆ XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG

#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)

◆ XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR

#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)

◆ XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG

#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)

◆ XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR

#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)

◆ XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG

#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)

◆ XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR

#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)

◆ XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG

#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)

◆ XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL

#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK)

◆ XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL

#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK)

◆ XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG

#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)

◆ XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M

#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK)

◆ XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M

#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK)

◆ XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG

#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)

◆ XTALOSC24M_OSC_CONFIG2_ENABLE_1M

#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)

◆ XTALOSC24M_OSC_CONFIG2_MUX_1M

#define XTALOSC24M_OSC_CONFIG2_MUX_1M ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK)

◆ XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL

#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK)

◆ XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG

#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)

◆ XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M

#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK)

◆ XTALOSC24M_OSC_CONFIG2_SET_MUX_1M

#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK)

◆ XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL

#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK)

◆ XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG

#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)

◆ XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M

#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK)

◆ XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M

#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK)

MISC0 - Miscellaneous Register 0

MISC0_SET - Miscellaneous Register 0

MISC0_CLR - Miscellaneous Register 0

MISC0_TOG - Miscellaneous Register 0

LOWPWR_CTRL - XTAL OSC (LP) Control Register

LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register

LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register

LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register

OSC_CONFIG0 - XTAL OSC Configuration 0 Register

OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register

OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register

OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register

OSC_CONFIG1 - XTAL OSC Configuration 1 Register

OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register

OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register

OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register

OSC_CONFIG2 - XTAL OSC Configuration 2 Register

OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register

OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register

OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register

Detailed Description

Macro Definition Documentation

◆ XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL

◆ XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST

◆ XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL

◆ XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN

◆ XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE

◆ XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF

◆ XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY

◆ XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT

◆ XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_LPBG_SEL

◆ XTALOSC24M_LOWPWR_CTRL_LPBG_TEST

◆ XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_OSC_SEL

◆ XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN

◆ XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE

◆ XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF

◆ XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL

◆ XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST

◆ XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL

◆ XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN

◆ XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE

◆ XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF

◆ XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY

◆ XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT

◆ XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL

◆ XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST

◆ XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE

◆ XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL

◆ XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN

◆ XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE

◆ XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF

◆ XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY

◆ XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT

◆ XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY

◆ XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT

◆ XTALOSC24M_MISC0_CLKGATE_CTRL

◆ XTALOSC24M_MISC0_CLKGATE_DELAY