![]() |
RTEMS 6.3
|
This group contains register bit definitions. More...
Macros | |
| #define | GRSPWROUTER_PCTRL2_SM_SHIFT 24 |
| #define | GRSPWROUTER_PCTRL2_SM_MASK 0xff000000U |
| #define | GRSPWROUTER_PCTRL2_SM_GET(_reg) |
| #define | GRSPWROUTER_PCTRL2_SM_SET(_reg, _val) |
| #define | GRSPWROUTER_PCTRL2_SM(_val) |
| #define | GRSPWROUTER_PCTRL2_SV_SHIFT 16 |
| #define | GRSPWROUTER_PCTRL2_SV_MASK 0xff0000U |
| #define | GRSPWROUTER_PCTRL2_SV_GET(_reg) |
| #define | GRSPWROUTER_PCTRL2_SV_SET(_reg, _val) |
| #define | GRSPWROUTER_PCTRL2_SV(_val) |
| #define | GRSPWROUTER_PCTRL2_OR 0x8000U |
| #define | GRSPWROUTER_PCTRL2_UR 0x4000U |
| #define | GRSPWROUTER_PCTRL2_R 0x2000U |
| #define | GRSPWROUTER_PCTRL2_AT 0x1000U |
| #define | GRSPWROUTER_PCTRL2_AR 0x800U |
| #define | GRSPWROUTER_PCTRL2_IT 0x400U |
| #define | GRSPWROUTER_PCTRL2_IR 0x200U |
| #define | GRSPWROUTER_PCTRL2_SD_SHIFT 1 |
| #define | GRSPWROUTER_PCTRL2_SD_MASK 0x3eU |
| #define | GRSPWROUTER_PCTRL2_SD_GET(_reg) |
| #define | GRSPWROUTER_PCTRL2_SD_SET(_reg, _val) |
| #define | GRSPWROUTER_PCTRL2_SD(_val) |
| #define | GRSPWROUTER_PCTRL2_SC 0x1U |
This group contains register bit definitions.
| #define GRSPWROUTER_PCTRL2_SD | ( | _val | ) |
| #define GRSPWROUTER_PCTRL2_SD_GET | ( | _reg | ) |
| #define GRSPWROUTER_PCTRL2_SD_SET | ( | _reg, | |
| _val ) |
| #define GRSPWROUTER_PCTRL2_SM | ( | _val | ) |
| #define GRSPWROUTER_PCTRL2_SM_GET | ( | _reg | ) |
| #define GRSPWROUTER_PCTRL2_SM_SET | ( | _reg, | |
| _val ) |
| #define GRSPWROUTER_PCTRL2_SV | ( | _val | ) |
| #define GRSPWROUTER_PCTRL2_SV_GET | ( | _reg | ) |
| #define GRSPWROUTER_PCTRL2_SV_SET | ( | _reg, | |
| _val ) |