RTEMS 6.3
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Processor n interrupt force register (PIFORCE)

This group contains register bit definitions. More...

Macros

#define IRQAMP_PIFORCE_FC_15_1_SHIFT   17
#define IRQAMP_PIFORCE_FC_15_1_MASK   0xfffe0000U
#define IRQAMP_PIFORCE_FC_15_1_GET(_reg)
#define IRQAMP_PIFORCE_FC_15_1_SET(_reg, _val)
#define IRQAMP_PIFORCE_FC_15_1(_val)
#define IRQAMP_PIFORCE_IF15_1_SHIFT   1
#define IRQAMP_PIFORCE_IF15_1_MASK   0xfffeU
#define IRQAMP_PIFORCE_IF15_1_GET(_reg)
#define IRQAMP_PIFORCE_IF15_1_SET(_reg, _val)
#define IRQAMP_PIFORCE_IF15_1(_val)

Detailed Description

This group contains register bit definitions.

Macro Definition Documentation

◆ IRQAMP_PIFORCE_FC_15_1

#define IRQAMP_PIFORCE_FC_15_1 ( _val)
Value:
( ( ( _val ) << IRQAMP_PIFORCE_FC_15_1_SHIFT ) & \
IRQAMP_PIFORCE_FC_15_1_MASK )

◆ IRQAMP_PIFORCE_FC_15_1_GET

#define IRQAMP_PIFORCE_FC_15_1_GET ( _reg)
Value:
( ( ( _reg ) & IRQAMP_PIFORCE_FC_15_1_MASK ) >> \
IRQAMP_PIFORCE_FC_15_1_SHIFT )

◆ IRQAMP_PIFORCE_FC_15_1_SET

#define IRQAMP_PIFORCE_FC_15_1_SET ( _reg,
_val )
Value:
( ( ( _reg ) & ~IRQAMP_PIFORCE_FC_15_1_MASK ) | \
( ( ( _val ) << IRQAMP_PIFORCE_FC_15_1_SHIFT ) & \
IRQAMP_PIFORCE_FC_15_1_MASK ) )

◆ IRQAMP_PIFORCE_IF15_1

#define IRQAMP_PIFORCE_IF15_1 ( _val)
Value:
( ( ( _val ) << IRQAMP_PIFORCE_IF15_1_SHIFT ) & \
IRQAMP_PIFORCE_IF15_1_MASK )

◆ IRQAMP_PIFORCE_IF15_1_GET

#define IRQAMP_PIFORCE_IF15_1_GET ( _reg)
Value:
( ( ( _reg ) & IRQAMP_PIFORCE_IF15_1_MASK ) >> \
IRQAMP_PIFORCE_IF15_1_SHIFT )

◆ IRQAMP_PIFORCE_IF15_1_SET

#define IRQAMP_PIFORCE_IF15_1_SET ( _reg,
_val )
Value:
( ( ( _reg ) & ~IRQAMP_PIFORCE_IF15_1_MASK ) | \
( ( ( _val ) << IRQAMP_PIFORCE_IF15_1_SHIFT ) & \
IRQAMP_PIFORCE_IF15_1_MASK ) )