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RTEMS 6.3
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This group contains register bit definitions. More...
Macros | |
| #define | GRIOMMU_CTRL_PGSZ_SHIFT 18 |
| #define | GRIOMMU_CTRL_PGSZ_MASK 0x1c0000U |
| #define | GRIOMMU_CTRL_PGSZ_GET(_reg) |
| #define | GRIOMMU_CTRL_PGSZ_SET(_reg, _val) |
| #define | GRIOMMU_CTRL_PGSZ(_val) |
| #define | GRIOMMU_CTRL_LB 0x20000U |
| #define | GRIOMMU_CTRL_SP 0x10000U |
| #define | GRIOMMU_CTRL_ITR_SHIFT 12 |
| #define | GRIOMMU_CTRL_ITR_MASK 0xf000U |
| #define | GRIOMMU_CTRL_ITR_GET(_reg) |
| #define | GRIOMMU_CTRL_ITR_SET(_reg, _val) |
| #define | GRIOMMU_CTRL_ITR(_val) |
| #define | GRIOMMU_CTRL_DP 0x800U |
| #define | GRIOMMU_CTRL_SIV 0x400U |
| #define | GRIOMMU_CTRL_HPROT_SHIFT 8 |
| #define | GRIOMMU_CTRL_HPROT_MASK 0x300U |
| #define | GRIOMMU_CTRL_HPROT_GET(_reg) |
| #define | GRIOMMU_CTRL_HPROT_SET(_reg, _val) |
| #define | GRIOMMU_CTRL_HPROT(_val) |
| #define | GRIOMMU_CTRL_AU 0x80U |
| #define | GRIOMMU_CTRL_WP 0x40U |
| #define | GRIOMMU_CTRL_DM 0x20U |
| #define | GRIOMMU_CTRL_GS 0x10U |
| #define | GRIOMMU_CTRL_CE 0x8U |
| #define | GRIOMMU_CTRL_PM_SHIFT 1 |
| #define | GRIOMMU_CTRL_PM_MASK 0x6U |
| #define | GRIOMMU_CTRL_PM_GET(_reg) |
| #define | GRIOMMU_CTRL_PM_SET(_reg, _val) |
| #define | GRIOMMU_CTRL_PM(_val) |
| #define | GRIOMMU_CTRL_EN 0x1U |
This group contains register bit definitions.
| #define GRIOMMU_CTRL_HPROT | ( | _val | ) |
| #define GRIOMMU_CTRL_HPROT_GET | ( | _reg | ) |
| #define GRIOMMU_CTRL_HPROT_SET | ( | _reg, | |
| _val ) |
| #define GRIOMMU_CTRL_ITR | ( | _val | ) |
| #define GRIOMMU_CTRL_ITR_GET | ( | _reg | ) |
| #define GRIOMMU_CTRL_ITR_SET | ( | _reg, | |
| _val ) |
| #define GRIOMMU_CTRL_PGSZ | ( | _val | ) |
| #define GRIOMMU_CTRL_PGSZ_GET | ( | _reg | ) |
| #define GRIOMMU_CTRL_PGSZ_SET | ( | _reg, | |
| _val ) |
| #define GRIOMMU_CTRL_PM | ( | _val | ) |
| #define GRIOMMU_CTRL_PM_GET | ( | _reg | ) |
| #define GRIOMMU_CTRL_PM_SET | ( | _reg, | |
| _val ) |