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RTEMS 6.3
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This group contains register bit definitions. More...
Macros | |
| #define | GRIOMMU_CAP1_CADDR_SHIFT 20 |
| #define | GRIOMMU_CAP1_CADDR_MASK 0xfff00000U |
| #define | GRIOMMU_CAP1_CADDR_GET(_reg) |
| #define | GRIOMMU_CAP1_CADDR_SET(_reg, _val) |
| #define | GRIOMMU_CAP1_CADDR(_val) |
| #define | GRIOMMU_CAP1_CMASK_SHIFT 16 |
| #define | GRIOMMU_CAP1_CMASK_MASK 0xf0000U |
| #define | GRIOMMU_CAP1_CMASK_GET(_reg) |
| #define | GRIOMMU_CAP1_CMASK_SET(_reg, _val) |
| #define | GRIOMMU_CAP1_CMASK(_val) |
| #define | GRIOMMU_CAP1_CTAGBITS_SHIFT 8 |
| #define | GRIOMMU_CAP1_CTAGBITS_MASK 0xff00U |
| #define | GRIOMMU_CAP1_CTAGBITS_GET(_reg) |
| #define | GRIOMMU_CAP1_CTAGBITS_SET(_reg, _val) |
| #define | GRIOMMU_CAP1_CTAGBITS(_val) |
| #define | GRIOMMU_CAP1_CISIZE_SHIFT 5 |
| #define | GRIOMMU_CAP1_CISIZE_MASK 0xe0U |
| #define | GRIOMMU_CAP1_CISIZE_GET(_reg) |
| #define | GRIOMMU_CAP1_CISIZE_SET(_reg, _val) |
| #define | GRIOMMU_CAP1_CISIZE(_val) |
| #define | GRIOMMU_CAP1_CLINES_SHIFT 0 |
| #define | GRIOMMU_CAP1_CLINES_MASK 0x1fU |
| #define | GRIOMMU_CAP1_CLINES_GET(_reg) |
| #define | GRIOMMU_CAP1_CLINES_SET(_reg, _val) |
| #define | GRIOMMU_CAP1_CLINES(_val) |
This group contains register bit definitions.
| #define GRIOMMU_CAP1_CADDR | ( | _val | ) |
| #define GRIOMMU_CAP1_CADDR_GET | ( | _reg | ) |
| #define GRIOMMU_CAP1_CADDR_SET | ( | _reg, | |
| _val ) |
| #define GRIOMMU_CAP1_CISIZE | ( | _val | ) |
| #define GRIOMMU_CAP1_CISIZE_GET | ( | _reg | ) |
| #define GRIOMMU_CAP1_CISIZE_SET | ( | _reg, | |
| _val ) |
| #define GRIOMMU_CAP1_CLINES | ( | _val | ) |
| #define GRIOMMU_CAP1_CLINES_GET | ( | _reg | ) |
| #define GRIOMMU_CAP1_CLINES_SET | ( | _reg, | |
| _val ) |
| #define GRIOMMU_CAP1_CMASK | ( | _val | ) |
| #define GRIOMMU_CAP1_CMASK_GET | ( | _reg | ) |
| #define GRIOMMU_CAP1_CMASK_SET | ( | _reg, | |
| _val ) |
| #define GRIOMMU_CAP1_CTAGBITS | ( | _val | ) |
| #define GRIOMMU_CAP1_CTAGBITS_GET | ( | _reg | ) |
| #define GRIOMMU_CAP1_CTAGBITS_SET | ( | _reg, | |
| _val ) |