RTEMS 6.3
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Macros
RCC Private macros to check input parameters
STM32H7xx_HAL_Driver | Board Support Packages » ARM » STM32H7 » RCC » RCC Private Macros | Board Support Packages » ARM » STM32H7

Macros

#define IS_RCC_OSCILLATORTYPE(OSCILLATOR)
#define IS_RCC_HSE(HSE)
#define IS_RCC_LSE(LSE)
#define IS_RCC_HSI(HSI)
#define IS_RCC_HSI48(HSI48)
#define IS_RCC_LSI(LSI)
#define IS_RCC_CSI(CSI)
#define IS_RCC_PLL(PLL)
#define IS_RCC_PLLSOURCE(SOURCE)
#define IS_RCC_PLLRGE_VALUE(VALUE)
#define IS_RCC_PLLVCO_VALUE(VALUE)
#define IS_RCC_PLLFRACN_VALUE(VALUE)
#define IS_RCC_PLLM_VALUE(VALUE)
#define IS_RCC_PLLN_VALUE(VALUE)
#define IS_RCC_PLLP_VALUE(VALUE)
#define IS_RCC_PLLQ_VALUE(VALUE)
#define IS_RCC_PLLR_VALUE(VALUE)
#define IS_RCC_PLLCLOCKOUT_VALUE(VALUE)
#define IS_RCC_CLOCKTYPE(CLK)
#define IS_RCC_SYSCLKSOURCE(SOURCE)
#define IS_RCC_SYSCLK(SYSCLK)
#define IS_RCC_HCLK(HCLK)
#define IS_RCC_CDPCLK1(CDPCLK1)
#define IS_RCC_D1PCLK1   IS_RCC_CDPCLK1
#define IS_RCC_PCLK1(PCLK1)
#define IS_RCC_PCLK2(PCLK2)
#define IS_RCC_SRDPCLK1(SRDPCLK1)
#define IS_RCC_D3PCLK1   IS_RCC_SRDPCLK1
#define IS_RCC_RTCCLKSOURCE(SOURCE)
#define IS_RCC_MCO(MCOx)
#define IS_RCC_MCO1SOURCE(SOURCE)
#define IS_RCC_MCO2SOURCE(SOURCE)
#define IS_RCC_MCODIV(DIV)
#define IS_RCC_FLAG(FLAG)
#define IS_RCC_HSICALIBRATION_VALUE(VALUE)
#define IS_RCC_CSICALIBRATION_VALUE(VALUE)
#define IS_RCC_STOP_WAKEUPCLOCK(SOURCE)
#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE)

Detailed Description

Macro Definition Documentation

◆ IS_RCC_CDPCLK1

#define IS_RCC_CDPCLK1 ( CDPCLK1)
Value:
(((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \
((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \
((CDPCLK1) == RCC_APB3_DIV16))

◆ IS_RCC_CLOCKTYPE

#define IS_RCC_CLOCKTYPE ( CLK)
Value:
((1U <= (CLK)) && ((CLK) <= 0x3FU))

◆ IS_RCC_CSI

#define IS_RCC_CSI ( CSI)
Value:
(((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
CSI
#define CSI
Definition MIMXRT1052.h:11297

◆ IS_RCC_CSICALIBRATION_VALUE

#define IS_RCC_CSICALIBRATION_VALUE ( VALUE)
Value:
((VALUE) <= 0x3FU)

◆ IS_RCC_FLAG

#define IS_RCC_FLAG ( FLAG)
Value:
(((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \
((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_CPUCKRDY) || ((FLAG) == RCC_FLAG_CDCKRDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \
((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || \
((FLAG) == RCC_FLAG_CDRST) || ((FLAG) == RCC_FLAG_BORRST) || \
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV ))

◆ IS_RCC_HCLK

#define IS_RCC_HCLK ( HCLK)
Value:
(((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || \
((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || \
((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || \
((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \
((HCLK) == RCC_HCLK_DIV512))

◆ IS_RCC_HSE

#define IS_RCC_HSE ( HSE)
Value:
(((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
((HSE) == RCC_HSE_BYPASS))

◆ IS_RCC_HSI

#define IS_RCC_HSI ( HSI)
Value:
(((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || \
((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \
((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))
RCC_HSI_DIV8
#define RCC_HSI_DIV8
Definition stm32h7xx_hal_rcc.h:215
RCC_HSI_ON
#define RCC_HSI_ON
Definition stm32h7xx_hal_rcc.h:210
RCC_HSI_OFF
#define RCC_HSI_OFF
Definition stm32h7xx_hal_rcc.h:209
RCC_HSI_DIV4
#define RCC_HSI_DIV4
Definition stm32h7xx_hal_rcc.h:214
RCC_HSI_DIV2
#define RCC_HSI_DIV2
Definition stm32h7xx_hal_rcc.h:213
RCC_HSI_DIV1
#define RCC_HSI_DIV1
Definition stm32h7xx_hal_rcc.h:212

◆ IS_RCC_HSI48

#define IS_RCC_HSI48 ( HSI48)
Value:
(((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))

◆ IS_RCC_HSICALIBRATION_VALUE

#define IS_RCC_HSICALIBRATION_VALUE ( VALUE)
Value:
((VALUE) <= 0x7FU)

◆ IS_RCC_LSE

#define IS_RCC_LSE ( LSE)
Value:
(((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
((LSE) == RCC_LSE_BYPASS))

◆ IS_RCC_LSI

#define IS_RCC_LSI ( LSI)
Value:
(((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))

◆ IS_RCC_MCO

#define IS_RCC_MCO ( MCOx)
Value:
(((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))

◆ IS_RCC_MCO1SOURCE

#define IS_RCC_MCO1SOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK) || \
((SOURCE) == RCC_MCO1SOURCE_HSI48))

◆ IS_RCC_MCO2SOURCE

#define IS_RCC_MCO2SOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \
((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK) || \
((SOURCE) == RCC_MCO2SOURCE_CSICLK) || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))

◆ IS_RCC_MCODIV

#define IS_RCC_MCODIV ( DIV)
Value:
(((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \
((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \
((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \
((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \
((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \
((DIV) == RCC_MCODIV_15))

◆ IS_RCC_OSCILLATORTYPE

#define IS_RCC_OSCILLATORTYPE ( OSCILLATOR)
Value:
(((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))

◆ IS_RCC_PCLK1

#define IS_RCC_PCLK1 ( PCLK1)
Value:
(((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \
((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \
((PCLK1) == RCC_APB1_DIV16))

◆ IS_RCC_PCLK2

#define IS_RCC_PCLK2 ( PCLK2)
Value:
(((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \
((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \
((PCLK2) == RCC_APB2_DIV16))

◆ IS_RCC_PLL

#define IS_RCC_PLL ( PLL)
Value:
(((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
((PLL) == RCC_PLL_ON))

◆ IS_RCC_PLLCLOCKOUT_VALUE

#define IS_RCC_PLLCLOCKOUT_VALUE ( VALUE)
Value:
(((VALUE) == RCC_PLL1_DIVP) || \
((VALUE) == RCC_PLL1_DIVQ) || \
((VALUE) == RCC_PLL1_DIVR))

◆ IS_RCC_PLLFRACN_VALUE

#define IS_RCC_PLLFRACN_VALUE ( VALUE)
Value:
((VALUE) <= 8191U)

◆ IS_RCC_PLLM_VALUE

#define IS_RCC_PLLM_VALUE ( VALUE)
Value:
((1U <= (VALUE)) && ((VALUE) <= 63U))

◆ IS_RCC_PLLN_VALUE

#define IS_RCC_PLLN_VALUE ( VALUE)
Value:
((4U <= (VALUE)) && ((VALUE) <= 512U))

◆ IS_RCC_PLLP_VALUE

#define IS_RCC_PLLP_VALUE ( VALUE)
Value:
((1U <= (VALUE)) && ((VALUE) <= 128U))

◆ IS_RCC_PLLQ_VALUE

#define IS_RCC_PLLQ_VALUE ( VALUE)
Value:
((1U <= (VALUE)) && ((VALUE) <= 128U))

◆ IS_RCC_PLLR_VALUE

#define IS_RCC_PLLR_VALUE ( VALUE)
Value:
((1U <= (VALUE)) && ((VALUE) <= 128U))

◆ IS_RCC_PLLRGE_VALUE

#define IS_RCC_PLLRGE_VALUE ( VALUE)
Value:
(((VALUE) == RCC_PLL1VCIRANGE_0) || \
((VALUE) == RCC_PLL1VCIRANGE_1) || \
((VALUE) == RCC_PLL1VCIRANGE_2) || \
((VALUE) == RCC_PLL1VCIRANGE_3))
RCC_PLL1VCIRANGE_1
#define RCC_PLL1VCIRANGE_1
Definition stm32h7xx_hal_rcc.h:301
RCC_PLL1VCIRANGE_2
#define RCC_PLL1VCIRANGE_2
Definition stm32h7xx_hal_rcc.h:302
RCC_PLL1VCIRANGE_3
#define RCC_PLL1VCIRANGE_3
Definition stm32h7xx_hal_rcc.h:303
RCC_PLL1VCIRANGE_0
#define RCC_PLL1VCIRANGE_0
Definition stm32h7xx_hal_rcc.h:300

◆ IS_RCC_PLLSOURCE

#define IS_RCC_PLLSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_PLLSOURCE_CSI) || \
((SOURCE) == RCC_PLLSOURCE_HSI) || \
((SOURCE) == RCC_PLLSOURCE_NONE) || \
((SOURCE) == RCC_PLLSOURCE_HSE))

◆ IS_RCC_PLLVCO_VALUE

#define IS_RCC_PLLVCO_VALUE ( VALUE)
Value:
(((VALUE) == RCC_PLL1VCOWIDE) || ((VALUE) == RCC_PLL1VCOMEDIUM))

◆ IS_RCC_SRDPCLK1

#define IS_RCC_SRDPCLK1 ( SRDPCLK1)
Value:
(((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \
((SRDPCLK1) == RCC_APB4_DIV4) || ((SRDPCLK1) == RCC_APB4_DIV8) || \
((SRDPCLK1) == RCC_APB4_DIV16))

◆ IS_RCC_STOP_KERWAKEUPCLOCK

#define IS_RCC_STOP_KERWAKEUPCLOCK ( SOURCE)
Value:
(((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \
((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))

◆ IS_RCC_STOP_WAKEUPCLOCK

#define IS_RCC_STOP_WAKEUPCLOCK ( SOURCE)
Value:
(((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \
((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))

◆ IS_RCC_SYSCLK

#define IS_RCC_SYSCLK ( SYSCLK)
Value:
(((SYSCLK) == RCC_SYSCLK_DIV1) || ((SYSCLK) == RCC_SYSCLK_DIV2) || \
((SYSCLK) == RCC_SYSCLK_DIV4) || ((SYSCLK) == RCC_SYSCLK_DIV8) || \
((SYSCLK) == RCC_SYSCLK_DIV16) || ((SYSCLK) == RCC_SYSCLK_DIV64) || \
((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \
((SYSCLK) == RCC_SYSCLK_DIV512))

◆ IS_RCC_SYSCLKSOURCE

#define IS_RCC_SYSCLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \
((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
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