RTEMS 6.3
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Macros

#define RCC_SPI6CLKSOURCE_SRDPCLK4   (0x00000000U)
#define RCC_SPI6CLKSOURCE_D3PCLK1   RCC_SPI6CLKSOURCE_SRDPCLK4
#define RCC_SPI6CLKSOURCE_PCLK4   RCC_SPI6CLKSOURCE_SRDPCLK4
#define RCC_SPI6CLKSOURCE_PLL2   RCC_SRDCCIPR_SPI6SEL_0
#define RCC_SPI6CLKSOURCE_PLL3   RCC_SRDCCIPR_SPI6SEL_1
#define RCC_SPI6CLKSOURCE_HSI   (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
#define RCC_SPI6CLKSOURCE_CSI   RCC_SRDCCIPR_SPI6SEL_2
#define RCC_SPI6CLKSOURCE_HSE   (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
#define RCC_SPI6CLKSOURCE_PIN   (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)

Detailed Description