MT25TL01G_Exported_Constants

Macros
#define	MT25TL01G_FLASH_SIZE   0x8000000
	MT25TL01G Configuration.
#define	MT25TL01G_SECTOR_SIZE   0x10000
#define	MT25TL01G_SUBSECTOR_SIZE   0x1000
#define	MT25TL01G_PAGE_SIZE   0x100
#define	MT25TL01G_DIE_ERASE_MAX_TIME   460000
#define	MT25TL01G_SECTOR_ERASE_MAX_TIME   1000
#define	MT25TL01G_SUBSECTOR_ERASE_MAX_TIME   400
#define	MT25TL01G_RESET_ENABLE_CMD   0x66
	MT25TL01G Commands.
#define	MT25TL01G_RESET_MEMORY_CMD   0x99
#define	MT25TL01G_READ_ID_CMD   0x9E
#define	MT25TL01G_READ_ID_CMD2   0x9F
#define	MT25TL01G_MULTIPLE_IO_READ_ID_CMD   0xAF
#define	MT25TL01G_READ_SERIAL_FLASH_DISCO_PARAM_CMD   0x5A
#define	MT25TL01G_READ_CMD   0x03
#define	MT25TL01G_READ_4_BYTE_ADDR_CMD   0x13
#define	MT25TL01G_FAST_READ_CMD   0x0B
#define	MT25TL01G_FAST_READ_DTR_CMD   0x0D
#define	MT25TL01G_FAST_READ_4_BYTE_ADDR_CMD   0x0C
#define	MT25TL01G_FAST_READ_4_BYTE_DTR_CMD   0x0E
#define	MT25TL01G_DUAL_OUT_FAST_READ_CMD   0x3B
#define	MT25TL01G_DUAL_OUT_FAST_READ_DTR_CMD   0x3D
#define	MT25TL01G_DUAL_OUT_FAST_READ_4_BYTE_ADDR_CMD   0x3C
#define	MT25TL01G_DUAL_INOUT_FAST_READ_CMD   0xBB
#define	MT25TL01G_DUAL_INOUT_FAST_READ_DTR_CMD   0xBD
#define	MT25TL01G_DUAL_INOUT_FAST_READ_4_BYTE_ADDR_CMD   0xBC
#define	MT25TL01G_QUAD_OUT_FAST_READ_CMD   0x6B
#define	MT25TL01G_QUAD_OUT_FAST_READ_DTR_CMD   0x6D
#define	MT25TL01G_QUAD_OUT_FAST_READ_4_BYTE_ADDR_CMD   0x6C
#define	MT25TL01G_QUAD_INOUT_FAST_READ_CMD   0xEB
#define	MT25TL01G_QUAD_INOUT_FAST_READ_DTR_CMD   0xED
#define	MT25TL01G_QUAD_INOUT_FAST_READ_4_BYTE_ADDR_CMD   0xEC
#define	MT25TL01G_QUAD_INOUT_FAST_READ_4_BYTE_DTR_CMD   0xEE
#define	MT25TL01G_WRITE_ENABLE_CMD   0x06
#define	MT25TL01G_WRITE_DISABLE_CMD   0x04
#define	MT25TL01G_READ_STATUS_REG_CMD   0x05
#define	MT25TL01G_WRITE_STATUS_REG_CMD   0x01
#define	MT25TL01G_READ_LOCK_REG_CMD   0xE8
#define	MT25TL01G_WRITE_LOCK_REG_CMD   0xE5
#define	MT25TL01G_READ_FLAG_STATUS_REG_CMD   0x70
#define	MT25TL01G_CLEAR_FLAG_STATUS_REG_CMD   0x50
#define	MT25TL01G_READ_NONVOL_CFG_REG_CMD   0xB5
#define	MT25TL01G_WRITE_NONVOL_CFG_REG_CMD   0xB1
#define	MT25TL01G_READ_VOL_CFG_REG_CMD   0x85
#define	MT25TL01G_WRITE_VOL_CFG_REG_CMD   0x81
#define	MT25TL01G_READ_ENHANCED_VOL_CFG_REG_CMD   0x65
#define	MT25TL01G_WRITE_ENHANCED_VOL_CFG_REG_CMD   0x61
#define	MT25TL01G_READ_EXT_ADDR_REG_CMD   0xC8
#define	MT25TL01G_WRITE_EXT_ADDR_REG_CMD   0xC5
#define	MT25TL01G_PAGE_PROG_CMD   0x02
#define	MT25TL01G_PAGE_PROG_4_BYTE_ADDR_CMD   0x12
#define	MT25TL01G_DUAL_IN_FAST_PROG_CMD   0xA2
#define	MT25TL01G_EXT_DUAL_IN_FAST_PROG_CMD   0xD2
#define	MT25TL01G_QUAD_IN_FAST_PROG_CMD   0x32
#define	MT25TL01G_EXT_QUAD_IN_FAST_PROG_CMD   0x38
#define	MT25TL01G_QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD   0x34
#define	MT25TL01G_SUBSECTOR_ERASE_CMD_4K   0x20
#define	MT25TL01G_SUBSECTOR_ERASE_4_BYTE_ADDR_CMD_4K   0x21
#define	MT25TL01G_SUBSECTOR_ERASE_CMD_32K   0x52
#define	MT25TL01G_SECTOR_ERASE_CMD   0xD8
#define	MT25TL01G_SECTOR_ERASE_4_BYTE_ADDR_CMD   0xDC
#define	MT25TL01G_DIE_ERASE_CMD   0xC7
#define	MT25TL01G_PROG_ERASE_RESUME_CMD   0x7A
#define	MT25TL01G_PROG_ERASE_SUSPEND_CMD   0x75
#define	MT25TL01G_READ_OTP_ARRAY_CMD   0x4B
#define	MT25TL01G_PROG_OTP_ARRAY_CMD   0x42
#define	MT25TL01G_ENTER_4_BYTE_ADDR_MODE_CMD   0xB7
#define	MT25TL01G_EXIT_4_BYTE_ADDR_MODE_CMD   0xE9
#define	MT25TL01G_ENTER_QUAD_CMD   0x35
#define	MT25TL01G_EXIT_QUAD_CMD   0xF5
#define	MT25TL01G_ENTER_DEEP_POWER_DOWN   0xB9
#define	MT25TL01G_RELEASE_FROM_DEEP_POWER_DOWN   0xAB
#define	MT25TL01G_READ_SECTOR_PROTECTION_CMD   0x2D
#define	MT25TL01G_PROGRAM_SECTOR_PROTECTION   0x2C
#define	MT25TL01G_READ_PASSWORD_CMD   0x27
#define	MT25TL01G_WRITE_PASSWORD_CMD   0x28
#define	MT25TL01G_UNLOCK_PASSWORD_CMD   0x29
#define	MT25TL01G_READ_GLOBAL_FREEZE_BIT   0xA7
#define	MT25TL01G_READ_VOLATILE_LOCK_BITS   0xE8
#define	MT25TL01G_WRITE_VOLATILE_LOCK_BITS   0xE5
#define	MT25TL01G_WRITE_4_BYTE_VOLATILE_LOCK_BITS   0xE1
#define	MT25TL01G_READ_4_BYTE_VOLATILE_LOCK_BITS   0xE0
#define	MT25TL01G_READ_OTP_ARRAY   0x4B
#define	MT25TL01G_PROGRAM_OTP_ARRAY   0x42
#define	MT25TL01G_SR_WIP   ((uint8_t)0x01)
	MT25TL01G Registers.
#define	MT25TL01G_SR_WREN   ((uint8_t)0x02)
#define	MT25TL01G_SR_BLOCKPR   ((uint8_t)0x5C)
#define	MT25TL01G_SR_PRBOTTOM   ((uint8_t)0x20)
#define	MT25TL01G_SR_SRWREN   ((uint8_t)0x80)
#define	MT25TL01G_NVCR_NBADDR   ((uint16_t)0x0001)
#define	MT25TL01G_NVCR_SEGMENT   ((uint16_t)0x0002)
#define	MT25TL01G_NVCR_DUAL   ((uint16_t)0x0004)
#define	MT25TL01G_NVCR_QUAB   ((uint16_t)0x0008)
#define	MT25TL01G_NVCR_RH   ((uint16_t)0x0010)
#define	MT25TL01G_NVCR_DTRP   ((uint16_t)0x0020)
#define	MT25TL01G_NVCR_ODS   ((uint16_t)0x01C0)
#define	MT25TL01G_NVCR_XIP   ((uint16_t)0x0E00)
#define	MT25TL01G_NVCR_NB_DUMMY   ((uint16_t)0xF000)
#define	MT25TL01G_VCR_WRAP   ((uint8_t)0x03)
#define	MT25TL01G_VCR_XIP   ((uint8_t)0x08)
#define	MT25TL01G_VCR_NB_DUMMY   ((uint8_t)0xF0)
#define	MT25TL01G_EAR_HIGHEST_SE   ((uint8_t)0x03)
#define	MT25TL01G_EAR_THIRD_SEG   ((uint8_t)0x02)
#define	MT25TL01G_EAR_SECOND_SEG   ((uint8_t)0x01)
#define	MT25TL01G_EAR_LOWEST_SEG   ((uint8_t)0x00)
#define	MT25TL01G_EVCR_ODS   ((uint8_t)0x07)
#define	MT25TL01G_EVCR_RH   ((uint8_t)0x10)
#define	MT25TL01G_EVCR_DTRP   ((uint8_t)0x20)
#define	MT25TL01G_EVCR_DUAL   ((uint8_t)0x40)
#define	MT25TL01G_EVCR_QUAD   ((uint8_t)0x80)
#define	MT25TL01G_FSR_NBADDR   ((uint8_t)0x01)
#define	MT25TL01G_FSR_PRERR   ((uint8_t)0x02)
#define	MT25TL01G_FSR_PGSUS   ((uint8_t)0x04)
#define	MT25TL01G_FSR_PGERR   ((uint8_t)0x10)
#define	MT25TL01G_FSR_ERERR   ((uint8_t)0x20)
#define	MT25TL01G_FSR_ERSUS   ((uint8_t)0x40)
#define	MT25TL01G_FSR_READY   ((uint8_t)0x80)

Detailed Description

Macro Definition Documentation

MT25TL01G_EAR_HIGHEST_SE

#define MT25TL01G_EAR_HIGHEST_SE   ((uint8_t)0x03)

Select the Highest 128Mb segment

MT25TL01G_EAR_LOWEST_SEG

#define MT25TL01G_EAR_LOWEST_SEG   ((uint8_t)0x00)

Select the Lowest 128Mb segment (default)

MT25TL01G_EAR_SECOND_SEG

#define MT25TL01G_EAR_SECOND_SEG   ((uint8_t)0x01)

Select the Second 128Mb segment

MT25TL01G_EAR_THIRD_SEG

#define MT25TL01G_EAR_THIRD_SEG   ((uint8_t)0x02)

Select the Third 128Mb segment

MT25TL01G_EVCR_DTRP

#define MT25TL01G_EVCR_DTRP   ((uint8_t)0x20)

Double transfer rate protocol

MT25TL01G_EVCR_DUAL

#define MT25TL01G_EVCR_DUAL   ((uint8_t)0x40)

Dual I/O protocol

MT25TL01G_EVCR_ODS

#define MT25TL01G_EVCR_ODS   ((uint8_t)0x07)

Output driver strength

MT25TL01G_EVCR_QUAD

#define MT25TL01G_EVCR_QUAD   ((uint8_t)0x80)

Quad I/O protocol

MT25TL01G_EVCR_RH

#define MT25TL01G_EVCR_RH   ((uint8_t)0x10)

Reset/hold

MT25TL01G_FSR_ERERR

#define MT25TL01G_FSR_ERERR   ((uint8_t)0x20)

Erase error

MT25TL01G_FSR_ERSUS

#define MT25TL01G_FSR_ERSUS   ((uint8_t)0x40)

Erase operation suspended

MT25TL01G_FSR_NBADDR

#define MT25TL01G_FSR_NBADDR   ((uint8_t)0x01)

3-bytes or 4-bytes addressing

MT25TL01G_FSR_PGERR

#define MT25TL01G_FSR_PGERR   ((uint8_t)0x10)

Program error

MT25TL01G_FSR_PGSUS

#define MT25TL01G_FSR_PGSUS   ((uint8_t)0x04)

Program operation suspended

MT25TL01G_FSR_PRERR

#define MT25TL01G_FSR_PRERR   ((uint8_t)0x02)

Protection error

MT25TL01G_FSR_READY

#define MT25TL01G_FSR_READY   ((uint8_t)0x80)

Ready or command in progress

MT25TL01G_NVCR_DTRP

#define MT25TL01G_NVCR_DTRP   ((uint16_t)0x0020)

Double transfer rate protocol

MT25TL01G_NVCR_DUAL

#define MT25TL01G_NVCR_DUAL   ((uint16_t)0x0004)

Dual I/O protocol

MT25TL01G_NVCR_NB_DUMMY

#define MT25TL01G_NVCR_NB_DUMMY   ((uint16_t)0xF000)

Number of dummy clock cycles

MT25TL01G_NVCR_NBADDR

#define MT25TL01G_NVCR_NBADDR   ((uint16_t)0x0001)

3-bytes or 4-bytes addressing

MT25TL01G_NVCR_ODS

#define MT25TL01G_NVCR_ODS   ((uint16_t)0x01C0)

Output driver strength

MT25TL01G_NVCR_QUAB

#define MT25TL01G_NVCR_QUAB   ((uint16_t)0x0008)

Quad I/O protocol

MT25TL01G_NVCR_RH

#define MT25TL01G_NVCR_RH   ((uint16_t)0x0010)

Reset/hold

MT25TL01G_NVCR_SEGMENT

#define MT25TL01G_NVCR_SEGMENT   ((uint16_t)0x0002)

Upper or lower 128Mb segment selected by default

MT25TL01G_NVCR_XIP

#define MT25TL01G_NVCR_XIP   ((uint16_t)0x0E00)

XIP mode at power-on reset

MT25TL01G_SR_BLOCKPR

#define MT25TL01G_SR_BLOCKPR   ((uint8_t)0x5C)

Block protected against program and erase operations

MT25TL01G_SR_PRBOTTOM

#define MT25TL01G_SR_PRBOTTOM   ((uint8_t)0x20)

Protected memory area defined by BLOCKPR starts from top or bottom

MT25TL01G_SR_SRWREN

#define MT25TL01G_SR_SRWREN   ((uint8_t)0x80)

Status register write enable/disable

MT25TL01G_SR_WIP

#define MT25TL01G_SR_WIP   ((uint8_t)0x01)

MT25TL01G Registers.

Write in progress

MT25TL01G_SR_WREN

#define MT25TL01G_SR_WREN   ((uint8_t)0x02)

Write enable latch

MT25TL01G_VCR_NB_DUMMY

#define MT25TL01G_VCR_NB_DUMMY   ((uint8_t)0xF0)

Number of dummy clock cycles

MT25TL01G_VCR_WRAP

#define MT25TL01G_VCR_WRAP   ((uint8_t)0x03)

Wrap

MT25TL01G_VCR_XIP

#define MT25TL01G_VCR_XIP   ((uint8_t)0x08)

XIP