Floating Point Unit (FPU)

Type definitions for the Floating Point Unit (FPU). More...

Topics
	Core Debug Registers (CoreDebug)
	Type definitions for the Core Debug Registers.

Data Structures
struct	FPU_Type
	Structure type to access the Floating Point Unit (FPU). More...
#define	FPU_FPCCR_ASPEN_Pos   31U
#define	FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
#define	FPU_FPCCR_LSPEN_Pos   30U
#define	FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
#define	FPU_FPCCR_MONRDY_Pos   8U
#define	FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
#define	FPU_FPCCR_BFRDY_Pos   6U
#define	FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
#define	FPU_FPCCR_MMRDY_Pos   5U
#define	FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
#define	FPU_FPCCR_HFRDY_Pos   4U
#define	FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
#define	FPU_FPCCR_THREAD_Pos   3U
#define	FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
#define	FPU_FPCCR_USER_Pos   1U
#define	FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
#define	FPU_FPCCR_LSPACT_Pos   0U
#define	FPU_FPCCR_LSPACT_Msk   (1UL )
#define	FPU_FPCAR_ADDRESS_Pos   3U
#define	FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
#define	FPU_FPDSCR_AHP_Pos   26U
#define	FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
#define	FPU_FPDSCR_DN_Pos   25U
#define	FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
#define	FPU_FPDSCR_FZ_Pos   24U
#define	FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
#define	FPU_FPDSCR_RMode_Pos   22U
#define	FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
#define	FPU_MVFR0_FP_rounding_modes_Pos   28U
#define	FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
#define	FPU_MVFR0_Short_vectors_Pos   24U
#define	FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
#define	FPU_MVFR0_Square_root_Pos   20U
#define	FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
#define	FPU_MVFR0_Divide_Pos   16U
#define	FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
#define	FPU_MVFR0_FP_excep_trapping_Pos   12U
#define	FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
#define	FPU_MVFR0_Double_precision_Pos   8U
#define	FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
#define	FPU_MVFR0_Single_precision_Pos   4U
#define	FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
#define	FPU_MVFR0_A_SIMD_registers_Pos   0U
#define	FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL )
#define	FPU_MVFR1_FP_fused_MAC_Pos   28U
#define	FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
#define	FPU_MVFR1_FP_HPFP_Pos   24U
#define	FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
#define	FPU_MVFR1_D_NaN_mode_Pos   4U
#define	FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
#define	FPU_MVFR1_FtZ_mode_Pos   0U
#define	FPU_MVFR1_FtZ_mode_Msk   (0xFUL )
#define	FPU_MVFR2_VFP_Misc_Pos   4U
#define	FPU_MVFR2_VFP_Misc_Msk   (0xFUL << FPU_MVFR2_VFP_Misc_Pos)
#define	FPU_FPCCR_ASPEN_Pos   31U
#define	FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
#define	FPU_FPCCR_LSPEN_Pos   30U
#define	FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
#define	FPU_FPCCR_MONRDY_Pos   8U
#define	FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
#define	FPU_FPCCR_BFRDY_Pos   6U
#define	FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
#define	FPU_FPCCR_MMRDY_Pos   5U
#define	FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
#define	FPU_FPCCR_HFRDY_Pos   4U
#define	FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
#define	FPU_FPCCR_THREAD_Pos   3U
#define	FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
#define	FPU_FPCCR_USER_Pos   1U
#define	FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
#define	FPU_FPCCR_LSPACT_Pos   0U
#define	FPU_FPCCR_LSPACT_Msk   (1UL )
#define	FPU_FPCAR_ADDRESS_Pos   3U
#define	FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
#define	FPU_FPDSCR_AHP_Pos   26U
#define	FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
#define	FPU_FPDSCR_DN_Pos   25U
#define	FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
#define	FPU_FPDSCR_FZ_Pos   24U
#define	FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
#define	FPU_FPDSCR_RMode_Pos   22U
#define	FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
#define	FPU_MVFR0_FP_rounding_modes_Pos   28U
#define	FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
#define	FPU_MVFR0_Short_vectors_Pos   24U
#define	FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
#define	FPU_MVFR0_Square_root_Pos   20U
#define	FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
#define	FPU_MVFR0_Divide_Pos   16U
#define	FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
#define	FPU_MVFR0_FP_excep_trapping_Pos   12U
#define	FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
#define	FPU_MVFR0_Double_precision_Pos   8U
#define	FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
#define	FPU_MVFR0_Single_precision_Pos   4U
#define	FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
#define	FPU_MVFR0_A_SIMD_registers_Pos   0U
#define	FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL )
#define	FPU_MVFR1_FP_fused_MAC_Pos   28U
#define	FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
#define	FPU_MVFR1_FP_HPFP_Pos   24U
#define	FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
#define	FPU_MVFR1_D_NaN_mode_Pos   4U
#define	FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
#define	FPU_MVFR1_FtZ_mode_Pos   0U
#define	FPU_MVFR1_FtZ_mode_Msk   (0xFUL )
#define	FPU_MVFR2_VFP_Misc_Pos   4U
#define	FPU_MVFR2_VFP_Misc_Msk   (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

Detailed Description

Type definitions for the Floating Point Unit (FPU).

Macro Definition Documentation

FPU_FPCAR_ADDRESS_Msk [1/2]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

FPU_FPCAR_ADDRESS_Msk [2/2]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

FPU_FPCAR_ADDRESS_Pos [1/2]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

FPU_FPCAR_ADDRESS_Pos [2/2]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

FPU_FPCCR_ASPEN_Msk [1/2]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

FPU_FPCCR_ASPEN_Msk [2/2]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

FPU_FPCCR_ASPEN_Pos [1/2]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

FPU_FPCCR_ASPEN_Pos [2/2]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

FPU_FPCCR_BFRDY_Msk [1/2]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

FPU_FPCCR_BFRDY_Msk [2/2]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

FPU_FPCCR_BFRDY_Pos [1/2]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

FPU_FPCCR_BFRDY_Pos [2/2]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

FPU_FPCCR_HFRDY_Msk [1/2]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

FPU_FPCCR_HFRDY_Msk [2/2]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

FPU_FPCCR_HFRDY_Pos [1/2]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

FPU_FPCCR_HFRDY_Pos [2/2]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

FPU_FPCCR_LSPACT_Msk [1/2]

#define FPU_FPCCR_LSPACT_Msk   (1UL )

FPCCR: Lazy state preservation active bit Mask

FPU_FPCCR_LSPACT_Msk [2/2]

#define FPU_FPCCR_LSPACT_Msk   (1UL )

FPCCR: Lazy state preservation active bit Mask

FPU_FPCCR_LSPACT_Pos [1/2]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

FPU_FPCCR_LSPACT_Pos [2/2]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

FPU_FPCCR_LSPEN_Msk [1/2]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

FPU_FPCCR_LSPEN_Msk [2/2]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

FPU_FPCCR_LSPEN_Pos [1/2]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

FPU_FPCCR_LSPEN_Pos [2/2]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

FPU_FPCCR_MMRDY_Msk [1/2]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

FPU_FPCCR_MMRDY_Msk [2/2]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

FPU_FPCCR_MMRDY_Pos [1/2]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

FPU_FPCCR_MMRDY_Pos [2/2]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

FPU_FPCCR_MONRDY_Msk [1/2]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

FPU_FPCCR_MONRDY_Msk [2/2]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

FPU_FPCCR_MONRDY_Pos [1/2]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

FPU_FPCCR_MONRDY_Pos [2/2]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

FPU_FPCCR_THREAD_Msk [1/2]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

FPU_FPCCR_THREAD_Msk [2/2]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

FPU_FPCCR_THREAD_Pos [1/2]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

FPU_FPCCR_THREAD_Pos [2/2]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

FPU_FPCCR_USER_Msk [1/2]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

FPU_FPCCR_USER_Msk [2/2]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

FPU_FPCCR_USER_Pos [1/2]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

FPU_FPCCR_USER_Pos [2/2]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

FPU_FPDSCR_AHP_Msk [1/2]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

FPU_FPDSCR_AHP_Msk [2/2]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

FPU_FPDSCR_AHP_Pos [1/2]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

FPU_FPDSCR_AHP_Pos [2/2]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

FPU_FPDSCR_DN_Msk [1/2]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

FPU_FPDSCR_DN_Msk [2/2]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

FPU_FPDSCR_DN_Pos [1/2]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

FPU_FPDSCR_DN_Pos [2/2]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

FPU_FPDSCR_FZ_Msk [1/2]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

FPU_FPDSCR_FZ_Msk [2/2]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

FPU_FPDSCR_FZ_Pos [1/2]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

FPU_FPDSCR_FZ_Pos [2/2]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

FPU_FPDSCR_RMode_Msk [1/2]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

FPU_FPDSCR_RMode_Msk [2/2]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

FPU_FPDSCR_RMode_Pos [1/2]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

FPU_FPDSCR_RMode_Pos [2/2]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

FPU_MVFR0_A_SIMD_registers_Msk [1/2]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL )

MVFR0: A_SIMD registers bits Mask

FPU_MVFR0_A_SIMD_registers_Msk [2/2]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL )

MVFR0: A_SIMD registers bits Mask

FPU_MVFR0_A_SIMD_registers_Pos [1/2]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

FPU_MVFR0_A_SIMD_registers_Pos [2/2]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

FPU_MVFR0_Divide_Msk [1/2]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

FPU_MVFR0_Divide_Msk [2/2]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

FPU_MVFR0_Divide_Pos [1/2]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

FPU_MVFR0_Divide_Pos [2/2]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

FPU_MVFR0_Double_precision_Msk [1/2]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

FPU_MVFR0_Double_precision_Msk [2/2]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

FPU_MVFR0_Double_precision_Pos [1/2]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

FPU_MVFR0_Double_precision_Pos [2/2]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

FPU_MVFR0_FP_excep_trapping_Msk [1/2]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

FPU_MVFR0_FP_excep_trapping_Msk [2/2]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

FPU_MVFR0_FP_excep_trapping_Pos [1/2]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

FPU_MVFR0_FP_excep_trapping_Pos [2/2]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

FPU_MVFR0_FP_rounding_modes_Msk [1/2]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

FPU_MVFR0_FP_rounding_modes_Msk [2/2]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

FPU_MVFR0_FP_rounding_modes_Pos [1/2]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

FPU_MVFR0_FP_rounding_modes_Pos [2/2]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

FPU_MVFR0_Short_vectors_Msk [1/2]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

FPU_MVFR0_Short_vectors_Msk [2/2]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

FPU_MVFR0_Short_vectors_Pos [1/2]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

FPU_MVFR0_Short_vectors_Pos [2/2]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

FPU_MVFR0_Single_precision_Msk [1/2]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

FPU_MVFR0_Single_precision_Msk [2/2]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

FPU_MVFR0_Single_precision_Pos [1/2]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

FPU_MVFR0_Single_precision_Pos [2/2]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

FPU_MVFR0_Square_root_Msk [1/2]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

FPU_MVFR0_Square_root_Msk [2/2]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

FPU_MVFR0_Square_root_Pos [1/2]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

FPU_MVFR0_Square_root_Pos [2/2]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

FPU_MVFR1_D_NaN_mode_Msk [1/2]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

FPU_MVFR1_D_NaN_mode_Msk [2/2]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

FPU_MVFR1_D_NaN_mode_Pos [1/2]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

FPU_MVFR1_D_NaN_mode_Pos [2/2]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

FPU_MVFR1_FP_fused_MAC_Msk [1/2]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

FPU_MVFR1_FP_fused_MAC_Msk [2/2]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

FPU_MVFR1_FP_fused_MAC_Pos [1/2]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

FPU_MVFR1_FP_fused_MAC_Pos [2/2]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

FPU_MVFR1_FP_HPFP_Msk [1/2]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

FPU_MVFR1_FP_HPFP_Msk [2/2]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

FPU_MVFR1_FP_HPFP_Pos [1/2]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

FPU_MVFR1_FP_HPFP_Pos [2/2]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

FPU_MVFR1_FtZ_mode_Msk [1/2]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL )

MVFR1: FtZ mode bits Mask

FPU_MVFR1_FtZ_mode_Msk [2/2]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL )

MVFR1: FtZ mode bits Mask

FPU_MVFR1_FtZ_mode_Pos [1/2]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

FPU_MVFR1_FtZ_mode_Pos [2/2]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

FPU_MVFR2_VFP_Misc_Msk [1/2]

#define FPU_MVFR2_VFP_Misc_Msk   (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

MVFR2: VFP Misc bits Mask

FPU_MVFR2_VFP_Misc_Msk [2/2]

#define FPU_MVFR2_VFP_Misc_Msk   (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

MVFR2: VFP Misc bits Mask

FPU_MVFR2_VFP_Misc_Pos [1/2]

#define FPU_MVFR2_VFP_Misc_Pos   4U

MVFR2: VFP Misc bits Position

FPU_MVFR2_VFP_Misc_Pos [2/2]

#define FPU_MVFR2_VFP_Misc_Pos   4U

MVFR2: VFP Misc bits Position