RTEMS 6.3
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gr740-iopll-regs.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11
12/*
13 * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/*
38 * This file is part of the RTEMS quality process and was automatically
39 * generated. If you find something that needs to be fixed or
40 * worded better please post a report or patch to an RTEMS mailing list
41 * or raise a bug report:
42 *
43 * https://www.rtems.org/bugs.html
44 *
45 * For information on updating and regenerating please refer to the How-To
46 * section in the Software Requirements Engineering chapter of the
47 * RTEMS Software Engineering manual. The manual is provided as a part of
48 * a release. For development sources please refer to the online
49 * documentation at:
50 *
51 * https://docs.rtems.org
52 */
53
54/* Generated from spec:/bsp/sparc/leon3/if/gr740-iopll-header */
55
56#ifndef _BSP_GR740_IOPLL_REGS_H
57#define _BSP_GR740_IOPLL_REGS_H
58
59#include <stdint.h>
60
61#ifdef __cplusplus
62extern "C" {
63#endif
64
65/* Generated from spec:/bsp/sparc/leon3/if/gr740-iopll */
66
76
85
86#define GR740_IOPLL_FTMFUNC_FTMEN_SHIFT 0
87#define GR740_IOPLL_FTMFUNC_FTMEN_MASK 0x3fffffU
88#define GR740_IOPLL_FTMFUNC_FTMEN_GET( _reg ) \
89 ( ( ( _reg ) & GR740_IOPLL_FTMFUNC_FTMEN_MASK ) >> \
90 GR740_IOPLL_FTMFUNC_FTMEN_SHIFT )
91#define GR740_IOPLL_FTMFUNC_FTMEN_SET( _reg, _val ) \
92 ( ( ( _reg ) & ~GR740_IOPLL_FTMFUNC_FTMEN_MASK ) | \
93 ( ( ( _val ) << GR740_IOPLL_FTMFUNC_FTMEN_SHIFT ) & \
94 GR740_IOPLL_FTMFUNC_FTMEN_MASK ) )
95#define GR740_IOPLL_FTMFUNC_FTMEN( _val ) \
96 ( ( ( _val ) << GR740_IOPLL_FTMFUNC_FTMEN_SHIFT ) & \
97 GR740_IOPLL_FTMFUNC_FTMEN_MASK )
98
100
109
110#define GR740_IOPLL_ALTFUNC_ALTEN_SHIFT 0
111#define GR740_IOPLL_ALTFUNC_ALTEN_MASK 0x3fffffU
112#define GR740_IOPLL_ALTFUNC_ALTEN_GET( _reg ) \
113 ( ( ( _reg ) & GR740_IOPLL_ALTFUNC_ALTEN_MASK ) >> \
114 GR740_IOPLL_ALTFUNC_ALTEN_SHIFT )
115#define GR740_IOPLL_ALTFUNC_ALTEN_SET( _reg, _val ) \
116 ( ( ( _reg ) & ~GR740_IOPLL_ALTFUNC_ALTEN_MASK ) | \
117 ( ( ( _val ) << GR740_IOPLL_ALTFUNC_ALTEN_SHIFT ) & \
118 GR740_IOPLL_ALTFUNC_ALTEN_MASK ) )
119#define GR740_IOPLL_ALTFUNC_ALTEN( _val ) \
120 ( ( ( _val ) << GR740_IOPLL_ALTFUNC_ALTEN_SHIFT ) & \
121 GR740_IOPLL_ALTFUNC_ALTEN_MASK )
122
124
133
134#define GR740_IOPLL_LVDSMCLK_SMEM 0x20000U
135
136#define GR740_IOPLL_LVDSMCLK_DMEM 0x10000U
137
138#define GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT 0
139#define GR740_IOPLL_LVDSMCLK_SPWOE_MASK 0xffU
140#define GR740_IOPLL_LVDSMCLK_SPWOE_GET( _reg ) \
141 ( ( ( _reg ) & GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) >> \
142 GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT )
143#define GR740_IOPLL_LVDSMCLK_SPWOE_SET( _reg, _val ) \
144 ( ( ( _reg ) & ~GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) | \
145 ( ( ( _val ) << GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT ) & \
146 GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) )
147#define GR740_IOPLL_LVDSMCLK_SPWOE( _val ) \
148 ( ( ( _val ) << GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT ) & \
149 GR740_IOPLL_LVDSMCLK_SPWOE_MASK )
150
152
161
162#define GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT 27
163#define GR740_IOPLL_PLLNEWCFG_SWTAG_MASK 0x18000000U
164#define GR740_IOPLL_PLLNEWCFG_SWTAG_GET( _reg ) \
165 ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) >> \
166 GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT )
167#define GR740_IOPLL_PLLNEWCFG_SWTAG_SET( _reg, _val ) \
168 ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) | \
169 ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT ) & \
170 GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) )
171#define GR740_IOPLL_PLLNEWCFG_SWTAG( _val ) \
172 ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT ) & \
173 GR740_IOPLL_PLLNEWCFG_SWTAG_MASK )
174
175#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT 18
176#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK 0x7fc0000U
177#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_GET( _reg ) \
178 ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) >> \
179 GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT )
180#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SET( _reg, _val ) \
181 ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) | \
182 ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT ) & \
183 GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) )
184#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG( _val ) \
185 ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT ) & \
186 GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK )
187
188#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT 9
189#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK 0x3fe00U
190#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_GET( _reg ) \
191 ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) >> \
192 GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT )
193#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SET( _reg, _val ) \
194 ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) | \
195 ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT ) & \
196 GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) )
197#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG( _val ) \
198 ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT ) & \
199 GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK )
200
201#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT 0
202#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK 0x1ffU
203#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_GET( _reg ) \
204 ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) >> \
205 GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT )
206#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SET( _reg, _val ) \
207 ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) | \
208 ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT ) & \
209 GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) )
210#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG( _val ) \
211 ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT ) & \
212 GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK )
213
215
224
225#define GR740_IOPLL_PLLRECFG_RECONF_SHIFT 0
226#define GR740_IOPLL_PLLRECFG_RECONF_MASK 0x7U
227#define GR740_IOPLL_PLLRECFG_RECONF_GET( _reg ) \
228 ( ( ( _reg ) & GR740_IOPLL_PLLRECFG_RECONF_MASK ) >> \
229 GR740_IOPLL_PLLRECFG_RECONF_SHIFT )
230#define GR740_IOPLL_PLLRECFG_RECONF_SET( _reg, _val ) \
231 ( ( ( _reg ) & ~GR740_IOPLL_PLLRECFG_RECONF_MASK ) | \
232 ( ( ( _val ) << GR740_IOPLL_PLLRECFG_RECONF_SHIFT ) & \
233 GR740_IOPLL_PLLRECFG_RECONF_MASK ) )
234#define GR740_IOPLL_PLLRECFG_RECONF( _val ) \
235 ( ( ( _val ) << GR740_IOPLL_PLLRECFG_RECONF_SHIFT ) & \
236 GR740_IOPLL_PLLRECFG_RECONF_MASK )
237
239
248
249#define GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT 27
250#define GR740_IOPLL_PLLCURCFG_SWTAG_MASK 0x18000000U
251#define GR740_IOPLL_PLLCURCFG_SWTAG_GET( _reg ) \
252 ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) >> \
253 GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT )
254#define GR740_IOPLL_PLLCURCFG_SWTAG_SET( _reg, _val ) \
255 ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) | \
256 ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT ) & \
257 GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) )
258#define GR740_IOPLL_PLLCURCFG_SWTAG( _val ) \
259 ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT ) & \
260 GR740_IOPLL_PLLCURCFG_SWTAG_MASK )
261
262#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT 18
263#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK 0x7fc0000U
264#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_GET( _reg ) \
265 ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) >> \
266 GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT )
267#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SET( _reg, _val ) \
268 ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) | \
269 ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT ) & \
270 GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) )
271#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG( _val ) \
272 ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT ) & \
273 GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK )
274
275#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT 9
276#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK 0x3fe00U
277#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_GET( _reg ) \
278 ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) >> \
279 GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT )
280#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SET( _reg, _val ) \
281 ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) | \
282 ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT ) & \
283 GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) )
284#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG( _val ) \
285 ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT ) & \
286 GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK )
287
288#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT 0
289#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK 0x1ffU
290#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_GET( _reg ) \
291 ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) >> \
292 GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT )
293#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SET( _reg, _val ) \
294 ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) | \
295 ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT ) & \
296 GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) )
297#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG( _val ) \
298 ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT ) & \
299 GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK )
300
302
311
312#define GR740_IOPLL_DRVSTR1_S9_SHIFT 18
313#define GR740_IOPLL_DRVSTR1_S9_MASK 0xc0000U
314#define GR740_IOPLL_DRVSTR1_S9_GET( _reg ) \
315 ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S9_MASK ) >> \
316 GR740_IOPLL_DRVSTR1_S9_SHIFT )
317#define GR740_IOPLL_DRVSTR1_S9_SET( _reg, _val ) \
318 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S9_MASK ) | \
319 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S9_SHIFT ) & \
320 GR740_IOPLL_DRVSTR1_S9_MASK ) )
321#define GR740_IOPLL_DRVSTR1_S9( _val ) \
322 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S9_SHIFT ) & \
323 GR740_IOPLL_DRVSTR1_S9_MASK )
324
325#define GR740_IOPLL_DRVSTR1_S8_SHIFT 16
326#define GR740_IOPLL_DRVSTR1_S8_MASK 0x30000U
327#define GR740_IOPLL_DRVSTR1_S8_GET( _reg ) \
328 ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S8_MASK ) >> \
329 GR740_IOPLL_DRVSTR1_S8_SHIFT )
330#define GR740_IOPLL_DRVSTR1_S8_SET( _reg, _val ) \
331 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S8_MASK ) | \
332 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S8_SHIFT ) & \
333 GR740_IOPLL_DRVSTR1_S8_MASK ) )
334#define GR740_IOPLL_DRVSTR1_S8( _val ) \
335 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S8_SHIFT ) & \
336 GR740_IOPLL_DRVSTR1_S8_MASK )
337
338#define GR740_IOPLL_DRVSTR1_S7_SHIFT 14
339#define GR740_IOPLL_DRVSTR1_S7_MASK 0xc000U
340#define GR740_IOPLL_DRVSTR1_S7_GET( _reg ) \
341 ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S7_MASK ) >> \
342 GR740_IOPLL_DRVSTR1_S7_SHIFT )
343#define GR740_IOPLL_DRVSTR1_S7_SET( _reg, _val ) \
344 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S7_MASK ) | \
345 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S7_SHIFT ) & \
346 GR740_IOPLL_DRVSTR1_S7_MASK ) )
347#define GR740_IOPLL_DRVSTR1_S7( _val ) \
348 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S7_SHIFT ) & \
349 GR740_IOPLL_DRVSTR1_S7_MASK )
350
351#define GR740_IOPLL_DRVSTR1_S6_SHIFT 12
352#define GR740_IOPLL_DRVSTR1_S6_MASK 0x3000U
353#define GR740_IOPLL_DRVSTR1_S6_GET( _reg ) \
354 ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S6_MASK ) >> \
355 GR740_IOPLL_DRVSTR1_S6_SHIFT )
356#define GR740_IOPLL_DRVSTR1_S6_SET( _reg, _val ) \
357 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S6_MASK ) | \
358 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S6_SHIFT ) & \
359 GR740_IOPLL_DRVSTR1_S6_MASK ) )
360#define GR740_IOPLL_DRVSTR1_S6( _val ) \
361 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S6_SHIFT ) & \
362 GR740_IOPLL_DRVSTR1_S6_MASK )
363
364#define GR740_IOPLL_DRVSTR1_S5_SHIFT 10
365#define GR740_IOPLL_DRVSTR1_S5_MASK 0xc00U
366#define GR740_IOPLL_DRVSTR1_S5_GET( _reg ) \
367 ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S5_MASK ) >> \
368 GR740_IOPLL_DRVSTR1_S5_SHIFT )
369#define GR740_IOPLL_DRVSTR1_S5_SET( _reg, _val ) \
370 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S5_MASK ) | \
371 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S5_SHIFT ) & \
372 GR740_IOPLL_DRVSTR1_S5_MASK ) )
373#define GR740_IOPLL_DRVSTR1_S5( _val ) \
374 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S5_SHIFT ) & \
375 GR740_IOPLL_DRVSTR1_S5_MASK )
376
377#define GR740_IOPLL_DRVSTR1_S4_SHIFT 8
378#define GR740_IOPLL_DRVSTR1_S4_MASK 0x300U
379#define GR740_IOPLL_DRVSTR1_S4_GET( _reg ) \
380 ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S4_MASK ) >> \
381 GR740_IOPLL_DRVSTR1_S4_SHIFT )
382#define GR740_IOPLL_DRVSTR1_S4_SET( _reg, _val ) \
383 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S4_MASK ) | \
384 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S4_SHIFT ) & \
385 GR740_IOPLL_DRVSTR1_S4_MASK ) )
386#define GR740_IOPLL_DRVSTR1_S4( _val ) \
387 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S4_SHIFT ) & \
388 GR740_IOPLL_DRVSTR1_S4_MASK )
389
390#define GR740_IOPLL_DRVSTR1_S3_SHIFT 6
391#define GR740_IOPLL_DRVSTR1_S3_MASK 0xc0U
392#define GR740_IOPLL_DRVSTR1_S3_GET( _reg ) \
393 ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S3_MASK ) >> \
394 GR740_IOPLL_DRVSTR1_S3_SHIFT )
395#define GR740_IOPLL_DRVSTR1_S3_SET( _reg, _val ) \
396 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S3_MASK ) | \
397 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S3_SHIFT ) & \
398 GR740_IOPLL_DRVSTR1_S3_MASK ) )
399#define GR740_IOPLL_DRVSTR1_S3( _val ) \
400 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S3_SHIFT ) & \
401 GR740_IOPLL_DRVSTR1_S3_MASK )
402
403#define GR740_IOPLL_DRVSTR1_S2_SHIFT 4
404#define GR740_IOPLL_DRVSTR1_S2_MASK 0x30U
405#define GR740_IOPLL_DRVSTR1_S2_GET( _reg ) \
406 ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S2_MASK ) >> \
407 GR740_IOPLL_DRVSTR1_S2_SHIFT )
408#define GR740_IOPLL_DRVSTR1_S2_SET( _reg, _val ) \
409 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S2_MASK ) | \
410 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S2_SHIFT ) & \
411 GR740_IOPLL_DRVSTR1_S2_MASK ) )
412#define GR740_IOPLL_DRVSTR1_S2( _val ) \
413 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S2_SHIFT ) & \
414 GR740_IOPLL_DRVSTR1_S2_MASK )
415
416#define GR740_IOPLL_DRVSTR1_S1_SHIFT 2
417#define GR740_IOPLL_DRVSTR1_S1_MASK 0xcU
418#define GR740_IOPLL_DRVSTR1_S1_GET( _reg ) \
419 ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S1_MASK ) >> \
420 GR740_IOPLL_DRVSTR1_S1_SHIFT )
421#define GR740_IOPLL_DRVSTR1_S1_SET( _reg, _val ) \
422 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S1_MASK ) | \
423 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S1_SHIFT ) & \
424 GR740_IOPLL_DRVSTR1_S1_MASK ) )
425#define GR740_IOPLL_DRVSTR1_S1( _val ) \
426 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S1_SHIFT ) & \
427 GR740_IOPLL_DRVSTR1_S1_MASK )
428
429#define GR740_IOPLL_DRVSTR1_S0_SHIFT 0
430#define GR740_IOPLL_DRVSTR1_S0_MASK 0x3U
431#define GR740_IOPLL_DRVSTR1_S0_GET( _reg ) \
432 ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S0_MASK ) >> \
433 GR740_IOPLL_DRVSTR1_S0_SHIFT )
434#define GR740_IOPLL_DRVSTR1_S0_SET( _reg, _val ) \
435 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S0_MASK ) | \
436 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S0_SHIFT ) & \
437 GR740_IOPLL_DRVSTR1_S0_MASK ) )
438#define GR740_IOPLL_DRVSTR1_S0( _val ) \
439 ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S0_SHIFT ) & \
440 GR740_IOPLL_DRVSTR1_S0_MASK )
441
443
452
453#define GR740_IOPLL_DRVSTR2_S19_SHIFT 18
454#define GR740_IOPLL_DRVSTR2_S19_MASK 0xc0000U
455#define GR740_IOPLL_DRVSTR2_S19_GET( _reg ) \
456 ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S19_MASK ) >> \
457 GR740_IOPLL_DRVSTR2_S19_SHIFT )
458#define GR740_IOPLL_DRVSTR2_S19_SET( _reg, _val ) \
459 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S19_MASK ) | \
460 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S19_SHIFT ) & \
461 GR740_IOPLL_DRVSTR2_S19_MASK ) )
462#define GR740_IOPLL_DRVSTR2_S19( _val ) \
463 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S19_SHIFT ) & \
464 GR740_IOPLL_DRVSTR2_S19_MASK )
465
466#define GR740_IOPLL_DRVSTR2_S18_SHIFT 16
467#define GR740_IOPLL_DRVSTR2_S18_MASK 0x30000U
468#define GR740_IOPLL_DRVSTR2_S18_GET( _reg ) \
469 ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S18_MASK ) >> \
470 GR740_IOPLL_DRVSTR2_S18_SHIFT )
471#define GR740_IOPLL_DRVSTR2_S18_SET( _reg, _val ) \
472 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S18_MASK ) | \
473 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S18_SHIFT ) & \
474 GR740_IOPLL_DRVSTR2_S18_MASK ) )
475#define GR740_IOPLL_DRVSTR2_S18( _val ) \
476 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S18_SHIFT ) & \
477 GR740_IOPLL_DRVSTR2_S18_MASK )
478
479#define GR740_IOPLL_DRVSTR2_S17_SHIFT 14
480#define GR740_IOPLL_DRVSTR2_S17_MASK 0xc000U
481#define GR740_IOPLL_DRVSTR2_S17_GET( _reg ) \
482 ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S17_MASK ) >> \
483 GR740_IOPLL_DRVSTR2_S17_SHIFT )
484#define GR740_IOPLL_DRVSTR2_S17_SET( _reg, _val ) \
485 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S17_MASK ) | \
486 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S17_SHIFT ) & \
487 GR740_IOPLL_DRVSTR2_S17_MASK ) )
488#define GR740_IOPLL_DRVSTR2_S17( _val ) \
489 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S17_SHIFT ) & \
490 GR740_IOPLL_DRVSTR2_S17_MASK )
491
492#define GR740_IOPLL_DRVSTR2_S16_SHIFT 12
493#define GR740_IOPLL_DRVSTR2_S16_MASK 0x3000U
494#define GR740_IOPLL_DRVSTR2_S16_GET( _reg ) \
495 ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S16_MASK ) >> \
496 GR740_IOPLL_DRVSTR2_S16_SHIFT )
497#define GR740_IOPLL_DRVSTR2_S16_SET( _reg, _val ) \
498 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S16_MASK ) | \
499 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S16_SHIFT ) & \
500 GR740_IOPLL_DRVSTR2_S16_MASK ) )
501#define GR740_IOPLL_DRVSTR2_S16( _val ) \
502 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S16_SHIFT ) & \
503 GR740_IOPLL_DRVSTR2_S16_MASK )
504
505#define GR740_IOPLL_DRVSTR2_S15_SHIFT 10
506#define GR740_IOPLL_DRVSTR2_S15_MASK 0xc00U
507#define GR740_IOPLL_DRVSTR2_S15_GET( _reg ) \
508 ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S15_MASK ) >> \
509 GR740_IOPLL_DRVSTR2_S15_SHIFT )
510#define GR740_IOPLL_DRVSTR2_S15_SET( _reg, _val ) \
511 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S15_MASK ) | \
512 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S15_SHIFT ) & \
513 GR740_IOPLL_DRVSTR2_S15_MASK ) )
514#define GR740_IOPLL_DRVSTR2_S15( _val ) \
515 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S15_SHIFT ) & \
516 GR740_IOPLL_DRVSTR2_S15_MASK )
517
518#define GR740_IOPLL_DRVSTR2_S14_SHIFT 8
519#define GR740_IOPLL_DRVSTR2_S14_MASK 0x300U
520#define GR740_IOPLL_DRVSTR2_S14_GET( _reg ) \
521 ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S14_MASK ) >> \
522 GR740_IOPLL_DRVSTR2_S14_SHIFT )
523#define GR740_IOPLL_DRVSTR2_S14_SET( _reg, _val ) \
524 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S14_MASK ) | \
525 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S14_SHIFT ) & \
526 GR740_IOPLL_DRVSTR2_S14_MASK ) )
527#define GR740_IOPLL_DRVSTR2_S14( _val ) \
528 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S14_SHIFT ) & \
529 GR740_IOPLL_DRVSTR2_S14_MASK )
530
531#define GR740_IOPLL_DRVSTR2_S13_SHIFT 6
532#define GR740_IOPLL_DRVSTR2_S13_MASK 0xc0U
533#define GR740_IOPLL_DRVSTR2_S13_GET( _reg ) \
534 ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S13_MASK ) >> \
535 GR740_IOPLL_DRVSTR2_S13_SHIFT )
536#define GR740_IOPLL_DRVSTR2_S13_SET( _reg, _val ) \
537 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S13_MASK ) | \
538 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S13_SHIFT ) & \
539 GR740_IOPLL_DRVSTR2_S13_MASK ) )
540#define GR740_IOPLL_DRVSTR2_S13( _val ) \
541 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S13_SHIFT ) & \
542 GR740_IOPLL_DRVSTR2_S13_MASK )
543
544#define GR740_IOPLL_DRVSTR2_S12_SHIFT 4
545#define GR740_IOPLL_DRVSTR2_S12_MASK 0x30U
546#define GR740_IOPLL_DRVSTR2_S12_GET( _reg ) \
547 ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S12_MASK ) >> \
548 GR740_IOPLL_DRVSTR2_S12_SHIFT )
549#define GR740_IOPLL_DRVSTR2_S12_SET( _reg, _val ) \
550 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S12_MASK ) | \
551 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S12_SHIFT ) & \
552 GR740_IOPLL_DRVSTR2_S12_MASK ) )
553#define GR740_IOPLL_DRVSTR2_S12( _val ) \
554 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S12_SHIFT ) & \
555 GR740_IOPLL_DRVSTR2_S12_MASK )
556
557#define GR740_IOPLL_DRVSTR2_S11_SHIFT 2
558#define GR740_IOPLL_DRVSTR2_S11_MASK 0xcU
559#define GR740_IOPLL_DRVSTR2_S11_GET( _reg ) \
560 ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S11_MASK ) >> \
561 GR740_IOPLL_DRVSTR2_S11_SHIFT )
562#define GR740_IOPLL_DRVSTR2_S11_SET( _reg, _val ) \
563 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S11_MASK ) | \
564 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S11_SHIFT ) & \
565 GR740_IOPLL_DRVSTR2_S11_MASK ) )
566#define GR740_IOPLL_DRVSTR2_S11( _val ) \
567 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S11_SHIFT ) & \
568 GR740_IOPLL_DRVSTR2_S11_MASK )
569
570#define GR740_IOPLL_DRVSTR2_S10_SHIFT 0
571#define GR740_IOPLL_DRVSTR2_S10_MASK 0x3U
572#define GR740_IOPLL_DRVSTR2_S10_GET( _reg ) \
573 ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S10_MASK ) >> \
574 GR740_IOPLL_DRVSTR2_S10_SHIFT )
575#define GR740_IOPLL_DRVSTR2_S10_SET( _reg, _val ) \
576 ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S10_MASK ) | \
577 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S10_SHIFT ) & \
578 GR740_IOPLL_DRVSTR2_S10_MASK ) )
579#define GR740_IOPLL_DRVSTR2_S10( _val ) \
580 ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S10_SHIFT ) & \
581 GR740_IOPLL_DRVSTR2_S10_MASK )
582
584
593
594#define GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT 16
595#define GR740_IOPLL_LOCKDOWN_PERMANENT_MASK 0xff0000U
596#define GR740_IOPLL_LOCKDOWN_PERMANENT_GET( _reg ) \
597 ( ( ( _reg ) & GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) >> \
598 GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT )
599#define GR740_IOPLL_LOCKDOWN_PERMANENT_SET( _reg, _val ) \
600 ( ( ( _reg ) & ~GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) | \
601 ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT ) & \
602 GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) )
603#define GR740_IOPLL_LOCKDOWN_PERMANENT( _val ) \
604 ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT ) & \
605 GR740_IOPLL_LOCKDOWN_PERMANENT_MASK )
606
607#define GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT 0
608#define GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK 0xffU
609#define GR740_IOPLL_LOCKDOWN_REVOCABLE_GET( _reg ) \
610 ( ( ( _reg ) & GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) >> \
611 GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT )
612#define GR740_IOPLL_LOCKDOWN_REVOCABLE_SET( _reg, _val ) \
613 ( ( ( _reg ) & ~GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) | \
614 ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT ) & \
615 GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) )
616#define GR740_IOPLL_LOCKDOWN_REVOCABLE( _val ) \
617 ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT ) & \
618 GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK )
619
621
626typedef struct gr740_iopll {
630 uint32_t ftmfunc;
631
635 uint32_t altfunc;
636
640 uint32_t lvdsmclk;
641
645 uint32_t pllnewcfg;
646
650 uint32_t pllrecfg;
651
655 uint32_t pllcurcfg;
656
660 uint32_t drvstr1;
661
665 uint32_t drvstr2;
666
670 uint32_t lockdown;
671} gr740_iopll;
672
674
675#ifdef __cplusplus
676}
677#endif
678
679#endif /* _BSP_GR740_IOPLL_REGS_H */
gr740_iopll
This structure defines the GR740 I/0 and PLL Configuration register block memory map.
Definition gr740-iopll-regs.h:626
gr740_iopll::drvstr1
uint32_t drvstr1
See Drive strength configuration register 1 (DRVSTR1).
Definition gr740-iopll-regs.h:660
gr740_iopll::pllnewcfg
uint32_t pllnewcfg
See PLL new configuration register (PLLNEWCFG).
Definition gr740-iopll-regs.h:645
gr740_iopll::pllrecfg
uint32_t pllrecfg
See PLL reconfigure command register (PLLRECFG).
Definition gr740-iopll-regs.h:650
gr740_iopll::lockdown
uint32_t lockdown
See Configuration lockdown register (LOCKDOWN).
Definition gr740-iopll-regs.h:670
gr740_iopll::pllcurcfg
uint32_t pllcurcfg
See PLL current configuration register (PLLCURCFG).
Definition gr740-iopll-regs.h:655
gr740_iopll::lvdsmclk
uint32_t lvdsmclk
See LVDS and memory clock pad enable register (LVDSMCLK).
Definition gr740-iopll-regs.h:640
gr740_iopll::altfunc
uint32_t altfunc
See Alternative function enable register (ALTFUNC).
Definition gr740-iopll-regs.h:635
gr740_iopll::drvstr2
uint32_t drvstr2
See Drive strength configuration register 2 (DRVSTR2).
Definition gr740-iopll-regs.h:665
gr740_iopll::ftmfunc
uint32_t ftmfunc
See FTMCTRL function enable register (FTMFUNC).
Definition gr740-iopll-regs.h:630
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