arm-pl111-regs.h File Reference

ARM PL111 Register definitions. More...

#include <bsp/utility.h>

Go to the source code of this file.

Data Structures
struct	pl111_lcd
struct	pl111_crsr
struct	pl111

Macros
#define	PL111_LCD_TIMING0_PPL(val)
#define	PL111_LCD_TIMING0_PPL_GET(reg)
#define	PL111_LCD_TIMING0_PPL_SET(reg, val)
#define	PL111_LCD_TIMING0_HSW(val)
#define	PL111_LCD_TIMING0_HSW_GET(reg)
#define	PL111_LCD_TIMING0_HSW_SET(reg, val)
#define	PL111_LCD_TIMING0_HFP(val)
#define	PL111_LCD_TIMING0_HFP_GET(reg)
#define	PL111_LCD_TIMING0_HFP_SET(reg, val)
#define	PL111_LCD_TIMING0_HBP(val)
#define	PL111_LCD_TIMING0_HBP_GET(reg)
#define	PL111_LCD_TIMING0_HBP_SET(reg, val)
#define	PL111_LCD_TIMING1_LPP(val)
#define	PL111_LCD_TIMING1_LPP_GET(reg)
#define	PL111_LCD_TIMING1_LPP_SET(reg, val)
#define	PL111_LCD_TIMING1_VSW(val)
#define	PL111_LCD_TIMING1_VSW_GET(reg)
#define	PL111_LCD_TIMING1_VSW_SET(reg, val)
#define	PL111_LCD_TIMING1_VFP(val)
#define	PL111_LCD_TIMING1_VFP_GET(reg)
#define	PL111_LCD_TIMING1_VFP_SET(reg, val)
#define	PL111_LCD_TIMING1_VBP(val)
#define	PL111_LCD_TIMING1_VBP_GET(reg)
#define	PL111_LCD_TIMING1_VBP_SET(reg, val)
#define	PL111_LCD_TIMING2_PCD_LO(val)
#define	PL111_LCD_TIMING2_PCD_LO_GET(reg)
#define	PL111_LCD_TIMING2_PCD_LO_SET(reg, val)
#define	PL111_LCD_TIMING2_CLKSEL   BSP_BIT32(5)
#define	PL111_LCD_TIMING2_ACB(val)
#define	PL111_LCD_TIMING2_ACB_GET(reg)
#define	PL111_LCD_TIMING2_ACB_SET(reg, val)
#define	PL111_LCD_TIMING2_IVS   BSP_BIT32(11)
#define	PL111_LCD_TIMING2_IHS   BSP_BIT32(12)
#define	PL111_LCD_TIMING2_IPC   BSP_BIT32(13)
#define	PL111_LCD_TIMING2_IOE   BSP_BIT32(14)
#define	PL111_LCD_TIMING2_CPL(val)
#define	PL111_LCD_TIMING2_CPL_GET(reg)
#define	PL111_LCD_TIMING2_CPL_SET(reg, val)
#define	PL111_LCD_TIMING2_BCD   BSP_BIT32(26)
#define	PL111_LCD_TIMING2_PCD_HI(val)
#define	PL111_LCD_TIMING2_PCD_HI_GET(reg)
#define	PL111_LCD_TIMING2_PCD_HI_SET(reg, val)
#define	PL111_LCD_TIMING3_LED(val)
#define	PL111_LCD_TIMING3_LED_GET(reg)
#define	PL111_LCD_TIMING3_LED_SET(reg, val)
#define	PL111_LCD_TIMING3_LEE   BSP_BIT32(16)
#define	PL111_LCD_CONTROL_LCD_EN   BSP_BIT32(0)
#define	PL111_LCD_CONTROL_LCD_BPP(val)
#define	PL111_LCD_CONTROL_LCD_BPP_GET(reg)
#define	PL111_LCD_CONTROL_LCD_BPP_SET(reg, val)
#define	PL111_LCD_CONTROL_LCD_BPP_1   0x00U
#define	PL111_LCD_CONTROL_LCD_BPP_2   0x01U
#define	PL111_LCD_CONTROL_LCD_BPP_4   0x02U
#define	PL111_LCD_CONTROL_LCD_BPP_8   0x03U
#define	PL111_LCD_CONTROL_LCD_BPP_16   0x04U
#define	PL111_LCD_CONTROL_LCD_BPP_24   0x05U
#define	PL111_LCD_CONTROL_LCD_BPP_16_5_6_5   0x06U
#define	PL111_LCD_CONTROL_LCD_BPP_12   0x07U
#define	PL111_LCD_CONTROL_LCD_BW   BSP_BIT32(4)
#define	PL111_LCD_CONTROL_LCD_TFT   BSP_BIT32(5)
#define	PL111_LCD_CONTROL_LCD_MONO8   BSP_BIT32(6)
#define	PL111_LCD_CONTROL_LCD_DUAL   BSP_BIT32(7)
#define	PL111_LCD_CONTROL_BGR   BSP_BIT32(8)
#define	PL111_LCD_CONTROL_BEBO   BSP_BIT32(9)
#define	PL111_LCD_CONTROL_BEPO   BSP_BIT32(10)
#define	PL111_LCD_CONTROL_LCD_PWR   BSP_BIT32(11)
#define	PL111_LCD_CONTROL_LCD_V_COMP(val)
#define	PL111_LCD_CONTROL_LCD_V_COMP_GET(reg)
#define	PL111_LCD_CONTROL_LCD_V_COMP_SET(reg, val)
#define	PL111_LCD_CONTROL_WATERMARK   BSP_BIT32(16)
#define	PL111_LCD_I_FUF   BSP_BIT32(1)
#define	PL111_LCD_I_LNBU   BSP_BIT32(2)
#define	PL111_LCD_I_VCOMP   BSP_BIT32(3)
#define	PL111_LCD_I_MBERROR   BSP_BIT32(4)
#define	PL111_LCD_PAL_R(val)
#define	PL111_LCD_PAL_R_GET(reg)
#define	PL111_LCD_PAL_R_SET(reg, val)
#define	PL111_LCD_PAL_G(val)
#define	PL111_LCD_PAL_G_GET(reg)
#define	PL111_LCD_PAL_G_SET(reg, val)
#define	PL111_LCD_PAL_B(val)
#define	PL111_LCD_PAL_B_GET(reg)
#define	PL111_LCD_PAL_B_SET(reg, val)
#define	PL111_LCD_PAL_I   BSP_BIT16(15)
#define	PL111_CRSR_CTRL_ON   BSP_BIT32(0)
#define	PL111_CRSR_CTRL_NUMBER(val)
#define	PL111_CRSR_CTRL_NUMBER_GET(reg)
#define	PL111_CRSR_CTRL_NUMBER_SET(reg, val)
#define	PL111_CRSR_CONFIG_SIZE   BSP_BIT32(0)
#define	PL111_CRSR_CONFIG_FRAME_SYNC   BSP_BIT32(1)
#define	PL111_CRSR_PALETTE_RED(val)
#define	PL111_CRSR_PALETTE_RED_GET(reg)
#define	PL111_CRSR_PALETTE_RED_SET(reg, val)
#define	PL111_CRSR_PALETTE_GREEN(val)
#define	PL111_CRSR_PALETTE_GREEN_GET(reg)
#define	PL111_CRSR_PALETTE_GREEN_SET(reg, val)
#define	PL111_CRSR_PALETTE_BLUE(val)
#define	PL111_CRSR_PALETTE_BLUE_GET(reg)
#define	PL111_CRSR_PALETTE_BLUE_SET(reg, val)
#define	PL111_CRSR_XY_X(val)
#define	PL111_CRSR_XY_X_GET(reg)
#define	PL111_CRSR_XY_X_SET(reg, val)
#define	PL111_CRSR_XY_X_EXP(val)
#define	PL111_CRSR_XY_X_EXP_GET(reg)
#define	PL111_CRSR_XY_X_EXP_SET(reg, val)
#define	PL111_CRSR_XY_Y(val)
#define	PL111_CRSR_XY_Y_GET(reg)
#define	PL111_CRSR_XY_Y_SET(reg, val)
#define	PL111_CRSR_XY_Y_EXP(val)
#define	PL111_CRSR_XY_Y_EXP_GET(reg)
#define	PL111_CRSR_XY_Y_EXP_SET(reg, val)
#define	PL111_CRSR_CLIP_X(val)
#define	PL111_CRSR_CLIP_X_GET(reg)
#define	PL111_CRSR_CLIP_X_SET(reg, val)
#define	PL111_CRSR_CLIP_Y(val)
#define	PL111_CRSR_CLIP_Y_GET(reg)
#define	PL111_CRSR_CLIP_Y_SET(reg, val)
#define	PL111_CRSR_I_CRSR   BSP_BIT32(0)

Detailed Description

ARM PL111 Register definitions.

Macro Definition Documentation

PL111_CRSR_CLIP_X

#define PL111_CRSR_CLIP_X

(

val

)

Value:

BSP_FLD32(val, 0, 5)

PL111_CRSR_CLIP_X_GET

#define PL111_CRSR_CLIP_X_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 5)

PL111_CRSR_CLIP_X_SET

#define PL111_CRSR_CLIP_X_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 5)

PL111_CRSR_CLIP_Y

#define PL111_CRSR_CLIP_Y

(

val

)

Value:

BSP_FLD32(val, 8, 13)

PL111_CRSR_CLIP_Y_GET

#define PL111_CRSR_CLIP_Y_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 8, 13)

PL111_CRSR_CLIP_Y_SET

#define PL111_CRSR_CLIP_Y_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 8, 13)

PL111_CRSR_CTRL_NUMBER

#define PL111_CRSR_CTRL_NUMBER

(

val

)

Value:

BSP_FLD32(val, 4, 5)

PL111_CRSR_CTRL_NUMBER_GET

#define PL111_CRSR_CTRL_NUMBER_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 4, 5)

PL111_CRSR_CTRL_NUMBER_SET

#define PL111_CRSR_CTRL_NUMBER_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 4, 5)

PL111_CRSR_PALETTE_BLUE

#define PL111_CRSR_PALETTE_BLUE

(

val

)

Value:

BSP_FLD32(val, 16, 23)

PL111_CRSR_PALETTE_BLUE_GET

#define PL111_CRSR_PALETTE_BLUE_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 16, 23)

PL111_CRSR_PALETTE_BLUE_SET

#define PL111_CRSR_PALETTE_BLUE_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 16, 23)

PL111_CRSR_PALETTE_GREEN

#define PL111_CRSR_PALETTE_GREEN

(

val

)

Value:

BSP_FLD32(val, 8, 15)

PL111_CRSR_PALETTE_GREEN_GET

#define PL111_CRSR_PALETTE_GREEN_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 8, 15)

PL111_CRSR_PALETTE_GREEN_SET

#define PL111_CRSR_PALETTE_GREEN_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 8, 15)

PL111_CRSR_PALETTE_RED

#define PL111_CRSR_PALETTE_RED

(

val

)

Value:

BSP_FLD32(val, 0, 7)

PL111_CRSR_PALETTE_RED_GET

#define PL111_CRSR_PALETTE_RED_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 7)

PL111_CRSR_PALETTE_RED_SET

#define PL111_CRSR_PALETTE_RED_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 7)

PL111_CRSR_XY_X

#define PL111_CRSR_XY_X

(

val

)

Value:

BSP_FLD32(val, 0, 9)

PL111_CRSR_XY_X_EXP

#define PL111_CRSR_XY_X_EXP

(

val

)

Value:

BSP_FLD32(val, 10, 11)

PL111_CRSR_XY_X_EXP_GET

#define PL111_CRSR_XY_X_EXP_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 10, 11)

PL111_CRSR_XY_X_EXP_SET

#define PL111_CRSR_XY_X_EXP_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 10, 11)

PL111_CRSR_XY_X_GET

#define PL111_CRSR_XY_X_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 9)

PL111_CRSR_XY_X_SET

#define PL111_CRSR_XY_X_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 9)

PL111_CRSR_XY_Y

#define PL111_CRSR_XY_Y

(

val

)

Value:

BSP_FLD32(val, 16, 25)

PL111_CRSR_XY_Y_EXP

#define PL111_CRSR_XY_Y_EXP

(

val

)

Value:

BSP_FLD32(val, 25, 27)

PL111_CRSR_XY_Y_EXP_GET

#define PL111_CRSR_XY_Y_EXP_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 25, 27)

PL111_CRSR_XY_Y_EXP_SET

#define PL111_CRSR_XY_Y_EXP_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 25, 27)

PL111_CRSR_XY_Y_GET

#define PL111_CRSR_XY_Y_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 16, 25)

PL111_CRSR_XY_Y_SET

#define PL111_CRSR_XY_Y_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 16, 25)

PL111_LCD_CONTROL_LCD_BPP

#define PL111_LCD_CONTROL_LCD_BPP

(

val

)

Value:

BSP_FLD32(val, 1, 3)

PL111_LCD_CONTROL_LCD_BPP_GET

#define PL111_LCD_CONTROL_LCD_BPP_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 1, 3)

PL111_LCD_CONTROL_LCD_BPP_SET

#define PL111_LCD_CONTROL_LCD_BPP_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 1, 3)

PL111_LCD_CONTROL_LCD_V_COMP

#define PL111_LCD_CONTROL_LCD_V_COMP

(

val

)

Value:

BSP_FLD32(val, 12, 13)

PL111_LCD_CONTROL_LCD_V_COMP_GET

#define PL111_LCD_CONTROL_LCD_V_COMP_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 12, 13)

PL111_LCD_CONTROL_LCD_V_COMP_SET

#define PL111_LCD_CONTROL_LCD_V_COMP_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 12, 13)

PL111_LCD_PAL_B

#define PL111_LCD_PAL_B

(

val

)

Value:

BSP_FLD16(val, 10, 14)

PL111_LCD_PAL_B_GET

#define PL111_LCD_PAL_B_GET

(

reg

)

Value:

BSP_FLD16GET(reg, 10, 14)

PL111_LCD_PAL_B_SET

#define PL111_LCD_PAL_B_SET	(		reg,
			val )

Value:

BSP_FLD16SET(reg, val, 10, 14)

PL111_LCD_PAL_G

#define PL111_LCD_PAL_G

(

val

)

Value:

BSP_FLD16(val, 5, 9)

PL111_LCD_PAL_G_GET

#define PL111_LCD_PAL_G_GET

(

reg

)

Value:

BSP_FLD16GET(reg, 5, 9)

PL111_LCD_PAL_G_SET

#define PL111_LCD_PAL_G_SET	(		reg,
			val )

Value:

BSP_FLD16SET(reg, val, 5, 9)

PL111_LCD_PAL_R

#define PL111_LCD_PAL_R

(

val

)

Value:

BSP_FLD16(val, 0, 4)

PL111_LCD_PAL_R_GET

#define PL111_LCD_PAL_R_GET

(

reg

)

Value:

BSP_FLD16GET(reg, 0, 4)

PL111_LCD_PAL_R_SET

#define PL111_LCD_PAL_R_SET	(		reg,
			val )

Value:

BSP_FLD16SET(reg, val, 0, 4)

PL111_LCD_TIMING0_HBP

#define PL111_LCD_TIMING0_HBP

(

val

)

Value:

BSP_FLD32(val, 24, 31)

PL111_LCD_TIMING0_HBP_GET

#define PL111_LCD_TIMING0_HBP_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 24, 31)

PL111_LCD_TIMING0_HBP_SET

#define PL111_LCD_TIMING0_HBP_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 24, 31)

PL111_LCD_TIMING0_HFP

#define PL111_LCD_TIMING0_HFP

(

val

)

Value:

BSP_FLD32(val, 16, 23)

PL111_LCD_TIMING0_HFP_GET

#define PL111_LCD_TIMING0_HFP_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 16, 23)

PL111_LCD_TIMING0_HFP_SET

#define PL111_LCD_TIMING0_HFP_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 16, 23)

PL111_LCD_TIMING0_HSW

#define PL111_LCD_TIMING0_HSW

(

val

)

Value:

BSP_FLD32(val, 8, 15)

PL111_LCD_TIMING0_HSW_GET

#define PL111_LCD_TIMING0_HSW_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 8, 15)

PL111_LCD_TIMING0_HSW_SET

#define PL111_LCD_TIMING0_HSW_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 8, 15)

PL111_LCD_TIMING0_PPL

#define PL111_LCD_TIMING0_PPL

(

val

)

Value:

BSP_FLD32(val, 2, 7)

PL111_LCD_TIMING0_PPL_GET

#define PL111_LCD_TIMING0_PPL_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 2, 7)

PL111_LCD_TIMING0_PPL_SET

#define PL111_LCD_TIMING0_PPL_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 2, 7)

PL111_LCD_TIMING1_LPP

#define PL111_LCD_TIMING1_LPP

(

val

)

Value:

BSP_FLD32(val, 0, 9)

PL111_LCD_TIMING1_LPP_GET

#define PL111_LCD_TIMING1_LPP_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 9)

PL111_LCD_TIMING1_LPP_SET

#define PL111_LCD_TIMING1_LPP_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 9)

PL111_LCD_TIMING1_VBP

#define PL111_LCD_TIMING1_VBP

(

val

)

Value:

BSP_FLD32(val, 24, 31)

PL111_LCD_TIMING1_VBP_GET

#define PL111_LCD_TIMING1_VBP_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 24, 31)

PL111_LCD_TIMING1_VBP_SET

#define PL111_LCD_TIMING1_VBP_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 24, 31)

PL111_LCD_TIMING1_VFP

#define PL111_LCD_TIMING1_VFP

(

val

)

Value:

BSP_FLD32(val, 16, 23)

PL111_LCD_TIMING1_VFP_GET

#define PL111_LCD_TIMING1_VFP_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 16, 23)

PL111_LCD_TIMING1_VFP_SET

#define PL111_LCD_TIMING1_VFP_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 16, 23)

PL111_LCD_TIMING1_VSW

#define PL111_LCD_TIMING1_VSW

(

val

)

Value:

BSP_FLD32(val, 10, 15)

PL111_LCD_TIMING1_VSW_GET

#define PL111_LCD_TIMING1_VSW_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 10, 15)

PL111_LCD_TIMING1_VSW_SET

#define PL111_LCD_TIMING1_VSW_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 10, 15)

PL111_LCD_TIMING2_ACB

#define PL111_LCD_TIMING2_ACB

(

val

)

Value:

BSP_FLD32(val, 6, 10)

PL111_LCD_TIMING2_ACB_GET

#define PL111_LCD_TIMING2_ACB_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 6, 10)

PL111_LCD_TIMING2_ACB_SET

#define PL111_LCD_TIMING2_ACB_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 6, 10)

PL111_LCD_TIMING2_CPL

#define PL111_LCD_TIMING2_CPL

(

val

)

Value:

BSP_FLD32(val, 16, 25)

PL111_LCD_TIMING2_CPL_GET

#define PL111_LCD_TIMING2_CPL_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 16, 25)

PL111_LCD_TIMING2_CPL_SET

#define PL111_LCD_TIMING2_CPL_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 16, 25)

PL111_LCD_TIMING2_PCD_HI

#define PL111_LCD_TIMING2_PCD_HI

(

val

)

Value:

BSP_FLD32(val, 27, 31)

PL111_LCD_TIMING2_PCD_HI_GET

#define PL111_LCD_TIMING2_PCD_HI_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 27, 31)

PL111_LCD_TIMING2_PCD_HI_SET

#define PL111_LCD_TIMING2_PCD_HI_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 27, 31)

PL111_LCD_TIMING2_PCD_LO

#define PL111_LCD_TIMING2_PCD_LO

(

val

)

Value:

BSP_FLD32(val, 0, 4)

PL111_LCD_TIMING2_PCD_LO_GET

#define PL111_LCD_TIMING2_PCD_LO_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 4)

PL111_LCD_TIMING2_PCD_LO_SET

#define PL111_LCD_TIMING2_PCD_LO_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 4)

PL111_LCD_TIMING3_LED

#define PL111_LCD_TIMING3_LED

(

val

)

Value:

BSP_FLD32(val, 0, 6)

PL111_LCD_TIMING3_LED_GET

#define PL111_LCD_TIMING3_LED_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 6)

PL111_LCD_TIMING3_LED_SET

#define PL111_LCD_TIMING3_LED_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 6)