arm-pl011-regs.h File Reference

ARM PL011 Register definitions. More...

#include <bsp/utility.h>

Go to the source code of this file.

Data Structures
struct	pl011_base

Macros
#define	PL011_UARTDR_OE   BSP_BIT32(11)
#define	PL011_UARTDR_BE   BSP_BIT32(10)
#define	PL011_UARTDR_PE   BSP_BIT32(9)
#define	PL011_UARTDR_FE   BSP_BIT32(8)
#define	PL011_UARTDR_DATA(val)
#define	PL011_UARTDR_DATA_GET(reg)
#define	PL011_UARTDR_DATA_SET(reg, val)
#define	PL011_UARTRSR_UARTECR_OE   BSP_BIT32(3)
#define	PL011_UARTRSR_UARTECR_BE   BSP_BIT32(2)
#define	PL011_UARTRSR_UARTECR_PE   BSP_BIT32(1)
#define	PL011_UARTRSR_UARTECR_FE   BSP_BIT32(0)
#define	PL011_UARTFR_RI   BSP_BIT32(8)
#define	PL011_UARTFR_TXFE   BSP_BIT32(7)
#define	PL011_UARTFR_RXFF   BSP_BIT32(6)
#define	PL011_UARTFR_TXFF   BSP_BIT32(5)
#define	PL011_UARTFR_RXFE   BSP_BIT32(4)
#define	PL011_UARTFR_BUSY   BSP_BIT32(3)
#define	PL011_UARTFR_DCD   BSP_BIT32(2)
#define	PL011_UARTFR_DSR   BSP_BIT32(1)
#define	PL011_UARTFR_CTS   BSP_BIT32(0)
#define	PL011_UARTILPR_ILPDVSR(val)
#define	PL011_UARTILPR_ILPDVSR_GET(reg)
#define	PL011_UARTILPR_ILPDVSR_SET(reg, val)
#define	PL011_UARTIBRD_BAUD_DIVINT_WIDTH   16
#define	PL011_UARTIBRD_BAUD_DIVINT_MASK   BSP_MSK32(0, PL011_UARTIBRD_BAUD_DIVINT_WIDTH - 1)
#define	PL011_UARTIBRD_BAUD_DIVINT(val)
#define	PL011_UARTIBRD_BAUD_DIVINT_GET(reg)
#define	PL011_UARTIBRD_BAUD_DIVINT_SET(reg, val)
#define	PL011_UARTFBRD_BAUD_DIVFRAC_WIDTH   6
#define	PL011_UARTFBRD_BAUD_DIVFRAC_MASK   BSP_MSK32(0, PL011_UARTFBRD_BAUD_DIVFRAC_WIDTH - 1)
#define	PL011_UARTFBRD_BAUD_DIVFRAC(val)
#define	PL011_UARTFBRD_BAUD_DIVFRAC_GET(reg)
#define	PL011_UARTFBRD_BAUD_DIVFRAC_SET(reg, val)
#define	PL011_UARTLCR_H_SPS   BSP_BIT32(7)
#define	PL011_UARTLCR_H_WLEN(val)
#define	PL011_UARTLCR_H_WLEN_GET(reg)
#define	PL011_UARTLCR_H_WLEN_SET(reg, val)
#define	PL011_UARTLCR_H_WLEN_5   0x00U
#define	PL011_UARTLCR_H_WLEN_6   0x01U
#define	PL011_UARTLCR_H_WLEN_7   0x02U
#define	PL011_UARTLCR_H_WLEN_8   0x03U
#define	PL011_UARTLCR_H_FEN   BSP_BIT32(4)
#define	PL011_UARTLCR_H_STP2   BSP_BIT32(3)
#define	PL011_UARTLCR_H_EPS   BSP_BIT32(2)
#define	PL011_UARTLCR_H_PEN   BSP_BIT32(1)
#define	PL011_UARTLCR_H_BRK   BSP_BIT32(0)
#define	PL011_UARTCR_CTSEN   BSP_BIT32(15)
#define	PL011_UARTCR_RTSEN   BSP_BIT32(14)
#define	PL011_UARTCR_OUT2   BSP_BIT32(13)
#define	PL011_UARTCR_OUT1   BSP_BIT32(12)
#define	PL011_UARTCR_RTS   BSP_BIT32(11)
#define	PL011_UARTCR_DTR   BSP_BIT32(10)
#define	PL011_UARTCR_RXE   BSP_BIT32(9)
#define	PL011_UARTCR_TXE   BSP_BIT32(8)
#define	PL011_UARTCR_LBE   BSP_BIT32(7)
#define	PL011_UARTCR_SIRLP   BSP_BIT32(2)
#define	PL011_UARTCR_SIREN   BSP_BIT32(1)
#define	PL011_UARTCR_UARTEN   BSP_BIT32(0)
#define	PL011_UARTIFLS_RXIFLSEL(val)
#define	PL011_UARTIFLS_RXIFLSEL_GET(reg)
#define	PL011_UARTIFLS_RXIFLSEL_SET(reg, val)
#define	PL011_UARTIFLS_TXIFLSEL(val)
#define	PL011_UARTIFLS_TXIFLSEL_GET(reg)
#define	PL011_UARTIFLS_TXIFLSEL_SET(reg, val)
#define	PL011_UARTI_OEI   BSP_BIT32(10)
#define	PL011_UARTI_BEI   BSP_BIT32(9)
#define	PL011_UARTI_PEI   BSP_BIT32(8)
#define	PL011_UARTI_FEI   BSP_BIT32(7)
#define	PL011_UARTI_RTI   BSP_BIT32(6)
#define	PL011_UARTI_TXI   BSP_BIT32(5)
#define	PL011_UARTI_RXI   BSP_BIT32(4)
#define	PL011_UARTI_DSRMI   BSP_BIT32(3)
#define	PL011_UARTI_DCDMI   BSP_BIT32(2)
#define	PL011_UARTI_CTSMI   BSP_BIT32(1)
#define	PL011_UARTI_RIMI   BSP_BIT32(0)
#define	PL011_UARTI_MASK   BSP_MSK32(0, 10)
#define	PL011_UARTDMACR_DMAONERR   BSP_BIT32(2)
#define	PL011_UARTDMACR_TXDMAE   BSP_BIT32(1)
#define	PL011_UARTDMACR_RXDMAE   BSP_BIT32(0)

Detailed Description

ARM PL011 Register definitions.

Macro Definition Documentation

PL011_UARTDR_DATA

#define PL011_UARTDR_DATA

(

val

)

Value:

BSP_FLD32(val, 0, 7)

PL011_UARTDR_DATA_GET

#define PL011_UARTDR_DATA_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 7)

PL011_UARTDR_DATA_SET

#define PL011_UARTDR_DATA_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 7)

PL011_UARTFBRD_BAUD_DIVFRAC

#define PL011_UARTFBRD_BAUD_DIVFRAC

(

val

)

Value:

BSP_FLD32(val, 0, 5)

PL011_UARTFBRD_BAUD_DIVFRAC_GET

#define PL011_UARTFBRD_BAUD_DIVFRAC_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 5)

PL011_UARTFBRD_BAUD_DIVFRAC_SET

#define PL011_UARTFBRD_BAUD_DIVFRAC_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 5)

PL011_UARTIBRD_BAUD_DIVINT

#define PL011_UARTIBRD_BAUD_DIVINT

(

val

)

Value:

BSP_FLD32(val, 0, 15)

PL011_UARTIBRD_BAUD_DIVINT_GET

#define PL011_UARTIBRD_BAUD_DIVINT_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 15)

PL011_UARTIBRD_BAUD_DIVINT_SET

#define PL011_UARTIBRD_BAUD_DIVINT_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 15)

PL011_UARTIFLS_RXIFLSEL

#define PL011_UARTIFLS_RXIFLSEL

(

val

)

Value:

BSP_FLD32(val, 3, 5)

PL011_UARTIFLS_RXIFLSEL_GET

#define PL011_UARTIFLS_RXIFLSEL_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 3, 5)

PL011_UARTIFLS_RXIFLSEL_SET

#define PL011_UARTIFLS_RXIFLSEL_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 3, 5)

PL011_UARTIFLS_TXIFLSEL

#define PL011_UARTIFLS_TXIFLSEL

(

val

)

Value:

BSP_FLD32(val, 0, 2)

PL011_UARTIFLS_TXIFLSEL_GET

#define PL011_UARTIFLS_TXIFLSEL_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 2)

PL011_UARTIFLS_TXIFLSEL_SET

#define PL011_UARTIFLS_TXIFLSEL_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 2)

PL011_UARTILPR_ILPDVSR

#define PL011_UARTILPR_ILPDVSR

(

val

)

Value:

BSP_FLD32(val, 0, 7)

PL011_UARTILPR_ILPDVSR_GET

#define PL011_UARTILPR_ILPDVSR_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 7)

PL011_UARTILPR_ILPDVSR_SET

#define PL011_UARTILPR_ILPDVSR_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 7)

PL011_UARTLCR_H_WLEN

#define PL011_UARTLCR_H_WLEN

(

val

)

Value:

BSP_FLD32(val, 5, 6)

PL011_UARTLCR_H_WLEN_GET

#define PL011_UARTLCR_H_WLEN_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 5, 6)

PL011_UARTLCR_H_WLEN_SET

#define PL011_UARTLCR_H_WLEN_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 5, 6)