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bsps
arm
altera-cyclone-v
include
bsp
socal
alt_rstmgr.h
Go to the documentation of this file.
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/*******************************************************************************
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* *
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* Copyright 2013 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. The name of the author may not be used to endorse or promote products *
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* derived from this software without specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
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* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
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* *
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*******************************************************************************/
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/* Altera - ALT_RSTMGR */
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#ifndef __ALTERA_ALT_RSTMGR_H__
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#define __ALTERA_ALT_RSTMGR_H__
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#ifdef __cplusplus
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extern
"C"
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{
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#endif
/* __cplusplus */
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/*
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* Component : Reset Manager Module - ALT_RSTMGR
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* Reset Manager Module
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*
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* Registers in the Reset Manager module
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*
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*/
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/*
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* Register : Status Register - stat
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*
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* The STAT register contains bits that indicate the reset source or a timeout
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* event. For reset sources, a field is 1 if its associated reset requester caused
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* the reset. For timeout events, a field is 1 if its associated timeout occured as
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* part of a hardware sequenced warm/debug reset.
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*
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* Software clears bits by writing them with a value of 1. Writes to bits with a
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* value of 0 are ignored.
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*
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* After a cold reset is complete, all bits are reset to their reset value except
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* for the bit(s) that indicate the source of the cold reset. If multiple cold
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* reset requests overlap with each other, the source de-asserts the request last
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* will be logged. The other reset request source(s) de-assert the request in the
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* same cycle will also be logged, the rest of the fields are reset to default
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* value of 0.
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*
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* After a warm reset is complete, the bit(s) that indicate the source of the warm
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* reset are set to 1. A warm reset doesn't clear any of the bits in the STAT
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* register; these bits must be cleared by software writing the STAT register.
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*
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* Register Layout
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*
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* Bits | Access | Reset | Description
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* :--------|:-------|:------|:-------------------------------------
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* [0] | RW | 0x0 | Power-On Voltage Detector Cold Reset
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* [1] | RW | 0x0 | nPOR Pin Cold Reset
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* [2] | RW | 0x0 | FPGA Core Cold Reset
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* [3] | RW | 0x0 | CONFIG_IO Cold Reset
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* [4] | RW | 0x0 | Software Cold Reset
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* [7:5] | ??? | 0x0 | *UNDEFINED*
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* [8] | RW | 0x0 | nRST Pin Warm Reset
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* [9] | RW | 0x0 | FPGA Core Warm Reset
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* [10] | RW | 0x0 | Software Warm Reset
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* [11] | ??? | 0x0 | *UNDEFINED*
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* [12] | RW | 0x0 | MPU Watchdog 0 Warm Reset
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* [13] | RW | 0x0 | MPU Watchdog 1 Warm Reset
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* [14] | RW | 0x0 | L4 Watchdog 0 Warm Reset
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* [15] | RW | 0x0 | L4 Watchdog 1 Warm Reset
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* [17:16] | ??? | 0x0 | *UNDEFINED*
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* [18] | RW | 0x0 | FPGA Core Debug Reset
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* [19] | RW | 0x0 | DAP Debug Reset
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* [23:20] | ??? | 0x0 | *UNDEFINED*
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* [24] | RW | 0x0 | SDRAM Self-Refresh Timeout
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* [25] | RW | 0x0 | FPGA manager handshake Timeout
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* [26] | RW | 0x0 | SCAN manager handshake Timeout
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* [27] | RW | 0x0 | FPGA handshake Timeout
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* [28] | RW | 0x0 | ETR Stall Timeout
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* [31:29] | ??? | 0x0 | *UNDEFINED*
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*
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*/
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/*
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* Field : Power-On Voltage Detector Cold Reset - porvoltrst
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*
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* Built-in POR voltage detector triggered a cold reset (por_voltage_req = 1)
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*
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* Field Access Macros:
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*
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*/
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/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
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#define ALT_RSTMGR_STAT_PORVOLTRST_LSB 0
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/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
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#define ALT_RSTMGR_STAT_PORVOLTRST_MSB 0
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/* The width in bits of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
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#define ALT_RSTMGR_STAT_PORVOLTRST_WIDTH 1
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/* The mask used to set the ALT_RSTMGR_STAT_PORVOLTRST register field value. */
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#define ALT_RSTMGR_STAT_PORVOLTRST_SET_MSK 0x00000001
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/* The mask used to clear the ALT_RSTMGR_STAT_PORVOLTRST register field value. */
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#define ALT_RSTMGR_STAT_PORVOLTRST_CLR_MSK 0xfffffffe
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/* The reset value of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
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#define ALT_RSTMGR_STAT_PORVOLTRST_RESET 0x0
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/* Extracts the ALT_RSTMGR_STAT_PORVOLTRST field value from a register. */
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#define ALT_RSTMGR_STAT_PORVOLTRST_GET(value) (((value) & 0x00000001) >> 0)
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/* Produces a ALT_RSTMGR_STAT_PORVOLTRST register field value suitable for setting the register. */
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#define ALT_RSTMGR_STAT_PORVOLTRST_SET(value) (((value) << 0) & 0x00000001)
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/*
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* Field : nPOR Pin Cold Reset - nporpinrst
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*
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* nPOR pin triggered a cold reset (por_pin_req = 1)
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*
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* Field Access Macros:
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*
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*/
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/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */
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#define ALT_RSTMGR_STAT_NPORPINRST_LSB 1
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/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */
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#define ALT_RSTMGR_STAT_NPORPINRST_MSB 1
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/* The width in bits of the ALT_RSTMGR_STAT_NPORPINRST register field. */
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#define ALT_RSTMGR_STAT_NPORPINRST_WIDTH 1
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/* The mask used to set the ALT_RSTMGR_STAT_NPORPINRST register field value. */
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#define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK 0x00000002
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/* The mask used to clear the ALT_RSTMGR_STAT_NPORPINRST register field value. */
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#define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK 0xfffffffd
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/* The reset value of the ALT_RSTMGR_STAT_NPORPINRST register field. */
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#define ALT_RSTMGR_STAT_NPORPINRST_RESET 0x0
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/* Extracts the ALT_RSTMGR_STAT_NPORPINRST field value from a register. */
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#define ALT_RSTMGR_STAT_NPORPINRST_GET(value) (((value) & 0x00000002) >> 1)
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/* Produces a ALT_RSTMGR_STAT_NPORPINRST register field value suitable for setting the register. */
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#define ALT_RSTMGR_STAT_NPORPINRST_SET(value) (((value) << 1) & 0x00000002)
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/*
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* Field : FPGA Core Cold Reset - fpgacoldrst
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*
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* FPGA core triggered a cold reset (f2h_cold_rst_req_n = 1)
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*
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* Field Access Macros:
162
*
163
*/
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/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
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#define ALT_RSTMGR_STAT_FPGACOLDRST_LSB 2
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/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
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#define ALT_RSTMGR_STAT_FPGACOLDRST_MSB 2
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/* The width in bits of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
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#define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH 1
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/* The mask used to set the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */
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#define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK 0x00000004
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/* The mask used to clear the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */
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#define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK 0xfffffffb
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/* The reset value of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
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#define ALT_RSTMGR_STAT_FPGACOLDRST_RESET 0x0
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/* Extracts the ALT_RSTMGR_STAT_FPGACOLDRST field value from a register. */
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#define ALT_RSTMGR_STAT_FPGACOLDRST_GET(value) (((value) & 0x00000004) >> 2)
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/* Produces a ALT_RSTMGR_STAT_FPGACOLDRST register field value suitable for setting the register. */
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#define ALT_RSTMGR_STAT_FPGACOLDRST_SET(value) (((value) << 2) & 0x00000004)
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/*
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* Field : CONFIG_IO Cold Reset - configiocoldrst
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*
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* FPGA entered CONFIG_IO mode and a triggered a cold reset
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*
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* Field Access Macros:
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*
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*/
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/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB 3
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/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB 3
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/* The width in bits of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH 1
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/* The mask used to set the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK 0x00000008
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/* The mask used to clear the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK 0xfffffff7
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/* The reset value of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET 0x0
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/* Extracts the ALT_RSTMGR_STAT_CFGIOCOLDRST field value from a register. */
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value) (((value) & 0x00000008) >> 3)
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/* Produces a ALT_RSTMGR_STAT_CFGIOCOLDRST register field value suitable for setting the register. */
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value) (((value) << 3) & 0x00000008)
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/*
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* Field : Software Cold Reset - swcoldrst
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*
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* Software wrote CTRL.SWCOLDRSTREQ to 1 and triggered a cold reset
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*
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* Field Access Macros:
212
*
213
*/
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/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
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#define ALT_RSTMGR_STAT_SWCOLDRST_LSB 4
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/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
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#define ALT_RSTMGR_STAT_SWCOLDRST_MSB 4
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/* The width in bits of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
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#define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH 1
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/* The mask used to set the ALT_RSTMGR_STAT_SWCOLDRST register field value. */
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#define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK 0x00000010
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/* The mask used to clear the ALT_RSTMGR_STAT_SWCOLDRST register field value. */
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#define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK 0xffffffef
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/* The reset value of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
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#define ALT_RSTMGR_STAT_SWCOLDRST_RESET 0x0
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/* Extracts the ALT_RSTMGR_STAT_SWCOLDRST field value from a register. */
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#define ALT_RSTMGR_STAT_SWCOLDRST_GET(value) (((value) & 0x00000010) >> 4)
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/* Produces a ALT_RSTMGR_STAT_SWCOLDRST register field value suitable for setting the register. */
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#define ALT_RSTMGR_STAT_SWCOLDRST_SET(value) (((value) << 4) & 0x00000010)
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/*
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* Field : nRST Pin Warm Reset - nrstpinrst
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*
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* nRST pin triggered a hardware sequenced warm reset
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*
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* Field Access Macros:
237
*
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*/
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/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
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#define ALT_RSTMGR_STAT_NRSTPINRST_LSB 8
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/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
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#define ALT_RSTMGR_STAT_NRSTPINRST_MSB 8
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/* The width in bits of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
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#define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH 1
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/* The mask used to set the ALT_RSTMGR_STAT_NRSTPINRST register field value. */
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#define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK 0x00000100
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/* The mask used to clear the ALT_RSTMGR_STAT_NRSTPINRST register field value. */
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#define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK 0xfffffeff
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/* The reset value of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
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#define ALT_RSTMGR_STAT_NRSTPINRST_RESET 0x0
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/* Extracts the ALT_RSTMGR_STAT_NRSTPINRST field value from a register. */
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#define ALT_RSTMGR_STAT_NRSTPINRST_GET(value) (((value) & 0x00000100) >> 8)
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/* Produces a ALT_RSTMGR_STAT_NRSTPINRST register field value suitable for setting the register. */
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#define ALT_RSTMGR_STAT_NRSTPINRST_SET(value) (((value) << 8) & 0x00000100)
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/*
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* Field : FPGA Core Warm Reset - fpgawarmrst
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*
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* FPGA core triggered a hardware sequenced warm reset (f2h_warm_rst_req_n = 1)
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*
261
* Field Access Macros:
262
*
263
*/
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/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
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#define ALT_RSTMGR_STAT_FPGAWARMRST_LSB 9
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/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
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#define ALT_RSTMGR_STAT_FPGAWARMRST_MSB 9
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/* The width in bits of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
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#define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH 1
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/* The mask used to set the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */
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#define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK 0x00000200
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/* The mask used to clear the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */
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#define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK 0xfffffdff
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/* The reset value of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
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#define ALT_RSTMGR_STAT_FPGAWARMRST_RESET 0x0
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/* Extracts the ALT_RSTMGR_STAT_FPGAWARMRST field value from a register. */
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#define ALT_RSTMGR_STAT_FPGAWARMRST_GET(value) (((value) & 0x00000200) >> 9)
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/* Produces a ALT_RSTMGR_STAT_FPGAWARMRST register field value suitable for setting the register. */
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#define ALT_RSTMGR_STAT_FPGAWARMRST_SET(value) (((value) << 9) & 0x00000200)
280
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/*
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* Field : Software Warm Reset - swwarmrst
283
*
284
* Software wrote CTRL.SWWARMRSTREQ to 1 and triggered a hardware sequenced warm
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* reset
286
*
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* Field Access Macros:
288
*
289
*/
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/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */
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#define ALT_RSTMGR_STAT_SWWARMRST_LSB 10
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/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */
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#define ALT_RSTMGR_STAT_SWWARMRST_MSB 10
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/* The width in bits of the ALT_RSTMGR_STAT_SWWARMRST register field. */
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#define ALT_RSTMGR_STAT_SWWARMRST_WIDTH 1
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/* The mask used to set the ALT_RSTMGR_STAT_SWWARMRST register field value. */
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#define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK 0x00000400
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/* The mask used to clear the ALT_RSTMGR_STAT_SWWARMRST register field value. */
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#define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK 0xfffffbff
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/* The reset value of the ALT_RSTMGR_STAT_SWWARMRST register field. */
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#define ALT_RSTMGR_STAT_SWWARMRST_RESET 0x0
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/* Extracts the ALT_RSTMGR_STAT_SWWARMRST field value from a register. */
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#define ALT_RSTMGR_STAT_SWWARMRST_GET(value) (((value) & 0x00000400) >> 10)
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/* Produces a ALT_RSTMGR_STAT_SWWARMRST register field value suitable for setting the register. */
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#define ALT_RSTMGR_STAT_SWWARMRST_SET(value) (((value) << 10) & 0x00000400)
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/*
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* Field : MPU Watchdog 0 Warm Reset - mpuwd0rst
309
*
310
* MPU Watchdog 0 triggered a hardware sequenced warm reset
311
*
312
* Field Access Macros:
313
*
314
*/
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/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
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#define ALT_RSTMGR_STAT_MPUWD0RST_LSB 12
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/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
318
#define ALT_RSTMGR_STAT_MPUWD0RST_MSB 12
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/* The width in bits of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
320
#define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH 1
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/* The mask used to set the ALT_RSTMGR_STAT_MPUWD0RST register field value. */
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#define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK 0x00001000
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/* The mask used to clear the ALT_RSTMGR_STAT_MPUWD0RST register field value. */
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#define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK 0xffffefff
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/* The reset value of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
326
#define ALT_RSTMGR_STAT_MPUWD0RST_RESET 0x0
327
/* Extracts the ALT_RSTMGR_STAT_MPUWD0RST field value from a register. */
328
#define ALT_RSTMGR_STAT_MPUWD0RST_GET(value) (((value) & 0x00001000) >> 12)
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/* Produces a ALT_RSTMGR_STAT_MPUWD0RST register field value suitable for setting the register. */
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#define ALT_RSTMGR_STAT_MPUWD0RST_SET(value) (((value) << 12) & 0x00001000)
331
332
/*
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* Field : MPU Watchdog 1 Warm Reset - mpuwd1rst
334
*
335
* MPU Watchdog 1 triggered a hardware sequenced warm reset
336
*
337
* Field Access Macros:
338
*
339
*/
340
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
341
#define ALT_RSTMGR_STAT_MPUWD1RST_LSB 13
342
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
343
#define ALT_RSTMGR_STAT_MPUWD1RST_MSB 13
344
/* The width in bits of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
345
#define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH 1
346
/* The mask used to set the ALT_RSTMGR_STAT_MPUWD1RST register field value. */
347
#define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK 0x00002000
348
/* The mask used to clear the ALT_RSTMGR_STAT_MPUWD1RST register field value. */
349
#define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK 0xffffdfff
350
/* The reset value of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
351
#define ALT_RSTMGR_STAT_MPUWD1RST_RESET 0x0
352
/* Extracts the ALT_RSTMGR_STAT_MPUWD1RST field value from a register. */
353
#define ALT_RSTMGR_STAT_MPUWD1RST_GET(value) (((value) & 0x00002000) >> 13)
354
/* Produces a ALT_RSTMGR_STAT_MPUWD1RST register field value suitable for setting the register. */
355
#define ALT_RSTMGR_STAT_MPUWD1RST_SET(value) (((value) << 13) & 0x00002000)
356
357
/*
358
* Field : L4 Watchdog 0 Warm Reset - l4wd0rst
359
*
360
* L4 Watchdog 0 triggered a hardware sequenced warm reset
361
*
362
* Field Access Macros:
363
*
364
*/
365
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */
366
#define ALT_RSTMGR_STAT_L4WD0RST_LSB 14
367
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */
368
#define ALT_RSTMGR_STAT_L4WD0RST_MSB 14
369
/* The width in bits of the ALT_RSTMGR_STAT_L4WD0RST register field. */
370
#define ALT_RSTMGR_STAT_L4WD0RST_WIDTH 1
371
/* The mask used to set the ALT_RSTMGR_STAT_L4WD0RST register field value. */
372
#define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK 0x00004000
373
/* The mask used to clear the ALT_RSTMGR_STAT_L4WD0RST register field value. */
374
#define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK 0xffffbfff
375
/* The reset value of the ALT_RSTMGR_STAT_L4WD0RST register field. */
376
#define ALT_RSTMGR_STAT_L4WD0RST_RESET 0x0
377
/* Extracts the ALT_RSTMGR_STAT_L4WD0RST field value from a register. */
378
#define ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00004000) >> 14)
379
/* Produces a ALT_RSTMGR_STAT_L4WD0RST register field value suitable for setting the register. */
380
#define ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 14) & 0x00004000)
381
382
/*
383
* Field : L4 Watchdog 1 Warm Reset - l4wd1rst
384
*
385
* L4 Watchdog 1 triggered a hardware sequenced warm reset
386
*
387
* Field Access Macros:
388
*
389
*/
390
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */
391
#define ALT_RSTMGR_STAT_L4WD1RST_LSB 15
392
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */
393
#define ALT_RSTMGR_STAT_L4WD1RST_MSB 15
394
/* The width in bits of the ALT_RSTMGR_STAT_L4WD1RST register field. */
395
#define ALT_RSTMGR_STAT_L4WD1RST_WIDTH 1
396
/* The mask used to set the ALT_RSTMGR_STAT_L4WD1RST register field value. */
397
#define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK 0x00008000
398
/* The mask used to clear the ALT_RSTMGR_STAT_L4WD1RST register field value. */
399
#define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK 0xffff7fff
400
/* The reset value of the ALT_RSTMGR_STAT_L4WD1RST register field. */
401
#define ALT_RSTMGR_STAT_L4WD1RST_RESET 0x0
402
/* Extracts the ALT_RSTMGR_STAT_L4WD1RST field value from a register. */
403
#define ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00008000) >> 15)
404
/* Produces a ALT_RSTMGR_STAT_L4WD1RST register field value suitable for setting the register. */
405
#define ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 15) & 0x00008000)
406
407
/*
408
* Field : FPGA Core Debug Reset - fpgadbgrst
409
*
410
* FPGA triggered debug reset (f2h_dbg_rst_req_n = 1)
411
*
412
* Field Access Macros:
413
*
414
*/
415
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
416
#define ALT_RSTMGR_STAT_FPGADBGRST_LSB 18
417
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
418
#define ALT_RSTMGR_STAT_FPGADBGRST_MSB 18
419
/* The width in bits of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
420
#define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH 1
421
/* The mask used to set the ALT_RSTMGR_STAT_FPGADBGRST register field value. */
422
#define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK 0x00040000
423
/* The mask used to clear the ALT_RSTMGR_STAT_FPGADBGRST register field value. */
424
#define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK 0xfffbffff
425
/* The reset value of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
426
#define ALT_RSTMGR_STAT_FPGADBGRST_RESET 0x0
427
/* Extracts the ALT_RSTMGR_STAT_FPGADBGRST field value from a register. */
428
#define ALT_RSTMGR_STAT_FPGADBGRST_GET(value) (((value) & 0x00040000) >> 18)
429
/* Produces a ALT_RSTMGR_STAT_FPGADBGRST register field value suitable for setting the register. */
430
#define ALT_RSTMGR_STAT_FPGADBGRST_SET(value) (((value) << 18) & 0x00040000)
431
432
/*
433
* Field : DAP Debug Reset - cdbgreqrst
434
*
435
* DAP triggered debug reset
436
*
437
* Field Access Macros:
438
*
439
*/
440
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
441
#define ALT_RSTMGR_STAT_CDBGREQRST_LSB 19
442
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
443
#define ALT_RSTMGR_STAT_CDBGREQRST_MSB 19
444
/* The width in bits of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
445
#define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH 1
446
/* The mask used to set the ALT_RSTMGR_STAT_CDBGREQRST register field value. */
447
#define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK 0x00080000
448
/* The mask used to clear the ALT_RSTMGR_STAT_CDBGREQRST register field value. */
449
#define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK 0xfff7ffff
450
/* The reset value of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
451
#define ALT_RSTMGR_STAT_CDBGREQRST_RESET 0x0
452
/* Extracts the ALT_RSTMGR_STAT_CDBGREQRST field value from a register. */
453
#define ALT_RSTMGR_STAT_CDBGREQRST_GET(value) (((value) & 0x00080000) >> 19)
454
/* Produces a ALT_RSTMGR_STAT_CDBGREQRST register field value suitable for setting the register. */
455
#define ALT_RSTMGR_STAT_CDBGREQRST_SET(value) (((value) << 19) & 0x00080000)
456
457
/*
458
* Field : SDRAM Self-Refresh Timeout - sdrselfreftimeout
459
*
460
* A 1 indicates that Reset Manager's request to the SDRAM Controller Subsystem to
461
* put the SDRAM devices into self-refresh mode before starting a hardware
462
* sequenced warm reset timed-out and the Reset Manager had to proceed with the
463
* warm reset anyway.
464
*
465
* Field Access Macros:
466
*
467
*/
468
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
469
#define ALT_RSTMGR_STAT_SDRSELFREFTMO_LSB 24
470
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
471
#define ALT_RSTMGR_STAT_SDRSELFREFTMO_MSB 24
472
/* The width in bits of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
473
#define ALT_RSTMGR_STAT_SDRSELFREFTMO_WIDTH 1
474
/* The mask used to set the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */
475
#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET_MSK 0x01000000
476
/* The mask used to clear the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */
477
#define ALT_RSTMGR_STAT_SDRSELFREFTMO_CLR_MSK 0xfeffffff
478
/* The reset value of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
479
#define ALT_RSTMGR_STAT_SDRSELFREFTMO_RESET 0x0
480
/* Extracts the ALT_RSTMGR_STAT_SDRSELFREFTMO field value from a register. */
481
#define ALT_RSTMGR_STAT_SDRSELFREFTMO_GET(value) (((value) & 0x01000000) >> 24)
482
/* Produces a ALT_RSTMGR_STAT_SDRSELFREFTMO register field value suitable for setting the register. */
483
#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET(value) (((value) << 24) & 0x01000000)
484
485
/*
486
* Field : FPGA manager handshake Timeout - fpgamgrhstimeout
487
*
488
* A 1 indicates that Reset Manager's request to the FPGA manager to stop driving
489
* configuration clock to FPGA CB before starting a hardware sequenced warm reset
490
* timed-out and the Reset Manager had to proceed with the warm reset anyway.
491
*
492
* Field Access Macros:
493
*
494
*/
495
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
496
#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_LSB 25
497
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
498
#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_MSB 25
499
/* The width in bits of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
500
#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_WIDTH 1
501
/* The mask used to set the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */
502
#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET_MSK 0x02000000
503
/* The mask used to clear the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */
504
#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_CLR_MSK 0xfdffffff
505
/* The reset value of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
506
#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_RESET 0x0
507
/* Extracts the ALT_RSTMGR_STAT_FPGAMGRHSTMO field value from a register. */
508
#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_GET(value) (((value) & 0x02000000) >> 25)
509
/* Produces a ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value suitable for setting the register. */
510
#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET(value) (((value) << 25) & 0x02000000)
511
512
/*
513
* Field : SCAN manager handshake Timeout - scanhstimeout
514
*
515
* A 1 indicates that Reset Manager's request to the SCAN manager to stop driving
516
* JTAG clock to FPGA CB before starting a hardware sequenced warm reset timed-out
517
* and the Reset Manager had to proceed with the warm reset anyway.
518
*
519
* Field Access Macros:
520
*
521
*/
522
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
523
#define ALT_RSTMGR_STAT_SCANHSTMO_LSB 26
524
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
525
#define ALT_RSTMGR_STAT_SCANHSTMO_MSB 26
526
/* The width in bits of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
527
#define ALT_RSTMGR_STAT_SCANHSTMO_WIDTH 1
528
/* The mask used to set the ALT_RSTMGR_STAT_SCANHSTMO register field value. */
529
#define ALT_RSTMGR_STAT_SCANHSTMO_SET_MSK 0x04000000
530
/* The mask used to clear the ALT_RSTMGR_STAT_SCANHSTMO register field value. */
531
#define ALT_RSTMGR_STAT_SCANHSTMO_CLR_MSK 0xfbffffff
532
/* The reset value of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
533
#define ALT_RSTMGR_STAT_SCANHSTMO_RESET 0x0
534
/* Extracts the ALT_RSTMGR_STAT_SCANHSTMO field value from a register. */
535
#define ALT_RSTMGR_STAT_SCANHSTMO_GET(value) (((value) & 0x04000000) >> 26)
536
/* Produces a ALT_RSTMGR_STAT_SCANHSTMO register field value suitable for setting the register. */
537
#define ALT_RSTMGR_STAT_SCANHSTMO_SET(value) (((value) << 26) & 0x04000000)
538
539
/*
540
* Field : FPGA handshake Timeout - fpgahstimeout
541
*
542
* A 1 indicates that Reset Manager's handshake request to FPGA before starting a
543
* hardware sequenced warm reset timed-out and the Reset Manager had to proceed
544
* with the warm reset anyway.
545
*
546
* Field Access Macros:
547
*
548
*/
549
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
550
#define ALT_RSTMGR_STAT_FPGAHSTMO_LSB 27
551
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
552
#define ALT_RSTMGR_STAT_FPGAHSTMO_MSB 27
553
/* The width in bits of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
554
#define ALT_RSTMGR_STAT_FPGAHSTMO_WIDTH 1
555
/* The mask used to set the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */
556
#define ALT_RSTMGR_STAT_FPGAHSTMO_SET_MSK 0x08000000
557
/* The mask used to clear the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */
558
#define ALT_RSTMGR_STAT_FPGAHSTMO_CLR_MSK 0xf7ffffff
559
/* The reset value of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
560
#define ALT_RSTMGR_STAT_FPGAHSTMO_RESET 0x0
561
/* Extracts the ALT_RSTMGR_STAT_FPGAHSTMO field value from a register. */
562
#define ALT_RSTMGR_STAT_FPGAHSTMO_GET(value) (((value) & 0x08000000) >> 27)
563
/* Produces a ALT_RSTMGR_STAT_FPGAHSTMO register field value suitable for setting the register. */
564
#define ALT_RSTMGR_STAT_FPGAHSTMO_SET(value) (((value) << 27) & 0x08000000)
565
566
/*
567
* Field : ETR Stall Timeout - etrstalltimeout
568
*
569
* A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to
570
* stall its AXI master port before starting a hardware sequenced warm reset timed-
571
* out and the Reset Manager had to proceed with the warm reset anyway.
572
*
573
* Field Access Macros:
574
*
575
*/
576
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
577
#define ALT_RSTMGR_STAT_ETRSTALLTMO_LSB 28
578
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
579
#define ALT_RSTMGR_STAT_ETRSTALLTMO_MSB 28
580
/* The width in bits of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
581
#define ALT_RSTMGR_STAT_ETRSTALLTMO_WIDTH 1
582
/* The mask used to set the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */
583
#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET_MSK 0x10000000
584
/* The mask used to clear the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */
585
#define ALT_RSTMGR_STAT_ETRSTALLTMO_CLR_MSK 0xefffffff
586
/* The reset value of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
587
#define ALT_RSTMGR_STAT_ETRSTALLTMO_RESET 0x0
588
/* Extracts the ALT_RSTMGR_STAT_ETRSTALLTMO field value from a register. */
589
#define ALT_RSTMGR_STAT_ETRSTALLTMO_GET(value) (((value) & 0x10000000) >> 28)
590
/* Produces a ALT_RSTMGR_STAT_ETRSTALLTMO register field value suitable for setting the register. */
591
#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET(value) (((value) << 28) & 0x10000000)
592
593
#ifndef __ASSEMBLY__
594
/*
595
* WARNING: The C register and register group struct declarations are provided for
596
* convenience and illustrative purposes. They should, however, be used with
597
* caution as the C language standard provides no guarantees about the alignment or
598
* atomicity of device memory accesses. The recommended practice for writing
599
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
600
* alt_write_word() functions.
601
*
602
* The struct declaration for register ALT_RSTMGR_STAT.
603
*/
604
struct
ALT_RSTMGR_STAT_s
605
{
606
uint32_t porvoltrst : 1;
/* Power-On Voltage Detector Cold Reset */
607
uint32_t nporpinrst : 1;
/* nPOR Pin Cold Reset */
608
uint32_t fpgacoldrst : 1;
/* FPGA Core Cold Reset */
609
uint32_t configiocoldrst : 1;
/* CONFIG_IO Cold Reset */
610
uint32_t swcoldrst : 1;
/* Software Cold Reset */
611
uint32_t : 3;
/* *UNDEFINED* */
612
uint32_t nrstpinrst : 1;
/* nRST Pin Warm Reset */
613
uint32_t fpgawarmrst : 1;
/* FPGA Core Warm Reset */
614
uint32_t swwarmrst : 1;
/* Software Warm Reset */
615
uint32_t : 1;
/* *UNDEFINED* */
616
uint32_t mpuwd0rst : 1;
/* MPU Watchdog 0 Warm Reset */
617
uint32_t mpuwd1rst : 1;
/* MPU Watchdog 1 Warm Reset */
618
uint32_t l4wd0rst : 1;
/* L4 Watchdog 0 Warm Reset */
619
uint32_t l4wd1rst : 1;
/* L4 Watchdog 1 Warm Reset */
620
uint32_t : 2;
/* *UNDEFINED* */
621
uint32_t fpgadbgrst : 1;
/* FPGA Core Debug Reset */
622
uint32_t cdbgreqrst : 1;
/* DAP Debug Reset */
623
uint32_t : 4;
/* *UNDEFINED* */
624
uint32_t sdrselfreftimeout : 1;
/* SDRAM Self-Refresh Timeout */
625
uint32_t fpgamgrhstimeout : 1;
/* FPGA manager handshake Timeout */
626
uint32_t scanhstimeout : 1;
/* SCAN manager handshake Timeout */
627
uint32_t fpgahstimeout : 1;
/* FPGA handshake Timeout */
628
uint32_t etrstalltimeout : 1;
/* ETR Stall Timeout */
629
uint32_t : 3;
/* *UNDEFINED* */
630
};
631
632
/* The typedef declaration for register ALT_RSTMGR_STAT. */
633
typedef
volatile
struct
ALT_RSTMGR_STAT_s
ALT_RSTMGR_STAT_t;
634
#endif
/* __ASSEMBLY__ */
635
636
/* The byte offset of the ALT_RSTMGR_STAT register from the beginning of the component. */
637
#define ALT_RSTMGR_STAT_OFST 0x0
638
639
/*
640
* Register : Control Register - ctrl
641
*
642
* The CTRL register is used by software to control reset behavior.It includes
643
* fields for software to initiate the cold and warm reset, enable hardware
644
* handshake with other modules before warm reset, and perform software handshake.
645
* The software handshake sequence must match the hardware sequence. Software
646
* mustde-assert the handshake request after asserting warm reset and before de-
647
* assert the warm reset.
648
*
649
* Fields are only reset by a cold reset.
650
*
651
* Register Layout
652
*
653
* Bits | Access | Reset | Description
654
* :--------|:-------|:--------|:---------------------------------------------------
655
* [0] | RW | 0x0 | Software Cold Reset Request
656
* [1] | RW | 0x0 | Software Warm Reset Request
657
* [3:2] | ??? | 0x0 | *UNDEFINED*
658
* [4] | RW | 0x0 | SDRAM Self-Refresh Enable
659
* [5] | RW | 0x0 | SDRAM Self-Refresh Request
660
* [6] | R | 0x0 | SDRAM Self-Refresh Acknowledge
661
* [7] | ??? | 0x0 | *UNDEFINED*
662
* [8] | RW | 0x0 | FPGA Manager Handshake Enable
663
* [9] | RW | 0x0 | FPGA Manager Handshake Request
664
* [10] | R | Unknown | FPGA Manager Handshake Acknowledge
665
* [11] | ??? | 0x0 | *UNDEFINED*
666
* [12] | RW | 0x0 | SCAN Manager Handshake Enable
667
* [13] | RW | 0x0 | SCAN Manager Handshake Request
668
* [14] | R | Unknown | SCAN Manager Handshake Acknowledge
669
* [15] | ??? | 0x0 | *UNDEFINED*
670
* [16] | RW | 0x0 | FPGA Handshake Enable
671
* [17] | RW | 0x0 | FPGA Handshake Request
672
* [18] | R | Unknown | FPGA Handshake Acknowledge
673
* [19] | ??? | 0x0 | *UNDEFINED*
674
* [20] | RW | 0x1 | ETR (Embedded Trace Router) Stall Enable
675
* [21] | RW | 0x0 | ETR (Embedded Trace Router) Stall Request
676
* [22] | R | 0x0 | ETR (Embedded Trace Router) Stall Acknowledge
677
* [23] | RW | 0x0 | ETR (Embedded Trace Router) Stall After Warm Reset
678
* [31:24] | ??? | 0x0 | *UNDEFINED*
679
*
680
*/
681
/*
682
* Field : Software Cold Reset Request - swcoldrstreq
683
*
684
* This is a one-shot bit written by software to 1 to trigger a cold reset. It
685
* always reads the value 0.
686
*
687
* Field Access Macros:
688
*
689
*/
690
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
691
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB 0
692
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
693
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB 0
694
/* The width in bits of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
695
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH 1
696
/* The mask used to set the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */
697
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK 0x00000001
698
/* The mask used to clear the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */
699
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK 0xfffffffe
700
/* The reset value of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
701
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET 0x0
702
/* Extracts the ALT_RSTMGR_CTL_SWCOLDRSTREQ field value from a register. */
703
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET(value) (((value) & 0x00000001) >> 0)
704
/* Produces a ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value suitable for setting the register. */
705
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET(value) (((value) << 0) & 0x00000001)
706
707
/*
708
* Field : Software Warm Reset Request - swwarmrstreq
709
*
710
* This is a one-shot bit written by software to 1 to trigger a hardware sequenced
711
* warm reset. It always reads the value 0.
712
*
713
* Field Access Macros:
714
*
715
*/
716
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
717
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB 1
718
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
719
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB 1
720
/* The width in bits of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
721
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH 1
722
/* The mask used to set the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */
723
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK 0x00000002
724
/* The mask used to clear the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */
725
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK 0xfffffffd
726
/* The reset value of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
727
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET 0x0
728
/* Extracts the ALT_RSTMGR_CTL_SWWARMRSTREQ field value from a register. */
729
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_GET(value) (((value) & 0x00000002) >> 1)
730
/* Produces a ALT_RSTMGR_CTL_SWWARMRSTREQ register field value suitable for setting the register. */
731
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET(value) (((value) << 1) & 0x00000002)
732
733
/*
734
* Field : SDRAM Self-Refresh Enable - sdrselfrefen
735
*
736
* This field controls whether the contents of SDRAM devices survive a hardware
737
* sequenced warm reset. If set to 1, the Reset Manager makes a request to the
738
* SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode
739
* before asserting warm reset signals. However, if SDRAM is already in warm reset,
740
* Handshake with SDRAM is not performed.
741
*
742
* Field Access Macros:
743
*
744
*/
745
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
746
#define ALT_RSTMGR_CTL_SDRSELFREFEN_LSB 4
747
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
748
#define ALT_RSTMGR_CTL_SDRSELFREFEN_MSB 4
749
/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
750
#define ALT_RSTMGR_CTL_SDRSELFREFEN_WIDTH 1
751
/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */
752
#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK 0x00000010
753
/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */
754
#define ALT_RSTMGR_CTL_SDRSELFREFEN_CLR_MSK 0xffffffef
755
/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
756
#define ALT_RSTMGR_CTL_SDRSELFREFEN_RESET 0x0
757
/* Extracts the ALT_RSTMGR_CTL_SDRSELFREFEN field value from a register. */
758
#define ALT_RSTMGR_CTL_SDRSELFREFEN_GET(value) (((value) & 0x00000010) >> 4)
759
/* Produces a ALT_RSTMGR_CTL_SDRSELFREFEN register field value suitable for setting the register. */
760
#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET(value) (((value) << 4) & 0x00000010)
761
762
/*
763
* Field : SDRAM Self-Refresh Request - sdrselfrefreq
764
*
765
* Software writes this field 1 to request to the SDRAM Controller Subsystem that
766
* it puts the SDRAM devices into self-refresh mode. This is done to preserve SDRAM
767
* contents across a software warm reset.
768
*
769
* Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0.
770
* Note that it is possible for the SDRAM Controller Subsystem to never assert
771
* SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted.
772
*
773
* Field Access Macros:
774
*
775
*/
776
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
777
#define ALT_RSTMGR_CTL_SDRSELFREFREQ_LSB 5
778
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
779
#define ALT_RSTMGR_CTL_SDRSELFREFREQ_MSB 5
780
/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
781
#define ALT_RSTMGR_CTL_SDRSELFREFREQ_WIDTH 1
782
/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */
783
#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET_MSK 0x00000020
784
/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */
785
#define ALT_RSTMGR_CTL_SDRSELFREFREQ_CLR_MSK 0xffffffdf
786
/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
787
#define ALT_RSTMGR_CTL_SDRSELFREFREQ_RESET 0x0
788
/* Extracts the ALT_RSTMGR_CTL_SDRSELFREFREQ field value from a register. */
789
#define ALT_RSTMGR_CTL_SDRSELFREFREQ_GET(value) (((value) & 0x00000020) >> 5)
790
/* Produces a ALT_RSTMGR_CTL_SDRSELFREFREQ register field value suitable for setting the register. */
791
#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET(value) (((value) << 5) & 0x00000020)
792
793
/*
794
* Field : SDRAM Self-Refresh Acknowledge - sdrselfreqack
795
*
796
* This is the acknowlege for a SDRAM self-refresh mode request initiated by the
797
* SDRSELFREFREQ field. A 1 indicates that the SDRAM Controller Subsystem has put
798
* the SDRAM devices into self-refresh mode.
799
*
800
* Field Access Macros:
801
*
802
*/
803
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
804
#define ALT_RSTMGR_CTL_SDRSELFREQACK_LSB 6
805
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
806
#define ALT_RSTMGR_CTL_SDRSELFREQACK_MSB 6
807
/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
808
#define ALT_RSTMGR_CTL_SDRSELFREQACK_WIDTH 1
809
/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */
810
#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET_MSK 0x00000040
811
/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */
812
#define ALT_RSTMGR_CTL_SDRSELFREQACK_CLR_MSK 0xffffffbf
813
/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
814
#define ALT_RSTMGR_CTL_SDRSELFREQACK_RESET 0x0
815
/* Extracts the ALT_RSTMGR_CTL_SDRSELFREQACK field value from a register. */
816
#define ALT_RSTMGR_CTL_SDRSELFREQACK_GET(value) (((value) & 0x00000040) >> 6)
817
/* Produces a ALT_RSTMGR_CTL_SDRSELFREQACK register field value suitable for setting the register. */
818
#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET(value) (((value) << 6) & 0x00000040)
819
820
/*
821
* Field : FPGA Manager Handshake Enable - fpgamgrhsen
822
*
823
* Enables a handshake between the Reset Manager and FPGA Manager before a warm
824
* reset. The handshake is used to warn the FPGA Manager that a warm reset it
825
* coming so it can prepare for it. When the FPGA Manager receives a warm reset
826
* handshake, the FPGA Manager drives its output clock to a quiescent state to
827
* avoid glitches.
828
*
829
* If set to 1, the Manager makes a request to the FPGA Managerbefore asserting
830
* warm reset signals. However if the FPGA Manager is already in warm reset, the
831
* handshake is skipped.
832
*
833
* If set to 0, the handshake is skipped.
834
*
835
* Field Access Macros:
836
*
837
*/
838
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
839
#define ALT_RSTMGR_CTL_FPGAMGRHSEN_LSB 8
840
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
841
#define ALT_RSTMGR_CTL_FPGAMGRHSEN_MSB 8
842
/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
843
#define ALT_RSTMGR_CTL_FPGAMGRHSEN_WIDTH 1
844
/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */
845
#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK 0x00000100
846
/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */
847
#define ALT_RSTMGR_CTL_FPGAMGRHSEN_CLR_MSK 0xfffffeff
848
/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
849
#define ALT_RSTMGR_CTL_FPGAMGRHSEN_RESET 0x0
850
/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSEN field value from a register. */
851
#define ALT_RSTMGR_CTL_FPGAMGRHSEN_GET(value) (((value) & 0x00000100) >> 8)
852
/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSEN register field value suitable for setting the register. */
853
#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET(value) (((value) << 8) & 0x00000100)
854
855
/*
856
* Field : FPGA Manager Handshake Request - fpgamgrhsreq
857
*
858
* Software writes this field 1 to request to the FPGA Manager to idle its output
859
* clock.
860
*
861
* Software waits for the FPGAMGRHSACK to be 1 and then writes this field to 0.
862
* Note that it is possible for the FPGA Manager to never assert FPGAMGRHSACK so
863
* software should timeout in this case.
864
*
865
* Field Access Macros:
866
*
867
*/
868
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
869
#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_LSB 9
870
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
871
#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_MSB 9
872
/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
873
#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_WIDTH 1
874
/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */
875
#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET_MSK 0x00000200
876
/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */
877
#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_CLR_MSK 0xfffffdff
878
/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
879
#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_RESET 0x0
880
/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSREQ field value from a register. */
881
#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_GET(value) (((value) & 0x00000200) >> 9)
882
/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value suitable for setting the register. */
883
#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET(value) (((value) << 9) & 0x00000200)
884
885
/*
886
* Field : FPGA Manager Handshake Acknowledge - fpgamgrhsack
887
*
888
* This is the acknowlege (high active) that the FPGA manager has successfully
889
* idled its output clock.
890
*
891
* Field Access Macros:
892
*
893
*/
894
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */
895
#define ALT_RSTMGR_CTL_FPGAMGRHSACK_LSB 10
896
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */
897
#define ALT_RSTMGR_CTL_FPGAMGRHSACK_MSB 10
898
/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */
899
#define ALT_RSTMGR_CTL_FPGAMGRHSACK_WIDTH 1
900
/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */
901
#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET_MSK 0x00000400
902
/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */
903
#define ALT_RSTMGR_CTL_FPGAMGRHSACK_CLR_MSK 0xfffffbff
904
/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field is UNKNOWN. */
905
#define ALT_RSTMGR_CTL_FPGAMGRHSACK_RESET 0x0
906
/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSACK field value from a register. */
907
#define ALT_RSTMGR_CTL_FPGAMGRHSACK_GET(value) (((value) & 0x00000400) >> 10)
908
/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSACK register field value suitable for setting the register. */
909
#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET(value) (((value) << 10) & 0x00000400)
910
911
/*
912
* Field : SCAN Manager Handshake Enable - scanmgrhsen
913
*
914
* Enables a handshake between the Reset Manager and Scan Manager before a warm
915
* reset. The handshake is used to warn the Scan Manager that a warm reset it
916
* coming so it can prepare for it. When the Scan Manager receives a warm reset
917
* handshake, the Scan Manager drives its output clocks to a quiescent state to
918
* avoid glitches.
919
*
920
* If set to 1, the Reset Manager makes a request to the Scan Managerbefore
921
* asserting warm reset signals. However if the Scan Manager is already in warm
922
* reset, the handshake is skipped.
923
*
924
* If set to 0, the handshake is skipped.
925
*
926
* Field Access Macros:
927
*
928
*/
929
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
930
#define ALT_RSTMGR_CTL_SCANMGRHSEN_LSB 12
931
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
932
#define ALT_RSTMGR_CTL_SCANMGRHSEN_MSB 12
933
/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
934
#define ALT_RSTMGR_CTL_SCANMGRHSEN_WIDTH 1
935
/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */
936
#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK 0x00001000
937
/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */
938
#define ALT_RSTMGR_CTL_SCANMGRHSEN_CLR_MSK 0xffffefff
939
/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
940
#define ALT_RSTMGR_CTL_SCANMGRHSEN_RESET 0x0
941
/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSEN field value from a register. */
942
#define ALT_RSTMGR_CTL_SCANMGRHSEN_GET(value) (((value) & 0x00001000) >> 12)
943
/* Produces a ALT_RSTMGR_CTL_SCANMGRHSEN register field value suitable for setting the register. */
944
#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET(value) (((value) << 12) & 0x00001000)
945
946
/*
947
* Field : SCAN Manager Handshake Request - scanmgrhsreq
948
*
949
* Software writes this field 1 to request to the SCAN manager to idle its output
950
* clocks.
951
*
952
* Software waits for the SCANMGRHSACK to be 1 and then writes this field to 0.
953
* Note that it is possible for the Scan Manager to never assert SCANMGRHSACK (e.g.
954
* its input clock is disabled) so software should timeout in this case.
955
*
956
* Field Access Macros:
957
*
958
*/
959
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
960
#define ALT_RSTMGR_CTL_SCANMGRHSREQ_LSB 13
961
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
962
#define ALT_RSTMGR_CTL_SCANMGRHSREQ_MSB 13
963
/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
964
#define ALT_RSTMGR_CTL_SCANMGRHSREQ_WIDTH 1
965
/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */
966
#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET_MSK 0x00002000
967
/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */
968
#define ALT_RSTMGR_CTL_SCANMGRHSREQ_CLR_MSK 0xffffdfff
969
/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
970
#define ALT_RSTMGR_CTL_SCANMGRHSREQ_RESET 0x0
971
/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSREQ field value from a register. */
972
#define ALT_RSTMGR_CTL_SCANMGRHSREQ_GET(value) (((value) & 0x00002000) >> 13)
973
/* Produces a ALT_RSTMGR_CTL_SCANMGRHSREQ register field value suitable for setting the register. */
974
#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET(value) (((value) << 13) & 0x00002000)
975
976
/*
977
* Field : SCAN Manager Handshake Acknowledge - scanmgrhsack
978
*
979
* This is the acknowlege (high active) that the SCAN manager has successfully
980
* idled its output clocks.
981
*
982
* Field Access Macros:
983
*
984
*/
985
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */
986
#define ALT_RSTMGR_CTL_SCANMGRHSACK_LSB 14
987
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */
988
#define ALT_RSTMGR_CTL_SCANMGRHSACK_MSB 14
989
/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */
990
#define ALT_RSTMGR_CTL_SCANMGRHSACK_WIDTH 1
991
/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */
992
#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET_MSK 0x00004000
993
/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */
994
#define ALT_RSTMGR_CTL_SCANMGRHSACK_CLR_MSK 0xffffbfff
995
/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSACK register field is UNKNOWN. */
996
#define ALT_RSTMGR_CTL_SCANMGRHSACK_RESET 0x0
997
/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSACK field value from a register. */
998
#define ALT_RSTMGR_CTL_SCANMGRHSACK_GET(value) (((value) & 0x00004000) >> 14)
999
/* Produces a ALT_RSTMGR_CTL_SCANMGRHSACK register field value suitable for setting the register. */
1000
#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET(value) (((value) << 14) & 0x00004000)
1001
1002
/*
1003
* Field : FPGA Handshake Enable - fpgahsen
1004
*
1005
* This field controls whether to perform handshake with FPGA before asserting warm
1006
* reset.
1007
*
1008
* If set to 1, the Reset Manager makes a request to the FPGAbefore asserting warm
1009
* reset signals. However if FPGA is already in warm reset state, the handshake is
1010
* not performed.
1011
*
1012
* If set to 0, the handshake is not performed
1013
*
1014
* Field Access Macros:
1015
*
1016
*/
1017
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
1018
#define ALT_RSTMGR_CTL_FPGAHSEN_LSB 16
1019
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
1020
#define ALT_RSTMGR_CTL_FPGAHSEN_MSB 16
1021
/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
1022
#define ALT_RSTMGR_CTL_FPGAHSEN_WIDTH 1
1023
/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSEN register field value. */
1024
#define ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK 0x00010000
1025
/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSEN register field value. */
1026
#define ALT_RSTMGR_CTL_FPGAHSEN_CLR_MSK 0xfffeffff
1027
/* The reset value of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
1028
#define ALT_RSTMGR_CTL_FPGAHSEN_RESET 0x0
1029
/* Extracts the ALT_RSTMGR_CTL_FPGAHSEN field value from a register. */
1030
#define ALT_RSTMGR_CTL_FPGAHSEN_GET(value) (((value) & 0x00010000) >> 16)
1031
/* Produces a ALT_RSTMGR_CTL_FPGAHSEN register field value suitable for setting the register. */
1032
#define ALT_RSTMGR_CTL_FPGAHSEN_SET(value) (((value) << 16) & 0x00010000)
1033
1034
/*
1035
* Field : FPGA Handshake Request - fpgahsreq
1036
*
1037
* Software writes this field 1 to initiate handshake request to FPGA .
1038
*
1039
* Software waits for the FPGAHSACK to be active and then writes this field to 0.
1040
* Note that it is possible for the FPGA to never assert FPGAHSACK so software
1041
* should timeout in this case.
1042
*
1043
* Field Access Macros:
1044
*
1045
*/
1046
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
1047
#define ALT_RSTMGR_CTL_FPGAHSREQ_LSB 17
1048
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
1049
#define ALT_RSTMGR_CTL_FPGAHSREQ_MSB 17
1050
/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
1051
#define ALT_RSTMGR_CTL_FPGAHSREQ_WIDTH 1
1052
/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */
1053
#define ALT_RSTMGR_CTL_FPGAHSREQ_SET_MSK 0x00020000
1054
/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */
1055
#define ALT_RSTMGR_CTL_FPGAHSREQ_CLR_MSK 0xfffdffff
1056
/* The reset value of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
1057
#define ALT_RSTMGR_CTL_FPGAHSREQ_RESET 0x0
1058
/* Extracts the ALT_RSTMGR_CTL_FPGAHSREQ field value from a register. */
1059
#define ALT_RSTMGR_CTL_FPGAHSREQ_GET(value) (((value) & 0x00020000) >> 17)
1060
/* Produces a ALT_RSTMGR_CTL_FPGAHSREQ register field value suitable for setting the register. */
1061
#define ALT_RSTMGR_CTL_FPGAHSREQ_SET(value) (((value) << 17) & 0x00020000)
1062
1063
/*
1064
* Field : FPGA Handshake Acknowledge - fpgahsack
1065
*
1066
* This is the acknowlege (high active) that the FPGA handshake acknowledge has
1067
* been received by Reset Manager.
1068
*
1069
* Field Access Macros:
1070
*
1071
*/
1072
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */
1073
#define ALT_RSTMGR_CTL_FPGAHSACK_LSB 18
1074
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */
1075
#define ALT_RSTMGR_CTL_FPGAHSACK_MSB 18
1076
/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSACK register field. */
1077
#define ALT_RSTMGR_CTL_FPGAHSACK_WIDTH 1
1078
/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSACK register field value. */
1079
#define ALT_RSTMGR_CTL_FPGAHSACK_SET_MSK 0x00040000
1080
/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSACK register field value. */
1081
#define ALT_RSTMGR_CTL_FPGAHSACK_CLR_MSK 0xfffbffff
1082
/* The reset value of the ALT_RSTMGR_CTL_FPGAHSACK register field is UNKNOWN. */
1083
#define ALT_RSTMGR_CTL_FPGAHSACK_RESET 0x0
1084
/* Extracts the ALT_RSTMGR_CTL_FPGAHSACK field value from a register. */
1085
#define ALT_RSTMGR_CTL_FPGAHSACK_GET(value) (((value) & 0x00040000) >> 18)
1086
/* Produces a ALT_RSTMGR_CTL_FPGAHSACK register field value suitable for setting the register. */
1087
#define ALT_RSTMGR_CTL_FPGAHSACK_SET(value) (((value) << 18) & 0x00040000)
1088
1089
/*
1090
* Field : ETR (Embedded Trace Router) Stall Enable - etrstallen
1091
*
1092
* This field controls whether the ETR is requested to idle its AXI master
1093
* interface (i.e. finish outstanding transactions and not initiate any more) to
1094
* the L3 Interconnect before a warm or debug reset. If set to 1, the Reset Manager
1095
* makes a request to the ETR to stall its AXI master and waits for it to finish
1096
* any outstanding AXI transactions before a warm reset of the L3 Interconnect or a
1097
* debug reset of the ETR. This stalling is required because the debug logic
1098
* (including the ETR) is reset on a debug reset and the ETR AXI master is
1099
* connected to the L3 Interconnect which is reset on a warm reset and these resets
1100
* can happen independently.
1101
*
1102
* Field Access Macros:
1103
*
1104
*/
1105
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
1106
#define ALT_RSTMGR_CTL_ETRSTALLEN_LSB 20
1107
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
1108
#define ALT_RSTMGR_CTL_ETRSTALLEN_MSB 20
1109
/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
1110
#define ALT_RSTMGR_CTL_ETRSTALLEN_WIDTH 1
1111
/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */
1112
#define ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK 0x00100000
1113
/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */
1114
#define ALT_RSTMGR_CTL_ETRSTALLEN_CLR_MSK 0xffefffff
1115
/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
1116
#define ALT_RSTMGR_CTL_ETRSTALLEN_RESET 0x1
1117
/* Extracts the ALT_RSTMGR_CTL_ETRSTALLEN field value from a register. */
1118
#define ALT_RSTMGR_CTL_ETRSTALLEN_GET(value) (((value) & 0x00100000) >> 20)
1119
/* Produces a ALT_RSTMGR_CTL_ETRSTALLEN register field value suitable for setting the register. */
1120
#define ALT_RSTMGR_CTL_ETRSTALLEN_SET(value) (((value) << 20) & 0x00100000)
1121
1122
/*
1123
* Field : ETR (Embedded Trace Router) Stall Request - etrstallreq
1124
*
1125
* Software writes this field 1 to request to the ETR that it stalls its AXI master
1126
* to the L3 Interconnect.
1127
*
1128
* Software waits for the ETRSTALLACK to be 1 and then writes this field to 0.
1129
* Note that it is possible for the ETR to never assert ETRSTALLACK so software
1130
* should timeout if ETRSTALLACK is never asserted.
1131
*
1132
* Field Access Macros:
1133
*
1134
*/
1135
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
1136
#define ALT_RSTMGR_CTL_ETRSTALLREQ_LSB 21
1137
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
1138
#define ALT_RSTMGR_CTL_ETRSTALLREQ_MSB 21
1139
/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
1140
#define ALT_RSTMGR_CTL_ETRSTALLREQ_WIDTH 1
1141
/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */
1142
#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET_MSK 0x00200000
1143
/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */
1144
#define ALT_RSTMGR_CTL_ETRSTALLREQ_CLR_MSK 0xffdfffff
1145
/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
1146
#define ALT_RSTMGR_CTL_ETRSTALLREQ_RESET 0x0
1147
/* Extracts the ALT_RSTMGR_CTL_ETRSTALLREQ field value from a register. */
1148
#define ALT_RSTMGR_CTL_ETRSTALLREQ_GET(value) (((value) & 0x00200000) >> 21)
1149
/* Produces a ALT_RSTMGR_CTL_ETRSTALLREQ register field value suitable for setting the register. */
1150
#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET(value) (((value) << 21) & 0x00200000)
1151
1152
/*
1153
* Field : ETR (Embedded Trace Router) Stall Acknowledge - etrstallack
1154
*
1155
* This is the acknowlege for a ETR AXI master stall initiated by the ETRSTALLREQ
1156
* field. A 1 indicates that the ETR has stalled its AXI master
1157
*
1158
* Field Access Macros:
1159
*
1160
*/
1161
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
1162
#define ALT_RSTMGR_CTL_ETRSTALLACK_LSB 22
1163
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
1164
#define ALT_RSTMGR_CTL_ETRSTALLACK_MSB 22
1165
/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
1166
#define ALT_RSTMGR_CTL_ETRSTALLACK_WIDTH 1
1167
/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */
1168
#define ALT_RSTMGR_CTL_ETRSTALLACK_SET_MSK 0x00400000
1169
/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */
1170
#define ALT_RSTMGR_CTL_ETRSTALLACK_CLR_MSK 0xffbfffff
1171
/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
1172
#define ALT_RSTMGR_CTL_ETRSTALLACK_RESET 0x0
1173
/* Extracts the ALT_RSTMGR_CTL_ETRSTALLACK field value from a register. */
1174
#define ALT_RSTMGR_CTL_ETRSTALLACK_GET(value) (((value) & 0x00400000) >> 22)
1175
/* Produces a ALT_RSTMGR_CTL_ETRSTALLACK register field value suitable for setting the register. */
1176
#define ALT_RSTMGR_CTL_ETRSTALLACK_SET(value) (((value) << 22) & 0x00400000)
1177
1178
/*
1179
* Field : ETR (Embedded Trace Router) Stall After Warm Reset - etrstallwarmrst
1180
*
1181
* If a warm reset occurs and ETRSTALLEN is 1, hardware sets this bit to 1 to
1182
* indicate that the stall of the ETR AXI master is pending. Hardware leaves the
1183
* ETR stalled until software clears this field by writing it with 1. Software must
1184
* only clear this field when it is ready to have the ETR AXI master start making
1185
* AXI requests to write trace data.
1186
*
1187
* Field Access Macros:
1188
*
1189
*/
1190
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
1191
#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_LSB 23
1192
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
1193
#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_MSB 23
1194
/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
1195
#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_WIDTH 1
1196
/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */
1197
#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET_MSK 0x00800000
1198
/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */
1199
#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_CLR_MSK 0xff7fffff
1200
/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
1201
#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_RESET 0x0
1202
/* Extracts the ALT_RSTMGR_CTL_ETRSTALLWARMRST field value from a register. */
1203
#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_GET(value) (((value) & 0x00800000) >> 23)
1204
/* Produces a ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value suitable for setting the register. */
1205
#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET(value) (((value) << 23) & 0x00800000)
1206
1207
#ifndef __ASSEMBLY__
1208
/*
1209
* WARNING: The C register and register group struct declarations are provided for
1210
* convenience and illustrative purposes. They should, however, be used with
1211
* caution as the C language standard provides no guarantees about the alignment or
1212
* atomicity of device memory accesses. The recommended practice for writing
1213
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
1214
* alt_write_word() functions.
1215
*
1216
* The struct declaration for register ALT_RSTMGR_CTL.
1217
*/
1218
struct
ALT_RSTMGR_CTL_s
1219
{
1220
uint32_t swcoldrstreq : 1;
/* Software Cold Reset Request */
1221
uint32_t swwarmrstreq : 1;
/* Software Warm Reset Request */
1222
uint32_t : 2;
/* *UNDEFINED* */
1223
uint32_t sdrselfrefen : 1;
/* SDRAM Self-Refresh Enable */
1224
uint32_t sdrselfrefreq : 1;
/* SDRAM Self-Refresh Request */
1225
const
uint32_t sdrselfreqack : 1;
/* SDRAM Self-Refresh Acknowledge */
1226
uint32_t : 1;
/* *UNDEFINED* */
1227
uint32_t fpgamgrhsen : 1;
/* FPGA Manager Handshake Enable */
1228
uint32_t fpgamgrhsreq : 1;
/* FPGA Manager Handshake Request */
1229
const
uint32_t fpgamgrhsack : 1;
/* FPGA Manager Handshake Acknowledge */
1230
uint32_t : 1;
/* *UNDEFINED* */
1231
uint32_t scanmgrhsen : 1;
/* SCAN Manager Handshake Enable */
1232
uint32_t scanmgrhsreq : 1;
/* SCAN Manager Handshake Request */
1233
const
uint32_t scanmgrhsack : 1;
/* SCAN Manager Handshake Acknowledge */
1234
uint32_t : 1;
/* *UNDEFINED* */
1235
uint32_t fpgahsen : 1;
/* FPGA Handshake Enable */
1236
uint32_t fpgahsreq : 1;
/* FPGA Handshake Request */
1237
const
uint32_t fpgahsack : 1;
/* FPGA Handshake Acknowledge */
1238
uint32_t : 1;
/* *UNDEFINED* */
1239
uint32_t etrstallen : 1;
/* ETR (Embedded Trace Router) Stall Enable */
1240
uint32_t etrstallreq : 1;
/* ETR (Embedded Trace Router) Stall Request */
1241
const
uint32_t etrstallack : 1;
/* ETR (Embedded Trace Router) Stall Acknowledge */
1242
uint32_t etrstallwarmrst : 1;
/* ETR (Embedded Trace Router) Stall After Warm Reset */
1243
uint32_t : 8;
/* *UNDEFINED* */
1244
};
1245
1246
/* The typedef declaration for register ALT_RSTMGR_CTL. */
1247
typedef
volatile
struct
ALT_RSTMGR_CTL_s
ALT_RSTMGR_CTL_t;
1248
#endif
/* __ASSEMBLY__ */
1249
1250
/* The byte offset of the ALT_RSTMGR_CTL register from the beginning of the component. */
1251
#define ALT_RSTMGR_CTL_OFST 0x4
1252
1253
/*
1254
* Register : Reset Cycles Count Register - counts
1255
*
1256
* The COUNTS register is used by software to control reset behavior.It includes
1257
* fields for software to control the behavior of the warm reset and nRST pin.
1258
*
1259
* Fields are only reset by a cold reset.
1260
*
1261
* Register Layout
1262
*
1263
* Bits | Access | Reset | Description
1264
* :--------|:-------|:------|:-------------------------------
1265
* [7:0] | RW | 0x80 | Warm reset release delay count
1266
* [27:8] | RW | 0x800 | nRST Pin Count
1267
* [31:28] | ??? | 0x0 | *UNDEFINED*
1268
*
1269
*/
1270
/*
1271
* Field : Warm reset release delay count - warmrstcycles
1272
*
1273
* On a warm reset, the Reset Manager releases the reset to the Clock Manager, and
1274
* then waits for the number of cycles specified in this register before releasing
1275
* the rest of the hardware controlled resets. Value must be greater than 16.
1276
*
1277
* Field Access Macros:
1278
*
1279
*/
1280
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1281
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB 0
1282
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1283
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB 7
1284
/* The width in bits of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1285
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH 8
1286
/* The mask used to set the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */
1287
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK 0x000000ff
1288
/* The mask used to clear the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */
1289
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK 0xffffff00
1290
/* The reset value of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1291
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET 0x80
1292
/* Extracts the ALT_RSTMGR_COUNTS_WARMRSTCYCLES field value from a register. */
1293
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value) (((value) & 0x000000ff) >> 0)
1294
/* Produces a ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value suitable for setting the register. */
1295
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value) (((value) << 0) & 0x000000ff)
1296
1297
/*
1298
* Field : nRST Pin Count - nrstcnt
1299
*
1300
* The Reset Manager pulls down the nRST pin on a warm reset for the number of
1301
* cycles specified in this register. A value of 0x0 prevents the Reset Manager
1302
* from pulling down the nRST pin.
1303
*
1304
* Field Access Macros:
1305
*
1306
*/
1307
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1308
#define ALT_RSTMGR_COUNTS_NRSTCNT_LSB 8
1309
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1310
#define ALT_RSTMGR_COUNTS_NRSTCNT_MSB 27
1311
/* The width in bits of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1312
#define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH 20
1313
/* The mask used to set the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */
1314
#define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK 0x0fffff00
1315
/* The mask used to clear the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */
1316
#define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK 0xf00000ff
1317
/* The reset value of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1318
#define ALT_RSTMGR_COUNTS_NRSTCNT_RESET 0x800
1319
/* Extracts the ALT_RSTMGR_COUNTS_NRSTCNT field value from a register. */
1320
#define ALT_RSTMGR_COUNTS_NRSTCNT_GET(value) (((value) & 0x0fffff00) >> 8)
1321
/* Produces a ALT_RSTMGR_COUNTS_NRSTCNT register field value suitable for setting the register. */
1322
#define ALT_RSTMGR_COUNTS_NRSTCNT_SET(value) (((value) << 8) & 0x0fffff00)
1323
1324
#ifndef __ASSEMBLY__
1325
/*
1326
* WARNING: The C register and register group struct declarations are provided for
1327
* convenience and illustrative purposes. They should, however, be used with
1328
* caution as the C language standard provides no guarantees about the alignment or
1329
* atomicity of device memory accesses. The recommended practice for writing
1330
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
1331
* alt_write_word() functions.
1332
*
1333
* The struct declaration for register ALT_RSTMGR_COUNTS.
1334
*/
1335
struct
ALT_RSTMGR_COUNTS_s
1336
{
1337
uint32_t warmrstcycles : 8;
/* Warm reset release delay count */
1338
uint32_t nrstcnt : 20;
/* nRST Pin Count */
1339
uint32_t : 4;
/* *UNDEFINED* */
1340
};
1341
1342
/* The typedef declaration for register ALT_RSTMGR_COUNTS. */
1343
typedef
volatile
struct
ALT_RSTMGR_COUNTS_s
ALT_RSTMGR_COUNTS_t;
1344
#endif
/* __ASSEMBLY__ */
1345
1346
/* The byte offset of the ALT_RSTMGR_COUNTS register from the beginning of the component. */
1347
#define ALT_RSTMGR_COUNTS_OFST 0x8
1348
1349
/*
1350
* Register : MPU Module Reset Register - mpumodrst
1351
*
1352
* The MPUMODRST register is used by software to trigger module resets (individual
1353
* module reset signals). Software explicitly asserts and de-asserts module reset
1354
* signals by writing bits in the appropriate *MODRST register. It is up to
1355
* software to ensure module reset signals are asserted for the appropriate length
1356
* of time and are de-asserted in the correct order. It is also up to software to
1357
* not assert a module reset signal that would prevent software from de-asserting
1358
* the module reset signal. For example, software should not assert the module
1359
* reset to the CPU executing the software.
1360
*
1361
* Software writes a bit to 1 to assert the module reset signal and to 0 to de-
1362
* assert the module reset signal.
1363
*
1364
* All fields except CPU1 are only reset by a cold reset. The CPU1 field is reset
1365
* by a cold reset. The CPU1 field is also reset by a warm reset if not masked by
1366
* the corresponding MPUWARMMASK field.
1367
*
1368
* Register Layout
1369
*
1370
* Bits | Access | Reset | Description
1371
* :-------|:-------|:------|:----------------
1372
* [0] | RW | 0x0 | CPU0
1373
* [1] | RW | 0x1 | CPU1
1374
* [2] | RW | 0x0 | Watchdogs
1375
* [3] | RW | 0x0 | SCU/Peripherals
1376
* [4] | RW | 0x0 | L2
1377
* [31:5] | ??? | 0x0 | *UNDEFINED*
1378
*
1379
*/
1380
/*
1381
* Field : CPU0 - cpu0
1382
*
1383
* Resets Cortex-A9 CPU0 in MPU. Whe software changes this field from 0 to 1,
1384
* ittriggers the following sequence: 1. CPU0 reset is asserted. cpu0 clkoff is
1385
* de-asserted 2. after 32 osc1_clk cycles, cpu0 clkoff is asserted.
1386
*
1387
* When software changes this field from 1 to 0, it triggers the following
1388
* sequence: 1.CPU0 reset is de-asserted. 2. after 32 cycles, cpu0 clkoff is de-
1389
* asserted.
1390
*
1391
* Software needs to wait for at least 64 osc1_clk cycles between each change of
1392
* this field to keep the proper reset/clkoff sequence.
1393
*
1394
* Field Access Macros:
1395
*
1396
*/
1397
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
1398
#define ALT_RSTMGR_MPUMODRST_CPU0_LSB 0
1399
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
1400
#define ALT_RSTMGR_MPUMODRST_CPU0_MSB 0
1401
/* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
1402
#define ALT_RSTMGR_MPUMODRST_CPU0_WIDTH 1
1403
/* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */
1404
#define ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK 0x00000001
1405
/* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */
1406
#define ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK 0xfffffffe
1407
/* The reset value of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
1408
#define ALT_RSTMGR_MPUMODRST_CPU0_RESET 0x0
1409
/* Extracts the ALT_RSTMGR_MPUMODRST_CPU0 field value from a register. */
1410
#define ALT_RSTMGR_MPUMODRST_CPU0_GET(value) (((value) & 0x00000001) >> 0)
1411
/* Produces a ALT_RSTMGR_MPUMODRST_CPU0 register field value suitable for setting the register. */
1412
#define ALT_RSTMGR_MPUMODRST_CPU0_SET(value) (((value) << 0) & 0x00000001)
1413
1414
/*
1415
* Field : CPU1 - cpu1
1416
*
1417
* Resets Cortex-A9 CPU1 in MPU.
1418
*
1419
* It is reset to 1 on a cold or warm reset. This holds CPU1 in reset until
1420
* software is ready to release CPU1 from reset by writing 0 to this field.
1421
*
1422
* On single-core devices, writes to this field are ignored.On dual-core devices,
1423
* writes to this field trigger the same sequence as writes to the CPU0 field
1424
* (except the sequence is performed on CPU1).
1425
*
1426
* Field Access Macros:
1427
*
1428
*/
1429
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
1430
#define ALT_RSTMGR_MPUMODRST_CPU1_LSB 1
1431
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
1432
#define ALT_RSTMGR_MPUMODRST_CPU1_MSB 1
1433
/* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
1434
#define ALT_RSTMGR_MPUMODRST_CPU1_WIDTH 1
1435
/* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */
1436
#define ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK 0x00000002
1437
/* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */
1438
#define ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK 0xfffffffd
1439
/* The reset value of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
1440
#define ALT_RSTMGR_MPUMODRST_CPU1_RESET 0x1
1441
/* Extracts the ALT_RSTMGR_MPUMODRST_CPU1 field value from a register. */
1442
#define ALT_RSTMGR_MPUMODRST_CPU1_GET(value) (((value) & 0x00000002) >> 1)
1443
/* Produces a ALT_RSTMGR_MPUMODRST_CPU1 register field value suitable for setting the register. */
1444
#define ALT_RSTMGR_MPUMODRST_CPU1_SET(value) (((value) << 1) & 0x00000002)
1445
1446
/*
1447
* Field : Watchdogs - wds
1448
*
1449
* Resets both per-CPU Watchdog Reset Status registers in MPU.
1450
*
1451
* Field Access Macros:
1452
*
1453
*/
1454
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */
1455
#define ALT_RSTMGR_MPUMODRST_WDS_LSB 2
1456
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */
1457
#define ALT_RSTMGR_MPUMODRST_WDS_MSB 2
1458
/* The width in bits of the ALT_RSTMGR_MPUMODRST_WDS register field. */
1459
#define ALT_RSTMGR_MPUMODRST_WDS_WIDTH 1
1460
/* The mask used to set the ALT_RSTMGR_MPUMODRST_WDS register field value. */
1461
#define ALT_RSTMGR_MPUMODRST_WDS_SET_MSK 0x00000004
1462
/* The mask used to clear the ALT_RSTMGR_MPUMODRST_WDS register field value. */
1463
#define ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK 0xfffffffb
1464
/* The reset value of the ALT_RSTMGR_MPUMODRST_WDS register field. */
1465
#define ALT_RSTMGR_MPUMODRST_WDS_RESET 0x0
1466
/* Extracts the ALT_RSTMGR_MPUMODRST_WDS field value from a register. */
1467
#define ALT_RSTMGR_MPUMODRST_WDS_GET(value) (((value) & 0x00000004) >> 2)
1468
/* Produces a ALT_RSTMGR_MPUMODRST_WDS register field value suitable for setting the register. */
1469
#define ALT_RSTMGR_MPUMODRST_WDS_SET(value) (((value) << 2) & 0x00000004)
1470
1471
/*
1472
* Field : SCU/Peripherals - scuper
1473
*
1474
* Resets SCU and peripherals. Peripherals consist of the interrupt controller,
1475
* global timer, both per-CPU private timers, and both per-CPU watchdogs (except
1476
* for the Watchdog Reset Status registers).
1477
*
1478
* Field Access Macros:
1479
*
1480
*/
1481
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
1482
#define ALT_RSTMGR_MPUMODRST_SCUPER_LSB 3
1483
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
1484
#define ALT_RSTMGR_MPUMODRST_SCUPER_MSB 3
1485
/* The width in bits of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
1486
#define ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH 1
1487
/* The mask used to set the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */
1488
#define ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK 0x00000008
1489
/* The mask used to clear the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */
1490
#define ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK 0xfffffff7
1491
/* The reset value of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
1492
#define ALT_RSTMGR_MPUMODRST_SCUPER_RESET 0x0
1493
/* Extracts the ALT_RSTMGR_MPUMODRST_SCUPER field value from a register. */
1494
#define ALT_RSTMGR_MPUMODRST_SCUPER_GET(value) (((value) & 0x00000008) >> 3)
1495
/* Produces a ALT_RSTMGR_MPUMODRST_SCUPER register field value suitable for setting the register. */
1496
#define ALT_RSTMGR_MPUMODRST_SCUPER_SET(value) (((value) << 3) & 0x00000008)
1497
1498
/*
1499
* Field : L2 - l2
1500
*
1501
* Resets L2 cache controller
1502
*
1503
* Field Access Macros:
1504
*
1505
*/
1506
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */
1507
#define ALT_RSTMGR_MPUMODRST_L2_LSB 4
1508
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */
1509
#define ALT_RSTMGR_MPUMODRST_L2_MSB 4
1510
/* The width in bits of the ALT_RSTMGR_MPUMODRST_L2 register field. */
1511
#define ALT_RSTMGR_MPUMODRST_L2_WIDTH 1
1512
/* The mask used to set the ALT_RSTMGR_MPUMODRST_L2 register field value. */
1513
#define ALT_RSTMGR_MPUMODRST_L2_SET_MSK 0x00000010
1514
/* The mask used to clear the ALT_RSTMGR_MPUMODRST_L2 register field value. */
1515
#define ALT_RSTMGR_MPUMODRST_L2_CLR_MSK 0xffffffef
1516
/* The reset value of the ALT_RSTMGR_MPUMODRST_L2 register field. */
1517
#define ALT_RSTMGR_MPUMODRST_L2_RESET 0x0
1518
/* Extracts the ALT_RSTMGR_MPUMODRST_L2 field value from a register. */
1519
#define ALT_RSTMGR_MPUMODRST_L2_GET(value) (((value) & 0x00000010) >> 4)
1520
/* Produces a ALT_RSTMGR_MPUMODRST_L2 register field value suitable for setting the register. */
1521
#define ALT_RSTMGR_MPUMODRST_L2_SET(value) (((value) << 4) & 0x00000010)
1522
1523
#ifndef __ASSEMBLY__
1524
/*
1525
* WARNING: The C register and register group struct declarations are provided for
1526
* convenience and illustrative purposes. They should, however, be used with
1527
* caution as the C language standard provides no guarantees about the alignment or
1528
* atomicity of device memory accesses. The recommended practice for writing
1529
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
1530
* alt_write_word() functions.
1531
*
1532
* The struct declaration for register ALT_RSTMGR_MPUMODRST.
1533
*/
1534
struct
ALT_RSTMGR_MPUMODRST_s
1535
{
1536
uint32_t cpu0 : 1;
/* CPU0 */
1537
uint32_t cpu1 : 1;
/* CPU1 */
1538
uint32_t wds : 1;
/* Watchdogs */
1539
uint32_t scuper : 1;
/* SCU/Peripherals */
1540
uint32_t l2 : 1;
/* L2 */
1541
uint32_t : 27;
/* *UNDEFINED* */
1542
};
1543
1544
/* The typedef declaration for register ALT_RSTMGR_MPUMODRST. */
1545
typedef
volatile
struct
ALT_RSTMGR_MPUMODRST_s
ALT_RSTMGR_MPUMODRST_t;
1546
#endif
/* __ASSEMBLY__ */
1547
1548
/* The byte offset of the ALT_RSTMGR_MPUMODRST register from the beginning of the component. */
1549
#define ALT_RSTMGR_MPUMODRST_OFST 0x10
1550
1551
/*
1552
* Register : Peripheral Module Reset Register - permodrst
1553
*
1554
* The PERMODRST register is used by software to trigger module resets (individual
1555
* module reset signals). Software explicitly asserts and de-asserts module reset
1556
* signals by writing bits in the appropriate *MODRST register. It is up to
1557
* software to ensure module reset signals are asserted for the appropriate length
1558
* of time and are de-asserted in the correct order. It is also up to software to
1559
* not assert a module reset signal that would prevent software from de-asserting
1560
* the module reset signal. For example, software should not assert the module
1561
* reset to the CPU executing the software.
1562
*
1563
* Software writes a bit to 1 to assert the module reset signal and to 0 to de-
1564
* assert the module reset signal.
1565
*
1566
* All fields are reset by a cold reset.All fields are also reset by a warm reset
1567
* if not masked by the corresponding PERWARMMASK field.
1568
*
1569
* The reset value of all fields is 1. This holds the corresponding module in reset
1570
* until software is ready to release the module from reset by writing 0 to its
1571
* field.
1572
*
1573
* Register Layout
1574
*
1575
* Bits | Access | Reset | Description
1576
* :--------|:-------|:------|:---------------------------
1577
* [0] | RW | 0x1 | EMAC0
1578
* [1] | RW | 0x1 | EMAC1
1579
* [2] | RW | 0x1 | USB0
1580
* [3] | RW | 0x1 | USB1
1581
* [4] | RW | 0x1 | NAND Flash
1582
* [5] | RW | 0x1 | QSPI Flash
1583
* [6] | RW | 0x1 | L4 Watchdog 0
1584
* [7] | RW | 0x1 | L4 Watchdog 1
1585
* [8] | RW | 0x1 | OSC1 Timer 0
1586
* [9] | RW | 0x1 | OSC1 Timer 1
1587
* [10] | RW | 0x1 | SP Timer 0
1588
* [11] | RW | 0x1 | SP Timer 1
1589
* [12] | RW | 0x1 | I2C0
1590
* [13] | RW | 0x1 | I2C1
1591
* [14] | RW | 0x1 | I2C2
1592
* [15] | RW | 0x1 | I2C3
1593
* [16] | RW | 0x1 | UART0
1594
* [17] | RW | 0x1 | UART1
1595
* [18] | RW | 0x1 | SPIM0
1596
* [19] | RW | 0x1 | SPIM1
1597
* [20] | RW | 0x1 | SPIS0
1598
* [21] | RW | 0x1 | SPIS1
1599
* [22] | RW | 0x1 | SD/MMC
1600
* [23] | RW | 0x1 | CAN0
1601
* [24] | RW | 0x1 | CAN1
1602
* [25] | RW | 0x1 | GPIO0
1603
* [26] | RW | 0x1 | GPIO1
1604
* [27] | RW | 0x1 | GPIO2
1605
* [28] | RW | 0x1 | DMA Controller
1606
* [29] | RW | 0x1 | SDRAM Controller Subsystem
1607
* [31:30] | ??? | 0x0 | *UNDEFINED*
1608
*
1609
*/
1610
/*
1611
* Field : EMAC0 - emac0
1612
*
1613
* Resets EMAC0
1614
*
1615
* Field Access Macros:
1616
*
1617
*/
1618
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
1619
#define ALT_RSTMGR_PERMODRST_EMAC0_LSB 0
1620
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
1621
#define ALT_RSTMGR_PERMODRST_EMAC0_MSB 0
1622
/* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
1623
#define ALT_RSTMGR_PERMODRST_EMAC0_WIDTH 1
1624
/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */
1625
#define ALT_RSTMGR_PERMODRST_EMAC0_SET_MSK 0x00000001
1626
/* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */
1627
#define ALT_RSTMGR_PERMODRST_EMAC0_CLR_MSK 0xfffffffe
1628
/* The reset value of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
1629
#define ALT_RSTMGR_PERMODRST_EMAC0_RESET 0x1
1630
/* Extracts the ALT_RSTMGR_PERMODRST_EMAC0 field value from a register. */
1631
#define ALT_RSTMGR_PERMODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0)
1632
/* Produces a ALT_RSTMGR_PERMODRST_EMAC0 register field value suitable for setting the register. */
1633
#define ALT_RSTMGR_PERMODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001)
1634
1635
/*
1636
* Field : EMAC1 - emac1
1637
*
1638
* Resets EMAC1
1639
*
1640
* Field Access Macros:
1641
*
1642
*/
1643
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
1644
#define ALT_RSTMGR_PERMODRST_EMAC1_LSB 1
1645
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
1646
#define ALT_RSTMGR_PERMODRST_EMAC1_MSB 1
1647
/* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
1648
#define ALT_RSTMGR_PERMODRST_EMAC1_WIDTH 1
1649
/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */
1650
#define ALT_RSTMGR_PERMODRST_EMAC1_SET_MSK 0x00000002
1651
/* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */
1652
#define ALT_RSTMGR_PERMODRST_EMAC1_CLR_MSK 0xfffffffd
1653
/* The reset value of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
1654
#define ALT_RSTMGR_PERMODRST_EMAC1_RESET 0x1
1655
/* Extracts the ALT_RSTMGR_PERMODRST_EMAC1 field value from a register. */
1656
#define ALT_RSTMGR_PERMODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1)
1657
/* Produces a ALT_RSTMGR_PERMODRST_EMAC1 register field value suitable for setting the register. */
1658
#define ALT_RSTMGR_PERMODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002)
1659
1660
/*
1661
* Field : USB0 - usb0
1662
*
1663
* Resets USB0
1664
*
1665
* Field Access Macros:
1666
*
1667
*/
1668
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */
1669
#define ALT_RSTMGR_PERMODRST_USB0_LSB 2
1670
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */
1671
#define ALT_RSTMGR_PERMODRST_USB0_MSB 2
1672
/* The width in bits of the ALT_RSTMGR_PERMODRST_USB0 register field. */
1673
#define ALT_RSTMGR_PERMODRST_USB0_WIDTH 1
1674
/* The mask used to set the ALT_RSTMGR_PERMODRST_USB0 register field value. */
1675
#define ALT_RSTMGR_PERMODRST_USB0_SET_MSK 0x00000004
1676
/* The mask used to clear the ALT_RSTMGR_PERMODRST_USB0 register field value. */
1677
#define ALT_RSTMGR_PERMODRST_USB0_CLR_MSK 0xfffffffb
1678
/* The reset value of the ALT_RSTMGR_PERMODRST_USB0 register field. */
1679
#define ALT_RSTMGR_PERMODRST_USB0_RESET 0x1
1680
/* Extracts the ALT_RSTMGR_PERMODRST_USB0 field value from a register. */
1681
#define ALT_RSTMGR_PERMODRST_USB0_GET(value) (((value) & 0x00000004) >> 2)
1682
/* Produces a ALT_RSTMGR_PERMODRST_USB0 register field value suitable for setting the register. */
1683
#define ALT_RSTMGR_PERMODRST_USB0_SET(value) (((value) << 2) & 0x00000004)
1684
1685
/*
1686
* Field : USB1 - usb1
1687
*
1688
* Resets USB1
1689
*
1690
* Field Access Macros:
1691
*
1692
*/
1693
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */
1694
#define ALT_RSTMGR_PERMODRST_USB1_LSB 3
1695
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */
1696
#define ALT_RSTMGR_PERMODRST_USB1_MSB 3
1697
/* The width in bits of the ALT_RSTMGR_PERMODRST_USB1 register field. */
1698
#define ALT_RSTMGR_PERMODRST_USB1_WIDTH 1
1699
/* The mask used to set the ALT_RSTMGR_PERMODRST_USB1 register field value. */
1700
#define ALT_RSTMGR_PERMODRST_USB1_SET_MSK 0x00000008
1701
/* The mask used to clear the ALT_RSTMGR_PERMODRST_USB1 register field value. */
1702
#define ALT_RSTMGR_PERMODRST_USB1_CLR_MSK 0xfffffff7
1703
/* The reset value of the ALT_RSTMGR_PERMODRST_USB1 register field. */
1704
#define ALT_RSTMGR_PERMODRST_USB1_RESET 0x1
1705
/* Extracts the ALT_RSTMGR_PERMODRST_USB1 field value from a register. */
1706
#define ALT_RSTMGR_PERMODRST_USB1_GET(value) (((value) & 0x00000008) >> 3)
1707
/* Produces a ALT_RSTMGR_PERMODRST_USB1 register field value suitable for setting the register. */
1708
#define ALT_RSTMGR_PERMODRST_USB1_SET(value) (((value) << 3) & 0x00000008)
1709
1710
/*
1711
* Field : NAND Flash - nand
1712
*
1713
* Resets NAND flash controller
1714
*
1715
* Field Access Macros:
1716
*
1717
*/
1718
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */
1719
#define ALT_RSTMGR_PERMODRST_NAND_LSB 4
1720
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */
1721
#define ALT_RSTMGR_PERMODRST_NAND_MSB 4
1722
/* The width in bits of the ALT_RSTMGR_PERMODRST_NAND register field. */
1723
#define ALT_RSTMGR_PERMODRST_NAND_WIDTH 1
1724
/* The mask used to set the ALT_RSTMGR_PERMODRST_NAND register field value. */
1725
#define ALT_RSTMGR_PERMODRST_NAND_SET_MSK 0x00000010
1726
/* The mask used to clear the ALT_RSTMGR_PERMODRST_NAND register field value. */
1727
#define ALT_RSTMGR_PERMODRST_NAND_CLR_MSK 0xffffffef
1728
/* The reset value of the ALT_RSTMGR_PERMODRST_NAND register field. */
1729
#define ALT_RSTMGR_PERMODRST_NAND_RESET 0x1
1730
/* Extracts the ALT_RSTMGR_PERMODRST_NAND field value from a register. */
1731
#define ALT_RSTMGR_PERMODRST_NAND_GET(value) (((value) & 0x00000010) >> 4)
1732
/* Produces a ALT_RSTMGR_PERMODRST_NAND register field value suitable for setting the register. */
1733
#define ALT_RSTMGR_PERMODRST_NAND_SET(value) (((value) << 4) & 0x00000010)
1734
1735
/*
1736
* Field : QSPI Flash - qspi
1737
*
1738
* Resets QSPI flash controller
1739
*
1740
* Field Access Macros:
1741
*
1742
*/
1743
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */
1744
#define ALT_RSTMGR_PERMODRST_QSPI_LSB 5
1745
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */
1746
#define ALT_RSTMGR_PERMODRST_QSPI_MSB 5
1747
/* The width in bits of the ALT_RSTMGR_PERMODRST_QSPI register field. */
1748
#define ALT_RSTMGR_PERMODRST_QSPI_WIDTH 1
1749
/* The mask used to set the ALT_RSTMGR_PERMODRST_QSPI register field value. */
1750
#define ALT_RSTMGR_PERMODRST_QSPI_SET_MSK 0x00000020
1751
/* The mask used to clear the ALT_RSTMGR_PERMODRST_QSPI register field value. */
1752
#define ALT_RSTMGR_PERMODRST_QSPI_CLR_MSK 0xffffffdf
1753
/* The reset value of the ALT_RSTMGR_PERMODRST_QSPI register field. */
1754
#define ALT_RSTMGR_PERMODRST_QSPI_RESET 0x1
1755
/* Extracts the ALT_RSTMGR_PERMODRST_QSPI field value from a register. */
1756
#define ALT_RSTMGR_PERMODRST_QSPI_GET(value) (((value) & 0x00000020) >> 5)
1757
/* Produces a ALT_RSTMGR_PERMODRST_QSPI register field value suitable for setting the register. */
1758
#define ALT_RSTMGR_PERMODRST_QSPI_SET(value) (((value) << 5) & 0x00000020)
1759
1760
/*
1761
* Field : L4 Watchdog 0 - l4wd0
1762
*
1763
* Resets watchdog 0 connected to L4
1764
*
1765
* Field Access Macros:
1766
*
1767
*/
1768
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
1769
#define ALT_RSTMGR_PERMODRST_L4WD0_LSB 6
1770
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
1771
#define ALT_RSTMGR_PERMODRST_L4WD0_MSB 6
1772
/* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
1773
#define ALT_RSTMGR_PERMODRST_L4WD0_WIDTH 1
1774
/* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */
1775
#define ALT_RSTMGR_PERMODRST_L4WD0_SET_MSK 0x00000040
1776
/* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */
1777
#define ALT_RSTMGR_PERMODRST_L4WD0_CLR_MSK 0xffffffbf
1778
/* The reset value of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
1779
#define ALT_RSTMGR_PERMODRST_L4WD0_RESET 0x1
1780
/* Extracts the ALT_RSTMGR_PERMODRST_L4WD0 field value from a register. */
1781
#define ALT_RSTMGR_PERMODRST_L4WD0_GET(value) (((value) & 0x00000040) >> 6)
1782
/* Produces a ALT_RSTMGR_PERMODRST_L4WD0 register field value suitable for setting the register. */
1783
#define ALT_RSTMGR_PERMODRST_L4WD0_SET(value) (((value) << 6) & 0x00000040)
1784
1785
/*
1786
* Field : L4 Watchdog 1 - l4wd1
1787
*
1788
* Resets watchdog 1 connected to L4
1789
*
1790
* Field Access Macros:
1791
*
1792
*/
1793
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
1794
#define ALT_RSTMGR_PERMODRST_L4WD1_LSB 7
1795
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
1796
#define ALT_RSTMGR_PERMODRST_L4WD1_MSB 7
1797
/* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
1798
#define ALT_RSTMGR_PERMODRST_L4WD1_WIDTH 1
1799
/* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */
1800
#define ALT_RSTMGR_PERMODRST_L4WD1_SET_MSK 0x00000080
1801
/* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */
1802
#define ALT_RSTMGR_PERMODRST_L4WD1_CLR_MSK 0xffffff7f
1803
/* The reset value of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
1804
#define ALT_RSTMGR_PERMODRST_L4WD1_RESET 0x1
1805
/* Extracts the ALT_RSTMGR_PERMODRST_L4WD1 field value from a register. */
1806
#define ALT_RSTMGR_PERMODRST_L4WD1_GET(value) (((value) & 0x00000080) >> 7)
1807
/* Produces a ALT_RSTMGR_PERMODRST_L4WD1 register field value suitable for setting the register. */
1808
#define ALT_RSTMGR_PERMODRST_L4WD1_SET(value) (((value) << 7) & 0x00000080)
1809
1810
/*
1811
* Field : OSC1 Timer 0 - osc1timer0
1812
*
1813
* Resets OSC1 timer 0 connected to L4
1814
*
1815
* Field Access Macros:
1816
*
1817
*/
1818
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
1819
#define ALT_RSTMGR_PERMODRST_OSC1TMR0_LSB 8
1820
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
1821
#define ALT_RSTMGR_PERMODRST_OSC1TMR0_MSB 8
1822
/* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
1823
#define ALT_RSTMGR_PERMODRST_OSC1TMR0_WIDTH 1
1824
/* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */
1825
#define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET_MSK 0x00000100
1826
/* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */
1827
#define ALT_RSTMGR_PERMODRST_OSC1TMR0_CLR_MSK 0xfffffeff
1828
/* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
1829
#define ALT_RSTMGR_PERMODRST_OSC1TMR0_RESET 0x1
1830
/* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR0 field value from a register. */
1831
#define ALT_RSTMGR_PERMODRST_OSC1TMR0_GET(value) (((value) & 0x00000100) >> 8)
1832
/* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value suitable for setting the register. */
1833
#define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET(value) (((value) << 8) & 0x00000100)
1834
1835
/*
1836
* Field : OSC1 Timer 1 - osc1timer1
1837
*
1838
* Resets OSC1 timer 1 connected to L4
1839
*
1840
* Field Access Macros:
1841
*
1842
*/
1843
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
1844
#define ALT_RSTMGR_PERMODRST_OSC1TMR1_LSB 9
1845
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
1846
#define ALT_RSTMGR_PERMODRST_OSC1TMR1_MSB 9
1847
/* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
1848
#define ALT_RSTMGR_PERMODRST_OSC1TMR1_WIDTH 1
1849
/* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */
1850
#define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET_MSK 0x00000200
1851
/* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */
1852
#define ALT_RSTMGR_PERMODRST_OSC1TMR1_CLR_MSK 0xfffffdff
1853
/* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
1854
#define ALT_RSTMGR_PERMODRST_OSC1TMR1_RESET 0x1
1855
/* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR1 field value from a register. */
1856
#define ALT_RSTMGR_PERMODRST_OSC1TMR1_GET(value) (((value) & 0x00000200) >> 9)
1857
/* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value suitable for setting the register. */
1858
#define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET(value) (((value) << 9) & 0x00000200)
1859
1860
/*
1861
* Field : SP Timer 0 - sptimer0
1862
*
1863
* Resets SP timer 0 connected to L4
1864
*
1865
* Field Access Macros:
1866
*
1867
*/
1868
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
1869
#define ALT_RSTMGR_PERMODRST_SPTMR0_LSB 10
1870
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
1871
#define ALT_RSTMGR_PERMODRST_SPTMR0_MSB 10
1872
/* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
1873
#define ALT_RSTMGR_PERMODRST_SPTMR0_WIDTH 1
1874
/* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */
1875
#define ALT_RSTMGR_PERMODRST_SPTMR0_SET_MSK 0x00000400
1876
/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */
1877
#define ALT_RSTMGR_PERMODRST_SPTMR0_CLR_MSK 0xfffffbff
1878
/* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
1879
#define ALT_RSTMGR_PERMODRST_SPTMR0_RESET 0x1
1880
/* Extracts the ALT_RSTMGR_PERMODRST_SPTMR0 field value from a register. */
1881
#define ALT_RSTMGR_PERMODRST_SPTMR0_GET(value) (((value) & 0x00000400) >> 10)
1882
/* Produces a ALT_RSTMGR_PERMODRST_SPTMR0 register field value suitable for setting the register. */
1883
#define ALT_RSTMGR_PERMODRST_SPTMR0_SET(value) (((value) << 10) & 0x00000400)
1884
1885
/*
1886
* Field : SP Timer 1 - sptimer1
1887
*
1888
* Resets SP timer 1 connected to L4
1889
*
1890
* Field Access Macros:
1891
*
1892
*/
1893
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
1894
#define ALT_RSTMGR_PERMODRST_SPTMR1_LSB 11
1895
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
1896
#define ALT_RSTMGR_PERMODRST_SPTMR1_MSB 11
1897
/* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
1898
#define ALT_RSTMGR_PERMODRST_SPTMR1_WIDTH 1
1899
/* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */
1900
#define ALT_RSTMGR_PERMODRST_SPTMR1_SET_MSK 0x00000800
1901
/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */
1902
#define ALT_RSTMGR_PERMODRST_SPTMR1_CLR_MSK 0xfffff7ff
1903
/* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
1904
#define ALT_RSTMGR_PERMODRST_SPTMR1_RESET 0x1
1905
/* Extracts the ALT_RSTMGR_PERMODRST_SPTMR1 field value from a register. */
1906
#define ALT_RSTMGR_PERMODRST_SPTMR1_GET(value) (((value) & 0x00000800) >> 11)
1907
/* Produces a ALT_RSTMGR_PERMODRST_SPTMR1 register field value suitable for setting the register. */
1908
#define ALT_RSTMGR_PERMODRST_SPTMR1_SET(value) (((value) << 11) & 0x00000800)
1909
1910
/*
1911
* Field : I2C0 - i2c0
1912
*
1913
* Resets I2C0 controller
1914
*
1915
* Field Access Macros:
1916
*
1917
*/
1918
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
1919
#define ALT_RSTMGR_PERMODRST_I2C0_LSB 12
1920
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
1921
#define ALT_RSTMGR_PERMODRST_I2C0_MSB 12
1922
/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
1923
#define ALT_RSTMGR_PERMODRST_I2C0_WIDTH 1
1924
/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C0 register field value. */
1925
#define ALT_RSTMGR_PERMODRST_I2C0_SET_MSK 0x00001000
1926
/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C0 register field value. */
1927
#define ALT_RSTMGR_PERMODRST_I2C0_CLR_MSK 0xffffefff
1928
/* The reset value of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
1929
#define ALT_RSTMGR_PERMODRST_I2C0_RESET 0x1
1930
/* Extracts the ALT_RSTMGR_PERMODRST_I2C0 field value from a register. */
1931
#define ALT_RSTMGR_PERMODRST_I2C0_GET(value) (((value) & 0x00001000) >> 12)
1932
/* Produces a ALT_RSTMGR_PERMODRST_I2C0 register field value suitable for setting the register. */
1933
#define ALT_RSTMGR_PERMODRST_I2C0_SET(value) (((value) << 12) & 0x00001000)
1934
1935
/*
1936
* Field : I2C1 - i2c1
1937
*
1938
* Resets I2C1 controller
1939
*
1940
* Field Access Macros:
1941
*
1942
*/
1943
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
1944
#define ALT_RSTMGR_PERMODRST_I2C1_LSB 13
1945
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
1946
#define ALT_RSTMGR_PERMODRST_I2C1_MSB 13
1947
/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
1948
#define ALT_RSTMGR_PERMODRST_I2C1_WIDTH 1
1949
/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C1 register field value. */
1950
#define ALT_RSTMGR_PERMODRST_I2C1_SET_MSK 0x00002000
1951
/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C1 register field value. */
1952
#define ALT_RSTMGR_PERMODRST_I2C1_CLR_MSK 0xffffdfff
1953
/* The reset value of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
1954
#define ALT_RSTMGR_PERMODRST_I2C1_RESET 0x1
1955
/* Extracts the ALT_RSTMGR_PERMODRST_I2C1 field value from a register. */
1956
#define ALT_RSTMGR_PERMODRST_I2C1_GET(value) (((value) & 0x00002000) >> 13)
1957
/* Produces a ALT_RSTMGR_PERMODRST_I2C1 register field value suitable for setting the register. */
1958
#define ALT_RSTMGR_PERMODRST_I2C1_SET(value) (((value) << 13) & 0x00002000)
1959
1960
/*
1961
* Field : I2C2 - i2c2
1962
*
1963
* Resets I2C2 controller
1964
*
1965
* Field Access Macros:
1966
*
1967
*/
1968
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
1969
#define ALT_RSTMGR_PERMODRST_I2C2_LSB 14
1970
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
1971
#define ALT_RSTMGR_PERMODRST_I2C2_MSB 14
1972
/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
1973
#define ALT_RSTMGR_PERMODRST_I2C2_WIDTH 1
1974
/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C2 register field value. */
1975
#define ALT_RSTMGR_PERMODRST_I2C2_SET_MSK 0x00004000
1976
/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C2 register field value. */
1977
#define ALT_RSTMGR_PERMODRST_I2C2_CLR_MSK 0xffffbfff
1978
/* The reset value of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
1979
#define ALT_RSTMGR_PERMODRST_I2C2_RESET 0x1
1980
/* Extracts the ALT_RSTMGR_PERMODRST_I2C2 field value from a register. */
1981
#define ALT_RSTMGR_PERMODRST_I2C2_GET(value) (((value) & 0x00004000) >> 14)
1982
/* Produces a ALT_RSTMGR_PERMODRST_I2C2 register field value suitable for setting the register. */
1983
#define ALT_RSTMGR_PERMODRST_I2C2_SET(value) (((value) << 14) & 0x00004000)
1984
1985
/*
1986
* Field : I2C3 - i2c3
1987
*
1988
* Resets I2C3 controller
1989
*
1990
* Field Access Macros:
1991
*
1992
*/
1993
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
1994
#define ALT_RSTMGR_PERMODRST_I2C3_LSB 15
1995
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
1996
#define ALT_RSTMGR_PERMODRST_I2C3_MSB 15
1997
/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
1998
#define ALT_RSTMGR_PERMODRST_I2C3_WIDTH 1
1999
/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C3 register field value. */
2000
#define ALT_RSTMGR_PERMODRST_I2C3_SET_MSK 0x00008000
2001
/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C3 register field value. */
2002
#define ALT_RSTMGR_PERMODRST_I2C3_CLR_MSK 0xffff7fff
2003
/* The reset value of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
2004
#define ALT_RSTMGR_PERMODRST_I2C3_RESET 0x1
2005
/* Extracts the ALT_RSTMGR_PERMODRST_I2C3 field value from a register. */
2006
#define ALT_RSTMGR_PERMODRST_I2C3_GET(value) (((value) & 0x00008000) >> 15)
2007
/* Produces a ALT_RSTMGR_PERMODRST_I2C3 register field value suitable for setting the register. */
2008
#define ALT_RSTMGR_PERMODRST_I2C3_SET(value) (((value) << 15) & 0x00008000)
2009
2010
/*
2011
* Field : UART0 - uart0
2012
*
2013
* Resets UART0
2014
*
2015
* Field Access Macros:
2016
*
2017
*/
2018
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */
2019
#define ALT_RSTMGR_PERMODRST_UART0_LSB 16
2020
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */
2021
#define ALT_RSTMGR_PERMODRST_UART0_MSB 16
2022
/* The width in bits of the ALT_RSTMGR_PERMODRST_UART0 register field. */
2023
#define ALT_RSTMGR_PERMODRST_UART0_WIDTH 1
2024
/* The mask used to set the ALT_RSTMGR_PERMODRST_UART0 register field value. */
2025
#define ALT_RSTMGR_PERMODRST_UART0_SET_MSK 0x00010000
2026
/* The mask used to clear the ALT_RSTMGR_PERMODRST_UART0 register field value. */
2027
#define ALT_RSTMGR_PERMODRST_UART0_CLR_MSK 0xfffeffff
2028
/* The reset value of the ALT_RSTMGR_PERMODRST_UART0 register field. */
2029
#define ALT_RSTMGR_PERMODRST_UART0_RESET 0x1
2030
/* Extracts the ALT_RSTMGR_PERMODRST_UART0 field value from a register. */
2031
#define ALT_RSTMGR_PERMODRST_UART0_GET(value) (((value) & 0x00010000) >> 16)
2032
/* Produces a ALT_RSTMGR_PERMODRST_UART0 register field value suitable for setting the register. */
2033
#define ALT_RSTMGR_PERMODRST_UART0_SET(value) (((value) << 16) & 0x00010000)
2034
2035
/*
2036
* Field : UART1 - uart1
2037
*
2038
* Resets UART1
2039
*
2040
* Field Access Macros:
2041
*
2042
*/
2043
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */
2044
#define ALT_RSTMGR_PERMODRST_UART1_LSB 17
2045
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */
2046
#define ALT_RSTMGR_PERMODRST_UART1_MSB 17
2047
/* The width in bits of the ALT_RSTMGR_PERMODRST_UART1 register field. */
2048
#define ALT_RSTMGR_PERMODRST_UART1_WIDTH 1
2049
/* The mask used to set the ALT_RSTMGR_PERMODRST_UART1 register field value. */
2050
#define ALT_RSTMGR_PERMODRST_UART1_SET_MSK 0x00020000
2051
/* The mask used to clear the ALT_RSTMGR_PERMODRST_UART1 register field value. */
2052
#define ALT_RSTMGR_PERMODRST_UART1_CLR_MSK 0xfffdffff
2053
/* The reset value of the ALT_RSTMGR_PERMODRST_UART1 register field. */
2054
#define ALT_RSTMGR_PERMODRST_UART1_RESET 0x1
2055
/* Extracts the ALT_RSTMGR_PERMODRST_UART1 field value from a register. */
2056
#define ALT_RSTMGR_PERMODRST_UART1_GET(value) (((value) & 0x00020000) >> 17)
2057
/* Produces a ALT_RSTMGR_PERMODRST_UART1 register field value suitable for setting the register. */
2058
#define ALT_RSTMGR_PERMODRST_UART1_SET(value) (((value) << 17) & 0x00020000)
2059
2060
/*
2061
* Field : SPIM0 - spim0
2062
*
2063
* Resets SPIM0 controller
2064
*
2065
* Field Access Macros:
2066
*
2067
*/
2068
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
2069
#define ALT_RSTMGR_PERMODRST_SPIM0_LSB 18
2070
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
2071
#define ALT_RSTMGR_PERMODRST_SPIM0_MSB 18
2072
/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
2073
#define ALT_RSTMGR_PERMODRST_SPIM0_WIDTH 1
2074
/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */
2075
#define ALT_RSTMGR_PERMODRST_SPIM0_SET_MSK 0x00040000
2076
/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */
2077
#define ALT_RSTMGR_PERMODRST_SPIM0_CLR_MSK 0xfffbffff
2078
/* The reset value of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
2079
#define ALT_RSTMGR_PERMODRST_SPIM0_RESET 0x1
2080
/* Extracts the ALT_RSTMGR_PERMODRST_SPIM0 field value from a register. */
2081
#define ALT_RSTMGR_PERMODRST_SPIM0_GET(value) (((value) & 0x00040000) >> 18)
2082
/* Produces a ALT_RSTMGR_PERMODRST_SPIM0 register field value suitable for setting the register. */
2083
#define ALT_RSTMGR_PERMODRST_SPIM0_SET(value) (((value) << 18) & 0x00040000)
2084
2085
/*
2086
* Field : SPIM1 - spim1
2087
*
2088
* Resets SPIM1 controller
2089
*
2090
* Field Access Macros:
2091
*
2092
*/
2093
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
2094
#define ALT_RSTMGR_PERMODRST_SPIM1_LSB 19
2095
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
2096
#define ALT_RSTMGR_PERMODRST_SPIM1_MSB 19
2097
/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
2098
#define ALT_RSTMGR_PERMODRST_SPIM1_WIDTH 1
2099
/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */
2100
#define ALT_RSTMGR_PERMODRST_SPIM1_SET_MSK 0x00080000
2101
/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */
2102
#define ALT_RSTMGR_PERMODRST_SPIM1_CLR_MSK 0xfff7ffff
2103
/* The reset value of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
2104
#define ALT_RSTMGR_PERMODRST_SPIM1_RESET 0x1
2105
/* Extracts the ALT_RSTMGR_PERMODRST_SPIM1 field value from a register. */
2106
#define ALT_RSTMGR_PERMODRST_SPIM1_GET(value) (((value) & 0x00080000) >> 19)
2107
/* Produces a ALT_RSTMGR_PERMODRST_SPIM1 register field value suitable for setting the register. */
2108
#define ALT_RSTMGR_PERMODRST_SPIM1_SET(value) (((value) << 19) & 0x00080000)
2109
2110
/*
2111
* Field : SPIS0 - spis0
2112
*
2113
* Resets SPIS0 controller
2114
*
2115
* Field Access Macros:
2116
*
2117
*/
2118
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
2119
#define ALT_RSTMGR_PERMODRST_SPIS0_LSB 20
2120
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
2121
#define ALT_RSTMGR_PERMODRST_SPIS0_MSB 20
2122
/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
2123
#define ALT_RSTMGR_PERMODRST_SPIS0_WIDTH 1
2124
/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */
2125
#define ALT_RSTMGR_PERMODRST_SPIS0_SET_MSK 0x00100000
2126
/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */
2127
#define ALT_RSTMGR_PERMODRST_SPIS0_CLR_MSK 0xffefffff
2128
/* The reset value of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
2129
#define ALT_RSTMGR_PERMODRST_SPIS0_RESET 0x1
2130
/* Extracts the ALT_RSTMGR_PERMODRST_SPIS0 field value from a register. */
2131
#define ALT_RSTMGR_PERMODRST_SPIS0_GET(value) (((value) & 0x00100000) >> 20)
2132
/* Produces a ALT_RSTMGR_PERMODRST_SPIS0 register field value suitable for setting the register. */
2133
#define ALT_RSTMGR_PERMODRST_SPIS0_SET(value) (((value) << 20) & 0x00100000)
2134
2135
/*
2136
* Field : SPIS1 - spis1
2137
*
2138
* Resets SPIS1 controller
2139
*
2140
* Field Access Macros:
2141
*
2142
*/
2143
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
2144
#define ALT_RSTMGR_PERMODRST_SPIS1_LSB 21
2145
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
2146
#define ALT_RSTMGR_PERMODRST_SPIS1_MSB 21
2147
/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
2148
#define ALT_RSTMGR_PERMODRST_SPIS1_WIDTH 1
2149
/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */
2150
#define ALT_RSTMGR_PERMODRST_SPIS1_SET_MSK 0x00200000
2151
/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */
2152
#define ALT_RSTMGR_PERMODRST_SPIS1_CLR_MSK 0xffdfffff
2153
/* The reset value of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
2154
#define ALT_RSTMGR_PERMODRST_SPIS1_RESET 0x1
2155
/* Extracts the ALT_RSTMGR_PERMODRST_SPIS1 field value from a register. */
2156
#define ALT_RSTMGR_PERMODRST_SPIS1_GET(value) (((value) & 0x00200000) >> 21)
2157
/* Produces a ALT_RSTMGR_PERMODRST_SPIS1 register field value suitable for setting the register. */
2158
#define ALT_RSTMGR_PERMODRST_SPIS1_SET(value) (((value) << 21) & 0x00200000)
2159
2160
/*
2161
* Field : SD/MMC - sdmmc
2162
*
2163
* Resets SD/MMC controller
2164
*
2165
* Field Access Macros:
2166
*
2167
*/
2168
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
2169
#define ALT_RSTMGR_PERMODRST_SDMMC_LSB 22
2170
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
2171
#define ALT_RSTMGR_PERMODRST_SDMMC_MSB 22
2172
/* The width in bits of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
2173
#define ALT_RSTMGR_PERMODRST_SDMMC_WIDTH 1
2174
/* The mask used to set the ALT_RSTMGR_PERMODRST_SDMMC register field value. */
2175
#define ALT_RSTMGR_PERMODRST_SDMMC_SET_MSK 0x00400000
2176
/* The mask used to clear the ALT_RSTMGR_PERMODRST_SDMMC register field value. */
2177
#define ALT_RSTMGR_PERMODRST_SDMMC_CLR_MSK 0xffbfffff
2178
/* The reset value of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
2179
#define ALT_RSTMGR_PERMODRST_SDMMC_RESET 0x1
2180
/* Extracts the ALT_RSTMGR_PERMODRST_SDMMC field value from a register. */
2181
#define ALT_RSTMGR_PERMODRST_SDMMC_GET(value) (((value) & 0x00400000) >> 22)
2182
/* Produces a ALT_RSTMGR_PERMODRST_SDMMC register field value suitable for setting the register. */
2183
#define ALT_RSTMGR_PERMODRST_SDMMC_SET(value) (((value) << 22) & 0x00400000)
2184
2185
/*
2186
* Field : CAN0 - can0
2187
*
2188
* Resets CAN0 controller.
2189
*
2190
* Writes to this field on devices not containing CAN controllers will be ignored.
2191
*
2192
* Field Access Macros:
2193
*
2194
*/
2195
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
2196
#define ALT_RSTMGR_PERMODRST_CAN0_LSB 23
2197
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
2198
#define ALT_RSTMGR_PERMODRST_CAN0_MSB 23
2199
/* The width in bits of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
2200
#define ALT_RSTMGR_PERMODRST_CAN0_WIDTH 1
2201
/* The mask used to set the ALT_RSTMGR_PERMODRST_CAN0 register field value. */
2202
#define ALT_RSTMGR_PERMODRST_CAN0_SET_MSK 0x00800000
2203
/* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN0 register field value. */
2204
#define ALT_RSTMGR_PERMODRST_CAN0_CLR_MSK 0xff7fffff
2205
/* The reset value of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
2206
#define ALT_RSTMGR_PERMODRST_CAN0_RESET 0x1
2207
/* Extracts the ALT_RSTMGR_PERMODRST_CAN0 field value from a register. */
2208
#define ALT_RSTMGR_PERMODRST_CAN0_GET(value) (((value) & 0x00800000) >> 23)
2209
/* Produces a ALT_RSTMGR_PERMODRST_CAN0 register field value suitable for setting the register. */
2210
#define ALT_RSTMGR_PERMODRST_CAN0_SET(value) (((value) << 23) & 0x00800000)
2211
2212
/*
2213
* Field : CAN1 - can1
2214
*
2215
* Resets CAN1 controller.
2216
*
2217
* Writes to this field on devices not containing CAN controllers will be ignored.
2218
*
2219
* Field Access Macros:
2220
*
2221
*/
2222
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
2223
#define ALT_RSTMGR_PERMODRST_CAN1_LSB 24
2224
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
2225
#define ALT_RSTMGR_PERMODRST_CAN1_MSB 24
2226
/* The width in bits of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
2227
#define ALT_RSTMGR_PERMODRST_CAN1_WIDTH 1
2228
/* The mask used to set the ALT_RSTMGR_PERMODRST_CAN1 register field value. */
2229
#define ALT_RSTMGR_PERMODRST_CAN1_SET_MSK 0x01000000
2230
/* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN1 register field value. */
2231
#define ALT_RSTMGR_PERMODRST_CAN1_CLR_MSK 0xfeffffff
2232
/* The reset value of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
2233
#define ALT_RSTMGR_PERMODRST_CAN1_RESET 0x1
2234
/* Extracts the ALT_RSTMGR_PERMODRST_CAN1 field value from a register. */
2235
#define ALT_RSTMGR_PERMODRST_CAN1_GET(value) (((value) & 0x01000000) >> 24)
2236
/* Produces a ALT_RSTMGR_PERMODRST_CAN1 register field value suitable for setting the register. */
2237
#define ALT_RSTMGR_PERMODRST_CAN1_SET(value) (((value) << 24) & 0x01000000)
2238
2239
/*
2240
* Field : GPIO0 - gpio0
2241
*
2242
* Resets GPIO0
2243
*
2244
* Field Access Macros:
2245
*
2246
*/
2247
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
2248
#define ALT_RSTMGR_PERMODRST_GPIO0_LSB 25
2249
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
2250
#define ALT_RSTMGR_PERMODRST_GPIO0_MSB 25
2251
/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
2252
#define ALT_RSTMGR_PERMODRST_GPIO0_WIDTH 1
2253
/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */
2254
#define ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK 0x02000000
2255
/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */
2256
#define ALT_RSTMGR_PERMODRST_GPIO0_CLR_MSK 0xfdffffff
2257
/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
2258
#define ALT_RSTMGR_PERMODRST_GPIO0_RESET 0x1
2259
/* Extracts the ALT_RSTMGR_PERMODRST_GPIO0 field value from a register. */
2260
#define ALT_RSTMGR_PERMODRST_GPIO0_GET(value) (((value) & 0x02000000) >> 25)
2261
/* Produces a ALT_RSTMGR_PERMODRST_GPIO0 register field value suitable for setting the register. */
2262
#define ALT_RSTMGR_PERMODRST_GPIO0_SET(value) (((value) << 25) & 0x02000000)
2263
2264
/*
2265
* Field : GPIO1 - gpio1
2266
*
2267
* Resets GPIO1
2268
*
2269
* Field Access Macros:
2270
*
2271
*/
2272
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
2273
#define ALT_RSTMGR_PERMODRST_GPIO1_LSB 26
2274
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
2275
#define ALT_RSTMGR_PERMODRST_GPIO1_MSB 26
2276
/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
2277
#define ALT_RSTMGR_PERMODRST_GPIO1_WIDTH 1
2278
/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */
2279
#define ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK 0x04000000
2280
/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */
2281
#define ALT_RSTMGR_PERMODRST_GPIO1_CLR_MSK 0xfbffffff
2282
/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
2283
#define ALT_RSTMGR_PERMODRST_GPIO1_RESET 0x1
2284
/* Extracts the ALT_RSTMGR_PERMODRST_GPIO1 field value from a register. */
2285
#define ALT_RSTMGR_PERMODRST_GPIO1_GET(value) (((value) & 0x04000000) >> 26)
2286
/* Produces a ALT_RSTMGR_PERMODRST_GPIO1 register field value suitable for setting the register. */
2287
#define ALT_RSTMGR_PERMODRST_GPIO1_SET(value) (((value) << 26) & 0x04000000)
2288
2289
/*
2290
* Field : GPIO2 - gpio2
2291
*
2292
* Resets GPIO2
2293
*
2294
* Field Access Macros:
2295
*
2296
*/
2297
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
2298
#define ALT_RSTMGR_PERMODRST_GPIO2_LSB 27
2299
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
2300
#define ALT_RSTMGR_PERMODRST_GPIO2_MSB 27
2301
/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
2302
#define ALT_RSTMGR_PERMODRST_GPIO2_WIDTH 1
2303
/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */
2304
#define ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK 0x08000000
2305
/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */
2306
#define ALT_RSTMGR_PERMODRST_GPIO2_CLR_MSK 0xf7ffffff
2307
/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
2308
#define ALT_RSTMGR_PERMODRST_GPIO2_RESET 0x1
2309
/* Extracts the ALT_RSTMGR_PERMODRST_GPIO2 field value from a register. */
2310
#define ALT_RSTMGR_PERMODRST_GPIO2_GET(value) (((value) & 0x08000000) >> 27)
2311
/* Produces a ALT_RSTMGR_PERMODRST_GPIO2 register field value suitable for setting the register. */
2312
#define ALT_RSTMGR_PERMODRST_GPIO2_SET(value) (((value) << 27) & 0x08000000)
2313
2314
/*
2315
* Field : DMA Controller - dma
2316
*
2317
* Resets DMA controller
2318
*
2319
* Field Access Macros:
2320
*
2321
*/
2322
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */
2323
#define ALT_RSTMGR_PERMODRST_DMA_LSB 28
2324
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */
2325
#define ALT_RSTMGR_PERMODRST_DMA_MSB 28
2326
/* The width in bits of the ALT_RSTMGR_PERMODRST_DMA register field. */
2327
#define ALT_RSTMGR_PERMODRST_DMA_WIDTH 1
2328
/* The mask used to set the ALT_RSTMGR_PERMODRST_DMA register field value. */
2329
#define ALT_RSTMGR_PERMODRST_DMA_SET_MSK 0x10000000
2330
/* The mask used to clear the ALT_RSTMGR_PERMODRST_DMA register field value. */
2331
#define ALT_RSTMGR_PERMODRST_DMA_CLR_MSK 0xefffffff
2332
/* The reset value of the ALT_RSTMGR_PERMODRST_DMA register field. */
2333
#define ALT_RSTMGR_PERMODRST_DMA_RESET 0x1
2334
/* Extracts the ALT_RSTMGR_PERMODRST_DMA field value from a register. */
2335
#define ALT_RSTMGR_PERMODRST_DMA_GET(value) (((value) & 0x10000000) >> 28)
2336
/* Produces a ALT_RSTMGR_PERMODRST_DMA register field value suitable for setting the register. */
2337
#define ALT_RSTMGR_PERMODRST_DMA_SET(value) (((value) << 28) & 0x10000000)
2338
2339
/*
2340
* Field : SDRAM Controller Subsystem - sdr
2341
*
2342
* Resets SDRAM Controller Subsystem affected by a warm or cold reset.
2343
*
2344
* Field Access Macros:
2345
*
2346
*/
2347
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */
2348
#define ALT_RSTMGR_PERMODRST_SDR_LSB 29
2349
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */
2350
#define ALT_RSTMGR_PERMODRST_SDR_MSB 29
2351
/* The width in bits of the ALT_RSTMGR_PERMODRST_SDR register field. */
2352
#define ALT_RSTMGR_PERMODRST_SDR_WIDTH 1
2353
/* The mask used to set the ALT_RSTMGR_PERMODRST_SDR register field value. */
2354
#define ALT_RSTMGR_PERMODRST_SDR_SET_MSK 0x20000000
2355
/* The mask used to clear the ALT_RSTMGR_PERMODRST_SDR register field value. */
2356
#define ALT_RSTMGR_PERMODRST_SDR_CLR_MSK 0xdfffffff
2357
/* The reset value of the ALT_RSTMGR_PERMODRST_SDR register field. */
2358
#define ALT_RSTMGR_PERMODRST_SDR_RESET 0x1
2359
/* Extracts the ALT_RSTMGR_PERMODRST_SDR field value from a register. */
2360
#define ALT_RSTMGR_PERMODRST_SDR_GET(value) (((value) & 0x20000000) >> 29)
2361
/* Produces a ALT_RSTMGR_PERMODRST_SDR register field value suitable for setting the register. */
2362
#define ALT_RSTMGR_PERMODRST_SDR_SET(value) (((value) << 29) & 0x20000000)
2363
2364
#ifndef __ASSEMBLY__
2365
/*
2366
* WARNING: The C register and register group struct declarations are provided for
2367
* convenience and illustrative purposes. They should, however, be used with
2368
* caution as the C language standard provides no guarantees about the alignment or
2369
* atomicity of device memory accesses. The recommended practice for writing
2370
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
2371
* alt_write_word() functions.
2372
*
2373
* The struct declaration for register ALT_RSTMGR_PERMODRST.
2374
*/
2375
struct
ALT_RSTMGR_PERMODRST_s
2376
{
2377
uint32_t emac0 : 1;
/* EMAC0 */
2378
uint32_t emac1 : 1;
/* EMAC1 */
2379
uint32_t usb0 : 1;
/* USB0 */
2380
uint32_t usb1 : 1;
/* USB1 */
2381
uint32_t nand : 1;
/* NAND Flash */
2382
uint32_t qspi : 1;
/* QSPI Flash */
2383
uint32_t l4wd0 : 1;
/* L4 Watchdog 0 */
2384
uint32_t l4wd1 : 1;
/* L4 Watchdog 1 */
2385
uint32_t osc1timer0 : 1;
/* OSC1 Timer 0 */
2386
uint32_t osc1timer1 : 1;
/* OSC1 Timer 1 */
2387
uint32_t sptimer0 : 1;
/* SP Timer 0 */
2388
uint32_t sptimer1 : 1;
/* SP Timer 1 */
2389
uint32_t i2c0 : 1;
/* I2C0 */
2390
uint32_t i2c1 : 1;
/* I2C1 */
2391
uint32_t i2c2 : 1;
/* I2C2 */
2392
uint32_t i2c3 : 1;
/* I2C3 */
2393
uint32_t uart0 : 1;
/* UART0 */
2394
uint32_t uart1 : 1;
/* UART1 */
2395
uint32_t spim0 : 1;
/* SPIM0 */
2396
uint32_t spim1 : 1;
/* SPIM1 */
2397
uint32_t spis0 : 1;
/* SPIS0 */
2398
uint32_t spis1 : 1;
/* SPIS1 */
2399
uint32_t sdmmc : 1;
/* SD/MMC */
2400
uint32_t can0 : 1;
/* CAN0 */
2401
uint32_t can1 : 1;
/* CAN1 */
2402
uint32_t gpio0 : 1;
/* GPIO0 */
2403
uint32_t gpio1 : 1;
/* GPIO1 */
2404
uint32_t gpio2 : 1;
/* GPIO2 */
2405
uint32_t dma : 1;
/* DMA Controller */
2406
uint32_t sdr : 1;
/* SDRAM Controller Subsystem */
2407
uint32_t : 2;
/* *UNDEFINED* */
2408
};
2409
2410
/* The typedef declaration for register ALT_RSTMGR_PERMODRST. */
2411
typedef
volatile
struct
ALT_RSTMGR_PERMODRST_s
ALT_RSTMGR_PERMODRST_t;
2412
#endif
/* __ASSEMBLY__ */
2413
2414
/* The byte offset of the ALT_RSTMGR_PERMODRST register from the beginning of the component. */
2415
#define ALT_RSTMGR_PERMODRST_OFST 0x14
2416
2417
/*
2418
* Register : Peripheral 2 Module Reset Register - per2modrst
2419
*
2420
* The PER2MODRST register is used by software to trigger module resets (individual
2421
* module reset signals). Software explicitly asserts and de-asserts module reset
2422
* signals by writing bits in the appropriate *MODRST register. It is up to
2423
* software to ensure module reset signals are asserted for the appropriate length
2424
* of time and are de-asserted in the correct order. It is also up to software to
2425
* not assert a module reset signal that would prevent software from de-asserting
2426
* the module reset signal. For example, software should not assert the module
2427
* reset to the CPU executing the software.
2428
*
2429
* Software writes a bit to 1 to assert the module reset signal and to 0 to de-
2430
* assert the module reset signal.
2431
*
2432
* All fields are reset by a cold reset.All fields are also reset by a warm reset
2433
* if not masked by the corresponding PERWARMMASK field.
2434
*
2435
* The reset value of all fields is 1. This holds the corresponding module in reset
2436
* until software is ready to release the module from reset by writing 0 to its
2437
* field.
2438
*
2439
* Register Layout
2440
*
2441
* Bits | Access | Reset | Description
2442
* :-------|:-------|:------|:------------
2443
* [0] | RW | 0x1 | FPGA DMA0
2444
* [1] | RW | 0x1 | FPGA DMA1
2445
* [2] | RW | 0x1 | FPGA DMA2
2446
* [3] | RW | 0x1 | FPGA DMA3
2447
* [4] | RW | 0x1 | FPGA DMA4
2448
* [5] | RW | 0x1 | FPGA DMA5
2449
* [6] | RW | 0x1 | FPGA DMA6
2450
* [7] | RW | 0x1 | FPGA DMA7
2451
* [31:8] | ??? | 0x0 | *UNDEFINED*
2452
*
2453
*/
2454
/*
2455
* Field : FPGA DMA0 - dmaif0
2456
*
2457
* Resets DMA channel 0 interface adapter between FPGA Fabric and HPS DMA
2458
* Controller
2459
*
2460
* Field Access Macros:
2461
*
2462
*/
2463
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
2464
#define ALT_RSTMGR_PER2MODRST_DMAIF0_LSB 0
2465
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
2466
#define ALT_RSTMGR_PER2MODRST_DMAIF0_MSB 0
2467
/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
2468
#define ALT_RSTMGR_PER2MODRST_DMAIF0_WIDTH 1
2469
/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */
2470
#define ALT_RSTMGR_PER2MODRST_DMAIF0_SET_MSK 0x00000001
2471
/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */
2472
#define ALT_RSTMGR_PER2MODRST_DMAIF0_CLR_MSK 0xfffffffe
2473
/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
2474
#define ALT_RSTMGR_PER2MODRST_DMAIF0_RESET 0x1
2475
/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF0 field value from a register. */
2476
#define ALT_RSTMGR_PER2MODRST_DMAIF0_GET(value) (((value) & 0x00000001) >> 0)
2477
/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF0 register field value suitable for setting the register. */
2478
#define ALT_RSTMGR_PER2MODRST_DMAIF0_SET(value) (((value) << 0) & 0x00000001)
2479
2480
/*
2481
* Field : FPGA DMA1 - dmaif1
2482
*
2483
* Resets DMA channel 1 interface adapter between FPGA Fabric and HPS DMA
2484
* Controller
2485
*
2486
* Field Access Macros:
2487
*
2488
*/
2489
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
2490
#define ALT_RSTMGR_PER2MODRST_DMAIF1_LSB 1
2491
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
2492
#define ALT_RSTMGR_PER2MODRST_DMAIF1_MSB 1
2493
/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
2494
#define ALT_RSTMGR_PER2MODRST_DMAIF1_WIDTH 1
2495
/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */
2496
#define ALT_RSTMGR_PER2MODRST_DMAIF1_SET_MSK 0x00000002
2497
/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */
2498
#define ALT_RSTMGR_PER2MODRST_DMAIF1_CLR_MSK 0xfffffffd
2499
/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
2500
#define ALT_RSTMGR_PER2MODRST_DMAIF1_RESET 0x1
2501
/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF1 field value from a register. */
2502
#define ALT_RSTMGR_PER2MODRST_DMAIF1_GET(value) (((value) & 0x00000002) >> 1)
2503
/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF1 register field value suitable for setting the register. */
2504
#define ALT_RSTMGR_PER2MODRST_DMAIF1_SET(value) (((value) << 1) & 0x00000002)
2505
2506
/*
2507
* Field : FPGA DMA2 - dmaif2
2508
*
2509
* Resets DMA channel 2 interface adapter between FPGA Fabric and HPS DMA
2510
* Controller
2511
*
2512
* Field Access Macros:
2513
*
2514
*/
2515
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
2516
#define ALT_RSTMGR_PER2MODRST_DMAIF2_LSB 2
2517
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
2518
#define ALT_RSTMGR_PER2MODRST_DMAIF2_MSB 2
2519
/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
2520
#define ALT_RSTMGR_PER2MODRST_DMAIF2_WIDTH 1
2521
/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */
2522
#define ALT_RSTMGR_PER2MODRST_DMAIF2_SET_MSK 0x00000004
2523
/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */
2524
#define ALT_RSTMGR_PER2MODRST_DMAIF2_CLR_MSK 0xfffffffb
2525
/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
2526
#define ALT_RSTMGR_PER2MODRST_DMAIF2_RESET 0x1
2527
/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF2 field value from a register. */
2528
#define ALT_RSTMGR_PER2MODRST_DMAIF2_GET(value) (((value) & 0x00000004) >> 2)
2529
/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF2 register field value suitable for setting the register. */
2530
#define ALT_RSTMGR_PER2MODRST_DMAIF2_SET(value) (((value) << 2) & 0x00000004)
2531
2532
/*
2533
* Field : FPGA DMA3 - dmaif3
2534
*
2535
* Resets DMA channel 3 interface adapter between FPGA Fabric and HPS DMA
2536
* Controller
2537
*
2538
* Field Access Macros:
2539
*
2540
*/
2541
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
2542
#define ALT_RSTMGR_PER2MODRST_DMAIF3_LSB 3
2543
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
2544
#define ALT_RSTMGR_PER2MODRST_DMAIF3_MSB 3
2545
/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
2546
#define ALT_RSTMGR_PER2MODRST_DMAIF3_WIDTH 1
2547
/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */
2548
#define ALT_RSTMGR_PER2MODRST_DMAIF3_SET_MSK 0x00000008
2549
/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */
2550
#define ALT_RSTMGR_PER2MODRST_DMAIF3_CLR_MSK 0xfffffff7
2551
/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
2552
#define ALT_RSTMGR_PER2MODRST_DMAIF3_RESET 0x1
2553
/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF3 field value from a register. */
2554
#define ALT_RSTMGR_PER2MODRST_DMAIF3_GET(value) (((value) & 0x00000008) >> 3)
2555
/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF3 register field value suitable for setting the register. */
2556
#define ALT_RSTMGR_PER2MODRST_DMAIF3_SET(value) (((value) << 3) & 0x00000008)
2557
2558
/*
2559
* Field : FPGA DMA4 - dmaif4
2560
*
2561
* Resets DMA channel 4 interface adapter between FPGA Fabric and HPS DMA
2562
* Controller
2563
*
2564
* Field Access Macros:
2565
*
2566
*/
2567
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
2568
#define ALT_RSTMGR_PER2MODRST_DMAIF4_LSB 4
2569
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
2570
#define ALT_RSTMGR_PER2MODRST_DMAIF4_MSB 4
2571
/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
2572
#define ALT_RSTMGR_PER2MODRST_DMAIF4_WIDTH 1
2573
/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */
2574
#define ALT_RSTMGR_PER2MODRST_DMAIF4_SET_MSK 0x00000010
2575
/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */
2576
#define ALT_RSTMGR_PER2MODRST_DMAIF4_CLR_MSK 0xffffffef
2577
/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
2578
#define ALT_RSTMGR_PER2MODRST_DMAIF4_RESET 0x1
2579
/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF4 field value from a register. */
2580
#define ALT_RSTMGR_PER2MODRST_DMAIF4_GET(value) (((value) & 0x00000010) >> 4)
2581
/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF4 register field value suitable for setting the register. */
2582
#define ALT_RSTMGR_PER2MODRST_DMAIF4_SET(value) (((value) << 4) & 0x00000010)
2583
2584
/*
2585
* Field : FPGA DMA5 - dmaif5
2586
*
2587
* Resets DMA channel 5 interface adapter between FPGA Fabric and HPS DMA
2588
* Controller
2589
*
2590
* Field Access Macros:
2591
*
2592
*/
2593
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
2594
#define ALT_RSTMGR_PER2MODRST_DMAIF5_LSB 5
2595
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
2596
#define ALT_RSTMGR_PER2MODRST_DMAIF5_MSB 5
2597
/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
2598
#define ALT_RSTMGR_PER2MODRST_DMAIF5_WIDTH 1
2599
/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */
2600
#define ALT_RSTMGR_PER2MODRST_DMAIF5_SET_MSK 0x00000020
2601
/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */
2602
#define ALT_RSTMGR_PER2MODRST_DMAIF5_CLR_MSK 0xffffffdf
2603
/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
2604
#define ALT_RSTMGR_PER2MODRST_DMAIF5_RESET 0x1
2605
/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF5 field value from a register. */
2606
#define ALT_RSTMGR_PER2MODRST_DMAIF5_GET(value) (((value) & 0x00000020) >> 5)
2607
/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF5 register field value suitable for setting the register. */
2608
#define ALT_RSTMGR_PER2MODRST_DMAIF5_SET(value) (((value) << 5) & 0x00000020)
2609
2610
/*
2611
* Field : FPGA DMA6 - dmaif6
2612
*
2613
* Resets DMA channel 6 interface adapter between FPGA Fabric and HPS DMA
2614
* Controller
2615
*
2616
* Field Access Macros:
2617
*
2618
*/
2619
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
2620
#define ALT_RSTMGR_PER2MODRST_DMAIF6_LSB 6
2621
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
2622
#define ALT_RSTMGR_PER2MODRST_DMAIF6_MSB 6
2623
/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
2624
#define ALT_RSTMGR_PER2MODRST_DMAIF6_WIDTH 1
2625
/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */
2626
#define ALT_RSTMGR_PER2MODRST_DMAIF6_SET_MSK 0x00000040
2627
/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */
2628
#define ALT_RSTMGR_PER2MODRST_DMAIF6_CLR_MSK 0xffffffbf
2629
/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
2630
#define ALT_RSTMGR_PER2MODRST_DMAIF6_RESET 0x1
2631
/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF6 field value from a register. */
2632
#define ALT_RSTMGR_PER2MODRST_DMAIF6_GET(value) (((value) & 0x00000040) >> 6)
2633
/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF6 register field value suitable for setting the register. */
2634
#define ALT_RSTMGR_PER2MODRST_DMAIF6_SET(value) (((value) << 6) & 0x00000040)
2635
2636
/*
2637
* Field : FPGA DMA7 - dmaif7
2638
*
2639
* Resets DMA channel 7 interface adapter between FPGA Fabric and HPS DMA
2640
* Controller
2641
*
2642
* Field Access Macros:
2643
*
2644
*/
2645
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
2646
#define ALT_RSTMGR_PER2MODRST_DMAIF7_LSB 7
2647
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
2648
#define ALT_RSTMGR_PER2MODRST_DMAIF7_MSB 7
2649
/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
2650
#define ALT_RSTMGR_PER2MODRST_DMAIF7_WIDTH 1
2651
/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */
2652
#define ALT_RSTMGR_PER2MODRST_DMAIF7_SET_MSK 0x00000080
2653
/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */
2654
#define ALT_RSTMGR_PER2MODRST_DMAIF7_CLR_MSK 0xffffff7f
2655
/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
2656
#define ALT_RSTMGR_PER2MODRST_DMAIF7_RESET 0x1
2657
/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF7 field value from a register. */
2658
#define ALT_RSTMGR_PER2MODRST_DMAIF7_GET(value) (((value) & 0x00000080) >> 7)
2659
/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF7 register field value suitable for setting the register. */
2660
#define ALT_RSTMGR_PER2MODRST_DMAIF7_SET(value) (((value) << 7) & 0x00000080)
2661
2662
#ifndef __ASSEMBLY__
2663
/*
2664
* WARNING: The C register and register group struct declarations are provided for
2665
* convenience and illustrative purposes. They should, however, be used with
2666
* caution as the C language standard provides no guarantees about the alignment or
2667
* atomicity of device memory accesses. The recommended practice for writing
2668
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
2669
* alt_write_word() functions.
2670
*
2671
* The struct declaration for register ALT_RSTMGR_PER2MODRST.
2672
*/
2673
struct
ALT_RSTMGR_PER2MODRST_s
2674
{
2675
uint32_t dmaif0 : 1;
/* FPGA DMA0 */
2676
uint32_t dmaif1 : 1;
/* FPGA DMA1 */
2677
uint32_t dmaif2 : 1;
/* FPGA DMA2 */
2678
uint32_t dmaif3 : 1;
/* FPGA DMA3 */
2679
uint32_t dmaif4 : 1;
/* FPGA DMA4 */
2680
uint32_t dmaif5 : 1;
/* FPGA DMA5 */
2681
uint32_t dmaif6 : 1;
/* FPGA DMA6 */
2682
uint32_t dmaif7 : 1;
/* FPGA DMA7 */
2683
uint32_t : 24;
/* *UNDEFINED* */
2684
};
2685
2686
/* The typedef declaration for register ALT_RSTMGR_PER2MODRST. */
2687
typedef
volatile
struct
ALT_RSTMGR_PER2MODRST_s
ALT_RSTMGR_PER2MODRST_t;
2688
#endif
/* __ASSEMBLY__ */
2689
2690
/* The byte offset of the ALT_RSTMGR_PER2MODRST register from the beginning of the component. */
2691
#define ALT_RSTMGR_PER2MODRST_OFST 0x18
2692
2693
/*
2694
* Register : Bridge Module Reset Register - brgmodrst
2695
*
2696
* The BRGMODRST register is used by software to trigger module resets (individual
2697
* module reset signals). Software explicitly asserts and de-asserts module reset
2698
* signals by writing bits in the appropriate *MODRST register. It is up to
2699
* software to ensure module reset signals are asserted for the appropriate length
2700
* of time and are de-asserted in the correct order. It is also up to software to
2701
* not assert a module reset signal that would prevent software from de-asserting
2702
* the module reset signal. For example, software should not assert the module
2703
* reset to the CPU executing the software.
2704
*
2705
* Software writes a bit to 1 to assert the module reset signal and to 0 to de-
2706
* assert the module reset signal.
2707
*
2708
* All fields are reset by a cold reset.All fields are also reset by a warm reset
2709
* if not masked by the corresponding BRGWARMMASK field.
2710
*
2711
* The reset value of all fields is 1. This holds the corresponding module in reset
2712
* until software is ready to release the module from reset by writing 0 to its
2713
* field.
2714
*
2715
* Register Layout
2716
*
2717
* Bits | Access | Reset | Description
2718
* :-------|:-------|:------|:------------------
2719
* [0] | RW | 0x1 | HPS2FPGA Bridge
2720
* [1] | RW | 0x1 | LWHPS2FPGA Bridge
2721
* [2] | RW | 0x1 | FPGA2HPS Bridge
2722
* [31:3] | ??? | 0x0 | *UNDEFINED*
2723
*
2724
*/
2725
/*
2726
* Field : HPS2FPGA Bridge - hps2fpga
2727
*
2728
* Resets HPS2FPGA Bridge
2729
*
2730
* Field Access Macros:
2731
*
2732
*/
2733
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */
2734
#define ALT_RSTMGR_BRGMODRST_H2F_LSB 0
2735
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */
2736
#define ALT_RSTMGR_BRGMODRST_H2F_MSB 0
2737
/* The width in bits of the ALT_RSTMGR_BRGMODRST_H2F register field. */
2738
#define ALT_RSTMGR_BRGMODRST_H2F_WIDTH 1
2739
/* The mask used to set the ALT_RSTMGR_BRGMODRST_H2F register field value. */
2740
#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001
2741
/* The mask used to clear the ALT_RSTMGR_BRGMODRST_H2F register field value. */
2742
#define ALT_RSTMGR_BRGMODRST_H2F_CLR_MSK 0xfffffffe
2743
/* The reset value of the ALT_RSTMGR_BRGMODRST_H2F register field. */
2744
#define ALT_RSTMGR_BRGMODRST_H2F_RESET 0x1
2745
/* Extracts the ALT_RSTMGR_BRGMODRST_H2F field value from a register. */
2746
#define ALT_RSTMGR_BRGMODRST_H2F_GET(value) (((value) & 0x00000001) >> 0)
2747
/* Produces a ALT_RSTMGR_BRGMODRST_H2F register field value suitable for setting the register. */
2748
#define ALT_RSTMGR_BRGMODRST_H2F_SET(value) (((value) << 0) & 0x00000001)
2749
2750
/*
2751
* Field : LWHPS2FPGA Bridge - lwhps2fpga
2752
*
2753
* Resets LWHPS2FPGA Bridge
2754
*
2755
* Field Access Macros:
2756
*
2757
*/
2758
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
2759
#define ALT_RSTMGR_BRGMODRST_LWH2F_LSB 1
2760
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
2761
#define ALT_RSTMGR_BRGMODRST_LWH2F_MSB 1
2762
/* The width in bits of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
2763
#define ALT_RSTMGR_BRGMODRST_LWH2F_WIDTH 1
2764
/* The mask used to set the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */
2765
#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002
2766
/* The mask used to clear the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */
2767
#define ALT_RSTMGR_BRGMODRST_LWH2F_CLR_MSK 0xfffffffd
2768
/* The reset value of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
2769
#define ALT_RSTMGR_BRGMODRST_LWH2F_RESET 0x1
2770
/* Extracts the ALT_RSTMGR_BRGMODRST_LWH2F field value from a register. */
2771
#define ALT_RSTMGR_BRGMODRST_LWH2F_GET(value) (((value) & 0x00000002) >> 1)
2772
/* Produces a ALT_RSTMGR_BRGMODRST_LWH2F register field value suitable for setting the register. */
2773
#define ALT_RSTMGR_BRGMODRST_LWH2F_SET(value) (((value) << 1) & 0x00000002)
2774
2775
/*
2776
* Field : FPGA2HPS Bridge - fpga2hps
2777
*
2778
* Resets FPGA2HPS Bridge
2779
*
2780
* Field Access Macros:
2781
*
2782
*/
2783
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */
2784
#define ALT_RSTMGR_BRGMODRST_F2H_LSB 2
2785
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */
2786
#define ALT_RSTMGR_BRGMODRST_F2H_MSB 2
2787
/* The width in bits of the ALT_RSTMGR_BRGMODRST_F2H register field. */
2788
#define ALT_RSTMGR_BRGMODRST_F2H_WIDTH 1
2789
/* The mask used to set the ALT_RSTMGR_BRGMODRST_F2H register field value. */
2790
#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004
2791
/* The mask used to clear the ALT_RSTMGR_BRGMODRST_F2H register field value. */
2792
#define ALT_RSTMGR_BRGMODRST_F2H_CLR_MSK 0xfffffffb
2793
/* The reset value of the ALT_RSTMGR_BRGMODRST_F2H register field. */
2794
#define ALT_RSTMGR_BRGMODRST_F2H_RESET 0x1
2795
/* Extracts the ALT_RSTMGR_BRGMODRST_F2H field value from a register. */
2796
#define ALT_RSTMGR_BRGMODRST_F2H_GET(value) (((value) & 0x00000004) >> 2)
2797
/* Produces a ALT_RSTMGR_BRGMODRST_F2H register field value suitable for setting the register. */
2798
#define ALT_RSTMGR_BRGMODRST_F2H_SET(value) (((value) << 2) & 0x00000004)
2799
2800
#ifndef __ASSEMBLY__
2801
/*
2802
* WARNING: The C register and register group struct declarations are provided for
2803
* convenience and illustrative purposes. They should, however, be used with
2804
* caution as the C language standard provides no guarantees about the alignment or
2805
* atomicity of device memory accesses. The recommended practice for writing
2806
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
2807
* alt_write_word() functions.
2808
*
2809
* The struct declaration for register ALT_RSTMGR_BRGMODRST.
2810
*/
2811
struct
ALT_RSTMGR_BRGMODRST_s
2812
{
2813
uint32_t hps2fpga : 1;
/* HPS2FPGA Bridge */
2814
uint32_t lwhps2fpga : 1;
/* LWHPS2FPGA Bridge */
2815
uint32_t fpga2hps : 1;
/* FPGA2HPS Bridge */
2816
uint32_t : 29;
/* *UNDEFINED* */
2817
};
2818
2819
/* The typedef declaration for register ALT_RSTMGR_BRGMODRST. */
2820
typedef
volatile
struct
ALT_RSTMGR_BRGMODRST_s
ALT_RSTMGR_BRGMODRST_t;
2821
#endif
/* __ASSEMBLY__ */
2822
2823
/* The byte offset of the ALT_RSTMGR_BRGMODRST register from the beginning of the component. */
2824
#define ALT_RSTMGR_BRGMODRST_OFST 0x1c
2825
2826
/*
2827
* Register : Miscellaneous Module Reset Register - miscmodrst
2828
*
2829
* The MISCMODRST register is used by software to trigger module resets (individual
2830
* module reset signals). Software explicitly asserts and de-asserts module reset
2831
* signals by writing bits in the appropriate *MODRST register. It is up to
2832
* software to ensure module reset signals are asserted for the appropriate length
2833
* of time and are de-asserted in the correct order. It is also up to software to
2834
* not assert a module reset signal that would prevent software from de-asserting
2835
* the module reset signal. For example, software should not assert the module
2836
* reset to the CPU executing the software.
2837
*
2838
* Software writes a bit to 1 to assert the module reset signal and to 0 to de-
2839
* assert the module reset signal.
2840
*
2841
* All fields are only reset by a cold reset
2842
*
2843
* Register Layout
2844
*
2845
* Bits | Access | Reset | Description
2846
* :--------|:-------|:------|:--------------------------------------
2847
* [0] | RW | 0x0 | Boot ROM
2848
* [1] | RW | 0x0 | On-chip RAM
2849
* [2] | RW | 0x0 | System Manager (Cold or Warm)
2850
* [3] | RW | 0x0 | System Manager (Cold-only)
2851
* [4] | RW | 0x0 | FPGA Manager
2852
* [5] | RW | 0x0 | ACP ID Mapper
2853
* [6] | RW | 0x0 | HPS to FPGA Core (Cold or Warm)
2854
* [7] | RW | 0x0 | HPS to FPGA Core (Cold-only)
2855
* [8] | RW | 0x0 | nRST Pin
2856
* [9] | RW | 0x0 | Timestamp
2857
* [10] | RW | 0x0 | Clock Manager
2858
* [11] | RW | 0x0 | Scan Manager
2859
* [12] | RW | 0x0 | Freeze Controller
2860
* [13] | RW | 0x0 | System/Debug
2861
* [14] | RW | 0x0 | Debug
2862
* [15] | RW | 0x0 | TAP Controller
2863
* [16] | RW | 0x0 | SDRAM Controller Subsystem Cold Reset
2864
* [31:17] | ??? | 0x0 | *UNDEFINED*
2865
*
2866
*/
2867
/*
2868
* Field : Boot ROM - rom
2869
*
2870
* Resets Boot ROM
2871
*
2872
* Field Access Macros:
2873
*
2874
*/
2875
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */
2876
#define ALT_RSTMGR_MISCMODRST_ROM_LSB 0
2877
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */
2878
#define ALT_RSTMGR_MISCMODRST_ROM_MSB 0
2879
/* The width in bits of the ALT_RSTMGR_MISCMODRST_ROM register field. */
2880
#define ALT_RSTMGR_MISCMODRST_ROM_WIDTH 1
2881
/* The mask used to set the ALT_RSTMGR_MISCMODRST_ROM register field value. */
2882
#define ALT_RSTMGR_MISCMODRST_ROM_SET_MSK 0x00000001
2883
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_ROM register field value. */
2884
#define ALT_RSTMGR_MISCMODRST_ROM_CLR_MSK 0xfffffffe
2885
/* The reset value of the ALT_RSTMGR_MISCMODRST_ROM register field. */
2886
#define ALT_RSTMGR_MISCMODRST_ROM_RESET 0x0
2887
/* Extracts the ALT_RSTMGR_MISCMODRST_ROM field value from a register. */
2888
#define ALT_RSTMGR_MISCMODRST_ROM_GET(value) (((value) & 0x00000001) >> 0)
2889
/* Produces a ALT_RSTMGR_MISCMODRST_ROM register field value suitable for setting the register. */
2890
#define ALT_RSTMGR_MISCMODRST_ROM_SET(value) (((value) << 0) & 0x00000001)
2891
2892
/*
2893
* Field : On-chip RAM - ocram
2894
*
2895
* Resets On-chip RAM
2896
*
2897
* Field Access Macros:
2898
*
2899
*/
2900
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
2901
#define ALT_RSTMGR_MISCMODRST_OCRAM_LSB 1
2902
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
2903
#define ALT_RSTMGR_MISCMODRST_OCRAM_MSB 1
2904
/* The width in bits of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
2905
#define ALT_RSTMGR_MISCMODRST_OCRAM_WIDTH 1
2906
/* The mask used to set the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */
2907
#define ALT_RSTMGR_MISCMODRST_OCRAM_SET_MSK 0x00000002
2908
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */
2909
#define ALT_RSTMGR_MISCMODRST_OCRAM_CLR_MSK 0xfffffffd
2910
/* The reset value of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
2911
#define ALT_RSTMGR_MISCMODRST_OCRAM_RESET 0x0
2912
/* Extracts the ALT_RSTMGR_MISCMODRST_OCRAM field value from a register. */
2913
#define ALT_RSTMGR_MISCMODRST_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
2914
/* Produces a ALT_RSTMGR_MISCMODRST_OCRAM register field value suitable for setting the register. */
2915
#define ALT_RSTMGR_MISCMODRST_OCRAM_SET(value) (((value) << 1) & 0x00000002)
2916
2917
/*
2918
* Field : System Manager (Cold or Warm) - sysmgr
2919
*
2920
* Resets logic in System Manager that doesn't differentiate between cold and warm
2921
* resets
2922
*
2923
* Field Access Macros:
2924
*
2925
*/
2926
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
2927
#define ALT_RSTMGR_MISCMODRST_SYSMGR_LSB 2
2928
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
2929
#define ALT_RSTMGR_MISCMODRST_SYSMGR_MSB 2
2930
/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
2931
#define ALT_RSTMGR_MISCMODRST_SYSMGR_WIDTH 1
2932
/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */
2933
#define ALT_RSTMGR_MISCMODRST_SYSMGR_SET_MSK 0x00000004
2934
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */
2935
#define ALT_RSTMGR_MISCMODRST_SYSMGR_CLR_MSK 0xfffffffb
2936
/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
2937
#define ALT_RSTMGR_MISCMODRST_SYSMGR_RESET 0x0
2938
/* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGR field value from a register. */
2939
#define ALT_RSTMGR_MISCMODRST_SYSMGR_GET(value) (((value) & 0x00000004) >> 2)
2940
/* Produces a ALT_RSTMGR_MISCMODRST_SYSMGR register field value suitable for setting the register. */
2941
#define ALT_RSTMGR_MISCMODRST_SYSMGR_SET(value) (((value) << 2) & 0x00000004)
2942
2943
/*
2944
* Field : System Manager (Cold-only) - sysmgrcold
2945
*
2946
* Resets logic in System Manager that is only reset by a cold reset (ignores warm
2947
* reset)
2948
*
2949
* Field Access Macros:
2950
*
2951
*/
2952
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
2953
#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_LSB 3
2954
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
2955
#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_MSB 3
2956
/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
2957
#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_WIDTH 1
2958
/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */
2959
#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET_MSK 0x00000008
2960
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */
2961
#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_CLR_MSK 0xfffffff7
2962
/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
2963
#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_RESET 0x0
2964
/* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD field value from a register. */
2965
#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_GET(value) (((value) & 0x00000008) >> 3)
2966
/* Produces a ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value suitable for setting the register. */
2967
#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET(value) (((value) << 3) & 0x00000008)
2968
2969
/*
2970
* Field : FPGA Manager - fpgamgr
2971
*
2972
* Resets FPGA Manager
2973
*
2974
* Field Access Macros:
2975
*
2976
*/
2977
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
2978
#define ALT_RSTMGR_MISCMODRST_FPGAMGR_LSB 4
2979
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
2980
#define ALT_RSTMGR_MISCMODRST_FPGAMGR_MSB 4
2981
/* The width in bits of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
2982
#define ALT_RSTMGR_MISCMODRST_FPGAMGR_WIDTH 1
2983
/* The mask used to set the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */
2984
#define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET_MSK 0x00000010
2985
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */
2986
#define ALT_RSTMGR_MISCMODRST_FPGAMGR_CLR_MSK 0xffffffef
2987
/* The reset value of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
2988
#define ALT_RSTMGR_MISCMODRST_FPGAMGR_RESET 0x0
2989
/* Extracts the ALT_RSTMGR_MISCMODRST_FPGAMGR field value from a register. */
2990
#define ALT_RSTMGR_MISCMODRST_FPGAMGR_GET(value) (((value) & 0x00000010) >> 4)
2991
/* Produces a ALT_RSTMGR_MISCMODRST_FPGAMGR register field value suitable for setting the register. */
2992
#define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET(value) (((value) << 4) & 0x00000010)
2993
2994
/*
2995
* Field : ACP ID Mapper - acpidmap
2996
*
2997
* Resets ACP ID Mapper
2998
*
2999
* Field Access Macros:
3000
*
3001
*/
3002
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
3003
#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_LSB 5
3004
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
3005
#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_MSB 5
3006
/* The width in bits of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
3007
#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_WIDTH 1
3008
/* The mask used to set the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */
3009
#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET_MSK 0x00000020
3010
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */
3011
#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_CLR_MSK 0xffffffdf
3012
/* The reset value of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
3013
#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_RESET 0x0
3014
/* Extracts the ALT_RSTMGR_MISCMODRST_ACPIDMAP field value from a register. */
3015
#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_GET(value) (((value) & 0x00000020) >> 5)
3016
/* Produces a ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value suitable for setting the register. */
3017
#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET(value) (((value) << 5) & 0x00000020)
3018
3019
/*
3020
* Field : HPS to FPGA Core (Cold or Warm) - s2f
3021
*
3022
* Resets logic in FPGA core that doesn't differentiate between HPS cold and warm
3023
* resets (h2f_rst_n = 1)
3024
*
3025
* Field Access Macros:
3026
*
3027
*/
3028
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */
3029
#define ALT_RSTMGR_MISCMODRST_S2F_LSB 6
3030
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */
3031
#define ALT_RSTMGR_MISCMODRST_S2F_MSB 6
3032
/* The width in bits of the ALT_RSTMGR_MISCMODRST_S2F register field. */
3033
#define ALT_RSTMGR_MISCMODRST_S2F_WIDTH 1
3034
/* The mask used to set the ALT_RSTMGR_MISCMODRST_S2F register field value. */
3035
#define ALT_RSTMGR_MISCMODRST_S2F_SET_MSK 0x00000040
3036
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2F register field value. */
3037
#define ALT_RSTMGR_MISCMODRST_S2F_CLR_MSK 0xffffffbf
3038
/* The reset value of the ALT_RSTMGR_MISCMODRST_S2F register field. */
3039
#define ALT_RSTMGR_MISCMODRST_S2F_RESET 0x0
3040
/* Extracts the ALT_RSTMGR_MISCMODRST_S2F field value from a register. */
3041
#define ALT_RSTMGR_MISCMODRST_S2F_GET(value) (((value) & 0x00000040) >> 6)
3042
/* Produces a ALT_RSTMGR_MISCMODRST_S2F register field value suitable for setting the register. */
3043
#define ALT_RSTMGR_MISCMODRST_S2F_SET(value) (((value) << 6) & 0x00000040)
3044
3045
/*
3046
* Field : HPS to FPGA Core (Cold-only) - s2fcold
3047
*
3048
* Resets logic in FPGA core that is only reset by a cold reset (ignores warm
3049
* reset) (h2f_cold_rst_n = 1)
3050
*
3051
* Field Access Macros:
3052
*
3053
*/
3054
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
3055
#define ALT_RSTMGR_MISCMODRST_S2FCOLD_LSB 7
3056
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
3057
#define ALT_RSTMGR_MISCMODRST_S2FCOLD_MSB 7
3058
/* The width in bits of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
3059
#define ALT_RSTMGR_MISCMODRST_S2FCOLD_WIDTH 1
3060
/* The mask used to set the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */
3061
#define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET_MSK 0x00000080
3062
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */
3063
#define ALT_RSTMGR_MISCMODRST_S2FCOLD_CLR_MSK 0xffffff7f
3064
/* The reset value of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
3065
#define ALT_RSTMGR_MISCMODRST_S2FCOLD_RESET 0x0
3066
/* Extracts the ALT_RSTMGR_MISCMODRST_S2FCOLD field value from a register. */
3067
#define ALT_RSTMGR_MISCMODRST_S2FCOLD_GET(value) (((value) & 0x00000080) >> 7)
3068
/* Produces a ALT_RSTMGR_MISCMODRST_S2FCOLD register field value suitable for setting the register. */
3069
#define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET(value) (((value) << 7) & 0x00000080)
3070
3071
/*
3072
* Field : nRST Pin - nrstpin
3073
*
3074
* Pulls nRST pin low
3075
*
3076
* Field Access Macros:
3077
*
3078
*/
3079
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
3080
#define ALT_RSTMGR_MISCMODRST_NRSTPIN_LSB 8
3081
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
3082
#define ALT_RSTMGR_MISCMODRST_NRSTPIN_MSB 8
3083
/* The width in bits of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
3084
#define ALT_RSTMGR_MISCMODRST_NRSTPIN_WIDTH 1
3085
/* The mask used to set the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */
3086
#define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET_MSK 0x00000100
3087
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */
3088
#define ALT_RSTMGR_MISCMODRST_NRSTPIN_CLR_MSK 0xfffffeff
3089
/* The reset value of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
3090
#define ALT_RSTMGR_MISCMODRST_NRSTPIN_RESET 0x0
3091
/* Extracts the ALT_RSTMGR_MISCMODRST_NRSTPIN field value from a register. */
3092
#define ALT_RSTMGR_MISCMODRST_NRSTPIN_GET(value) (((value) & 0x00000100) >> 8)
3093
/* Produces a ALT_RSTMGR_MISCMODRST_NRSTPIN register field value suitable for setting the register. */
3094
#define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET(value) (((value) << 8) & 0x00000100)
3095
3096
/*
3097
* Field : Timestamp - timestampcold
3098
*
3099
* Resets debug timestamp to 0 (cold reset only)
3100
*
3101
* Field Access Macros:
3102
*
3103
*/
3104
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
3105
#define ALT_RSTMGR_MISCMODRST_TSCOLD_LSB 9
3106
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
3107
#define ALT_RSTMGR_MISCMODRST_TSCOLD_MSB 9
3108
/* The width in bits of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
3109
#define ALT_RSTMGR_MISCMODRST_TSCOLD_WIDTH 1
3110
/* The mask used to set the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */
3111
#define ALT_RSTMGR_MISCMODRST_TSCOLD_SET_MSK 0x00000200
3112
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */
3113
#define ALT_RSTMGR_MISCMODRST_TSCOLD_CLR_MSK 0xfffffdff
3114
/* The reset value of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
3115
#define ALT_RSTMGR_MISCMODRST_TSCOLD_RESET 0x0
3116
/* Extracts the ALT_RSTMGR_MISCMODRST_TSCOLD field value from a register. */
3117
#define ALT_RSTMGR_MISCMODRST_TSCOLD_GET(value) (((value) & 0x00000200) >> 9)
3118
/* Produces a ALT_RSTMGR_MISCMODRST_TSCOLD register field value suitable for setting the register. */
3119
#define ALT_RSTMGR_MISCMODRST_TSCOLD_SET(value) (((value) << 9) & 0x00000200)
3120
3121
/*
3122
* Field : Clock Manager - clkmgrcold
3123
*
3124
* Resets Clock Manager (cold reset only)
3125
*
3126
* Field Access Macros:
3127
*
3128
*/
3129
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
3130
#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_LSB 10
3131
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
3132
#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_MSB 10
3133
/* The width in bits of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
3134
#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_WIDTH 1
3135
/* The mask used to set the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */
3136
#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET_MSK 0x00000400
3137
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */
3138
#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_CLR_MSK 0xfffffbff
3139
/* The reset value of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
3140
#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_RESET 0x0
3141
/* Extracts the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD field value from a register. */
3142
#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_GET(value) (((value) & 0x00000400) >> 10)
3143
/* Produces a ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value suitable for setting the register. */
3144
#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET(value) (((value) << 10) & 0x00000400)
3145
3146
/*
3147
* Field : Scan Manager - scanmgr
3148
*
3149
* Resets Scan Manager
3150
*
3151
* Field Access Macros:
3152
*
3153
*/
3154
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
3155
#define ALT_RSTMGR_MISCMODRST_SCANMGR_LSB 11
3156
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
3157
#define ALT_RSTMGR_MISCMODRST_SCANMGR_MSB 11
3158
/* The width in bits of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
3159
#define ALT_RSTMGR_MISCMODRST_SCANMGR_WIDTH 1
3160
/* The mask used to set the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */
3161
#define ALT_RSTMGR_MISCMODRST_SCANMGR_SET_MSK 0x00000800
3162
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */
3163
#define ALT_RSTMGR_MISCMODRST_SCANMGR_CLR_MSK 0xfffff7ff
3164
/* The reset value of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
3165
#define ALT_RSTMGR_MISCMODRST_SCANMGR_RESET 0x0
3166
/* Extracts the ALT_RSTMGR_MISCMODRST_SCANMGR field value from a register. */
3167
#define ALT_RSTMGR_MISCMODRST_SCANMGR_GET(value) (((value) & 0x00000800) >> 11)
3168
/* Produces a ALT_RSTMGR_MISCMODRST_SCANMGR register field value suitable for setting the register. */
3169
#define ALT_RSTMGR_MISCMODRST_SCANMGR_SET(value) (((value) << 11) & 0x00000800)
3170
3171
/*
3172
* Field : Freeze Controller - frzctrlcold
3173
*
3174
* Resets Freeze Controller in System Manager (cold reset only)
3175
*
3176
* Field Access Macros:
3177
*
3178
*/
3179
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */
3180
#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_LSB 12
3181
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */
3182
#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_MSB 12
3183
/* The width in bits of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */
3184
#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_WIDTH 1
3185
/* The mask used to set the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value. */
3186
#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET_MSK 0x00001000
3187
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value. */
3188
#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_CLR_MSK 0xffffefff
3189
/* The reset value of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */
3190
#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_RESET 0x0
3191
/* Extracts the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD field value from a register. */
3192
#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_GET(value) (((value) & 0x00001000) >> 12)
3193
/* Produces a ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value suitable for setting the register. */
3194
#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET(value) (((value) << 12) & 0x00001000)
3195
3196
/*
3197
* Field : System/Debug - sysdbg
3198
*
3199
* Resets logic that spans the system and debug domains.
3200
*
3201
* Field Access Macros:
3202
*
3203
*/
3204
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */
3205
#define ALT_RSTMGR_MISCMODRST_SYSDBG_LSB 13
3206
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */
3207
#define ALT_RSTMGR_MISCMODRST_SYSDBG_MSB 13
3208
/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */
3209
#define ALT_RSTMGR_MISCMODRST_SYSDBG_WIDTH 1
3210
/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSDBG register field value. */
3211
#define ALT_RSTMGR_MISCMODRST_SYSDBG_SET_MSK 0x00002000
3212
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSDBG register field value. */
3213
#define ALT_RSTMGR_MISCMODRST_SYSDBG_CLR_MSK 0xffffdfff
3214
/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */
3215
#define ALT_RSTMGR_MISCMODRST_SYSDBG_RESET 0x0
3216
/* Extracts the ALT_RSTMGR_MISCMODRST_SYSDBG field value from a register. */
3217
#define ALT_RSTMGR_MISCMODRST_SYSDBG_GET(value) (((value) & 0x00002000) >> 13)
3218
/* Produces a ALT_RSTMGR_MISCMODRST_SYSDBG register field value suitable for setting the register. */
3219
#define ALT_RSTMGR_MISCMODRST_SYSDBG_SET(value) (((value) << 13) & 0x00002000)
3220
3221
/*
3222
* Field : Debug - dbg
3223
*
3224
* Resets logic located only in the debug domain.
3225
*
3226
* Field Access Macros:
3227
*
3228
*/
3229
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_DBG register field. */
3230
#define ALT_RSTMGR_MISCMODRST_DBG_LSB 14
3231
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_DBG register field. */
3232
#define ALT_RSTMGR_MISCMODRST_DBG_MSB 14
3233
/* The width in bits of the ALT_RSTMGR_MISCMODRST_DBG register field. */
3234
#define ALT_RSTMGR_MISCMODRST_DBG_WIDTH 1
3235
/* The mask used to set the ALT_RSTMGR_MISCMODRST_DBG register field value. */
3236
#define ALT_RSTMGR_MISCMODRST_DBG_SET_MSK 0x00004000
3237
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_DBG register field value. */
3238
#define ALT_RSTMGR_MISCMODRST_DBG_CLR_MSK 0xffffbfff
3239
/* The reset value of the ALT_RSTMGR_MISCMODRST_DBG register field. */
3240
#define ALT_RSTMGR_MISCMODRST_DBG_RESET 0x0
3241
/* Extracts the ALT_RSTMGR_MISCMODRST_DBG field value from a register. */
3242
#define ALT_RSTMGR_MISCMODRST_DBG_GET(value) (((value) & 0x00004000) >> 14)
3243
/* Produces a ALT_RSTMGR_MISCMODRST_DBG register field value suitable for setting the register. */
3244
#define ALT_RSTMGR_MISCMODRST_DBG_SET(value) (((value) << 14) & 0x00004000)
3245
3246
/*
3247
* Field : TAP Controller - tapcold
3248
*
3249
* Resets portion of DAP JTAG TAP controller no reset by a debug probe reset (i.e.
3250
* nTRST pin). Cold reset only.
3251
*
3252
* Field Access Macros:
3253
*
3254
*/
3255
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */
3256
#define ALT_RSTMGR_MISCMODRST_TAPCOLD_LSB 15
3257
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */
3258
#define ALT_RSTMGR_MISCMODRST_TAPCOLD_MSB 15
3259
/* The width in bits of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */
3260
#define ALT_RSTMGR_MISCMODRST_TAPCOLD_WIDTH 1
3261
/* The mask used to set the ALT_RSTMGR_MISCMODRST_TAPCOLD register field value. */
3262
#define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET_MSK 0x00008000
3263
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_TAPCOLD register field value. */
3264
#define ALT_RSTMGR_MISCMODRST_TAPCOLD_CLR_MSK 0xffff7fff
3265
/* The reset value of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */
3266
#define ALT_RSTMGR_MISCMODRST_TAPCOLD_RESET 0x0
3267
/* Extracts the ALT_RSTMGR_MISCMODRST_TAPCOLD field value from a register. */
3268
#define ALT_RSTMGR_MISCMODRST_TAPCOLD_GET(value) (((value) & 0x00008000) >> 15)
3269
/* Produces a ALT_RSTMGR_MISCMODRST_TAPCOLD register field value suitable for setting the register. */
3270
#define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET(value) (((value) << 15) & 0x00008000)
3271
3272
/*
3273
* Field : SDRAM Controller Subsystem Cold Reset - sdrcold
3274
*
3275
* Resets logic in SDRAM Controller Subsystem affected only by a cold reset.
3276
*
3277
* Field Access Macros:
3278
*
3279
*/
3280
/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */
3281
#define ALT_RSTMGR_MISCMODRST_SDRCOLD_LSB 16
3282
/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */
3283
#define ALT_RSTMGR_MISCMODRST_SDRCOLD_MSB 16
3284
/* The width in bits of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */
3285
#define ALT_RSTMGR_MISCMODRST_SDRCOLD_WIDTH 1
3286
/* The mask used to set the ALT_RSTMGR_MISCMODRST_SDRCOLD register field value. */
3287
#define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET_MSK 0x00010000
3288
/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SDRCOLD register field value. */
3289
#define ALT_RSTMGR_MISCMODRST_SDRCOLD_CLR_MSK 0xfffeffff
3290
/* The reset value of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */
3291
#define ALT_RSTMGR_MISCMODRST_SDRCOLD_RESET 0x0
3292
/* Extracts the ALT_RSTMGR_MISCMODRST_SDRCOLD field value from a register. */
3293
#define ALT_RSTMGR_MISCMODRST_SDRCOLD_GET(value) (((value) & 0x00010000) >> 16)
3294
/* Produces a ALT_RSTMGR_MISCMODRST_SDRCOLD register field value suitable for setting the register. */
3295
#define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET(value) (((value) << 16) & 0x00010000)
3296
3297
#ifndef __ASSEMBLY__
3298
/*
3299
* WARNING: The C register and register group struct declarations are provided for
3300
* convenience and illustrative purposes. They should, however, be used with
3301
* caution as the C language standard provides no guarantees about the alignment or
3302
* atomicity of device memory accesses. The recommended practice for writing
3303
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
3304
* alt_write_word() functions.
3305
*
3306
* The struct declaration for register ALT_RSTMGR_MISCMODRST.
3307
*/
3308
struct
ALT_RSTMGR_MISCMODRST_s
3309
{
3310
uint32_t rom : 1;
/* Boot ROM */
3311
uint32_t ocram : 1;
/* On-chip RAM */
3312
uint32_t sysmgr : 1;
/* System Manager (Cold or Warm) */
3313
uint32_t sysmgrcold : 1;
/* System Manager (Cold-only) */
3314
uint32_t fpgamgr : 1;
/* FPGA Manager */
3315
uint32_t acpidmap : 1;
/* ACP ID Mapper */
3316
uint32_t s2f : 1;
/* HPS to FPGA Core (Cold or Warm) */
3317
uint32_t s2fcold : 1;
/* HPS to FPGA Core (Cold-only) */
3318
uint32_t nrstpin : 1;
/* nRST Pin */
3319
uint32_t timestampcold : 1;
/* Timestamp */
3320
uint32_t clkmgrcold : 1;
/* Clock Manager */
3321
uint32_t scanmgr : 1;
/* Scan Manager */
3322
uint32_t frzctrlcold : 1;
/* Freeze Controller */
3323
uint32_t sysdbg : 1;
/* System/Debug */
3324
uint32_t dbg : 1;
/* Debug */
3325
uint32_t tapcold : 1;
/* TAP Controller */
3326
uint32_t sdrcold : 1;
/* SDRAM Controller Subsystem Cold Reset */
3327
uint32_t : 15;
/* *UNDEFINED* */
3328
};
3329
3330
/* The typedef declaration for register ALT_RSTMGR_MISCMODRST. */
3331
typedef
volatile
struct
ALT_RSTMGR_MISCMODRST_s
ALT_RSTMGR_MISCMODRST_t;
3332
#endif
/* __ASSEMBLY__ */
3333
3334
/* The byte offset of the ALT_RSTMGR_MISCMODRST register from the beginning of the component. */
3335
#define ALT_RSTMGR_MISCMODRST_OFST 0x20
3336
3337
#ifndef __ASSEMBLY__
3338
/*
3339
* WARNING: The C register and register group struct declarations are provided for
3340
* convenience and illustrative purposes. They should, however, be used with
3341
* caution as the C language standard provides no guarantees about the alignment or
3342
* atomicity of device memory accesses. The recommended practice for writing
3343
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
3344
* alt_write_word() functions.
3345
*
3346
* The struct declaration for register group ALT_RSTMGR.
3347
*/
3348
struct
ALT_RSTMGR_s
3349
{
3350
volatile
ALT_RSTMGR_STAT_t stat;
/* ALT_RSTMGR_STAT */
3351
volatile
ALT_RSTMGR_CTL_t ctrl;
/* ALT_RSTMGR_CTL */
3352
volatile
ALT_RSTMGR_COUNTS_t counts;
/* ALT_RSTMGR_COUNTS */
3353
volatile
uint32_t _pad_0xc_0xf;
/* *UNDEFINED* */
3354
volatile
ALT_RSTMGR_MPUMODRST_t mpumodrst;
/* ALT_RSTMGR_MPUMODRST */
3355
volatile
ALT_RSTMGR_PERMODRST_t permodrst;
/* ALT_RSTMGR_PERMODRST */
3356
volatile
ALT_RSTMGR_PER2MODRST_t per2modrst;
/* ALT_RSTMGR_PER2MODRST */
3357
volatile
ALT_RSTMGR_BRGMODRST_t brgmodrst;
/* ALT_RSTMGR_BRGMODRST */
3358
volatile
ALT_RSTMGR_MISCMODRST_t miscmodrst;
/* ALT_RSTMGR_MISCMODRST */
3359
volatile
uint32_t _pad_0x24_0x100[55];
/* *UNDEFINED* */
3360
};
3361
3362
/* The typedef declaration for register group ALT_RSTMGR. */
3363
typedef
volatile
struct
ALT_RSTMGR_s
ALT_RSTMGR_t;
3364
/* The struct declaration for the raw register contents of register group ALT_RSTMGR. */
3365
struct
ALT_RSTMGR_raw_s
3366
{
3367
volatile
uint32_t stat;
/* ALT_RSTMGR_STAT */
3368
volatile
uint32_t ctrl;
/* ALT_RSTMGR_CTL */
3369
volatile
uint32_t counts;
/* ALT_RSTMGR_COUNTS */
3370
volatile
uint32_t _pad_0xc_0xf;
/* *UNDEFINED* */
3371
volatile
uint32_t mpumodrst;
/* ALT_RSTMGR_MPUMODRST */
3372
volatile
uint32_t permodrst;
/* ALT_RSTMGR_PERMODRST */
3373
volatile
uint32_t per2modrst;
/* ALT_RSTMGR_PER2MODRST */
3374
volatile
uint32_t brgmodrst;
/* ALT_RSTMGR_BRGMODRST */
3375
volatile
uint32_t miscmodrst;
/* ALT_RSTMGR_MISCMODRST */
3376
volatile
uint32_t _pad_0x24_0x100[55];
/* *UNDEFINED* */
3377
};
3378
3379
/* The typedef declaration for the raw register contents of register group ALT_RSTMGR. */
3380
typedef
volatile
struct
ALT_RSTMGR_raw_s
ALT_RSTMGR_raw_t;
3381
#endif
/* __ASSEMBLY__ */
3382
3383
3384
#ifdef __cplusplus
3385
}
3386
#endif
/* __cplusplus */
3387
#endif
/* __ALTERA_ALT_RSTMGR_H__ */
3388
ALT_RSTMGR_BRGMODRST_s
Definition
alt_rstmgr.h:2812
ALT_RSTMGR_COUNTS_s
Definition
alt_rstmgr.h:1336
ALT_RSTMGR_CTL_s
Definition
alt_rstmgr.h:1219
ALT_RSTMGR_MISCMODRST_s
Definition
alt_rstmgr.h:3309
ALT_RSTMGR_MPUMODRST_s
Definition
alt_rstmgr.h:1535
ALT_RSTMGR_PER2MODRST_s
Definition
alt_rstmgr.h:2674
ALT_RSTMGR_PERMODRST_s
Definition
alt_rstmgr.h:2376
ALT_RSTMGR_STAT_s
Definition
alt_rstmgr.h:605
ALT_RSTMGR_raw_s
Definition
alt_rstmgr.h:3366
ALT_RSTMGR_s
Definition
alt_rstmgr.h:3349
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