RTEMS: cpukit/score/cpu/m68k/include/rtems/m68k/m68302.h File Reference

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Data Structures | Macros | Typedefs | Enumerations | Variables
m68302.h File Reference

Definitions for Motorola MC68302 Processor. More...

Go to the source code of this file.

## Data Structures
struct | m302_DRAM_refresh_t
struct | m302_SCC_bd
struct | m302_SCC_bd_table_t
struct | m302_SCC_parameters_t
struct | m302_SCC_UartSpecific_t
struct | m302_SCC_HdlcSpecific_t
struct | m302_SCC_t
struct | m302_SCC_Registers_t
struct | m302_internalReg_t
struct | m302_dualPortRAM_t

## Macros
#define | M302_BAR (*((volatile uint16_t *) 0xf2))
#define | M302_SCR (*((volatile uint32_t *) 0xf4))
#define | RBIT_SCR_IPA 0x08000000
#define | RBIT_SCR_HWT 0x04000000
#define | RBIT_SCR_WPV 0x02000000
#define | RBIT_SCR_ADC 0x01000000
#define | RBIT_SCR_ERRE 0x00400000
#define | RBIT_SCR_VGE 0x00200000
#define | RBIT_SCR_WPVE 0x00100000
#define | RBIT_SCR_RMCST 0x00080000
#define | RBIT_SCR_EMWS 0x00040000
#define | RBIT_SCR_ADCE 0x00020000
#define | RBIT_SCR_BCLM 0x00010000
#define | RBIT_SCR_FRZW 0x00008000
#define | RBIT_SCR_FRZ2 0x00004000
#define | RBIT_SCR_FRZ1 0x00002000
#define | RBIT_SCR_SAM 0x00001000
#define | RBIT_SCR_HWDEN 0x00000800
#define | RBIT_SCR_HWDCN2 0x00000400
#define | RBIT_SCR_HWDCN1 0x00000200 /* 512 clocks */
#define | RBIT_SCR_HWDCN0 0x00000100 /* 128 clocks */
#define | RBIT_SCR_LPREC 0x00000080
#define | RBIT_SCR_LPP16 0x00000040
#define | RBIT_SCR_LPEN 0x00000020
#define | RBIT_SCR_LPCLKDIV 0x0000001f
#define | M68K_IVEC_BUS_ERROR 2
#define | M68K_IVEC_ADDRESS_ERROR 3
#define | M68K_IVEC_ILLEGAL_OPCODE 4
#define | M68K_IVEC_ZERO_DIVIDE 5
#define | M68K_IVEC_CHK 6
#define | M68K_IVEC_TRAPV 7
#define | M68K_IVEC_PRIVILEGE 8
#define | M68K_IVEC_TRACE 9
#define | M68K_IVEC_LINE_A 10
#define | M68K_IVEC_LINE_F 11
#define | M68K_IVEC_UNINITIALIZED_INT 15
#define | M68K_IVEC_SPURIOUS_INT 24
#define | M68K_IVEC_LEVEL1_AUTOVECTOR 25
#define | M68K_IVEC_LEVEL2_AUTOVECTOR 26
#define | M68K_IVEC_LEVEL3_AUTOVECTOR 27
#define | M68K_IVEC_LEVEL4_AUTOVECTOR 28
#define | M68K_IVEC_LEVEL5_AUTOVECTOR 29
#define | M68K_IVEC_LEVEL6_AUTOVECTOR 30
#define | M68K_IVEC_LEVEL7_AUTOVECTOR 31
#define | M68K_IVEC_TRAP0 32
#define | M68K_IVEC_TRAP1 33
#define | M68K_IVEC_TRAP2 34
#define | M68K_IVEC_TRAP3 35
#define | M68K_IVEC_TRAP4 36
#define | M68K_IVEC_TRAP5 37
#define | M68K_IVEC_TRAP6 38
#define | M68K_IVEC_TRAP7 39
#define | M68K_IVEC_TRAP8 40
#define | M68K_IVEC_TRAP9 41
#define | M68K_IVEC_TRAP10 42
#define | M68K_IVEC_TRAP11 43
#define | M68K_IVEC_TRAP12 44
#define | M68K_IVEC_TRAP13 45
#define | M68K_IVEC_TRAP14 46
#define | M68K_IVEC_TRAP15 47
#define | RBIT_GIMR_MOD (1<<15)
#define | RBIT_GIMR_IV7 (1<<14)
#define | RBIT_GIMR_IV6 (1<<13)
#define | RBIT_GIMR_IV1 (1<<12)
#define | RBIT_GIMR_ET7 (1<<10)
#define | RBIT_GIMR_ET6 (1<<9)
#define | RBIT_GIMR_ET1 (1<<8)
#define | RBIT_GIMR_VECTOR (7<<5)
#define | RBIT_IPR_PB11 (1<<15)
#define | RBIT_IPR_PB10 (1<<14)
#define | RBIT_IPR_SCC1 (1<<13)
#define | RBIT_IPR_SDMA (1<<12)
#define | RBIT_IPR_IDMA (1<<11)
#define | RBIT_IPR_SCC2 (1<<10)
#define | RBIT_IPR_TIMER1 (1<<9)
#define | RBIT_IPR_SCC3 (1<<8)
#define | RBIT_IPR_PB9 (1<<7)
#define | RBIT_IPR_TIMER2 (1<<6)
#define | RBIT_IPR_SCP (1<<5)
#define | RBIT_IPR_TIMER3 (1<<4)
#define | RBIT_IPR_SMC1 (1<<3)
#define | RBIT_IPR_SMC2 (1<<2)
#define | RBIT_IPR_PB8 (1<<1)
#define | RBIT_IPR_ERR (1<<0)
#define | RBIT_ISR_PB11 (1<<15)
#define | RBIT_ISR_PB10 (1<<14)
#define | RBIT_ISR_SCC1 (1<<13)
#define | RBIT_ISR_SDMA (1<<12)
#define | RBIT_ISR_IDMA (1<<11)
#define | RBIT_ISR_SCC2 (1<<10)
#define | RBIT_ISR_TIMER1 (1<<9)
#define | RBIT_ISR_SCC3 (1<<8)
#define | RBIT_ISR_PB9 (1<<7)
#define | RBIT_ISR_TIMER2 (1<<6)
#define | RBIT_ISR_SCP (1<<5)
#define | RBIT_ISR_TIMER3 (1<<4)
#define | RBIT_ISR_SMC1 (1<<3)
#define | RBIT_ISR_SMC2 (1<<2)
#define | RBIT_ISR_PB8 (1<<1)
#define | RBIT_IMR_PB11 (1<<15) /* PB11 Interrupt Mask */
#define | RBIT_IMR_PB10 (1<<14) /* PB10 Interrupt Mask */
#define | RBIT_IMR_SCC1 (1<<13) /* SCC1 Interrupt Mask */
#define | RBIT_IMR_SDMA (1<<12) /* SDMA Interrupt Mask */
#define | RBIT_IMR_IDMA (1<<11) /* IDMA Interrupt Mask */
#define | RBIT_IMR_SCC2 (1<<10) /* SCC2 Interrupt Mask */
#define | RBIT_IMR_TIMER1 (1<<9) /* TIMER1 Interrupt Mask */
#define | RBIT_IMR_SCC3 (1<<8) /* SCC3 Interrupt Mask */
#define | RBIT_IMR_PB9 (1<<7) /* PB9 Interrupt Mask */
#define | RBIT_IMR_TIMER2 (1<<6) /* TIMER2 Interrupt Mask */
#define | RBIT_IMR_SCP (1<<5) /* SCP Interrupt Mask */
#define | RBIT_IMR_TIMER3 (1<<4) /* TIMER3 Interrupt Mask */
#define | RBIT_IMR_SMC1 (1<<3) /* SMC1 Interrupt Mask */
#define | RBIT_IMR_SMC2 (1<<2) /* SMC2 Interrupt Mask */
#define | RBIT_IMR_PB8 (1<<1) /* PB8 Interrupt Mask */
#define | RBIT_TMR_ICLK_STOP (0<<1)
#define | RBIT_TMR_ICLK_MASTER (1<<1)
#define | RBIT_TMR_ICLK_MASTER16 (2<<1)
#define | RBIT_TMR_ICLK_TIN (3<<1)
#define | RBIT_TMR_OM (1<<5)
#define | RBIT_TMR_ORI (1<<4)
#define | RBIT_TMR_FRR (1<<3)
#define | RBIT_TMR_RST (1<<0)
#define | RBIT_TER_REF (1<<1) /* Output Reference Event */
#define | RBIT_TER_CAP (1<<0) /* Capture Event */
#define | RCV_ERR 0x003F
#define | RBIT_UART_CTRL (1<<11) /* buffer contains a control char */
#define | RBIT_UART_ADDR (1<<10) /* first byte contains an address */
#define | RBIT_UART_MATCH (1<<9) /* indicates which addr char matched */
#define | RBIT_UART_IDLE (1<<8) /* buffer closed due to IDLE sequence */
#define | RBIT_UART_BR (1<<5) /* break sequence was received */
#define | RBIT_UART_FR (1<<4) /* framing error was received */
#define | RBIT_UART_PR (1<<3) /* parity error was received */
#define | RBIT_UART_OV (1<<1) /* receiver overrun occurred */
#define | RBIT_UART_CD (1<<0) /* carrier detect lost */
#define | RBIT_UART_STATUS 0x003B /* all status bits */
#define | RBIT_UART_CR
#define | RBIT_UART_A
#define | RBIT_UART_PREAMBLE (1<<9) /* send preamble before data */
#define | RBIT_UART_CTS_LOST (1<<0) /* CTS lost */
#define | M302_UART_EV_CTS (1<<7) /* CTS status changed */
#define | M302_UART_EV_CD (1<<6) /* carrier detect status changed */
#define | M302_UART_EV_IDL (1<<5) /* IDLE sequence status changed */
#define | M302_UART_EV_BRK (1<<4) /* break character was received */
#define | M302_UART_EV_CCR (1<<3) /* control character received */
#define | M302_UART_EV_TX (1<<1) /* buffer has been transmitted */
#define | M302_UART_EV_RX (1<<0) /* buffer has been received */
#define | RBIT_HDLC_EMPTY_BIT 0x8000 /* buffer associated with BD is empty */
#define | RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in a frame */
#define | RBIT_HDLC_FIRST_BIT 0x0400 /* buffer is first in a frame */
#define | RBIT_HDLC_FRAME_LEN 0x0020 /* receiver frame length violation */
#define | RBIT_HDLC_NONOCT_Rx 0x0010 /* received non-octet aligned frame */
#define | RBIT_HDLC_ABORT_SEQ 0x0008 /* received abort sequence */
#define | RBIT_HDLC_CRC_ERROR 0x0004 /* frame contains a CRC error */
#define | RBIT_HDLC_OVERRUN 0x0002 /* receiver overrun occurred */
#define | RBIT_HDLC_CD_LOST 0x0001 /* carrier detect lost */
#define | RBIT_HDLC_READY_BIT 0x8000 /* buffer is ready to transmit */
#define | RBIT_HDLC_EXT_BUFFER 0x4000 /* buffer is in external memory */
#define | RBIT_HDLC_WRAP_BIT 0x2000 /* last buffer in bd table, so wrap */
#define | RBIT_HDLC_WAKE_UP 0x1000 /* interrupt when buffer serviced */
#define | RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in the frame */
#define | RBIT_HDLC_TxCRC_BIT 0x0400 /* transmit a CRC sequence */
#define | RBIT_HDLC_UNDERRUN 0x0002 /* transmitter underrun */
#define | RBIT_HDLC_CTS_LOST 0x0001 /* CTS lost */
#define | RBIT_HDLC_CTS 0x80 /* CTS status changed */
#define | RBIT_HDLC_CD 0x40 /* carrier detect status changed */
#define | RBIT_HDLC_IDL 0x20 /* IDLE sequence status changed */
#define | RBIT_HDLC_TXE 0x10 /* transmit error */
#define | RBIT_HDLC_RXF 0x08 /* received frame */
#define | RBIT_HDLC_BSY
#define | RBIT_HDLC_TXB 0x02 /* buffer has been transmitted */
#define | RBIT_HDLC_RXB 0x01 /* received buffer */
#define | RBIT_SCON_WOMS
#define | RBIT_SCON_EXTC (1<<14) /* External Clock Source */
#define | RBIT_SCON_TCS (1<<13) /* Transmit Clock Source */
#define | RBIT_SCON_RCS (1<<12) /* Receive Clock Source */
#define | RBIT_SCM_ENR (1<<3) /* Enable receiver */
#define | RBIT_SCM_ENT (1<<2) /* Enable transmitter */
#define | BR_ENABLED 1
#define | BR_DISABLED 0
#define | BR_FC_NULL 0
#define | BR_READ_ONLY 0
#define | BR_READ_WRITE 2
#define | OR_DTACK_0 0x0000
#define | OR_DTACK_1 0x2000
#define | OR_DTACK_2 0x4000
#define | OR_DTACK_3 0x6000
#define | OR_DTACK_4 0x8000
#define | OR_DTACK_5 0xA000
#define | OR_DTACK_6 0xC000
#define | OR_DTACK_EXT 0xE000
#define | OR_SIZE_64K 0x1FE0
#define | OR_SIZE_128K 0x1FC0
#define | OR_SIZE_256K 0x1F80
#define | OR_SIZE_512K 0x1F00
#define | OR_SIZE_1M 0x1E00
#define | OR_SIZE_2M 0x1C00
#define | OR_MASK_RW 0x0000
#define | OR_NO_MASK_RW 0x0002
#define | OR_MASK_FC 0x0000
#define | OR_NO_MASK_FC 0x0001
#define | MAKE_BR(base_address, enable, rw, fc) ((base_address >> 11) | fc | rw | enable)
#define | MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask) (DtAck | ((~(bsize - 1) & 0x00FFFFFF) >> 11) | FC_Mask | RW_Mask)
#define | __REG_CAT(r, n) r ## n
#define | WRITE_BR(csel, base_address, enable, rw, fc) __REG_CAT(m302.reg.br, csel) = MAKE_BR(base_address, enable, rw, fc)
#define | WRITE_OR(csel, bsize, DtAck, RW_Mask, FC_Mask) __REG_CAT(m302.reg.or, csel) = MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask)
#define | WATCHDOG_ENABLE (1)
#define | WATCHDOG_TRIGGER() (m302.reg.wrr = 0x10 | WATCHDOG_ENABLE, m302.reg.wcn = 0)
#define | WATCHDOG_TOGGLE() (m302.reg.wcn = WATCHDOG_TIMEOUT_PERIOD)
#define | DISABLE_WATCHDOG() (m302.reg.wrr = 0)

## Typedefs
typedef struct m302_SCC_bd | m302_SCC_bd_t

## Enumerations
enum | m68302_ivec_e { M302_IVEC_ERR =0 , M302_IVEC_PB8 =1 , M302_IVEC_SMC2 =2 , M302_IVEC_SMC1 =3 , M302_IVEC_TIMER3 =4 , M302_IVEC_SCP =5 , M302_IVEC_TIMER2 =6 , M302_IVEC_PB9 =7 , M302_IVEC_SCC3 =8 , M302_IVEC_TIMER1 =9 , M302_IVEC_SCC2 =10 , M302_IVEC_IDMA =11 , M302_IVEC_SDMA =12 , M302_IVEC_SCC1 =13 , M302_IVEC_PB10 =14 , M302_IVEC_PB11 =15 , M302_IVEC_IRQ1 =17 , M302_IVEC_IRQ6 =22 , M302_IVEC_IRQ7 =23 }

## Variables
volatile m302_dualPortRAM_t | m302

## Detailed Description

Definitions for Motorola MC68302 Processor.

Section references in this file refer to revision 2 of Motorola's "MC68302 Integrated Multiprotocol Processor User's Manual". (Motorola document MC68302UM/AD REV 2.)

Based on Don Meyer's cpu68302.h that was posted in comp.sys.m68k on 17 February, 1993.

## Macro Definition Documentation

## ◆ RBIT_HDLC_BSY

#define RBIT_HDLC_BSY

Value:
0x04 /* frame rcvd and discarded due to
* lack of buffers
*/

## ◆ RBIT_SCON_WOMS

#define RBIT_SCON_WOMS

Value:
(1<<15) /* Wired-OR Mode Select (NMSI mode only)
* When set, the TXD driver is an
* open-drain output */

## ◆ RBIT_UART_A

#define RBIT_UART_A

Value:
(1<<10) /* buffer contains address characters
* only valid in multidrop mode (UM0=1)
*/

## ◆ RBIT_UART_CR

#define RBIT_UART_CR

Value:
(1<<11) /* clear-to-send report
* this results in two idle bits
* between back-to-back frames
*/