RTEMS: bsp_tlb_entry_t Struct Reference

| RTEMS 5.4-rc2

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Data Fields
bsp_tlb_entry_t Struct Reference
Board Support Packages » PowerPC » Xilinx Virtex-4 » Virtex 4 - MMU Support | Board Support Packages » PowerPC » Xilinx Virtex-5 » Virtex 5 - MMU Support

## Data Fields
struct {
uint32_t pad:24
uint32_t tid:8
} | id
struct {
uint32_t epn:22
uint32_t size:3
uint32_t v:1
uint32_t att:2
uint32_t pad:4
} | hi
struct {
uint32_t rpn:22
uint32_t perm:6
uint32_t wimg:4
} | lo
struct {
uint32_t pad:24
uint32_t tid:8
} | id
struct {
uint32_t epn:22
uint32_t v:1
uint32_t ts:1
uint32_t size:4
uint32_t tpar:4
} | w0
struct {
uint32_t rpn:22
uint32_t par1:2
uint32_t pad:4
uint32_t erpn:4
} | w1
struct {
uint32_t par2:2
uint32_t pad1:14
uint32_t att:4
uint32_t wimge:5
uint32_t pad2:1
uint32_t perm:6
} | w2

## Field Documentation

## ◆ att

uint32_t bsp_tlb_entry_t::att

Valid

## ◆

struct { ... } bsp_tlb_entry_t::lo

High word

## ◆ pad

uint32_t bsp_tlb_entry_t::pad

Little-endian, User-defined

For matching the TLB array parity

## ◆ pad1

uint32_t bsp_tlb_entry_t::pad1

Parity for TLB word 2

## ◆ pad2

uint32_t bsp_tlb_entry_t::pad2

Write-Through/Caching Inhibited/Memory Coherent/Guarded/Endian

## ◆ par1

uint32_t bsp_tlb_entry_t::par1

The real (translated) page number.

## ◆ perm

uint32_t bsp_tlb_entry_t::perm

Real page number

## ◆ size

uint32_t bsp_tlb_entry_t::size

Effective page number

Translation Address Space

## ◆ tpar

uint32_t bsp_tlb_entry_t::tpar

Page size

## ◆ ts

uint32_t bsp_tlb_entry_t::ts

Valid

## ◆ v

uint32_t bsp_tlb_entry_t::v

Page size

Effective page number

## ◆ wimg

uint32_t bsp_tlb_entry_t::wimg

Execute enable, Write-enable, Zone select

## ◆ wimge

uint32_t bsp_tlb_entry_t::wimge

User-defined attributes

The documentation for this struct was generated from the following files:

- bsps/powerpc/virtex4/include/bsp/mmu.h
- bsps/powerpc/virtex5/include/bsp/mmu.h