RTEMS: bsps/m68k/mcf5206elite/include/bsp.h Source File

| RTEMS 5.4-rc2

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bsp.h
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1
9/*
10 * Board Support Package for MCF5206eLITE evaluation board
11 * BSP definitions
12 *
13 * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
14 * Author: Victor V. Vengerov <vvv@oktet.ru>
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 *
19 * http://www.rtems.org/license/LICENSE.
20 */
21
22#ifndef LIBBSP_M68K_MCF5206ELITE_BSP_H
23#define LIBBSP_M68K_MCF5206ELITE_BSP_H
24
35#include "mcf5206/mcf5206e.h"
36
37/*** Board resources allocation ***/
38
39/*
40 * To achieve some compatibility with dBUG monitor, we use the same
41 * memory resources allocation as it is used in dBUG.
42 *
43 * If this definitions will be changed, change the linker script also.
44 */
45
46/* Memory mapping */
47/* CS0: Boot Flash */
48#define BSP_MEM_ADDR_FLASH (0xFFE00000)
49#define BSP_MEM_SIZE_FLASH (1*1024*1024)
50#define BSP_MEM_MASK_FLASH (MCF5206E_CSMR_MASK_1M)
51
52/* CS2: External SRAM */
53#define BSP_MEM_ADDR_ESRAM (0x30000000)
54#define BSP_MEM_SIZE_ESRAM (1*1024*1024)
55#define BSP_MEM_MASK_ESRAM (MCF5206E_CSMR_MASK_1M)
56
57/* CS3: General-Purpose I/O register */
58#define BSP_MEM_ADDR_GPIO (0x40000000)
59#define BSP_MEM_SIZE_GPIO (64*1024)
60#define BSP_MEM_MASK_GPIO (MCF5206E_CSMR_MASK_64K)
61
62/* DRAM0: Dynamic RAM */
63#define BSP_MEM_ADDR_DRAM (0x00000000)
64#define BSP_MEM_SIZE_DRAM (16*1024*1024)
65#define BSP_MEM_MASK_DRAM (MCF5206E_DCMR_MASK_16M)
66
67/* On-chip SRAM */
68#define BSP_MEM_ADDR_SRAM (0x20000000)
69#define BSP_MEM_SIZE_SRAM (8*1024)
70
71/* On-chip peripherial registers */
72#define BSP_MEM_ADDR_IMM (0x10000000)
73#define BSP_MEM_SIZE_IMM (1*1024)
74#define MBAR BSP_MEM_ADDR_IMM
75
76/* Interrupt vector assignment */
77#define BSP_INTVEC_AVEC1 (25)
78#define BSP_INTLVL_AVEC1 (1)
79#define BSP_INTPRIO_AVEC1 (3)
80
81#define BSP_INTVEC_AVEC2 (26)
82#define BSP_INTLVL_AVEC2 (2)
83#define BSP_INTPRIO_AVEC2 (3)
84
85#define BSP_INTVEC_AVEC3 (27)
86#define BSP_INTLVL_AVEC3 (3)
87#define BSP_INTPRIO_AVEC3 (3)
88
89#define BSP_INTVEC_AVEC4 (28)
90#define BSP_INTLVL_AVEC4 (4)
91#define BSP_INTPRIO_AVEC4 (3)
92
93#define BSP_INTVEC_AVEC5 (29)
94#define BSP_INTLVL_AVEC5 (5)
95#define BSP_INTPRIO_AVEC5 (3)
96
97#define BSP_INTVEC_AVEC6 (30)
98#define BSP_INTLVL_AVEC6 (6)
99#define BSP_INTPRIO_AVEC6 (3)
100
101#define BSP_INTVEC_AVEC7 (31)
102#define BSP_INTLVL_AVEC7 (7)
103#define BSP_INTPRIO_AVEC7 (3)
104
105#define BSP_INTVEC_TIMER1 (BSP_INTVEC_AVEC5)
106#define BSP_INTLVL_TIMER1 (BSP_INTLVL_AVEC5)
107#define BSP_INTPRIO_TIMER1 (2)
108
109#define BSP_INTVEC_TIMER2 (BSP_INTVEC_AVEC6)
110#define BSP_INTLVL_TIMER2 (BSP_INTLVL_AVEC6)
111#define BSP_INTPRIO_TIMER2 (2)
112
113#define BSP_INTVEC_MBUS (BSP_INTVEC_AVEC4)
114#define BSP_INTLVL_MBUS (BSP_INTLVL_AVEC4)
115#define BSP_INTPRIO_MBUS (2)
116
117#define BSP_INTVEC_UART1 (64)
118#define BSP_INTLVL_UART1 (4)
119#define BSP_INTPRIO_UART1 (0)
120
121#define BSP_INTVEC_UART2 (65)
122#define BSP_INTLVL_UART2 (4)
123#define BSP_INTPRIO_UART2 (1)
124
125#define BSP_INTVEC_DMA0 (66)
126#define BSP_INTLVL_DMA0 (3)
127#define BSP_INTPRIO_DMA0 (1)
128
129#define BSP_INTVEC_DMA1 (67)
130#define BSP_INTLVL_DMA1 (3)
131#define BSP_INTPRIO_DMA1 (2)
132
133/* Location of DS1307 Real-Time Clock/NVRAM chip */
134#define DS1307_I2C_BUS_NUMBER (0)
135
136#ifndef ASM
137
138#include <bspopts.h>
139#include <rtems.h>
140#include <bsp/default-initial-extension.h>
141
142#ifdef __cplusplus
143extern "C" {
144#endif
145
146/* System frequency */
147#define BSP_SYSTEM_FREQUENCY ((unsigned int)&_SYS_CLOCK_FREQUENCY)
148extern char _SYS_CLOCK_FREQUENCY; /* Don't use this variable directly!!! */
149
150/* MBUS I2C bus clock default frequency */
151#define BSP_MBUS_FREQUENCY (16000)
152
153/* Number of I2C buses supported in this board */
154#define I2C_NUMBER_OF_BUSES (1)
155
156/* I2C bus selection */
157#define I2C_SELECT_BUS(bus)
158
159/*
160 * Simple spin delay in microsecond units for device drivers.
161 * This is very dependent on the clock speed of the target.
162 */
163
164#define rtems_bsp_delay( microseconds ) \
165 { register uint32_t _delay=(microseconds); \
166 register uint32_t _tmp=123; \
167 __asm__ volatile( "0: \
168 nbcd %0 ; \
169 nbcd %0 ; \
170 dbf %1,0b" \
171 : "=d" (_tmp), "=d" (_delay) \
172 : "0" (_tmp), "1" (_delay) ); \
173 }
174
175
176extern rtems_isr_entry M68Kvec[]; /* vector table address */
177
178extern rtems_isr (*rtems_clock_hook)(rtems_vector_number);
179
180/* functions */
181
182rtems_isr_entry set_vector(
183 rtems_isr_entry handler,
184 rtems_vector_number vector,
185 int type
186);
187
188/*
189 * Prototypes for BSP methods that cross file boundaries
190 */
191void Init5206e(void);
192
193#ifdef __cplusplus
194}
195#endif
196
197#endif /* ASM */
198
201#endif
default-initial-extension.h
DEFAULT_INITIAL_EXTENSION Support.
rtems_isr
ISR_Handler rtems_isr
Return type for interrupt handler.
Definition: intr.h:52
rtems_vector_number
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition: intr.h:47
rtems.h