RTEMS: cpukit/score/cpu/sparc/include/rtems/score/sparc.h File Reference

| RTEMS 5.4-rc2

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Macros | Functions
sparc.h File Reference

Information Required to Build RTEMS for a Particular Member of the SPARC Family. More...

`#include <rtems/score/basedefs.h>`

Go to the source code of this file.

## Macros
#define | SPARC_HAS_BITSCAN 0
#define | SPARC_NUMBER_OF_REGISTER_WINDOWS 8
#define | SPARC_LEON3FT_B2BST_NOP
#define | SPARC_HAS_FPU 1
#define | CPU_MODEL_NAME "w/FPU"
#define | CPU_NAME "SPARC"
#define | SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */
#define | SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */
#define | SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */
#define | SPARC_PSR_S_MASK 0x00000080 /* bit 7 */
#define | SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */
#define | SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */
#define | SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */
#define | SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */
#define | SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */
#define | SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */
#define | SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */
#define | SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */
#define | SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */
#define | SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */
#define | SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */
#define | SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */
#define | SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */
#define | SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */
#define | SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */
#define | SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */
#define | LEON3_ASR17_PROCESSOR_INDEX_SHIFT 28
#define | SPARC_SWTRAP_SYSCALL 0
#define | SPARC_SWTRAP_IRQDIS 9
#define | SPARC_SWTRAP_IRQEN 10
#define | SPARC_SWTRAP_IRQDIS_FP 11
#define | nop()
#define | sparc_get_psr(_psr)
| Macro to obtain the PSR.
#define | sparc_set_psr(_psr)
| Macro to set the PSR.
#define | sparc_get_tbr(_tbr)
| Macro to obtain the TBR.
#define | sparc_set_tbr(_tbr)
| Macro to set the TBR.
#define | sparc_get_wim(_wim)
| Macro to obtain the WIM.
#define | sparc_set_wim(_wim)
| Macro to set the WIM.
#define | sparc_get_y(_y)
| Macro to obtain the Y register.
#define | sparc_set_y(_y)
| Macro to set the Y register.
#define | sparc_flash_interrupts(_psr)
| SPARC flash processor interrupts.
#define | sparc_get_interrupt_level(_level)
| SPARC obtain interrupt level.

## Functions
void | sparc_syscall_exit (uint32_t exitcode1, uint32_t exitcode2) RTEMS_NO_RETURN
| SPARC exit through system call 1.

## Detailed Description

Information Required to Build RTEMS for a Particular Member of the SPARC Family.

This file contains the information required to build RTEMS for a particular member of the SPARC family. It does this by setting variables to indicate which implementation dependent features are present in a particular member of the family.

## Macro Definition Documentation

## ◆ CPU_MODEL_NAME

#define CPU_MODEL_NAME "w/FPU"

This macro contains a string describing the multilib variant being build.

## ◆ CPU_NAME

#define CPU_NAME "SPARC"

Define the name of the CPU family.

## ◆ nop

#define nop | ( |  | ) |

Value:
do { \
__asm__ volatile ( "nop" ); \
} while ( 0 )

This macro is a standard nop instruction.

## ◆ sparc_flash_interrupts

#define sparc_flash_interrupts | ( |  | _psr | ) |

Value:
do { \
sparc_enable_interrupts( (_psr) ); \
_psr = sparc_disable_interrupts(); \
} while ( 0 )

SPARC flash processor interrupts.

This method is invoked to temporarily enable all maskable interrupts.

Parameters

  [in] | _psr | is the PSR returned by sparc_disable_interrupts.

## ◆ sparc_get_interrupt_level

#define sparc_get_interrupt_level | ( |  | _level | ) |

Value:
do { \
uint32_t _psr_level = 0; \
\
sparc_get_psr( _psr_level ); \
(_level) = \
(_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \
} while ( 0 )
SPARC_PSR_PIL_BIT_POSITION
#define SPARC_PSR_PIL_BIT_POSITION
Definition: sparc.h:148
SPARC_PSR_PIL_MASK
#define SPARC_PSR_PIL_MASK
Definition: sparc.h:127

SPARC obtain interrupt level.

This method is invoked to obtain the current interrupt disable level.

Parameters

  [in] | _level | is the PSR returned by sparc_disable_interrupts.

## ◆ sparc_get_psr

#define sparc_get_psr | ( |  | _psr | ) |

Value:
do { \
(_psr) = 0; \
__asm__ volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \
} while ( 0 )

Macro to obtain the PSR.

This macro returns the current contents of the PSR register in _psr.

## ◆ sparc_get_tbr

#define sparc_get_tbr | ( |  | _tbr | ) |

Value:
do { \
(_tbr) = 0; /* to avoid unitialized warnings */ \
__asm__ volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \
} while ( 0 )

Macro to obtain the TBR.

This macro returns the current contents of the TBR register in _tbr.

## ◆ sparc_get_wim

#define sparc_get_wim | ( |  | _wim | ) |

Value:
do { \
__asm__ volatile( "rd %%wim, %0" : "=r" (_wim) : "0" (_wim) ); \
} while ( 0 )

Macro to obtain the WIM.

This macro returns the current contents of the WIM field in _wim.

## ◆ sparc_get_y

#define sparc_get_y | ( |  | _y | ) |

Value:
do { \
__asm__ volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \
} while ( 0 )

Macro to obtain the Y register.

This macro returns the current contents of the Y register in _y.

## ◆ SPARC_HAS_BITSCAN

#define SPARC_HAS_BITSCAN 0

Some higher end SPARCs have a bitscan instructions. It would be nice to take advantage of them. Right now, there is no port to a CPU model with this feature and no (untested) code that is based on this feature flag.

## ◆ SPARC_HAS_FPU

#define SPARC_HAS_FPU 1

This macro indicates whether this multilib variation has hardware floating point or not. We use the gcc cpp predefine _SOFT_FLOAT to determine that.

## ◆ SPARC_LEON3FT_B2BST_NOP

#define SPARC_LEON3FT_B2BST_NOP

See GRLIB-TN-0009: "LEON3FT Stale Cache Entry After Store with Data Tag Parity Error"

## ◆ SPARC_NUMBER_OF_REGISTER_WINDOWS

#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8

This should be OK until a port to a higher end SPARC processor is made that has more than 8 register windows. If this cannot be determined based on multilib settings (v7/v8/v9), then the cpu_asm.S code that depends on this will have to move to libcpu.

## ◆ SPARC_PSR_CWP_BIT_POSITION

#define SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */

This constant is the starting bit position of the CWP in the PSR.

## ◆ SPARC_PSR_CWP_MASK

#define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */

PSR masks and starting bit positions

NOTE: Reserved bits are ignored.

## ◆ SPARC_PSR_EC_BIT_POSITION

#define SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */

This constant is the starting bit position of the EC in the PSR.

## ◆ SPARC_PSR_EC_MASK

#define SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */

This constant is a mask for the EC bits in the PSR.

## ◆ SPARC_PSR_EF_BIT_POSITION

#define SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */

This constant is the starting bit position of the EF in the PSR.

## ◆ SPARC_PSR_EF_MASK

#define SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */

This constant is a mask for the EF bits in the PSR.

## ◆ SPARC_PSR_ET_BIT_POSITION

#define SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */

This constant is the starting bit position of the ET in the PSR.

## ◆ SPARC_PSR_ET_MASK

#define SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */

This constant is a mask for the ET bits in the PSR.

## ◆ SPARC_PSR_ICC_BIT_POSITION

#define SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */

This constant is the starting bit position of the ICC in the PSR.

## ◆ SPARC_PSR_ICC_MASK

#define SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */

This constant is a mask for the ICC bits in the PSR.

## ◆ SPARC_PSR_IMPL_BIT_POSITION

#define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */

This constant is the starting bit position of the IMPL in the PSR.

## ◆ SPARC_PSR_IMPL_MASK

#define SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */

This constant is a mask for the IMPL bits in the PSR.

## ◆ SPARC_PSR_PIL_BIT_POSITION

#define SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */

This constant is the starting bit position of the PIL in the PSR.

## ◆ SPARC_PSR_PIL_MASK

#define SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */

This constant is a mask for the PIL bits in the PSR.

## ◆ SPARC_PSR_PS_BIT_POSITION

#define SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */

This constant is the starting bit position of the PS in the PSR.

## ◆ SPARC_PSR_PS_MASK

#define SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */

This constant is a mask for the PS bits in the PSR.

## ◆ SPARC_PSR_S_BIT_POSITION

#define SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */

This constant is the starting bit position of the S in the PSR.

## ◆ SPARC_PSR_S_MASK

#define SPARC_PSR_S_MASK 0x00000080 /* bit 7 */

This constant is a mask for the S bits in the PSR.

## ◆ SPARC_PSR_VER_BIT_POSITION

#define SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */

This constant is the starting bit position of the VER in the PSR.

## ◆ SPARC_PSR_VER_MASK

#define SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */

This constant is a mask for the VER bits in the PSR.

## ◆ sparc_set_psr

#define sparc_set_psr | ( |  | _psr | ) |

Value:
do { \
__asm__ volatile ( "mov %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \
nop(); \
nop(); \
nop(); \
} while ( 0 )

Macro to set the PSR.

This macro sets the PSR register to the value in _psr.

## ◆ sparc_set_tbr

#define sparc_set_tbr | ( |  | _tbr | ) |

Value:
do { \
__asm__ volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \
} while ( 0 )

Macro to set the TBR.

This macro sets the TBR register to the value in _tbr.

## ◆ sparc_set_wim

#define sparc_set_wim | ( |  | _wim | ) |

Value:
do { \
__asm__ volatile( "wr %0, %%wim" : "=r" (_wim) : "0" (_wim) ); \
nop(); \
nop(); \
nop(); \
} while ( 0 )

Macro to set the WIM.

This macro sets the WIM field to the value in _wim.

## ◆ sparc_set_y

#define sparc_set_y | ( |  | _y | ) |

Value:
do { \
__asm__ volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \
} while ( 0 )

Macro to set the Y register.

This macro sets the Y register to the value in _y.

## Function Documentation

## ◆ sparc_syscall_exit()

void sparc_syscall_exit | ( | uint32_t | exitcode1,
|  | uint32_t | exitcode2
| ) |  |

SPARC exit through system call 1.

This method is invoked to go into system error halt. The optional arguments can be given to hypervisor, hardware debugger, simulator or similar.

System error mode is entered when taking a trap when traps have been disabled. What happens when error mode is entered depends on the motherboard. In a typical development systems the CPU relingish control to the debugger, simulator, hypervisor or similar. The following steps are taken:

1. Going into system error mode by Software Trap 0
2. g1=1 (syscall 1 - Exit)
3. g2=Primary exit code
4. g3=Secondary exit code. Dependends on g2 exit type.

This function never returns.

Parameters

  [in] | exitcode1 | Primary exit code stored in CPU g2 register after exit
  [in] | exitcode2 | Primary exit code stored in CPU g3 register after exit