RTEMS: bsps/shared/dev/serial/z85c30_p.h Source File

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z85c30_p.h
1/*
2 * This include file contains all private driver definitions for the
3 * Zilog z85c30.
4 *
5 * COPYRIGHT (c) 1998 by Radstone Technology
6 *
7 *
8 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
9 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
10 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
11 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
12 *
13 * You are hereby granted permission to use, copy, modify, and distribute
14 * this file, provided that this notice, plus the above copyright notice
15 * and disclaimer, appears in all copies. Radstone Technology will provide
16 * no support for this code.
17 *
18 * COPYRIGHT (c) 1989-1997.
19 * On-Line Applications Research Corporation (OAR).
20 *
21 * The license and distribution terms for this file may in
22 * the file LICENSE in this distribution or at
23 * http://www.rtems.org/license/LICENSE.
24 */
25
26#ifndef __Z85C30_P_H
27#define __Z85C30_P_H
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33/*
34 * Define Z85C30_STATIC to nothing while debugging so the entry points
35 * will show up in the symbol table.
36 */
37
38#define Z85C30_STATIC
39
40/* #define Z85C30_STATIC static */
41
42/* bit values for write register 0 */
43/* command register */
44
45#define SCC_WR0_SEL_WR0 0x00
46#define SCC_WR0_SEL_WR1 0x01
47#define SCC_WR0_SEL_WR2 0x02
48#define SCC_WR0_SEL_WR3 0x03
49#define SCC_WR0_SEL_WR4 0x04
50#define SCC_WR0_SEL_WR5 0x05
51#define SCC_WR0_SEL_WR6 0x06
52#define SCC_WR0_SEL_WR7 0x07
53#define SCC_WR0_SEL_WR8 0x08
54#define SCC_WR0_SEL_WR9 0x09
55#define SCC_WR0_SEL_WR10 0x0a
56#define SCC_WR0_SEL_WR11 0x0b
57#define SCC_WR0_SEL_WR12 0x0c
58#define SCC_WR0_SEL_WR13 0x0d
59#define SCC_WR0_SEL_WR14 0x0e
60#define SCC_WR0_SEL_WR15 0x0f
61#define SCC_WR0_SEL_RD0 0x00
62#define SCC_WR0_SEL_RD1 0x01
63#define SCC_WR0_SEL_RD2 0x02
64#define SCC_WR0_SEL_RD3 0x03
65#define SCC_WR0_SEL_RD4 0x04
66#define SCC_WR0_SEL_RD5 0x05
67#define SCC_WR0_SEL_RD6 0x06
68#define SCC_WR0_SEL_RD7 0x07
69#define SCC_WR0_SEL_RD8 0x08
70#define SCC_WR0_SEL_RD9 0x09
71#define SCC_WR0_SEL_RD10 0x0a
72#define SCC_WR0_SEL_RD11 0x0b
73#define SCC_WR0_SEL_RD12 0x0c
74#define SCC_WR0_SEL_RD13 0x0d
75#define SCC_WR0_SEL_RD14 0x0e
76#define SCC_WR0_SEL_RD15 0x0f
77#define SCC_WR0_NULL_CODE 0x00
78#define SCC_WR0_RST_INT 0x10
79#define SCC_WR0_SEND_ABORT 0x18
80#define SCC_WR0_EN_INT_RX 0x20
81#define SCC_WR0_RST_TX_INT 0x28
82#define SCC_WR0_ERR_RST 0x30
83#define SCC_WR0_RST_HI_IUS 0x38
84#define SCC_WR0_RST_RX_CRC 0x40
85#define SCC_WR0_RST_TX_CRC 0x80
86#define SCC_WR0_RST_TX_UND 0xc0
87
88/* write register 2 */
89/* interrupt vector */
90
91/* bit values for write register 1 */
92/* tx/rx interrupt and data transfer mode definition */
93
94#define SCC_WR1_EXT_INT_EN 0x01
95#define SCC_WR1_TX_INT_EN 0x02
96#define SCC_WR1_PARITY 0x04
97#define SCC_WR1_RX_INT_DIS 0x00
98#define SCC_WR1_RX_INT_FIR 0x08
99#define SCC_WR1_INT_ALL_RX 0x10
100#define SCC_WR1_RX_INT_SPE 0x18
101#define SCC_WR1_RDMA_RECTR 0x20
102#define SCC_WR1_RDMA_FUNC 0x40
103#define SCC_WR1_RDMA_EN 0x80
104
105#define SCC_ENABLE_ALL_INTR \
106 (SCC_WR1_EXT_INT_EN | SCC_WR1_TX_INT_EN | SCC_WR1_INT_ALL_RX)
107
108#define SCC_DISABLE_ALL_INTR 0x00
109
110#define SCC_ENABLE_ALL_INTR_EXCEPT_TX \
111 (SCC_WR1_EXT_INT_EN | SCC_WR1_INT_ALL_RX)
112
113/* bit values for write register 3 */
114/* receive parameters and control */
115
116#define SCC_WR3_RX_EN 0x01
117#define SCC_WR3_SYNC_CHAR 0x02
118#define SCC_WR3_ADR_SEARCH 0x04
119#define SCC_WR3_RX_CRC_EN 0x08
120#define SCC_WR3_ENTER_HUNT 0x10
121#define SCC_WR3_AUTO_EN 0x20
122#define SCC_WR3_RX_5_BITS 0x00
123#define SCC_WR3_RX_7_BITS 0x40
124#define SCC_WR3_RX_6_BITS 0x80
125#define SCC_WR3_RX_8_BITS 0xc0
126
127/* bit values for write register 4 */
128/* tx/rx misc parameters and modes */
129
130#define SCC_WR4_PAR_EN 0x01
131#define SCC_WR4_PAR_EVEN 0x02
132#define SCC_WR4_SYNC_EN 0x00
133#define SCC_WR4_1_STOP 0x04
134#define SCC_WR4_2_STOP 0x0c
135#define SCC_WR4_8_SYNC 0x00
136#define SCC_WR4_16_SYNC 0x10
137#define SCC_WR4_SDLC 0x20
138#define SCC_WR4_EXT_SYNC 0x30
139#define SCC_WR4_1_CLOCK 0x00
140#define SCC_WR4_16_CLOCK 0x40
141#define SCC_WR4_32_CLOCK 0x80
142#define SCC_WR4_64_CLOCK 0xc0
143
144/* bit values for write register 5 */
145/* transmit parameter and controls */
146
147#define SCC_WR5_TX_CRC_EN 0x01
148#define SCC_WR5_RTS 0x02
149#define SCC_WR5_SDLC 0x04
150#define SCC_WR5_TX_EN 0x08
151#define SCC_WR5_SEND_BRK 0x10
152
153#define SCC_WR5_TX_5_BITS 0x00
154#define SCC_WR5_TX_7_BITS 0x20
155#define SCC_WR5_TX_6_BITS 0x40
156#define SCC_WR5_TX_8_BITS 0x60
157#define SCC_WR5_DTR 0x80
158
159/* write register 6 */
160/* sync chars or sdlc address field */
161
162/* write register 7 */
163/* sync char or sdlc flag */
164
165/* write register 8 */
166/* transmit buffer */
167
168/* bit values for write register 9 */
169/* master interrupt control */
170
171#define SCC_WR9_VIS 0x01
172#define SCC_WR9_NV 0x02
173#define SCC_WR9_DLC 0x04
174#define SCC_WR9_MIE 0x08
175#define SCC_WR9_STATUS_HI 0x10
176#define SCC_WR9_NO_RST 0x00
177#define SCC_WR9_CH_B_RST 0x40
178#define SCC_WR9_CH_A_RST 0x80
179#define SCC_WR9_HDWR_RST 0xc0
180
181/* bit values for write register 10 */
182/* misc tx/rx control bits */
183
184#define SCC_WR10_6_BIT_SYNC 0x01
185#define SCC_WR10_LOOP_MODE 0x02
186#define SCC_WR10_ABORT_UND 0x04
187#define SCC_WR10_MARK_IDLE 0x08
188#define SCC_WR10_ACT_POLL 0x10
189#define SCC_WR10_NRZ 0x00
190#define SCC_WR10_NRZI 0x20
191#define SCC_WR10_FM1 0x40
192#define SCC_WR10_FM0 0x60
193#define SCC_WR10_CRC_PRESET 0x80
194
195/* bit values for write register 11 */
196/* clock mode control */
197
198#define SCC_WR11_OUT_XTAL 0x00
199#define SCC_WR11_OUT_TX_CLK 0x01
200#define SCC_WR11_OUT_BR_GEN 0x02
201#define SCC_WR11_OUT_DPLL 0x03
202#define SCC_WR11_TRXC_OI 0x04
203#define SCC_WR11_TX_RTXC 0x00
204#define SCC_WR11_TX_TRXC 0x08
205#define SCC_WR11_TX_BR_GEN 0x10
206#define SCC_WR11_TX_DPLL 0x18
207#define SCC_WR11_RX_RTXC 0x00
208#define SCC_WR11_RX_TRXC 0x20
209#define SCC_WR11_RX_BR_GEN 0x40
210#define SCC_WR11_RX_DPLL 0x60
211#define SCC_WR11_RTXC_XTAL 0x80
212
213/* write register 12 */
214/* lower byte of baud rate generator time constant */
215
216/* write register 13 */
217/* upper byte of baud rate generator time constant */
218
219/* bit values for write register 14 */
220/* misc control bits */
221
222#define SCC_WR14_BR_EN 0x01
223#define SCC_WR14_BR_SRC 0x02
224#define SCC_WR14_DTR_FUNC 0x04
225#define SCC_WR14_AUTO_ECHO 0x08
226#define SCC_WR14_LCL_LOOP 0x10
227#define SCC_WR14_NULL 0x00
228#define SCC_WR14_SEARCH 0x20
229#define SCC_WR14_RST_CLK 0x40
230#define SCC_WR14_DIS_DPLL 0x60
231#define SCC_WR14_SRC_BR 0x80
232#define SCC_WR14_SRC_RTXC 0xa0
233#define SCC_WR14_FM_MODE 0xc0
234#define SCC_WR14_NRZI 0xe0
235
236/* bit values for write register 15 */
237/* external/status interrupt control */
238
239#define SCC_WR15_ZERO_CNT 0x02
240#define SCC_WR15_CD_IE 0x08
241#define SCC_WR15_SYNC_IE 0x10
242#define SCC_WR15_CTS_IE 0x20
243#define SCC_WR15_TX_UND_IE 0x40
244#define SCC_WR15_BREAK_IE 0x80
245
246/* bit values for read register 0 */
247/* tx/rx buffer status and external status */
248
249#define SCC_RR0_RX_AVAIL 0x01
250#define SCC_RR0_ZERO_CNT 0x02
251#define SCC_RR0_TX_EMPTY 0x04
252#define SCC_RR0_CD 0x08
253#define SCC_RR0_SYNC 0x10
254#define SCC_RR0_CTS 0x20
255#define SCC_RR0_TX_UND 0x40
256#define SCC_RR0_BREAK 0x80
257
258/* bit values for read register 1 */
259
260#define SCC_RR1_ALL_SENT 0x01
261#define SCC_RR1_RES_CD_2 0x02
262#define SCC_RR1_RES_CD_1 0x01
263#define SCC_RR1_RES_CD_0 0x08
264#define SCC_RR1_PAR_ERR 0x10
265#define SCC_RR1_RX_OV_ERR 0x20
266#define SCC_RR1_CRC_ERR 0x40
267#define SCC_RR1_END_FRAME 0x80
268
269/* read register 2 */
270/* interrupt vector */
271
272/* bit values for read register 3 */
273/* interrupt pending register */
274
275#define SCC_RR3_B_EXT_IP 0x01
276#define SCC_RR3_B_TX_IP 0x02
277#define SCC_RR3_B_RX_IP 0x04
278#define SCC_RR3_A_EXT_IP 0x08
279#define SCC_RR3_A_TX_IP 0x10
280#define SCC_RR3_A_RX_IP 0x20
281
282/* read register 8 */
283/* receive data register */
284
285/* bit values for read register 10 */
286/* misc status bits */
287
288#define SCC_RR10_ON_LOOP 0x02
289#define SCC_RR10_LOOP_SEND 0x10
290#define SCC_RR10_2_CLK_MIS 0x40
291#define SCC_RR10_1_CLK_MIS 0x80
292
293/* read register 12 */
294/* lower byte of time constant */
295
296/* read register 13 */
297/* upper byte of time constant */
298
299/* bit values for read register 15 */
300/* external/status ie bits */
301
302#define SCC_RR15_ZERO_CNT 0x02
303#define SCC_RR15_CD_IE 0x08
304#define SCC_RR15_SYNC_IE 0x10
305#define SCC_RR15_CTS_IE 0x20
306#define SCC_RR15_TX_UND_IE 0x40
307#define SCC_RR15_BREAK_IE 0x80
308
309 typedef struct _z85c30_context
310{
311 uint8_t ucModemCtrl;
312} z85c30_context;
313
314/*
315 * The following macro calculates the Baud constant. For the Z85C30 chip.
316 *
317 * Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2
318 * eg ((10,000,000 / 16) / (2 * Baud Rate)) - 2
319 */
320
321#define Z85C30_Baud( _clock, _baud_rate ) \
322 ( ((_clock) /( 16 * 2 * _baud_rate)) - 2)
323
324#define Z85C30_Status_Is_RX_character_available(_status) \
325 ((_status) & SCC_RR0_RX_AVAIL)
326
327#define Z85C30_Status_Is_TX_buffer_empty(_status) \
328 ((_status) & SCC_RR0_TX_EMPTY)
329
330#define Z85C30_Status_Is_CTS_asserted(_status) \
331 ((_status) & SCC_RR0_CTS)
332
333#define Z85C30_Status_Is_break_abort(_status) \
334 ((_status) & SCC_RR0_BREAK)
335
336/*
337 * Private routines
338 */
339
340Z85C30_STATIC void z85c30_initialize_port(
341 int minor
342);
343
344Z85C30_STATIC void z85c30_init(int minor);
345
346Z85C30_STATIC int z85c30_set_attributes(
347 int minor,
348 const struct termios *t
349);
350
351Z85C30_STATIC int z85c30_open(
352 int major,
353 int minor,
354 void * arg
355);
356
357Z85C30_STATIC int z85c30_close(
358 int major,
359 int minor,
360 void * arg
361);
362
363Z85C30_STATIC void z85c30_write_polled(
364 int minor,
365 char cChar
366);
367
368Z85C30_STATIC int z85c30_assert_RTS(
369 int minor
370);
371
372Z85C30_STATIC int z85c30_negate_RTS(
373 int minor
374);
375
376Z85C30_STATIC int z85c30_assert_DTR(
377 int minor
378);
379
380Z85C30_STATIC int z85c30_negate_DTR(
381 int minor
382);
383
384Z85C30_STATIC void z85c30_initialize_interrupts(int minor);
385
386Z85C30_STATIC ssize_t z85c30_write_support_int(
387 int minor,
388 const char *buf,
389 size_t len
390);
391
392Z85C30_STATIC ssize_t z85c30_write_support_polled(
393 int minor,
394 const char *buf,
395 size_t len
396);
397
398Z85C30_STATIC int z85c30_inbyte_nonblocking_polled(
399 int minor
400);
401
402Z85C30_STATIC void z85c30_enable_interrupts(
403 int minor,
404 int interrupt_mask
405);
406
407Z85C30_STATIC void z85c30_process(
408 int minor,
409 uint8_t ucIntPend
410);
411
412Z85C30_STATIC rtems_isr z85c30_isr(
413 rtems_vector_number vector
414);
415
416#ifdef __cplusplus
417}
418#endif
419
420#endif
rtems_isr
ISR_Handler rtems_isr
Return type for interrupt handler.
Definition: intr.h:52
rtems_vector_number
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition: intr.h:47
_z85c30_context
Definition: z85c30_p.h:310