RTEMS: Qspi Struct Reference

| RTEMS 5.4-rc2

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Data Fields
Qspi Struct Reference

Qspi hardware registers. More...

`#include <component_qspi.h>`

## Data Fields
__O uint32_t | QSPI_CR
| (Qspi Offset: 0x00) Control Register
__IO uint32_t | QSPI_MR
| (Qspi Offset: 0x04) Mode Register
__I uint32_t | QSPI_RDR
| (Qspi Offset: 0x08) Receive Data Register
__O uint32_t | QSPI_TDR
| (Qspi Offset: 0x0C) Transmit Data Register
__I uint32_t | QSPI_SR
| (Qspi Offset: 0x10) Status Register
__O uint32_t | QSPI_IER
| (Qspi Offset: 0x14) Interrupt Enable Register
__O uint32_t | QSPI_IDR
| (Qspi Offset: 0x18) Interrupt Disable Register
__I uint32_t | QSPI_IMR
| (Qspi Offset: 0x1C) Interrupt Mask Register
__IO uint32_t | QSPI_SCR
| (Qspi Offset: 0x20) Serial Clock Register
__I uint32_t | Reserved1 [3]
__IO uint32_t | QSPI_IAR
| (Qspi Offset: 0x30) Instruction Address Register
__IO uint32_t | QSPI_ICR
| (Qspi Offset: 0x34) Instruction Code Register
__IO uint32_t | QSPI_IFR
| (Qspi Offset: 0x38) Instruction Frame Register
__I uint32_t | Reserved2 [1]
__IO uint32_t | QSPI_SMR
| (Qspi Offset: 0x40) Scrambling Mode Register
__O uint32_t | QSPI_SKR
| (Qspi Offset: 0x44) Scrambling Key Register
__I uint32_t | Reserved3 [39]
__IO uint32_t | QSPI_WPMR
| (Qspi Offset: 0xE4) Write Protection Mode Register
__I uint32_t | QSPI_WPSR
| (Qspi Offset: 0xE8) Write Protection Status Register
__I uint32_t | Reserved4 [4]
__I uint32_t | QSPI_VERSION
| (Qspi Offset: 0x00FC) Version Register

## Detailed Description

Qspi hardware registers.

The documentation for this struct was generated from the following files:

- bsps/arm/atsam/include/libchip/include/same70/component/component_qspi.h
- bsps/arm/atsam/include/libchip/include/sams70/component/component_qspi.h
- bsps/arm/atsam/include/libchip/include/samv71/component/component_qspi.h