RTEMS: bsps/arm/atsam/include/libchip/include/sams70/component/component_usart.h Source File

| RTEMS 5.4-rc2

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component_usart.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70_USART_COMPONENT_
31#define _SAMS70_USART_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __O uint32_t US_CR;
43 __IO uint32_t US_MR;
44 __O uint32_t US_IER;
45 __O uint32_t US_IDR;
46 __I uint32_t US_IMR;
47 __I uint32_t US_CSR;
48 __I uint32_t US_RHR;
49 __O uint32_t US_THR;
50 __IO uint32_t US_BRGR;
51 __IO uint32_t US_RTOR;
52 __IO uint32_t US_TTGR;
53 __I uint32_t Reserved1[5];
54 __IO uint32_t US_FIDI;
55 __I uint32_t US_NER;
56 __I uint32_t Reserved2[1];
57 __IO uint32_t US_IF;
58 __IO uint32_t US_MAN;
59 __IO uint32_t US_LINMR;
60 __IO uint32_t US_LINIR;
61 __I uint32_t US_LINBRR;
62 __IO uint32_t US_LONMR;
63 __IO uint32_t US_LONPR;
64 __IO uint32_t US_LONDL;
65 __IO uint32_t US_LONL2HDR;
66 __I uint32_t US_LONBL;
67 __IO uint32_t US_LONB1TX;
68 __IO uint32_t US_LONB1RX;
69 __IO uint32_t US_LONPRIO;
70 __IO uint32_t US_IDTTX;
71 __IO uint32_t US_IDTRX;
72 __IO uint32_t US_ICDIFF;
73 __I uint32_t Reserved3[22];
74 __IO uint32_t US_WPMR;
75 __I uint32_t US_WPSR;
76} Usart;
77#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
78/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
79#define US_CR_RSTRX (0x1u << 2)
80#define US_CR_RSTTX (0x1u << 3)
81#define US_CR_RXEN (0x1u << 4)
82#define US_CR_RXDIS (0x1u << 5)
83#define US_CR_TXEN (0x1u << 6)
84#define US_CR_TXDIS (0x1u << 7)
85#define US_CR_RSTSTA (0x1u << 8)
86#define US_CR_STTBRK (0x1u << 9)
87#define US_CR_STPBRK (0x1u << 10)
88#define US_CR_STTTO (0x1u << 11)
89#define US_CR_SENDA (0x1u << 12)
90#define US_CR_RSTIT (0x1u << 13)
91#define US_CR_RSTNACK (0x1u << 14)
92#define US_CR_RETTO (0x1u << 15)
93#define US_CR_DTREN (0x1u << 16)
94#define US_CR_DTRDIS (0x1u << 17)
95#define US_CR_RTSEN (0x1u << 18)
96#define US_CR_RTSDIS (0x1u << 19)
97#define US_CR_LINABT (0x1u << 20)
98#define US_CR_LINWKUP (0x1u << 21)
99#define US_CR_FCS (0x1u << 18)
100#define US_CR_RCS (0x1u << 19)
101/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
102#define US_MR_USART_MODE_Pos 0
103#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos)
104#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos)))
105#define US_MR_USART_MODE_NORMAL (0x0u << 0)
106#define US_MR_USART_MODE_RS485 (0x1u << 0)
107#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0)
108#define US_MR_USART_MODE_MODEM (0x3u << 0)
109#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0)
110#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0)
111#define US_MR_USART_MODE_IRDA (0x8u << 0)
112#define US_MR_USART_MODE_LON (0x9u << 0)
113#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0)
114#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0)
115#define US_MR_USCLKS_Pos 4
116#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos)
117#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos)))
118#define US_MR_USCLKS_MCK (0x0u << 4)
119#define US_MR_USCLKS_DIV (0x1u << 4)
120#define US_MR_USCLKS_PCK (0x2u << 4)
121#define US_MR_USCLKS_SCK (0x3u << 4)
122#define US_MR_CHRL_Pos 6
123#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos)
124#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos)))
125#define US_MR_CHRL_5_BIT (0x0u << 6)
126#define US_MR_CHRL_6_BIT (0x1u << 6)
127#define US_MR_CHRL_7_BIT (0x2u << 6)
128#define US_MR_CHRL_8_BIT (0x3u << 6)
129#define US_MR_SYNC (0x1u << 8)
130#define US_MR_PAR_Pos 9
131#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos)
132#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos)))
133#define US_MR_PAR_EVEN (0x0u << 9)
134#define US_MR_PAR_ODD (0x1u << 9)
135#define US_MR_PAR_SPACE (0x2u << 9)
136#define US_MR_PAR_MARK (0x3u << 9)
137#define US_MR_PAR_NO (0x4u << 9)
138#define US_MR_PAR_MULTIDROP (0x6u << 9)
139#define US_MR_NBSTOP_Pos 12
140#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos)
141#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos)))
142#define US_MR_NBSTOP_1_BIT (0x0u << 12)
143#define US_MR_NBSTOP_1_5_BIT (0x1u << 12)
144#define US_MR_NBSTOP_2_BIT (0x2u << 12)
145#define US_MR_CHMODE_Pos 14
146#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos)
147#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos)))
148#define US_MR_CHMODE_NORMAL (0x0u << 14)
149#define US_MR_CHMODE_AUTOMATIC (0x1u << 14)
150#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14)
151#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14)
152#define US_MR_MSBF (0x1u << 16)
153#define US_MR_MODE9 (0x1u << 17)
154#define US_MR_CLKO (0x1u << 18)
155#define US_MR_OVER (0x1u << 19)
156#define US_MR_INACK (0x1u << 20)
157#define US_MR_DSNACK (0x1u << 21)
158#define US_MR_VAR_SYNC (0x1u << 22)
159#define US_MR_INVDATA (0x1u << 23)
160#define US_MR_MAX_ITERATION_Pos 24
161#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos)
162#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
163#define US_MR_FILTER (0x1u << 28)
164#define US_MR_MAN (0x1u << 29)
165#define US_MR_MODSYNC (0x1u << 30)
166#define US_MR_ONEBIT (0x1u << 31)
167#define US_MR_CPHA (0x1u << 8)
168#define US_MR_CPOL (0x1u << 16)
169#define US_MR_WRDBT (0x1u << 20)
170/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
171#define US_IER_RXRDY (0x1u << 0)
172#define US_IER_TXRDY (0x1u << 1)
173#define US_IER_RXBRK (0x1u << 2)
174#define US_IER_OVRE (0x1u << 5)
175#define US_IER_FRAME (0x1u << 6)
176#define US_IER_PARE (0x1u << 7)
177#define US_IER_TIMEOUT (0x1u << 8)
178#define US_IER_TXEMPTY (0x1u << 9)
179#define US_IER_ITER (0x1u << 10)
180#define US_IER_NACK (0x1u << 13)
181#define US_IER_RIIC (0x1u << 16)
182#define US_IER_DSRIC (0x1u << 17)
183#define US_IER_DCDIC (0x1u << 18)
184#define US_IER_CTSIC (0x1u << 19)
185#define US_IER_MANE (0x1u << 24)
186#define US_IER_UNRE (0x1u << 10)
187#define US_IER_NSSE (0x1u << 19)
188#define US_IER_LINBK (0x1u << 13)
189#define US_IER_LINID (0x1u << 14)
190#define US_IER_LINTC (0x1u << 15)
191#define US_IER_LINBE (0x1u << 25)
192#define US_IER_LINISFE (0x1u << 26)
193#define US_IER_LINIPE (0x1u << 27)
194#define US_IER_LINCE (0x1u << 28)
195#define US_IER_LINSNRE (0x1u << 29)
196#define US_IER_LINSTE (0x1u << 30)
197#define US_IER_LINHTE (0x1u << 31)
198#define US_IER_LSFE (0x1u << 6)
199#define US_IER_LCRCE (0x1u << 7)
200#define US_IER_LTXD (0x1u << 24)
201#define US_IER_LCOL (0x1u << 25)
202#define US_IER_LFET (0x1u << 26)
203#define US_IER_LRXD (0x1u << 27)
204#define US_IER_LBLOVFE (0x1u << 28)
205/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
206#define US_IDR_RXRDY (0x1u << 0)
207#define US_IDR_TXRDY (0x1u << 1)
208#define US_IDR_RXBRK (0x1u << 2)
209#define US_IDR_OVRE (0x1u << 5)
210#define US_IDR_FRAME (0x1u << 6)
211#define US_IDR_PARE (0x1u << 7)
212#define US_IDR_TIMEOUT (0x1u << 8)
213#define US_IDR_TXEMPTY (0x1u << 9)
214#define US_IDR_ITER (0x1u << 10)
215#define US_IDR_NACK (0x1u << 13)
216#define US_IDR_RIIC (0x1u << 16)
217#define US_IDR_DSRIC (0x1u << 17)
218#define US_IDR_DCDIC (0x1u << 18)
219#define US_IDR_CTSIC (0x1u << 19)
220#define US_IDR_MANE (0x1u << 24)
221#define US_IDR_UNRE (0x1u << 10)
222#define US_IDR_NSSE (0x1u << 19)
223#define US_IDR_LINBK (0x1u << 13)
224#define US_IDR_LINID (0x1u << 14)
225#define US_IDR_LINTC (0x1u << 15)
226#define US_IDR_LINBE (0x1u << 25)
227#define US_IDR_LINISFE (0x1u << 26)
228#define US_IDR_LINIPE (0x1u << 27)
229#define US_IDR_LINCE (0x1u << 28)
230#define US_IDR_LINSNRE (0x1u << 29)
231#define US_IDR_LINSTE (0x1u << 30)
232#define US_IDR_LINHTE (0x1u << 31)
233#define US_IDR_LSFE (0x1u << 6)
234#define US_IDR_LCRCE (0x1u << 7)
235#define US_IDR_LTXD (0x1u << 24)
236#define US_IDR_LCOL (0x1u << 25)
237#define US_IDR_LFET (0x1u << 26)
238#define US_IDR_LRXD (0x1u << 27)
239#define US_IDR_LBLOVFE (0x1u << 28)
240/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
241#define US_IMR_RXRDY (0x1u << 0)
242#define US_IMR_TXRDY (0x1u << 1)
243#define US_IMR_RXBRK (0x1u << 2)
244#define US_IMR_OVRE (0x1u << 5)
245#define US_IMR_FRAME (0x1u << 6)
246#define US_IMR_PARE (0x1u << 7)
247#define US_IMR_TIMEOUT (0x1u << 8)
248#define US_IMR_TXEMPTY (0x1u << 9)
249#define US_IMR_ITER (0x1u << 10)
250#define US_IMR_NACK (0x1u << 13)
251#define US_IMR_RIIC (0x1u << 16)
252#define US_IMR_DSRIC (0x1u << 17)
253#define US_IMR_DCDIC (0x1u << 18)
254#define US_IMR_CTSIC (0x1u << 19)
255#define US_IMR_MANE (0x1u << 24)
256#define US_IMR_UNRE (0x1u << 10)
257#define US_IMR_NSSE (0x1u << 19)
258#define US_IMR_LINBK (0x1u << 13)
259#define US_IMR_LINID (0x1u << 14)
260#define US_IMR_LINTC (0x1u << 15)
261#define US_IMR_LINBE (0x1u << 25)
262#define US_IMR_LINISFE (0x1u << 26)
263#define US_IMR_LINIPE (0x1u << 27)
264#define US_IMR_LINCE (0x1u << 28)
265#define US_IMR_LINSNRE (0x1u << 29)
266#define US_IMR_LINSTE (0x1u << 30)
267#define US_IMR_LINHTE (0x1u << 31)
268#define US_IMR_LSFE (0x1u << 6)
269#define US_IMR_LCRCE (0x1u << 7)
270#define US_IMR_LTXD (0x1u << 24)
271#define US_IMR_LCOL (0x1u << 25)
272#define US_IMR_LFET (0x1u << 26)
273#define US_IMR_LRXD (0x1u << 27)
274#define US_IMR_LBLOVFE (0x1u << 28)
275/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
276#define US_CSR_RXRDY (0x1u << 0)
277#define US_CSR_TXRDY (0x1u << 1)
278#define US_CSR_RXBRK (0x1u << 2)
279#define US_CSR_OVRE (0x1u << 5)
280#define US_CSR_FRAME (0x1u << 6)
281#define US_CSR_PARE (0x1u << 7)
282#define US_CSR_TIMEOUT (0x1u << 8)
283#define US_CSR_TXEMPTY (0x1u << 9)
284#define US_CSR_ITER (0x1u << 10)
285#define US_CSR_NACK (0x1u << 13)
286#define US_CSR_RIIC (0x1u << 16)
287#define US_CSR_DSRIC (0x1u << 17)
288#define US_CSR_DCDIC (0x1u << 18)
289#define US_CSR_CTSIC (0x1u << 19)
290#define US_CSR_RI (0x1u << 20)
291#define US_CSR_DSR (0x1u << 21)
292#define US_CSR_DCD (0x1u << 22)
293#define US_CSR_CTS (0x1u << 23)
294#define US_CSR_MANERR (0x1u << 24)
295#define US_CSR_UNRE (0x1u << 10)
296#define US_CSR_NSSE (0x1u << 19)
297#define US_CSR_NSS (0x1u << 23)
298#define US_CSR_LINBK (0x1u << 13)
299#define US_CSR_LINID (0x1u << 14)
300#define US_CSR_LINTC (0x1u << 15)
301#define US_CSR_LINBLS (0x1u << 23)
302#define US_CSR_LINBE (0x1u << 25)
303#define US_CSR_LINISFE (0x1u << 26)
304#define US_CSR_LINIPE (0x1u << 27)
305#define US_CSR_LINCE (0x1u << 28)
306#define US_CSR_LINSNRE (0x1u << 29)
307#define US_CSR_LINSTE (0x1u << 30)
308#define US_CSR_LINHTE (0x1u << 31)
309#define US_CSR_LSFE (0x1u << 6)
310#define US_CSR_LCRCE (0x1u << 7)
311#define US_CSR_LTXD (0x1u << 24)
312#define US_CSR_LCOL (0x1u << 25)
313#define US_CSR_LFET (0x1u << 26)
314#define US_CSR_LRXD (0x1u << 27)
315#define US_CSR_LBLOVFE (0x1u << 28)
316/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */
317#define US_RHR_RXCHR_Pos 0
318#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos)
319#define US_RHR_RXSYNH (0x1u << 15)
320/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */
321#define US_THR_TXCHR_Pos 0
322#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos)
323#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
324#define US_THR_TXSYNH (0x1u << 15)
325/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
326#define US_BRGR_CD_Pos 0
327#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos)
328#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
329#define US_BRGR_FP_Pos 16
330#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos)
331#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
332/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
333#define US_RTOR_TO_Pos 0
334#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos)
335#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
336/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
337#define US_TTGR_TG_Pos 0
338#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos)
339#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
340#define US_TTGR_PCYCLE_Pos 0
341#define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos)
342#define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos)))
343/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
344#define US_FIDI_FI_DI_RATIO_Pos 0
345#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos)
346#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
347#define US_FIDI_BETA2_Pos 0
348#define US_FIDI_BETA2_Msk (0xffffffu << US_FIDI_BETA2_Pos)
349#define US_FIDI_BETA2(value) ((US_FIDI_BETA2_Msk & ((value) << US_FIDI_BETA2_Pos)))
350/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
351#define US_NER_NB_ERRORS_Pos 0
352#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos)
353/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
354#define US_IF_IRDA_FILTER_Pos 0
355#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos)
356#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
357/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */
358#define US_MAN_TX_PL_Pos 0
359#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos)
360#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
361#define US_MAN_TX_PP_Pos 8
362#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos)
363#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos)))
364#define US_MAN_TX_PP_ALL_ONE (0x0u << 8)
365#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8)
366#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8)
367#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8)
368#define US_MAN_TX_MPOL (0x1u << 12)
369#define US_MAN_RX_PL_Pos 16
370#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos)
371#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
372#define US_MAN_RX_PP_Pos 24
373#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos)
374#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos)))
375#define US_MAN_RX_PP_ALL_ONE (0x0u << 24)
376#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24)
377#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24)
378#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24)
379#define US_MAN_RX_MPOL (0x1u << 28)
380#define US_MAN_ONE (0x1u << 29)
381#define US_MAN_DRIFT (0x1u << 30)
382#define US_MAN_RXIDLEV (0x1u << 31)
383/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */
384#define US_LINMR_NACT_Pos 0
385#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos)
386#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos)))
387#define US_LINMR_NACT_PUBLISH (0x0u << 0)
388#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0)
389#define US_LINMR_NACT_IGNORE (0x2u << 0)
390#define US_LINMR_PARDIS (0x1u << 2)
391#define US_LINMR_CHKDIS (0x1u << 3)
392#define US_LINMR_CHKTYP (0x1u << 4)
393#define US_LINMR_DLM (0x1u << 5)
394#define US_LINMR_FSDIS (0x1u << 6)
395#define US_LINMR_WKUPTYP (0x1u << 7)
396#define US_LINMR_DLC_Pos 8
397#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos)
398#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))
399#define US_LINMR_PDCM (0x1u << 16)
400#define US_LINMR_SYNCDIS (0x1u << 17)
401/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */
402#define US_LINIR_IDCHR_Pos 0
403#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos)
404#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))
405/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */
406#define US_LINBRR_LINCD_Pos 0
407#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos)
408#define US_LINBRR_LINFP_Pos 16
409#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos)
410/* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */
411#define US_LONMR_COMMT (0x1u << 0)
412#define US_LONMR_COLDET (0x1u << 1)
413#define US_LONMR_TCOL (0x1u << 2)
414#define US_LONMR_CDTAIL (0x1u << 3)
415#define US_LONMR_DMAM (0x1u << 4)
416#define US_LONMR_LCDS (0x1u << 5)
417#define US_LONMR_EOFS_Pos 16
418#define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos)
419#define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos)))
420/* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */
421#define US_LONPR_LONPL_Pos 0
422#define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos)
423#define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos)))
424/* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */
425#define US_LONDL_LONDL_Pos 0
426#define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos)
427#define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos)))
428/* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */
429#define US_LONL2HDR_BLI_Pos 0
430#define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos)
431#define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos)))
432#define US_LONL2HDR_ALTP (0x1u << 6)
433#define US_LONL2HDR_PB (0x1u << 7)
434/* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */
435#define US_LONBL_LONBL_Pos 0
436#define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos)
437/* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */
438#define US_LONB1TX_BETA1TX_Pos 0
439#define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos)
440#define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos)))
441/* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */
442#define US_LONB1RX_BETA1RX_Pos 0
443#define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos)
444#define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos)))
445/* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */
446#define US_LONPRIO_PSNB_Pos 0
447#define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos)
448#define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos)))
449#define US_LONPRIO_NPS_Pos 8
450#define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos)
451#define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos)))
452/* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */
453#define US_IDTTX_IDTTX_Pos 0
454#define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos)
455#define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos)))
456/* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */
457#define US_IDTRX_IDTRX_Pos 0
458#define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos)
459#define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos)))
460/* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */
461#define US_ICDIFF_ICDIFF_Pos 0
462#define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos)
463#define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos)))
464/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */
465#define US_WPMR_WPEN (0x1u << 0)
466#define US_WPMR_WPKEY_Pos 8
467#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos)
468#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
469#define US_WPMR_WPKEY_PASSWD (0x555341u << 8)
470/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */
471#define US_WPSR_WPVS (0x1u << 0)
472#define US_WPSR_WPVSRC_Pos 8
473#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos)
476
477
478#endif /* _SAMS70_USART_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Usart
Usart hardware registers.
Definition: component_usart.h:41