RTEMS: bsps/powerpc/beatnik/net/porting/pcireg.h Source File

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pcireg.h
1/*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/pci/pcireg.h,v 1.39.4.3 2005/04/02 05:03:34 jmg Exp $
27 *
28 */
29
30/*
31 * PCIM_xxx: mask to locate subfield in register
32 * PCIR_xxx: config register offset
33 * PCIC_xxx: device class
34 * PCIS_xxx: device subclass
35 * PCIP_xxx: device programming interface
36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
37 * PCID_xxx: device ID
38 * PCIY_xxx: capability identification number
39 */
40
41/* some PCI bus constants */
42
43#define PCI_BUSMAX 255
44#define PCI_SLOTMAX 31
45#define PCI_FUNCMAX 7
46#define PCI_REGMAX 255
47#define PCI_MAXHDRTYPE 2
48
49/* PCI config header registers for all devices */
50
51#define PCIR_DEVVENDOR 0x00
52#define PCIR_VENDOR 0x00
53#define PCIR_DEVICE 0x02
54#define PCIR_COMMAND 0x04
55#define PCIM_CMD_PORTEN 0x0001
56#define PCIM_CMD_MEMEN 0x0002
57#define PCIM_CMD_BUSMASTEREN 0x0004
58#define PCIM_CMD_SPECIALEN 0x0008
59#define PCIM_CMD_MWRICEN 0x0010
60#define PCIM_CMD_PERRESPEN 0x0040
61#define PCIM_CMD_SERRESPEN 0x0100
62#define PCIM_CMD_BACKTOBACK 0x0200
63#define PCIR_STATUS 0x06
64#define PCIM_STATUS_CAPPRESENT 0x0010
65#define PCIM_STATUS_66CAPABLE 0x0020
66#define PCIM_STATUS_BACKTOBACK 0x0080
67#define PCIM_STATUS_PERRREPORT 0x0100
68#define PCIM_STATUS_SEL_FAST 0x0000
69#define PCIM_STATUS_SEL_MEDIMUM 0x0200
70#define PCIM_STATUS_SEL_SLOW 0x0400
71#define PCIM_STATUS_SEL_MASK 0x0600
72#define PCIM_STATUS_STABORT 0x0800
73#define PCIM_STATUS_RTABORT 0x1000
74#define PCIM_STATUS_RMABORT 0x2000
75#define PCIM_STATUS_SERR 0x4000
76#define PCIM_STATUS_PERR 0x8000
77#define PCIR_REVID 0x08
78#define PCIR_PROGIF 0x09
79#define PCIR_SUBCLASS 0x0a
80#define PCIR_CLASS 0x0b
81#define PCIR_CACHELNSZ 0x0c
82#define PCIR_LATTIMER 0x0d
83#define PCIR_HDRTYPE 0x0e
84#ifndef BURN_BRIDGES
85#define PCIR_HEADERTYPE PCIR_HDRTYPE
86#endif
87#define PCIM_HDRTYPE 0x7f
88#define PCIM_HDRTYPE_NORMAL 0x00
89#define PCIM_HDRTYPE_BRIDGE 0x01
90#define PCIM_HDRTYPE_CARDBUS 0x02
91#define PCIM_MFDEV 0x80
92#define PCIR_BIST 0x0f
93
94/* Capability Identification Numbers */
95
96#define PCIY_PMG 0x01 /* PCI Power Management */
97#define PCIY_AGP 0x02 /* AGP */
98#define PCIY_VPD 0x03 /* Vital Product Data */
99#define PCIY_SLOTID 0x04 /* Slot Identification */
100#define PCIY_MSI 0x05 /* Message Signaled Interrupts */
101#define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */
102#define PCIY_PCIX 0x07 /* PCI-X */
103#define PCIY_HT 0x08 /* HyperTransport */
104#define PCIY_VENDOR 0x09 /* Vendor Unique */
105#define PCIY_DEBUG 0x0a /* Debug port */
106#define PCIY_CRES 0x0b /* CompactPCI central resource control */
107#define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */
108#define PCIY_AGP8X 0x0e /* AGP 8x */
109#define PCIY_SECDEV 0x0f /* Secure Device */
110#define PCIY_EXPRESS 0x10 /* PCI Express */
111#define PCIY_MSIX 0x11 /* MSI-X */
112
113/* config registers for header type 0 devices */
114
115#define PCIR_BARS 0x10
116#define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
117#ifndef BURN_BRIDGES
118#define PCIR_MAPS PCIR_BARS
119#endif
120#define PCIR_CARDBUSCIS 0x28
121#define PCIR_SUBVEND_0 0x2c
122#define PCIR_SUBDEV_0 0x2e
123#define PCIR_BIOS 0x30
124#define PCIM_BIOS_ENABLE 0x01
125#define PCIR_CAP_PTR 0x34
126#define PCIR_INTLINE 0x3c
127#define PCIR_INTPIN 0x3d
128#define PCIR_MINGNT 0x3e
129#define PCIR_MAXLAT 0x3f
130
131/* config registers for header type 1 (PCI-to-PCI bridge) devices */
132
133#define PCIR_SECSTAT_1 0x1e
134
135#define PCIR_PRIBUS_1 0x18
136#define PCIR_SECBUS_1 0x19
137#define PCIR_SUBBUS_1 0x1a
138#define PCIR_SECLAT_1 0x1b
139
140#define PCIR_IOBASEL_1 0x1c
141#define PCIR_IOLIMITL_1 0x1d
142#define PCIR_IOBASEH_1 0x30
143#define PCIR_IOLIMITH_1 0x32
144#define PCIM_BRIO_16 0x0
145#define PCIM_BRIO_32 0x1
146#define PCIM_BRIO_MASK 0xf
147
148#define PCIR_MEMBASE_1 0x20
149#define PCIR_MEMLIMIT_1 0x22
150
151#define PCIR_PMBASEL_1 0x24
152#define PCIR_PMLIMITL_1 0x26
153#define PCIR_PMBASEH_1 0x28
154#define PCIR_PMLIMITH_1 0x2c
155
156#define PCIR_BRIDGECTL_1 0x3e
157
158#define PCIR_SUBVEND_1 0x34
159#define PCIR_SUBDEV_1 0x36
160
161/* config registers for header type 2 (CardBus) devices */
162
163#define PCIR_SECSTAT_2 0x16
164
165#define PCIR_PRIBUS_2 0x18
166#define PCIR_SECBUS_2 0x19
167#define PCIR_SUBBUS_2 0x1a
168#define PCIR_SECLAT_2 0x1b
169
170#define PCIR_MEMBASE0_2 0x1c
171#define PCIR_MEMLIMIT0_2 0x20
172#define PCIR_MEMBASE1_2 0x24
173#define PCIR_MEMLIMIT1_2 0x28
174#define PCIR_IOBASE0_2 0x2c
175#define PCIR_IOLIMIT0_2 0x30
176#define PCIR_IOBASE1_2 0x34
177#define PCIR_IOLIMIT1_2 0x38
178
179#define PCIR_BRIDGECTL_2 0x3e
180
181#define PCIR_SUBVEND_2 0x40
182#define PCIR_SUBDEV_2 0x42
183
184#define PCIR_PCCARDIF_2 0x44
185
186/* PCI device class, subclass and programming interface definitions */
187
188#define PCIC_OLD 0x00
189#define PCIS_OLD_NONVGA 0x00
190#define PCIS_OLD_VGA 0x01
191
192#define PCIC_STORAGE 0x01
193#define PCIS_STORAGE_SCSI 0x00
194#define PCIS_STORAGE_IDE 0x01
195#define PCIP_STORAGE_IDE_MODEPRIM 0x01
196#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02
197#define PCIP_STORAGE_IDE_MODESEC 0x04
198#define PCIP_STORAGE_IDE_PROGINDSEC 0x08
199#define PCIP_STORAGE_IDE_MASTERDEV 0x80
200#define PCIS_STORAGE_FLOPPY 0x02
201#define PCIS_STORAGE_IPI 0x03
202#define PCIS_STORAGE_RAID 0x04
203#define PCIS_STORAGE_OTHER 0x80
204
205#define PCIC_NETWORK 0x02
206#define PCIS_NETWORK_ETHERNET 0x00
207#define PCIS_NETWORK_TOKENRING 0x01
208#define PCIS_NETWORK_FDDI 0x02
209#define PCIS_NETWORK_ATM 0x03
210#define PCIS_NETWORK_ISDN 0x04
211#define PCIS_NETWORK_OTHER 0x80
212
213#define PCIC_DISPLAY 0x03
214#define PCIS_DISPLAY_VGA 0x00
215#define PCIS_DISPLAY_XGA 0x01
216#define PCIS_DISPLAY_3D 0x02
217#define PCIS_DISPLAY_OTHER 0x80
218
219#define PCIC_MULTIMEDIA 0x04
220#define PCIS_MULTIMEDIA_VIDEO 0x00
221#define PCIS_MULTIMEDIA_AUDIO 0x01
222#define PCIS_MULTIMEDIA_TELE 0x02
223#define PCIS_MULTIMEDIA_OTHER 0x80
224
225#define PCIC_MEMORY 0x05
226#define PCIS_MEMORY_RAM 0x00
227#define PCIS_MEMORY_FLASH 0x01
228#define PCIS_MEMORY_OTHER 0x80
229
230#define PCIC_BRIDGE 0x06
231#define PCIS_BRIDGE_HOST 0x00
232#define PCIS_BRIDGE_ISA 0x01
233#define PCIS_BRIDGE_EISA 0x02
234#define PCIS_BRIDGE_MCA 0x03
235#define PCIS_BRIDGE_PCI 0x04
236#define PCIS_BRIDGE_PCMCIA 0x05
237#define PCIS_BRIDGE_NUBUS 0x06
238#define PCIS_BRIDGE_CARDBUS 0x07
239#define PCIS_BRIDGE_RACEWAY 0x08
240#define PCIS_BRIDGE_OTHER 0x80
241
242#define PCIC_SIMPLECOMM 0x07
243#define PCIS_SIMPLECOMM_UART 0x00
244#define PCIP_SIMPLECOMM_UART_16550A 0x02
245#define PCIS_SIMPLECOMM_PAR 0x01
246#define PCIS_SIMPLECOMM_MULSER 0x02
247#define PCIS_SIMPLECOMM_MODEM 0x03
248#define PCIS_SIMPLECOMM_OTHER 0x80
249
250#define PCIC_BASEPERIPH 0x08
251#define PCIS_BASEPERIPH_PIC 0x00
252#define PCIS_BASEPERIPH_DMA 0x01
253#define PCIS_BASEPERIPH_TIMER 0x02
254#define PCIS_BASEPERIPH_RTC 0x03
255#define PCIS_BASEPERIPH_PCIHOT 0x04
256#define PCIS_BASEPERIPH_OTHER 0x80
257
258#define PCIC_INPUTDEV 0x09
259#define PCIS_INPUTDEV_KEYBOARD 0x00
260#define PCIS_INPUTDEV_DIGITIZER 0x01
261#define PCIS_INPUTDEV_MOUSE 0x02
262#define PCIS_INPUTDEV_SCANNER 0x03
263#define PCIS_INPUTDEV_GAMEPORT 0x04
264#define PCIS_INPUTDEV_OTHER 0x80
265
266#define PCIC_DOCKING 0x0a
267#define PCIS_DOCKING_GENERIC 0x00
268#define PCIS_DOCKING_OTHER 0x80
269
270#define PCIC_PROCESSOR 0x0b
271#define PCIS_PROCESSOR_386 0x00
272#define PCIS_PROCESSOR_486 0x01
273#define PCIS_PROCESSOR_PENTIUM 0x02
274#define PCIS_PROCESSOR_ALPHA 0x10
275#define PCIS_PROCESSOR_POWERPC 0x20
276#define PCIS_PROCESSOR_MIPS 0x30
277#define PCIS_PROCESSOR_COPROC 0x40
278
279#define PCIC_SERIALBUS 0x0c
280#define PCIS_SERIALBUS_FW 0x00
281#define PCIS_SERIALBUS_ACCESS 0x01
282#define PCIS_SERIALBUS_SSA 0x02
283#define PCIS_SERIALBUS_USB 0x03
284#define PCIP_SERIALBUS_USB_UHCI 0x00
285#define PCIP_SERIALBUS_USB_OHCI 0x10
286#define PCIP_SERIALBUS_USB_EHCI 0x20
287#define PCIS_SERIALBUS_FC 0x04
288#define PCIS_SERIALBUS_SMBUS 0x05
289
290#define PCIC_WIRELESS 0x0d
291#define PCIS_WIRELESS_IRDA 0x00
292#define PCIS_WIRELESS_IR 0x01
293#define PCIS_WIRELESS_RF 0x10
294#define PCIS_WIRELESS_OTHER 0x80
295
296#define PCIC_INTELLIIO 0x0e
297#define PCIS_INTELLIIO_I2O 0x00
298
299#define PCIC_SATCOM 0x0f
300#define PCIS_SATCOM_TV 0x01
301#define PCIS_SATCOM_AUDIO 0x02
302#define PCIS_SATCOM_VOICE 0x03
303#define PCIS_SATCOM_DATA 0x04
304
305#define PCIC_CRYPTO 0x10
306#define PCIS_CRYPTO_NETCOMP 0x00
307#define PCIS_CRYPTO_ENTERTAIN 0x10
308#define PCIS_CRYPTO_OTHER 0x80
309
310#define PCIC_DASP 0x11
311#define PCIS_DASP_DPIO 0x00
312#define PCIS_DASP_OTHER 0x80
313
314#define PCIC_OTHER 0xff
315
316/* PCI power manangement */
317
318#define PCIR_POWER_CAP 0x2
319#define PCIM_PCAP_SPEC 0x0007
320#define PCIM_PCAP_PMEREQCLK 0x0008
321#define PCIM_PCAP_PMEREQPWR 0x0010
322#define PCIM_PCAP_DEVSPECINIT 0x0020
323#define PCIM_PCAP_DYNCLOCK 0x0040
324#define PCIM_PCAP_SECCLOCK 0x00c0
325#define PCIM_PCAP_CLOCKMASK 0x00c0
326#define PCIM_PCAP_REQFULLCLOCK 0x0100
327#define PCIM_PCAP_D1SUPP 0x0200
328#define PCIM_PCAP_D2SUPP 0x0400
329#define PCIM_PCAP_D0PME 0x1000
330#define PCIM_PCAP_D1PME 0x2000
331#define PCIM_PCAP_D2PME 0x4000
332
333#define PCIR_POWER_STATUS 0x4
334#define PCIM_PSTAT_D0 0x0000
335#define PCIM_PSTAT_D1 0x0001
336#define PCIM_PSTAT_D2 0x0002
337#define PCIM_PSTAT_D3 0x0003
338#define PCIM_PSTAT_DMASK 0x0003
339#define PCIM_PSTAT_REPENABLE 0x0010
340#define PCIM_PSTAT_PMEENABLE 0x0100
341#define PCIM_PSTAT_D0POWER 0x0000
342#define PCIM_PSTAT_D1POWER 0x0200
343#define PCIM_PSTAT_D2POWER 0x0400
344#define PCIM_PSTAT_D3POWER 0x0600
345#define PCIM_PSTAT_D0HEAT 0x0800
346#define PCIM_PSTAT_D1HEAT 0x1000
347#define PCIM_PSTAT_D2HEAT 0x1200
348#define PCIM_PSTAT_D3HEAT 0x1400
349#define PCIM_PSTAT_DATAUNKN 0x0000
350#define PCIM_PSTAT_DATADIV10 0x2000
351#define PCIM_PSTAT_DATADIV100 0x4000
352#define PCIM_PSTAT_DATADIV1000 0x6000
353#define PCIM_PSTAT_DATADIVMASK 0x6000
354#define PCIM_PSTAT_PME 0x8000
355
356#define PCIR_POWER_PMCSR 0x6
357#define PCIM_PMCSR_DCLOCK 0x10
358#define PCIM_PMCSR_B2SUPP 0x20
359#define PCIM_BMCSR_B3SUPP 0x40
360#define PCIM_BMCSR_BPCE 0x80
361
362#define PCIR_POWER_DATA 0x7
363
364/* PCI Message Signalled Interrupts (MSI) */
365#define PCIR_MSI_CTRL 0x2
366#define PCIM_MSICTRL_VECTOR 0x0100
367#define PCIM_MSICTRL_64BIT 0x0080
368#define PCIM_MSICTRL_MME_MASK 0x0070
369#define PCIM_MSICTRL_MME_1 0x0000
370#define PCIM_MSICTRL_MME_2 0x0010
371#define PCIM_MSICTRL_MME_4 0x0020
372#define PCIM_MSICTRL_MME_8 0x0030
373#define PCIM_MSICTRL_MME_16 0x0040
374#define PCIM_MSICTRL_MME_32 0x0050
375#define PCIM_MSICTRL_MMC_MASK 0x000E
376#define PCIM_MSICTRL_MMC_1 0x0000
377#define PCIM_MSICTRL_MMC_2 0x0002
378#define PCIM_MSICTRL_MMC_4 0x0004
379#define PCIM_MSICTRL_MMC_8 0x0006
380#define PCIM_MSICTRL_MMC_16 0x0008
381#define PCIM_MSICTRL_MMC_32 0x000A
382#define PCIM_MSICTRL_MSI_ENABLE 0x0001
383#define PCIR_MSI_ADDR 0x4
384#define PCIR_MSI_ADDR_HIGH 0x8
385#define PCIR_MSI_DATA 0x8
386#define PCIR_MSI_DATA_64BIT 0xc
387#define PCIR_MSI_MASK 0x10
388#define PCIR_MSI_PENDING 0x14
389
390/* PCI-X definitions */
391#define PCIXR_COMMAND 0x96
392#define PCIXR_DEVADDR 0x98
393#define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */
394#define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */
395#define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */
396#define PCIXR_STATUS 0x9A
397#define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */
398#define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */
399#define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */
400#define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */
401#define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */
402#define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */
403#define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */
404#define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */
405#define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */