RTEMS: cpukit/score/cpu/nios2/include/rtems/score/cpu.h Source File

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cpu.h
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1
9/*
10 * Copyright (c) 2011 embedded brains GmbH
11 *
12 * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
13 *
14 * COPYRIGHT (c) 1989-2004.
15 * On-Line Applications Research Corporation (OAR).
16 *
17 * The license and distribution terms for this file may be
18 * found in the file LICENSE in this distribution or at
19 * http://www.rtems.org/license/LICENSE.
20 */
21
22#ifndef _RTEMS_SCORE_CPU_H
23#define _RTEMS_SCORE_CPU_H
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#include <rtems/score/basedefs.h>
30#include <rtems/score/nios2.h>
31
32#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
33
34#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
35
36#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
37
38#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
39
40#define CPU_ISR_PASSES_FRAME_POINTER FALSE
41
42#define CPU_HARDWARE_FP FALSE
43
44#define CPU_SOFTWARE_FP FALSE
45
46#define CPU_ALL_TASKS_ARE_FP FALSE
47
48#define CPU_IDLE_TASK_IS_FP FALSE
49
50#define CPU_USE_DEFERRED_FP_SWITCH FALSE
51
52#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
53
54#define CPU_STACK_GROWS_UP FALSE
55
56/* FIXME: Is this the right value? */
57#define CPU_CACHE_LINE_BYTES 32
58
59#define CPU_STRUCTURE_ALIGNMENT \
60 RTEMS_SECTION( ".sdata" ) RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
61
62#define CPU_STACK_MINIMUM_SIZE (4 * 1024)
63
64#define CPU_SIZEOF_POINTER 4
65
66/*
67 * Alignment value according to "Nios II Processor Reference" chapter 7
68 * "Application Binary Interface" section "Memory Alignment".
69 */
70#define CPU_ALIGNMENT 4
71
72#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
73
74/*
75 * Alignment value according to "Nios II Processor Reference" chapter 7
76 * "Application Binary Interface" section "Stacks".
77 */
78#define CPU_STACK_ALIGNMENT 4
79
80#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
81
82/*
83 * A Nios II configuration with an external interrupt controller (EIC) supports
84 * up to 64 interrupt levels. A Nios II configuration with an internal
85 * interrupt controller (IIC) has only two interrupt levels (enabled and
86 * disabled). The _CPU_ISR_Get_level() and _CPU_ISR_Set_level() functions will
87 * take care about configuration specific mappings.
88 */
89#define CPU_MODES_INTERRUPT_MASK 0x3f
90
91#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
92
93#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
94
95#define CPU_MAXIMUM_PROCESSORS 32
96
97#ifndef ASM
98
113typedef struct {
114 uint32_t r16;
115 uint32_t r17;
116 uint32_t r18;
117 uint32_t r19;
118 uint32_t r20;
119 uint32_t r21;
120 uint32_t r22;
121 uint32_t r23;
122 uint32_t fp;
123 uint32_t status;
124 uint32_t sp;
125 uint32_t ra;
126 uint32_t thread_dispatch_disabled;
127 uint32_t stack_mpubase;
128 uint32_t stack_mpuacc;
129} Context_Control;
130
131#define _CPU_Context_Get_SP( _context ) \
132 (_context)->sp
133
134typedef void CPU_Interrupt_frame;
135
136typedef struct {
137 uint32_t r1;
138 uint32_t r2;
139 uint32_t r3;
140 uint32_t r4;
141 uint32_t r5;
142 uint32_t r6;
143 uint32_t r7;
144 uint32_t r8;
145 uint32_t r9;
146 uint32_t r10;
147 uint32_t r11;
148 uint32_t r12;
149 uint32_t r13;
150 uint32_t r14;
151 uint32_t r15;
152 uint32_t r16;
153 uint32_t r17;
154 uint32_t r18;
155 uint32_t r19;
156 uint32_t r20;
157 uint32_t r21;
158 uint32_t r22;
159 uint32_t r23;
160 uint32_t gp;
161 uint32_t fp;
162 uint32_t sp;
163 uint32_t ra;
164 uint32_t et;
165 uint32_t ea;
166 uint32_t status;
167 uint32_t ienable;
168 uint32_t ipending;
169} CPU_Exception_frame;
170
171#define _CPU_Initialize_vectors()
172
193#define _CPU_ISR_Disable( _isr_cookie ) \
194 do { \
195 int _tmp; \
196 __asm__ volatile ( \
197 "rdctl %0, status\n" \
198 "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \
199 "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \
200 "and %1, %0, %1\n" \
201 "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \
202 "wrctl status, %1" \
203 : "=&r" (_isr_cookie), "=&r" (_tmp) \
204 ); \
205 } while ( 0 )
206
213#define _CPU_ISR_Enable( _isr_cookie ) \
214 __builtin_wrctl( 0, (int) _isr_cookie )
215
227#define _CPU_ISR_Flash( _isr_cookie ) \
228 do { \
229 int _status = __builtin_rdctl( 0 ); \
230 __builtin_wrctl( 0, (int) _isr_cookie ); \
231 __builtin_wrctl( 0, _status ); \
232 } while ( 0 )
233
234bool _CPU_ISR_Is_enabled( uint32_t level );
235
244void _CPU_ISR_Set_level( uint32_t new_level );
245
259uint32_t _CPU_ISR_Get_level( void );
260
278void _CPU_Context_Initialize(
279 Context_Control *context,
280 void *stack_area_begin,
281 size_t stack_area_size,
282 uint32_t new_level,
283 void (*entry_point)( void ),
284 bool is_fp,
285 void *tls_area
286);
287
288#define _CPU_Context_Restart_self( _the_context ) \
289 _CPU_Context_restore( (_the_context) );
290
291void _CPU_Fatal_halt( uint32_t _source, uint32_t _error )
292 RTEMS_NO_RETURN;
293
297void _CPU_Initialize( void );
298
299typedef void ( *CPU_ISR_handler )( uint32_t );
300
301void _CPU_ISR_install_vector(
302 uint32_t vector,
303 CPU_ISR_handler new_handler,
304 CPU_ISR_handler *old_handler
305);
306
307void *_CPU_Thread_Idle_body( uintptr_t ignored );
308
309void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
310
311void _CPU_Context_restore(
312 Context_Control *new_context
313) RTEMS_NO_RETURN;
314
315void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
316
317static inline uint32_t CPU_swap_u32( uint32_t value )
318{
319 uint32_t byte1, byte2, byte3, byte4, swapped;
320
321 byte4 = (value >> 24) & 0xff;
322 byte3 = (value >> 16) & 0xff;
323 byte2 = (value >> 8) & 0xff;
324 byte1 = value & 0xff;
325
326 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
327
328 return swapped;
329}
330
331#define CPU_swap_u16( value ) \
332 (((value&0xff) << 8) | ((value >> 8)&0xff))
333
334typedef uint32_t CPU_Counter_ticks;
335
336uint32_t _CPU_Counter_frequency( void );
337
338CPU_Counter_ticks _CPU_Counter_read( void );
339
340static inline CPU_Counter_ticks _CPU_Counter_difference(
341 CPU_Counter_ticks second,
342 CPU_Counter_ticks first
343)
344{
345 return second - first;
346}
347
349 typedef uintptr_t CPU_Uint32ptr;
350
351#endif /* ASM */
352
353#ifdef __cplusplus
354}
355#endif
356
357#endif
basedefs.h
Basic Definitions.
RTEMS_NO_RETURN
#define RTEMS_NO_RETURN
Definition: basedefs.h:102
_CPU_Thread_Idle_body
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
_CPU_Initialize
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
CPU_Uint32ptr
uintptr_t CPU_Uint32ptr
Definition: cpu.h:662
_CPU_ISR_install_vector
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
_CPU_Exception_frame_print
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
_CPU_Counter_frequency
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
_CPU_Context_switch
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
_CPU_Counter_read
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
_CPU_ISR_Set_level
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:400
ra
#define ra
return address *‍/
Definition: regs.h:66
sp
#define sp
stack-pointer *‍/
Definition: regs.h:64
fp
#define fp
frame-pointer *‍/
Definition: regs.h:65
gp
#define gp
global data pointer *‍/
Definition: regs.h:63
nios2.h
NIOS II Set up Basic CPU Dependency Settings Based on Compiler Settings.
CPU_Exception_frame
The set of registers that specifies the complete processor state.
Definition: cpu.h:629
CPU_Interrupt_frame
Interrupt stack frame (ISF).
Definition: cpu.h:191
Context_Control
Thread register context.
Definition: cpu.h:194