RTEMS: Cache Management API

| RTEMS 5.4-rc2

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Modules
Cache Management API
Board Support Packages » ARM » Intel Cyclone V » Contributed Code

## Modules
| L1 Cache Management API
| L2 Cache Management API
| System Level Cache Management API

## Detailed Description

This module defines the cache management API for enabling and disabling L1 data cache, L1 instruction cache, L1 dynamic branch prediction caches, L1 TLB cache, and L2 cache in the SoC. As well, many it allows users to perform cache maintenance operations on these caches. This includes the following operations:

- Invalidate: Marks the cache line as being invalid, freeing up the space to cache other data. All APIs which enable caches invalidates the memory before being enabling the cache.
- Clean: If the cache line is dirty, it synchronizes the cache line data with the upper level memory system and marks that line as clean. All APIs which disable caches cleans the memory before disabling the cache.
- Purge: A term used in this API as a short form for clean and invalidate. This operation cleans and invalidates a cache line in that order, as a single command to the cache controller.

The following reference materials were used in the design of this API:

- ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition
- Cortex™-A9 Technical Reference Manual
- Cortex™-A9 MPCore Technical Reference Manual
- CoreLink™ Level 2 Cache Controller L2C-310 Technical Reference Manual