RTEMS: bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h File Reference

| RTEMS 5.4-rc2

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Data Structures | Macros | Typedefs
alt_qspi.h File Reference
Board Support Packages » ARM » Intel Cyclone V » Contributed Code

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## Data Structures
struct | ALT_QSPI_CFG_s
struct | ALT_QSPI_DEVRD_s
struct | ALT_QSPI_DEVWR_s
struct | ALT_QSPI_DELAY_s
struct | ALT_QSPI_RDDATACAP_s
struct | ALT_QSPI_DEVSZ_s
struct | ALT_QSPI_SRAMPART_s
struct | ALT_QSPI_INDADDRTRIG_s
struct | ALT_QSPI_DMAPER_s
struct | ALT_QSPI_REMAPADDR_s
struct | ALT_QSPI_MODBIT_s
struct | ALT_QSPI_SRAMFILL_s
struct | ALT_QSPI_TXTHRESH_s
struct | ALT_QSPI_RXTHRESH_s
struct | ALT_QSPI_IRQSTAT_s
struct | ALT_QSPI_IRQMSK_s
struct | ALT_QSPI_LOWWRPROT_s
struct | ALT_QSPI_UPPWRPROT_s
struct | ALT_QSPI_WRPROT_s
struct | ALT_QSPI_INDRD_s
struct | ALT_QSPI_INDRDWATER_s
struct | ALT_QSPI_INDRDSTADDR_s
struct | ALT_QSPI_INDRDCNT_s
struct | ALT_QSPI_INDWR_s
struct | ALT_QSPI_INDWRWATER_s
struct | ALT_QSPI_INDWRSTADDR_s
struct | ALT_QSPI_INDWRCNT_s
struct | ALT_QSPI_FLSHCMD_s
struct | ALT_QSPI_FLSHCMDADDR_s
struct | ALT_QSPI_FLSHCMDRDDATALO_s
struct | ALT_QSPI_FLSHCMDRDDATAUP_s
struct | ALT_QSPI_FLSHCMDWRDATALO_s
struct | ALT_QSPI_FLSHCMDWRDATAUP_s
struct | ALT_QSPI_MODULEID_s
struct | ALT_QSPI_s
struct | ALT_QSPI_raw_s

## Macros
#define | ALT_QSPI_CFG_EN_E_DIS 0x0
#define | ALT_QSPI_CFG_EN_E_EN 0x1
#define | ALT_QSPI_CFG_EN_LSB 0
#define | ALT_QSPI_CFG_EN_MSB 0
#define | ALT_QSPI_CFG_EN_WIDTH 1
#define | ALT_QSPI_CFG_EN_SET_MSK 0x00000001
#define | ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe
#define | ALT_QSPI_CFG_EN_RESET 0x0
#define | ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1
#define | ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0
#define | ALT_QSPI_CFG_SELCLKPOL_LSB 1
#define | ALT_QSPI_CFG_SELCLKPOL_MSB 1
#define | ALT_QSPI_CFG_SELCLKPOL_WIDTH 1
#define | ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002
#define | ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd
#define | ALT_QSPI_CFG_SELCLKPOL_RESET 0x0
#define | ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0
#define | ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1
#define | ALT_QSPI_CFG_SELCLKPHASE_LSB 2
#define | ALT_QSPI_CFG_SELCLKPHASE_MSB 2
#define | ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1
#define | ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004
#define | ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb
#define | ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0
#define | ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0
#define | ALT_QSPI_CFG_ENDIRACC_E_EN 0x1
#define | ALT_QSPI_CFG_ENDIRACC_LSB 7
#define | ALT_QSPI_CFG_ENDIRACC_MSB 7
#define | ALT_QSPI_CFG_ENDIRACC_WIDTH 1
#define | ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080
#define | ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f
#define | ALT_QSPI_CFG_ENDIRACC_RESET 0x0
#define | ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7)
#define | ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080)
#define | ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1
#define | ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0
#define | ALT_QSPI_CFG_ENLEGACYIP_LSB 8
#define | ALT_QSPI_CFG_ENLEGACYIP_MSB 8
#define | ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1
#define | ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100
#define | ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff
#define | ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0
#define | ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8)
#define | ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100)
#define | ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1
#define | ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0
#define | ALT_QSPI_CFG_PERSELDEC_LSB 9
#define | ALT_QSPI_CFG_PERSELDEC_MSB 9
#define | ALT_QSPI_CFG_PERSELDEC_WIDTH 1
#define | ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200
#define | ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff
#define | ALT_QSPI_CFG_PERSELDEC_RESET 0x0
#define | ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9)
#define | ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200)
#define | ALT_QSPI_CFG_PERCSLINES_LSB 10
#define | ALT_QSPI_CFG_PERCSLINES_MSB 13
#define | ALT_QSPI_CFG_PERCSLINES_WIDTH 4
#define | ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00
#define | ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff
#define | ALT_QSPI_CFG_PERCSLINES_RESET 0x0
#define | ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10)
#define | ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00)
#define | ALT_QSPI_CFG_WP_E_WRPROTON 0x1
#define | ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0
#define | ALT_QSPI_CFG_WP_LSB 14
#define | ALT_QSPI_CFG_WP_MSB 14
#define | ALT_QSPI_CFG_WP_WIDTH 1
#define | ALT_QSPI_CFG_WP_SET_MSK 0x00004000
#define | ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff
#define | ALT_QSPI_CFG_WP_RESET 0x0
#define | ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14)
#define | ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000)
#define | ALT_QSPI_CFG_ENDMA_E_EN 0x1
#define | ALT_QSPI_CFG_ENDMA_E_DIS 0x0
#define | ALT_QSPI_CFG_ENDMA_LSB 15
#define | ALT_QSPI_CFG_ENDMA_MSB 15
#define | ALT_QSPI_CFG_ENDMA_WIDTH 1
#define | ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000
#define | ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff
#define | ALT_QSPI_CFG_ENDMA_RESET 0x0
#define | ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15)
#define | ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000)
#define | ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1
#define | ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0
#define | ALT_QSPI_CFG_ENAHBREMAP_LSB 16
#define | ALT_QSPI_CFG_ENAHBREMAP_MSB 16
#define | ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1
#define | ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000
#define | ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff
#define | ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0
#define | ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16)
#define | ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000)
#define | ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1
#define | ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0
#define | ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17
#define | ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17
#define | ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1
#define | ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000
#define | ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff
#define | ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0
#define | ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17)
#define | ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000)
#define | ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1
#define | ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0
#define | ALT_QSPI_CFG_ENTERXIPIMM_LSB 18
#define | ALT_QSPI_CFG_ENTERXIPIMM_MSB 18
#define | ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1
#define | ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000
#define | ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff
#define | ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0
#define | ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18)
#define | ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000)
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe
#define | ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf
#define | ALT_QSPI_CFG_BAUDDIV_LSB 19
#define | ALT_QSPI_CFG_BAUDDIV_MSB 22
#define | ALT_QSPI_CFG_BAUDDIV_WIDTH 4
#define | ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000
#define | ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff
#define | ALT_QSPI_CFG_BAUDDIV_RESET 0xf
#define | ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19)
#define | ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000)
#define | ALT_QSPI_CFG_IDLE_E_SET 0x1
#define | ALT_QSPI_CFG_IDLE_E_NOTSET 0x0
#define | ALT_QSPI_CFG_IDLE_LSB 31
#define | ALT_QSPI_CFG_IDLE_MSB 31
#define | ALT_QSPI_CFG_IDLE_WIDTH 1
#define | ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000
#define | ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff
#define | ALT_QSPI_CFG_IDLE_RESET 0x0
#define | ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31)
#define | ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000)
#define | ALT_QSPI_CFG_OFST 0x0
#define | ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3
#define | ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb
#define | ALT_QSPI_DEVRD_RDOPCODE_LSB 0
#define | ALT_QSPI_DEVRD_RDOPCODE_MSB 7
#define | ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8
#define | ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff
#define | ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00
#define | ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3
#define | ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0)
#define | ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff)
#define | ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0
#define | ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1
#define | ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2
#define | ALT_QSPI_DEVRD_INSTWIDTH_LSB 8
#define | ALT_QSPI_DEVRD_INSTWIDTH_MSB 9
#define | ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2
#define | ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300
#define | ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff
#define | ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0
#define | ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8)
#define | ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300)
#define | ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0
#define | ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1
#define | ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2
#define | ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12
#define | ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13
#define | ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2
#define | ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000
#define | ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff
#define | ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0
#define | ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
#define | ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
#define | ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0
#define | ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1
#define | ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2
#define | ALT_QSPI_DEVRD_DATAWIDTH_LSB 16
#define | ALT_QSPI_DEVRD_DATAWIDTH_MSB 17
#define | ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2
#define | ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000
#define | ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff
#define | ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0
#define | ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
#define | ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
#define | ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0
#define | ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1
#define | ALT_QSPI_DEVRD_ENMODBITS_LSB 20
#define | ALT_QSPI_DEVRD_ENMODBITS_MSB 20
#define | ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1
#define | ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000
#define | ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff
#define | ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0
#define | ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20)
#define | ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000)
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24)
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000)
#define | ALT_QSPI_DEVRD_OFST 0x4
#define | ALT_QSPI_DEVWR_WROPCODE_LSB 0
#define | ALT_QSPI_DEVWR_WROPCODE_MSB 7
#define | ALT_QSPI_DEVWR_WROPCODE_WIDTH 8
#define | ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff
#define | ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00
#define | ALT_QSPI_DEVWR_WROPCODE_RESET 0x2
#define | ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0)
#define | ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff)
#define | ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0
#define | ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1
#define | ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2
#define | ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12
#define | ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13
#define | ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2
#define | ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000
#define | ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff
#define | ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0
#define | ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
#define | ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
#define | ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0
#define | ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1
#define | ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2
#define | ALT_QSPI_DEVWR_DATAWIDTH_LSB 16
#define | ALT_QSPI_DEVWR_DATAWIDTH_MSB 17
#define | ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2
#define | ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000
#define | ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff
#define | ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0
#define | ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
#define | ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24)
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000)
#define | ALT_QSPI_DEVWR_OFST 0x8
#define | ALT_QSPI_DELAY_INIT_LSB 0
#define | ALT_QSPI_DELAY_INIT_MSB 7
#define | ALT_QSPI_DELAY_INIT_WIDTH 8
#define | ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff
#define | ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00
#define | ALT_QSPI_DELAY_INIT_RESET 0x0
#define | ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0)
#define | ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff)
#define | ALT_QSPI_DELAY_AFTER_LSB 8
#define | ALT_QSPI_DELAY_AFTER_MSB 15
#define | ALT_QSPI_DELAY_AFTER_WIDTH 8
#define | ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00
#define | ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff
#define | ALT_QSPI_DELAY_AFTER_RESET 0x0
#define | ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8)
#define | ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00)
#define | ALT_QSPI_DELAY_BTWN_LSB 16
#define | ALT_QSPI_DELAY_BTWN_MSB 23
#define | ALT_QSPI_DELAY_BTWN_WIDTH 8
#define | ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000
#define | ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff
#define | ALT_QSPI_DELAY_BTWN_RESET 0x0
#define | ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16)
#define | ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000)
#define | ALT_QSPI_DELAY_NSS_LSB 24
#define | ALT_QSPI_DELAY_NSS_MSB 31
#define | ALT_QSPI_DELAY_NSS_WIDTH 8
#define | ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000
#define | ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff
#define | ALT_QSPI_DELAY_NSS_RESET 0x0
#define | ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24)
#define | ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000)
#define | ALT_QSPI_DELAY_OFST 0xc
#define | ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x0
#define | ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x1
#define | ALT_QSPI_RDDATACAP_BYP_LSB 0
#define | ALT_QSPI_RDDATACAP_BYP_MSB 0
#define | ALT_QSPI_RDDATACAP_BYP_WIDTH 1
#define | ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001
#define | ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe
#define | ALT_QSPI_RDDATACAP_BYP_RESET 0x1
#define | ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_QSPI_RDDATACAP_DELAY_LSB 1
#define | ALT_QSPI_RDDATACAP_DELAY_MSB 4
#define | ALT_QSPI_RDDATACAP_DELAY_WIDTH 4
#define | ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e
#define | ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1
#define | ALT_QSPI_RDDATACAP_DELAY_RESET 0x0
#define | ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1)
#define | ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e)
#define | ALT_QSPI_RDDATACAP_OFST 0x10
#define | ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0
#define | ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3
#define | ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4
#define | ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f
#define | ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0
#define | ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2
#define | ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0)
#define | ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f)
#define | ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4
#define | ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15
#define | ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12
#define | ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0
#define | ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f
#define | ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100
#define | ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4)
#define | ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0)
#define | ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16
#define | ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20
#define | ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5
#define | ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000
#define | ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff
#define | ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10
#define | ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16)
#define | ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000)
#define | ALT_QSPI_DEVSZ_OFST 0x14
#define | ALT_QSPI_SRAMPART_ADDR_LSB 0
#define | ALT_QSPI_SRAMPART_ADDR_MSB 6
#define | ALT_QSPI_SRAMPART_ADDR_WIDTH 7
#define | ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x0000007f
#define | ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff80
#define | ALT_QSPI_SRAMPART_ADDR_RESET 0x40
#define | ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x0000007f) >> 0)
#define | ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x0000007f)
#define | ALT_QSPI_SRAMPART_OFST 0x18
#define | ALT_QSPI_INDADDRTRIG_ADDR_LSB 0
#define | ALT_QSPI_INDADDRTRIG_ADDR_MSB 31
#define | ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32
#define | ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff
#define | ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000
#define | ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0
#define | ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_QSPI_INDADDRTRIG_OFST 0x1c
#define | ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0
#define | ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3
#define | ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4
#define | ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f
#define | ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0
#define | ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0
#define | ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0)
#define | ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f)
#define | ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8
#define | ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11
#define | ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4
#define | ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00
#define | ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff
#define | ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0
#define | ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8)
#define | ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00)
#define | ALT_QSPI_DMAPER_OFST 0x20
#define | ALT_QSPI_REMAPADDR_VALUE_LSB 0
#define | ALT_QSPI_REMAPADDR_VALUE_MSB 31
#define | ALT_QSPI_REMAPADDR_VALUE_WIDTH 32
#define | ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff
#define | ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000
#define | ALT_QSPI_REMAPADDR_VALUE_RESET 0x0
#define | ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_QSPI_REMAPADDR_OFST 0x24
#define | ALT_QSPI_MODBIT_MOD_LSB 0
#define | ALT_QSPI_MODBIT_MOD_MSB 7
#define | ALT_QSPI_MODBIT_MOD_WIDTH 8
#define | ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff
#define | ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00
#define | ALT_QSPI_MODBIT_MOD_RESET 0x0
#define | ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0)
#define | ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff)
#define | ALT_QSPI_MODBIT_OFST 0x28
#define | ALT_QSPI_SRAMFILL_INDRDPART_LSB 0
#define | ALT_QSPI_SRAMFILL_INDRDPART_MSB 15
#define | ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16
#define | ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff
#define | ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000
#define | ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0
#define | ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0)
#define | ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff)
#define | ALT_QSPI_SRAMFILL_INDWRPART_LSB 16
#define | ALT_QSPI_SRAMFILL_INDWRPART_MSB 31
#define | ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16
#define | ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000
#define | ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff
#define | ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0
#define | ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16)
#define | ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000)
#define | ALT_QSPI_SRAMFILL_OFST 0x2c
#define | ALT_QSPI_TXTHRESH_LEVEL_LSB 0
#define | ALT_QSPI_TXTHRESH_LEVEL_MSB 3
#define | ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4
#define | ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f
#define | ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0
#define | ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1
#define | ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
#define | ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
#define | ALT_QSPI_TXTHRESH_OFST 0x30
#define | ALT_QSPI_RXTHRESH_LEVEL_LSB 0
#define | ALT_QSPI_RXTHRESH_LEVEL_MSB 3
#define | ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4
#define | ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f
#define | ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0
#define | ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1
#define | ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
#define | ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
#define | ALT_QSPI_RXTHRESH_OFST 0x34
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1
#define | ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0
#define | ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2
#define | ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2
#define | ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1
#define | ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004
#define | ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb
#define | ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0
#define | ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
#define | ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1
#define | ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0
#define | ALT_QSPI_IRQSTAT_RXOVER_LSB 7
#define | ALT_QSPI_IRQSTAT_RXOVER_MSB 7
#define | ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1
#define | ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080
#define | ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f
#define | ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0
#define | ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
#define | ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080)
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
#define | ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0
#define | ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1
#define | ALT_QSPI_IRQSTAT_TXFULL_LSB 9
#define | ALT_QSPI_IRQSTAT_TXFULL_MSB 9
#define | ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1
#define | ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200
#define | ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff
#define | ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0
#define | ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
#define | ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200)
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
#define | ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0
#define | ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1
#define | ALT_QSPI_IRQSTAT_RXFULL_LSB 11
#define | ALT_QSPI_IRQSTAT_RXFULL_MSB 11
#define | ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1
#define | ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800
#define | ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff
#define | ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0
#define | ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
#define | ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800)
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
#define | ALT_QSPI_IRQSTAT_OFST 0x40
#define | ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0
#define | ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1
#define | ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1
#define | ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1
#define | ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1
#define | ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002
#define | ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd
#define | ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0
#define | ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0
#define | ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1
#define | ALT_QSPI_IRQMSK_INDOPDONE_LSB 2
#define | ALT_QSPI_IRQMSK_INDOPDONE_MSB 2
#define | ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1
#define | ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004
#define | ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb
#define | ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0
#define | ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0
#define | ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1
#define | ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3
#define | ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3
#define | ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1
#define | ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008
#define | ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7
#define | ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0
#define | ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0
#define | ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1
#define | ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4
#define | ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4
#define | ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1
#define | ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010
#define | ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef
#define | ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0
#define | ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0
#define | ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1
#define | ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5
#define | ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5
#define | ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1
#define | ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020
#define | ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf
#define | ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0
#define | ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0
#define | ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1
#define | ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6
#define | ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6
#define | ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1
#define | ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040
#define | ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf
#define | ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0
#define | ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
#define | ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
#define | ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0
#define | ALT_QSPI_IRQMSK_RXOVER_E_END 0x1
#define | ALT_QSPI_IRQMSK_RXOVER_LSB 7
#define | ALT_QSPI_IRQMSK_RXOVER_MSB 7
#define | ALT_QSPI_IRQMSK_RXOVER_WIDTH 1
#define | ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080
#define | ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f
#define | ALT_QSPI_IRQMSK_RXOVER_RESET 0x0
#define | ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
#define | ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080)
#define | ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0
#define | ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1
#define | ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8
#define | ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8
#define | ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1
#define | ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100
#define | ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff
#define | ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0
#define | ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
#define | ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
#define | ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0
#define | ALT_QSPI_IRQMSK_TXFULL_E_END 0x1
#define | ALT_QSPI_IRQMSK_TXFULL_LSB 9
#define | ALT_QSPI_IRQMSK_TXFULL_MSB 9
#define | ALT_QSPI_IRQMSK_TXFULL_WIDTH 1
#define | ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200
#define | ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff
#define | ALT_QSPI_IRQMSK_TXFULL_RESET 0x0
#define | ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
#define | ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200)
#define | ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0
#define | ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1
#define | ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10
#define | ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10
#define | ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1
#define | ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400
#define | ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff
#define | ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0
#define | ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
#define | ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
#define | ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0
#define | ALT_QSPI_IRQMSK_RXFULL_E_END 0x1
#define | ALT_QSPI_IRQMSK_RXFULL_LSB 11
#define | ALT_QSPI_IRQMSK_RXFULL_MSB 11
#define | ALT_QSPI_IRQMSK_RXFULL_WIDTH 1
#define | ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800
#define | ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff
#define | ALT_QSPI_IRQMSK_RXFULL_RESET 0x0
#define | ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
#define | ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800)
#define | ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0
#define | ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1
#define | ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12
#define | ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12
#define | ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1
#define | ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000
#define | ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff
#define | ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0
#define | ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
#define | ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
#define | ALT_QSPI_IRQMSK_OFST 0x44
#define | ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0
#define | ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31
#define | ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32
#define | ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff
#define | ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000
#define | ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0
#define | ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_QSPI_LOWWRPROT_OFST 0x50
#define | ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0
#define | ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31
#define | ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32
#define | ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff
#define | ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000
#define | ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0
#define | ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_QSPI_UPPWRPROT_OFST 0x54
#define | ALT_QSPI_WRPROT_INV_E_EN 0x1
#define | ALT_QSPI_WRPROT_INV_E_DIS 0x0
#define | ALT_QSPI_WRPROT_INV_LSB 0
#define | ALT_QSPI_WRPROT_INV_MSB 0
#define | ALT_QSPI_WRPROT_INV_WIDTH 1
#define | ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001
#define | ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe
#define | ALT_QSPI_WRPROT_INV_RESET 0x0
#define | ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_QSPI_WRPROT_EN_E_EN 0x1
#define | ALT_QSPI_WRPROT_EN_E_DIS 0x0
#define | ALT_QSPI_WRPROT_EN_LSB 1
#define | ALT_QSPI_WRPROT_EN_MSB 1
#define | ALT_QSPI_WRPROT_EN_WIDTH 1
#define | ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002
#define | ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd
#define | ALT_QSPI_WRPROT_EN_RESET 0x0
#define | ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_QSPI_WRPROT_OFST 0x58
#define | ALT_QSPI_INDRD_START_E_END 0x1
#define | ALT_QSPI_INDRD_START_E_DISD 0x0
#define | ALT_QSPI_INDRD_START_LSB 0
#define | ALT_QSPI_INDRD_START_MSB 0
#define | ALT_QSPI_INDRD_START_WIDTH 1
#define | ALT_QSPI_INDRD_START_SET_MSK 0x00000001
#define | ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe
#define | ALT_QSPI_INDRD_START_RESET 0x0
#define | ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1
#define | ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0
#define | ALT_QSPI_INDRD_CANCEL_LSB 1
#define | ALT_QSPI_INDRD_CANCEL_MSB 1
#define | ALT_QSPI_INDRD_CANCEL_WIDTH 1
#define | ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002
#define | ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd
#define | ALT_QSPI_INDRD_CANCEL_RESET 0x0
#define | ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1
#define | ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0
#define | ALT_QSPI_INDRD_RD_STAT_LSB 2
#define | ALT_QSPI_INDRD_RD_STAT_MSB 2
#define | ALT_QSPI_INDRD_RD_STAT_WIDTH 1
#define | ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004
#define | ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb
#define | ALT_QSPI_INDRD_RD_STAT_RESET 0x0
#define | ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1
#define | ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0
#define | ALT_QSPI_INDRD_SRAM_FULL_LSB 3
#define | ALT_QSPI_INDRD_SRAM_FULL_MSB 3
#define | ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1
#define | ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008
#define | ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7
#define | ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0
#define | ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1
#define | ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0
#define | ALT_QSPI_INDRD_RD_QUEUED_LSB 4
#define | ALT_QSPI_INDRD_RD_QUEUED_MSB 4
#define | ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1
#define | ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010
#define | ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef
#define | ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0
#define | ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6)
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0)
#define | ALT_QSPI_INDRD_OFST 0x60
#define | ALT_QSPI_INDRDWATER_LEVEL_LSB 0
#define | ALT_QSPI_INDRDWATER_LEVEL_MSB 31
#define | ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32
#define | ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff
#define | ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000
#define | ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0
#define | ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_QSPI_INDRDWATER_OFST 0x64
#define | ALT_QSPI_INDRDSTADDR_ADDR_LSB 0
#define | ALT_QSPI_INDRDSTADDR_ADDR_MSB 31
#define | ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32
#define | ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff
#define | ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000
#define | ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0
#define | ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_QSPI_INDRDSTADDR_OFST 0x68
#define | ALT_QSPI_INDRDCNT_VALUE_LSB 0
#define | ALT_QSPI_INDRDCNT_VALUE_MSB 31
#define | ALT_QSPI_INDRDCNT_VALUE_WIDTH 32
#define | ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff
#define | ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000
#define | ALT_QSPI_INDRDCNT_VALUE_RESET 0x0
#define | ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_QSPI_INDRDCNT_OFST 0x6c
#define | ALT_QSPI_INDWR_START_E_END 0x1
#define | ALT_QSPI_INDWR_START_E_DISD 0x0
#define | ALT_QSPI_INDWR_START_LSB 0
#define | ALT_QSPI_INDWR_START_MSB 0
#define | ALT_QSPI_INDWR_START_WIDTH 1
#define | ALT_QSPI_INDWR_START_SET_MSK 0x00000001
#define | ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe
#define | ALT_QSPI_INDWR_START_RESET 0x0
#define | ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1
#define | ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0
#define | ALT_QSPI_INDWR_CANCEL_LSB 1
#define | ALT_QSPI_INDWR_CANCEL_MSB 1
#define | ALT_QSPI_INDWR_CANCEL_WIDTH 1
#define | ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002
#define | ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd
#define | ALT_QSPI_INDWR_CANCEL_RESET 0x0
#define | ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1
#define | ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0
#define | ALT_QSPI_INDWR_RDSTAT_LSB 2
#define | ALT_QSPI_INDWR_RDSTAT_MSB 2
#define | ALT_QSPI_INDWR_RDSTAT_WIDTH 1
#define | ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004
#define | ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb
#define | ALT_QSPI_INDWR_RDSTAT_RESET 0x0
#define | ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_QSPI_INDWR_SRAMFULL_LSB 3
#define | ALT_QSPI_INDWR_SRAMFULL_MSB 3
#define | ALT_QSPI_INDWR_SRAMFULL_WIDTH 1
#define | ALT_QSPI_INDWR_SRAMFULL_SET_MSK 0x00000008
#define | ALT_QSPI_INDWR_SRAMFULL_CLR_MSK 0xfffffff7
#define | ALT_QSPI_INDWR_SRAMFULL_RESET 0x0
#define | ALT_QSPI_INDWR_SRAMFULL_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_QSPI_INDWR_SRAMFULL_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1
#define | ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0
#define | ALT_QSPI_INDWR_RDQUEUED_LSB 4
#define | ALT_QSPI_INDWR_RDQUEUED_MSB 4
#define | ALT_QSPI_INDWR_RDQUEUED_WIDTH 1
#define | ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010
#define | ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef
#define | ALT_QSPI_INDWR_RDQUEUED_RESET 0x0
#define | ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1
#define | ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0
#define | ALT_QSPI_INDWR_INDDONE_LSB 5
#define | ALT_QSPI_INDWR_INDDONE_MSB 5
#define | ALT_QSPI_INDWR_INDDONE_WIDTH 1
#define | ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020
#define | ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf
#define | ALT_QSPI_INDWR_INDDONE_RESET 0x0
#define | ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_QSPI_INDWR_INDCNT_LSB 6
#define | ALT_QSPI_INDWR_INDCNT_MSB 7
#define | ALT_QSPI_INDWR_INDCNT_WIDTH 2
#define | ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0
#define | ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f
#define | ALT_QSPI_INDWR_INDCNT_RESET 0x0
#define | ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6)
#define | ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0)
#define | ALT_QSPI_INDWR_OFST 0x70
#define | ALT_QSPI_INDWRWATER_LEVEL_LSB 0
#define | ALT_QSPI_INDWRWATER_LEVEL_MSB 31
#define | ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32
#define | ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff
#define | ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000
#define | ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff
#define | ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_QSPI_INDWRWATER_OFST 0x74
#define | ALT_QSPI_INDWRSTADDR_ADDR_LSB 0
#define | ALT_QSPI_INDWRSTADDR_ADDR_MSB 31
#define | ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32
#define | ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff
#define | ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000
#define | ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0
#define | ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_QSPI_INDWRSTADDR_OFST 0x78
#define | ALT_QSPI_INDWRCNT_VALUE_LSB 0
#define | ALT_QSPI_INDWRCNT_VALUE_MSB 31
#define | ALT_QSPI_INDWRCNT_VALUE_WIDTH 32
#define | ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff
#define | ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000
#define | ALT_QSPI_INDWRCNT_VALUE_RESET 0x0
#define | ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_QSPI_INDWRCNT_OFST 0x7c
#define | ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1
#define | ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0
#define | ALT_QSPI_FLSHCMD_EXECCMD_LSB 0
#define | ALT_QSPI_FLSHCMD_EXECCMD_MSB 0
#define | ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1
#define | ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001
#define | ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe
#define | ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0
#define | ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1
#define | ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0
#define | ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1
#define | ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1
#define | ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1
#define | ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002
#define | ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd
#define | ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0
#define | ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7
#define | ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11
#define | ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5
#define | ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80
#define | ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f
#define | ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0
#define | ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7)
#define | ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80)
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12)
#define | ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000)
#define | ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1
#define | ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0
#define | ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15
#define | ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15
#define | ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1
#define | ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000
#define | ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff
#define | ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0
#define | ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15)
#define | ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000)
#define | ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0
#define | ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1
#define | ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2
#define | ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3
#define | ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16
#define | ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17
#define | ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2
#define | ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000
#define | ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff
#define | ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0
#define | ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16)
#define | ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000)
#define | ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1
#define | ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0
#define | ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18
#define | ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18
#define | ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1
#define | ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000
#define | ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff
#define | ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0
#define | ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18)
#define | ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000)
#define | ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1
#define | ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0
#define | ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19
#define | ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19
#define | ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1
#define | ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000
#define | ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff
#define | ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0
#define | ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19)
#define | ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000)
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20)
#define | ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000)
#define | ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1
#define | ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0
#define | ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23
#define | ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23
#define | ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1
#define | ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000
#define | ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff
#define | ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0
#define | ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23)
#define | ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000)
#define | ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24
#define | ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31
#define | ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8
#define | ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000
#define | ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff
#define | ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0
#define | ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24)
#define | ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000)
#define | ALT_QSPI_FLSHCMD_OFST 0x90
#define | ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0
#define | ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31
#define | ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32
#define | ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff
#define | ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000
#define | ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0
#define | ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_QSPI_FLSHCMDADDR_OFST 0x94
#define | ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0
#define | ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31
#define | ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32
#define | ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff
#define | ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000
#define | ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0
#define | ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0
#define | ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0
#define | ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31
#define | ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32
#define | ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff
#define | ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000
#define | ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0
#define | ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4
#define | ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0
#define | ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31
#define | ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32
#define | ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff
#define | ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000
#define | ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0
#define | ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8
#define | ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0
#define | ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31
#define | ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32
#define | ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff
#define | ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000
#define | ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0
#define | ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac
#define | ALT_QSPI_MODULEID_VALUE_LSB 0
#define | ALT_QSPI_MODULEID_VALUE_MSB 24
#define | ALT_QSPI_MODULEID_VALUE_WIDTH 25
#define | ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff
#define | ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000
#define | ALT_QSPI_MODULEID_VALUE_RESET 0x1001
#define | ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0)
#define | ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff)
#define | ALT_QSPI_MODULEID_OFST 0xfc

## Typedefs
typedef volatile struct ALT_QSPI_CFG_s | ALT_QSPI_CFG_t
typedef volatile struct ALT_QSPI_DEVRD_s | ALT_QSPI_DEVRD_t
typedef volatile struct ALT_QSPI_DEVWR_s | ALT_QSPI_DEVWR_t
typedef volatile struct ALT_QSPI_DELAY_s | ALT_QSPI_DELAY_t
typedef volatile struct ALT_QSPI_RDDATACAP_s | ALT_QSPI_RDDATACAP_t
typedef volatile struct ALT_QSPI_DEVSZ_s | ALT_QSPI_DEVSZ_t
typedef volatile struct ALT_QSPI_SRAMPART_s | ALT_QSPI_SRAMPART_t
typedef volatile struct ALT_QSPI_INDADDRTRIG_s | ALT_QSPI_INDADDRTRIG_t
typedef volatile struct ALT_QSPI_DMAPER_s | ALT_QSPI_DMAPER_t
typedef volatile struct ALT_QSPI_REMAPADDR_s | ALT_QSPI_REMAPADDR_t
typedef volatile struct ALT_QSPI_MODBIT_s | ALT_QSPI_MODBIT_t
typedef volatile struct ALT_QSPI_SRAMFILL_s | ALT_QSPI_SRAMFILL_t
typedef volatile struct ALT_QSPI_TXTHRESH_s | ALT_QSPI_TXTHRESH_t
typedef volatile struct ALT_QSPI_RXTHRESH_s | ALT_QSPI_RXTHRESH_t
typedef volatile struct ALT_QSPI_IRQSTAT_s | ALT_QSPI_IRQSTAT_t
typedef volatile struct ALT_QSPI_IRQMSK_s | ALT_QSPI_IRQMSK_t
typedef volatile struct ALT_QSPI_LOWWRPROT_s | ALT_QSPI_LOWWRPROT_t
typedef volatile struct ALT_QSPI_UPPWRPROT_s | ALT_QSPI_UPPWRPROT_t
typedef volatile struct ALT_QSPI_WRPROT_s | ALT_QSPI_WRPROT_t
typedef volatile struct ALT_QSPI_INDRD_s | ALT_QSPI_INDRD_t
typedef volatile struct ALT_QSPI_INDRDWATER_s | ALT_QSPI_INDRDWATER_t
typedef volatile struct ALT_QSPI_INDRDSTADDR_s | ALT_QSPI_INDRDSTADDR_t
typedef volatile struct ALT_QSPI_INDRDCNT_s | ALT_QSPI_INDRDCNT_t
typedef volatile struct ALT_QSPI_INDWR_s | ALT_QSPI_INDWR_t
typedef volatile struct ALT_QSPI_INDWRWATER_s | ALT_QSPI_INDWRWATER_t
typedef volatile struct ALT_QSPI_INDWRSTADDR_s | ALT_QSPI_INDWRSTADDR_t
typedef volatile struct ALT_QSPI_INDWRCNT_s | ALT_QSPI_INDWRCNT_t
typedef volatile struct ALT_QSPI_FLSHCMD_s | ALT_QSPI_FLSHCMD_t
typedef volatile struct ALT_QSPI_FLSHCMDADDR_s | ALT_QSPI_FLSHCMDADDR_t
typedef volatile struct ALT_QSPI_FLSHCMDRDDATALO_s | ALT_QSPI_FLSHCMDRDDATALO_t
typedef volatile struct ALT_QSPI_FLSHCMDRDDATAUP_s | ALT_QSPI_FLSHCMDRDDATAUP_t
typedef volatile struct ALT_QSPI_FLSHCMDWRDATALO_s | ALT_QSPI_FLSHCMDWRDATALO_t
typedef volatile struct ALT_QSPI_FLSHCMDWRDATAUP_s | ALT_QSPI_FLSHCMDWRDATAUP_t
typedef volatile struct ALT_QSPI_MODULEID_s | ALT_QSPI_MODULEID_t
typedef volatile struct ALT_QSPI_s | ALT_QSPI_t
typedef volatile struct ALT_QSPI_raw_s | ALT_QSPI_raw_t