RTEMS: bsps/bfin/include/libcpu/ppiRegs.h Source File

| RTEMS 5.4-rc2

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ppiRegs.h
1/* Blackfin Parallel Peripheral Interface Registers
2 *
3 * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
4 * written by Allan Hessenflow <allanh@kallisti.com>
5 *
6 * The license and distribution terms for this file may be
7 * found in the file LICENSE in this distribution or at
8 * http://www.rtems.org/license/LICENSE.
9 */
10
11#ifndef _ppiRegs_h_
12#define _ppiRegs_h_
13
14
15/* register addresses */
16
17#define PPI_CONTROL_OFFSET 0x0000
18#define PPI_STATUS_OFFSET 0x0004
19#define PPI_COUNT_OFFSET 0x0008
20#define PPI_DELAY_OFFSET 0x000c
21#define PPI_FRAME_OFFSET 0x0010
22
23
24/* register fields */
25
26#define PPI_CONTROL_POLS 0x8000
27#define PPI_CONTROL_POLC 0x4000
28#define PPI_CONTROL_DLEN_MASK 0x3800
29#define PPI_CONTROL_DLEN_8 0x0000
30#define PPI_CONTROL_DLEN_10 0x0800
31#define PPI_CONTROL_DLEN_11 0x1000
32#define PPI_CONTROL_DLEN_12 0x1800
33#define PPI_CONTROL_DLEN_13 0x2000
34#define PPI_CONTROL_DLEN_14 0x2800
35#define PPI_CONTROL_DLEN_15 0x3000
36#define PPI_CONTROL_DLEN_16 0x3800
37#define PPI_CONTROL_SKIP_EO 0x0400
38#define PPI_CONTROL_SKIP_EN 0x0200
39#define PPI_CONTROL_PACK_EN 0x0080
40#define PPI_CONTROL_FLD_SEL 0x0040
41#define PPI_CONTROL_PORT_CFG_MASK 0x0030
42#define PPI_CONTROL_PORT_CFG_SHIFT 4
43#define PPI_CONTROL_XFR_TYPE_MASK 0x000c
44#define PPI_CONTROL_XFR_TYPE_SHIFT 2
45#define PPI_CONTROL_PORT_DIR 0x0002
46#define PPI_CONTROL_PORT_EN 0x0001
47
48#define PPI_STATUS_ERR_NCOR 0x8000
49#define PPI_STATUS_ERR_DET 0x4000
50#define PPI_STATUS_UNDR 0x2000
51#define PPI_STATUS_OVR 0x1000
52#define PPI_STATUS_FT_ERR 0x0800
53#define PPI_STATUS_FLD 0x0400
54#define PPI_STATUS_LT_ERR_UNDR 0x0200
55#define PPI_STATUS_LT_ERR_OVR 0x0100
56
57
58#endif /* _ppiRegs_h_ */