RTEMS: bsps/arm/atsam/include/libchip/include/sams70/component/component_rstc.h Source File

| RTEMS 5.4-rc2

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component_rstc.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70_RSTC_COMPONENT_
31#define _SAMS70_RSTC_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __O uint32_t RSTC_CR;
43 __I uint32_t RSTC_SR;
44 __IO uint32_t RSTC_MR;
45} Rstc;
46#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
47/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
48#define RSTC_CR_PROCRST (0x1u << 0)
49#define RSTC_CR_EXTRST (0x1u << 3)
50#define RSTC_CR_KEY_Pos 24
51#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos)
52#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
53#define RSTC_CR_KEY_PASSWD (0xA5u << 24)
54/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
55#define RSTC_SR_URSTS (0x1u << 0)
56#define RSTC_SR_RSTTYP_Pos 8
57#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos)
58#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8)
59#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8)
60#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8)
61#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8)
62#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8)
63#define RSTC_SR_NRSTL (0x1u << 16)
64#define RSTC_SR_SRCMP (0x1u << 17)
65/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
66#define RSTC_MR_URSTEN (0x1u << 0)
67#define RSTC_MR_URSTIEN (0x1u << 4)
68#define RSTC_MR_ERSTL_Pos 8
69#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos)
70#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
71#define RSTC_MR_KEY_Pos 24
72#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos)
73#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
74#define RSTC_MR_KEY_PASSWD (0xA5u << 24)
77
78
79#endif /* _SAMS70_RSTC_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Rstc
Rstc hardware registers.
Definition: component_rstc.h:41