RTEMS: bsps/lm32/lm32_evr/include/system_conf.h Source File

| RTEMS 5.4-rc2

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system_conf.h
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1
9#ifndef __SYSTEM_CONFIG_H_
10#define __SYSTEM_CONFIG_H_
11
12
13#define FPGA_DEVICE_FAMILY "ECP2M"
14#define PLATFORM_NAME "platform1"
15#define USE_PLL (0)
16#define CPU_FREQUENCY (75000000)
17
18
19/* FOUND 1 CPU UNIT(S) */
20
21/*
22 * CPU Instance LM32 component configuration
23 */
24#define CPU_NAME "LM32"
25#define CPU_EBA (0x04000000)
26#define CPU_DIVIDE_ENABLED (1)
27#define CPU_SIGN_EXTEND_ENABLED (1)
28#define CPU_MULTIPLIER_ENABLED (1)
29#define CPU_SHIFT_ENABLED (1)
30#define CPU_DEBUG_ENABLED (1)
31#define CPU_HW_BREAKPOINTS_ENABLED (0)
32#define CPU_NUM_HW_BREAKPOINTS (0)
33#define CPU_NUM_WATCHPOINTS (0)
34#define CPU_ICACHE_ENABLED (1)
35#define CPU_ICACHE_SETS (512)
36#define CPU_ICACHE_ASSOC (1)
37#define CPU_ICACHE_BYTES_PER_LINE (16)
38#define CPU_DCACHE_ENABLED (1)
39#define CPU_DCACHE_SETS (512)
40#define CPU_DCACHE_ASSOC (1)
41#define CPU_DCACHE_BYTES_PER_LINE (16)
42#define CPU_DEBA (0x0C000000)
43#define CPU_CHARIO_IN (1)
44#define CPU_CHARIO_OUT (1)
45#define CPU_CHARIO_TYPE "JTAG UART"
46
47/*
48 * gpio component configuration
49 */
50#define GPIO_NAME "gpio"
51#define GPIO_BASE_ADDRESS (0x80004000)
52#define GPIO_SIZE (128)
53#define GPIO_CHARIO_IN (0)
54#define GPIO_CHARIO_OUT (0)
55#define GPIO_ADDRESS_LOCK (1)
56#define GPIO_DISABLE (0)
57#define GPIO_OUTPUT_PORTS_ONLY (1)
58#define GPIO_INPUT_PORTS_ONLY (0)
59#define GPIO_TRISTATE_PORTS (0)
60#define GPIO_BOTH_INPUT_AND_OUTPUT (0)
61#define GPIO_DATA_WIDTH (4)
62#define GPIO_INPUT_WIDTH (1)
63#define GPIO_OUTPUT_WIDTH (1)
64#define GPIO_IRQ_MODE (0)
65#define GPIO_LEVEL (0)
66#define GPIO_EDGE (0)
67#define GPIO_EITHER_EDGE_IRQ (0)
68#define GPIO_POSE_EDGE_IRQ (0)
69#define GPIO_NEGE_EDGE_IRQ (0)
70
71/*
72 * uart component configuration
73 */
74#define UART_NAME "uart"
75#define UART_BASE_ADDRESS (0x80006000)
76#define UART_SIZE (128)
77#define UART_IRQ (0)
78#define UART_CHARIO_IN (1)
79#define UART_CHARIO_OUT (1)
80#define UART_CHARIO_TYPE "RS-232"
81#define UART_ADDRESS_LOCK (1)
82#define UART_DISABLE (0)
83#define UART_MODEM (0)
84#define UART_ADDRWIDTH (5)
85#define UART_DATAWIDTH (8)
86#define UART_BAUD_RATE (115200)
87#define UART_IB_SIZE (4)
88#define UART_OB_SIZE (4)
89#define UART_BLOCK_WRITE (1)
90#define UART_BLOCK_READ (1)
91#define UART_DATA_BITS (8)
92#define UART_STOP_BITS (1)
93#define UART_FIFO (0)
94#define UART_INTERRUPT_DRIVEN (1)
95
96/*
97 * ebr component configuration
98 */
99#define EBR_NAME "ebr"
100#define EBR_BASE_ADDRESS (0x04000000)
101#define EBR_SIZE (32768)
102#define EBR_IS_READABLE (1)
103#define EBR_IS_WRITABLE (1)
104#define EBR_ADDRESS_LOCK (1)
105#define EBR_DISABLE (0)
106#define EBR_EBR_DATA_WIDTH (32)
107#define EBR_INIT_FILE_NAME "none"
108#define EBR_INIT_FILE_FORMAT "hex"
109
110/*
111 * ts_mac_core component configuration
112 */
113#define TS_MAC_CORE_NAME "ts_mac_core"
114#define TS_MAC_CORE_BASE_ADDRESS (0x80008000)
115#define TS_MAC_CORE_SIZE (8192)
116#define TS_MAC_CORE_IRQ (2)
117#define TS_MAC_CORE_CHARIO_IN (0)
118#define TS_MAC_CORE_CHARIO_OUT (0)
119#define TS_MAC_CORE_ADDRESS_LOCK (1)
120#define TS_MAC_CORE_DISABLE (0)
121#define TS_MAC_CORE_STAT_REGS (1)
122#define TS_MAC_CORE_TXRX_FIFO_DEPTH (512)
123#define TS_MAC_CORE_MIIM_MODULE (1)
124#define TS_MAC_CORE_NGO "l:/mrf/lattice/crio-lm32/platform1/components/ts_mac_top_v27/ipexpress/ts_mac_core/ts_mac_core.ngo"
125#define TS_MAC_CORE_ISPLEVER_PRJ "l:/mrf/lattice/crio-lm32/criomico.syn"
126
127/*
128 * timer0 component configuration
129 */
130#define TIMER0_NAME "timer0"
131#define TIMER0_BASE_ADDRESS (0x80002000)
132#define TIMER0_SIZE (128)
133#define TIMER0_IRQ (1)
134#define TIMER0_CHARIO_IN (0)
135#define TIMER0_CHARIO_OUT (0)
136#define TIMER0_ADDRESS_LOCK (1)
137#define TIMER0_DISABLE (0)
138#define TIMER0_PERIOD_NUM (20)
139#define TIMER0_PERIOD_WIDTH (32)
140#define TIMER0_WRITEABLE_PERIOD (1)
141#define TIMER0_READABLE_SNAPSHOT (1)
142#define TIMER0_START_STOP_CONTROL (1)
143#define TIMER0_WATCHDOG (0)
144
145/*
146 * timer1 component configuration
147 */
148#define TIMER1_NAME "timer1"
149#define TIMER1_BASE_ADDRESS (0x8000A000)
150#define TIMER1_SIZE (128)
151#define TIMER1_IRQ (3)
152#define TIMER1_CHARIO_IN (0)
153#define TIMER1_CHARIO_OUT (0)
154#define TIMER1_ADDRESS_LOCK (1)
155#define TIMER1_DISABLE (0)
156#define TIMER1_PERIOD_NUM (20)
157#define TIMER1_PERIOD_WIDTH (32)
158#define TIMER1_WRITEABLE_PERIOD (1)
159#define TIMER1_READABLE_SNAPSHOT (1)
160#define TIMER1_START_STOP_CONTROL (1)
161#define TIMER1_WATCHDOG (0)
162
163/*
164 * ddr2_sdram component configuration
165 */
166#define DDR2_SDRAM_NAME "ddr2_sdram"
167#define DDR2_SDRAM_BASE_ADDRESS (0x08000000)
168#define DDR2_SDRAM_SIZE (33554432)
169#define DDR2_SDRAM_IS_READABLE (1)
170#define DDR2_SDRAM_IS_WRITABLE (1)
171#define DDR2_SDRAM_BST_CNT_READ (1)
172#define DDR2_SDRAM_ADDRESS_LOCK (1)
173#define DDR2_SDRAM_DISABLE (0)
174#define DDR2_SDRAM_NGO "L:/mrf/lattice/cRIO-LM32/platform1/components/wb_ddr2_ctl_v65/ipexpress/ddr2_sdram/ddr2_sdram.ngo"
175#define DDR2_SDRAM_ISPLEVER_PRJ "l:/mrf/lattice/crio-lm32/criomico.syn"
176#define DDR2_SDRAM_PARAM_FILE "ddr_p_eval/$/src/params/ddr_sdram_mem_params.v"
177#define DDR2_SDRAM_MEM_TOP "ddr_p_eval/$/src/rtl/top/@/ddr_sdram_mem_top.v"
178
179
180#endif /* __SYSTEM_CONFIG_H_ */