RTEMS: bsps/include/grlib/satcan.h Source File

| RTEMS 5.4-rc2

Loading...
Searching...
No Matches
satcan.h
1/*
2 * Header file for RTEMS SATCAN FPGA driver
3 *
4 * COPYRIGHT (c) 2009.
5 * Cobham Gaisler AB.
6 *
7 * The license and distribution terms for this file may be
8 * found in the file LICENSE in this distribution or at
9 * http://www.rtems.org/license/LICENSE.
10 */
11
12#ifndef __SATCAN_H__
13#define __SATCAN_H__
14
15#ifdef __cplusplus
16extern "C" {
17#endif
18
19/* Config structure passed to SatCAN_init(..) */
20 typedef struct {
21 /* Configuration */
22 int nodeno;
23 int dps;
24 /* Callback functions */
25 void (*ahb_irq_callback)(void);
26 void (*pps_irq_callback)(void);
27 void (*m5_irq_callback)(void);
28 void (*m4_irq_callback)(void);
29 void (*m3_irq_callback)(void);
30 void (*m2_irq_callback)(void);
31 void (*m1_irq_callback)(void);
32 void (*sync_irq_callback)(void);
33 void (*can_irq_callback)(unsigned int fifo);
34} satcan_config;
35
36#define SATCAN_HEADER_SIZE 4
37#define SATCAN_HEADER_NMM_POS 3
38#define SATCAN_PAYLOAD_SIZE 8
39
40/* SatCAN message */
41 typedef struct {
42 unsigned char header[SATCAN_HEADER_SIZE]; /* Header of SatCAN message */
43 unsigned char payload[SATCAN_PAYLOAD_SIZE]; /* Payload of SatCAN message */
44} satcan_msg;
45
46/* SatCAN modify register structure */
47 typedef struct {
48 unsigned int reg;
49 unsigned int val;
50} satcan_regmod;
51
52/* Driver interface */
53int satcan_register(satcan_config *conf);
54
55/* SatCAN interrupt IDs */
56#define SATCAN_IRQ_NONACT_TO_ACT 0
57#define SATCAN_IRQ_ACTIVE_TO_NONACT 1
58#define SATCAN_IRQ_STR1_TO_DPS 2
59#define SATCAN_IRQ_DPS_TO_STR1 3
60#define SATCAN_IRQ_STR2_TO_DPS 4
61#define SATCAN_IRQ_DPS_TO_STR2 5
62#define SATCAN_IRQ_STR3_TO_DPS 6
63#define SATCAN_IRQ_DPS_TO_STR3 7
64#define SATCAN_IRQ_PLD1_TO_DPS 8
65#define SATCAN_IRQ_DPS_TO_PLD1 9
66#define SATCAN_IRQ_PLD2_TO_DPS 10
67#define SATCAN_IRQ_DPS_TO_PLD2 11
68#define SATCAN_IRQ_SYNC 16
69#define SATCAN_IRQ_TIME_MARKER1 17
70#define SATCAN_IRQ_TIME_MARKER2 18
71#define SATCAN_IRQ_TIME_MARKER3 19
72#define SATCAN_IRQ_TIME_MARKER4 20
73#define SATCAN_IRQ_TIME_MARKER5 21
74#define SATCAN_IRQ_EOD1 22
75#define SATCAN_IRQ_EOD2 23
76#define SATCAN_IRQ_TOD 24
77#define SATCAN_IRQ_CRITICAL 25
78
79/* IOC */
80#define SATCAN_IOC_DMA_2K 1 /* Use DMA area for 2K messages */
81#define SATCAN_IOC_DMA_8K 2 /* Use DMA area for 8K messages */
82#define SATCAN_IOC_GET_REG 3 /* Provides direct read access to all core registers */
83#define SATCAN_IOC_SET_REG 4 /* Provides direct write access to all core registers */
84#define SATCAN_IOC_OR_REG 5 /* Provides direct read access to all core registers */
85#define SATCAN_IOC_AND_REG 6 /* Provides direct write access to all core registers */
86#define SATCAN_IOC_EN_TX1_DIS_TX2 7 /* Enable DMA TX channel 1, Disable DMA TX channel 2 */
87#define SATCAN_IOC_EN_TX2_DIS_TX1 8 /* Enable DMA TX channel 2, Disable DMA TX channel 1 */
88#define SATCAN_IOC_GET_DMA_MODE 9 /* Returns the current DMA mode */
89#define SATCAN_IOC_SET_DMA_MODE 10 /* Sets the DMA mode */
90#define SATCAN_IOC_ACTIVATE_DMA 11 /* Directly activate DMA channel */
91#define SATCAN_IOC_DEACTIVATE_DMA 12 /* Directly deactivate DMA channel */
92#define SATCAN_IOC_DMA_STATUS 13 /* Returns status of directly activated DMA */
93#define SATCAN_IOC_GET_DOFFSET 14 /* Get TX DMA offset */
94#define SATCAN_IOC_SET_DOFFSET 15 /* Set TX DMA offset */
95#define SATCAN_IOC_GET_TIMEOUT 16 /* Set TX DMA timeout */
96#define SATCAN_IOC_SET_TIMEOUT 17 /* Get TX DMA timeout */
97
98
99/* Values used to select core register with IOC_SET_REG/IOC_GET_REG */
100#define SATCAN_SWRES 0 /* Software reset */
101#define SATCAN_INT_EN 1 /* Interrupt enable */
102#define SATCAN_FIFO 3 /* FIFO read */
103#define SATCAN_FIFO_RES 4 /* FIFO reset */
104#define SATCAN_TSTAMP 5 /* Current time stamp */
105#define SATCAN_CMD0 6 /* Command register 0 */
106#define SATCAN_CMD1 7 /* Command register 1 */
107#define SATCAN_START_CTC 8 /* Start cycle time counter */
108#define SATCAN_RAM_BASE 9 /* RAM offset address */
109#define SATCAN_STOP_CTC 10 /* Stop cycle time counter / DPS active status */
110#define SATCAN_DPS_ACT 10 /* Stop cycle time counter / DPS active status */
111#define SATCAN_PLL_RST 11 /* DPLL reset */
112#define SATCAN_PLL_CMD 12 /* DPLL command */
113#define SATCAN_PLL_STAT 13 /* DPLL status */
114#define SATCAN_PLL_OFF 14 /* DPLL offset */
115#define SATCAN_DMA 15 /* DMA channel enable */
116#define SATCAN_DMA_TX_1_CUR 16 /* DMA channel 1 TX current address */
117#define SATCAN_DMA_TX_1_END 17 /* DMA channel 1 TX end address */
118#define SATCAN_DMA_TX_2_CUR 18 /* DMA channel 2 TX current address */
119#define SATCAN_DMA_TX_2_END 19 /* DMA channel 2 TX end address */
120#define SATCAN_RX 20 /* CAN RX enable / Filter start ID */
121#define SATCAN_FILTER_START 20 /* CAN RX enable / Filter start ID */
122#define SATCAN_FILTER_SETUP 21 /* Filter setup / Filter stop ID */
123#define SATCAN_FILTER_STOP 21 /* Filter setup / Filter stop ID */
124#define SATCAN_WCTRL 32 /* Wrapper status/control register */
125#define SATCAN_WIPEND 33 /* Wrapper interrupt pending register */
126#define SATCAN_WIMASK 34 /* Wrapper interrupt mask register */
127#define SATCAN_WAHBADDR 35 /* Wrapper AHB address register */
128
129
130/* Values used to communicate DMA mode */
131#define SATCAN_DMA_MODE_USER 0
132#define SATCAN_DMA_MODE_SYSTEM 1
133
134/* Values used to directly activate DMA channel */
135#define SATCAN_DMA_ENABLE_TX1 1
136#define SATCAN_DMA_ENABLE_TX2 2
137
138#ifdef __cplusplus
139}
140#endif
141
142#endif /* __SATCAN_H__ */
satcan_config
Definition: satcan.h:20
satcan_msg
Definition: satcan.h:41
satcan_regmod
Definition: satcan.h:47