RTEMS: bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h File Reference

| RTEMS 5.4-rc2

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Data Structures | Macros | Typedefs
alt_rstmgr.h File Reference
Board Support Packages » ARM » Intel Cyclone V » Contributed Code

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## Data Structures
struct | ALT_RSTMGR_STAT_s
struct | ALT_RSTMGR_CTL_s
struct | ALT_RSTMGR_COUNTS_s
struct | ALT_RSTMGR_MPUMODRST_s
struct | ALT_RSTMGR_PERMODRST_s
struct | ALT_RSTMGR_PER2MODRST_s
struct | ALT_RSTMGR_BRGMODRST_s
struct | ALT_RSTMGR_MISCMODRST_s
struct | ALT_RSTMGR_s
struct | ALT_RSTMGR_raw_s

## Macros
#define | ALT_RSTMGR_STAT_PORVOLTRST_LSB 0
#define | ALT_RSTMGR_STAT_PORVOLTRST_MSB 0
#define | ALT_RSTMGR_STAT_PORVOLTRST_WIDTH 1
#define | ALT_RSTMGR_STAT_PORVOLTRST_SET_MSK 0x00000001
#define | ALT_RSTMGR_STAT_PORVOLTRST_CLR_MSK 0xfffffffe
#define | ALT_RSTMGR_STAT_PORVOLTRST_RESET 0x0
#define | ALT_RSTMGR_STAT_PORVOLTRST_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_RSTMGR_STAT_PORVOLTRST_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_RSTMGR_STAT_NPORPINRST_LSB 1
#define | ALT_RSTMGR_STAT_NPORPINRST_MSB 1
#define | ALT_RSTMGR_STAT_NPORPINRST_WIDTH 1
#define | ALT_RSTMGR_STAT_NPORPINRST_SET_MSK 0x00000002
#define | ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK 0xfffffffd
#define | ALT_RSTMGR_STAT_NPORPINRST_RESET 0x0
#define | ALT_RSTMGR_STAT_NPORPINRST_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_RSTMGR_STAT_NPORPINRST_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_RSTMGR_STAT_FPGACOLDRST_LSB 2
#define | ALT_RSTMGR_STAT_FPGACOLDRST_MSB 2
#define | ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH 1
#define | ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK 0x00000004
#define | ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK 0xfffffffb
#define | ALT_RSTMGR_STAT_FPGACOLDRST_RESET 0x0
#define | ALT_RSTMGR_STAT_FPGACOLDRST_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_RSTMGR_STAT_FPGACOLDRST_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB 3
#define | ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB 3
#define | ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH 1
#define | ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK 0x00000008
#define | ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK 0xfffffff7
#define | ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET 0x0
#define | ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_RSTMGR_STAT_SWCOLDRST_LSB 4
#define | ALT_RSTMGR_STAT_SWCOLDRST_MSB 4
#define | ALT_RSTMGR_STAT_SWCOLDRST_WIDTH 1
#define | ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK 0x00000010
#define | ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK 0xffffffef
#define | ALT_RSTMGR_STAT_SWCOLDRST_RESET 0x0
#define | ALT_RSTMGR_STAT_SWCOLDRST_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_RSTMGR_STAT_SWCOLDRST_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_RSTMGR_STAT_NRSTPINRST_LSB 8
#define | ALT_RSTMGR_STAT_NRSTPINRST_MSB 8
#define | ALT_RSTMGR_STAT_NRSTPINRST_WIDTH 1
#define | ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK 0x00000100
#define | ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK 0xfffffeff
#define | ALT_RSTMGR_STAT_NRSTPINRST_RESET 0x0
#define | ALT_RSTMGR_STAT_NRSTPINRST_GET(value) (((value) & 0x00000100) >> 8)
#define | ALT_RSTMGR_STAT_NRSTPINRST_SET(value) (((value) << 8) & 0x00000100)
#define | ALT_RSTMGR_STAT_FPGAWARMRST_LSB 9
#define | ALT_RSTMGR_STAT_FPGAWARMRST_MSB 9
#define | ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH 1
#define | ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK 0x00000200
#define | ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK 0xfffffdff
#define | ALT_RSTMGR_STAT_FPGAWARMRST_RESET 0x0
#define | ALT_RSTMGR_STAT_FPGAWARMRST_GET(value) (((value) & 0x00000200) >> 9)
#define | ALT_RSTMGR_STAT_FPGAWARMRST_SET(value) (((value) << 9) & 0x00000200)
#define | ALT_RSTMGR_STAT_SWWARMRST_LSB 10
#define | ALT_RSTMGR_STAT_SWWARMRST_MSB 10
#define | ALT_RSTMGR_STAT_SWWARMRST_WIDTH 1
#define | ALT_RSTMGR_STAT_SWWARMRST_SET_MSK 0x00000400
#define | ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK 0xfffffbff
#define | ALT_RSTMGR_STAT_SWWARMRST_RESET 0x0
#define | ALT_RSTMGR_STAT_SWWARMRST_GET(value) (((value) & 0x00000400) >> 10)
#define | ALT_RSTMGR_STAT_SWWARMRST_SET(value) (((value) << 10) & 0x00000400)
#define | ALT_RSTMGR_STAT_MPUWD0RST_LSB 12
#define | ALT_RSTMGR_STAT_MPUWD0RST_MSB 12
#define | ALT_RSTMGR_STAT_MPUWD0RST_WIDTH 1
#define | ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK 0x00001000
#define | ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK 0xffffefff
#define | ALT_RSTMGR_STAT_MPUWD0RST_RESET 0x0
#define | ALT_RSTMGR_STAT_MPUWD0RST_GET(value) (((value) & 0x00001000) >> 12)
#define | ALT_RSTMGR_STAT_MPUWD0RST_SET(value) (((value) << 12) & 0x00001000)
#define | ALT_RSTMGR_STAT_MPUWD1RST_LSB 13
#define | ALT_RSTMGR_STAT_MPUWD1RST_MSB 13
#define | ALT_RSTMGR_STAT_MPUWD1RST_WIDTH 1
#define | ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK 0x00002000
#define | ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK 0xffffdfff
#define | ALT_RSTMGR_STAT_MPUWD1RST_RESET 0x0
#define | ALT_RSTMGR_STAT_MPUWD1RST_GET(value) (((value) & 0x00002000) >> 13)
#define | ALT_RSTMGR_STAT_MPUWD1RST_SET(value) (((value) << 13) & 0x00002000)
#define | ALT_RSTMGR_STAT_L4WD0RST_LSB 14
#define | ALT_RSTMGR_STAT_L4WD0RST_MSB 14
#define | ALT_RSTMGR_STAT_L4WD0RST_WIDTH 1
#define | ALT_RSTMGR_STAT_L4WD0RST_SET_MSK 0x00004000
#define | ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK 0xffffbfff
#define | ALT_RSTMGR_STAT_L4WD0RST_RESET 0x0
#define | ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00004000) >> 14)
#define | ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 14) & 0x00004000)
#define | ALT_RSTMGR_STAT_L4WD1RST_LSB 15
#define | ALT_RSTMGR_STAT_L4WD1RST_MSB 15
#define | ALT_RSTMGR_STAT_L4WD1RST_WIDTH 1
#define | ALT_RSTMGR_STAT_L4WD1RST_SET_MSK 0x00008000
#define | ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK 0xffff7fff
#define | ALT_RSTMGR_STAT_L4WD1RST_RESET 0x0
#define | ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00008000) >> 15)
#define | ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 15) & 0x00008000)
#define | ALT_RSTMGR_STAT_FPGADBGRST_LSB 18
#define | ALT_RSTMGR_STAT_FPGADBGRST_MSB 18
#define | ALT_RSTMGR_STAT_FPGADBGRST_WIDTH 1
#define | ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK 0x00040000
#define | ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK 0xfffbffff
#define | ALT_RSTMGR_STAT_FPGADBGRST_RESET 0x0
#define | ALT_RSTMGR_STAT_FPGADBGRST_GET(value) (((value) & 0x00040000) >> 18)
#define | ALT_RSTMGR_STAT_FPGADBGRST_SET(value) (((value) << 18) & 0x00040000)
#define | ALT_RSTMGR_STAT_CDBGREQRST_LSB 19
#define | ALT_RSTMGR_STAT_CDBGREQRST_MSB 19
#define | ALT_RSTMGR_STAT_CDBGREQRST_WIDTH 1
#define | ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK 0x00080000
#define | ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK 0xfff7ffff
#define | ALT_RSTMGR_STAT_CDBGREQRST_RESET 0x0
#define | ALT_RSTMGR_STAT_CDBGREQRST_GET(value) (((value) & 0x00080000) >> 19)
#define | ALT_RSTMGR_STAT_CDBGREQRST_SET(value) (((value) << 19) & 0x00080000)
#define | ALT_RSTMGR_STAT_SDRSELFREFTMO_LSB 24
#define | ALT_RSTMGR_STAT_SDRSELFREFTMO_MSB 24
#define | ALT_RSTMGR_STAT_SDRSELFREFTMO_WIDTH 1
#define | ALT_RSTMGR_STAT_SDRSELFREFTMO_SET_MSK 0x01000000
#define | ALT_RSTMGR_STAT_SDRSELFREFTMO_CLR_MSK 0xfeffffff
#define | ALT_RSTMGR_STAT_SDRSELFREFTMO_RESET 0x0
#define | ALT_RSTMGR_STAT_SDRSELFREFTMO_GET(value) (((value) & 0x01000000) >> 24)
#define | ALT_RSTMGR_STAT_SDRSELFREFTMO_SET(value) (((value) << 24) & 0x01000000)
#define | ALT_RSTMGR_STAT_FPGAMGRHSTMO_LSB 25
#define | ALT_RSTMGR_STAT_FPGAMGRHSTMO_MSB 25
#define | ALT_RSTMGR_STAT_FPGAMGRHSTMO_WIDTH 1
#define | ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET_MSK 0x02000000
#define | ALT_RSTMGR_STAT_FPGAMGRHSTMO_CLR_MSK 0xfdffffff
#define | ALT_RSTMGR_STAT_FPGAMGRHSTMO_RESET 0x0
#define | ALT_RSTMGR_STAT_FPGAMGRHSTMO_GET(value) (((value) & 0x02000000) >> 25)
#define | ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET(value) (((value) << 25) & 0x02000000)
#define | ALT_RSTMGR_STAT_SCANHSTMO_LSB 26
#define | ALT_RSTMGR_STAT_SCANHSTMO_MSB 26
#define | ALT_RSTMGR_STAT_SCANHSTMO_WIDTH 1
#define | ALT_RSTMGR_STAT_SCANHSTMO_SET_MSK 0x04000000
#define | ALT_RSTMGR_STAT_SCANHSTMO_CLR_MSK 0xfbffffff
#define | ALT_RSTMGR_STAT_SCANHSTMO_RESET 0x0
#define | ALT_RSTMGR_STAT_SCANHSTMO_GET(value) (((value) & 0x04000000) >> 26)
#define | ALT_RSTMGR_STAT_SCANHSTMO_SET(value) (((value) << 26) & 0x04000000)
#define | ALT_RSTMGR_STAT_FPGAHSTMO_LSB 27
#define | ALT_RSTMGR_STAT_FPGAHSTMO_MSB 27
#define | ALT_RSTMGR_STAT_FPGAHSTMO_WIDTH 1
#define | ALT_RSTMGR_STAT_FPGAHSTMO_SET_MSK 0x08000000
#define | ALT_RSTMGR_STAT_FPGAHSTMO_CLR_MSK 0xf7ffffff
#define | ALT_RSTMGR_STAT_FPGAHSTMO_RESET 0x0
#define | ALT_RSTMGR_STAT_FPGAHSTMO_GET(value) (((value) & 0x08000000) >> 27)
#define | ALT_RSTMGR_STAT_FPGAHSTMO_SET(value) (((value) << 27) & 0x08000000)
#define | ALT_RSTMGR_STAT_ETRSTALLTMO_LSB 28
#define | ALT_RSTMGR_STAT_ETRSTALLTMO_MSB 28
#define | ALT_RSTMGR_STAT_ETRSTALLTMO_WIDTH 1
#define | ALT_RSTMGR_STAT_ETRSTALLTMO_SET_MSK 0x10000000
#define | ALT_RSTMGR_STAT_ETRSTALLTMO_CLR_MSK 0xefffffff
#define | ALT_RSTMGR_STAT_ETRSTALLTMO_RESET 0x0
#define | ALT_RSTMGR_STAT_ETRSTALLTMO_GET(value) (((value) & 0x10000000) >> 28)
#define | ALT_RSTMGR_STAT_ETRSTALLTMO_SET(value) (((value) << 28) & 0x10000000)
#define | ALT_RSTMGR_STAT_OFST 0x0
#define | ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB 0
#define | ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB 0
#define | ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH 1
#define | ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK 0x00000001
#define | ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK 0xfffffffe
#define | ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET 0x0
#define | ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB 1
#define | ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB 1
#define | ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH 1
#define | ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK 0x00000002
#define | ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK 0xfffffffd
#define | ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET 0x0
#define | ALT_RSTMGR_CTL_SWWARMRSTREQ_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_RSTMGR_CTL_SWWARMRSTREQ_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_RSTMGR_CTL_SDRSELFREFEN_LSB 4
#define | ALT_RSTMGR_CTL_SDRSELFREFEN_MSB 4
#define | ALT_RSTMGR_CTL_SDRSELFREFEN_WIDTH 1
#define | ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK 0x00000010
#define | ALT_RSTMGR_CTL_SDRSELFREFEN_CLR_MSK 0xffffffef
#define | ALT_RSTMGR_CTL_SDRSELFREFEN_RESET 0x0
#define | ALT_RSTMGR_CTL_SDRSELFREFEN_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_RSTMGR_CTL_SDRSELFREFEN_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_RSTMGR_CTL_SDRSELFREFREQ_LSB 5
#define | ALT_RSTMGR_CTL_SDRSELFREFREQ_MSB 5
#define | ALT_RSTMGR_CTL_SDRSELFREFREQ_WIDTH 1
#define | ALT_RSTMGR_CTL_SDRSELFREFREQ_SET_MSK 0x00000020
#define | ALT_RSTMGR_CTL_SDRSELFREFREQ_CLR_MSK 0xffffffdf
#define | ALT_RSTMGR_CTL_SDRSELFREFREQ_RESET 0x0
#define | ALT_RSTMGR_CTL_SDRSELFREFREQ_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_RSTMGR_CTL_SDRSELFREFREQ_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_RSTMGR_CTL_SDRSELFREQACK_LSB 6
#define | ALT_RSTMGR_CTL_SDRSELFREQACK_MSB 6
#define | ALT_RSTMGR_CTL_SDRSELFREQACK_WIDTH 1
#define | ALT_RSTMGR_CTL_SDRSELFREQACK_SET_MSK 0x00000040
#define | ALT_RSTMGR_CTL_SDRSELFREQACK_CLR_MSK 0xffffffbf
#define | ALT_RSTMGR_CTL_SDRSELFREQACK_RESET 0x0
#define | ALT_RSTMGR_CTL_SDRSELFREQACK_GET(value) (((value) & 0x00000040) >> 6)
#define | ALT_RSTMGR_CTL_SDRSELFREQACK_SET(value) (((value) << 6) & 0x00000040)
#define | ALT_RSTMGR_CTL_FPGAMGRHSEN_LSB 8
#define | ALT_RSTMGR_CTL_FPGAMGRHSEN_MSB 8
#define | ALT_RSTMGR_CTL_FPGAMGRHSEN_WIDTH 1
#define | ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK 0x00000100
#define | ALT_RSTMGR_CTL_FPGAMGRHSEN_CLR_MSK 0xfffffeff
#define | ALT_RSTMGR_CTL_FPGAMGRHSEN_RESET 0x0
#define | ALT_RSTMGR_CTL_FPGAMGRHSEN_GET(value) (((value) & 0x00000100) >> 8)
#define | ALT_RSTMGR_CTL_FPGAMGRHSEN_SET(value) (((value) << 8) & 0x00000100)
#define | ALT_RSTMGR_CTL_FPGAMGRHSREQ_LSB 9
#define | ALT_RSTMGR_CTL_FPGAMGRHSREQ_MSB 9
#define | ALT_RSTMGR_CTL_FPGAMGRHSREQ_WIDTH 1
#define | ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET_MSK 0x00000200
#define | ALT_RSTMGR_CTL_FPGAMGRHSREQ_CLR_MSK 0xfffffdff
#define | ALT_RSTMGR_CTL_FPGAMGRHSREQ_RESET 0x0
#define | ALT_RSTMGR_CTL_FPGAMGRHSREQ_GET(value) (((value) & 0x00000200) >> 9)
#define | ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET(value) (((value) << 9) & 0x00000200)
#define | ALT_RSTMGR_CTL_FPGAMGRHSACK_LSB 10
#define | ALT_RSTMGR_CTL_FPGAMGRHSACK_MSB 10
#define | ALT_RSTMGR_CTL_FPGAMGRHSACK_WIDTH 1
#define | ALT_RSTMGR_CTL_FPGAMGRHSACK_SET_MSK 0x00000400
#define | ALT_RSTMGR_CTL_FPGAMGRHSACK_CLR_MSK 0xfffffbff
#define | ALT_RSTMGR_CTL_FPGAMGRHSACK_RESET 0x0
#define | ALT_RSTMGR_CTL_FPGAMGRHSACK_GET(value) (((value) & 0x00000400) >> 10)
#define | ALT_RSTMGR_CTL_FPGAMGRHSACK_SET(value) (((value) << 10) & 0x00000400)
#define | ALT_RSTMGR_CTL_SCANMGRHSEN_LSB 12
#define | ALT_RSTMGR_CTL_SCANMGRHSEN_MSB 12
#define | ALT_RSTMGR_CTL_SCANMGRHSEN_WIDTH 1
#define | ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK 0x00001000
#define | ALT_RSTMGR_CTL_SCANMGRHSEN_CLR_MSK 0xffffefff
#define | ALT_RSTMGR_CTL_SCANMGRHSEN_RESET 0x0
#define | ALT_RSTMGR_CTL_SCANMGRHSEN_GET(value) (((value) & 0x00001000) >> 12)
#define | ALT_RSTMGR_CTL_SCANMGRHSEN_SET(value) (((value) << 12) & 0x00001000)
#define | ALT_RSTMGR_CTL_SCANMGRHSREQ_LSB 13
#define | ALT_RSTMGR_CTL_SCANMGRHSREQ_MSB 13
#define | ALT_RSTMGR_CTL_SCANMGRHSREQ_WIDTH 1
#define | ALT_RSTMGR_CTL_SCANMGRHSREQ_SET_MSK 0x00002000
#define | ALT_RSTMGR_CTL_SCANMGRHSREQ_CLR_MSK 0xffffdfff
#define | ALT_RSTMGR_CTL_SCANMGRHSREQ_RESET 0x0
#define | ALT_RSTMGR_CTL_SCANMGRHSREQ_GET(value) (((value) & 0x00002000) >> 13)
#define | ALT_RSTMGR_CTL_SCANMGRHSREQ_SET(value) (((value) << 13) & 0x00002000)
#define | ALT_RSTMGR_CTL_SCANMGRHSACK_LSB 14
#define | ALT_RSTMGR_CTL_SCANMGRHSACK_MSB 14
#define | ALT_RSTMGR_CTL_SCANMGRHSACK_WIDTH 1
#define | ALT_RSTMGR_CTL_SCANMGRHSACK_SET_MSK 0x00004000
#define | ALT_RSTMGR_CTL_SCANMGRHSACK_CLR_MSK 0xffffbfff
#define | ALT_RSTMGR_CTL_SCANMGRHSACK_RESET 0x0
#define | ALT_RSTMGR_CTL_SCANMGRHSACK_GET(value) (((value) & 0x00004000) >> 14)
#define | ALT_RSTMGR_CTL_SCANMGRHSACK_SET(value) (((value) << 14) & 0x00004000)
#define | ALT_RSTMGR_CTL_FPGAHSEN_LSB 16
#define | ALT_RSTMGR_CTL_FPGAHSEN_MSB 16
#define | ALT_RSTMGR_CTL_FPGAHSEN_WIDTH 1
#define | ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK 0x00010000
#define | ALT_RSTMGR_CTL_FPGAHSEN_CLR_MSK 0xfffeffff
#define | ALT_RSTMGR_CTL_FPGAHSEN_RESET 0x0
#define | ALT_RSTMGR_CTL_FPGAHSEN_GET(value) (((value) & 0x00010000) >> 16)
#define | ALT_RSTMGR_CTL_FPGAHSEN_SET(value) (((value) << 16) & 0x00010000)
#define | ALT_RSTMGR_CTL_FPGAHSREQ_LSB 17
#define | ALT_RSTMGR_CTL_FPGAHSREQ_MSB 17
#define | ALT_RSTMGR_CTL_FPGAHSREQ_WIDTH 1
#define | ALT_RSTMGR_CTL_FPGAHSREQ_SET_MSK 0x00020000
#define | ALT_RSTMGR_CTL_FPGAHSREQ_CLR_MSK 0xfffdffff
#define | ALT_RSTMGR_CTL_FPGAHSREQ_RESET 0x0
#define | ALT_RSTMGR_CTL_FPGAHSREQ_GET(value) (((value) & 0x00020000) >> 17)
#define | ALT_RSTMGR_CTL_FPGAHSREQ_SET(value) (((value) << 17) & 0x00020000)
#define | ALT_RSTMGR_CTL_FPGAHSACK_LSB 18
#define | ALT_RSTMGR_CTL_FPGAHSACK_MSB 18
#define | ALT_RSTMGR_CTL_FPGAHSACK_WIDTH 1
#define | ALT_RSTMGR_CTL_FPGAHSACK_SET_MSK 0x00040000
#define | ALT_RSTMGR_CTL_FPGAHSACK_CLR_MSK 0xfffbffff
#define | ALT_RSTMGR_CTL_FPGAHSACK_RESET 0x0
#define | ALT_RSTMGR_CTL_FPGAHSACK_GET(value) (((value) & 0x00040000) >> 18)
#define | ALT_RSTMGR_CTL_FPGAHSACK_SET(value) (((value) << 18) & 0x00040000)
#define | ALT_RSTMGR_CTL_ETRSTALLEN_LSB 20
#define | ALT_RSTMGR_CTL_ETRSTALLEN_MSB 20
#define | ALT_RSTMGR_CTL_ETRSTALLEN_WIDTH 1
#define | ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK 0x00100000
#define | ALT_RSTMGR_CTL_ETRSTALLEN_CLR_MSK 0xffefffff
#define | ALT_RSTMGR_CTL_ETRSTALLEN_RESET 0x1
#define | ALT_RSTMGR_CTL_ETRSTALLEN_GET(value) (((value) & 0x00100000) >> 20)
#define | ALT_RSTMGR_CTL_ETRSTALLEN_SET(value) (((value) << 20) & 0x00100000)
#define | ALT_RSTMGR_CTL_ETRSTALLREQ_LSB 21
#define | ALT_RSTMGR_CTL_ETRSTALLREQ_MSB 21
#define | ALT_RSTMGR_CTL_ETRSTALLREQ_WIDTH 1
#define | ALT_RSTMGR_CTL_ETRSTALLREQ_SET_MSK 0x00200000
#define | ALT_RSTMGR_CTL_ETRSTALLREQ_CLR_MSK 0xffdfffff
#define | ALT_RSTMGR_CTL_ETRSTALLREQ_RESET 0x0
#define | ALT_RSTMGR_CTL_ETRSTALLREQ_GET(value) (((value) & 0x00200000) >> 21)
#define | ALT_RSTMGR_CTL_ETRSTALLREQ_SET(value) (((value) << 21) & 0x00200000)
#define | ALT_RSTMGR_CTL_ETRSTALLACK_LSB 22
#define | ALT_RSTMGR_CTL_ETRSTALLACK_MSB 22
#define | ALT_RSTMGR_CTL_ETRSTALLACK_WIDTH 1
#define | ALT_RSTMGR_CTL_ETRSTALLACK_SET_MSK 0x00400000
#define | ALT_RSTMGR_CTL_ETRSTALLACK_CLR_MSK 0xffbfffff
#define | ALT_RSTMGR_CTL_ETRSTALLACK_RESET 0x0
#define | ALT_RSTMGR_CTL_ETRSTALLACK_GET(value) (((value) & 0x00400000) >> 22)
#define | ALT_RSTMGR_CTL_ETRSTALLACK_SET(value) (((value) << 22) & 0x00400000)
#define | ALT_RSTMGR_CTL_ETRSTALLWARMRST_LSB 23
#define | ALT_RSTMGR_CTL_ETRSTALLWARMRST_MSB 23
#define | ALT_RSTMGR_CTL_ETRSTALLWARMRST_WIDTH 1
#define | ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET_MSK 0x00800000
#define | ALT_RSTMGR_CTL_ETRSTALLWARMRST_CLR_MSK 0xff7fffff
#define | ALT_RSTMGR_CTL_ETRSTALLWARMRST_RESET 0x0
#define | ALT_RSTMGR_CTL_ETRSTALLWARMRST_GET(value) (((value) & 0x00800000) >> 23)
#define | ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET(value) (((value) << 23) & 0x00800000)
#define | ALT_RSTMGR_CTL_OFST 0x4
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB 0
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB 7
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH 8
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK 0x000000ff
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK 0xffffff00
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET 0x80
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value) (((value) & 0x000000ff) >> 0)
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value) (((value) << 0) & 0x000000ff)
#define | ALT_RSTMGR_COUNTS_NRSTCNT_LSB 8
#define | ALT_RSTMGR_COUNTS_NRSTCNT_MSB 27
#define | ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH 20
#define | ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK 0x0fffff00
#define | ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK 0xf00000ff
#define | ALT_RSTMGR_COUNTS_NRSTCNT_RESET 0x800
#define | ALT_RSTMGR_COUNTS_NRSTCNT_GET(value) (((value) & 0x0fffff00) >> 8)
#define | ALT_RSTMGR_COUNTS_NRSTCNT_SET(value) (((value) << 8) & 0x0fffff00)
#define | ALT_RSTMGR_COUNTS_OFST 0x8
#define | ALT_RSTMGR_MPUMODRST_CPU0_LSB 0
#define | ALT_RSTMGR_MPUMODRST_CPU0_MSB 0
#define | ALT_RSTMGR_MPUMODRST_CPU0_WIDTH 1
#define | ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK 0x00000001
#define | ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK 0xfffffffe
#define | ALT_RSTMGR_MPUMODRST_CPU0_RESET 0x0
#define | ALT_RSTMGR_MPUMODRST_CPU0_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_RSTMGR_MPUMODRST_CPU0_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_RSTMGR_MPUMODRST_CPU1_LSB 1
#define | ALT_RSTMGR_MPUMODRST_CPU1_MSB 1
#define | ALT_RSTMGR_MPUMODRST_CPU1_WIDTH 1
#define | ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK 0x00000002
#define | ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK 0xfffffffd
#define | ALT_RSTMGR_MPUMODRST_CPU1_RESET 0x1
#define | ALT_RSTMGR_MPUMODRST_CPU1_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_RSTMGR_MPUMODRST_CPU1_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_RSTMGR_MPUMODRST_WDS_LSB 2
#define | ALT_RSTMGR_MPUMODRST_WDS_MSB 2
#define | ALT_RSTMGR_MPUMODRST_WDS_WIDTH 1
#define | ALT_RSTMGR_MPUMODRST_WDS_SET_MSK 0x00000004
#define | ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK 0xfffffffb
#define | ALT_RSTMGR_MPUMODRST_WDS_RESET 0x0
#define | ALT_RSTMGR_MPUMODRST_WDS_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_RSTMGR_MPUMODRST_WDS_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_RSTMGR_MPUMODRST_SCUPER_LSB 3
#define | ALT_RSTMGR_MPUMODRST_SCUPER_MSB 3
#define | ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH 1
#define | ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK 0x00000008
#define | ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK 0xfffffff7
#define | ALT_RSTMGR_MPUMODRST_SCUPER_RESET 0x0
#define | ALT_RSTMGR_MPUMODRST_SCUPER_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_RSTMGR_MPUMODRST_SCUPER_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_RSTMGR_MPUMODRST_L2_LSB 4
#define | ALT_RSTMGR_MPUMODRST_L2_MSB 4
#define | ALT_RSTMGR_MPUMODRST_L2_WIDTH 1
#define | ALT_RSTMGR_MPUMODRST_L2_SET_MSK 0x00000010
#define | ALT_RSTMGR_MPUMODRST_L2_CLR_MSK 0xffffffef
#define | ALT_RSTMGR_MPUMODRST_L2_RESET 0x0
#define | ALT_RSTMGR_MPUMODRST_L2_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_RSTMGR_MPUMODRST_L2_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_RSTMGR_MPUMODRST_OFST 0x10
#define | ALT_RSTMGR_PERMODRST_EMAC0_LSB 0
#define | ALT_RSTMGR_PERMODRST_EMAC0_MSB 0
#define | ALT_RSTMGR_PERMODRST_EMAC0_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_EMAC0_SET_MSK 0x00000001
#define | ALT_RSTMGR_PERMODRST_EMAC0_CLR_MSK 0xfffffffe
#define | ALT_RSTMGR_PERMODRST_EMAC0_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_RSTMGR_PERMODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_RSTMGR_PERMODRST_EMAC1_LSB 1
#define | ALT_RSTMGR_PERMODRST_EMAC1_MSB 1
#define | ALT_RSTMGR_PERMODRST_EMAC1_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_EMAC1_SET_MSK 0x00000002
#define | ALT_RSTMGR_PERMODRST_EMAC1_CLR_MSK 0xfffffffd
#define | ALT_RSTMGR_PERMODRST_EMAC1_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_RSTMGR_PERMODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_RSTMGR_PERMODRST_USB0_LSB 2
#define | ALT_RSTMGR_PERMODRST_USB0_MSB 2
#define | ALT_RSTMGR_PERMODRST_USB0_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_USB0_SET_MSK 0x00000004
#define | ALT_RSTMGR_PERMODRST_USB0_CLR_MSK 0xfffffffb
#define | ALT_RSTMGR_PERMODRST_USB0_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_USB0_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_RSTMGR_PERMODRST_USB0_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_RSTMGR_PERMODRST_USB1_LSB 3
#define | ALT_RSTMGR_PERMODRST_USB1_MSB 3
#define | ALT_RSTMGR_PERMODRST_USB1_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_USB1_SET_MSK 0x00000008
#define | ALT_RSTMGR_PERMODRST_USB1_CLR_MSK 0xfffffff7
#define | ALT_RSTMGR_PERMODRST_USB1_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_USB1_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_RSTMGR_PERMODRST_USB1_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_RSTMGR_PERMODRST_NAND_LSB 4
#define | ALT_RSTMGR_PERMODRST_NAND_MSB 4
#define | ALT_RSTMGR_PERMODRST_NAND_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_NAND_SET_MSK 0x00000010
#define | ALT_RSTMGR_PERMODRST_NAND_CLR_MSK 0xffffffef
#define | ALT_RSTMGR_PERMODRST_NAND_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_NAND_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_RSTMGR_PERMODRST_NAND_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_RSTMGR_PERMODRST_QSPI_LSB 5
#define | ALT_RSTMGR_PERMODRST_QSPI_MSB 5
#define | ALT_RSTMGR_PERMODRST_QSPI_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_QSPI_SET_MSK 0x00000020
#define | ALT_RSTMGR_PERMODRST_QSPI_CLR_MSK 0xffffffdf
#define | ALT_RSTMGR_PERMODRST_QSPI_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_QSPI_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_RSTMGR_PERMODRST_QSPI_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_RSTMGR_PERMODRST_L4WD0_LSB 6
#define | ALT_RSTMGR_PERMODRST_L4WD0_MSB 6
#define | ALT_RSTMGR_PERMODRST_L4WD0_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_L4WD0_SET_MSK 0x00000040
#define | ALT_RSTMGR_PERMODRST_L4WD0_CLR_MSK 0xffffffbf
#define | ALT_RSTMGR_PERMODRST_L4WD0_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_L4WD0_GET(value) (((value) & 0x00000040) >> 6)
#define | ALT_RSTMGR_PERMODRST_L4WD0_SET(value) (((value) << 6) & 0x00000040)
#define | ALT_RSTMGR_PERMODRST_L4WD1_LSB 7
#define | ALT_RSTMGR_PERMODRST_L4WD1_MSB 7
#define | ALT_RSTMGR_PERMODRST_L4WD1_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_L4WD1_SET_MSK 0x00000080
#define | ALT_RSTMGR_PERMODRST_L4WD1_CLR_MSK 0xffffff7f
#define | ALT_RSTMGR_PERMODRST_L4WD1_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_L4WD1_GET(value) (((value) & 0x00000080) >> 7)
#define | ALT_RSTMGR_PERMODRST_L4WD1_SET(value) (((value) << 7) & 0x00000080)
#define | ALT_RSTMGR_PERMODRST_OSC1TMR0_LSB 8
#define | ALT_RSTMGR_PERMODRST_OSC1TMR0_MSB 8
#define | ALT_RSTMGR_PERMODRST_OSC1TMR0_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_OSC1TMR0_SET_MSK 0x00000100
#define | ALT_RSTMGR_PERMODRST_OSC1TMR0_CLR_MSK 0xfffffeff
#define | ALT_RSTMGR_PERMODRST_OSC1TMR0_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_OSC1TMR0_GET(value) (((value) & 0x00000100) >> 8)
#define | ALT_RSTMGR_PERMODRST_OSC1TMR0_SET(value) (((value) << 8) & 0x00000100)
#define | ALT_RSTMGR_PERMODRST_OSC1TMR1_LSB 9
#define | ALT_RSTMGR_PERMODRST_OSC1TMR1_MSB 9
#define | ALT_RSTMGR_PERMODRST_OSC1TMR1_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_OSC1TMR1_SET_MSK 0x00000200
#define | ALT_RSTMGR_PERMODRST_OSC1TMR1_CLR_MSK 0xfffffdff
#define | ALT_RSTMGR_PERMODRST_OSC1TMR1_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_OSC1TMR1_GET(value) (((value) & 0x00000200) >> 9)
#define | ALT_RSTMGR_PERMODRST_OSC1TMR1_SET(value) (((value) << 9) & 0x00000200)
#define | ALT_RSTMGR_PERMODRST_SPTMR0_LSB 10
#define | ALT_RSTMGR_PERMODRST_SPTMR0_MSB 10
#define | ALT_RSTMGR_PERMODRST_SPTMR0_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_SPTMR0_SET_MSK 0x00000400
#define | ALT_RSTMGR_PERMODRST_SPTMR0_CLR_MSK 0xfffffbff
#define | ALT_RSTMGR_PERMODRST_SPTMR0_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_SPTMR0_GET(value) (((value) & 0x00000400) >> 10)
#define | ALT_RSTMGR_PERMODRST_SPTMR0_SET(value) (((value) << 10) & 0x00000400)
#define | ALT_RSTMGR_PERMODRST_SPTMR1_LSB 11
#define | ALT_RSTMGR_PERMODRST_SPTMR1_MSB 11
#define | ALT_RSTMGR_PERMODRST_SPTMR1_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_SPTMR1_SET_MSK 0x00000800
#define | ALT_RSTMGR_PERMODRST_SPTMR1_CLR_MSK 0xfffff7ff
#define | ALT_RSTMGR_PERMODRST_SPTMR1_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_SPTMR1_GET(value) (((value) & 0x00000800) >> 11)
#define | ALT_RSTMGR_PERMODRST_SPTMR1_SET(value) (((value) << 11) & 0x00000800)
#define | ALT_RSTMGR_PERMODRST_I2C0_LSB 12
#define | ALT_RSTMGR_PERMODRST_I2C0_MSB 12
#define | ALT_RSTMGR_PERMODRST_I2C0_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_I2C0_SET_MSK 0x00001000
#define | ALT_RSTMGR_PERMODRST_I2C0_CLR_MSK 0xffffefff
#define | ALT_RSTMGR_PERMODRST_I2C0_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_I2C0_GET(value) (((value) & 0x00001000) >> 12)
#define | ALT_RSTMGR_PERMODRST_I2C0_SET(value) (((value) << 12) & 0x00001000)
#define | ALT_RSTMGR_PERMODRST_I2C1_LSB 13
#define | ALT_RSTMGR_PERMODRST_I2C1_MSB 13
#define | ALT_RSTMGR_PERMODRST_I2C1_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_I2C1_SET_MSK 0x00002000
#define | ALT_RSTMGR_PERMODRST_I2C1_CLR_MSK 0xffffdfff
#define | ALT_RSTMGR_PERMODRST_I2C1_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_I2C1_GET(value) (((value) & 0x00002000) >> 13)
#define | ALT_RSTMGR_PERMODRST_I2C1_SET(value) (((value) << 13) & 0x00002000)
#define | ALT_RSTMGR_PERMODRST_I2C2_LSB 14
#define | ALT_RSTMGR_PERMODRST_I2C2_MSB 14
#define | ALT_RSTMGR_PERMODRST_I2C2_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_I2C2_SET_MSK 0x00004000
#define | ALT_RSTMGR_PERMODRST_I2C2_CLR_MSK 0xffffbfff
#define | ALT_RSTMGR_PERMODRST_I2C2_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_I2C2_GET(value) (((value) & 0x00004000) >> 14)
#define | ALT_RSTMGR_PERMODRST_I2C2_SET(value) (((value) << 14) & 0x00004000)
#define | ALT_RSTMGR_PERMODRST_I2C3_LSB 15
#define | ALT_RSTMGR_PERMODRST_I2C3_MSB 15
#define | ALT_RSTMGR_PERMODRST_I2C3_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_I2C3_SET_MSK 0x00008000
#define | ALT_RSTMGR_PERMODRST_I2C3_CLR_MSK 0xffff7fff
#define | ALT_RSTMGR_PERMODRST_I2C3_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_I2C3_GET(value) (((value) & 0x00008000) >> 15)
#define | ALT_RSTMGR_PERMODRST_I2C3_SET(value) (((value) << 15) & 0x00008000)
#define | ALT_RSTMGR_PERMODRST_UART0_LSB 16
#define | ALT_RSTMGR_PERMODRST_UART0_MSB 16
#define | ALT_RSTMGR_PERMODRST_UART0_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_UART0_SET_MSK 0x00010000
#define | ALT_RSTMGR_PERMODRST_UART0_CLR_MSK 0xfffeffff
#define | ALT_RSTMGR_PERMODRST_UART0_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_UART0_GET(value) (((value) & 0x00010000) >> 16)
#define | ALT_RSTMGR_PERMODRST_UART0_SET(value) (((value) << 16) & 0x00010000)
#define | ALT_RSTMGR_PERMODRST_UART1_LSB 17
#define | ALT_RSTMGR_PERMODRST_UART1_MSB 17
#define | ALT_RSTMGR_PERMODRST_UART1_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_UART1_SET_MSK 0x00020000
#define | ALT_RSTMGR_PERMODRST_UART1_CLR_MSK 0xfffdffff
#define | ALT_RSTMGR_PERMODRST_UART1_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_UART1_GET(value) (((value) & 0x00020000) >> 17)
#define | ALT_RSTMGR_PERMODRST_UART1_SET(value) (((value) << 17) & 0x00020000)
#define | ALT_RSTMGR_PERMODRST_SPIM0_LSB 18
#define | ALT_RSTMGR_PERMODRST_SPIM0_MSB 18
#define | ALT_RSTMGR_PERMODRST_SPIM0_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_SPIM0_SET_MSK 0x00040000
#define | ALT_RSTMGR_PERMODRST_SPIM0_CLR_MSK 0xfffbffff
#define | ALT_RSTMGR_PERMODRST_SPIM0_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_SPIM0_GET(value) (((value) & 0x00040000) >> 18)
#define | ALT_RSTMGR_PERMODRST_SPIM0_SET(value) (((value) << 18) & 0x00040000)
#define | ALT_RSTMGR_PERMODRST_SPIM1_LSB 19
#define | ALT_RSTMGR_PERMODRST_SPIM1_MSB 19
#define | ALT_RSTMGR_PERMODRST_SPIM1_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_SPIM1_SET_MSK 0x00080000
#define | ALT_RSTMGR_PERMODRST_SPIM1_CLR_MSK 0xfff7ffff
#define | ALT_RSTMGR_PERMODRST_SPIM1_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_SPIM1_GET(value) (((value) & 0x00080000) >> 19)
#define | ALT_RSTMGR_PERMODRST_SPIM1_SET(value) (((value) << 19) & 0x00080000)
#define | ALT_RSTMGR_PERMODRST_SPIS0_LSB 20
#define | ALT_RSTMGR_PERMODRST_SPIS0_MSB 20
#define | ALT_RSTMGR_PERMODRST_SPIS0_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_SPIS0_SET_MSK 0x00100000
#define | ALT_RSTMGR_PERMODRST_SPIS0_CLR_MSK 0xffefffff
#define | ALT_RSTMGR_PERMODRST_SPIS0_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_SPIS0_GET(value) (((value) & 0x00100000) >> 20)
#define | ALT_RSTMGR_PERMODRST_SPIS0_SET(value) (((value) << 20) & 0x00100000)
#define | ALT_RSTMGR_PERMODRST_SPIS1_LSB 21
#define | ALT_RSTMGR_PERMODRST_SPIS1_MSB 21
#define | ALT_RSTMGR_PERMODRST_SPIS1_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_SPIS1_SET_MSK 0x00200000
#define | ALT_RSTMGR_PERMODRST_SPIS1_CLR_MSK 0xffdfffff
#define | ALT_RSTMGR_PERMODRST_SPIS1_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_SPIS1_GET(value) (((value) & 0x00200000) >> 21)
#define | ALT_RSTMGR_PERMODRST_SPIS1_SET(value) (((value) << 21) & 0x00200000)
#define | ALT_RSTMGR_PERMODRST_SDMMC_LSB 22
#define | ALT_RSTMGR_PERMODRST_SDMMC_MSB 22
#define | ALT_RSTMGR_PERMODRST_SDMMC_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_SDMMC_SET_MSK 0x00400000
#define | ALT_RSTMGR_PERMODRST_SDMMC_CLR_MSK 0xffbfffff
#define | ALT_RSTMGR_PERMODRST_SDMMC_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_SDMMC_GET(value) (((value) & 0x00400000) >> 22)
#define | ALT_RSTMGR_PERMODRST_SDMMC_SET(value) (((value) << 22) & 0x00400000)
#define | ALT_RSTMGR_PERMODRST_CAN0_LSB 23
#define | ALT_RSTMGR_PERMODRST_CAN0_MSB 23
#define | ALT_RSTMGR_PERMODRST_CAN0_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_CAN0_SET_MSK 0x00800000
#define | ALT_RSTMGR_PERMODRST_CAN0_CLR_MSK 0xff7fffff
#define | ALT_RSTMGR_PERMODRST_CAN0_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_CAN0_GET(value) (((value) & 0x00800000) >> 23)
#define | ALT_RSTMGR_PERMODRST_CAN0_SET(value) (((value) << 23) & 0x00800000)
#define | ALT_RSTMGR_PERMODRST_CAN1_LSB 24
#define | ALT_RSTMGR_PERMODRST_CAN1_MSB 24
#define | ALT_RSTMGR_PERMODRST_CAN1_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_CAN1_SET_MSK 0x01000000
#define | ALT_RSTMGR_PERMODRST_CAN1_CLR_MSK 0xfeffffff
#define | ALT_RSTMGR_PERMODRST_CAN1_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_CAN1_GET(value) (((value) & 0x01000000) >> 24)
#define | ALT_RSTMGR_PERMODRST_CAN1_SET(value) (((value) << 24) & 0x01000000)
#define | ALT_RSTMGR_PERMODRST_GPIO0_LSB 25
#define | ALT_RSTMGR_PERMODRST_GPIO0_MSB 25
#define | ALT_RSTMGR_PERMODRST_GPIO0_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK 0x02000000
#define | ALT_RSTMGR_PERMODRST_GPIO0_CLR_MSK 0xfdffffff
#define | ALT_RSTMGR_PERMODRST_GPIO0_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_GPIO0_GET(value) (((value) & 0x02000000) >> 25)
#define | ALT_RSTMGR_PERMODRST_GPIO0_SET(value) (((value) << 25) & 0x02000000)
#define | ALT_RSTMGR_PERMODRST_GPIO1_LSB 26
#define | ALT_RSTMGR_PERMODRST_GPIO1_MSB 26
#define | ALT_RSTMGR_PERMODRST_GPIO1_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK 0x04000000
#define | ALT_RSTMGR_PERMODRST_GPIO1_CLR_MSK 0xfbffffff
#define | ALT_RSTMGR_PERMODRST_GPIO1_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_GPIO1_GET(value) (((value) & 0x04000000) >> 26)
#define | ALT_RSTMGR_PERMODRST_GPIO1_SET(value) (((value) << 26) & 0x04000000)
#define | ALT_RSTMGR_PERMODRST_GPIO2_LSB 27
#define | ALT_RSTMGR_PERMODRST_GPIO2_MSB 27
#define | ALT_RSTMGR_PERMODRST_GPIO2_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK 0x08000000
#define | ALT_RSTMGR_PERMODRST_GPIO2_CLR_MSK 0xf7ffffff
#define | ALT_RSTMGR_PERMODRST_GPIO2_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_GPIO2_GET(value) (((value) & 0x08000000) >> 27)
#define | ALT_RSTMGR_PERMODRST_GPIO2_SET(value) (((value) << 27) & 0x08000000)
#define | ALT_RSTMGR_PERMODRST_DMA_LSB 28
#define | ALT_RSTMGR_PERMODRST_DMA_MSB 28
#define | ALT_RSTMGR_PERMODRST_DMA_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_DMA_SET_MSK 0x10000000
#define | ALT_RSTMGR_PERMODRST_DMA_CLR_MSK 0xefffffff
#define | ALT_RSTMGR_PERMODRST_DMA_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_DMA_GET(value) (((value) & 0x10000000) >> 28)
#define | ALT_RSTMGR_PERMODRST_DMA_SET(value) (((value) << 28) & 0x10000000)
#define | ALT_RSTMGR_PERMODRST_SDR_LSB 29
#define | ALT_RSTMGR_PERMODRST_SDR_MSB 29
#define | ALT_RSTMGR_PERMODRST_SDR_WIDTH 1
#define | ALT_RSTMGR_PERMODRST_SDR_SET_MSK 0x20000000
#define | ALT_RSTMGR_PERMODRST_SDR_CLR_MSK 0xdfffffff
#define | ALT_RSTMGR_PERMODRST_SDR_RESET 0x1
#define | ALT_RSTMGR_PERMODRST_SDR_GET(value) (((value) & 0x20000000) >> 29)
#define | ALT_RSTMGR_PERMODRST_SDR_SET(value) (((value) << 29) & 0x20000000)
#define | ALT_RSTMGR_PERMODRST_OFST 0x14
#define | ALT_RSTMGR_PER2MODRST_DMAIF0_LSB 0
#define | ALT_RSTMGR_PER2MODRST_DMAIF0_MSB 0
#define | ALT_RSTMGR_PER2MODRST_DMAIF0_WIDTH 1
#define | ALT_RSTMGR_PER2MODRST_DMAIF0_SET_MSK 0x00000001
#define | ALT_RSTMGR_PER2MODRST_DMAIF0_CLR_MSK 0xfffffffe
#define | ALT_RSTMGR_PER2MODRST_DMAIF0_RESET 0x1
#define | ALT_RSTMGR_PER2MODRST_DMAIF0_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_RSTMGR_PER2MODRST_DMAIF0_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_RSTMGR_PER2MODRST_DMAIF1_LSB 1
#define | ALT_RSTMGR_PER2MODRST_DMAIF1_MSB 1
#define | ALT_RSTMGR_PER2MODRST_DMAIF1_WIDTH 1
#define | ALT_RSTMGR_PER2MODRST_DMAIF1_SET_MSK 0x00000002
#define | ALT_RSTMGR_PER2MODRST_DMAIF1_CLR_MSK 0xfffffffd
#define | ALT_RSTMGR_PER2MODRST_DMAIF1_RESET 0x1
#define | ALT_RSTMGR_PER2MODRST_DMAIF1_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_RSTMGR_PER2MODRST_DMAIF1_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_RSTMGR_PER2MODRST_DMAIF2_LSB 2
#define | ALT_RSTMGR_PER2MODRST_DMAIF2_MSB 2
#define | ALT_RSTMGR_PER2MODRST_DMAIF2_WIDTH 1
#define | ALT_RSTMGR_PER2MODRST_DMAIF2_SET_MSK 0x00000004
#define | ALT_RSTMGR_PER2MODRST_DMAIF2_CLR_MSK 0xfffffffb
#define | ALT_RSTMGR_PER2MODRST_DMAIF2_RESET 0x1
#define | ALT_RSTMGR_PER2MODRST_DMAIF2_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_RSTMGR_PER2MODRST_DMAIF2_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_RSTMGR_PER2MODRST_DMAIF3_LSB 3
#define | ALT_RSTMGR_PER2MODRST_DMAIF3_MSB 3
#define | ALT_RSTMGR_PER2MODRST_DMAIF3_WIDTH 1
#define | ALT_RSTMGR_PER2MODRST_DMAIF3_SET_MSK 0x00000008
#define | ALT_RSTMGR_PER2MODRST_DMAIF3_CLR_MSK 0xfffffff7
#define | ALT_RSTMGR_PER2MODRST_DMAIF3_RESET 0x1
#define | ALT_RSTMGR_PER2MODRST_DMAIF3_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_RSTMGR_PER2MODRST_DMAIF3_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_RSTMGR_PER2MODRST_DMAIF4_LSB 4
#define | ALT_RSTMGR_PER2MODRST_DMAIF4_MSB 4
#define | ALT_RSTMGR_PER2MODRST_DMAIF4_WIDTH 1
#define | ALT_RSTMGR_PER2MODRST_DMAIF4_SET_MSK 0x00000010
#define | ALT_RSTMGR_PER2MODRST_DMAIF4_CLR_MSK 0xffffffef
#define | ALT_RSTMGR_PER2MODRST_DMAIF4_RESET 0x1
#define | ALT_RSTMGR_PER2MODRST_DMAIF4_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_RSTMGR_PER2MODRST_DMAIF4_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_RSTMGR_PER2MODRST_DMAIF5_LSB 5
#define | ALT_RSTMGR_PER2MODRST_DMAIF5_MSB 5
#define | ALT_RSTMGR_PER2MODRST_DMAIF5_WIDTH 1
#define | ALT_RSTMGR_PER2MODRST_DMAIF5_SET_MSK 0x00000020
#define | ALT_RSTMGR_PER2MODRST_DMAIF5_CLR_MSK 0xffffffdf
#define | ALT_RSTMGR_PER2MODRST_DMAIF5_RESET 0x1
#define | ALT_RSTMGR_PER2MODRST_DMAIF5_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_RSTMGR_PER2MODRST_DMAIF5_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_RSTMGR_PER2MODRST_DMAIF6_LSB 6
#define | ALT_RSTMGR_PER2MODRST_DMAIF6_MSB 6
#define | ALT_RSTMGR_PER2MODRST_DMAIF6_WIDTH 1
#define | ALT_RSTMGR_PER2MODRST_DMAIF6_SET_MSK 0x00000040
#define | ALT_RSTMGR_PER2MODRST_DMAIF6_CLR_MSK 0xffffffbf
#define | ALT_RSTMGR_PER2MODRST_DMAIF6_RESET 0x1
#define | ALT_RSTMGR_PER2MODRST_DMAIF6_GET(value) (((value) & 0x00000040) >> 6)
#define | ALT_RSTMGR_PER2MODRST_DMAIF6_SET(value) (((value) << 6) & 0x00000040)
#define | ALT_RSTMGR_PER2MODRST_DMAIF7_LSB 7
#define | ALT_RSTMGR_PER2MODRST_DMAIF7_MSB 7
#define | ALT_RSTMGR_PER2MODRST_DMAIF7_WIDTH 1
#define | ALT_RSTMGR_PER2MODRST_DMAIF7_SET_MSK 0x00000080
#define | ALT_RSTMGR_PER2MODRST_DMAIF7_CLR_MSK 0xffffff7f
#define | ALT_RSTMGR_PER2MODRST_DMAIF7_RESET 0x1
#define | ALT_RSTMGR_PER2MODRST_DMAIF7_GET(value) (((value) & 0x00000080) >> 7)
#define | ALT_RSTMGR_PER2MODRST_DMAIF7_SET(value) (((value) << 7) & 0x00000080)
#define | ALT_RSTMGR_PER2MODRST_OFST 0x18
#define | ALT_RSTMGR_BRGMODRST_H2F_LSB 0
#define | ALT_RSTMGR_BRGMODRST_H2F_MSB 0
#define | ALT_RSTMGR_BRGMODRST_H2F_WIDTH 1
#define | ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001
#define | ALT_RSTMGR_BRGMODRST_H2F_CLR_MSK 0xfffffffe
#define | ALT_RSTMGR_BRGMODRST_H2F_RESET 0x1
#define | ALT_RSTMGR_BRGMODRST_H2F_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_RSTMGR_BRGMODRST_H2F_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_RSTMGR_BRGMODRST_LWH2F_LSB 1
#define | ALT_RSTMGR_BRGMODRST_LWH2F_MSB 1
#define | ALT_RSTMGR_BRGMODRST_LWH2F_WIDTH 1
#define | ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002
#define | ALT_RSTMGR_BRGMODRST_LWH2F_CLR_MSK 0xfffffffd
#define | ALT_RSTMGR_BRGMODRST_LWH2F_RESET 0x1
#define | ALT_RSTMGR_BRGMODRST_LWH2F_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_RSTMGR_BRGMODRST_LWH2F_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_RSTMGR_BRGMODRST_F2H_LSB 2
#define | ALT_RSTMGR_BRGMODRST_F2H_MSB 2
#define | ALT_RSTMGR_BRGMODRST_F2H_WIDTH 1
#define | ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004
#define | ALT_RSTMGR_BRGMODRST_F2H_CLR_MSK 0xfffffffb
#define | ALT_RSTMGR_BRGMODRST_F2H_RESET 0x1
#define | ALT_RSTMGR_BRGMODRST_F2H_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_RSTMGR_BRGMODRST_F2H_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_RSTMGR_BRGMODRST_OFST 0x1c
#define | ALT_RSTMGR_MISCMODRST_ROM_LSB 0
#define | ALT_RSTMGR_MISCMODRST_ROM_MSB 0
#define | ALT_RSTMGR_MISCMODRST_ROM_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_ROM_SET_MSK 0x00000001
#define | ALT_RSTMGR_MISCMODRST_ROM_CLR_MSK 0xfffffffe
#define | ALT_RSTMGR_MISCMODRST_ROM_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_ROM_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_RSTMGR_MISCMODRST_ROM_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_RSTMGR_MISCMODRST_OCRAM_LSB 1
#define | ALT_RSTMGR_MISCMODRST_OCRAM_MSB 1
#define | ALT_RSTMGR_MISCMODRST_OCRAM_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_OCRAM_SET_MSK 0x00000002
#define | ALT_RSTMGR_MISCMODRST_OCRAM_CLR_MSK 0xfffffffd
#define | ALT_RSTMGR_MISCMODRST_OCRAM_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_RSTMGR_MISCMODRST_OCRAM_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_RSTMGR_MISCMODRST_SYSMGR_LSB 2
#define | ALT_RSTMGR_MISCMODRST_SYSMGR_MSB 2
#define | ALT_RSTMGR_MISCMODRST_SYSMGR_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_SYSMGR_SET_MSK 0x00000004
#define | ALT_RSTMGR_MISCMODRST_SYSMGR_CLR_MSK 0xfffffffb
#define | ALT_RSTMGR_MISCMODRST_SYSMGR_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_SYSMGR_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_RSTMGR_MISCMODRST_SYSMGR_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_LSB 3
#define | ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_MSB 3
#define | ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET_MSK 0x00000008
#define | ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_CLR_MSK 0xfffffff7
#define | ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_RSTMGR_MISCMODRST_FPGAMGR_LSB 4
#define | ALT_RSTMGR_MISCMODRST_FPGAMGR_MSB 4
#define | ALT_RSTMGR_MISCMODRST_FPGAMGR_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_FPGAMGR_SET_MSK 0x00000010
#define | ALT_RSTMGR_MISCMODRST_FPGAMGR_CLR_MSK 0xffffffef
#define | ALT_RSTMGR_MISCMODRST_FPGAMGR_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_FPGAMGR_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_RSTMGR_MISCMODRST_FPGAMGR_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_RSTMGR_MISCMODRST_ACPIDMAP_LSB 5
#define | ALT_RSTMGR_MISCMODRST_ACPIDMAP_MSB 5
#define | ALT_RSTMGR_MISCMODRST_ACPIDMAP_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET_MSK 0x00000020
#define | ALT_RSTMGR_MISCMODRST_ACPIDMAP_CLR_MSK 0xffffffdf
#define | ALT_RSTMGR_MISCMODRST_ACPIDMAP_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_ACPIDMAP_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_RSTMGR_MISCMODRST_S2F_LSB 6
#define | ALT_RSTMGR_MISCMODRST_S2F_MSB 6
#define | ALT_RSTMGR_MISCMODRST_S2F_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_S2F_SET_MSK 0x00000040
#define | ALT_RSTMGR_MISCMODRST_S2F_CLR_MSK 0xffffffbf
#define | ALT_RSTMGR_MISCMODRST_S2F_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_S2F_GET(value) (((value) & 0x00000040) >> 6)
#define | ALT_RSTMGR_MISCMODRST_S2F_SET(value) (((value) << 6) & 0x00000040)
#define | ALT_RSTMGR_MISCMODRST_S2FCOLD_LSB 7
#define | ALT_RSTMGR_MISCMODRST_S2FCOLD_MSB 7
#define | ALT_RSTMGR_MISCMODRST_S2FCOLD_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_S2FCOLD_SET_MSK 0x00000080
#define | ALT_RSTMGR_MISCMODRST_S2FCOLD_CLR_MSK 0xffffff7f
#define | ALT_RSTMGR_MISCMODRST_S2FCOLD_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_S2FCOLD_GET(value) (((value) & 0x00000080) >> 7)
#define | ALT_RSTMGR_MISCMODRST_S2FCOLD_SET(value) (((value) << 7) & 0x00000080)
#define | ALT_RSTMGR_MISCMODRST_NRSTPIN_LSB 8
#define | ALT_RSTMGR_MISCMODRST_NRSTPIN_MSB 8
#define | ALT_RSTMGR_MISCMODRST_NRSTPIN_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_NRSTPIN_SET_MSK 0x00000100
#define | ALT_RSTMGR_MISCMODRST_NRSTPIN_CLR_MSK 0xfffffeff
#define | ALT_RSTMGR_MISCMODRST_NRSTPIN_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_NRSTPIN_GET(value) (((value) & 0x00000100) >> 8)
#define | ALT_RSTMGR_MISCMODRST_NRSTPIN_SET(value) (((value) << 8) & 0x00000100)
#define | ALT_RSTMGR_MISCMODRST_TSCOLD_LSB 9
#define | ALT_RSTMGR_MISCMODRST_TSCOLD_MSB 9
#define | ALT_RSTMGR_MISCMODRST_TSCOLD_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_TSCOLD_SET_MSK 0x00000200
#define | ALT_RSTMGR_MISCMODRST_TSCOLD_CLR_MSK 0xfffffdff
#define | ALT_RSTMGR_MISCMODRST_TSCOLD_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_TSCOLD_GET(value) (((value) & 0x00000200) >> 9)
#define | ALT_RSTMGR_MISCMODRST_TSCOLD_SET(value) (((value) << 9) & 0x00000200)
#define | ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_LSB 10
#define | ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_MSB 10
#define | ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET_MSK 0x00000400
#define | ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_CLR_MSK 0xfffffbff
#define | ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_GET(value) (((value) & 0x00000400) >> 10)
#define | ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET(value) (((value) << 10) & 0x00000400)
#define | ALT_RSTMGR_MISCMODRST_SCANMGR_LSB 11
#define | ALT_RSTMGR_MISCMODRST_SCANMGR_MSB 11
#define | ALT_RSTMGR_MISCMODRST_SCANMGR_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_SCANMGR_SET_MSK 0x00000800
#define | ALT_RSTMGR_MISCMODRST_SCANMGR_CLR_MSK 0xfffff7ff
#define | ALT_RSTMGR_MISCMODRST_SCANMGR_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_SCANMGR_GET(value) (((value) & 0x00000800) >> 11)
#define | ALT_RSTMGR_MISCMODRST_SCANMGR_SET(value) (((value) << 11) & 0x00000800)
#define | ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_LSB 12
#define | ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_MSB 12
#define | ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET_MSK 0x00001000
#define | ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_CLR_MSK 0xffffefff
#define | ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_GET(value) (((value) & 0x00001000) >> 12)
#define | ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET(value) (((value) << 12) & 0x00001000)
#define | ALT_RSTMGR_MISCMODRST_SYSDBG_LSB 13
#define | ALT_RSTMGR_MISCMODRST_SYSDBG_MSB 13
#define | ALT_RSTMGR_MISCMODRST_SYSDBG_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_SYSDBG_SET_MSK 0x00002000
#define | ALT_RSTMGR_MISCMODRST_SYSDBG_CLR_MSK 0xffffdfff
#define | ALT_RSTMGR_MISCMODRST_SYSDBG_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_SYSDBG_GET(value) (((value) & 0x00002000) >> 13)
#define | ALT_RSTMGR_MISCMODRST_SYSDBG_SET(value) (((value) << 13) & 0x00002000)
#define | ALT_RSTMGR_MISCMODRST_DBG_LSB 14
#define | ALT_RSTMGR_MISCMODRST_DBG_MSB 14
#define | ALT_RSTMGR_MISCMODRST_DBG_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_DBG_SET_MSK 0x00004000
#define | ALT_RSTMGR_MISCMODRST_DBG_CLR_MSK 0xffffbfff
#define | ALT_RSTMGR_MISCMODRST_DBG_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_DBG_GET(value) (((value) & 0x00004000) >> 14)
#define | ALT_RSTMGR_MISCMODRST_DBG_SET(value) (((value) << 14) & 0x00004000)
#define | ALT_RSTMGR_MISCMODRST_TAPCOLD_LSB 15
#define | ALT_RSTMGR_MISCMODRST_TAPCOLD_MSB 15
#define | ALT_RSTMGR_MISCMODRST_TAPCOLD_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_TAPCOLD_SET_MSK 0x00008000
#define | ALT_RSTMGR_MISCMODRST_TAPCOLD_CLR_MSK 0xffff7fff
#define | ALT_RSTMGR_MISCMODRST_TAPCOLD_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_TAPCOLD_GET(value) (((value) & 0x00008000) >> 15)
#define | ALT_RSTMGR_MISCMODRST_TAPCOLD_SET(value) (((value) << 15) & 0x00008000)
#define | ALT_RSTMGR_MISCMODRST_SDRCOLD_LSB 16
#define | ALT_RSTMGR_MISCMODRST_SDRCOLD_MSB 16
#define | ALT_RSTMGR_MISCMODRST_SDRCOLD_WIDTH 1
#define | ALT_RSTMGR_MISCMODRST_SDRCOLD_SET_MSK 0x00010000
#define | ALT_RSTMGR_MISCMODRST_SDRCOLD_CLR_MSK 0xfffeffff
#define | ALT_RSTMGR_MISCMODRST_SDRCOLD_RESET 0x0
#define | ALT_RSTMGR_MISCMODRST_SDRCOLD_GET(value) (((value) & 0x00010000) >> 16)
#define | ALT_RSTMGR_MISCMODRST_SDRCOLD_SET(value) (((value) << 16) & 0x00010000)
#define | ALT_RSTMGR_MISCMODRST_OFST 0x20

## Typedefs
typedef volatile struct ALT_RSTMGR_STAT_s | ALT_RSTMGR_STAT_t
typedef volatile struct ALT_RSTMGR_CTL_s | ALT_RSTMGR_CTL_t
typedef volatile struct ALT_RSTMGR_COUNTS_s | ALT_RSTMGR_COUNTS_t
typedef volatile struct ALT_RSTMGR_MPUMODRST_s | ALT_RSTMGR_MPUMODRST_t
typedef volatile struct ALT_RSTMGR_PERMODRST_s | ALT_RSTMGR_PERMODRST_t
typedef volatile struct ALT_RSTMGR_PER2MODRST_s | ALT_RSTMGR_PER2MODRST_t
typedef volatile struct ALT_RSTMGR_BRGMODRST_s | ALT_RSTMGR_BRGMODRST_t
typedef volatile struct ALT_RSTMGR_MISCMODRST_s | ALT_RSTMGR_MISCMODRST_t
typedef volatile struct ALT_RSTMGR_s | ALT_RSTMGR_t
typedef volatile struct ALT_RSTMGR_raw_s | ALT_RSTMGR_raw_t