RTEMS: bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h Source File

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alt_sysmgr.h
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1
7/*******************************************************************************
8* *
9* Copyright 2013 Altera Corporation. All Rights Reserved. *
10* *
11* Redistribution and use in source and binary forms, with or without *
12* modification, are permitted provided that the following conditions are met: *
13* *
14* 1. Redistributions of source code must retain the above copyright notice, *
15* this list of conditions and the following disclaimer. *
16* *
17* 2. Redistributions in binary form must reproduce the above copyright notice, *
18* this list of conditions and the following disclaimer in the documentation *
19* and/or other materials provided with the distribution. *
20* *
21* 3. The name of the author may not be used to endorse or promote products *
22* derived from this software without specific prior written permission. *
23* *
24* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
25* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
26* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
27* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
28* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
29* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
30* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
31* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
32* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
33* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
34* *
35*******************************************************************************/
36
37/* Altera - ALT_SYSMGR */
38
39#ifndef __ALTERA_ALT_SYSMGR_H__
40#define __ALTERA_ALT_SYSMGR_H__
41
42#ifdef __cplusplus
43extern "C"
44{
45#endif /* __cplusplus */
46
47/*
48 * Component : System Manager Module - ALT_SYSMGR
49 * System Manager Module
50 *
51 * Registers in the System Manager module
52 *
53 */
54/*
55 * Register : Silicon ID1 Register - siliconid1
56 *
57 * Specifies Silicon ID and revision number.
58 *
59 * Register Layout
60 *
61 * Bits | Access | Reset | Description
62 * :--------|:-------|:------|:-----------------
63 * [15:0] | R | 0x1 | Silicon Revision
64 * [31:16] | R | 0x0 | Silicon ID
65 *
66 */
67/*
68 * Field : Silicon Revision - rev
69 *
70 * Silicon revision number.
71 *
72 * Field Enumeration Values:
73 *
74 * Enum | Value | Description
75 * :---------------------------------|:------|:------------
76 * ALT_SYSMGR_SILICONID1_REV_E_REV1 | 0x1 | Revision 1
77 *
78 * Field Access Macros:
79 *
80 */
81/*
82 * Enumerated value for register field ALT_SYSMGR_SILICONID1_REV
83 *
84 * Revision 1
85 */
86#define ALT_SYSMGR_SILICONID1_REV_E_REV1 0x1
87
88/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID1_REV register field. */
89#define ALT_SYSMGR_SILICONID1_REV_LSB 0
90/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID1_REV register field. */
91#define ALT_SYSMGR_SILICONID1_REV_MSB 15
92/* The width in bits of the ALT_SYSMGR_SILICONID1_REV register field. */
93#define ALT_SYSMGR_SILICONID1_REV_WIDTH 16
94/* The mask used to set the ALT_SYSMGR_SILICONID1_REV register field value. */
95#define ALT_SYSMGR_SILICONID1_REV_SET_MSK 0x0000ffff
96/* The mask used to clear the ALT_SYSMGR_SILICONID1_REV register field value. */
97#define ALT_SYSMGR_SILICONID1_REV_CLR_MSK 0xffff0000
98/* The reset value of the ALT_SYSMGR_SILICONID1_REV register field. */
99#define ALT_SYSMGR_SILICONID1_REV_RESET 0x1
100/* Extracts the ALT_SYSMGR_SILICONID1_REV field value from a register. */
101#define ALT_SYSMGR_SILICONID1_REV_GET(value) (((value) & 0x0000ffff) >> 0)
102/* Produces a ALT_SYSMGR_SILICONID1_REV register field value suitable for setting the register. */
103#define ALT_SYSMGR_SILICONID1_REV_SET(value) (((value) << 0) & 0x0000ffff)
104
105/*
106 * Field : Silicon ID - id
107 *
108 * Silicon ID
109 *
110 * Field Enumeration Values:
111 *
112 * Enum | Value | Description
113 * :-------------------------------------------|:------|:----------------------------------------------
114 * ALT_SYSMGR_SILICONID1_ID_E_CYCLONEV_ARRIAV | 0x0 | HPS in Cyclone V and Arria V SoC FPGA devices
115 *
116 * Field Access Macros:
117 *
118 */
119/*
120 * Enumerated value for register field ALT_SYSMGR_SILICONID1_ID
121 *
122 * HPS in Cyclone V and Arria V SoC FPGA devices
123 */
124#define ALT_SYSMGR_SILICONID1_ID_E_CYCLONEV_ARRIAV 0x0
125
126/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID1_ID register field. */
127#define ALT_SYSMGR_SILICONID1_ID_LSB 16
128/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID1_ID register field. */
129#define ALT_SYSMGR_SILICONID1_ID_MSB 31
130/* The width in bits of the ALT_SYSMGR_SILICONID1_ID register field. */
131#define ALT_SYSMGR_SILICONID1_ID_WIDTH 16
132/* The mask used to set the ALT_SYSMGR_SILICONID1_ID register field value. */
133#define ALT_SYSMGR_SILICONID1_ID_SET_MSK 0xffff0000
134/* The mask used to clear the ALT_SYSMGR_SILICONID1_ID register field value. */
135#define ALT_SYSMGR_SILICONID1_ID_CLR_MSK 0x0000ffff
136/* The reset value of the ALT_SYSMGR_SILICONID1_ID register field. */
137#define ALT_SYSMGR_SILICONID1_ID_RESET 0x0
138/* Extracts the ALT_SYSMGR_SILICONID1_ID field value from a register. */
139#define ALT_SYSMGR_SILICONID1_ID_GET(value) (((value) & 0xffff0000) >> 16)
140/* Produces a ALT_SYSMGR_SILICONID1_ID register field value suitable for setting the register. */
141#define ALT_SYSMGR_SILICONID1_ID_SET(value) (((value) << 16) & 0xffff0000)
142
143#ifndef __ASSEMBLY__
144/*
145 * WARNING: The C register and register group struct declarations are provided for
146 * convenience and illustrative purposes. They should, however, be used with
147 * caution as the C language standard provides no guarantees about the alignment or
148 * atomicity of device memory accesses. The recommended practice for writing
149 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
150 * alt_write_word() functions.
151 *
152 * The struct declaration for register ALT_SYSMGR_SILICONID1.
153 */
154 struct ALT_SYSMGR_SILICONID1_s
155{
156 const uint32_t rev : 16; /* Silicon Revision */
157 const uint32_t id : 16; /* Silicon ID */
158};
159
160/* The typedef declaration for register ALT_SYSMGR_SILICONID1. */
161typedef volatile struct ALT_SYSMGR_SILICONID1_s ALT_SYSMGR_SILICONID1_t;
162#endif /* __ASSEMBLY__ */
163
164/* The byte offset of the ALT_SYSMGR_SILICONID1 register from the beginning of the component. */
165#define ALT_SYSMGR_SILICONID1_OFST 0x0
166
167/*
168 * Register : Silicon ID2 Register - siliconid2
169 *
170 * Reserved for future use.
171 *
172 * Register Layout
173 *
174 * Bits | Access | Reset | Description
175 * :-------|:-------|:------|:------------
176 * [31:0] | R | 0x0 | Reserved
177 *
178 */
179/*
180 * Field : Reserved - rsv
181 *
182 * Reserved for future use.
183 *
184 * Field Access Macros:
185 *
186 */
187/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID2_RSV register field. */
188#define ALT_SYSMGR_SILICONID2_RSV_LSB 0
189/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID2_RSV register field. */
190#define ALT_SYSMGR_SILICONID2_RSV_MSB 31
191/* The width in bits of the ALT_SYSMGR_SILICONID2_RSV register field. */
192#define ALT_SYSMGR_SILICONID2_RSV_WIDTH 32
193/* The mask used to set the ALT_SYSMGR_SILICONID2_RSV register field value. */
194#define ALT_SYSMGR_SILICONID2_RSV_SET_MSK 0xffffffff
195/* The mask used to clear the ALT_SYSMGR_SILICONID2_RSV register field value. */
196#define ALT_SYSMGR_SILICONID2_RSV_CLR_MSK 0x00000000
197/* The reset value of the ALT_SYSMGR_SILICONID2_RSV register field. */
198#define ALT_SYSMGR_SILICONID2_RSV_RESET 0x0
199/* Extracts the ALT_SYSMGR_SILICONID2_RSV field value from a register. */
200#define ALT_SYSMGR_SILICONID2_RSV_GET(value) (((value) & 0xffffffff) >> 0)
201/* Produces a ALT_SYSMGR_SILICONID2_RSV register field value suitable for setting the register. */
202#define ALT_SYSMGR_SILICONID2_RSV_SET(value) (((value) << 0) & 0xffffffff)
203
204#ifndef __ASSEMBLY__
205/*
206 * WARNING: The C register and register group struct declarations are provided for
207 * convenience and illustrative purposes. They should, however, be used with
208 * caution as the C language standard provides no guarantees about the alignment or
209 * atomicity of device memory accesses. The recommended practice for writing
210 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
211 * alt_write_word() functions.
212 *
213 * The struct declaration for register ALT_SYSMGR_SILICONID2.
214 */
215 struct ALT_SYSMGR_SILICONID2_s
216{
217 const uint32_t rsv : 32; /* Reserved */
218};
219
220/* The typedef declaration for register ALT_SYSMGR_SILICONID2. */
221typedef volatile struct ALT_SYSMGR_SILICONID2_s ALT_SYSMGR_SILICONID2_t;
222#endif /* __ASSEMBLY__ */
223
224/* The byte offset of the ALT_SYSMGR_SILICONID2 register from the beginning of the component. */
225#define ALT_SYSMGR_SILICONID2_OFST 0x4
226
227/*
228 * Register : L4 Watchdog Debug Register - wddbg
229 *
230 * Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These
231 * control registers are used to drive the pause input signal of the L4 watchdogs.
232 * Note that the watchdogs built into the MPU automatically are paused when their
233 * associated CPU enters debug mode. Only reset by a cold reset.
234 *
235 * Register Layout
236 *
237 * Bits | Access | Reset | Description
238 * :-------|:-------|:------|:------------
239 * [1:0] | RW | 0x3 | Debug Mode
240 * [3:2] | RW | 0x3 | Debug Mode
241 * [31:4] | ??? | 0x0 | *UNDEFINED*
242 *
243 */
244/*
245 * Field : Debug Mode - mode_0
246 *
247 * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index
248 * matches L4 watchdog index.
249 *
250 * Field Enumeration Values:
251 *
252 * Enum | Value | Description
253 * :-------------------------------------|:------|:-------------------------------------------------
254 * ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE | 0x0 | Continue normal operation ignoring debug mode of
255 * : | | CPUs
256 * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 | 0x1 | Pause normal operation only if CPU0 is in debug
257 * : | | mode
258 * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 | 0x2 | Pause normal operation only if CPU1 is in debug
259 * : | | mode
260 * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER | 0x3 | Pause normal operation if CPU0 or CPU1 is in
261 * : | | debug mode
262 *
263 * Field Access Macros:
264 *
265 */
266/*
267 * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0
268 *
269 * Continue normal operation ignoring debug mode of CPUs
270 */
271#define ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE 0x0
272/*
273 * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0
274 *
275 * Pause normal operation only if CPU0 is in debug mode
276 */
277#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 0x1
278/*
279 * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0
280 *
281 * Pause normal operation only if CPU1 is in debug mode
282 */
283#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 0x2
284/*
285 * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0
286 *
287 * Pause normal operation if CPU0 or CPU1 is in debug mode
288 */
289#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER 0x3
290
291/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field. */
292#define ALT_SYSMGR_WDDBG_MOD_0_LSB 0
293/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field. */
294#define ALT_SYSMGR_WDDBG_MOD_0_MSB 1
295/* The width in bits of the ALT_SYSMGR_WDDBG_MOD_0 register field. */
296#define ALT_SYSMGR_WDDBG_MOD_0_WIDTH 2
297/* The mask used to set the ALT_SYSMGR_WDDBG_MOD_0 register field value. */
298#define ALT_SYSMGR_WDDBG_MOD_0_SET_MSK 0x00000003
299/* The mask used to clear the ALT_SYSMGR_WDDBG_MOD_0 register field value. */
300#define ALT_SYSMGR_WDDBG_MOD_0_CLR_MSK 0xfffffffc
301/* The reset value of the ALT_SYSMGR_WDDBG_MOD_0 register field. */
302#define ALT_SYSMGR_WDDBG_MOD_0_RESET 0x3
303/* Extracts the ALT_SYSMGR_WDDBG_MOD_0 field value from a register. */
304#define ALT_SYSMGR_WDDBG_MOD_0_GET(value) (((value) & 0x00000003) >> 0)
305/* Produces a ALT_SYSMGR_WDDBG_MOD_0 register field value suitable for setting the register. */
306#define ALT_SYSMGR_WDDBG_MOD_0_SET(value) (((value) << 0) & 0x00000003)
307
308/*
309 * Field : Debug Mode - mode_1
310 *
311 * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index
312 * matches L4 watchdog index.
313 *
314 * Field Enumeration Values:
315 *
316 * Enum | Value | Description
317 * :-------------------------------------|:------|:-------------------------------------------------
318 * ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE | 0x0 | Continue normal operation ignoring debug mode of
319 * : | | CPUs
320 * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 | 0x1 | Pause normal operation only if CPU0 is in debug
321 * : | | mode
322 * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 | 0x2 | Pause normal operation only if CPU1 is in debug
323 * : | | mode
324 * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER | 0x3 | Pause normal operation if CPU0 or CPU1 is in
325 * : | | debug mode
326 *
327 * Field Access Macros:
328 *
329 */
330/*
331 * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1
332 *
333 * Continue normal operation ignoring debug mode of CPUs
334 */
335#define ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE 0x0
336/*
337 * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1
338 *
339 * Pause normal operation only if CPU0 is in debug mode
340 */
341#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 0x1
342/*
343 * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1
344 *
345 * Pause normal operation only if CPU1 is in debug mode
346 */
347#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 0x2
348/*
349 * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1
350 *
351 * Pause normal operation if CPU0 or CPU1 is in debug mode
352 */
353#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER 0x3
354
355/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field. */
356#define ALT_SYSMGR_WDDBG_MOD_1_LSB 2
357/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field. */
358#define ALT_SYSMGR_WDDBG_MOD_1_MSB 3
359/* The width in bits of the ALT_SYSMGR_WDDBG_MOD_1 register field. */
360#define ALT_SYSMGR_WDDBG_MOD_1_WIDTH 2
361/* The mask used to set the ALT_SYSMGR_WDDBG_MOD_1 register field value. */
362#define ALT_SYSMGR_WDDBG_MOD_1_SET_MSK 0x0000000c
363/* The mask used to clear the ALT_SYSMGR_WDDBG_MOD_1 register field value. */
364#define ALT_SYSMGR_WDDBG_MOD_1_CLR_MSK 0xfffffff3
365/* The reset value of the ALT_SYSMGR_WDDBG_MOD_1 register field. */
366#define ALT_SYSMGR_WDDBG_MOD_1_RESET 0x3
367/* Extracts the ALT_SYSMGR_WDDBG_MOD_1 field value from a register. */
368#define ALT_SYSMGR_WDDBG_MOD_1_GET(value) (((value) & 0x0000000c) >> 2)
369/* Produces a ALT_SYSMGR_WDDBG_MOD_1 register field value suitable for setting the register. */
370#define ALT_SYSMGR_WDDBG_MOD_1_SET(value) (((value) << 2) & 0x0000000c)
371
372#ifndef __ASSEMBLY__
373/*
374 * WARNING: The C register and register group struct declarations are provided for
375 * convenience and illustrative purposes. They should, however, be used with
376 * caution as the C language standard provides no guarantees about the alignment or
377 * atomicity of device memory accesses. The recommended practice for writing
378 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
379 * alt_write_word() functions.
380 *
381 * The struct declaration for register ALT_SYSMGR_WDDBG.
382 */
383 struct ALT_SYSMGR_WDDBG_s
384{
385 uint32_t mode_0 : 2; /* Debug Mode */
386 uint32_t mode_1 : 2; /* Debug Mode */
387 uint32_t : 28; /* *UNDEFINED* */
388};
389
390/* The typedef declaration for register ALT_SYSMGR_WDDBG. */
391typedef volatile struct ALT_SYSMGR_WDDBG_s ALT_SYSMGR_WDDBG_t;
392#endif /* __ASSEMBLY__ */
393
394/* The byte offset of the ALT_SYSMGR_WDDBG register from the beginning of the component. */
395#define ALT_SYSMGR_WDDBG_OFST 0x10
396
397/*
398 * Register : Boot Info Register - bootinfo
399 *
400 * Provides access to boot configuration information.
401 *
402 * Register Layout
403 *
404 * Bits | Access | Reset | Description
405 * :--------|:-------|:--------|:---------------------
406 * [2:0] | R | Unknown | Boot Select
407 * [4:3] | R | Unknown | Clock Select
408 * [7:5] | R | Unknown | HPS Pin Boot Select
409 * [9:8] | R | Unknown | HPS Pin Clock Select
410 * [31:10] | ??? | Unknown | *UNDEFINED*
411 *
412 */
413/*
414 * Field : Boot Select - bsel
415 *
416 * The boot select field specifies the boot source. It is read by the Boot ROM code
417 * on a cold or warm reset to determine the boot source.
418 *
419 * The HPS BSEL pins value are sampled upon deassertion of cold reset.
420 *
421 * Field Enumeration Values:
422 *
423 * Enum | Value | Description
424 * :--------------------------------------------------------|:------|:-----------------------------------
425 * ALT_SYSMGR_BOOT_BSEL_E_RSVD | 0x0 | Reserved
426 * ALT_SYSMGR_BOOT_BSEL_E_FPGA | 0x1 | FPGA (HPS2FPGA Bridge)
427 * ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V | 0x2 | NAND Flash (1.8v)
428 * ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V | 0x3 | NAND Flash (3.0v)
429 * ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V | 0x4 | SD/MMC External Transceiver (1.8v)
430 * ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V | 0x5 | SD/MMC Internal Transceiver (3.0v)
431 * ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V | 0x6 | QSPI Flash (1.8v)
432 * ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V | 0x7 | QSPI Flash (3.0v)
433 *
434 * Field Access Macros:
435 *
436 */
437/*
438 * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
439 *
440 * Reserved
441 */
442#define ALT_SYSMGR_BOOT_BSEL_E_RSVD 0x0
443/*
444 * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
445 *
446 * FPGA (HPS2FPGA Bridge)
447 */
448#define ALT_SYSMGR_BOOT_BSEL_E_FPGA 0x1
449/*
450 * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
451 *
452 * NAND Flash (1.8v)
453 */
454#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V 0x2
455/*
456 * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
457 *
458 * NAND Flash (3.0v)
459 */
460#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V 0x3
461/*
462 * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
463 *
464 * SD/MMC External Transceiver (1.8v)
465 */
466#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4
467/*
468 * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
469 *
470 * SD/MMC Internal Transceiver (3.0v)
471 */
472#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5
473/*
474 * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
475 *
476 * QSPI Flash (1.8v)
477 */
478#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V 0x6
479/*
480 * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
481 *
482 * QSPI Flash (3.0v)
483 */
484#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V 0x7
485
486/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_BSEL register field. */
487#define ALT_SYSMGR_BOOT_BSEL_LSB 0
488/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_BSEL register field. */
489#define ALT_SYSMGR_BOOT_BSEL_MSB 2
490/* The width in bits of the ALT_SYSMGR_BOOT_BSEL register field. */
491#define ALT_SYSMGR_BOOT_BSEL_WIDTH 3
492/* The mask used to set the ALT_SYSMGR_BOOT_BSEL register field value. */
493#define ALT_SYSMGR_BOOT_BSEL_SET_MSK 0x00000007
494/* The mask used to clear the ALT_SYSMGR_BOOT_BSEL register field value. */
495#define ALT_SYSMGR_BOOT_BSEL_CLR_MSK 0xfffffff8
496/* The reset value of the ALT_SYSMGR_BOOT_BSEL register field is UNKNOWN. */
497#define ALT_SYSMGR_BOOT_BSEL_RESET 0x0
498/* Extracts the ALT_SYSMGR_BOOT_BSEL field value from a register. */
499#define ALT_SYSMGR_BOOT_BSEL_GET(value) (((value) & 0x00000007) >> 0)
500/* Produces a ALT_SYSMGR_BOOT_BSEL register field value suitable for setting the register. */
501#define ALT_SYSMGR_BOOT_BSEL_SET(value) (((value) << 0) & 0x00000007)
502
503/*
504 * Field : Clock Select - csel
505 *
506 * The clock select field specifies clock information for booting. The clock select
507 * encoding is a function of the CSEL value. The clock select field is read by the
508 * Boot ROM code on a cold or warm reset when booting from a flash device to get
509 * information about how to setup the HPS clocking to boot from the specified clock
510 * device.
511 *
512 * The encoding of the clock select field is specified by the enum associated with
513 * this field.
514 *
515 * The HPS CSEL pins value are sampled upon deassertion of cold reset.
516 *
517 * Field Enumeration Values:
518 *
519 * Enum | Value | Description
520 * :------------------------------|:------|:------------------------------------------------
521 * ALT_SYSMGR_BOOT_CSEL_E_CSEL_0 | 0x0 | QSPI device clock is osc1_clk divided by 4,
522 * : | | SD/MMC device clock is osc1_clk divided by 4,
523 * : | | NAND device operation is osc1_clk divided by 25
524 * ALT_SYSMGR_BOOT_CSEL_E_CSEL_1 | 0x1 | QSPI device clock is osc1_clk divided by 2,
525 * : | | SD/MMC device clock is osc1_clk divided by 1,
526 * : | | NAND device operation is osc1_clk multiplied by
527 * : | | 20/25
528 * ALT_SYSMGR_BOOT_CSEL_E_CSEL_2 | 0x2 | QSPI device clock is osc1_clk divided by 1,
529 * : | | SD/MMC device clock is osc1_clk divided by 2,
530 * : | | NAND device operation is osc1_clk multiplied by
531 * : | | 10/25
532 * ALT_SYSMGR_BOOT_CSEL_E_CSEL_3 | 0x3 | QSPI device clock is osc1_clk multiplied by 2,
533 * : | | SD/MMC device clock is osc1_clk divided by 4,
534 * : | | NAND device operation is osc1_clk multiplied by
535 * : | | 5/25
536 *
537 * Field Access Macros:
538 *
539 */
540/*
541 * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL
542 *
543 * QSPI device clock is osc1_clk divided by 4, SD/MMC device clock is osc1_clk
544 * divided by 4, NAND device operation is osc1_clk divided by 25
545 */
546#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_0 0x0
547/*
548 * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL
549 *
550 * QSPI device clock is osc1_clk divided by 2, SD/MMC device clock is osc1_clk
551 * divided by 1, NAND device operation is osc1_clk multiplied by 20/25
552 */
553#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_1 0x1
554/*
555 * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL
556 *
557 * QSPI device clock is osc1_clk divided by 1, SD/MMC device clock is osc1_clk
558 * divided by 2, NAND device operation is osc1_clk multiplied by 10/25
559 */
560#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_2 0x2
561/*
562 * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL
563 *
564 * QSPI device clock is osc1_clk multiplied by 2, SD/MMC device clock is osc1_clk
565 * divided by 4, NAND device operation is osc1_clk multiplied by 5/25
566 */
567#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_3 0x3
568
569/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_CSEL register field. */
570#define ALT_SYSMGR_BOOT_CSEL_LSB 3
571/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_CSEL register field. */
572#define ALT_SYSMGR_BOOT_CSEL_MSB 4
573/* The width in bits of the ALT_SYSMGR_BOOT_CSEL register field. */
574#define ALT_SYSMGR_BOOT_CSEL_WIDTH 2
575/* The mask used to set the ALT_SYSMGR_BOOT_CSEL register field value. */
576#define ALT_SYSMGR_BOOT_CSEL_SET_MSK 0x00000018
577/* The mask used to clear the ALT_SYSMGR_BOOT_CSEL register field value. */
578#define ALT_SYSMGR_BOOT_CSEL_CLR_MSK 0xffffffe7
579/* The reset value of the ALT_SYSMGR_BOOT_CSEL register field is UNKNOWN. */
580#define ALT_SYSMGR_BOOT_CSEL_RESET 0x0
581/* Extracts the ALT_SYSMGR_BOOT_CSEL field value from a register. */
582#define ALT_SYSMGR_BOOT_CSEL_GET(value) (((value) & 0x00000018) >> 3)
583/* Produces a ALT_SYSMGR_BOOT_CSEL register field value suitable for setting the register. */
584#define ALT_SYSMGR_BOOT_CSEL_SET(value) (((value) << 3) & 0x00000018)
585
586/*
587 * Field : HPS Pin Boot Select - pinbsel
588 *
589 * Specifies the sampled value of the HPS BSEL pins. The value of HPS BSEL pins are
590 * sampled upon deassertion of cold reset.
591 *
592 * Field Access Macros:
593 *
594 */
595/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PINBSEL register field. */
596#define ALT_SYSMGR_BOOT_PINBSEL_LSB 5
597/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PINBSEL register field. */
598#define ALT_SYSMGR_BOOT_PINBSEL_MSB 7
599/* The width in bits of the ALT_SYSMGR_BOOT_PINBSEL register field. */
600#define ALT_SYSMGR_BOOT_PINBSEL_WIDTH 3
601/* The mask used to set the ALT_SYSMGR_BOOT_PINBSEL register field value. */
602#define ALT_SYSMGR_BOOT_PINBSEL_SET_MSK 0x000000e0
603/* The mask used to clear the ALT_SYSMGR_BOOT_PINBSEL register field value. */
604#define ALT_SYSMGR_BOOT_PINBSEL_CLR_MSK 0xffffff1f
605/* The reset value of the ALT_SYSMGR_BOOT_PINBSEL register field is UNKNOWN. */
606#define ALT_SYSMGR_BOOT_PINBSEL_RESET 0x0
607/* Extracts the ALT_SYSMGR_BOOT_PINBSEL field value from a register. */
608#define ALT_SYSMGR_BOOT_PINBSEL_GET(value) (((value) & 0x000000e0) >> 5)
609/* Produces a ALT_SYSMGR_BOOT_PINBSEL register field value suitable for setting the register. */
610#define ALT_SYSMGR_BOOT_PINBSEL_SET(value) (((value) << 5) & 0x000000e0)
611
612/*
613 * Field : HPS Pin Clock Select - pincsel
614 *
615 * Specifies the sampled value of the HPS CSEL pins. The value of HPS CSEL pins are
616 * sampled upon deassertion of cold reset.
617 *
618 * Field Access Macros:
619 *
620 */
621/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PINCSEL register field. */
622#define ALT_SYSMGR_BOOT_PINCSEL_LSB 8
623/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PINCSEL register field. */
624#define ALT_SYSMGR_BOOT_PINCSEL_MSB 9
625/* The width in bits of the ALT_SYSMGR_BOOT_PINCSEL register field. */
626#define ALT_SYSMGR_BOOT_PINCSEL_WIDTH 2
627/* The mask used to set the ALT_SYSMGR_BOOT_PINCSEL register field value. */
628#define ALT_SYSMGR_BOOT_PINCSEL_SET_MSK 0x00000300
629/* The mask used to clear the ALT_SYSMGR_BOOT_PINCSEL register field value. */
630#define ALT_SYSMGR_BOOT_PINCSEL_CLR_MSK 0xfffffcff
631/* The reset value of the ALT_SYSMGR_BOOT_PINCSEL register field is UNKNOWN. */
632#define ALT_SYSMGR_BOOT_PINCSEL_RESET 0x0
633/* Extracts the ALT_SYSMGR_BOOT_PINCSEL field value from a register. */
634#define ALT_SYSMGR_BOOT_PINCSEL_GET(value) (((value) & 0x00000300) >> 8)
635/* Produces a ALT_SYSMGR_BOOT_PINCSEL register field value suitable for setting the register. */
636#define ALT_SYSMGR_BOOT_PINCSEL_SET(value) (((value) << 8) & 0x00000300)
637
638#ifndef __ASSEMBLY__
639/*
640 * WARNING: The C register and register group struct declarations are provided for
641 * convenience and illustrative purposes. They should, however, be used with
642 * caution as the C language standard provides no guarantees about the alignment or
643 * atomicity of device memory accesses. The recommended practice for writing
644 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
645 * alt_write_word() functions.
646 *
647 * The struct declaration for register ALT_SYSMGR_BOOT.
648 */
649 struct ALT_SYSMGR_BOOT_s
650{
651 const uint32_t bsel : 3; /* Boot Select */
652 const uint32_t csel : 2; /* Clock Select */
653 const uint32_t pinbsel : 3; /* HPS Pin Boot Select */
654 const uint32_t pincsel : 2; /* HPS Pin Clock Select */
655 uint32_t : 22; /* *UNDEFINED* */
656};
657
658/* The typedef declaration for register ALT_SYSMGR_BOOT. */
659typedef volatile struct ALT_SYSMGR_BOOT_s ALT_SYSMGR_BOOT_t;
660#endif /* __ASSEMBLY__ */
661
662/* The byte offset of the ALT_SYSMGR_BOOT register from the beginning of the component. */
663#define ALT_SYSMGR_BOOT_OFST 0x14
664
665/*
666 * Register : HPS Info Register - hpsinfo
667 *
668 * Provides information about the HPS capabilities.
669 *
670 * Register Layout
671 *
672 * Bits | Access | Reset | Description
673 * :-------|:-------|:--------|:------------
674 * [0] | R | Unknown | Dual Core
675 * [1] | R | Unknown | CAN
676 * [31:2] | ??? | 0x0 | *UNDEFINED*
677 *
678 */
679/*
680 * Field : Dual Core - dualcore
681 *
682 * Indicates if CPU1 is available in MPU or not.
683 *
684 * Field Enumeration Values:
685 *
686 * Enum | Value | Description
687 * :-----------------------------------------|:------|:---------------------------------------------
688 * ALT_SYSMGR_HPSINFO_DUALCORE_E_SINGLECORE | 0x0 | Not dual-core (only CPU0 available).
689 * ALT_SYSMGR_HPSINFO_DUALCORE_E_DUALCORE | 0x1 | Is dual-core (CPU0 and CPU1 both available).
690 *
691 * Field Access Macros:
692 *
693 */
694/*
695 * Enumerated value for register field ALT_SYSMGR_HPSINFO_DUALCORE
696 *
697 * Not dual-core (only CPU0 available).
698 */
699#define ALT_SYSMGR_HPSINFO_DUALCORE_E_SINGLECORE 0x0
700/*
701 * Enumerated value for register field ALT_SYSMGR_HPSINFO_DUALCORE
702 *
703 * Is dual-core (CPU0 and CPU1 both available).
704 */
705#define ALT_SYSMGR_HPSINFO_DUALCORE_E_DUALCORE 0x1
706
707/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */
708#define ALT_SYSMGR_HPSINFO_DUALCORE_LSB 0
709/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */
710#define ALT_SYSMGR_HPSINFO_DUALCORE_MSB 0
711/* The width in bits of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */
712#define ALT_SYSMGR_HPSINFO_DUALCORE_WIDTH 1
713/* The mask used to set the ALT_SYSMGR_HPSINFO_DUALCORE register field value. */
714#define ALT_SYSMGR_HPSINFO_DUALCORE_SET_MSK 0x00000001
715/* The mask used to clear the ALT_SYSMGR_HPSINFO_DUALCORE register field value. */
716#define ALT_SYSMGR_HPSINFO_DUALCORE_CLR_MSK 0xfffffffe
717/* The reset value of the ALT_SYSMGR_HPSINFO_DUALCORE register field is UNKNOWN. */
718#define ALT_SYSMGR_HPSINFO_DUALCORE_RESET 0x0
719/* Extracts the ALT_SYSMGR_HPSINFO_DUALCORE field value from a register. */
720#define ALT_SYSMGR_HPSINFO_DUALCORE_GET(value) (((value) & 0x00000001) >> 0)
721/* Produces a ALT_SYSMGR_HPSINFO_DUALCORE register field value suitable for setting the register. */
722#define ALT_SYSMGR_HPSINFO_DUALCORE_SET(value) (((value) << 0) & 0x00000001)
723
724/*
725 * Field : CAN - can
726 *
727 * Indicates if CAN0 and CAN1 controllers are available or not.
728 *
729 * Field Enumeration Values:
730 *
731 * Enum | Value | Description
732 * :-----------------------------------------|:------|:---------------------------------
733 * ALT_SYSMGR_HPSINFO_CAN_E_CAN_UNAVAILABLE | 0x0 | CAN0 and CAN1 are not available.
734 * ALT_SYSMGR_HPSINFO_CAN_E_CAN_AVAILABLE | 0x1 | CAN0 and CAN1 are available.
735 *
736 * Field Access Macros:
737 *
738 */
739/*
740 * Enumerated value for register field ALT_SYSMGR_HPSINFO_CAN
741 *
742 * CAN0 and CAN1 are not available.
743 */
744#define ALT_SYSMGR_HPSINFO_CAN_E_CAN_UNAVAILABLE 0x0
745/*
746 * Enumerated value for register field ALT_SYSMGR_HPSINFO_CAN
747 *
748 * CAN0 and CAN1 are available.
749 */
750#define ALT_SYSMGR_HPSINFO_CAN_E_CAN_AVAILABLE 0x1
751
752/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_HPSINFO_CAN register field. */
753#define ALT_SYSMGR_HPSINFO_CAN_LSB 1
754/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_HPSINFO_CAN register field. */
755#define ALT_SYSMGR_HPSINFO_CAN_MSB 1
756/* The width in bits of the ALT_SYSMGR_HPSINFO_CAN register field. */
757#define ALT_SYSMGR_HPSINFO_CAN_WIDTH 1
758/* The mask used to set the ALT_SYSMGR_HPSINFO_CAN register field value. */
759#define ALT_SYSMGR_HPSINFO_CAN_SET_MSK 0x00000002
760/* The mask used to clear the ALT_SYSMGR_HPSINFO_CAN register field value. */
761#define ALT_SYSMGR_HPSINFO_CAN_CLR_MSK 0xfffffffd
762/* The reset value of the ALT_SYSMGR_HPSINFO_CAN register field is UNKNOWN. */
763#define ALT_SYSMGR_HPSINFO_CAN_RESET 0x0
764/* Extracts the ALT_SYSMGR_HPSINFO_CAN field value from a register. */
765#define ALT_SYSMGR_HPSINFO_CAN_GET(value) (((value) & 0x00000002) >> 1)
766/* Produces a ALT_SYSMGR_HPSINFO_CAN register field value suitable for setting the register. */
767#define ALT_SYSMGR_HPSINFO_CAN_SET(value) (((value) << 1) & 0x00000002)
768
769#ifndef __ASSEMBLY__
770/*
771 * WARNING: The C register and register group struct declarations are provided for
772 * convenience and illustrative purposes. They should, however, be used with
773 * caution as the C language standard provides no guarantees about the alignment or
774 * atomicity of device memory accesses. The recommended practice for writing
775 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
776 * alt_write_word() functions.
777 *
778 * The struct declaration for register ALT_SYSMGR_HPSINFO.
779 */
780 struct ALT_SYSMGR_HPSINFO_s
781{
782 const uint32_t dualcore : 1; /* Dual Core */
783 const uint32_t can : 1; /* CAN */
784 uint32_t : 30; /* *UNDEFINED* */
785};
786
787/* The typedef declaration for register ALT_SYSMGR_HPSINFO. */
788typedef volatile struct ALT_SYSMGR_HPSINFO_s ALT_SYSMGR_HPSINFO_t;
789#endif /* __ASSEMBLY__ */
790
791/* The byte offset of the ALT_SYSMGR_HPSINFO register from the beginning of the component. */
792#define ALT_SYSMGR_HPSINFO_OFST 0x18
793
794/*
795 * Register : Parity Fail Injection Register - parityinj
796 *
797 * Inject parity failures into the parity-protected RAMs in the MPU. Allows
798 * software to test the parity failure interrupt handler. The field array index
799 * corresponds to the CPU index.
800 *
801 * All fields are reset by a cold or warm reset.
802 *
803 * Register Layout
804 *
805 * Bits | Access | Reset | Description
806 * :--------|:-------|:------|:-----------------------------------------------------
807 * [0] | RW | 0x0 | Parity Fail Injection for Data Cache Data RAM
808 * [1] | RW | 0x0 | Parity Fail Injection for Data Cache Data RAM
809 * [2] | RW | 0x0 | Parity Fail Injection for Data Cache Tag RAM
810 * [3] | RW | 0x0 | Parity Fail Injection for Data Cache Tag RAM
811 * [4] | RW | 0x0 | Parity Fail Injection for Data Cache Outer RAM
812 * [5] | RW | 0x0 | Parity Fail Injection for Data Cache Outer RAM
813 * [6] | RW | 0x0 | Parity Fail Injection for Main TLB RAM
814 * [7] | RW | 0x0 | Parity Fail Injection for Main TLB RAM
815 * [8] | RW | 0x0 | Parity Fail Injection for Instruction Cache Data RAM
816 * [9] | RW | 0x0 | Parity Fail Injection for Instruction Cache Data RAM
817 * [10] | RW | 0x0 | Parity Fail Injection for Instruction Cache Tag RAM
818 * [11] | RW | 0x0 | Parity Fail Injection for Instruction Cache Tag RAM
819 * [12] | RW | 0x0 | Parity Fail Injection for GHB RAM
820 * [13] | RW | 0x0 | Parity Fail Injection for GHB RAM
821 * [14] | RW | 0x0 | Parity Fail Injection for BTAC RAM
822 * [15] | RW | 0x0 | Parity Fail Injection for BTAC RAM
823 * [31:16] | ??? | 0x0 | *UNDEFINED*
824 *
825 */
826/*
827 * Field : Parity Fail Injection for Data Cache Data RAM - dcdata_0
828 *
829 * If 1, injecting parity error to Data Cache Data RAM.The field array index
830 * corresponds to the CPU index.
831 *
832 * Field Access Macros:
833 *
834 */
835/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */
836#define ALT_SYSMGR_PARITYINJ_DCDATA_0_LSB 0
837/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */
838#define ALT_SYSMGR_PARITYINJ_DCDATA_0_MSB 0
839/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */
840#define ALT_SYSMGR_PARITYINJ_DCDATA_0_WIDTH 1
841/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value. */
842#define ALT_SYSMGR_PARITYINJ_DCDATA_0_SET_MSK 0x00000001
843/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value. */
844#define ALT_SYSMGR_PARITYINJ_DCDATA_0_CLR_MSK 0xfffffffe
845/* The reset value of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */
846#define ALT_SYSMGR_PARITYINJ_DCDATA_0_RESET 0x0
847/* Extracts the ALT_SYSMGR_PARITYINJ_DCDATA_0 field value from a register. */
848#define ALT_SYSMGR_PARITYINJ_DCDATA_0_GET(value) (((value) & 0x00000001) >> 0)
849/* Produces a ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value suitable for setting the register. */
850#define ALT_SYSMGR_PARITYINJ_DCDATA_0_SET(value) (((value) << 0) & 0x00000001)
851
852/*
853 * Field : Parity Fail Injection for Data Cache Data RAM - dcdata_1
854 *
855 * If 1, injecting parity error to Data Cache Data RAM.The field array index
856 * corresponds to the CPU index.
857 *
858 * Field Access Macros:
859 *
860 */
861/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */
862#define ALT_SYSMGR_PARITYINJ_DCDATA_1_LSB 1
863/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */
864#define ALT_SYSMGR_PARITYINJ_DCDATA_1_MSB 1
865/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */
866#define ALT_SYSMGR_PARITYINJ_DCDATA_1_WIDTH 1
867/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value. */
868#define ALT_SYSMGR_PARITYINJ_DCDATA_1_SET_MSK 0x00000002
869/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value. */
870#define ALT_SYSMGR_PARITYINJ_DCDATA_1_CLR_MSK 0xfffffffd
871/* The reset value of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */
872#define ALT_SYSMGR_PARITYINJ_DCDATA_1_RESET 0x0
873/* Extracts the ALT_SYSMGR_PARITYINJ_DCDATA_1 field value from a register. */
874#define ALT_SYSMGR_PARITYINJ_DCDATA_1_GET(value) (((value) & 0x00000002) >> 1)
875/* Produces a ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value suitable for setting the register. */
876#define ALT_SYSMGR_PARITYINJ_DCDATA_1_SET(value) (((value) << 1) & 0x00000002)
877
878/*
879 * Field : Parity Fail Injection for Data Cache Tag RAM - dctag_0
880 *
881 * If 1, injecting parity error to Data Cache Tag RAM.The field array index
882 * corresponds to the CPU index.
883 *
884 * Field Access Macros:
885 *
886 */
887/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */
888#define ALT_SYSMGR_PARITYINJ_DCTAG_0_LSB 2
889/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */
890#define ALT_SYSMGR_PARITYINJ_DCTAG_0_MSB 2
891/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */
892#define ALT_SYSMGR_PARITYINJ_DCTAG_0_WIDTH 1
893/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value. */
894#define ALT_SYSMGR_PARITYINJ_DCTAG_0_SET_MSK 0x00000004
895/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value. */
896#define ALT_SYSMGR_PARITYINJ_DCTAG_0_CLR_MSK 0xfffffffb
897/* The reset value of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */
898#define ALT_SYSMGR_PARITYINJ_DCTAG_0_RESET 0x0
899/* Extracts the ALT_SYSMGR_PARITYINJ_DCTAG_0 field value from a register. */
900#define ALT_SYSMGR_PARITYINJ_DCTAG_0_GET(value) (((value) & 0x00000004) >> 2)
901/* Produces a ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value suitable for setting the register. */
902#define ALT_SYSMGR_PARITYINJ_DCTAG_0_SET(value) (((value) << 2) & 0x00000004)
903
904/*
905 * Field : Parity Fail Injection for Data Cache Tag RAM - dctag_1
906 *
907 * If 1, injecting parity error to Data Cache Tag RAM.The field array index
908 * corresponds to the CPU index.
909 *
910 * Field Access Macros:
911 *
912 */
913/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */
914#define ALT_SYSMGR_PARITYINJ_DCTAG_1_LSB 3
915/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */
916#define ALT_SYSMGR_PARITYINJ_DCTAG_1_MSB 3
917/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */
918#define ALT_SYSMGR_PARITYINJ_DCTAG_1_WIDTH 1
919/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value. */
920#define ALT_SYSMGR_PARITYINJ_DCTAG_1_SET_MSK 0x00000008
921/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value. */
922#define ALT_SYSMGR_PARITYINJ_DCTAG_1_CLR_MSK 0xfffffff7
923/* The reset value of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */
924#define ALT_SYSMGR_PARITYINJ_DCTAG_1_RESET 0x0
925/* Extracts the ALT_SYSMGR_PARITYINJ_DCTAG_1 field value from a register. */
926#define ALT_SYSMGR_PARITYINJ_DCTAG_1_GET(value) (((value) & 0x00000008) >> 3)
927/* Produces a ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value suitable for setting the register. */
928#define ALT_SYSMGR_PARITYINJ_DCTAG_1_SET(value) (((value) << 3) & 0x00000008)
929
930/*
931 * Field : Parity Fail Injection for Data Cache Outer RAM - dcouter_0
932 *
933 * If 1, injecting parity error to Data Cache Outer RAM.The field array index
934 * corresponds to the CPU index.
935 *
936 * Field Access Macros:
937 *
938 */
939/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */
940#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_LSB 4
941/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */
942#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_MSB 4
943/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */
944#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_WIDTH 1
945/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value. */
946#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET_MSK 0x00000010
947/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value. */
948#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_CLR_MSK 0xffffffef
949/* The reset value of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */
950#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_RESET 0x0
951/* Extracts the ALT_SYSMGR_PARITYINJ_DCOUTER_0 field value from a register. */
952#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_GET(value) (((value) & 0x00000010) >> 4)
953/* Produces a ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value suitable for setting the register. */
954#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET(value) (((value) << 4) & 0x00000010)
955
956/*
957 * Field : Parity Fail Injection for Data Cache Outer RAM - dcouter_1
958 *
959 * If 1, injecting parity error to Data Cache Outer RAM.The field array index
960 * corresponds to the CPU index.
961 *
962 * Field Access Macros:
963 *
964 */
965/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */
966#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_LSB 5
967/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */
968#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_MSB 5
969/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */
970#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_WIDTH 1
971/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value. */
972#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET_MSK 0x00000020
973/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value. */
974#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_CLR_MSK 0xffffffdf
975/* The reset value of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */
976#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_RESET 0x0
977/* Extracts the ALT_SYSMGR_PARITYINJ_DCOUTER_1 field value from a register. */
978#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_GET(value) (((value) & 0x00000020) >> 5)
979/* Produces a ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value suitable for setting the register. */
980#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET(value) (((value) << 5) & 0x00000020)
981
982/*
983 * Field : Parity Fail Injection for Main TLB RAM - maintlb_0
984 *
985 * If 1, injecting parity error to Main TLB RAM.The field array index corresponds
986 * to the CPU index.
987 *
988 * Field Access Macros:
989 *
990 */
991/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */
992#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_LSB 6
993/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */
994#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_MSB 6
995/* The width in bits of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */
996#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_WIDTH 1
997/* The mask used to set the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value. */
998#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET_MSK 0x00000040
999/* The mask used to clear the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value. */
1000#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_CLR_MSK 0xffffffbf
1001/* The reset value of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */
1002#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_RESET 0x0
1003/* Extracts the ALT_SYSMGR_PARITYINJ_MAINTLB_0 field value from a register. */
1004#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_GET(value) (((value) & 0x00000040) >> 6)
1005/* Produces a ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value suitable for setting the register. */
1006#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET(value) (((value) << 6) & 0x00000040)
1007
1008/*
1009 * Field : Parity Fail Injection for Main TLB RAM - maintlb_1
1010 *
1011 * If 1, injecting parity error to Main TLB RAM.The field array index corresponds
1012 * to the CPU index.
1013 *
1014 * Field Access Macros:
1015 *
1016 */
1017/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */
1018#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_LSB 7
1019/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */
1020#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_MSB 7
1021/* The width in bits of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */
1022#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_WIDTH 1
1023/* The mask used to set the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value. */
1024#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET_MSK 0x00000080
1025/* The mask used to clear the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value. */
1026#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_CLR_MSK 0xffffff7f
1027/* The reset value of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */
1028#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_RESET 0x0
1029/* Extracts the ALT_SYSMGR_PARITYINJ_MAINTLB_1 field value from a register. */
1030#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_GET(value) (((value) & 0x00000080) >> 7)
1031/* Produces a ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value suitable for setting the register. */
1032#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET(value) (((value) << 7) & 0x00000080)
1033
1034/*
1035 * Field : Parity Fail Injection for Instruction Cache Data RAM - icdata_0
1036 *
1037 * If 1, injecting parity error to Instruction Cache Data RAM.The field array index
1038 * corresponds to the CPU index.
1039 *
1040 * Field Access Macros:
1041 *
1042 */
1043/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */
1044#define ALT_SYSMGR_PARITYINJ_ICDATA_0_LSB 8
1045/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */
1046#define ALT_SYSMGR_PARITYINJ_ICDATA_0_MSB 8
1047/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */
1048#define ALT_SYSMGR_PARITYINJ_ICDATA_0_WIDTH 1
1049/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value. */
1050#define ALT_SYSMGR_PARITYINJ_ICDATA_0_SET_MSK 0x00000100
1051/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value. */
1052#define ALT_SYSMGR_PARITYINJ_ICDATA_0_CLR_MSK 0xfffffeff
1053/* The reset value of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */
1054#define ALT_SYSMGR_PARITYINJ_ICDATA_0_RESET 0x0
1055/* Extracts the ALT_SYSMGR_PARITYINJ_ICDATA_0 field value from a register. */
1056#define ALT_SYSMGR_PARITYINJ_ICDATA_0_GET(value) (((value) & 0x00000100) >> 8)
1057/* Produces a ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value suitable for setting the register. */
1058#define ALT_SYSMGR_PARITYINJ_ICDATA_0_SET(value) (((value) << 8) & 0x00000100)
1059
1060/*
1061 * Field : Parity Fail Injection for Instruction Cache Data RAM - icdata_1
1062 *
1063 * If 1, injecting parity error to Instruction Cache Data RAM.The field array index
1064 * corresponds to the CPU index.
1065 *
1066 * Field Access Macros:
1067 *
1068 */
1069/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */
1070#define ALT_SYSMGR_PARITYINJ_ICDATA_1_LSB 9
1071/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */
1072#define ALT_SYSMGR_PARITYINJ_ICDATA_1_MSB 9
1073/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */
1074#define ALT_SYSMGR_PARITYINJ_ICDATA_1_WIDTH 1
1075/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value. */
1076#define ALT_SYSMGR_PARITYINJ_ICDATA_1_SET_MSK 0x00000200
1077/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value. */
1078#define ALT_SYSMGR_PARITYINJ_ICDATA_1_CLR_MSK 0xfffffdff
1079/* The reset value of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */
1080#define ALT_SYSMGR_PARITYINJ_ICDATA_1_RESET 0x0
1081/* Extracts the ALT_SYSMGR_PARITYINJ_ICDATA_1 field value from a register. */
1082#define ALT_SYSMGR_PARITYINJ_ICDATA_1_GET(value) (((value) & 0x00000200) >> 9)
1083/* Produces a ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value suitable for setting the register. */
1084#define ALT_SYSMGR_PARITYINJ_ICDATA_1_SET(value) (((value) << 9) & 0x00000200)
1085
1086/*
1087 * Field : Parity Fail Injection for Instruction Cache Tag RAM - ictag_0
1088 *
1089 * If 1, injecting parity error to Instruction Cache Tag RAM.The field array index
1090 * corresponds to the CPU index.
1091 *
1092 * Field Access Macros:
1093 *
1094 */
1095/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */
1096#define ALT_SYSMGR_PARITYINJ_ICTAG_0_LSB 10
1097/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */
1098#define ALT_SYSMGR_PARITYINJ_ICTAG_0_MSB 10
1099/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */
1100#define ALT_SYSMGR_PARITYINJ_ICTAG_0_WIDTH 1
1101/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value. */
1102#define ALT_SYSMGR_PARITYINJ_ICTAG_0_SET_MSK 0x00000400
1103/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value. */
1104#define ALT_SYSMGR_PARITYINJ_ICTAG_0_CLR_MSK 0xfffffbff
1105/* The reset value of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */
1106#define ALT_SYSMGR_PARITYINJ_ICTAG_0_RESET 0x0
1107/* Extracts the ALT_SYSMGR_PARITYINJ_ICTAG_0 field value from a register. */
1108#define ALT_SYSMGR_PARITYINJ_ICTAG_0_GET(value) (((value) & 0x00000400) >> 10)
1109/* Produces a ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value suitable for setting the register. */
1110#define ALT_SYSMGR_PARITYINJ_ICTAG_0_SET(value) (((value) << 10) & 0x00000400)
1111
1112/*
1113 * Field : Parity Fail Injection for Instruction Cache Tag RAM - ictag_1
1114 *
1115 * If 1, injecting parity error to Instruction Cache Tag RAM.The field array index
1116 * corresponds to the CPU index.
1117 *
1118 * Field Access Macros:
1119 *
1120 */
1121/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */
1122#define ALT_SYSMGR_PARITYINJ_ICTAG_1_LSB 11
1123/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */
1124#define ALT_SYSMGR_PARITYINJ_ICTAG_1_MSB 11
1125/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */
1126#define ALT_SYSMGR_PARITYINJ_ICTAG_1_WIDTH 1
1127/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value. */
1128#define ALT_SYSMGR_PARITYINJ_ICTAG_1_SET_MSK 0x00000800
1129/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value. */
1130#define ALT_SYSMGR_PARITYINJ_ICTAG_1_CLR_MSK 0xfffff7ff
1131/* The reset value of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */
1132#define ALT_SYSMGR_PARITYINJ_ICTAG_1_RESET 0x0
1133/* Extracts the ALT_SYSMGR_PARITYINJ_ICTAG_1 field value from a register. */
1134#define ALT_SYSMGR_PARITYINJ_ICTAG_1_GET(value) (((value) & 0x00000800) >> 11)
1135/* Produces a ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value suitable for setting the register. */
1136#define ALT_SYSMGR_PARITYINJ_ICTAG_1_SET(value) (((value) << 11) & 0x00000800)
1137
1138/*
1139 * Field : Parity Fail Injection for GHB RAM - ghb_0
1140 *
1141 * If 1, injecting parity error to GHB RAM.The field array index corresponds to the
1142 * CPU index.
1143 *
1144 * Field Access Macros:
1145 *
1146 */
1147/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */
1148#define ALT_SYSMGR_PARITYINJ_GHB_0_LSB 12
1149/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */
1150#define ALT_SYSMGR_PARITYINJ_GHB_0_MSB 12
1151/* The width in bits of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */
1152#define ALT_SYSMGR_PARITYINJ_GHB_0_WIDTH 1
1153/* The mask used to set the ALT_SYSMGR_PARITYINJ_GHB_0 register field value. */
1154#define ALT_SYSMGR_PARITYINJ_GHB_0_SET_MSK 0x00001000
1155/* The mask used to clear the ALT_SYSMGR_PARITYINJ_GHB_0 register field value. */
1156#define ALT_SYSMGR_PARITYINJ_GHB_0_CLR_MSK 0xffffefff
1157/* The reset value of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */
1158#define ALT_SYSMGR_PARITYINJ_GHB_0_RESET 0x0
1159/* Extracts the ALT_SYSMGR_PARITYINJ_GHB_0 field value from a register. */
1160#define ALT_SYSMGR_PARITYINJ_GHB_0_GET(value) (((value) & 0x00001000) >> 12)
1161/* Produces a ALT_SYSMGR_PARITYINJ_GHB_0 register field value suitable for setting the register. */
1162#define ALT_SYSMGR_PARITYINJ_GHB_0_SET(value) (((value) << 12) & 0x00001000)
1163
1164/*
1165 * Field : Parity Fail Injection for GHB RAM - ghb_1
1166 *
1167 * If 1, injecting parity error to GHB RAM.The field array index corresponds to the
1168 * CPU index.
1169 *
1170 * Field Access Macros:
1171 *
1172 */
1173/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */
1174#define ALT_SYSMGR_PARITYINJ_GHB_1_LSB 13
1175/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */
1176#define ALT_SYSMGR_PARITYINJ_GHB_1_MSB 13
1177/* The width in bits of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */
1178#define ALT_SYSMGR_PARITYINJ_GHB_1_WIDTH 1
1179/* The mask used to set the ALT_SYSMGR_PARITYINJ_GHB_1 register field value. */
1180#define ALT_SYSMGR_PARITYINJ_GHB_1_SET_MSK 0x00002000
1181/* The mask used to clear the ALT_SYSMGR_PARITYINJ_GHB_1 register field value. */
1182#define ALT_SYSMGR_PARITYINJ_GHB_1_CLR_MSK 0xffffdfff
1183/* The reset value of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */
1184#define ALT_SYSMGR_PARITYINJ_GHB_1_RESET 0x0
1185/* Extracts the ALT_SYSMGR_PARITYINJ_GHB_1 field value from a register. */
1186#define ALT_SYSMGR_PARITYINJ_GHB_1_GET(value) (((value) & 0x00002000) >> 13)
1187/* Produces a ALT_SYSMGR_PARITYINJ_GHB_1 register field value suitable for setting the register. */
1188#define ALT_SYSMGR_PARITYINJ_GHB_1_SET(value) (((value) << 13) & 0x00002000)
1189
1190/*
1191 * Field : Parity Fail Injection for BTAC RAM - btac_0
1192 *
1193 * If 1, injecting parity error to BTAC RAM.The field array index corresponds to
1194 * the CPU index.
1195 *
1196 * Field Access Macros:
1197 *
1198 */
1199/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */
1200#define ALT_SYSMGR_PARITYINJ_BTAC_0_LSB 14
1201/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */
1202#define ALT_SYSMGR_PARITYINJ_BTAC_0_MSB 14
1203/* The width in bits of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */
1204#define ALT_SYSMGR_PARITYINJ_BTAC_0_WIDTH 1
1205/* The mask used to set the ALT_SYSMGR_PARITYINJ_BTAC_0 register field value. */
1206#define ALT_SYSMGR_PARITYINJ_BTAC_0_SET_MSK 0x00004000
1207/* The mask used to clear the ALT_SYSMGR_PARITYINJ_BTAC_0 register field value. */
1208#define ALT_SYSMGR_PARITYINJ_BTAC_0_CLR_MSK 0xffffbfff
1209/* The reset value of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */
1210#define ALT_SYSMGR_PARITYINJ_BTAC_0_RESET 0x0
1211/* Extracts the ALT_SYSMGR_PARITYINJ_BTAC_0 field value from a register. */
1212#define ALT_SYSMGR_PARITYINJ_BTAC_0_GET(value) (((value) & 0x00004000) >> 14)
1213/* Produces a ALT_SYSMGR_PARITYINJ_BTAC_0 register field value suitable for setting the register. */
1214#define ALT_SYSMGR_PARITYINJ_BTAC_0_SET(value) (((value) << 14) & 0x00004000)
1215
1216/*
1217 * Field : Parity Fail Injection for BTAC RAM - btac_1
1218 *
1219 * If 1, injecting parity error to BTAC RAM.The field array index corresponds to
1220 * the CPU index.
1221 *
1222 * Field Access Macros:
1223 *
1224 */
1225/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */
1226#define ALT_SYSMGR_PARITYINJ_BTAC_1_LSB 15
1227/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */
1228#define ALT_SYSMGR_PARITYINJ_BTAC_1_MSB 15
1229/* The width in bits of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */
1230#define ALT_SYSMGR_PARITYINJ_BTAC_1_WIDTH 1
1231/* The mask used to set the ALT_SYSMGR_PARITYINJ_BTAC_1 register field value. */
1232#define ALT_SYSMGR_PARITYINJ_BTAC_1_SET_MSK 0x00008000
1233/* The mask used to clear the ALT_SYSMGR_PARITYINJ_BTAC_1 register field value. */
1234#define ALT_SYSMGR_PARITYINJ_BTAC_1_CLR_MSK 0xffff7fff
1235/* The reset value of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */
1236#define ALT_SYSMGR_PARITYINJ_BTAC_1_RESET 0x0
1237/* Extracts the ALT_SYSMGR_PARITYINJ_BTAC_1 field value from a register. */
1238#define ALT_SYSMGR_PARITYINJ_BTAC_1_GET(value) (((value) & 0x00008000) >> 15)
1239/* Produces a ALT_SYSMGR_PARITYINJ_BTAC_1 register field value suitable for setting the register. */
1240#define ALT_SYSMGR_PARITYINJ_BTAC_1_SET(value) (((value) << 15) & 0x00008000)
1241
1242#ifndef __ASSEMBLY__
1243/*
1244 * WARNING: The C register and register group struct declarations are provided for
1245 * convenience and illustrative purposes. They should, however, be used with
1246 * caution as the C language standard provides no guarantees about the alignment or
1247 * atomicity of device memory accesses. The recommended practice for writing
1248 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1249 * alt_write_word() functions.
1250 *
1251 * The struct declaration for register ALT_SYSMGR_PARITYINJ.
1252 */
1253 struct ALT_SYSMGR_PARITYINJ_s
1254{
1255 uint32_t dcdata_0 : 1; /* Parity Fail Injection for Data Cache Data RAM */
1256 uint32_t dcdata_1 : 1; /* Parity Fail Injection for Data Cache Data RAM */
1257 uint32_t dctag_0 : 1; /* Parity Fail Injection for Data Cache Tag RAM */
1258 uint32_t dctag_1 : 1; /* Parity Fail Injection for Data Cache Tag RAM */
1259 uint32_t dcouter_0 : 1; /* Parity Fail Injection for Data Cache Outer RAM */
1260 uint32_t dcouter_1 : 1; /* Parity Fail Injection for Data Cache Outer RAM */
1261 uint32_t maintlb_0 : 1; /* Parity Fail Injection for Main TLB RAM */
1262 uint32_t maintlb_1 : 1; /* Parity Fail Injection for Main TLB RAM */
1263 uint32_t icdata_0 : 1; /* Parity Fail Injection for Instruction Cache Data RAM */
1264 uint32_t icdata_1 : 1; /* Parity Fail Injection for Instruction Cache Data RAM */
1265 uint32_t ictag_0 : 1; /* Parity Fail Injection for Instruction Cache Tag RAM */
1266 uint32_t ictag_1 : 1; /* Parity Fail Injection for Instruction Cache Tag RAM */
1267 uint32_t ghb_0 : 1; /* Parity Fail Injection for GHB RAM */
1268 uint32_t ghb_1 : 1; /* Parity Fail Injection for GHB RAM */
1269 uint32_t btac_0 : 1; /* Parity Fail Injection for BTAC RAM */
1270 uint32_t btac_1 : 1; /* Parity Fail Injection for BTAC RAM */
1271 uint32_t : 16; /* *UNDEFINED* */
1272};
1273
1274/* The typedef declaration for register ALT_SYSMGR_PARITYINJ. */
1275typedef volatile struct ALT_SYSMGR_PARITYINJ_s ALT_SYSMGR_PARITYINJ_t;
1276#endif /* __ASSEMBLY__ */
1277
1278/* The byte offset of the ALT_SYSMGR_PARITYINJ register from the beginning of the component. */
1279#define ALT_SYSMGR_PARITYINJ_OFST 0x1c
1280
1281/*
1282 * Register Group : FPGA Interface Group - ALT_SYSMGR_FPGAINTF
1283 * FPGA Interface Group
1284 *
1285 * Registers used to enable/disable interfaces between the FPGA and HPS. Required
1286 * for either of the following situations:[list][*]Interfaces that cannot be
1287 * disabled by putting an HPS module associated with the interface into
1288 * reset.[*]HPS modules that accept signals from the FPGA fabric and those signals
1289 * might interfere with the normal operation of the module.[/list].
1290 *
1291 * All registers are only reset by a cold reset (ignore warm reset).
1292 *
1293 */
1294/*
1295 * Register : Global Disable Register - gbl
1296 *
1297 * Used to disable all interfaces between the FPGA and HPS.
1298 *
1299 * Register Layout
1300 *
1301 * Bits | Access | Reset | Description
1302 * :-------|:-------|:------|:-----------------
1303 * [0] | RW | 0x1 | Global Interface
1304 * [31:1] | ??? | 0x0 | *UNDEFINED*
1305 *
1306 */
1307/*
1308 * Field : Global Interface - intf
1309 *
1310 * Used to disable all interfaces between the FPGA and HPS. Software must ensure
1311 * that all interfaces between the FPGA and HPS are inactive before disabling them.
1312 *
1313 * Field Enumeration Values:
1314 *
1315 * Enum | Value | Description
1316 * :-----------------------------------|:------|:-------------------------------------------------
1317 * ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS | 0x0 | All interfaces between FPGA and HPS are
1318 * : | | disabled.
1319 * ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN | 0x1 | Interfaces between FPGA and HPS are not all
1320 * : | | disabled. Interfaces can be indivdually disabled
1321 * : | | by putting the HPS module associated with the
1322 * : | | interface in reset using registers in the Reset
1323 * : | | Manager or by using registers in this register
1324 * : | | group of the System Manager for interfaces
1325 * : | | without an associated module.
1326 *
1327 * Field Access Macros:
1328 *
1329 */
1330/*
1331 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_GBL_INTF
1332 *
1333 * All interfaces between FPGA and HPS are disabled.
1334 */
1335#define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS 0x0
1336/*
1337 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_GBL_INTF
1338 *
1339 * Interfaces between FPGA and HPS are not all disabled. Interfaces can be
1340 * indivdually disabled by putting the HPS module associated with the interface in
1341 * reset using registers in the Reset Manager or by using registers in this
1342 * register group of the System Manager for interfaces without an associated
1343 * module.
1344 */
1345#define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN 0x1
1346
1347/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */
1348#define ALT_SYSMGR_FPGAINTF_GBL_INTF_LSB 0
1349/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */
1350#define ALT_SYSMGR_FPGAINTF_GBL_INTF_MSB 0
1351/* The width in bits of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */
1352#define ALT_SYSMGR_FPGAINTF_GBL_INTF_WIDTH 1
1353/* The mask used to set the ALT_SYSMGR_FPGAINTF_GBL_INTF register field value. */
1354#define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK 0x00000001
1355/* The mask used to clear the ALT_SYSMGR_FPGAINTF_GBL_INTF register field value. */
1356#define ALT_SYSMGR_FPGAINTF_GBL_INTF_CLR_MSK 0xfffffffe
1357/* The reset value of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */
1358#define ALT_SYSMGR_FPGAINTF_GBL_INTF_RESET 0x1
1359/* Extracts the ALT_SYSMGR_FPGAINTF_GBL_INTF field value from a register. */
1360#define ALT_SYSMGR_FPGAINTF_GBL_INTF_GET(value) (((value) & 0x00000001) >> 0)
1361/* Produces a ALT_SYSMGR_FPGAINTF_GBL_INTF register field value suitable for setting the register. */
1362#define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET(value) (((value) << 0) & 0x00000001)
1363
1364#ifndef __ASSEMBLY__
1365/*
1366 * WARNING: The C register and register group struct declarations are provided for
1367 * convenience and illustrative purposes. They should, however, be used with
1368 * caution as the C language standard provides no guarantees about the alignment or
1369 * atomicity of device memory accesses. The recommended practice for writing
1370 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1371 * alt_write_word() functions.
1372 *
1373 * The struct declaration for register ALT_SYSMGR_FPGAINTF_GBL.
1374 */
1375 struct ALT_SYSMGR_FPGAINTF_GBL_s
1376{
1377 uint32_t intf : 1; /* Global Interface */
1378 uint32_t : 31; /* *UNDEFINED* */
1379};
1380
1381/* The typedef declaration for register ALT_SYSMGR_FPGAINTF_GBL. */
1382typedef volatile struct ALT_SYSMGR_FPGAINTF_GBL_s ALT_SYSMGR_FPGAINTF_GBL_t;
1383#endif /* __ASSEMBLY__ */
1384
1385/* The byte offset of the ALT_SYSMGR_FPGAINTF_GBL register from the beginning of the component. */
1386#define ALT_SYSMGR_FPGAINTF_GBL_OFST 0x0
1387
1388/*
1389 * Register : Individual Disable Register - indiv
1390 *
1391 * Used to disable individual interfaces between the FPGA and HPS.
1392 *
1393 * Register Layout
1394 *
1395 * Bits | Access | Reset | Description
1396 * :-------|:-------|:------|:------------------------------
1397 * [0] | RW | 0x1 | Reset Request Interface
1398 * [1] | RW | 0x1 | JTAG Enable Interface
1399 * [2] | RW | 0x1 | CONFIG_IO Interface
1400 * [3] | RW | 0x1 | Boundary-Scan Interface
1401 * [4] | RW | 0x1 | Trace Interface
1402 * [5] | ??? | 0x1 | *UNDEFINED*
1403 * [6] | RW | 0x1 | STM Event Interface
1404 * [7] | RW | 0x1 | Cross Trigger Interface (CTI)
1405 * [31:8] | ??? | 0x0 | *UNDEFINED*
1406 *
1407 */
1408/*
1409 * Field : Reset Request Interface - rstreqintf
1410 *
1411 * Used to disable the reset request interface. This interface allows logic in the
1412 * FPGA fabric to request HPS resets. This field disables the following reset
1413 * request signals from the FPGA fabric to HPS:[list][*]f2h_cold_rst_req_n -
1414 * Triggers a cold reset of the HPS[*]f2h_warm_rst_req_n - Triggers a warm reset of
1415 * the HPS[*]f2h_dbg_rst_req_n - Triggers a debug reset of the HPS[/list]
1416 *
1417 * Field Enumeration Values:
1418 *
1419 * Enum | Value | Description
1420 * :-------------------------------------------|:------|:-------------------------------------------------
1421 * ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS | 0x0 | Reset request interface is disabled. Logic in
1422 * : | | the FPGA fabric cannot reset the HPS.
1423 * ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN | 0x1 | Reset request interface is enabled. Logic in the
1424 * : | | FPGA fabric can reset the HPS.
1425 *
1426 * Field Access Macros:
1427 *
1428 */
1429/*
1430 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF
1431 *
1432 * Reset request interface is disabled. Logic in the FPGA fabric cannot reset the
1433 * HPS.
1434 */
1435#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS 0x0
1436/*
1437 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF
1438 *
1439 * Reset request interface is enabled. Logic in the FPGA fabric can reset the HPS.
1440 */
1441#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN 0x1
1442
1443/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */
1444#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_LSB 0
1445/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */
1446#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_MSB 0
1447/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */
1448#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_WIDTH 1
1449/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value. */
1450#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK 0x00000001
1451/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value. */
1452#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_CLR_MSK 0xfffffffe
1453/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */
1454#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_RESET 0x1
1455/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF field value from a register. */
1456#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_GET(value) (((value) & 0x00000001) >> 0)
1457/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value suitable for setting the register. */
1458#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET(value) (((value) << 0) & 0x00000001)
1459
1460/*
1461 * Field : JTAG Enable Interface - jtagenintf
1462 *
1463 * Used to disable the JTAG enable interface. This interface allows logic in the
1464 * FPGA fabric to disable the HPS JTAG operation.
1465 *
1466 * Field Enumeration Values:
1467 *
1468 * Enum | Value | Description
1469 * :-------------------------------------------|:------|:------------------------------------------------
1470 * ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS | 0x0 | JTAG enable interface is disabled. Logic in the
1471 * : | | FPGA fabric cannot disable the HPS JTAG.
1472 * ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN | 0x1 | JTAG enable interface is enabled. Logic in the
1473 * : | | FPGA fabric can disable the HPS JTAG.
1474 *
1475 * Field Access Macros:
1476 *
1477 */
1478/*
1479 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF
1480 *
1481 * JTAG enable interface is disabled. Logic in the FPGA fabric cannot disable the
1482 * HPS JTAG.
1483 */
1484#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS 0x0
1485/*
1486 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF
1487 *
1488 * JTAG enable interface is enabled. Logic in the FPGA fabric can disable the HPS
1489 * JTAG.
1490 */
1491#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN 0x1
1492
1493/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */
1494#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_LSB 1
1495/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */
1496#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_MSB 1
1497/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */
1498#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_WIDTH 1
1499/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value. */
1500#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK 0x00000002
1501/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value. */
1502#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_CLR_MSK 0xfffffffd
1503/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */
1504#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_RESET 0x1
1505/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF field value from a register. */
1506#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_GET(value) (((value) & 0x00000002) >> 1)
1507/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value suitable for setting the register. */
1508#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET(value) (((value) << 1) & 0x00000002)
1509
1510/*
1511 * Field : CONFIG_IO Interface - configiointf
1512 *
1513 * Used to disable the CONFIG_IO interface. This interface allows the FPGA JTAG TAP
1514 * controller to execute the CONFIG_IO instruction and configure all device I/Os
1515 * (FPGA and HPS). This is typically done before executing boundary-scan
1516 * instructions. The CONFIG_IO interface must be enabled before attempting to send
1517 * the CONFIG_IO instruction to the FPGA JTAG TAP controller.
1518 *
1519 * Field Enumeration Values:
1520 *
1521 * Enum | Value | Description
1522 * :------------------------------------------|:------|:-------------------------------------------------
1523 * ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS | 0x0 | CONFIG_IO interface is disabled. Execution of
1524 * : | | the CONFIG_IO instruction in the FPGA JTAG TAP
1525 * : | | controller is unsupported and produces undefined
1526 * : | | results.
1527 * ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN | 0x1 | CONFIG_IO interface is enabled. Execution of the
1528 * : | | CONFIG_IO instruction in the FPGA JTAG TAP
1529 * : | | controller is supported.
1530 *
1531 * Field Access Macros:
1532 *
1533 */
1534/*
1535 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF
1536 *
1537 * CONFIG_IO interface is disabled. Execution of the CONFIG_IO instruction in the
1538 * FPGA JTAG TAP controller is unsupported and produces undefined results.
1539 */
1540#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS 0x0
1541/*
1542 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF
1543 *
1544 * CONFIG_IO interface is enabled. Execution of the CONFIG_IO instruction in the
1545 * FPGA JTAG TAP controller is supported.
1546 */
1547#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN 0x1
1548
1549/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */
1550#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_LSB 2
1551/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */
1552#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_MSB 2
1553/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */
1554#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_WIDTH 1
1555/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value. */
1556#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK 0x00000004
1557/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value. */
1558#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_CLR_MSK 0xfffffffb
1559/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */
1560#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_RESET 0x1
1561/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF field value from a register. */
1562#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_GET(value) (((value) & 0x00000004) >> 2)
1563/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value suitable for setting the register. */
1564#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET(value) (((value) << 2) & 0x00000004)
1565
1566/*
1567 * Field : Boundary-Scan Interface - bscanintf
1568 *
1569 * Used to disable the boundary-scan interface. This interface allows the FPGA JTAG
1570 * TAP controller to execute boundary-scan instructions such as SAMPLE/PRELOAD,
1571 * EXTEST, and HIGHZ. The boundary-scan interface must be enabled before attempting
1572 * to send the boundary-scan instructions to the FPGA JTAG TAP controller.
1573 *
1574 * Field Enumeration Values:
1575 *
1576 * Enum | Value | Description
1577 * :------------------------------------------|:------|:-------------------------------------------------
1578 * ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS | 0x0 | Boundary-scan interface is disabled. Execution
1579 * : | | of boundary-scan instructions in the FPGA JTAG
1580 * : | | TAP controller is unsupported and produces
1581 * : | | undefined results.
1582 * ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN | 0x1 | Boundary-scan interface is enabled. Execution of
1583 * : | | the boundary-scan instructions in the FPGA JTAG
1584 * : | | TAP controller is supported.
1585 *
1586 * Field Access Macros:
1587 *
1588 */
1589/*
1590 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF
1591 *
1592 * Boundary-scan interface is disabled. Execution of boundary-scan instructions in
1593 * the FPGA JTAG TAP controller is unsupported and produces undefined results.
1594 */
1595#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS 0x0
1596/*
1597 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF
1598 *
1599 * Boundary-scan interface is enabled. Execution of the boundary-scan instructions
1600 * in the FPGA JTAG TAP controller is supported.
1601 */
1602#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN 0x1
1603
1604/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */
1605#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_LSB 3
1606/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */
1607#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_MSB 3
1608/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */
1609#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_WIDTH 1
1610/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value. */
1611#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK 0x00000008
1612/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value. */
1613#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_CLR_MSK 0xfffffff7
1614/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */
1615#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_RESET 0x1
1616/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF field value from a register. */
1617#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_GET(value) (((value) & 0x00000008) >> 3)
1618/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value suitable for setting the register. */
1619#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET(value) (((value) << 3) & 0x00000008)
1620
1621/*
1622 * Field : Trace Interface - traceintf
1623 *
1624 * Used to disable the trace interface. This interface allows the HPS debug logic
1625 * to send trace data to logic in the FPGA fabric.
1626 *
1627 * Field Enumeration Values:
1628 *
1629 * Enum | Value | Description
1630 * :------------------------------------------|:------|:-----------------------------------------------
1631 * ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS | 0x0 | Trace interface is disabled. HPS debug logic
1632 * : | | cannot send trace data to the FPGA fabric.
1633 * ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN | 0x1 | Trace interface is enabled. Other registers in
1634 * : | | the HPS debug logic must be programmmed to
1635 * : | | actually send trace data to the FPGA fabric.
1636 *
1637 * Field Access Macros:
1638 *
1639 */
1640/*
1641 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF
1642 *
1643 * Trace interface is disabled. HPS debug logic cannot send trace data to the FPGA
1644 * fabric.
1645 */
1646#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS 0x0
1647/*
1648 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF
1649 *
1650 * Trace interface is enabled. Other registers in the HPS debug logic must be
1651 * programmmed to actually send trace data to the FPGA fabric.
1652 */
1653#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN 0x1
1654
1655/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */
1656#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_LSB 4
1657/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */
1658#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_MSB 4
1659/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */
1660#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_WIDTH 1
1661/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value. */
1662#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK 0x00000010
1663/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value. */
1664#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_CLR_MSK 0xffffffef
1665/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */
1666#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_RESET 0x1
1667/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF field value from a register. */
1668#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_GET(value) (((value) & 0x00000010) >> 4)
1669/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value suitable for setting the register. */
1670#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET(value) (((value) << 4) & 0x00000010)
1671
1672/*
1673 * Field : STM Event Interface - stmeventintf
1674 *
1675 * Used to disable the STM event interface. This interface allows logic in the FPGA
1676 * fabric to trigger events to the STM debug module in the HPS.
1677 *
1678 * Field Enumeration Values:
1679 *
1680 * Enum | Value | Description
1681 * :---------------------------------------------|:------|:-----------------------------------------------
1682 * ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS | 0x0 | STM event interface is disabled. Logic in the
1683 * : | | FPGA fabric cannot trigger STM events.
1684 * ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN | 0x1 | STM event interface is enabled. Logic in the
1685 * : | | FPGA fabric can trigger STM events.
1686 *
1687 * Field Access Macros:
1688 *
1689 */
1690/*
1691 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF
1692 *
1693 * STM event interface is disabled. Logic in the FPGA fabric cannot trigger STM
1694 * events.
1695 */
1696#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS 0x0
1697/*
1698 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF
1699 *
1700 * STM event interface is enabled. Logic in the FPGA fabric can trigger STM
1701 * events.
1702 */
1703#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN 0x1
1704
1705/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */
1706#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_LSB 6
1707/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */
1708#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_MSB 6
1709/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */
1710#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_WIDTH 1
1711/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value. */
1712#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK 0x00000040
1713/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value. */
1714#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_CLR_MSK 0xffffffbf
1715/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */
1716#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_RESET 0x1
1717/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF field value from a register. */
1718#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_GET(value) (((value) & 0x00000040) >> 6)
1719/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value suitable for setting the register. */
1720#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET(value) (((value) << 6) & 0x00000040)
1721
1722/*
1723 * Field : Cross Trigger Interface (CTI) - crosstrigintf
1724 *
1725 * Used to disable the FPGA Fabric from sending triggers to HPS debug logic. Note
1726 * that this doesn't prevent the HPS debug logic from sending triggers to the FPGA
1727 * Fabric.
1728 *
1729 * Field Enumeration Values:
1730 *
1731 * Enum | Value | Description
1732 * :----------------------------------------------|:------|:----------------------------------
1733 * ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS | 0x0 | FPGA Fabric cannot send triggers.
1734 * ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN | 0x1 | FPGA Fabric can send triggers.
1735 *
1736 * Field Access Macros:
1737 *
1738 */
1739/*
1740 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF
1741 *
1742 * FPGA Fabric cannot send triggers.
1743 */
1744#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS 0x0
1745/*
1746 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF
1747 *
1748 * FPGA Fabric can send triggers.
1749 */
1750#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN 0x1
1751
1752/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */
1753#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_LSB 7
1754/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */
1755#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_MSB 7
1756/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */
1757#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_WIDTH 1
1758/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value. */
1759#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK 0x00000080
1760/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value. */
1761#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_CLR_MSK 0xffffff7f
1762/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */
1763#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_RESET 0x1
1764/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF field value from a register. */
1765#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_GET(value) (((value) & 0x00000080) >> 7)
1766/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value suitable for setting the register. */
1767#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET(value) (((value) << 7) & 0x00000080)
1768
1769#ifndef __ASSEMBLY__
1770/*
1771 * WARNING: The C register and register group struct declarations are provided for
1772 * convenience and illustrative purposes. They should, however, be used with
1773 * caution as the C language standard provides no guarantees about the alignment or
1774 * atomicity of device memory accesses. The recommended practice for writing
1775 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1776 * alt_write_word() functions.
1777 *
1778 * The struct declaration for register ALT_SYSMGR_FPGAINTF_INDIV.
1779 */
1780 struct ALT_SYSMGR_FPGAINTF_INDIV_s
1781{
1782 uint32_t rstreqintf : 1; /* Reset Request Interface */
1783 uint32_t jtagenintf : 1; /* JTAG Enable Interface */
1784 uint32_t configiointf : 1; /* CONFIG_IO Interface */
1785 uint32_t bscanintf : 1; /* Boundary-Scan Interface */
1786 uint32_t traceintf : 1; /* Trace Interface */
1787 uint32_t : 1; /* *UNDEFINED* */
1788 uint32_t stmeventintf : 1; /* STM Event Interface */
1789 uint32_t crosstrigintf : 1; /* Cross Trigger Interface (CTI) */
1790 uint32_t : 24; /* *UNDEFINED* */
1791};
1792
1793/* The typedef declaration for register ALT_SYSMGR_FPGAINTF_INDIV. */
1794typedef volatile struct ALT_SYSMGR_FPGAINTF_INDIV_s ALT_SYSMGR_FPGAINTF_INDIV_t;
1795#endif /* __ASSEMBLY__ */
1796
1797/* The byte offset of the ALT_SYSMGR_FPGAINTF_INDIV register from the beginning of the component. */
1798#define ALT_SYSMGR_FPGAINTF_INDIV_OFST 0x4
1799
1800/*
1801 * Register : Module Disable Register - module
1802 *
1803 * Used to disable signals from the FPGA fabric to individual HPS modules.
1804 *
1805 * Register Layout
1806 *
1807 * Bits | Access | Reset | Description
1808 * :-------|:-------|:------|:------------
1809 * [1:0] | ??? | 0x0 | *UNDEFINED*
1810 * [2] | RW | 0x0 | EMAC Module
1811 * [3] | RW | 0x0 | EMAC Module
1812 * [31:4] | ??? | 0x0 | *UNDEFINED*
1813 *
1814 */
1815/*
1816 * Field : EMAC Module - emac_0
1817 *
1818 * Used to disable signals from the FPGA fabric to the EMAC modules that could
1819 * potentially interfere with their normal operation.
1820 *
1821 * The array index corresponds to the EMAC module instance.
1822 *
1823 * Field Enumeration Values:
1824 *
1825 * Enum | Value | Description
1826 * :----------------------------------------|:------|:-------------------------------------------------
1827 * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_DIS | 0x0 | Signals from FPGA fabric cannot affect operation
1828 * : | | of the EMAC module.
1829 * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_EN | 0x1 | Signals from FPGA fabric can potentially affect
1830 * : | | operation of the EMAC module.
1831 *
1832 * Field Access Macros:
1833 *
1834 */
1835/*
1836 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0
1837 *
1838 * Signals from FPGA fabric cannot affect operation of the EMAC module.
1839 */
1840#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_DIS 0x0
1841/*
1842 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0
1843 *
1844 * Signals from FPGA fabric can potentially affect operation of the EMAC module.
1845 */
1846#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_EN 0x1
1847
1848/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */
1849#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_LSB 2
1850/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */
1851#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_MSB 2
1852/* The width in bits of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */
1853#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_WIDTH 1
1854/* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value. */
1855#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK 0x00000004
1856/* The mask used to clear the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value. */
1857#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_CLR_MSK 0xfffffffb
1858/* The reset value of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */
1859#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_RESET 0x0
1860/* Extracts the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 field value from a register. */
1861#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_GET(value) (((value) & 0x00000004) >> 2)
1862/* Produces a ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value suitable for setting the register. */
1863#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET(value) (((value) << 2) & 0x00000004)
1864
1865/*
1866 * Field : EMAC Module - emac_1
1867 *
1868 * Used to disable signals from the FPGA fabric to the EMAC modules that could
1869 * potentially interfere with their normal operation.
1870 *
1871 * The array index corresponds to the EMAC module instance.
1872 *
1873 * Field Enumeration Values:
1874 *
1875 * Enum | Value | Description
1876 * :----------------------------------------|:------|:-------------------------------------------------
1877 * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_DIS | 0x0 | Signals from FPGA fabric cannot affect operation
1878 * : | | of the EMAC module.
1879 * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_EN | 0x1 | Signals from FPGA fabric can potentially affect
1880 * : | | operation of the EMAC module.
1881 *
1882 * Field Access Macros:
1883 *
1884 */
1885/*
1886 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1
1887 *
1888 * Signals from FPGA fabric cannot affect operation of the EMAC module.
1889 */
1890#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_DIS 0x0
1891/*
1892 * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1
1893 *
1894 * Signals from FPGA fabric can potentially affect operation of the EMAC module.
1895 */
1896#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_EN 0x1
1897
1898/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */
1899#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_LSB 3
1900/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */
1901#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_MSB 3
1902/* The width in bits of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */
1903#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_WIDTH 1
1904/* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value. */
1905#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK 0x00000008
1906/* The mask used to clear the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value. */
1907#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_CLR_MSK 0xfffffff7
1908/* The reset value of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */
1909#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_RESET 0x0
1910/* Extracts the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 field value from a register. */
1911#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_GET(value) (((value) & 0x00000008) >> 3)
1912/* Produces a ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value suitable for setting the register. */
1913#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET(value) (((value) << 3) & 0x00000008)
1914
1915#ifndef __ASSEMBLY__
1916/*
1917 * WARNING: The C register and register group struct declarations are provided for
1918 * convenience and illustrative purposes. They should, however, be used with
1919 * caution as the C language standard provides no guarantees about the alignment or
1920 * atomicity of device memory accesses. The recommended practice for writing
1921 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1922 * alt_write_word() functions.
1923 *
1924 * The struct declaration for register ALT_SYSMGR_FPGAINTF_MODULE.
1925 */
1926 struct ALT_SYSMGR_FPGAINTF_MODULE_s
1927{
1928 uint32_t : 2; /* *UNDEFINED* */
1929 uint32_t emac_0 : 1; /* EMAC Module */
1930 uint32_t emac_1 : 1; /* EMAC Module */
1931 uint32_t : 28; /* *UNDEFINED* */
1932};
1933
1934/* The typedef declaration for register ALT_SYSMGR_FPGAINTF_MODULE. */
1935typedef volatile struct ALT_SYSMGR_FPGAINTF_MODULE_s ALT_SYSMGR_FPGAINTF_MODULE_t;
1936#endif /* __ASSEMBLY__ */
1937
1938/* The byte offset of the ALT_SYSMGR_FPGAINTF_MODULE register from the beginning of the component. */
1939#define ALT_SYSMGR_FPGAINTF_MODULE_OFST 0x8
1940
1941#ifndef __ASSEMBLY__
1942/*
1943 * WARNING: The C register and register group struct declarations are provided for
1944 * convenience and illustrative purposes. They should, however, be used with
1945 * caution as the C language standard provides no guarantees about the alignment or
1946 * atomicity of device memory accesses. The recommended practice for writing
1947 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1948 * alt_write_word() functions.
1949 *
1950 * The struct declaration for register group ALT_SYSMGR_FPGAINTF.
1951 */
1952 struct ALT_SYSMGR_FPGAINTF_s
1953{
1954 volatile ALT_SYSMGR_FPGAINTF_GBL_t gbl; /* ALT_SYSMGR_FPGAINTF_GBL */
1955 volatile ALT_SYSMGR_FPGAINTF_INDIV_t indiv; /* ALT_SYSMGR_FPGAINTF_INDIV */
1956 volatile ALT_SYSMGR_FPGAINTF_MODULE_t module; /* ALT_SYSMGR_FPGAINTF_MODULE */
1957 volatile uint32_t _pad_0xc_0x10; /* *UNDEFINED* */
1958};
1959
1960/* The typedef declaration for register group ALT_SYSMGR_FPGAINTF. */
1961typedef volatile struct ALT_SYSMGR_FPGAINTF_s ALT_SYSMGR_FPGAINTF_t;
1962/* The struct declaration for the raw register contents of register group ALT_SYSMGR_FPGAINTF. */
1963 struct ALT_SYSMGR_FPGAINTF_raw_s
1964{
1965 volatile uint32_t gbl; /* ALT_SYSMGR_FPGAINTF_GBL */
1966 volatile uint32_t indiv; /* ALT_SYSMGR_FPGAINTF_INDIV */
1967 volatile uint32_t module; /* ALT_SYSMGR_FPGAINTF_MODULE */
1968 volatile uint32_t _pad_0xc_0x10; /* *UNDEFINED* */
1969};
1970
1971/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_FPGAINTF. */
1972typedef volatile struct ALT_SYSMGR_FPGAINTF_raw_s ALT_SYSMGR_FPGAINTF_raw_t;
1973#endif /* __ASSEMBLY__ */
1974
1975
1976/*
1977 * Register Group : Scan Manager Group - ALT_SYSMGR_SCANMGR
1978 * Scan Manager Group
1979 *
1980 * Registers related to the Scan Manager that aren't located inside the Scan
1981 * Manager itself.
1982 *
1983 */
1984/*
1985 * Register : Scan Manager Control Register - ctrl
1986 *
1987 * Controls behaviors of Scan Manager not controlled by registers in the Scan
1988 * Manager itself.
1989 *
1990 * Register Layout
1991 *
1992 * Bits | Access | Reset | Description
1993 * :-------|:-------|:------|:-----------------
1994 * [0] | RW | 0x0 | FPGA JTAG Enable
1995 * [31:1] | ??? | 0x0 | *UNDEFINED*
1996 *
1997 */
1998/*
1999 * Field : FPGA JTAG Enable - fpgajtagen
2000 *
2001 * Controls whether FPGA JTAG pins or Scan Manager drives JTAG signals to the FPGA.
2002 *
2003 * Only reset by a cold reset (ignores warm reset).
2004 *
2005 * Field Enumeration Values:
2006 *
2007 * Enum | Value | Description
2008 * :---------------------------------------------|:------|:------------------------------------------
2009 * ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS | 0x0 | FPGA JTAG pins drive JTAG signals to FPGA
2010 * ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR | 0x1 | Scan Manager drives JTAG signals to FPGA
2011 *
2012 * Field Access Macros:
2013 *
2014 */
2015/*
2016 * Enumerated value for register field ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN
2017 *
2018 * FPGA JTAG pins drive JTAG signals to FPGA
2019 */
2020#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS 0x0
2021/*
2022 * Enumerated value for register field ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN
2023 *
2024 * Scan Manager drives JTAG signals to FPGA
2025 */
2026#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR 0x1
2027
2028/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */
2029#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_LSB 0
2030/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */
2031#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_MSB 0
2032/* The width in bits of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */
2033#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_WIDTH 1
2034/* The mask used to set the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value. */
2035#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET_MSK 0x00000001
2036/* The mask used to clear the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value. */
2037#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_CLR_MSK 0xfffffffe
2038/* The reset value of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */
2039#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_RESET 0x0
2040/* Extracts the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN field value from a register. */
2041#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_GET(value) (((value) & 0x00000001) >> 0)
2042/* Produces a ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value suitable for setting the register. */
2043#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET(value) (((value) << 0) & 0x00000001)
2044
2045#ifndef __ASSEMBLY__
2046/*
2047 * WARNING: The C register and register group struct declarations are provided for
2048 * convenience and illustrative purposes. They should, however, be used with
2049 * caution as the C language standard provides no guarantees about the alignment or
2050 * atomicity of device memory accesses. The recommended practice for writing
2051 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2052 * alt_write_word() functions.
2053 *
2054 * The struct declaration for register ALT_SYSMGR_SCANMGR_CTL.
2055 */
2056 struct ALT_SYSMGR_SCANMGR_CTL_s
2057{
2058 uint32_t fpgajtagen : 1; /* FPGA JTAG Enable */
2059 uint32_t : 31; /* *UNDEFINED* */
2060};
2061
2062/* The typedef declaration for register ALT_SYSMGR_SCANMGR_CTL. */
2063typedef volatile struct ALT_SYSMGR_SCANMGR_CTL_s ALT_SYSMGR_SCANMGR_CTL_t;
2064#endif /* __ASSEMBLY__ */
2065
2066/* The byte offset of the ALT_SYSMGR_SCANMGR_CTL register from the beginning of the component. */
2067#define ALT_SYSMGR_SCANMGR_CTL_OFST 0x0
2068
2069#ifndef __ASSEMBLY__
2070/*
2071 * WARNING: The C register and register group struct declarations are provided for
2072 * convenience and illustrative purposes. They should, however, be used with
2073 * caution as the C language standard provides no guarantees about the alignment or
2074 * atomicity of device memory accesses. The recommended practice for writing
2075 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2076 * alt_write_word() functions.
2077 *
2078 * The struct declaration for register group ALT_SYSMGR_SCANMGR.
2079 */
2080 struct ALT_SYSMGR_SCANMGR_s
2081{
2082 volatile ALT_SYSMGR_SCANMGR_CTL_t ctrl; /* ALT_SYSMGR_SCANMGR_CTL */
2083};
2084
2085/* The typedef declaration for register group ALT_SYSMGR_SCANMGR. */
2086typedef volatile struct ALT_SYSMGR_SCANMGR_s ALT_SYSMGR_SCANMGR_t;
2087/* The struct declaration for the raw register contents of register group ALT_SYSMGR_SCANMGR. */
2088 struct ALT_SYSMGR_SCANMGR_raw_s
2089{
2090 volatile uint32_t ctrl; /* ALT_SYSMGR_SCANMGR_CTL */
2091};
2092
2093/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_SCANMGR. */
2094typedef volatile struct ALT_SYSMGR_SCANMGR_raw_s ALT_SYSMGR_SCANMGR_raw_t;
2095#endif /* __ASSEMBLY__ */
2096
2097
2098/*
2099 * Register Group : Freeze Control Group - ALT_SYSMGR_FRZCTL
2100 * Freeze Control Group
2101 *
2102 * Registers used to generate HPS IO freeze signals.
2103 *
2104 * All registers are only reset by a cold reset (ignore warm reset).
2105 *
2106 */
2107/*
2108 * Register : VIO Control Register - vioctrl
2109 *
2110 * Used to drive freeze signals to HPS VIO banks.
2111 *
2112 * The register array index corresponds to the freeze channel.
2113 *
2114 * Freeze channel 0 provides freeze signals to VIO bank 0 and 1.
2115 *
2116 * Freeze channel 1 provides freeze signals to VIO bank 2 and 3. Only drives freeze
2117 * signals when SRC.VIO1 is set to SW.
2118 *
2119 * Freeze channel 2 provides freeze signals to VIO bank 4.
2120 *
2121 * All fields are only reset by a cold reset (ignore warm reset).
2122 *
2123 * The following equation determines when the weak pullup resistor is enabled:
2124 *
2125 * enabled = ~wkpullup | (CFF & cfg & tristate)
2126 *
2127 * where CFF is the value of weak pullup as set by IO configuration
2128 *
2129 * Register Layout
2130 *
2131 * Bits | Access | Reset | Description
2132 * :-------|:-------|:------|:-----------------
2133 * [0] | RW | 0x0 | IO Configuration
2134 * [1] | RW | 0x0 | IO Bus Hold
2135 * [2] | RW | 0x0 | IO Tri-State
2136 * [3] | RW | 0x0 | IO Weak Pullup
2137 * [4] | RW | 0x0 | IO Slew-rate
2138 * [31:5] | ??? | 0x0 | *UNDEFINED*
2139 *
2140 */
2141/*
2142 * Field : IO Configuration - cfg
2143 *
2144 * Controls IO configuration
2145 *
2146 * Field Enumeration Values:
2147 *
2148 * Enum | Value | Description
2149 * :-----------------------------------|:------|:-----------------------------------------------
2150 * ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS | 0x0 | Disable IO configuration (forced to a safe
2151 * : | | value).
2152 * ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG | 0x1 | Enables IO configuration as previously
2153 * : | | configured by software using the Scan Manager.
2154 *
2155 * Field Access Macros:
2156 *
2157 */
2158/*
2159 * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_CFG
2160 *
2161 * Disable IO configuration (forced to a safe value).
2162 */
2163#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS 0x0
2164/*
2165 * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_CFG
2166 *
2167 * Enables IO configuration as previously configured by software using the Scan
2168 * Manager.
2169 */
2170#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG 0x1
2171
2172/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */
2173#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_LSB 0
2174/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */
2175#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_MSB 0
2176/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */
2177#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_WIDTH 1
2178/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value. */
2179#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET_MSK 0x00000001
2180/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value. */
2181#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_CLR_MSK 0xfffffffe
2182/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */
2183#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_RESET 0x0
2184/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_CFG field value from a register. */
2185#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0)
2186/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value suitable for setting the register. */
2187#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001)
2188
2189/*
2190 * Field : IO Bus Hold - bushold
2191 *
2192 * Controls bus hold circuit
2193 *
2194 * Field Enumeration Values:
2195 *
2196 * Enum | Value | Description
2197 * :---------------------------------------|:------|:-------------------------------------------------
2198 * ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS | 0x0 | Disable bus hold circuit.
2199 * ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG | 0x1 | Bus hold circuit controlled by IO configuration.
2200 *
2201 * Field Access Macros:
2202 *
2203 */
2204/*
2205 * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD
2206 *
2207 * Disable bus hold circuit.
2208 */
2209#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS 0x0
2210/*
2211 * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD
2212 *
2213 * Bus hold circuit controlled by IO configuration.
2214 */
2215#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG 0x1
2216
2217/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */
2218#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_LSB 1
2219/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */
2220#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_MSB 1
2221/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */
2222#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_WIDTH 1
2223/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value. */
2224#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET_MSK 0x00000002
2225/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value. */
2226#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_CLR_MSK 0xfffffffd
2227/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */
2228#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_RESET 0x0
2229/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD field value from a register. */
2230#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1)
2231/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value suitable for setting the register. */
2232#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002)
2233
2234/*
2235 * Field : IO Tri-State - tristate
2236 *
2237 * Controls IO tri-state
2238 *
2239 * Field Enumeration Values:
2240 *
2241 * Enum | Value | Description
2242 * :----------------------------------------|:------|:---------------------------------------------
2243 * ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN | 0x0 | IO tri-state enabled.
2244 * ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG | 0x1 | IO tri-state controlled by IO configuration.
2245 *
2246 * Field Access Macros:
2247 *
2248 */
2249/*
2250 * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE
2251 *
2252 * IO tri-state enabled.
2253 */
2254#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN 0x0
2255/*
2256 * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE
2257 *
2258 * IO tri-state controlled by IO configuration.
2259 */
2260#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG 0x1
2261
2262/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */
2263#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_LSB 2
2264/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */
2265#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_MSB 2
2266/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */
2267#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_WIDTH 1
2268/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value. */
2269#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET_MSK 0x00000004
2270/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value. */
2271#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_CLR_MSK 0xfffffffb
2272/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */
2273#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_RESET 0x0
2274/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE field value from a register. */
2275#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2)
2276/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value suitable for setting the register. */
2277#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004)
2278
2279/*
2280 * Field : IO Weak Pullup - wkpullup
2281 *
2282 * Controls weak pullup resistor
2283 *
2284 * Field Enumeration Values:
2285 *
2286 * Enum | Value | Description
2287 * :----------------------------------------|:------|:---------------------------------------------
2288 * ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN | 0x0 | Weak pullup resistor enabled.
2289 * ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG | 0x1 | Weak pullup resistor enable controlled by IO
2290 * : | | configuration.
2291 *
2292 * Field Access Macros:
2293 *
2294 */
2295/*
2296 * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP
2297 *
2298 * Weak pullup resistor enabled.
2299 */
2300#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN 0x0
2301/*
2302 * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP
2303 *
2304 * Weak pullup resistor enable controlled by IO configuration.
2305 */
2306#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG 0x1
2307
2308/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */
2309#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_LSB 3
2310/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */
2311#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_MSB 3
2312/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */
2313#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_WIDTH 1
2314/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value. */
2315#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET_MSK 0x00000008
2316/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value. */
2317#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_CLR_MSK 0xfffffff7
2318/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */
2319#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_RESET 0x0
2320/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP field value from a register. */
2321#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3)
2322/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value suitable for setting the register. */
2323#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008)
2324
2325/*
2326 * Field : IO Slew-rate - slew
2327 *
2328 * Controls IO slew-rate
2329 *
2330 * Field Enumeration Values:
2331 *
2332 * Enum | Value | Description
2333 * :-------------------------------------|:------|:------------------------------------------
2334 * ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW | 0x0 | Slew-rate forced to slow.
2335 * ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG | 0x1 | Slew-rate controlled by IO configuration.
2336 *
2337 * Field Access Macros:
2338 *
2339 */
2340/*
2341 * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_SLEW
2342 *
2343 * Slew-rate forced to slow.
2344 */
2345#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW 0x0
2346/*
2347 * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_SLEW
2348 *
2349 * Slew-rate controlled by IO configuration.
2350 */
2351#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG 0x1
2352
2353/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */
2354#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_LSB 4
2355/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */
2356#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_MSB 4
2357/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */
2358#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_WIDTH 1
2359/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value. */
2360#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET_MSK 0x00000010
2361/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value. */
2362#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_CLR_MSK 0xffffffef
2363/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */
2364#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_RESET 0x0
2365/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW field value from a register. */
2366#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4)
2367/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value suitable for setting the register. */
2368#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010)
2369
2370#ifndef __ASSEMBLY__
2371/*
2372 * WARNING: The C register and register group struct declarations are provided for
2373 * convenience and illustrative purposes. They should, however, be used with
2374 * caution as the C language standard provides no guarantees about the alignment or
2375 * atomicity of device memory accesses. The recommended practice for writing
2376 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2377 * alt_write_word() functions.
2378 *
2379 * The struct declaration for register ALT_SYSMGR_FRZCTL_VIOCTL.
2380 */
2381 struct ALT_SYSMGR_FRZCTL_VIOCTL_s
2382{
2383 uint32_t cfg : 1; /* IO Configuration */
2384 uint32_t bushold : 1; /* IO Bus Hold */
2385 uint32_t tristate : 1; /* IO Tri-State */
2386 uint32_t wkpullup : 1; /* IO Weak Pullup */
2387 uint32_t slew : 1; /* IO Slew-rate */
2388 uint32_t : 27; /* *UNDEFINED* */
2389};
2390
2391/* The typedef declaration for register ALT_SYSMGR_FRZCTL_VIOCTL. */
2392typedef volatile struct ALT_SYSMGR_FRZCTL_VIOCTL_s ALT_SYSMGR_FRZCTL_VIOCTL_t;
2393#endif /* __ASSEMBLY__ */
2394
2395/* The byte offset of the ALT_SYSMGR_FRZCTL_VIOCTL register from the beginning of the component. */
2396#define ALT_SYSMGR_FRZCTL_VIOCTL_OFST 0x0
2397
2398/*
2399 * Register : HIO Control Register - hioctrl
2400 *
2401 * Used to drive freeze signals to HPS HIO bank (DDR SDRAM).
2402 *
2403 * All fields are only reset by a cold reset (ignore warm reset).
2404 *
2405 * The following equation determines when the weak pullup resistor is enabled:
2406 *
2407 * enabled = ~wkpullup | (CFF & cfg & tristate)
2408 *
2409 * where CFF is the value of weak pullup as set by IO configuration
2410 *
2411 * Register Layout
2412 *
2413 * Bits | Access | Reset | Description
2414 * :-------|:-------|:------|:-----------------------------------------
2415 * [0] | RW | 0x0 | IO Configuration
2416 * [1] | RW | 0x0 | IO Bus Hold
2417 * [2] | RW | 0x0 | IO Tri-State
2418 * [3] | RW | 0x0 | IO Weak Pullup
2419 * [4] | RW | 0x0 | IO Slew-rate
2420 * [5] | RW | 0x1 | DLL Reset
2421 * [6] | RW | 0x1 | OCT Reset
2422 * [7] | RW | 0x1 | IO and DQS Reset
2423 * [8] | RW | 0x0 | OCT Calibration and Configuration Enable
2424 * [31:9] | ??? | 0x0 | *UNDEFINED*
2425 *
2426 */
2427/*
2428 * Field : IO Configuration - cfg
2429 *
2430 * Controls IO configuration
2431 *
2432 * Field Enumeration Values:
2433 *
2434 * Enum | Value | Description
2435 * :-----------------------------------|:------|:-----------------------------------------------
2436 * ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS | 0x0 | Disable IO configuration (forced to a safe
2437 * : | | value).
2438 * ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG | 0x1 | Enables IO configuration as previously
2439 * : | | configured by software using the Scan Manager.
2440 *
2441 * Field Access Macros:
2442 *
2443 */
2444/*
2445 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_CFG
2446 *
2447 * Disable IO configuration (forced to a safe value).
2448 */
2449#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS 0x0
2450/*
2451 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_CFG
2452 *
2453 * Enables IO configuration as previously configured by software using the Scan
2454 * Manager.
2455 */
2456#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG 0x1
2457
2458/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */
2459#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_LSB 0
2460/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */
2461#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_MSB 0
2462/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */
2463#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_WIDTH 1
2464/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value. */
2465#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET_MSK 0x00000001
2466/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value. */
2467#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_CLR_MSK 0xfffffffe
2468/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */
2469#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_RESET 0x0
2470/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_CFG field value from a register. */
2471#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0)
2472/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value suitable for setting the register. */
2473#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001)
2474
2475/*
2476 * Field : IO Bus Hold - bushold
2477 *
2478 * Controls bus hold circuit
2479 *
2480 * Field Enumeration Values:
2481 *
2482 * Enum | Value | Description
2483 * :---------------------------------------|:------|:-------------------------------------------------
2484 * ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS | 0x0 | Disable bus hold circuit.
2485 * ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG | 0x1 | Bus hold circuit controlled by IO configuration.
2486 *
2487 * Field Access Macros:
2488 *
2489 */
2490/*
2491 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD
2492 *
2493 * Disable bus hold circuit.
2494 */
2495#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS 0x0
2496/*
2497 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD
2498 *
2499 * Bus hold circuit controlled by IO configuration.
2500 */
2501#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG 0x1
2502
2503/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */
2504#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_LSB 1
2505/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */
2506#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_MSB 1
2507/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */
2508#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_WIDTH 1
2509/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value. */
2510#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET_MSK 0x00000002
2511/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value. */
2512#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_CLR_MSK 0xfffffffd
2513/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */
2514#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_RESET 0x0
2515/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD field value from a register. */
2516#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1)
2517/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value suitable for setting the register. */
2518#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002)
2519
2520/*
2521 * Field : IO Tri-State - tristate
2522 *
2523 * Controls IO tri-state
2524 *
2525 * Field Enumeration Values:
2526 *
2527 * Enum | Value | Description
2528 * :----------------------------------------|:------|:---------------------------------------------
2529 * ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN | 0x0 | IO tri-state enabled.
2530 * ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG | 0x1 | IO tri-state controlled by IO configuration.
2531 *
2532 * Field Access Macros:
2533 *
2534 */
2535/*
2536 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE
2537 *
2538 * IO tri-state enabled.
2539 */
2540#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN 0x0
2541/*
2542 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE
2543 *
2544 * IO tri-state controlled by IO configuration.
2545 */
2546#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG 0x1
2547
2548/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */
2549#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_LSB 2
2550/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */
2551#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_MSB 2
2552/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */
2553#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_WIDTH 1
2554/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value. */
2555#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET_MSK 0x00000004
2556/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value. */
2557#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_CLR_MSK 0xfffffffb
2558/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */
2559#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_RESET 0x0
2560/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE field value from a register. */
2561#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2)
2562/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value suitable for setting the register. */
2563#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004)
2564
2565/*
2566 * Field : IO Weak Pullup - wkpullup
2567 *
2568 * Controls weak pullup resistor
2569 *
2570 * Field Enumeration Values:
2571 *
2572 * Enum | Value | Description
2573 * :----------------------------------------|:------|:---------------------------------------------
2574 * ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN | 0x0 | Weak pullup resistor enabled.
2575 * ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG | 0x1 | Weak pullup resistor enable controlled by IO
2576 * : | | configuration.
2577 *
2578 * Field Access Macros:
2579 *
2580 */
2581/*
2582 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP
2583 *
2584 * Weak pullup resistor enabled.
2585 */
2586#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN 0x0
2587/*
2588 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP
2589 *
2590 * Weak pullup resistor enable controlled by IO configuration.
2591 */
2592#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG 0x1
2593
2594/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */
2595#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_LSB 3
2596/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */
2597#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_MSB 3
2598/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */
2599#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_WIDTH 1
2600/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value. */
2601#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET_MSK 0x00000008
2602/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value. */
2603#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_CLR_MSK 0xfffffff7
2604/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */
2605#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_RESET 0x0
2606/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP field value from a register. */
2607#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3)
2608/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value suitable for setting the register. */
2609#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008)
2610
2611/*
2612 * Field : IO Slew-rate - slew
2613 *
2614 * Controls IO slew-rate
2615 *
2616 * Field Enumeration Values:
2617 *
2618 * Enum | Value | Description
2619 * :-------------------------------------|:------|:------------------------------------------
2620 * ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW | 0x0 | Slew-rate forced to slow.
2621 * ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG | 0x1 | Slew-rate controlled by IO configuration.
2622 *
2623 * Field Access Macros:
2624 *
2625 */
2626/*
2627 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_SLEW
2628 *
2629 * Slew-rate forced to slow.
2630 */
2631#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW 0x0
2632/*
2633 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_SLEW
2634 *
2635 * Slew-rate controlled by IO configuration.
2636 */
2637#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG 0x1
2638
2639/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */
2640#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_LSB 4
2641/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */
2642#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_MSB 4
2643/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */
2644#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_WIDTH 1
2645/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value. */
2646#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET_MSK 0x00000010
2647/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value. */
2648#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_CLR_MSK 0xffffffef
2649/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */
2650#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_RESET 0x0
2651/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW field value from a register. */
2652#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4)
2653/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value suitable for setting the register. */
2654#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010)
2655
2656/*
2657 * Field : DLL Reset - dllrst
2658 *
2659 * Controls DLL (Delay-Locked Loop) reset.
2660 *
2661 * Field Enumeration Values:
2662 *
2663 * Enum | Value | Description
2664 * :--------------------------------------|:------|:----------------------------------------------
2665 * ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS | 0x0 | No reset or clock gating.
2666 * ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN | 0x1 | Resets registers in the DLL and gates off DLL
2667 * : | | clock.
2668 *
2669 * Field Access Macros:
2670 *
2671 */
2672/*
2673 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST
2674 *
2675 * No reset or clock gating.
2676 */
2677#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS 0x0
2678/*
2679 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST
2680 *
2681 * Resets registers in the DLL and gates off DLL clock.
2682 */
2683#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN 0x1
2684
2685/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */
2686#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_LSB 5
2687/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */
2688#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_MSB 5
2689/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */
2690#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_WIDTH 1
2691/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value. */
2692#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET_MSK 0x00000020
2693/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value. */
2694#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_CLR_MSK 0xffffffdf
2695/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */
2696#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_RESET 0x1
2697/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST field value from a register. */
2698#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_GET(value) (((value) & 0x00000020) >> 5)
2699/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value suitable for setting the register. */
2700#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET(value) (((value) << 5) & 0x00000020)
2701
2702/*
2703 * Field : OCT Reset - octrst
2704 *
2705 * Controls OCT reset.
2706 *
2707 * Field Enumeration Values:
2708 *
2709 * Enum | Value | Description
2710 * :--------------------------------------|:------|:-----------------------------
2711 * ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS | 0x0 | No reset.
2712 * ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN | 0x1 | Resets registers in the OCT.
2713 *
2714 * Field Access Macros:
2715 *
2716 */
2717/*
2718 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST
2719 *
2720 * No reset.
2721 */
2722#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS 0x0
2723/*
2724 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST
2725 *
2726 * Resets registers in the OCT.
2727 */
2728#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN 0x1
2729
2730/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */
2731#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_LSB 6
2732/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */
2733#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_MSB 6
2734/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */
2735#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_WIDTH 1
2736/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value. */
2737#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET_MSK 0x00000040
2738/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value. */
2739#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_CLR_MSK 0xffffffbf
2740/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */
2741#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_RESET 0x1
2742/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST field value from a register. */
2743#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_GET(value) (((value) & 0x00000040) >> 6)
2744/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value suitable for setting the register. */
2745#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET(value) (((value) << 6) & 0x00000040)
2746
2747/*
2748 * Field : IO and DQS Reset - regrst
2749 *
2750 * Controls IO and DQS reset.
2751 *
2752 * Field Enumeration Values:
2753 *
2754 * Enum | Value | Description
2755 * :--------------------------------------|:------|:-------------------------------------------
2756 * ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS | 0x0 | No reset.
2757 * ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN | 0x1 | Resets all IO registers and DQS registers.
2758 *
2759 * Field Access Macros:
2760 *
2761 */
2762/*
2763 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_REGRST
2764 *
2765 * No reset.
2766 */
2767#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS 0x0
2768/*
2769 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_REGRST
2770 *
2771 * Resets all IO registers and DQS registers.
2772 */
2773#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN 0x1
2774
2775/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */
2776#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_LSB 7
2777/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */
2778#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_MSB 7
2779/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */
2780#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_WIDTH 1
2781/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value. */
2782#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET_MSK 0x00000080
2783/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value. */
2784#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_CLR_MSK 0xffffff7f
2785/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */
2786#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_RESET 0x1
2787/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST field value from a register. */
2788#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_GET(value) (((value) & 0x00000080) >> 7)
2789/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value suitable for setting the register. */
2790#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET(value) (((value) << 7) & 0x00000080)
2791
2792/*
2793 * Field : OCT Calibration and Configuration Enable - oct_cfgen_calstart
2794 *
2795 * Controls OCT calibration and OCT IO configuration enable.
2796 *
2797 * Field Enumeration Values:
2798 *
2799 * Enum | Value | Description
2800 * :--------------------------------------------------|:------|:-------------------------------------------------
2801 * ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS | 0x0 | Disables IO configuration (forced to a safe
2802 * : | | value) in OCT calibration block.
2803 * ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN | 0x1 | Starts OCT calibration state machine and enables
2804 * : | | IO configuration in OCT calibration block.
2805 *
2806 * Field Access Macros:
2807 *
2808 */
2809/*
2810 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART
2811 *
2812 * Disables IO configuration (forced to a safe value) in OCT calibration block.
2813 */
2814#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS 0x0
2815/*
2816 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART
2817 *
2818 * Starts OCT calibration state machine and enables IO configuration in OCT
2819 * calibration block.
2820 */
2821#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN 0x1
2822
2823/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */
2824#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_LSB 8
2825/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */
2826#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_MSB 8
2827/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */
2828#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_WIDTH 1
2829/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value. */
2830#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET_MSK 0x00000100
2831/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value. */
2832#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_CLR_MSK 0xfffffeff
2833/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */
2834#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_RESET 0x0
2835/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART field value from a register. */
2836#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_GET(value) (((value) & 0x00000100) >> 8)
2837/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value suitable for setting the register. */
2838#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET(value) (((value) << 8) & 0x00000100)
2839
2840#ifndef __ASSEMBLY__
2841/*
2842 * WARNING: The C register and register group struct declarations are provided for
2843 * convenience and illustrative purposes. They should, however, be used with
2844 * caution as the C language standard provides no guarantees about the alignment or
2845 * atomicity of device memory accesses. The recommended practice for writing
2846 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2847 * alt_write_word() functions.
2848 *
2849 * The struct declaration for register ALT_SYSMGR_FRZCTL_HIOCTL.
2850 */
2851 struct ALT_SYSMGR_FRZCTL_HIOCTL_s
2852{
2853 uint32_t cfg : 1; /* IO Configuration */
2854 uint32_t bushold : 1; /* IO Bus Hold */
2855 uint32_t tristate : 1; /* IO Tri-State */
2856 uint32_t wkpullup : 1; /* IO Weak Pullup */
2857 uint32_t slew : 1; /* IO Slew-rate */
2858 uint32_t dllrst : 1; /* DLL Reset */
2859 uint32_t octrst : 1; /* OCT Reset */
2860 uint32_t regrst : 1; /* IO and DQS Reset */
2861 uint32_t oct_cfgen_calstart : 1; /* OCT Calibration and Configuration Enable */
2862 uint32_t : 23; /* *UNDEFINED* */
2863};
2864
2865/* The typedef declaration for register ALT_SYSMGR_FRZCTL_HIOCTL. */
2866typedef volatile struct ALT_SYSMGR_FRZCTL_HIOCTL_s ALT_SYSMGR_FRZCTL_HIOCTL_t;
2867#endif /* __ASSEMBLY__ */
2868
2869/* The byte offset of the ALT_SYSMGR_FRZCTL_HIOCTL register from the beginning of the component. */
2870#define ALT_SYSMGR_FRZCTL_HIOCTL_OFST 0x10
2871
2872/*
2873 * Register : Source Register - src
2874 *
2875 * Contains register field to choose between software state machine (vioctrl array
2876 * index [1] register) or hardware state machine in the Freeze Controller as the
2877 * freeze signal source for VIO channel 1.
2878 *
2879 * All fields are only reset by a cold reset (ignore warm reset).
2880 *
2881 * Register Layout
2882 *
2883 * Bits | Access | Reset | Description
2884 * :-------|:-------|:------|:--------------------------
2885 * [0] | RW | 0x0 | VIO1 Freeze Signal Source
2886 * [31:1] | ??? | 0x0 | *UNDEFINED*
2887 *
2888 */
2889/*
2890 * Field : VIO1 Freeze Signal Source - vio1
2891 *
2892 * The freeze signal source for VIO channel 1 (VIO bank 2 and bank 3).
2893 *
2894 * Field Enumeration Values:
2895 *
2896 * Enum | Value | Description
2897 * :--------------------------------|:------|:-------------------------------------------------
2898 * ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW | 0x0 | VIO1 freeze signals are driven by software
2899 * : | | writing to the VIOCTRL[1] register. The
2900 * : | | VIO1-related fields in the hwctrl register are
2901 * : | | active but don't effect the VIO1 freeze signals.
2902 * ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW | 0x1 | VIO1 freeze signals are driven by the hardware
2903 * : | | state machine in the Freeze Controller. The
2904 * : | | VIO1-related fields in the hwctrl register are
2905 * : | | active and effect the VIO1 freeze signals.
2906 *
2907 * Field Access Macros:
2908 *
2909 */
2910/*
2911 * Enumerated value for register field ALT_SYSMGR_FRZCTL_SRC_VIO1
2912 *
2913 * VIO1 freeze signals are driven by software writing to the VIOCTRL[1] register.
2914 * The VIO1-related fields in the hwctrl register are active but don't effect the
2915 * VIO1 freeze signals.
2916 */
2917#define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW 0x0
2918/*
2919 * Enumerated value for register field ALT_SYSMGR_FRZCTL_SRC_VIO1
2920 *
2921 * VIO1 freeze signals are driven by the hardware state machine in the Freeze
2922 * Controller. The VIO1-related fields in the hwctrl register are active and effect
2923 * the VIO1 freeze signals.
2924 */
2925#define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW 0x1
2926
2927/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */
2928#define ALT_SYSMGR_FRZCTL_SRC_VIO1_LSB 0
2929/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */
2930#define ALT_SYSMGR_FRZCTL_SRC_VIO1_MSB 0
2931/* The width in bits of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */
2932#define ALT_SYSMGR_FRZCTL_SRC_VIO1_WIDTH 1
2933/* The mask used to set the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value. */
2934#define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET_MSK 0x00000001
2935/* The mask used to clear the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value. */
2936#define ALT_SYSMGR_FRZCTL_SRC_VIO1_CLR_MSK 0xfffffffe
2937/* The reset value of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */
2938#define ALT_SYSMGR_FRZCTL_SRC_VIO1_RESET 0x0
2939/* Extracts the ALT_SYSMGR_FRZCTL_SRC_VIO1 field value from a register. */
2940#define ALT_SYSMGR_FRZCTL_SRC_VIO1_GET(value) (((value) & 0x00000001) >> 0)
2941/* Produces a ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value suitable for setting the register. */
2942#define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET(value) (((value) << 0) & 0x00000001)
2943
2944#ifndef __ASSEMBLY__
2945/*
2946 * WARNING: The C register and register group struct declarations are provided for
2947 * convenience and illustrative purposes. They should, however, be used with
2948 * caution as the C language standard provides no guarantees about the alignment or
2949 * atomicity of device memory accesses. The recommended practice for writing
2950 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2951 * alt_write_word() functions.
2952 *
2953 * The struct declaration for register ALT_SYSMGR_FRZCTL_SRC.
2954 */
2955 struct ALT_SYSMGR_FRZCTL_SRC_s
2956{
2957 uint32_t vio1 : 1; /* VIO1 Freeze Signal Source */
2958 uint32_t : 31; /* *UNDEFINED* */
2959};
2960
2961/* The typedef declaration for register ALT_SYSMGR_FRZCTL_SRC. */
2962typedef volatile struct ALT_SYSMGR_FRZCTL_SRC_s ALT_SYSMGR_FRZCTL_SRC_t;
2963#endif /* __ASSEMBLY__ */
2964
2965/* The byte offset of the ALT_SYSMGR_FRZCTL_SRC register from the beginning of the component. */
2966#define ALT_SYSMGR_FRZCTL_SRC_OFST 0x14
2967
2968/*
2969 * Register : Hardware Control Register - hwctrl
2970 *
2971 * Activate freeze or thaw operations on VIO channel 1 (HPS IO bank 2 and bank 3)
2972 * and monitor for completeness and the current state.
2973 *
2974 * These fields interact with the hardware state machine in the Freeze Controller.
2975 * These fields can be accessed independent of the value of SRC1.VIO1 although they
2976 * only have an effect on the VIO channel 1 freeze signals when SRC1.VIO1 is setup
2977 * to have the hardware state machine be the freeze signal source.
2978 *
2979 * All fields are only reset by a cold reset (ignore warm reset).
2980 *
2981 * Register Layout
2982 *
2983 * Bits | Access | Reset | Description
2984 * :-------|:-------|:------|:----------------------------------
2985 * [0] | RW | 0x1 | VIO channel 1 Freeze/Thaw request
2986 * [2:1] | R | 0x2 | VIO channel 1 State
2987 * [31:3] | ??? | 0x0 | *UNDEFINED*
2988 *
2989 */
2990/*
2991 * Field : VIO channel 1 Freeze/Thaw request - vio1req
2992 *
2993 * Requests hardware state machine to generate freeze signal sequence to transition
2994 * between frozen and thawed states.
2995 *
2996 * If this field is read by software, it contains the value previously written by
2997 * software (i.e. this field is not written by hardware).
2998 *
2999 * Field Enumeration Values:
3000 *
3001 * Enum | Value | Description
3002 * :------------------------------------------|:------|:--------------------------------------
3003 * ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW | 0x0 | Requests a thaw (unfreeze) operation.
3004 * ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ | 0x1 | Requests a freeze operation.
3005 *
3006 * Field Access Macros:
3007 *
3008 */
3009/*
3010 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ
3011 *
3012 * Requests a thaw (unfreeze) operation.
3013 */
3014#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW 0x0
3015/*
3016 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ
3017 *
3018 * Requests a freeze operation.
3019 */
3020#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ 0x1
3021
3022/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */
3023#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_LSB 0
3024/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */
3025#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_MSB 0
3026/* The width in bits of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */
3027#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_WIDTH 1
3028/* The mask used to set the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value. */
3029#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET_MSK 0x00000001
3030/* The mask used to clear the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value. */
3031#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_CLR_MSK 0xfffffffe
3032/* The reset value of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */
3033#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_RESET 0x1
3034/* Extracts the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ field value from a register. */
3035#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_GET(value) (((value) & 0x00000001) >> 0)
3036/* Produces a ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value suitable for setting the register. */
3037#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET(value) (((value) << 0) & 0x00000001)
3038
3039/*
3040 * Field : VIO channel 1 State - vio1state
3041 *
3042 * Software reads this field to determine the current frozen/thawed state of the
3043 * VIO channel 1 or to determine when a freeze/thaw request is made by writing the
3044 * corresponding *REQ field in this register has completed.
3045 *
3046 * Reset by a cold reset (ignores warm reset).
3047 *
3048 * Field Enumeration Values:
3049 *
3050 * Enum | Value | Description
3051 * :--------------------------------------------------|:------|:-------------------------------------------------
3052 * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN | 0x0 | Transitioning from thawed state to frozen state.
3053 * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED | 0x1 | Thawed state. I/Os behave as configured. I/Os
3054 * : | | must be configured by the Scan Manager before
3055 * : | | entering this state.
3056 * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN | 0x2 | Frozen state. I/O configuration is ignored.
3057 * : | | Instead, I/Os are in tri-state mode with a weak
3058 * : | | pull-up. Scan Manager can be used to configure
3059 * : | | the I/Os while they are frozen.
3060 * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED | 0x3 | Transitioning from frozen state to thawed state.
3061 *
3062 * Field Access Macros:
3063 *
3064 */
3065/*
3066 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE
3067 *
3068 * Transitioning from thawed state to frozen state.
3069 */
3070#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN 0x0
3071/*
3072 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE
3073 *
3074 * Thawed state. I/Os behave as configured. I/Os must be configured by the Scan
3075 * Manager before entering this state.
3076 */
3077#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED 0x1
3078/*
3079 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE
3080 *
3081 * Frozen state. I/O configuration is ignored. Instead, I/Os are in tri-state mode
3082 * with a weak pull-up. Scan Manager can be used to configure the I/Os while they
3083 * are frozen.
3084 */
3085#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN 0x2
3086/*
3087 * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE
3088 *
3089 * Transitioning from frozen state to thawed state.
3090 */
3091#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED 0x3
3092
3093/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */
3094#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_LSB 1
3095/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */
3096#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_MSB 2
3097/* The width in bits of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */
3098#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_WIDTH 2
3099/* The mask used to set the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value. */
3100#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET_MSK 0x00000006
3101/* The mask used to clear the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value. */
3102#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_CLR_MSK 0xfffffff9
3103/* The reset value of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */
3104#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_RESET 0x2
3105/* Extracts the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE field value from a register. */
3106#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_GET(value) (((value) & 0x00000006) >> 1)
3107/* Produces a ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value suitable for setting the register. */
3108#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET(value) (((value) << 1) & 0x00000006)
3109
3110#ifndef __ASSEMBLY__
3111/*
3112 * WARNING: The C register and register group struct declarations are provided for
3113 * convenience and illustrative purposes. They should, however, be used with
3114 * caution as the C language standard provides no guarantees about the alignment or
3115 * atomicity of device memory accesses. The recommended practice for writing
3116 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3117 * alt_write_word() functions.
3118 *
3119 * The struct declaration for register ALT_SYSMGR_FRZCTL_HWCTL.
3120 */
3121 struct ALT_SYSMGR_FRZCTL_HWCTL_s
3122{
3123 uint32_t vio1req : 1; /* VIO channel 1 Freeze/Thaw request */
3124 const uint32_t vio1state : 2; /* VIO channel 1 State */
3125 uint32_t : 29; /* *UNDEFINED* */
3126};
3127
3128/* The typedef declaration for register ALT_SYSMGR_FRZCTL_HWCTL. */
3129typedef volatile struct ALT_SYSMGR_FRZCTL_HWCTL_s ALT_SYSMGR_FRZCTL_HWCTL_t;
3130#endif /* __ASSEMBLY__ */
3131
3132/* The byte offset of the ALT_SYSMGR_FRZCTL_HWCTL register from the beginning of the component. */
3133#define ALT_SYSMGR_FRZCTL_HWCTL_OFST 0x18
3134
3135#ifndef __ASSEMBLY__
3136/*
3137 * WARNING: The C register and register group struct declarations are provided for
3138 * convenience and illustrative purposes. They should, however, be used with
3139 * caution as the C language standard provides no guarantees about the alignment or
3140 * atomicity of device memory accesses. The recommended practice for writing
3141 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3142 * alt_write_word() functions.
3143 *
3144 * The struct declaration for register group ALT_SYSMGR_FRZCTL.
3145 */
3146 struct ALT_SYSMGR_FRZCTL_s
3147{
3148 volatile ALT_SYSMGR_FRZCTL_VIOCTL_t vioctrl[3]; /* ALT_SYSMGR_FRZCTL_VIOCTL */
3149 volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
3150 volatile ALT_SYSMGR_FRZCTL_HIOCTL_t hioctrl; /* ALT_SYSMGR_FRZCTL_HIOCTL */
3151 volatile ALT_SYSMGR_FRZCTL_SRC_t src; /* ALT_SYSMGR_FRZCTL_SRC */
3152 volatile ALT_SYSMGR_FRZCTL_HWCTL_t hwctrl; /* ALT_SYSMGR_FRZCTL_HWCTL */
3153 volatile uint32_t _pad_0x1c_0x20; /* *UNDEFINED* */
3154};
3155
3156/* The typedef declaration for register group ALT_SYSMGR_FRZCTL. */
3157typedef volatile struct ALT_SYSMGR_FRZCTL_s ALT_SYSMGR_FRZCTL_t;
3158/* The struct declaration for the raw register contents of register group ALT_SYSMGR_FRZCTL. */
3159 struct ALT_SYSMGR_FRZCTL_raw_s
3160{
3161 volatile uint32_t vioctrl[3]; /* ALT_SYSMGR_FRZCTL_VIOCTL */
3162 volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
3163 volatile uint32_t hioctrl; /* ALT_SYSMGR_FRZCTL_HIOCTL */
3164 volatile uint32_t src; /* ALT_SYSMGR_FRZCTL_SRC */
3165 volatile uint32_t hwctrl; /* ALT_SYSMGR_FRZCTL_HWCTL */
3166 volatile uint32_t _pad_0x1c_0x20; /* *UNDEFINED* */
3167};
3168
3169/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_FRZCTL. */
3170typedef volatile struct ALT_SYSMGR_FRZCTL_raw_s ALT_SYSMGR_FRZCTL_raw_t;
3171#endif /* __ASSEMBLY__ */
3172
3173
3174/*
3175 * Register Group : EMAC Group - ALT_SYSMGR_EMAC
3176 * EMAC Group
3177 *
3178 * External control registers for the EMACs
3179 *
3180 */
3181/*
3182 * Register : Control Register - ctrl
3183 *
3184 * Registers used by the EMACs. All fields are reset by a cold or warm reset.
3185 *
3186 * Register Layout
3187 *
3188 * Bits | Access | Reset | Description
3189 * :-------|:-------|:------|:---------------------
3190 * [1:0] | RW | 0x2 | PHY Interface Select
3191 * [3:2] | RW | 0x2 | PHY Interface Select
3192 * [4] | RW | 0x0 | PTP Clock Select
3193 * [5] | RW | 0x0 | PTP Clock Select
3194 * [31:6] | ??? | 0x0 | *UNDEFINED*
3195 *
3196 */
3197/*
3198 * Field : PHY Interface Select - physel_0
3199 *
3200 * Controls the PHY interface selection of the EMACs. This is sampled by an EMAC
3201 * module when it exits from reset. The associated enum defines the allowed values.
3202 * The field array index corresponds to the EMAC index.
3203 *
3204 * Field Enumeration Values:
3205 *
3206 * Enum | Value | Description
3207 * :----------------------------------------|:------|:------------------------------
3208 * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII | 0x0 | Select GMII/MII PHY interface
3209 * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII | 0x1 | Select RGMII PHY interface
3210 * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII | 0x2 | Select RMII PHY interface
3211 *
3212 * Field Access Macros:
3213 *
3214 */
3215/*
3216 * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0
3217 *
3218 * Select GMII/MII PHY interface
3219 */
3220#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII 0x0
3221/*
3222 * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0
3223 *
3224 * Select RGMII PHY interface
3225 */
3226#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII 0x1
3227/*
3228 * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0
3229 *
3230 * Select RMII PHY interface
3231 */
3232#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII 0x2
3233
3234/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */
3235#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_LSB 0
3236/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */
3237#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_MSB 1
3238/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */
3239#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_WIDTH 2
3240/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value. */
3241#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET_MSK 0x00000003
3242/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value. */
3243#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_CLR_MSK 0xfffffffc
3244/* The reset value of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */
3245#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_RESET 0x2
3246/* Extracts the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 field value from a register. */
3247#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_GET(value) (((value) & 0x00000003) >> 0)
3248/* Produces a ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value suitable for setting the register. */
3249#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET(value) (((value) << 0) & 0x00000003)
3250
3251/*
3252 * Field : PHY Interface Select - physel_1
3253 *
3254 * Controls the PHY interface selection of the EMACs. This is sampled by an EMAC
3255 * module when it exits from reset. The associated enum defines the allowed values.
3256 * The field array index corresponds to the EMAC index.
3257 *
3258 * Field Enumeration Values:
3259 *
3260 * Enum | Value | Description
3261 * :----------------------------------------|:------|:------------------------------
3262 * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII | 0x0 | Select GMII/MII PHY interface
3263 * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII | 0x1 | Select RGMII PHY interface
3264 * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII | 0x2 | Select RMII PHY interface
3265 *
3266 * Field Access Macros:
3267 *
3268 */
3269/*
3270 * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1
3271 *
3272 * Select GMII/MII PHY interface
3273 */
3274#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII 0x0
3275/*
3276 * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1
3277 *
3278 * Select RGMII PHY interface
3279 */
3280#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII 0x1
3281/*
3282 * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1
3283 *
3284 * Select RMII PHY interface
3285 */
3286#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII 0x2
3287
3288/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */
3289#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_LSB 2
3290/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */
3291#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_MSB 3
3292/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */
3293#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_WIDTH 2
3294/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value. */
3295#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET_MSK 0x0000000c
3296/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value. */
3297#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_CLR_MSK 0xfffffff3
3298/* The reset value of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */
3299#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_RESET 0x2
3300/* Extracts the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 field value from a register. */
3301#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_GET(value) (((value) & 0x0000000c) >> 2)
3302/* Produces a ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value suitable for setting the register. */
3303#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET(value) (((value) << 2) & 0x0000000c)
3304
3305/*
3306 * Field : PTP Clock Select - ptpclksel_0
3307 *
3308 * Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC
3309 * module when it exits from reset. The field array index corresponds to the EMAC
3310 * index.
3311 *
3312 * Field Enumeration Values:
3313 *
3314 * Enum | Value | Description
3315 * :---------------------------------------------------|:------|:-------------------------
3316 * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK | 0x0 | Selects osc1_clk
3317 * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK | 0x1 | Selects fpga_ptp_ref_clk
3318 *
3319 * Field Access Macros:
3320 *
3321 */
3322/*
3323 * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0
3324 *
3325 * Selects osc1_clk
3326 */
3327#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK 0x0
3328/*
3329 * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0
3330 *
3331 * Selects fpga_ptp_ref_clk
3332 */
3333#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK 0x1
3334
3335/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */
3336#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_LSB 4
3337/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */
3338#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_MSB 4
3339/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */
3340#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_WIDTH 1
3341/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value. */
3342#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET_MSK 0x00000010
3343/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value. */
3344#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_CLR_MSK 0xffffffef
3345/* The reset value of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */
3346#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_RESET 0x0
3347/* Extracts the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 field value from a register. */
3348#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_GET(value) (((value) & 0x00000010) >> 4)
3349/* Produces a ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value suitable for setting the register. */
3350#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET(value) (((value) << 4) & 0x00000010)
3351
3352/*
3353 * Field : PTP Clock Select - ptpclksel_1
3354 *
3355 * Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC
3356 * module when it exits from reset. The field array index corresponds to the EMAC
3357 * index.
3358 *
3359 * Field Enumeration Values:
3360 *
3361 * Enum | Value | Description
3362 * :---------------------------------------------------|:------|:-------------------------
3363 * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK | 0x0 | Selects osc1_clk
3364 * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK | 0x1 | Selects fpga_ptp_ref_clk
3365 *
3366 * Field Access Macros:
3367 *
3368 */
3369/*
3370 * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1
3371 *
3372 * Selects osc1_clk
3373 */
3374#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK 0x0
3375/*
3376 * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1
3377 *
3378 * Selects fpga_ptp_ref_clk
3379 */
3380#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK 0x1
3381
3382/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */
3383#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_LSB 5
3384/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */
3385#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_MSB 5
3386/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */
3387#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_WIDTH 1
3388/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value. */
3389#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET_MSK 0x00000020
3390/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value. */
3391#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_CLR_MSK 0xffffffdf
3392/* The reset value of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */
3393#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_RESET 0x0
3394/* Extracts the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 field value from a register. */
3395#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_GET(value) (((value) & 0x00000020) >> 5)
3396/* Produces a ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value suitable for setting the register. */
3397#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET(value) (((value) << 5) & 0x00000020)
3398
3399#ifndef __ASSEMBLY__
3400/*
3401 * WARNING: The C register and register group struct declarations are provided for
3402 * convenience and illustrative purposes. They should, however, be used with
3403 * caution as the C language standard provides no guarantees about the alignment or
3404 * atomicity of device memory accesses. The recommended practice for writing
3405 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3406 * alt_write_word() functions.
3407 *
3408 * The struct declaration for register ALT_SYSMGR_EMAC_CTL.
3409 */
3410 struct ALT_SYSMGR_EMAC_CTL_s
3411{
3412 uint32_t physel_0 : 2; /* PHY Interface Select */
3413 uint32_t physel_1 : 2; /* PHY Interface Select */
3414 uint32_t ptpclksel_0 : 1; /* PTP Clock Select */
3415 uint32_t ptpclksel_1 : 1; /* PTP Clock Select */
3416 uint32_t : 26; /* *UNDEFINED* */
3417};
3418
3419/* The typedef declaration for register ALT_SYSMGR_EMAC_CTL. */
3420typedef volatile struct ALT_SYSMGR_EMAC_CTL_s ALT_SYSMGR_EMAC_CTL_t;
3421#endif /* __ASSEMBLY__ */
3422
3423/* The byte offset of the ALT_SYSMGR_EMAC_CTL register from the beginning of the component. */
3424#define ALT_SYSMGR_EMAC_CTL_OFST 0x0
3425
3426/*
3427 * Register : EMAC L3 Master AxCACHE Register - l3master
3428 *
3429 * Controls the L3 master ARCACHE and AWCACHE AXI signals.
3430 *
3431 * These register bits should be updated only during system initialization prior to
3432 * removing the peripheral from reset. They may not be changed dynamically during
3433 * peripheral operation
3434 *
3435 * All fields are reset by a cold or warm reset.
3436 *
3437 * Register Layout
3438 *
3439 * Bits | Access | Reset | Description
3440 * :--------|:-------|:------|:-------------
3441 * [3:0] | RW | 0x0 | EMAC ARCACHE
3442 * [7:4] | RW | 0x0 | EMAC ARCACHE
3443 * [11:8] | RW | 0x0 | EMAC AWCACHE
3444 * [15:12] | RW | 0x0 | EMAC AWCACHE
3445 * [31:16] | ??? | 0x0 | *UNDEFINED*
3446 *
3447 */
3448/*
3449 * Field : EMAC ARCACHE - arcache_0
3450 *
3451 * Specifies the values of the 2 EMAC ARCACHE signals.
3452 *
3453 * The field array index corresponds to the EMAC index.
3454 *
3455 * Field Enumeration Values:
3456 *
3457 * Enum | Value | Description
3458 * :-------------------------------------------------------|:------|:-------------------------------------------------
3459 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable.
3460 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF | 0x1 | Bufferable only.
3461 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate.
3462 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate.
3463 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1 | 0x4 | Reserved.
3464 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2 | 0x5 | Reserved.
3465 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only.
3466 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only.
3467 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3 | 0x8 | Reserved.
3468 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4 | 0x9 | Reserved.
3469 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes
3470 * : | | only.
3471 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only.
3472 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5 | 0xc | Reserved.
3473 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6 | 0xd | Reserved.
3474 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads
3475 * : | | and writes.
3476 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and
3477 * : | | writes.
3478 *
3479 * Field Access Macros:
3480 *
3481 */
3482/*
3483 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3484 *
3485 * Noncacheable and nonbufferable.
3486 */
3487#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0
3488/*
3489 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3490 *
3491 * Bufferable only.
3492 */
3493#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF 0x1
3494/*
3495 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3496 *
3497 * Cacheable, but do not allocate.
3498 */
3499#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2
3500/*
3501 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3502 *
3503 * Cacheable and bufferable, but do not allocate.
3504 */
3505#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
3506/*
3507 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3508 *
3509 * Reserved.
3510 */
3511#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1 0x4
3512/*
3513 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3514 *
3515 * Reserved.
3516 */
3517#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2 0x5
3518/*
3519 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3520 *
3521 * Cacheable write-through, allocate on reads only.
3522 */
3523#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
3524/*
3525 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3526 *
3527 * Cacheable write-back, allocate on reads only.
3528 */
3529#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
3530/*
3531 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3532 *
3533 * Reserved.
3534 */
3535#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3 0x8
3536/*
3537 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3538 *
3539 * Reserved.
3540 */
3541#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4 0x9
3542/*
3543 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3544 *
3545 * Cacheable write-through, allocate on writes only.
3546 */
3547#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
3548/*
3549 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3550 *
3551 * Cacheable write-back, allocate on writes only.
3552 */
3553#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
3554/*
3555 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3556 *
3557 * Reserved.
3558 */
3559#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5 0xc
3560/*
3561 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3562 *
3563 * Reserved.
3564 */
3565#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6 0xd
3566/*
3567 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3568 *
3569 * Cacheable write-through, allocate on both reads and writes.
3570 */
3571#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
3572/*
3573 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3574 *
3575 * Cacheable write-back, allocate on both reads and writes.
3576 */
3577#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
3578
3579/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */
3580#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_LSB 0
3581/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */
3582#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_MSB 3
3583/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */
3584#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_WIDTH 4
3585/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value. */
3586#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET_MSK 0x0000000f
3587/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value. */
3588#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0
3589/* The reset value of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */
3590#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_RESET 0x0
3591/* Extracts the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 field value from a register. */
3592#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0)
3593/* Produces a ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value suitable for setting the register. */
3594#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f)
3595
3596/*
3597 * Field : EMAC ARCACHE - arcache_1
3598 *
3599 * Specifies the values of the 2 EMAC ARCACHE signals.
3600 *
3601 * The field array index corresponds to the EMAC index.
3602 *
3603 * Field Enumeration Values:
3604 *
3605 * Enum | Value | Description
3606 * :-------------------------------------------------------|:------|:-------------------------------------------------
3607 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable.
3608 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF | 0x1 | Bufferable only.
3609 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate.
3610 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate.
3611 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1 | 0x4 | Reserved.
3612 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2 | 0x5 | Reserved.
3613 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only.
3614 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only.
3615 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3 | 0x8 | Reserved.
3616 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4 | 0x9 | Reserved.
3617 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes
3618 * : | | only.
3619 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only.
3620 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5 | 0xc | Reserved.
3621 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6 | 0xd | Reserved.
3622 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads
3623 * : | | and writes.
3624 * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and
3625 * : | | writes.
3626 *
3627 * Field Access Macros:
3628 *
3629 */
3630/*
3631 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3632 *
3633 * Noncacheable and nonbufferable.
3634 */
3635#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF 0x0
3636/*
3637 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3638 *
3639 * Bufferable only.
3640 */
3641#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF 0x1
3642/*
3643 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3644 *
3645 * Cacheable, but do not allocate.
3646 */
3647#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC 0x2
3648/*
3649 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3650 *
3651 * Cacheable and bufferable, but do not allocate.
3652 */
3653#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC 0x3
3654/*
3655 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3656 *
3657 * Reserved.
3658 */
3659#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1 0x4
3660/*
3661 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3662 *
3663 * Reserved.
3664 */
3665#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2 0x5
3666/*
3667 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3668 *
3669 * Cacheable write-through, allocate on reads only.
3670 */
3671#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6
3672/*
3673 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3674 *
3675 * Cacheable write-back, allocate on reads only.
3676 */
3677#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7
3678/*
3679 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3680 *
3681 * Reserved.
3682 */
3683#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3 0x8
3684/*
3685 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3686 *
3687 * Reserved.
3688 */
3689#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4 0x9
3690/*
3691 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3692 *
3693 * Cacheable write-through, allocate on writes only.
3694 */
3695#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa
3696/*
3697 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3698 *
3699 * Cacheable write-back, allocate on writes only.
3700 */
3701#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb
3702/*
3703 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3704 *
3705 * Reserved.
3706 */
3707#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5 0xc
3708/*
3709 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3710 *
3711 * Reserved.
3712 */
3713#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6 0xd
3714/*
3715 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3716 *
3717 * Cacheable write-through, allocate on both reads and writes.
3718 */
3719#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe
3720/*
3721 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3722 *
3723 * Cacheable write-back, allocate on both reads and writes.
3724 */
3725#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC 0xf
3726
3727/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */
3728#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_LSB 4
3729/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */
3730#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_MSB 7
3731/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */
3732#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_WIDTH 4
3733/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value. */
3734#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET_MSK 0x000000f0
3735/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value. */
3736#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_CLR_MSK 0xffffff0f
3737/* The reset value of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */
3738#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_RESET 0x0
3739/* Extracts the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 field value from a register. */
3740#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_GET(value) (((value) & 0x000000f0) >> 4)
3741/* Produces a ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value suitable for setting the register. */
3742#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET(value) (((value) << 4) & 0x000000f0)
3743
3744/*
3745 * Field : EMAC AWCACHE - awcache_0
3746 *
3747 * Specifies the values of the 2 EMAC AWCACHE signals.
3748 *
3749 * The field array index corresponds to the EMAC index.
3750 *
3751 * Field Enumeration Values:
3752 *
3753 * Enum | Value | Description
3754 * :-------------------------------------------------------|:------|:-------------------------------------------------
3755 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable.
3756 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF | 0x1 | Bufferable only.
3757 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate.
3758 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate.
3759 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1 | 0x4 | Reserved.
3760 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2 | 0x5 | Reserved.
3761 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only.
3762 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only.
3763 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3 | 0x8 | Reserved.
3764 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4 | 0x9 | Reserved.
3765 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes
3766 * : | | only.
3767 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only.
3768 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5 | 0xc | Reserved.
3769 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6 | 0xd | Reserved.
3770 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads
3771 * : | | and writes.
3772 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and
3773 * : | | writes.
3774 *
3775 * Field Access Macros:
3776 *
3777 */
3778/*
3779 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3780 *
3781 * Noncacheable and nonbufferable.
3782 */
3783#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0
3784/*
3785 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3786 *
3787 * Bufferable only.
3788 */
3789#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF 0x1
3790/*
3791 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3792 *
3793 * Cacheable, but do not allocate.
3794 */
3795#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2
3796/*
3797 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3798 *
3799 * Cacheable and bufferable, but do not allocate.
3800 */
3801#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
3802/*
3803 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3804 *
3805 * Reserved.
3806 */
3807#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1 0x4
3808/*
3809 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3810 *
3811 * Reserved.
3812 */
3813#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2 0x5
3814/*
3815 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3816 *
3817 * Cacheable write-through, allocate on reads only.
3818 */
3819#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
3820/*
3821 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3822 *
3823 * Cacheable write-back, allocate on reads only.
3824 */
3825#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
3826/*
3827 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3828 *
3829 * Reserved.
3830 */
3831#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3 0x8
3832/*
3833 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3834 *
3835 * Reserved.
3836 */
3837#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4 0x9
3838/*
3839 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3840 *
3841 * Cacheable write-through, allocate on writes only.
3842 */
3843#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
3844/*
3845 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3846 *
3847 * Cacheable write-back, allocate on writes only.
3848 */
3849#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
3850/*
3851 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3852 *
3853 * Reserved.
3854 */
3855#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5 0xc
3856/*
3857 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3858 *
3859 * Reserved.
3860 */
3861#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6 0xd
3862/*
3863 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3864 *
3865 * Cacheable write-through, allocate on both reads and writes.
3866 */
3867#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
3868/*
3869 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3870 *
3871 * Cacheable write-back, allocate on both reads and writes.
3872 */
3873#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
3874
3875/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */
3876#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_LSB 8
3877/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */
3878#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_MSB 11
3879/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */
3880#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_WIDTH 4
3881/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value. */
3882#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET_MSK 0x00000f00
3883/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value. */
3884#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_CLR_MSK 0xfffff0ff
3885/* The reset value of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */
3886#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_RESET 0x0
3887/* Extracts the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 field value from a register. */
3888#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_GET(value) (((value) & 0x00000f00) >> 8)
3889/* Produces a ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value suitable for setting the register. */
3890#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET(value) (((value) << 8) & 0x00000f00)
3891
3892/*
3893 * Field : EMAC AWCACHE - awcache_1
3894 *
3895 * Specifies the values of the 2 EMAC AWCACHE signals.
3896 *
3897 * The field array index corresponds to the EMAC index.
3898 *
3899 * Field Enumeration Values:
3900 *
3901 * Enum | Value | Description
3902 * :-------------------------------------------------------|:------|:-------------------------------------------------
3903 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable.
3904 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF | 0x1 | Bufferable only.
3905 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate.
3906 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate.
3907 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1 | 0x4 | Reserved.
3908 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2 | 0x5 | Reserved.
3909 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only.
3910 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only.
3911 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3 | 0x8 | Reserved.
3912 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4 | 0x9 | Reserved.
3913 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes
3914 * : | | only.
3915 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only.
3916 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5 | 0xc | Reserved.
3917 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6 | 0xd | Reserved.
3918 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads
3919 * : | | and writes.
3920 * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and
3921 * : | | writes.
3922 *
3923 * Field Access Macros:
3924 *
3925 */
3926/*
3927 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3928 *
3929 * Noncacheable and nonbufferable.
3930 */
3931#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF 0x0
3932/*
3933 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3934 *
3935 * Bufferable only.
3936 */
3937#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF 0x1
3938/*
3939 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3940 *
3941 * Cacheable, but do not allocate.
3942 */
3943#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC 0x2
3944/*
3945 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3946 *
3947 * Cacheable and bufferable, but do not allocate.
3948 */
3949#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC 0x3
3950/*
3951 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3952 *
3953 * Reserved.
3954 */
3955#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1 0x4
3956/*
3957 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3958 *
3959 * Reserved.
3960 */
3961#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2 0x5
3962/*
3963 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3964 *
3965 * Cacheable write-through, allocate on reads only.
3966 */
3967#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6
3968/*
3969 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3970 *
3971 * Cacheable write-back, allocate on reads only.
3972 */
3973#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7
3974/*
3975 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3976 *
3977 * Reserved.
3978 */
3979#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3 0x8
3980/*
3981 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3982 *
3983 * Reserved.
3984 */
3985#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4 0x9
3986/*
3987 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3988 *
3989 * Cacheable write-through, allocate on writes only.
3990 */
3991#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa
3992/*
3993 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3994 *
3995 * Cacheable write-back, allocate on writes only.
3996 */
3997#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb
3998/*
3999 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
4000 *
4001 * Reserved.
4002 */
4003#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5 0xc
4004/*
4005 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
4006 *
4007 * Reserved.
4008 */
4009#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6 0xd
4010/*
4011 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
4012 *
4013 * Cacheable write-through, allocate on both reads and writes.
4014 */
4015#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe
4016/*
4017 * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
4018 *
4019 * Cacheable write-back, allocate on both reads and writes.
4020 */
4021#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC 0xf
4022
4023/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */
4024#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_LSB 12
4025/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */
4026#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_MSB 15
4027/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */
4028#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_WIDTH 4
4029/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value. */
4030#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET_MSK 0x0000f000
4031/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value. */
4032#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_CLR_MSK 0xffff0fff
4033/* The reset value of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */
4034#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_RESET 0x0
4035/* Extracts the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 field value from a register. */
4036#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_GET(value) (((value) & 0x0000f000) >> 12)
4037/* Produces a ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value suitable for setting the register. */
4038#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET(value) (((value) << 12) & 0x0000f000)
4039
4040#ifndef __ASSEMBLY__
4041/*
4042 * WARNING: The C register and register group struct declarations are provided for
4043 * convenience and illustrative purposes. They should, however, be used with
4044 * caution as the C language standard provides no guarantees about the alignment or
4045 * atomicity of device memory accesses. The recommended practice for writing
4046 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4047 * alt_write_word() functions.
4048 *
4049 * The struct declaration for register ALT_SYSMGR_EMAC_L3MST.
4050 */
4051 struct ALT_SYSMGR_EMAC_L3MST_s
4052{
4053 uint32_t arcache_0 : 4; /* EMAC ARCACHE */
4054 uint32_t arcache_1 : 4; /* EMAC ARCACHE */
4055 uint32_t awcache_0 : 4; /* EMAC AWCACHE */
4056 uint32_t awcache_1 : 4; /* EMAC AWCACHE */
4057 uint32_t : 16; /* *UNDEFINED* */
4058};
4059
4060/* The typedef declaration for register ALT_SYSMGR_EMAC_L3MST. */
4061typedef volatile struct ALT_SYSMGR_EMAC_L3MST_s ALT_SYSMGR_EMAC_L3MST_t;
4062#endif /* __ASSEMBLY__ */
4063
4064/* The byte offset of the ALT_SYSMGR_EMAC_L3MST register from the beginning of the component. */
4065#define ALT_SYSMGR_EMAC_L3MST_OFST 0x4
4066
4067#ifndef __ASSEMBLY__
4068/*
4069 * WARNING: The C register and register group struct declarations are provided for
4070 * convenience and illustrative purposes. They should, however, be used with
4071 * caution as the C language standard provides no guarantees about the alignment or
4072 * atomicity of device memory accesses. The recommended practice for writing
4073 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4074 * alt_write_word() functions.
4075 *
4076 * The struct declaration for register group ALT_SYSMGR_EMAC.
4077 */
4078 struct ALT_SYSMGR_EMAC_s
4079{
4080 volatile ALT_SYSMGR_EMAC_CTL_t ctrl; /* ALT_SYSMGR_EMAC_CTL */
4081 volatile ALT_SYSMGR_EMAC_L3MST_t l3master; /* ALT_SYSMGR_EMAC_L3MST */
4082 volatile uint32_t _pad_0x8_0x10[2]; /* *UNDEFINED* */
4083};
4084
4085/* The typedef declaration for register group ALT_SYSMGR_EMAC. */
4086typedef volatile struct ALT_SYSMGR_EMAC_s ALT_SYSMGR_EMAC_t;
4087/* The struct declaration for the raw register contents of register group ALT_SYSMGR_EMAC. */
4088 struct ALT_SYSMGR_EMAC_raw_s
4089{
4090 volatile uint32_t ctrl; /* ALT_SYSMGR_EMAC_CTL */
4091 volatile uint32_t l3master; /* ALT_SYSMGR_EMAC_L3MST */
4092 volatile uint32_t _pad_0x8_0x10[2]; /* *UNDEFINED* */
4093};
4094
4095/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_EMAC. */
4096typedef volatile struct ALT_SYSMGR_EMAC_raw_s ALT_SYSMGR_EMAC_raw_t;
4097#endif /* __ASSEMBLY__ */
4098
4099
4100/*
4101 * Register Group : DMA Controller Group - ALT_SYSMGR_DMA
4102 * DMA Controller Group
4103 *
4104 * Registers used by the DMA Controller to enable secured system support and select
4105 * DMA channels.
4106 *
4107 */
4108/*
4109 * Register : Control Register - ctrl
4110 *
4111 * Registers used by the DMA Controller. All fields are reset by a cold or warm
4112 * reset.
4113 *
4114 * These register bits should be updated during system initialization prior to
4115 * removing the DMA controller from reset. They may not be changed dynamically
4116 * during DMA operation.
4117 *
4118 * Register Layout
4119 *
4120 * Bits | Access | Reset | Description
4121 * :--------|:-------|:------|:------------------------
4122 * [0] | RW | 0x0 | Channel Select
4123 * [1] | RW | 0x0 | Channel Select
4124 * [2] | RW | 0x0 | Channel Select
4125 * [3] | RW | 0x0 | Channel Select
4126 * [4] | RW | 0x0 | Manager Thread Security
4127 * [12:5] | RW | 0x0 | IRQ Security
4128 * [31:13] | ??? | 0x0 | *UNDEFINED*
4129 *
4130 */
4131/*
4132 * Field : Channel Select - chansel_0
4133 *
4134 * Controls mux that selects whether FPGA or CAN connects to one of the DMA
4135 * peripheral request interfaces.The peripheral request interface index equals the
4136 * array index + 4. For example, array index 0 is for peripheral request index 4.
4137 *
4138 * Field Enumeration Values:
4139 *
4140 * Enum | Value | Description
4141 * :------------------------------------|:------|:-----------------------------------------
4142 * ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA | 0x0 | FPGA drives peripheral request interface
4143 * ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN | 0x1 | CAN drives peripheral request interface
4144 *
4145 * Field Access Macros:
4146 *
4147 */
4148/*
4149 * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_0
4150 *
4151 * FPGA drives peripheral request interface
4152 */
4153#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA 0x0
4154/*
4155 * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_0
4156 *
4157 * CAN drives peripheral request interface
4158 */
4159#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN 0x1
4160
4161/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */
4162#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_LSB 0
4163/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */
4164#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_MSB 0
4165/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */
4166#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_WIDTH 1
4167/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value. */
4168#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET_MSK 0x00000001
4169/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value. */
4170#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_CLR_MSK 0xfffffffe
4171/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */
4172#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_RESET 0x0
4173/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_0 field value from a register. */
4174#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_GET(value) (((value) & 0x00000001) >> 0)
4175/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value suitable for setting the register. */
4176#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET(value) (((value) << 0) & 0x00000001)
4177
4178/*
4179 * Field : Channel Select - chansel_1
4180 *
4181 * Controls mux that selects whether FPGA or CAN connects to one of the DMA
4182 * peripheral request interfaces.The peripheral request interface index equals the
4183 * array index + 4. For example, array index 0 is for peripheral request index 4.
4184 *
4185 * Field Enumeration Values:
4186 *
4187 * Enum | Value | Description
4188 * :------------------------------------|:------|:-----------------------------------------
4189 * ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA | 0x0 | FPGA drives peripheral request interface
4190 * ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN | 0x1 | CAN drives peripheral request interface
4191 *
4192 * Field Access Macros:
4193 *
4194 */
4195/*
4196 * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_1
4197 *
4198 * FPGA drives peripheral request interface
4199 */
4200#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA 0x0
4201/*
4202 * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_1
4203 *
4204 * CAN drives peripheral request interface
4205 */
4206#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN 0x1
4207
4208/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */
4209#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_LSB 1
4210/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */
4211#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_MSB 1
4212/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */
4213#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_WIDTH 1
4214/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value. */
4215#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET_MSK 0x00000002
4216/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value. */
4217#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_CLR_MSK 0xfffffffd
4218/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */
4219#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_RESET 0x0
4220/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_1 field value from a register. */
4221#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_GET(value) (((value) & 0x00000002) >> 1)
4222/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value suitable for setting the register. */
4223#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET(value) (((value) << 1) & 0x00000002)
4224
4225/*
4226 * Field : Channel Select - chansel_2
4227 *
4228 * Controls mux that selects whether FPGA or CAN connects to one of the DMA
4229 * peripheral request interfaces.The peripheral request interface index equals the
4230 * array index + 4. For example, array index 0 is for peripheral request index 4.
4231 *
4232 * Field Enumeration Values:
4233 *
4234 * Enum | Value | Description
4235 * :------------------------------------|:------|:-----------------------------------------
4236 * ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA | 0x0 | FPGA drives peripheral request interface
4237 * ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN | 0x1 | CAN drives peripheral request interface
4238 *
4239 * Field Access Macros:
4240 *
4241 */
4242/*
4243 * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_2
4244 *
4245 * FPGA drives peripheral request interface
4246 */
4247#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA 0x0
4248/*
4249 * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_2
4250 *
4251 * CAN drives peripheral request interface
4252 */
4253#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN 0x1
4254
4255/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */
4256#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_LSB 2
4257/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */
4258#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_MSB 2
4259/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */
4260#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_WIDTH 1
4261/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value. */
4262#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET_MSK 0x00000004
4263/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value. */
4264#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_CLR_MSK 0xfffffffb
4265/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */
4266#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_RESET 0x0
4267/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_2 field value from a register. */
4268#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_GET(value) (((value) & 0x00000004) >> 2)
4269/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value suitable for setting the register. */
4270#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET(value) (((value) << 2) & 0x00000004)
4271
4272/*
4273 * Field : Channel Select - chansel_3
4274 *
4275 * Controls mux that selects whether FPGA or CAN connects to one of the DMA
4276 * peripheral request interfaces.The peripheral request interface index equals the
4277 * array index + 4. For example, array index 0 is for peripheral request index 4.
4278 *
4279 * Field Enumeration Values:
4280 *
4281 * Enum | Value | Description
4282 * :------------------------------------|:------|:-----------------------------------------
4283 * ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA | 0x0 | FPGA drives peripheral request interface
4284 * ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN | 0x1 | CAN drives peripheral request interface
4285 *
4286 * Field Access Macros:
4287 *
4288 */
4289/*
4290 * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_3
4291 *
4292 * FPGA drives peripheral request interface
4293 */
4294#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA 0x0
4295/*
4296 * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_3
4297 *
4298 * CAN drives peripheral request interface
4299 */
4300#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN 0x1
4301
4302/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */
4303#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_LSB 3
4304/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */
4305#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_MSB 3
4306/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */
4307#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_WIDTH 1
4308/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value. */
4309#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET_MSK 0x00000008
4310/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value. */
4311#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_CLR_MSK 0xfffffff7
4312/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */
4313#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_RESET 0x0
4314/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_3 field value from a register. */
4315#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_GET(value) (((value) & 0x00000008) >> 3)
4316/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value suitable for setting the register. */
4317#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET(value) (((value) << 3) & 0x00000008)
4318
4319/*
4320 * Field : Manager Thread Security - mgrnonsecure
4321 *
4322 * Specifies the security state of the DMA manager thread.
4323 *
4324 * 0 = assigns DMA manager to the Secure state.
4325 *
4326 * 1 = assigns DMA manager to the Non-secure state.
4327 *
4328 * Sampled by the DMA controller when it exits from reset.
4329 *
4330 * Field Access Macros:
4331 *
4332 */
4333/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */
4334#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_LSB 4
4335/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */
4336#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_MSB 4
4337/* The width in bits of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */
4338#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_WIDTH 1
4339/* The mask used to set the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value. */
4340#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET_MSK 0x00000010
4341/* The mask used to clear the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value. */
4342#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_CLR_MSK 0xffffffef
4343/* The reset value of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */
4344#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_RESET 0x0
4345/* Extracts the ALT_SYSMGR_DMA_CTL_MGRNONSECURE field value from a register. */
4346#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_GET(value) (((value) & 0x00000010) >> 4)
4347/* Produces a ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value suitable for setting the register. */
4348#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET(value) (((value) << 4) & 0x00000010)
4349
4350/*
4351 * Field : IRQ Security - irqnonsecure
4352 *
4353 * Specifies the security state of an event-interrupt resource.
4354 *
4355 * If bit index [x] is 0, the DMAC assigns event<x> or irq[x] to the Secure state.
4356 *
4357 * If bit index [x] is 1, the DMAC assigns event<x> or irq[x] to the Non-secure
4358 * state.
4359 *
4360 * Field Access Macros:
4361 *
4362 */
4363/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */
4364#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_LSB 5
4365/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */
4366#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_MSB 12
4367/* The width in bits of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */
4368#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_WIDTH 8
4369/* The mask used to set the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value. */
4370#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET_MSK 0x00001fe0
4371/* The mask used to clear the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value. */
4372#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_CLR_MSK 0xffffe01f
4373/* The reset value of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */
4374#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_RESET 0x0
4375/* Extracts the ALT_SYSMGR_DMA_CTL_IRQNONSECURE field value from a register. */
4376#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_GET(value) (((value) & 0x00001fe0) >> 5)
4377/* Produces a ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value suitable for setting the register. */
4378#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET(value) (((value) << 5) & 0x00001fe0)
4379
4380#ifndef __ASSEMBLY__
4381/*
4382 * WARNING: The C register and register group struct declarations are provided for
4383 * convenience and illustrative purposes. They should, however, be used with
4384 * caution as the C language standard provides no guarantees about the alignment or
4385 * atomicity of device memory accesses. The recommended practice for writing
4386 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4387 * alt_write_word() functions.
4388 *
4389 * The struct declaration for register ALT_SYSMGR_DMA_CTL.
4390 */
4391 struct ALT_SYSMGR_DMA_CTL_s
4392{
4393 uint32_t chansel_0 : 1; /* Channel Select */
4394 uint32_t chansel_1 : 1; /* Channel Select */
4395 uint32_t chansel_2 : 1; /* Channel Select */
4396 uint32_t chansel_3 : 1; /* Channel Select */
4397 uint32_t mgrnonsecure : 1; /* Manager Thread Security */
4398 uint32_t irqnonsecure : 8; /* IRQ Security */
4399 uint32_t : 19; /* *UNDEFINED* */
4400};
4401
4402/* The typedef declaration for register ALT_SYSMGR_DMA_CTL. */
4403typedef volatile struct ALT_SYSMGR_DMA_CTL_s ALT_SYSMGR_DMA_CTL_t;
4404#endif /* __ASSEMBLY__ */
4405
4406/* The byte offset of the ALT_SYSMGR_DMA_CTL register from the beginning of the component. */
4407#define ALT_SYSMGR_DMA_CTL_OFST 0x0
4408
4409/*
4410 * Register : Peripheral Security Register - persecurity
4411 *
4412 * Controls the security state of a peripheral request interface. Sampled by the
4413 * DMA controller when it exits from reset.
4414 *
4415 * These register bits should be updated during system initialization prior to
4416 * removing the DMA controller from reset. They may not be changed dynamically
4417 * during DMA operation.
4418 *
4419 * Register Layout
4420 *
4421 * Bits | Access | Reset | Description
4422 * :-------|:-------|:------|:----------------------
4423 * [31:0] | RW | 0x0 | Peripheral Non-Secure
4424 *
4425 */
4426/*
4427 * Field : Peripheral Non-Secure - nonsecure
4428 *
4429 * If bit index [x] is 0, the DMA controller assigns peripheral request interface x
4430 * to the Secure state.
4431 *
4432 * If bit index [x] is 1, the DMA controller assigns peripheral request interface x
4433 * to the Non-secure state.
4434 *
4435 * Reset by a cold or warm reset.
4436 *
4437 * Field Access Macros:
4438 *
4439 */
4440/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */
4441#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_LSB 0
4442/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */
4443#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_MSB 31
4444/* The width in bits of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */
4445#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_WIDTH 32
4446/* The mask used to set the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value. */
4447#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET_MSK 0xffffffff
4448/* The mask used to clear the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value. */
4449#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_CLR_MSK 0x00000000
4450/* The reset value of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */
4451#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_RESET 0x0
4452/* Extracts the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE field value from a register. */
4453#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_GET(value) (((value) & 0xffffffff) >> 0)
4454/* Produces a ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value suitable for setting the register. */
4455#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET(value) (((value) << 0) & 0xffffffff)
4456
4457#ifndef __ASSEMBLY__
4458/*
4459 * WARNING: The C register and register group struct declarations are provided for
4460 * convenience and illustrative purposes. They should, however, be used with
4461 * caution as the C language standard provides no guarantees about the alignment or
4462 * atomicity of device memory accesses. The recommended practice for writing
4463 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4464 * alt_write_word() functions.
4465 *
4466 * The struct declaration for register ALT_SYSMGR_DMA_PERSECURITY.
4467 */
4468 struct ALT_SYSMGR_DMA_PERSECURITY_s
4469{
4470 uint32_t nonsecure : 32; /* Peripheral Non-Secure */
4471};
4472
4473/* The typedef declaration for register ALT_SYSMGR_DMA_PERSECURITY. */
4474typedef volatile struct ALT_SYSMGR_DMA_PERSECURITY_s ALT_SYSMGR_DMA_PERSECURITY_t;
4475#endif /* __ASSEMBLY__ */
4476
4477/* The byte offset of the ALT_SYSMGR_DMA_PERSECURITY register from the beginning of the component. */
4478#define ALT_SYSMGR_DMA_PERSECURITY_OFST 0x4
4479
4480#ifndef __ASSEMBLY__
4481/*
4482 * WARNING: The C register and register group struct declarations are provided for
4483 * convenience and illustrative purposes. They should, however, be used with
4484 * caution as the C language standard provides no guarantees about the alignment or
4485 * atomicity of device memory accesses. The recommended practice for writing
4486 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4487 * alt_write_word() functions.
4488 *
4489 * The struct declaration for register group ALT_SYSMGR_DMA.
4490 */
4491 struct ALT_SYSMGR_DMA_s
4492{
4493 volatile ALT_SYSMGR_DMA_CTL_t ctrl; /* ALT_SYSMGR_DMA_CTL */
4494 volatile ALT_SYSMGR_DMA_PERSECURITY_t persecurity; /* ALT_SYSMGR_DMA_PERSECURITY */
4495};
4496
4497/* The typedef declaration for register group ALT_SYSMGR_DMA. */
4498typedef volatile struct ALT_SYSMGR_DMA_s ALT_SYSMGR_DMA_t;
4499/* The struct declaration for the raw register contents of register group ALT_SYSMGR_DMA. */
4500 struct ALT_SYSMGR_DMA_raw_s
4501{
4502 volatile uint32_t ctrl; /* ALT_SYSMGR_DMA_CTL */
4503 volatile uint32_t persecurity; /* ALT_SYSMGR_DMA_PERSECURITY */
4504};
4505
4506/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_DMA. */
4507typedef volatile struct ALT_SYSMGR_DMA_raw_s ALT_SYSMGR_DMA_raw_t;
4508#endif /* __ASSEMBLY__ */
4509
4510
4511/*
4512 * Register Group : Preloader (initial software) Group - ALT_SYSMGR_ISW
4513 * Preloader (initial software) Group
4514 *
4515 * Registers used by preloader code and the OS.
4516 *
4517 * All registers are only reset by a cold reset (ignore warm reset).
4518 *
4519 */
4520/*
4521 * Register : Preloader to OS Handoff Information - handoff
4522 *
4523 * These registers are used to store handoff infomation between the preloader and
4524 * the OS. These 8 registers can be used to store any information. The contents of
4525 * these registers have no impact on the state of the HPS hardware.
4526 *
4527 * Register Layout
4528 *
4529 * Bits | Access | Reset | Description
4530 * :-------|:-------|:------|:------------------------------
4531 * [31:0] | RW | 0x0 | Preloader Handoff Information
4532 *
4533 */
4534/*
4535 * Field : Preloader Handoff Information - value
4536 *
4537 * Preloader Handoff Information.
4538 *
4539 * Field Access Macros:
4540 *
4541 */
4542/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */
4543#define ALT_SYSMGR_ISW_HANDOFF_VALUE_LSB 0
4544/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */
4545#define ALT_SYSMGR_ISW_HANDOFF_VALUE_MSB 31
4546/* The width in bits of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */
4547#define ALT_SYSMGR_ISW_HANDOFF_VALUE_WIDTH 32
4548/* The mask used to set the ALT_SYSMGR_ISW_HANDOFF_VALUE register field value. */
4549#define ALT_SYSMGR_ISW_HANDOFF_VALUE_SET_MSK 0xffffffff
4550/* The mask used to clear the ALT_SYSMGR_ISW_HANDOFF_VALUE register field value. */
4551#define ALT_SYSMGR_ISW_HANDOFF_VALUE_CLR_MSK 0x00000000
4552/* The reset value of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */
4553#define ALT_SYSMGR_ISW_HANDOFF_VALUE_RESET 0x0
4554/* Extracts the ALT_SYSMGR_ISW_HANDOFF_VALUE field value from a register. */
4555#define ALT_SYSMGR_ISW_HANDOFF_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4556/* Produces a ALT_SYSMGR_ISW_HANDOFF_VALUE register field value suitable for setting the register. */
4557#define ALT_SYSMGR_ISW_HANDOFF_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4558
4559#ifndef __ASSEMBLY__
4560/*
4561 * WARNING: The C register and register group struct declarations are provided for
4562 * convenience and illustrative purposes. They should, however, be used with
4563 * caution as the C language standard provides no guarantees about the alignment or
4564 * atomicity of device memory accesses. The recommended practice for writing
4565 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4566 * alt_write_word() functions.
4567 *
4568 * The struct declaration for register ALT_SYSMGR_ISW_HANDOFF.
4569 */
4570 struct ALT_SYSMGR_ISW_HANDOFF_s
4571{
4572 uint32_t value : 32; /* Preloader Handoff Information */
4573};
4574
4575/* The typedef declaration for register ALT_SYSMGR_ISW_HANDOFF. */
4576typedef volatile struct ALT_SYSMGR_ISW_HANDOFF_s ALT_SYSMGR_ISW_HANDOFF_t;
4577#endif /* __ASSEMBLY__ */
4578
4579/* The byte offset of the ALT_SYSMGR_ISW_HANDOFF register from the beginning of the component. */
4580#define ALT_SYSMGR_ISW_HANDOFF_OFST 0x0
4581
4582#ifndef __ASSEMBLY__
4583/*
4584 * WARNING: The C register and register group struct declarations are provided for
4585 * convenience and illustrative purposes. They should, however, be used with
4586 * caution as the C language standard provides no guarantees about the alignment or
4587 * atomicity of device memory accesses. The recommended practice for writing
4588 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4589 * alt_write_word() functions.
4590 *
4591 * The struct declaration for register group ALT_SYSMGR_ISW.
4592 */
4593 struct ALT_SYSMGR_ISW_s
4594{
4595 volatile ALT_SYSMGR_ISW_HANDOFF_t handoff[8]; /* ALT_SYSMGR_ISW_HANDOFF */
4596};
4597
4598/* The typedef declaration for register group ALT_SYSMGR_ISW. */
4599typedef volatile struct ALT_SYSMGR_ISW_s ALT_SYSMGR_ISW_t;
4600/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ISW. */
4601 struct ALT_SYSMGR_ISW_raw_s
4602{
4603 volatile uint32_t handoff[8]; /* ALT_SYSMGR_ISW_HANDOFF */
4604};
4605
4606/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ISW. */
4607typedef volatile struct ALT_SYSMGR_ISW_raw_s ALT_SYSMGR_ISW_raw_t;
4608#endif /* __ASSEMBLY__ */
4609
4610
4611/*
4612 * Register Group : Boot ROM Code Register Group - ALT_SYSMGR_ROMCODE
4613 * Boot ROM Code Register Group
4614 *
4615 * Registers used by the Boot ROM code. All fields are only reset by a cold reset
4616 * (ignore warm reset).
4617 *
4618 */
4619/*
4620 * Register : Control Register - ctrl
4621 *
4622 * Contains information used to control Boot ROM code.
4623 *
4624 * Register Layout
4625 *
4626 * Bits | Access | Reset | Description
4627 * :-------|:-------|:------|:-------------------------------------------
4628 * [0] | RW | 0x0 | Warm Reset Configure Pin Mux for Boot Pins
4629 * [1] | RW | 0x0 | Warm Reset Configure IOs for Boot Pins
4630 * [31:2] | ??? | 0x0 | *UNDEFINED*
4631 *
4632 */
4633/*
4634 * Field : Warm Reset Configure Pin Mux for Boot Pins - warmrstcfgpinmux
4635 *
4636 * Specifies whether the Boot ROM code configures the pin mux for boot pins after a
4637 * warm reset. Note that the Boot ROM code always configures the pin mux for boot
4638 * pins after a cold reset. After the Boot ROM code configures the pin mux for boot
4639 * pins, it always disables this field. It is up to user software to enable this
4640 * field if it wants a different behavior.
4641 *
4642 * Field Enumeration Values:
4643 *
4644 * Enum | Value | Description
4645 * :-----------------------------------------------|:------|:----------------------------------------------
4646 * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD | 0x0 | Boot ROM code will not configure pin mux for
4647 * : | | boot pins after a warm reset
4648 * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END | 0x1 | Boot ROM code will configure pin mux for boot
4649 * : | | pins after a warm reset
4650 *
4651 * Field Access Macros:
4652 *
4653 */
4654/*
4655 * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX
4656 *
4657 * Boot ROM code will not configure pin mux for boot pins after a warm reset
4658 */
4659#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD 0x0
4660/*
4661 * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX
4662 *
4663 * Boot ROM code will configure pin mux for boot pins after a warm reset
4664 */
4665#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END 0x1
4666
4667/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */
4668#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_LSB 0
4669/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */
4670#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_MSB 0
4671/* The width in bits of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */
4672#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_WIDTH 1
4673/* The mask used to set the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value. */
4674#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET_MSK 0x00000001
4675/* The mask used to clear the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value. */
4676#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_CLR_MSK 0xfffffffe
4677/* The reset value of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */
4678#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_RESET 0x0
4679/* Extracts the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX field value from a register. */
4680#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_GET(value) (((value) & 0x00000001) >> 0)
4681/* Produces a ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value suitable for setting the register. */
4682#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET(value) (((value) << 0) & 0x00000001)
4683
4684/*
4685 * Field : Warm Reset Configure IOs for Boot Pins - warmrstcfgio
4686 *
4687 * Specifies whether the Boot ROM code configures the IOs used by boot after a warm
4688 * reset. Note that the Boot ROM code always configures the IOs used by boot after
4689 * a cold reset. After the Boot ROM code configures the IOs used by boot, it always
4690 * disables this field. It is up to user software to enable this field if it wants
4691 * a different behavior.
4692 *
4693 * Field Enumeration Values:
4694 *
4695 * Enum | Value | Description
4696 * :-------------------------------------------|:------|:----------------------------------------------
4697 * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_DISD | 0x0 | Boot ROM code will not configure IOs used by
4698 * : | | boot after a warm reset
4699 * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_END | 0x1 | Boot ROM code will configure IOs used by boot
4700 * : | | after a warm reset
4701 *
4702 * Field Access Macros:
4703 *
4704 */
4705/*
4706 * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO
4707 *
4708 * Boot ROM code will not configure IOs used by boot after a warm reset
4709 */
4710#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_DISD 0x0
4711/*
4712 * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO
4713 *
4714 * Boot ROM code will configure IOs used by boot after a warm reset
4715 */
4716#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_END 0x1
4717
4718/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */
4719#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_LSB 1
4720/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */
4721#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_MSB 1
4722/* The width in bits of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */
4723#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_WIDTH 1
4724/* The mask used to set the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value. */
4725#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET_MSK 0x00000002
4726/* The mask used to clear the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value. */
4727#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_CLR_MSK 0xfffffffd
4728/* The reset value of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */
4729#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_RESET 0x0
4730/* Extracts the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO field value from a register. */
4731#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_GET(value) (((value) & 0x00000002) >> 1)
4732/* Produces a ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value suitable for setting the register. */
4733#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET(value) (((value) << 1) & 0x00000002)
4734
4735#ifndef __ASSEMBLY__
4736/*
4737 * WARNING: The C register and register group struct declarations are provided for
4738 * convenience and illustrative purposes. They should, however, be used with
4739 * caution as the C language standard provides no guarantees about the alignment or
4740 * atomicity of device memory accesses. The recommended practice for writing
4741 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4742 * alt_write_word() functions.
4743 *
4744 * The struct declaration for register ALT_SYSMGR_ROMCODE_CTL.
4745 */
4746 struct ALT_SYSMGR_ROMCODE_CTL_s
4747{
4748 uint32_t warmrstcfgpinmux : 1; /* Warm Reset Configure Pin Mux for Boot Pins */
4749 uint32_t warmrstcfgio : 1; /* Warm Reset Configure IOs for Boot Pins */
4750 uint32_t : 30; /* *UNDEFINED* */
4751};
4752
4753/* The typedef declaration for register ALT_SYSMGR_ROMCODE_CTL. */
4754typedef volatile struct ALT_SYSMGR_ROMCODE_CTL_s ALT_SYSMGR_ROMCODE_CTL_t;
4755#endif /* __ASSEMBLY__ */
4756
4757/* The byte offset of the ALT_SYSMGR_ROMCODE_CTL register from the beginning of the component. */
4758#define ALT_SYSMGR_ROMCODE_CTL_OFST 0x0
4759
4760/*
4761 * Register : CPU1 Start Address Register - cpu1startaddr
4762 *
4763 * When CPU1 is released from reset and the Boot ROM is located at the CPU1 reset
4764 * exception address (the typical case), the Boot ROM reset handler code reads the
4765 * address stored in this register and jumps it to hand off execution to user
4766 * software.
4767 *
4768 * Register Layout
4769 *
4770 * Bits | Access | Reset | Description
4771 * :-------|:-------|:------|:------------
4772 * [31:0] | RW | 0x0 | Address
4773 *
4774 */
4775/*
4776 * Field : Address - value
4777 *
4778 * Address for CPU1 to start executing at after coming out of reset.
4779 *
4780 * Field Access Macros:
4781 *
4782 */
4783/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */
4784#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_LSB 0
4785/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */
4786#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_MSB 31
4787/* The width in bits of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */
4788#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_WIDTH 32
4789/* The mask used to set the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value. */
4790#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET_MSK 0xffffffff
4791/* The mask used to clear the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value. */
4792#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_CLR_MSK 0x00000000
4793/* The reset value of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */
4794#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_RESET 0x0
4795/* Extracts the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE field value from a register. */
4796#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4797/* Produces a ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value suitable for setting the register. */
4798#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4799
4800#ifndef __ASSEMBLY__
4801/*
4802 * WARNING: The C register and register group struct declarations are provided for
4803 * convenience and illustrative purposes. They should, however, be used with
4804 * caution as the C language standard provides no guarantees about the alignment or
4805 * atomicity of device memory accesses. The recommended practice for writing
4806 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4807 * alt_write_word() functions.
4808 *
4809 * The struct declaration for register ALT_SYSMGR_ROMCODE_CPU1STARTADDR.
4810 */
4811 struct ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s
4812{
4813 uint32_t value : 32; /* Address */
4814};
4815
4816/* The typedef declaration for register ALT_SYSMGR_ROMCODE_CPU1STARTADDR. */
4817typedef volatile struct ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s ALT_SYSMGR_ROMCODE_CPU1STARTADDR_t;
4818#endif /* __ASSEMBLY__ */
4819
4820/* The byte offset of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR register from the beginning of the component. */
4821#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST 0x4
4822
4823/*
4824 * Register : Preloader (initial software) State Register - initswstate
4825 *
4826 * The preloader software (loaded by the Boot ROM) writes the magic value
4827 * 0x49535756 (ISWV in ASCII) to this register when it has reached a valid state.
4828 *
4829 * Register Layout
4830 *
4831 * Bits | Access | Reset | Description
4832 * :-------|:-------|:------|:------------
4833 * [31:0] | RW | 0x0 | Value
4834 *
4835 */
4836/*
4837 * Field : Value - value
4838 *
4839 * Written with magic value.
4840 *
4841 * Field Enumeration Values:
4842 *
4843 * Enum | Value | Description
4844 * :-----------------------------------------------|:-----------|:------------
4845 * ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_INVALID | 0x0 |
4846 * ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_VALID | 0x49535756 |
4847 *
4848 * Field Access Macros:
4849 *
4850 */
4851/*
4852 * Enumerated value for register field ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE
4853 *
4854 */
4855#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_INVALID 0x0
4856/*
4857 * Enumerated value for register field ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE
4858 *
4859 */
4860#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_VALID 0x49535756
4861
4862/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */
4863#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_LSB 0
4864/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */
4865#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_MSB 31
4866/* The width in bits of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */
4867#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_WIDTH 32
4868/* The mask used to set the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value. */
4869#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET_MSK 0xffffffff
4870/* The mask used to clear the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value. */
4871#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_CLR_MSK 0x00000000
4872/* The reset value of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */
4873#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_RESET 0x0
4874/* Extracts the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE field value from a register. */
4875#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4876/* Produces a ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value suitable for setting the register. */
4877#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4878
4879#ifndef __ASSEMBLY__
4880/*
4881 * WARNING: The C register and register group struct declarations are provided for
4882 * convenience and illustrative purposes. They should, however, be used with
4883 * caution as the C language standard provides no guarantees about the alignment or
4884 * atomicity of device memory accesses. The recommended practice for writing
4885 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4886 * alt_write_word() functions.
4887 *
4888 * The struct declaration for register ALT_SYSMGR_ROMCODE_INITSWSTATE.
4889 */
4890 struct ALT_SYSMGR_ROMCODE_INITSWSTATE_s
4891{
4892 uint32_t value : 32; /* Value */
4893};
4894
4895/* The typedef declaration for register ALT_SYSMGR_ROMCODE_INITSWSTATE. */
4896typedef volatile struct ALT_SYSMGR_ROMCODE_INITSWSTATE_s ALT_SYSMGR_ROMCODE_INITSWSTATE_t;
4897#endif /* __ASSEMBLY__ */
4898
4899/* The byte offset of the ALT_SYSMGR_ROMCODE_INITSWSTATE register from the beginning of the component. */
4900#define ALT_SYSMGR_ROMCODE_INITSWSTATE_OFST 0x8
4901
4902/*
4903 * Register : Preloader (initial software) Last Image Loaded Register - initswlastld
4904 *
4905 * Contains the index of the last preloader software image loaded by the Boot ROM
4906 * from the boot device.
4907 *
4908 * Register Layout
4909 *
4910 * Bits | Access | Reset | Description
4911 * :-------|:-------|:------|:------------
4912 * [1:0] | RW | 0x0 | Index
4913 * [31:2] | ??? | 0x0 | *UNDEFINED*
4914 *
4915 */
4916/*
4917 * Field : Index - index
4918 *
4919 * Index of last image loaded.
4920 *
4921 * Field Access Macros:
4922 *
4923 */
4924/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */
4925#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_LSB 0
4926/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */
4927#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_MSB 1
4928/* The width in bits of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */
4929#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_WIDTH 2
4930/* The mask used to set the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value. */
4931#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET_MSK 0x00000003
4932/* The mask used to clear the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value. */
4933#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_CLR_MSK 0xfffffffc
4934/* The reset value of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */
4935#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_RESET 0x0
4936/* Extracts the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX field value from a register. */
4937#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_GET(value) (((value) & 0x00000003) >> 0)
4938/* Produces a ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value suitable for setting the register. */
4939#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET(value) (((value) << 0) & 0x00000003)
4940
4941#ifndef __ASSEMBLY__
4942/*
4943 * WARNING: The C register and register group struct declarations are provided for
4944 * convenience and illustrative purposes. They should, however, be used with
4945 * caution as the C language standard provides no guarantees about the alignment or
4946 * atomicity of device memory accesses. The recommended practice for writing
4947 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4948 * alt_write_word() functions.
4949 *
4950 * The struct declaration for register ALT_SYSMGR_ROMCODE_INITSWLASTLD.
4951 */
4952 struct ALT_SYSMGR_ROMCODE_INITSWLASTLD_s
4953{
4954 uint32_t index : 2; /* Index */
4955 uint32_t : 30; /* *UNDEFINED* */
4956};
4957
4958/* The typedef declaration for register ALT_SYSMGR_ROMCODE_INITSWLASTLD. */
4959typedef volatile struct ALT_SYSMGR_ROMCODE_INITSWLASTLD_s ALT_SYSMGR_ROMCODE_INITSWLASTLD_t;
4960#endif /* __ASSEMBLY__ */
4961
4962/* The byte offset of the ALT_SYSMGR_ROMCODE_INITSWLASTLD register from the beginning of the component. */
4963#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_OFST 0xc
4964
4965/*
4966 * Register : Boot ROM Software State Register - bootromswstate
4967 *
4968 * 32-bits general purpose register used by the Boot ROM code. Actual usage is
4969 * defined in the Boot ROM source code.
4970 *
4971 * Register Layout
4972 *
4973 * Bits | Access | Reset | Description
4974 * :-------|:-------|:------|:------------------------
4975 * [31:0] | RW | 0x0 | Boot ROM Software State
4976 *
4977 */
4978/*
4979 * Field : Boot ROM Software State - value
4980 *
4981 * Reserved for Boot ROM use.
4982 *
4983 * Field Access Macros:
4984 *
4985 */
4986/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */
4987#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_LSB 0
4988/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */
4989#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_MSB 31
4990/* The width in bits of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */
4991#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_WIDTH 32
4992/* The mask used to set the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value. */
4993#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET_MSK 0xffffffff
4994/* The mask used to clear the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value. */
4995#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_CLR_MSK 0x00000000
4996/* The reset value of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */
4997#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_RESET 0x0
4998/* Extracts the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE field value from a register. */
4999#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
5000/* Produces a ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value suitable for setting the register. */
5001#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
5002
5003#ifndef __ASSEMBLY__
5004/*
5005 * WARNING: The C register and register group struct declarations are provided for
5006 * convenience and illustrative purposes. They should, however, be used with
5007 * caution as the C language standard provides no guarantees about the alignment or
5008 * atomicity of device memory accesses. The recommended practice for writing
5009 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5010 * alt_write_word() functions.
5011 *
5012 * The struct declaration for register ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE.
5013 */
5014 struct ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_s
5015{
5016 uint32_t value : 32; /* Boot ROM Software State */
5017};
5018
5019/* The typedef declaration for register ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE. */
5020typedef volatile struct ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_s ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_t;
5021#endif /* __ASSEMBLY__ */
5022
5023/* The byte offset of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE register from the beginning of the component. */
5024#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_OFST 0x10
5025
5026/*
5027 * Register Group : Warm Boot from On-Chip RAM Group - ALT_SYSMGR_ROMCODE_WARMRAM
5028 * Warm Boot from On-Chip RAM Group
5029 *
5030 * Registers used by the Boot ROM code to support booting from the On-chip RAM on a
5031 * warm reset. All these registers must be written by user software before a warm
5032 * reset occurs to make use of this feature.
5033 *
5034 */
5035/*
5036 * Register : Enable Register - enable
5037 *
5038 * Enables or disables the warm reset from On-chip RAM feature.
5039 *
5040 * Register Layout
5041 *
5042 * Bits | Access | Reset | Description
5043 * :-------|:-------|:------|:----------------------------
5044 * [31:0] | RW | 0x0 | Warm Reset from On-chip RAM
5045 *
5046 */
5047/*
5048 * Field : Warm Reset from On-chip RAM - magic
5049 *
5050 * Controls whether Boot ROM will attempt to boot from the contents of the On-chip
5051 * RAM on a warm reset. When this feature is enabled, the Boot ROM code will not
5052 * configure boot IOs, the pin mux, or clocks.
5053 *
5054 * Note that the enable value is a 32-bit magic value (provided by the enum).
5055 *
5056 * Field Enumeration Values:
5057 *
5058 * Enum | Value | Description
5059 * :-------------------------------------------|:-----------|:------------------------------------------------
5060 * ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_DISD | 0x0 | Boot ROM code will not attempt to boot from On-
5061 * : | | chip RAM on a warm reset
5062 * ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_END | 0xae9efebc | Boot ROM code will attempt to boot from On-chip
5063 * : | | RAM on a warm reset
5064 *
5065 * Field Access Macros:
5066 *
5067 */
5068/*
5069 * Enumerated value for register field ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC
5070 *
5071 * Boot ROM code will not attempt to boot from On-chip RAM on a warm reset
5072 */
5073#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_DISD 0x0
5074/*
5075 * Enumerated value for register field ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC
5076 *
5077 * Boot ROM code will attempt to boot from On-chip RAM on a warm reset
5078 */
5079#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_END 0xae9efebc
5080
5081/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */
5082#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_LSB 0
5083/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */
5084#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_MSB 31
5085/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */
5086#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_WIDTH 32
5087/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value. */
5088#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET_MSK 0xffffffff
5089/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value. */
5090#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_CLR_MSK 0x00000000
5091/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */
5092#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_RESET 0x0
5093/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC field value from a register. */
5094#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_GET(value) (((value) & 0xffffffff) >> 0)
5095/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value suitable for setting the register. */
5096#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET(value) (((value) << 0) & 0xffffffff)
5097
5098#ifndef __ASSEMBLY__
5099/*
5100 * WARNING: The C register and register group struct declarations are provided for
5101 * convenience and illustrative purposes. They should, however, be used with
5102 * caution as the C language standard provides no guarantees about the alignment or
5103 * atomicity of device memory accesses. The recommended practice for writing
5104 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5105 * alt_write_word() functions.
5106 *
5107 * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EN.
5108 */
5109 struct ALT_SYSMGR_ROMCODE_WARMRAM_EN_s
5110{
5111 uint32_t magic : 32; /* Warm Reset from On-chip RAM */
5112};
5113
5114/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EN. */
5115typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_EN_s ALT_SYSMGR_ROMCODE_WARMRAM_EN_t;
5116#endif /* __ASSEMBLY__ */
5117
5118/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register from the beginning of the component. */
5119#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST 0x0
5120/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register. */
5121#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST))
5122
5123/*
5124 * Register : Data Start Register - datastart
5125 *
5126 * Offset into On-chip RAM of the start of the region for CRC validation
5127 *
5128 * Register Layout
5129 *
5130 * Bits | Access | Reset | Description
5131 * :--------|:-------|:------|:------------------
5132 * [15:0] | RW | 0x0 | Data Start Offset
5133 * [31:16] | ??? | 0x0 | *UNDEFINED*
5134 *
5135 */
5136/*
5137 * Field : Data Start Offset - offset
5138 *
5139 * Contains the byte offset into the On-chip RAM of the start of the On-chip RAM
5140 * region for the warm boot CRC validation. The offset must be an integer multiple
5141 * of 4 (i.e. aligned to a word). The Boot ROM code will set the top 16 bits to
5142 * 0xFFFF and clear the bottom 2 bits.
5143 *
5144 * Field Access Macros:
5145 *
5146 */
5147/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */
5148#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_LSB 0
5149/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */
5150#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_MSB 15
5151/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */
5152#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_WIDTH 16
5153/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value. */
5154#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET_MSK 0x0000ffff
5155/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value. */
5156#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_CLR_MSK 0xffff0000
5157/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */
5158#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_RESET 0x0
5159/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET field value from a register. */
5160#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0)
5161/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value suitable for setting the register. */
5162#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET(value) (((value) << 0) & 0x0000ffff)
5163
5164#ifndef __ASSEMBLY__
5165/*
5166 * WARNING: The C register and register group struct declarations are provided for
5167 * convenience and illustrative purposes. They should, however, be used with
5168 * caution as the C language standard provides no guarantees about the alignment or
5169 * atomicity of device memory accesses. The recommended practice for writing
5170 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5171 * alt_write_word() functions.
5172 *
5173 * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART.
5174 */
5175 struct ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_s
5176{
5177 uint32_t offset : 16; /* Data Start Offset */
5178 uint32_t : 16; /* *UNDEFINED* */
5179};
5180
5181/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART. */
5182typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_s ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_t;
5183#endif /* __ASSEMBLY__ */
5184
5185/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register from the beginning of the component. */
5186#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST 0x4
5187/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register. */
5188#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST))
5189
5190/*
5191 * Register : Length Register - length
5192 *
5193 * Length of region in On-chip RAM for CRC validation.
5194 *
5195 * Register Layout
5196 *
5197 * Bits | Access | Reset | Description
5198 * :--------|:-------|:------|:------------
5199 * [15:0] | RW | 0x0 | Size
5200 * [31:16] | ??? | 0x0 | *UNDEFINED*
5201 *
5202 */
5203/*
5204 * Field : Size - size
5205 *
5206 * Contains the length (in bytes) of the region in the On-chip RAM for the warm
5207 * boot CRC validation.
5208 *
5209 * If the length is 0, the Boot ROM won't perform CRC calculation and CRC check to
5210 * avoid overhead caused by CRC validation.
5211 *
5212 * If the START + LENGTH exceeds the maximum offset into the On-chip RAM, the Boot
5213 * ROM won't boot from the On-chip RAM.
5214 *
5215 * The length must be an integer multiple of 4.
5216 *
5217 * The Boot ROM code will clear the top 16 bits and the bottom 2 bits.
5218 *
5219 * Field Access Macros:
5220 *
5221 */
5222/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */
5223#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_LSB 0
5224/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */
5225#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_MSB 15
5226/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */
5227#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_WIDTH 16
5228/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value. */
5229#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET_MSK 0x0000ffff
5230/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value. */
5231#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_CLR_MSK 0xffff0000
5232/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */
5233#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_RESET 0x0
5234/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE field value from a register. */
5235#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_GET(value) (((value) & 0x0000ffff) >> 0)
5236/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value suitable for setting the register. */
5237#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET(value) (((value) << 0) & 0x0000ffff)
5238
5239#ifndef __ASSEMBLY__
5240/*
5241 * WARNING: The C register and register group struct declarations are provided for
5242 * convenience and illustrative purposes. They should, however, be used with
5243 * caution as the C language standard provides no guarantees about the alignment or
5244 * atomicity of device memory accesses. The recommended practice for writing
5245 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5246 * alt_write_word() functions.
5247 *
5248 * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_LEN.
5249 */
5250 struct ALT_SYSMGR_ROMCODE_WARMRAM_LEN_s
5251{
5252 uint32_t size : 16; /* Size */
5253 uint32_t : 16; /* *UNDEFINED* */
5254};
5255
5256/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_LEN. */
5257typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_LEN_s ALT_SYSMGR_ROMCODE_WARMRAM_LEN_t;
5258#endif /* __ASSEMBLY__ */
5259
5260/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register from the beginning of the component. */
5261#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST 0x8
5262/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register. */
5263#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST))
5264
5265/*
5266 * Register : Execution Register - execution
5267 *
5268 * Offset into On-chip RAM to enter to on a warm boot.
5269 *
5270 * Register Layout
5271 *
5272 * Bits | Access | Reset | Description
5273 * :--------|:-------|:------|:-----------------
5274 * [15:0] | RW | 0x0 | Execution Offset
5275 * [31:16] | ??? | 0x0 | *UNDEFINED*
5276 *
5277 */
5278/*
5279 * Field : Execution Offset - offset
5280 *
5281 * Contains the byte offset into the On-chip RAM that the Boot ROM will jump to if
5282 * the CRC validation succeeds.
5283 *
5284 * The Boot ROM code will set the top 16 bits to 0xFFFF.
5285 *
5286 * Field Access Macros:
5287 *
5288 */
5289/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */
5290#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_LSB 0
5291/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */
5292#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_MSB 15
5293/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */
5294#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_WIDTH 16
5295/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value. */
5296#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET_MSK 0x0000ffff
5297/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value. */
5298#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_CLR_MSK 0xffff0000
5299/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */
5300#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_RESET 0x0
5301/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET field value from a register. */
5302#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0)
5303/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value suitable for setting the register. */
5304#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET(value) (((value) << 0) & 0x0000ffff)
5305
5306#ifndef __ASSEMBLY__
5307/*
5308 * WARNING: The C register and register group struct declarations are provided for
5309 * convenience and illustrative purposes. They should, however, be used with
5310 * caution as the C language standard provides no guarantees about the alignment or
5311 * atomicity of device memory accesses. The recommended practice for writing
5312 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5313 * alt_write_word() functions.
5314 *
5315 * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION.
5316 */
5317 struct ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_s
5318{
5319 uint32_t offset : 16; /* Execution Offset */
5320 uint32_t : 16; /* *UNDEFINED* */
5321};
5322
5323/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION. */
5324typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_s ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_t;
5325#endif /* __ASSEMBLY__ */
5326
5327/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register from the beginning of the component. */
5328#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST 0xc
5329/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register. */
5330#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST))
5331
5332/*
5333 * Register : Expected CRC Register - crc
5334 *
5335 * Length of region in On-chip RAM for CRC validation.
5336 *
5337 * Register Layout
5338 *
5339 * Bits | Access | Reset | Description
5340 * :-------|:-------|:-----------|:-------------
5341 * [31:0] | RW | 0xe763552a | Expected CRC
5342 *
5343 */
5344/*
5345 * Field : Expected CRC - expected
5346 *
5347 * Contains the expected CRC of the region in the On-chip RAM.The Boot ROM code
5348 * calculates the actual CRC for all bytes in the region specified by the DATA
5349 * START an LENGTH registers. The contents of the EXECUTION register (after it has
5350 * been read and modified by the Boot ROM code) is also included in the CRC
5351 * calculation. The contents of the EXECUTION register is added to the CRC
5352 * accumulator a byte at a time starting with the least significant byte. If the
5353 * actual CRC doesn't match the expected CRC value in this register, the Boot ROM
5354 * won't boot from the On-chip RAM.
5355 *
5356 * The CRC is a standard CRC32 with the polynomial:
5357 *
5358 * x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 +
5359 * x^2 + x + 1
5360 *
5361 * There is no reflection of the bits and the initial value of the remainder is
5362 * 0xFFFFFFFF and the final value is exclusive ORed with 0xFFFFFFFF.
5363 *
5364 * Field Access Macros:
5365 *
5366 */
5367/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */
5368#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_LSB 0
5369/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */
5370#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_MSB 31
5371/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */
5372#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_WIDTH 32
5373/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value. */
5374#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET_MSK 0xffffffff
5375/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value. */
5376#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_CLR_MSK 0x00000000
5377/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */
5378#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_RESET 0xe763552a
5379/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED field value from a register. */
5380#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_GET(value) (((value) & 0xffffffff) >> 0)
5381/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value suitable for setting the register. */
5382#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET(value) (((value) << 0) & 0xffffffff)
5383
5384#ifndef __ASSEMBLY__
5385/*
5386 * WARNING: The C register and register group struct declarations are provided for
5387 * convenience and illustrative purposes. They should, however, be used with
5388 * caution as the C language standard provides no guarantees about the alignment or
5389 * atomicity of device memory accesses. The recommended practice for writing
5390 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5391 * alt_write_word() functions.
5392 *
5393 * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_CRC.
5394 */
5395 struct ALT_SYSMGR_ROMCODE_WARMRAM_CRC_s
5396{
5397 uint32_t expected : 32; /* Expected CRC */
5398};
5399
5400/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_CRC. */
5401typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_CRC_s ALT_SYSMGR_ROMCODE_WARMRAM_CRC_t;
5402#endif /* __ASSEMBLY__ */
5403
5404/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register from the beginning of the component. */
5405#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST 0x10
5406/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register. */
5407#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST))
5408
5409#ifndef __ASSEMBLY__
5410/*
5411 * WARNING: The C register and register group struct declarations are provided for
5412 * convenience and illustrative purposes. They should, however, be used with
5413 * caution as the C language standard provides no guarantees about the alignment or
5414 * atomicity of device memory accesses. The recommended practice for writing
5415 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5416 * alt_write_word() functions.
5417 *
5418 * The struct declaration for register group ALT_SYSMGR_ROMCODE_WARMRAM.
5419 */
5420 struct ALT_SYSMGR_ROMCODE_WARMRAM_s
5421{
5422 volatile ALT_SYSMGR_ROMCODE_WARMRAM_EN_t enable; /* ALT_SYSMGR_ROMCODE_WARMRAM_EN */
5423 volatile ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_t datastart; /* ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART */
5424 volatile ALT_SYSMGR_ROMCODE_WARMRAM_LEN_t length; /* ALT_SYSMGR_ROMCODE_WARMRAM_LEN */
5425 volatile ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_t execution; /* ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION */
5426 volatile ALT_SYSMGR_ROMCODE_WARMRAM_CRC_t crc; /* ALT_SYSMGR_ROMCODE_WARMRAM_CRC */
5427 volatile uint32_t _pad_0x14_0x20[3]; /* *UNDEFINED* */
5428};
5429
5430/* The typedef declaration for register group ALT_SYSMGR_ROMCODE_WARMRAM. */
5431typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_s ALT_SYSMGR_ROMCODE_WARMRAM_t;
5432/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE_WARMRAM. */
5433 struct ALT_SYSMGR_ROMCODE_WARMRAM_raw_s
5434{
5435 volatile uint32_t enable; /* ALT_SYSMGR_ROMCODE_WARMRAM_EN */
5436 volatile uint32_t datastart; /* ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART */
5437 volatile uint32_t length; /* ALT_SYSMGR_ROMCODE_WARMRAM_LEN */
5438 volatile uint32_t execution; /* ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION */
5439 volatile uint32_t crc; /* ALT_SYSMGR_ROMCODE_WARMRAM_CRC */
5440 volatile uint32_t _pad_0x14_0x20[3]; /* *UNDEFINED* */
5441};
5442
5443/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE_WARMRAM. */
5444typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_raw_s ALT_SYSMGR_ROMCODE_WARMRAM_raw_t;
5445#endif /* __ASSEMBLY__ */
5446
5447
5448#ifndef __ASSEMBLY__
5449/*
5450 * WARNING: The C register and register group struct declarations are provided for
5451 * convenience and illustrative purposes. They should, however, be used with
5452 * caution as the C language standard provides no guarantees about the alignment or
5453 * atomicity of device memory accesses. The recommended practice for writing
5454 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5455 * alt_write_word() functions.
5456 *
5457 * The struct declaration for register group ALT_SYSMGR_ROMCODE.
5458 */
5459 struct ALT_SYSMGR_ROMCODE_s
5460{
5461 volatile ALT_SYSMGR_ROMCODE_CTL_t ctrl; /* ALT_SYSMGR_ROMCODE_CTL */
5462 volatile ALT_SYSMGR_ROMCODE_CPU1STARTADDR_t cpu1startaddr; /* ALT_SYSMGR_ROMCODE_CPU1STARTADDR */
5463 volatile ALT_SYSMGR_ROMCODE_INITSWSTATE_t initswstate; /* ALT_SYSMGR_ROMCODE_INITSWSTATE */
5464 volatile ALT_SYSMGR_ROMCODE_INITSWLASTLD_t initswlastld; /* ALT_SYSMGR_ROMCODE_INITSWLASTLD */
5465 volatile ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_t bootromswstate; /* ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE */
5466 volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
5467 volatile ALT_SYSMGR_ROMCODE_WARMRAM_t romcodegrp_warmramgrp; /* ALT_SYSMGR_ROMCODE_WARMRAM */
5468};
5469
5470/* The typedef declaration for register group ALT_SYSMGR_ROMCODE. */
5471typedef volatile struct ALT_SYSMGR_ROMCODE_s ALT_SYSMGR_ROMCODE_t;
5472/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE. */
5473 struct ALT_SYSMGR_ROMCODE_raw_s
5474{
5475 volatile uint32_t ctrl; /* ALT_SYSMGR_ROMCODE_CTL */
5476 volatile uint32_t cpu1startaddr; /* ALT_SYSMGR_ROMCODE_CPU1STARTADDR */
5477 volatile uint32_t initswstate; /* ALT_SYSMGR_ROMCODE_INITSWSTATE */
5478 volatile uint32_t initswlastld; /* ALT_SYSMGR_ROMCODE_INITSWLASTLD */
5479 volatile uint32_t bootromswstate; /* ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE */
5480 volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
5481 volatile ALT_SYSMGR_ROMCODE_WARMRAM_raw_t romcodegrp_warmramgrp; /* ALT_SYSMGR_ROMCODE_WARMRAM */
5482};
5483
5484/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE. */
5485typedef volatile struct ALT_SYSMGR_ROMCODE_raw_s ALT_SYSMGR_ROMCODE_raw_t;
5486#endif /* __ASSEMBLY__ */
5487
5488
5489/*
5490 * Register Group : Boot ROM Hardware Register Group - ALT_SYSMGR_ROMHW
5491 * Boot ROM Hardware Register Group
5492 *
5493 * Registers used by the Boot ROM hardware, not the code within it.
5494 *
5495 */
5496/*
5497 * Register : Boot ROM Hardware Control Register - ctrl
5498 *
5499 * Controls behavior of Boot ROM hardware.
5500 *
5501 * All fields are only reset by a cold reset (ignore warm reset).
5502 *
5503 * Register Layout
5504 *
5505 * Bits | Access | Reset | Description
5506 * :-------|:-------|:------|:-----------------------------------
5507 * [0] | RW | 0x0 | Wait State
5508 * [1] | RW | 0x1 | Enable Safe Mode Warm Reset Update
5509 * [31:2] | ??? | 0x0 | *UNDEFINED*
5510 *
5511 */
5512/*
5513 * Field : Wait State - waitstate
5514 *
5515 * Controls the number of wait states applied to the Boot ROM's read operation.
5516 *
5517 * This field is cleared on a cold reset and optionally updated by hardware upon
5518 * deassertion of warm reset.
5519 *
5520 * Field Enumeration Values:
5521 *
5522 * Enum | Value | Description
5523 * :-------------------------------------|:------|:-------------------------------------------------
5524 * ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS | 0x0 | No wait states are applied to the Boom ROM's
5525 * : | | read operation.
5526 * ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN | 0x1 | A single wait state is applied to the Boot ROM's
5527 * : | | read operation.
5528 *
5529 * Field Access Macros:
5530 *
5531 */
5532/*
5533 * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_WAITSTATE
5534 *
5535 * No wait states are applied to the Boom ROM's read operation.
5536 */
5537#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS 0x0
5538/*
5539 * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_WAITSTATE
5540 *
5541 * A single wait state is applied to the Boot ROM's read operation.
5542 */
5543#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN 0x1
5544
5545/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */
5546#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_LSB 0
5547/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */
5548#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_MSB 0
5549/* The width in bits of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */
5550#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_WIDTH 1
5551/* The mask used to set the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value. */
5552#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET_MSK 0x00000001
5553/* The mask used to clear the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value. */
5554#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_CLR_MSK 0xfffffffe
5555/* The reset value of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */
5556#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_RESET 0x0
5557/* Extracts the ALT_SYSMGR_ROMHW_CTL_WAITSTATE field value from a register. */
5558#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_GET(value) (((value) & 0x00000001) >> 0)
5559/* Produces a ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value suitable for setting the register. */
5560#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET(value) (((value) << 0) & 0x00000001)
5561
5562/*
5563 * Field : Enable Safe Mode Warm Reset Update - ensfmdwru
5564 *
5565 * Controls whether the wait state bit is updated upon deassertion of warm reset.
5566 *
5567 * This field is set on a cold reset.
5568 *
5569 * Field Enumeration Values:
5570 *
5571 * Enum | Value | Description
5572 * :-------------------------------------|:------|:-----------------------------------------------
5573 * ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS | 0x0 | Wait state bit is not updated upon deassertion
5574 * : | | of warm reset.
5575 * ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN | 0x1 | Wait state bit is updated upon deassertion of
5576 * : | | warm reset. It's value is updated based on the
5577 * : | | control bit from clock manager which specifies
5578 * : | | whether clock manager will be in safe mode or
5579 * : | | not after warm reset.
5580 *
5581 * Field Access Macros:
5582 *
5583 */
5584/*
5585 * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU
5586 *
5587 * Wait state bit is not updated upon deassertion of warm reset.
5588 */
5589#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS 0x0
5590/*
5591 * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU
5592 *
5593 * Wait state bit is updated upon deassertion of warm reset.
5594 *
5595 * It's value is updated based on the control bit from clock manager which
5596 * specifies whether clock manager will be in safe mode or not after warm reset.
5597 */
5598#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN 0x1
5599
5600/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */
5601#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_LSB 1
5602/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */
5603#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_MSB 1
5604/* The width in bits of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */
5605#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_WIDTH 1
5606/* The mask used to set the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value. */
5607#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET_MSK 0x00000002
5608/* The mask used to clear the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value. */
5609#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_CLR_MSK 0xfffffffd
5610/* The reset value of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */
5611#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_RESET 0x1
5612/* Extracts the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU field value from a register. */
5613#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_GET(value) (((value) & 0x00000002) >> 1)
5614/* Produces a ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value suitable for setting the register. */
5615#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET(value) (((value) << 1) & 0x00000002)
5616
5617#ifndef __ASSEMBLY__
5618/*
5619 * WARNING: The C register and register group struct declarations are provided for
5620 * convenience and illustrative purposes. They should, however, be used with
5621 * caution as the C language standard provides no guarantees about the alignment or
5622 * atomicity of device memory accesses. The recommended practice for writing
5623 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5624 * alt_write_word() functions.
5625 *
5626 * The struct declaration for register ALT_SYSMGR_ROMHW_CTL.
5627 */
5628 struct ALT_SYSMGR_ROMHW_CTL_s
5629{
5630 uint32_t waitstate : 1; /* Wait State */
5631 uint32_t ensfmdwru : 1; /* Enable Safe Mode Warm Reset Update */
5632 uint32_t : 30; /* *UNDEFINED* */
5633};
5634
5635/* The typedef declaration for register ALT_SYSMGR_ROMHW_CTL. */
5636typedef volatile struct ALT_SYSMGR_ROMHW_CTL_s ALT_SYSMGR_ROMHW_CTL_t;
5637#endif /* __ASSEMBLY__ */
5638
5639/* The byte offset of the ALT_SYSMGR_ROMHW_CTL register from the beginning of the component. */
5640#define ALT_SYSMGR_ROMHW_CTL_OFST 0x0
5641
5642#ifndef __ASSEMBLY__
5643/*
5644 * WARNING: The C register and register group struct declarations are provided for
5645 * convenience and illustrative purposes. They should, however, be used with
5646 * caution as the C language standard provides no guarantees about the alignment or
5647 * atomicity of device memory accesses. The recommended practice for writing
5648 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5649 * alt_write_word() functions.
5650 *
5651 * The struct declaration for register group ALT_SYSMGR_ROMHW.
5652 */
5653 struct ALT_SYSMGR_ROMHW_s
5654{
5655 volatile ALT_SYSMGR_ROMHW_CTL_t ctrl; /* ALT_SYSMGR_ROMHW_CTL */
5656};
5657
5658/* The typedef declaration for register group ALT_SYSMGR_ROMHW. */
5659typedef volatile struct ALT_SYSMGR_ROMHW_s ALT_SYSMGR_ROMHW_t;
5660/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMHW. */
5661 struct ALT_SYSMGR_ROMHW_raw_s
5662{
5663 volatile uint32_t ctrl; /* ALT_SYSMGR_ROMHW_CTL */
5664};
5665
5666/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMHW. */
5667typedef volatile struct ALT_SYSMGR_ROMHW_raw_s ALT_SYSMGR_ROMHW_raw_t;
5668#endif /* __ASSEMBLY__ */
5669
5670
5671/*
5672 * Register Group : SDMMC Controller Group - ALT_SYSMGR_SDMMC
5673 * SDMMC Controller Group
5674 *
5675 * Registers related to SDMMC Controller which aren't located inside the SDMMC
5676 * itself.
5677 *
5678 */
5679/*
5680 * Register : Control Register - ctrl
5681 *
5682 * Registers used by the SDMMC Controller. All fields are reset by a cold or warm
5683 * reset.
5684 *
5685 * Register Layout
5686 *
5687 * Bits | Access | Reset | Description
5688 * :-------|:-------|:------|:--------------------------------
5689 * [2:0] | RW | 0x0 | Drive Clock Phase Shift Select
5690 * [5:3] | RW | 0x0 | Sample Clock Phase Shift Select
5691 * [6] | RW | 0x0 | Feedback Clock Select
5692 * [31:7] | ??? | 0x0 | *UNDEFINED*
5693 *
5694 */
5695/*
5696 * Field : Drive Clock Phase Shift Select - drvsel
5697 *
5698 * Select which phase shift of the clock for cclk_in_drv.
5699 *
5700 * Field Enumeration Values:
5701 *
5702 * Enum | Value | Description
5703 * :-----------------------------------------|:------|:--------------------------------------------
5704 * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0 | 0x0 | 0 degrees phase shifted clock is selected
5705 * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45 | 0x1 | 45 degrees phase shifted clock is selected
5706 * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90 | 0x2 | 90 degrees phase shifted clock is selected
5707 * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135 | 0x3 | 135 degrees phase shifted clock is selected
5708 * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180 | 0x4 | 180 degrees phase shifted clock is selected
5709 * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225 | 0x5 | 225 degrees phase shifted clock is selected
5710 * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270 | 0x6 | 270 degrees phase shifted clock is selected
5711 * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315 | 0x7 | 315 degrees phase shifted clock is selected
5712 *
5713 * Field Access Macros:
5714 *
5715 */
5716/*
5717 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5718 *
5719 * 0 degrees phase shifted clock is selected
5720 */
5721#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0 0x0
5722/*
5723 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5724 *
5725 * 45 degrees phase shifted clock is selected
5726 */
5727#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45 0x1
5728/*
5729 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5730 *
5731 * 90 degrees phase shifted clock is selected
5732 */
5733#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90 0x2
5734/*
5735 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5736 *
5737 * 135 degrees phase shifted clock is selected
5738 */
5739#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135 0x3
5740/*
5741 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5742 *
5743 * 180 degrees phase shifted clock is selected
5744 */
5745#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180 0x4
5746/*
5747 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5748 *
5749 * 225 degrees phase shifted clock is selected
5750 */
5751#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225 0x5
5752/*
5753 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5754 *
5755 * 270 degrees phase shifted clock is selected
5756 */
5757#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270 0x6
5758/*
5759 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5760 *
5761 * 315 degrees phase shifted clock is selected
5762 */
5763#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315 0x7
5764
5765/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */
5766#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_LSB 0
5767/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */
5768#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_MSB 2
5769/* The width in bits of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */
5770#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_WIDTH 3
5771/* The mask used to set the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value. */
5772#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET_MSK 0x00000007
5773/* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value. */
5774#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_CLR_MSK 0xfffffff8
5775/* The reset value of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */
5776#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_RESET 0x0
5777/* Extracts the ALT_SYSMGR_SDMMC_CTL_DRVSEL field value from a register. */
5778#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_GET(value) (((value) & 0x00000007) >> 0)
5779/* Produces a ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value suitable for setting the register. */
5780#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET(value) (((value) << 0) & 0x00000007)
5781
5782/*
5783 * Field : Sample Clock Phase Shift Select - smplsel
5784 *
5785 * Select which phase shift of the clock for cclk_in_sample.
5786 *
5787 * Field Enumeration Values:
5788 *
5789 * Enum | Value | Description
5790 * :------------------------------------------|:------|:--------------------------------------------
5791 * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0 | 0x0 | 0 degrees phase shifted clock is selected
5792 * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45 | 0x1 | 45 degrees phase shifted clock is selected
5793 * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90 | 0x2 | 90 degrees phase shifted clock is selected
5794 * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135 | 0x3 | 135 degrees phase shifted clock is selected
5795 * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180 | 0x4 | 180 degrees phase shifted clock is selected
5796 * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225 | 0x5 | 225 degrees phase shifted clock is selected
5797 * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270 | 0x6 | 270 degrees phase shifted clock is selected
5798 * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315 | 0x7 | 315 degrees phase shifted clock is selected
5799 *
5800 * Field Access Macros:
5801 *
5802 */
5803/*
5804 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5805 *
5806 * 0 degrees phase shifted clock is selected
5807 */
5808#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0 0x0
5809/*
5810 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5811 *
5812 * 45 degrees phase shifted clock is selected
5813 */
5814#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45 0x1
5815/*
5816 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5817 *
5818 * 90 degrees phase shifted clock is selected
5819 */
5820#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90 0x2
5821/*
5822 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5823 *
5824 * 135 degrees phase shifted clock is selected
5825 */
5826#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135 0x3
5827/*
5828 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5829 *
5830 * 180 degrees phase shifted clock is selected
5831 */
5832#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180 0x4
5833/*
5834 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5835 *
5836 * 225 degrees phase shifted clock is selected
5837 */
5838#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225 0x5
5839/*
5840 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5841 *
5842 * 270 degrees phase shifted clock is selected
5843 */
5844#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270 0x6
5845/*
5846 * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5847 *
5848 * 315 degrees phase shifted clock is selected
5849 */
5850#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315 0x7
5851
5852/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */
5853#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_LSB 3
5854/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */
5855#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_MSB 5
5856/* The width in bits of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */
5857#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_WIDTH 3
5858/* The mask used to set the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value. */
5859#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET_MSK 0x00000038
5860/* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value. */
5861#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_CLR_MSK 0xffffffc7
5862/* The reset value of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */
5863#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_RESET 0x0
5864/* Extracts the ALT_SYSMGR_SDMMC_CTL_SMPLSEL field value from a register. */
5865#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_GET(value) (((value) & 0x00000038) >> 3)
5866/* Produces a ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value suitable for setting the register. */
5867#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET(value) (((value) << 3) & 0x00000038)
5868
5869/*
5870 * Field : Feedback Clock Select - fbclksel
5871 *
5872 * Select which fb_clk to be used as cclk_in_sample.
5873 *
5874 * If 0, cclk_in_sample is driven by internal phase shifted cclk_in.
5875 *
5876 * If 1, cclk_in_sample is driven by fb_clk_in. No phase shifting is provided
5877 * internally on cclk_in_sample.
5878 *
5879 * Note: Using the feedback clock (setting this bit to 1) is not a supported use
5880 * model.
5881 *
5882 * Field Access Macros:
5883 *
5884 */
5885/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */
5886#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_LSB 6
5887/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */
5888#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_MSB 6
5889/* The width in bits of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */
5890#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_WIDTH 1
5891/* The mask used to set the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value. */
5892#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET_MSK 0x00000040
5893/* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value. */
5894#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_CLR_MSK 0xffffffbf
5895/* The reset value of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */
5896#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_RESET 0x0
5897/* Extracts the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL field value from a register. */
5898#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_GET(value) (((value) & 0x00000040) >> 6)
5899/* Produces a ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value suitable for setting the register. */
5900#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET(value) (((value) << 6) & 0x00000040)
5901
5902#ifndef __ASSEMBLY__
5903/*
5904 * WARNING: The C register and register group struct declarations are provided for
5905 * convenience and illustrative purposes. They should, however, be used with
5906 * caution as the C language standard provides no guarantees about the alignment or
5907 * atomicity of device memory accesses. The recommended practice for writing
5908 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5909 * alt_write_word() functions.
5910 *
5911 * The struct declaration for register ALT_SYSMGR_SDMMC_CTL.
5912 */
5913 struct ALT_SYSMGR_SDMMC_CTL_s
5914{
5915 uint32_t drvsel : 3; /* Drive Clock Phase Shift Select */
5916 uint32_t smplsel : 3; /* Sample Clock Phase Shift Select */
5917 uint32_t fbclksel : 1; /* Feedback Clock Select */
5918 uint32_t : 25; /* *UNDEFINED* */
5919};
5920
5921/* The typedef declaration for register ALT_SYSMGR_SDMMC_CTL. */
5922typedef volatile struct ALT_SYSMGR_SDMMC_CTL_s ALT_SYSMGR_SDMMC_CTL_t;
5923#endif /* __ASSEMBLY__ */
5924
5925/* The byte offset of the ALT_SYSMGR_SDMMC_CTL register from the beginning of the component. */
5926#define ALT_SYSMGR_SDMMC_CTL_OFST 0x0
5927
5928/*
5929 * Register : SD/MMC L3 Master HPROT Register - l3master
5930 *
5931 * Controls the L3 master HPROT AHB-Lite signal.
5932 *
5933 * These register bits should be updated only during system initialization prior to
5934 * removing the peripheral from reset. They may not be changed dynamically during
5935 * peripheral operation
5936 *
5937 * All fields are reset by a cold or warm reset.
5938 *
5939 * Register Layout
5940 *
5941 * Bits | Access | Reset | Description
5942 * :-------|:-------|:------|:-------------------------
5943 * [0] | RW | 0x1 | SD/MMC HPROT Data/Opcode
5944 * [1] | RW | 0x1 | SD/MMC HPROT Privileged
5945 * [2] | RW | 0x0 | SD/MMC HPROT Bufferable
5946 * [3] | RW | 0x0 | SD/MMC HPROT Cacheable
5947 * [31:4] | ??? | 0x0 | *UNDEFINED*
5948 *
5949 */
5950/*
5951 * Field : SD/MMC HPROT Data/Opcode - hprotdata_0
5952 *
5953 * Specifies if the L3 master access is for data or opcode for the SD/MMC module.
5954 *
5955 * Field Enumeration Values:
5956 *
5957 * Enum | Value | Description
5958 * :--------------------------------------------|:------|:-------------
5959 * ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_OPCODE | 0x0 | Opcode fetch
5960 * ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_DATA | 0x1 | Data access
5961 *
5962 * Field Access Macros:
5963 *
5964 */
5965/*
5966 * Enumerated value for register field ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0
5967 *
5968 * Opcode fetch
5969 */
5970#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_OPCODE 0x0
5971/*
5972 * Enumerated value for register field ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0
5973 *
5974 * Data access
5975 */
5976#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_DATA 0x1
5977
5978/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */
5979#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_LSB 0
5980/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */
5981#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_MSB 0
5982/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */
5983#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_WIDTH 1
5984/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value. */
5985#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET_MSK 0x00000001
5986/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value. */
5987#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe
5988/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */
5989#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_RESET 0x1
5990/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 field value from a register. */
5991#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0)
5992/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value suitable for setting the register. */
5993#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001)
5994
5995/*
5996 * Field : SD/MMC HPROT Privileged - hprotpriv_0
5997 *
5998 * If 1, L3 master accesses for the SD/MMC module are privileged.
5999 *
6000 * Field Access Macros:
6001 *
6002 */
6003/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */
6004#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_LSB 1
6005/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */
6006#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_MSB 1
6007/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */
6008#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_WIDTH 1
6009/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value. */
6010#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET_MSK 0x00000002
6011/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value. */
6012#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffd
6013/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */
6014#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_RESET 0x1
6015/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 field value from a register. */
6016#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000002) >> 1)
6017/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value suitable for setting the register. */
6018#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET(value) (((value) << 1) & 0x00000002)
6019
6020/*
6021 * Field : SD/MMC HPROT Bufferable - hprotbuff_0
6022 *
6023 * If 1, L3 master accesses for the SD/MMC module are bufferable.
6024 *
6025 * Field Access Macros:
6026 *
6027 */
6028/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */
6029#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_LSB 2
6030/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */
6031#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_MSB 2
6032/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */
6033#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_WIDTH 1
6034/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value. */
6035#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET_MSK 0x00000004
6036/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value. */
6037#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_CLR_MSK 0xfffffffb
6038/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */
6039#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_RESET 0x0
6040/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 field value from a register. */
6041#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000004) >> 2)
6042/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value suitable for setting the register. */
6043#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET(value) (((value) << 2) & 0x00000004)
6044
6045/*
6046 * Field : SD/MMC HPROT Cacheable - hprotcache_0
6047 *
6048 * If 1, L3 master accesses for the SD/MMC module are cacheable.
6049 *
6050 * Field Access Macros:
6051 *
6052 */
6053/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */
6054#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_LSB 3
6055/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */
6056#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_MSB 3
6057/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */
6058#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_WIDTH 1
6059/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value. */
6060#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET_MSK 0x00000008
6061/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value. */
6062#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_CLR_MSK 0xfffffff7
6063/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */
6064#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_RESET 0x0
6065/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 field value from a register. */
6066#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000008) >> 3)
6067/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value suitable for setting the register. */
6068#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET(value) (((value) << 3) & 0x00000008)
6069
6070#ifndef __ASSEMBLY__
6071/*
6072 * WARNING: The C register and register group struct declarations are provided for
6073 * convenience and illustrative purposes. They should, however, be used with
6074 * caution as the C language standard provides no guarantees about the alignment or
6075 * atomicity of device memory accesses. The recommended practice for writing
6076 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6077 * alt_write_word() functions.
6078 *
6079 * The struct declaration for register ALT_SYSMGR_SDMMC_L3MST.
6080 */
6081 struct ALT_SYSMGR_SDMMC_L3MST_s
6082{
6083 uint32_t hprotdata_0 : 1; /* SD/MMC HPROT Data/Opcode */
6084 uint32_t hprotpriv_0 : 1; /* SD/MMC HPROT Privileged */
6085 uint32_t hprotbuff_0 : 1; /* SD/MMC HPROT Bufferable */
6086 uint32_t hprotcache_0 : 1; /* SD/MMC HPROT Cacheable */
6087 uint32_t : 28; /* *UNDEFINED* */
6088};
6089
6090/* The typedef declaration for register ALT_SYSMGR_SDMMC_L3MST. */
6091typedef volatile struct ALT_SYSMGR_SDMMC_L3MST_s ALT_SYSMGR_SDMMC_L3MST_t;
6092#endif /* __ASSEMBLY__ */
6093
6094/* The byte offset of the ALT_SYSMGR_SDMMC_L3MST register from the beginning of the component. */
6095#define ALT_SYSMGR_SDMMC_L3MST_OFST 0x4
6096
6097#ifndef __ASSEMBLY__
6098/*
6099 * WARNING: The C register and register group struct declarations are provided for
6100 * convenience and illustrative purposes. They should, however, be used with
6101 * caution as the C language standard provides no guarantees about the alignment or
6102 * atomicity of device memory accesses. The recommended practice for writing
6103 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6104 * alt_write_word() functions.
6105 *
6106 * The struct declaration for register group ALT_SYSMGR_SDMMC.
6107 */
6108 struct ALT_SYSMGR_SDMMC_s
6109{
6110 volatile ALT_SYSMGR_SDMMC_CTL_t ctrl; /* ALT_SYSMGR_SDMMC_CTL */
6111 volatile ALT_SYSMGR_SDMMC_L3MST_t l3master; /* ALT_SYSMGR_SDMMC_L3MST */
6112};
6113
6114/* The typedef declaration for register group ALT_SYSMGR_SDMMC. */
6115typedef volatile struct ALT_SYSMGR_SDMMC_s ALT_SYSMGR_SDMMC_t;
6116/* The struct declaration for the raw register contents of register group ALT_SYSMGR_SDMMC. */
6117 struct ALT_SYSMGR_SDMMC_raw_s
6118{
6119 volatile uint32_t ctrl; /* ALT_SYSMGR_SDMMC_CTL */
6120 volatile uint32_t l3master; /* ALT_SYSMGR_SDMMC_L3MST */
6121};
6122
6123/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_SDMMC. */
6124typedef volatile struct ALT_SYSMGR_SDMMC_raw_s ALT_SYSMGR_SDMMC_raw_t;
6125#endif /* __ASSEMBLY__ */
6126
6127
6128/*
6129 * Register Group : NAND Flash Controller Register Group - ALT_SYSMGR_NAND
6130 * NAND Flash Controller Register Group
6131 *
6132 * Registers related to NAND Flash Controller which aren't located in the NAND
6133 * Flash Controller itself.
6134 *
6135 */
6136/*
6137 * Register : Bootstrap Control Register - bootstrap
6138 *
6139 * Bootstrap fields sampled by NAND Flash Controller when released from reset.
6140 *
6141 * All fields are reset by a cold or warm reset.
6142 *
6143 * Register Layout
6144 *
6145 * Bits | Access | Reset | Description
6146 * :-------|:-------|:------|:--------------------------------------
6147 * [0] | RW | 0x0 | Bootstrap Inhibit Initialization
6148 * [1] | RW | 0x0 | Bootstrap 512 Byte Device
6149 * [2] | RW | 0x0 | Bootstrap Inhibit Load Block 0 Page 0
6150 * [3] | RW | 0x0 | Bootstrap Two Row Address Cycles
6151 * [31:4] | ??? | 0x0 | *UNDEFINED*
6152 *
6153 */
6154/*
6155 * Field : Bootstrap Inhibit Initialization - noinit
6156 *
6157 * If 1, inhibits NAND Flash Controller from performing initialization when coming
6158 * out of reset. Instead, software must program all registers pertaining to device
6159 * parameters like page size, width, etc.
6160 *
6161 * Field Access Macros:
6162 *
6163 */
6164/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */
6165#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_LSB 0
6166/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */
6167#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_MSB 0
6168/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */
6169#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_WIDTH 1
6170/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value. */
6171#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET_MSK 0x00000001
6172/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value. */
6173#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_CLR_MSK 0xfffffffe
6174/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */
6175#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_RESET 0x0
6176/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT field value from a register. */
6177#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_GET(value) (((value) & 0x00000001) >> 0)
6178/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value suitable for setting the register. */
6179#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET(value) (((value) << 0) & 0x00000001)
6180
6181/*
6182 * Field : Bootstrap 512 Byte Device - page512
6183 *
6184 * If 1, NAND device has a 512 byte page size.
6185 *
6186 * Field Access Macros:
6187 *
6188 */
6189/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */
6190#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_LSB 1
6191/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */
6192#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_MSB 1
6193/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */
6194#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_WIDTH 1
6195/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value. */
6196#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET_MSK 0x00000002
6197/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value. */
6198#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_CLR_MSK 0xfffffffd
6199/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */
6200#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_RESET 0x0
6201/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 field value from a register. */
6202#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_GET(value) (((value) & 0x00000002) >> 1)
6203/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value suitable for setting the register. */
6204#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET(value) (((value) << 1) & 0x00000002)
6205
6206/*
6207 * Field : Bootstrap Inhibit Load Block 0 Page 0 - noloadb0p0
6208 *
6209 * If 1, inhibits NAND Flash Controller from loading page 0 of block 0 of the NAND
6210 * device as part of the initialization procedure.
6211 *
6212 * Field Access Macros:
6213 *
6214 */
6215/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */
6216#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_LSB 2
6217/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */
6218#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_MSB 2
6219/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */
6220#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_WIDTH 1
6221/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value. */
6222#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET_MSK 0x00000004
6223/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value. */
6224#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_CLR_MSK 0xfffffffb
6225/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */
6226#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_RESET 0x0
6227/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 field value from a register. */
6228#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_GET(value) (((value) & 0x00000004) >> 2)
6229/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value suitable for setting the register. */
6230#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET(value) (((value) << 2) & 0x00000004)
6231
6232/*
6233 * Field : Bootstrap Two Row Address Cycles - tworowaddr
6234 *
6235 * If 1, NAND device requires only 2 row address cycles instead of the normal 3 row
6236 * address cycles.
6237 *
6238 * Field Access Macros:
6239 *
6240 */
6241/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */
6242#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_LSB 3
6243/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */
6244#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_MSB 3
6245/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */
6246#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_WIDTH 1
6247/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value. */
6248#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET_MSK 0x00000008
6249/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value. */
6250#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_CLR_MSK 0xfffffff7
6251/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */
6252#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_RESET 0x0
6253/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR field value from a register. */
6254#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_GET(value) (((value) & 0x00000008) >> 3)
6255/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value suitable for setting the register. */
6256#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET(value) (((value) << 3) & 0x00000008)
6257
6258#ifndef __ASSEMBLY__
6259/*
6260 * WARNING: The C register and register group struct declarations are provided for
6261 * convenience and illustrative purposes. They should, however, be used with
6262 * caution as the C language standard provides no guarantees about the alignment or
6263 * atomicity of device memory accesses. The recommended practice for writing
6264 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6265 * alt_write_word() functions.
6266 *
6267 * The struct declaration for register ALT_SYSMGR_NAND_BOOTSTRAP.
6268 */
6269 struct ALT_SYSMGR_NAND_BOOTSTRAP_s
6270{
6271 uint32_t noinit : 1; /* Bootstrap Inhibit Initialization */
6272 uint32_t page512 : 1; /* Bootstrap 512 Byte Device */
6273 uint32_t noloadb0p0 : 1; /* Bootstrap Inhibit Load Block 0 Page 0 */
6274 uint32_t tworowaddr : 1; /* Bootstrap Two Row Address Cycles */
6275 uint32_t : 28; /* *UNDEFINED* */
6276};
6277
6278/* The typedef declaration for register ALT_SYSMGR_NAND_BOOTSTRAP. */
6279typedef volatile struct ALT_SYSMGR_NAND_BOOTSTRAP_s ALT_SYSMGR_NAND_BOOTSTRAP_t;
6280#endif /* __ASSEMBLY__ */
6281
6282/* The byte offset of the ALT_SYSMGR_NAND_BOOTSTRAP register from the beginning of the component. */
6283#define ALT_SYSMGR_NAND_BOOTSTRAP_OFST 0x0
6284
6285/*
6286 * Register : NAND L3 Master AxCACHE Register - l3master
6287 *
6288 * Controls the L3 master ARCACHE and AWCACHE AXI signals.
6289 *
6290 * These register bits should be updated only during system initialization prior to
6291 * removing the peripheral from reset. They may not be changed dynamically during
6292 * peripheral operation
6293 *
6294 * All fields are reset by a cold or warm reset.
6295 *
6296 * Register Layout
6297 *
6298 * Bits | Access | Reset | Description
6299 * :-------|:-------|:------|:-------------
6300 * [3:0] | RW | 0x0 | NAND ARCACHE
6301 * [7:4] | RW | 0x0 | NAND AWCACHE
6302 * [31:8] | ??? | 0x0 | *UNDEFINED*
6303 *
6304 */
6305/*
6306 * Field : NAND ARCACHE - arcache_0
6307 *
6308 * Specifies the value of the module ARCACHE signal.
6309 *
6310 * Field Enumeration Values:
6311 *
6312 * Enum | Value | Description
6313 * :-------------------------------------------------------|:------|:-------------------------------------------------
6314 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable.
6315 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF | 0x1 | Bufferable only.
6316 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate.
6317 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate.
6318 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 | 0x4 | Reserved.
6319 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 | 0x5 | Reserved.
6320 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only.
6321 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only.
6322 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 | 0x8 | Reserved.
6323 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 | 0x9 | Reserved.
6324 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes
6325 * : | | only.
6326 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only.
6327 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 | 0xc | Reserved.
6328 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 | 0xd | Reserved.
6329 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads
6330 * : | | and writes.
6331 * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and
6332 * : | | writes.
6333 *
6334 * Field Access Macros:
6335 *
6336 */
6337/*
6338 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6339 *
6340 * Noncacheable and nonbufferable.
6341 */
6342#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0
6343/*
6344 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6345 *
6346 * Bufferable only.
6347 */
6348#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF 0x1
6349/*
6350 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6351 *
6352 * Cacheable, but do not allocate.
6353 */
6354#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2
6355/*
6356 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6357 *
6358 * Cacheable and bufferable, but do not allocate.
6359 */
6360#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
6361/*
6362 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6363 *
6364 * Reserved.
6365 */
6366#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 0x4
6367/*
6368 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6369 *
6370 * Reserved.
6371 */
6372#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 0x5
6373/*
6374 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6375 *
6376 * Cacheable write-through, allocate on reads only.
6377 */
6378#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
6379/*
6380 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6381 *
6382 * Cacheable write-back, allocate on reads only.
6383 */
6384#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
6385/*
6386 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6387 *
6388 * Reserved.
6389 */
6390#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 0x8
6391/*
6392 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6393 *
6394 * Reserved.
6395 */
6396#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 0x9
6397/*
6398 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6399 *
6400 * Cacheable write-through, allocate on writes only.
6401 */
6402#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
6403/*
6404 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6405 *
6406 * Cacheable write-back, allocate on writes only.
6407 */
6408#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
6409/*
6410 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6411 *
6412 * Reserved.
6413 */
6414#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 0xc
6415/*
6416 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6417 *
6418 * Reserved.
6419 */
6420#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 0xd
6421/*
6422 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6423 *
6424 * Cacheable write-through, allocate on both reads and writes.
6425 */
6426#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
6427/*
6428 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6429 *
6430 * Cacheable write-back, allocate on both reads and writes.
6431 */
6432#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
6433
6434/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */
6435#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_LSB 0
6436/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */
6437#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_MSB 3
6438/* The width in bits of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */
6439#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_WIDTH 4
6440/* The mask used to set the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value. */
6441#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET_MSK 0x0000000f
6442/* The mask used to clear the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value. */
6443#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0
6444/* The reset value of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */
6445#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_RESET 0x0
6446/* Extracts the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 field value from a register. */
6447#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0)
6448/* Produces a ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value suitable for setting the register. */
6449#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f)
6450
6451/*
6452 * Field : NAND AWCACHE - awcache_0
6453 *
6454 * Specifies the value of the module AWCACHE signal.
6455 *
6456 * Field Enumeration Values:
6457 *
6458 * Enum | Value | Description
6459 * :-------------------------------------------------------|:------|:-------------------------------------------------
6460 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable.
6461 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF | 0x1 | Bufferable only.
6462 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate.
6463 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate.
6464 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 | 0x4 | Reserved.
6465 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 | 0x5 | Reserved.
6466 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only.
6467 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only.
6468 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 | 0x8 | Reserved.
6469 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 | 0x9 | Reserved.
6470 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes
6471 * : | | only.
6472 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only.
6473 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 | 0xc | Reserved.
6474 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 | 0xd | Reserved.
6475 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads
6476 * : | | and writes.
6477 * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and
6478 * : | | writes.
6479 *
6480 * Field Access Macros:
6481 *
6482 */
6483/*
6484 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6485 *
6486 * Noncacheable and nonbufferable.
6487 */
6488#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0
6489/*
6490 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6491 *
6492 * Bufferable only.
6493 */
6494#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF 0x1
6495/*
6496 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6497 *
6498 * Cacheable, but do not allocate.
6499 */
6500#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2
6501/*
6502 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6503 *
6504 * Cacheable and bufferable, but do not allocate.
6505 */
6506#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
6507/*
6508 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6509 *
6510 * Reserved.
6511 */
6512#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 0x4
6513/*
6514 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6515 *
6516 * Reserved.
6517 */
6518#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 0x5
6519/*
6520 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6521 *
6522 * Cacheable write-through, allocate on reads only.
6523 */
6524#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
6525/*
6526 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6527 *
6528 * Cacheable write-back, allocate on reads only.
6529 */
6530#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
6531/*
6532 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6533 *
6534 * Reserved.
6535 */
6536#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 0x8
6537/*
6538 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6539 *
6540 * Reserved.
6541 */
6542#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 0x9
6543/*
6544 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6545 *
6546 * Cacheable write-through, allocate on writes only.
6547 */
6548#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
6549/*
6550 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6551 *
6552 * Cacheable write-back, allocate on writes only.
6553 */
6554#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
6555/*
6556 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6557 *
6558 * Reserved.
6559 */
6560#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 0xc
6561/*
6562 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6563 *
6564 * Reserved.
6565 */
6566#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 0xd
6567/*
6568 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6569 *
6570 * Cacheable write-through, allocate on both reads and writes.
6571 */
6572#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
6573/*
6574 * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6575 *
6576 * Cacheable write-back, allocate on both reads and writes.
6577 */
6578#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
6579
6580/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */
6581#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_LSB 4
6582/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */
6583#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_MSB 7
6584/* The width in bits of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */
6585#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_WIDTH 4
6586/* The mask used to set the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value. */
6587#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET_MSK 0x000000f0
6588/* The mask used to clear the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value. */
6589#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_CLR_MSK 0xffffff0f
6590/* The reset value of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */
6591#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_RESET 0x0
6592/* Extracts the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 field value from a register. */
6593#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_GET(value) (((value) & 0x000000f0) >> 4)
6594/* Produces a ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value suitable for setting the register. */
6595#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET(value) (((value) << 4) & 0x000000f0)
6596
6597#ifndef __ASSEMBLY__
6598/*
6599 * WARNING: The C register and register group struct declarations are provided for
6600 * convenience and illustrative purposes. They should, however, be used with
6601 * caution as the C language standard provides no guarantees about the alignment or
6602 * atomicity of device memory accesses. The recommended practice for writing
6603 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6604 * alt_write_word() functions.
6605 *
6606 * The struct declaration for register ALT_SYSMGR_NAND_L3MST.
6607 */
6608 struct ALT_SYSMGR_NAND_L3MST_s
6609{
6610 uint32_t arcache_0 : 4; /* NAND ARCACHE */
6611 uint32_t awcache_0 : 4; /* NAND AWCACHE */
6612 uint32_t : 24; /* *UNDEFINED* */
6613};
6614
6615/* The typedef declaration for register ALT_SYSMGR_NAND_L3MST. */
6616typedef volatile struct ALT_SYSMGR_NAND_L3MST_s ALT_SYSMGR_NAND_L3MST_t;
6617#endif /* __ASSEMBLY__ */
6618
6619/* The byte offset of the ALT_SYSMGR_NAND_L3MST register from the beginning of the component. */
6620#define ALT_SYSMGR_NAND_L3MST_OFST 0x4
6621
6622#ifndef __ASSEMBLY__
6623/*
6624 * WARNING: The C register and register group struct declarations are provided for
6625 * convenience and illustrative purposes. They should, however, be used with
6626 * caution as the C language standard provides no guarantees about the alignment or
6627 * atomicity of device memory accesses. The recommended practice for writing
6628 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6629 * alt_write_word() functions.
6630 *
6631 * The struct declaration for register group ALT_SYSMGR_NAND.
6632 */
6633 struct ALT_SYSMGR_NAND_s
6634{
6635 volatile ALT_SYSMGR_NAND_BOOTSTRAP_t bootstrap; /* ALT_SYSMGR_NAND_BOOTSTRAP */
6636 volatile ALT_SYSMGR_NAND_L3MST_t l3master; /* ALT_SYSMGR_NAND_L3MST */
6637};
6638
6639/* The typedef declaration for register group ALT_SYSMGR_NAND. */
6640typedef volatile struct ALT_SYSMGR_NAND_s ALT_SYSMGR_NAND_t;
6641/* The struct declaration for the raw register contents of register group ALT_SYSMGR_NAND. */
6642 struct ALT_SYSMGR_NAND_raw_s
6643{
6644 volatile uint32_t bootstrap; /* ALT_SYSMGR_NAND_BOOTSTRAP */
6645 volatile uint32_t l3master; /* ALT_SYSMGR_NAND_L3MST */
6646};
6647
6648/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_NAND. */
6649typedef volatile struct ALT_SYSMGR_NAND_raw_s ALT_SYSMGR_NAND_raw_t;
6650#endif /* __ASSEMBLY__ */
6651
6652
6653/*
6654 * Register Group : USB Controller Group - ALT_SYSMGR_USB
6655 * USB Controller Group
6656 *
6657 * Registers related to USB Controllers which aren't located inside the USB
6658 * controllers themselves.
6659 *
6660 */
6661/*
6662 * Register : USB L3 Master HPROT Register - l3master
6663 *
6664 * Controls the L3 master HPROT AHB-Lite signal.
6665 *
6666 * These register bits should be updated only during system initialization prior to
6667 * removing the peripheral from reset. They may not be changed dynamically during
6668 * peripheral operation
6669 *
6670 * All fields are reset by a cold or warm reset.
6671 *
6672 * Register Layout
6673 *
6674 * Bits | Access | Reset | Description
6675 * :-------|:-------|:------|:----------------------
6676 * [0] | RW | 0x1 | USB HPROT Data/Opcode
6677 * [1] | RW | 0x1 | USB HPROT Data/Opcode
6678 * [2] | RW | 0x1 | USB HPROT Privileged
6679 * [3] | RW | 0x1 | USB HPROT Privileged
6680 * [4] | RW | 0x0 | USB HPROT Bufferable
6681 * [5] | RW | 0x0 | USB HPROT Bufferable
6682 * [6] | RW | 0x0 | USB HPROT Cacheable
6683 * [7] | RW | 0x0 | USB HPROT Cacheable
6684 * [31:8] | ??? | 0x0 | *UNDEFINED*
6685 *
6686 */
6687/*
6688 * Field : USB HPROT Data/Opcode - hprotdata_0
6689 *
6690 * Specifies if the L3 master access is for data or opcode for the USB modules.
6691 *
6692 * The field array index corresponds to the USB index.
6693 *
6694 * Field Enumeration Values:
6695 *
6696 * Enum | Value | Description
6697 * :------------------------------------------|:------|:-------------
6698 * ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_OPCODE | 0x0 | Opcode fetch
6699 * ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_DATA | 0x1 | Data access
6700 *
6701 * Field Access Macros:
6702 *
6703 */
6704/*
6705 * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_0
6706 *
6707 * Opcode fetch
6708 */
6709#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_OPCODE 0x0
6710/*
6711 * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_0
6712 *
6713 * Data access
6714 */
6715#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_DATA 0x1
6716
6717/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */
6718#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_LSB 0
6719/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */
6720#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_MSB 0
6721/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */
6722#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_WIDTH 1
6723/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value. */
6724#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET_MSK 0x00000001
6725/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value. */
6726#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe
6727/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */
6728#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_RESET 0x1
6729/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 field value from a register. */
6730#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0)
6731/* Produces a ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value suitable for setting the register. */
6732#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001)
6733
6734/*
6735 * Field : USB HPROT Data/Opcode - hprotdata_1
6736 *
6737 * Specifies if the L3 master access is for data or opcode for the USB modules.
6738 *
6739 * The field array index corresponds to the USB index.
6740 *
6741 * Field Enumeration Values:
6742 *
6743 * Enum | Value | Description
6744 * :------------------------------------------|:------|:-------------
6745 * ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_OPCODE | 0x0 | Opcode fetch
6746 * ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_DATA | 0x1 | Data access
6747 *
6748 * Field Access Macros:
6749 *
6750 */
6751/*
6752 * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_1
6753 *
6754 * Opcode fetch
6755 */
6756#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_OPCODE 0x0
6757/*
6758 * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_1
6759 *
6760 * Data access
6761 */
6762#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_DATA 0x1
6763
6764/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */
6765#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_LSB 1
6766/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */
6767#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_MSB 1
6768/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */
6769#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_WIDTH 1
6770/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value. */
6771#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET_MSK 0x00000002
6772/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value. */
6773#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_CLR_MSK 0xfffffffd
6774/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */
6775#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_RESET 0x1
6776/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 field value from a register. */
6777#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_GET(value) (((value) & 0x00000002) >> 1)
6778/* Produces a ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value suitable for setting the register. */
6779#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET(value) (((value) << 1) & 0x00000002)
6780
6781/*
6782 * Field : USB HPROT Privileged - hprotpriv_0
6783 *
6784 * If 1, L3 master accesses for the USB modules are privileged.
6785 *
6786 * The field array index corresponds to the USB index.
6787 *
6788 * Field Access Macros:
6789 *
6790 */
6791/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */
6792#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_LSB 2
6793/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */
6794#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_MSB 2
6795/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */
6796#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_WIDTH 1
6797/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value. */
6798#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET_MSK 0x00000004
6799/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value. */
6800#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffb
6801/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */
6802#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_RESET 0x1
6803/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 field value from a register. */
6804#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000004) >> 2)
6805/* Produces a ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value suitable for setting the register. */
6806#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET(value) (((value) << 2) & 0x00000004)
6807
6808/*
6809 * Field : USB HPROT Privileged - hprotpriv_1
6810 *
6811 * If 1, L3 master accesses for the USB modules are privileged.
6812 *
6813 * The field array index corresponds to the USB index.
6814 *
6815 * Field Access Macros:
6816 *
6817 */
6818/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */
6819#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_LSB 3
6820/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */
6821#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_MSB 3
6822/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */
6823#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_WIDTH 1
6824/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value. */
6825#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET_MSK 0x00000008
6826/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value. */
6827#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_CLR_MSK 0xfffffff7
6828/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */
6829#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_RESET 0x1
6830/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 field value from a register. */
6831#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_GET(value) (((value) & 0x00000008) >> 3)
6832/* Produces a ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value suitable for setting the register. */
6833#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET(value) (((value) << 3) & 0x00000008)
6834
6835/*
6836 * Field : USB HPROT Bufferable - hprotbuff_0
6837 *
6838 * If 1, L3 master accesses for the USB modules are bufferable.
6839 *
6840 * The field array index corresponds to the USB index.
6841 *
6842 * Field Access Macros:
6843 *
6844 */
6845/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */
6846#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_LSB 4
6847/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */
6848#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_MSB 4
6849/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */
6850#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_WIDTH 1
6851/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value. */
6852#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET_MSK 0x00000010
6853/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value. */
6854#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_CLR_MSK 0xffffffef
6855/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */
6856#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_RESET 0x0
6857/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 field value from a register. */
6858#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000010) >> 4)
6859/* Produces a ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value suitable for setting the register. */
6860#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET(value) (((value) << 4) & 0x00000010)
6861
6862/*
6863 * Field : USB HPROT Bufferable - hprotbuff_1
6864 *
6865 * If 1, L3 master accesses for the USB modules are bufferable.
6866 *
6867 * The field array index corresponds to the USB index.
6868 *
6869 * Field Access Macros:
6870 *
6871 */
6872/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */
6873#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_LSB 5
6874/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */
6875#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_MSB 5
6876/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */
6877#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_WIDTH 1
6878/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value. */
6879#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET_MSK 0x00000020
6880/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value. */
6881#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_CLR_MSK 0xffffffdf
6882/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */
6883#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_RESET 0x0
6884/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 field value from a register. */
6885#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_GET(value) (((value) & 0x00000020) >> 5)
6886/* Produces a ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value suitable for setting the register. */
6887#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET(value) (((value) << 5) & 0x00000020)
6888
6889/*
6890 * Field : USB HPROT Cacheable - hprotcache_0
6891 *
6892 * If 1, L3 master accesses for the USB modules are cacheable.
6893 *
6894 * The field array index corresponds to the USB index.
6895 *
6896 * Field Access Macros:
6897 *
6898 */
6899/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */
6900#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_LSB 6
6901/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */
6902#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_MSB 6
6903/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */
6904#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_WIDTH 1
6905/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value. */
6906#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET_MSK 0x00000040
6907/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value. */
6908#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_CLR_MSK 0xffffffbf
6909/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */
6910#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_RESET 0x0
6911/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 field value from a register. */
6912#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000040) >> 6)
6913/* Produces a ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value suitable for setting the register. */
6914#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET(value) (((value) << 6) & 0x00000040)
6915
6916/*
6917 * Field : USB HPROT Cacheable - hprotcache_1
6918 *
6919 * If 1, L3 master accesses for the USB modules are cacheable.
6920 *
6921 * The field array index corresponds to the USB index.
6922 *
6923 * Field Access Macros:
6924 *
6925 */
6926/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */
6927#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_LSB 7
6928/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */
6929#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_MSB 7
6930/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */
6931#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_WIDTH 1
6932/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value. */
6933#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET_MSK 0x00000080
6934/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value. */
6935#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_CLR_MSK 0xffffff7f
6936/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */
6937#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_RESET 0x0
6938/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 field value from a register. */
6939#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_GET(value) (((value) & 0x00000080) >> 7)
6940/* Produces a ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value suitable for setting the register. */
6941#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET(value) (((value) << 7) & 0x00000080)
6942
6943#ifndef __ASSEMBLY__
6944/*
6945 * WARNING: The C register and register group struct declarations are provided for
6946 * convenience and illustrative purposes. They should, however, be used with
6947 * caution as the C language standard provides no guarantees about the alignment or
6948 * atomicity of device memory accesses. The recommended practice for writing
6949 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6950 * alt_write_word() functions.
6951 *
6952 * The struct declaration for register ALT_SYSMGR_USB_L3MST.
6953 */
6954 struct ALT_SYSMGR_USB_L3MST_s
6955{
6956 uint32_t hprotdata_0 : 1; /* USB HPROT Data/Opcode */
6957 uint32_t hprotdata_1 : 1; /* USB HPROT Data/Opcode */
6958 uint32_t hprotpriv_0 : 1; /* USB HPROT Privileged */
6959 uint32_t hprotpriv_1 : 1; /* USB HPROT Privileged */
6960 uint32_t hprotbuff_0 : 1; /* USB HPROT Bufferable */
6961 uint32_t hprotbuff_1 : 1; /* USB HPROT Bufferable */
6962 uint32_t hprotcache_0 : 1; /* USB HPROT Cacheable */
6963 uint32_t hprotcache_1 : 1; /* USB HPROT Cacheable */
6964 uint32_t : 24; /* *UNDEFINED* */
6965};
6966
6967/* The typedef declaration for register ALT_SYSMGR_USB_L3MST. */
6968typedef volatile struct ALT_SYSMGR_USB_L3MST_s ALT_SYSMGR_USB_L3MST_t;
6969#endif /* __ASSEMBLY__ */
6970
6971/* The byte offset of the ALT_SYSMGR_USB_L3MST register from the beginning of the component. */
6972#define ALT_SYSMGR_USB_L3MST_OFST 0x0
6973
6974#ifndef __ASSEMBLY__
6975/*
6976 * WARNING: The C register and register group struct declarations are provided for
6977 * convenience and illustrative purposes. They should, however, be used with
6978 * caution as the C language standard provides no guarantees about the alignment or
6979 * atomicity of device memory accesses. The recommended practice for writing
6980 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6981 * alt_write_word() functions.
6982 *
6983 * The struct declaration for register group ALT_SYSMGR_USB.
6984 */
6985 struct ALT_SYSMGR_USB_s
6986{
6987 volatile ALT_SYSMGR_USB_L3MST_t l3master; /* ALT_SYSMGR_USB_L3MST */
6988};
6989
6990/* The typedef declaration for register group ALT_SYSMGR_USB. */
6991typedef volatile struct ALT_SYSMGR_USB_s ALT_SYSMGR_USB_t;
6992/* The struct declaration for the raw register contents of register group ALT_SYSMGR_USB. */
6993 struct ALT_SYSMGR_USB_raw_s
6994{
6995 volatile uint32_t l3master; /* ALT_SYSMGR_USB_L3MST */
6996};
6997
6998/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_USB. */
6999typedef volatile struct ALT_SYSMGR_USB_raw_s ALT_SYSMGR_USB_raw_t;
7000#endif /* __ASSEMBLY__ */
7001
7002
7003/*
7004 * Register Group : ECC Management Register Group - ALT_SYSMGR_ECC
7005 * ECC Management Register Group
7006 *
7007 * ECC error status and control for all ECC-protected HPS RAM blocks.
7008 *
7009 */
7010/*
7011 * Register : L2 Data RAM ECC Enable Register - l2
7012 *
7013 * This register is used to enable ECC on the L2 Data RAM. ECC errors can be
7014 * injected into the write path using bits in this register. This register contains
7015 * interrupt status of the ECC single/double bit error.
7016 *
7017 * Only reset by a cold reset (ignores warm reset).
7018 *
7019 * Register Layout
7020 *
7021 * Bits | Access | Reset | Description
7022 * :-------|:-------|:------|:---------------------------------------------------------
7023 * [0] | RW | 0x0 | L2 Data RAM ECC Enable
7024 * [1] | RW | 0x0 | L2 Data RAM ECC inject single, correctable Error
7025 * [2] | RW | 0x0 | L2 Data RAM ECC inject double bit, non-correctable error
7026 * [31:3] | ??? | 0x0 | *UNDEFINED*
7027 *
7028 */
7029/*
7030 * Field : L2 Data RAM ECC Enable - en
7031 *
7032 * Enable ECC for L2 Data RAM
7033 *
7034 * Field Access Macros:
7035 *
7036 */
7037/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_EN register field. */
7038#define ALT_SYSMGR_ECC_L2_EN_LSB 0
7039/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_EN register field. */
7040#define ALT_SYSMGR_ECC_L2_EN_MSB 0
7041/* The width in bits of the ALT_SYSMGR_ECC_L2_EN register field. */
7042#define ALT_SYSMGR_ECC_L2_EN_WIDTH 1
7043/* The mask used to set the ALT_SYSMGR_ECC_L2_EN register field value. */
7044#define ALT_SYSMGR_ECC_L2_EN_SET_MSK 0x00000001
7045/* The mask used to clear the ALT_SYSMGR_ECC_L2_EN register field value. */
7046#define ALT_SYSMGR_ECC_L2_EN_CLR_MSK 0xfffffffe
7047/* The reset value of the ALT_SYSMGR_ECC_L2_EN register field. */
7048#define ALT_SYSMGR_ECC_L2_EN_RESET 0x0
7049/* Extracts the ALT_SYSMGR_ECC_L2_EN field value from a register. */
7050#define ALT_SYSMGR_ECC_L2_EN_GET(value) (((value) & 0x00000001) >> 0)
7051/* Produces a ALT_SYSMGR_ECC_L2_EN register field value suitable for setting the register. */
7052#define ALT_SYSMGR_ECC_L2_EN_SET(value) (((value) << 0) & 0x00000001)
7053
7054/*
7055 * Field : L2 Data RAM ECC inject single, correctable Error - injs
7056 *
7057 * Changing this bit from zero to one injects a single, correctable error into the
7058 * L2 Data RAM. This only injects one error into the L2 Data RAM.
7059 *
7060 * Field Access Macros:
7061 *
7062 */
7063/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_INJS register field. */
7064#define ALT_SYSMGR_ECC_L2_INJS_LSB 1
7065/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_INJS register field. */
7066#define ALT_SYSMGR_ECC_L2_INJS_MSB 1
7067/* The width in bits of the ALT_SYSMGR_ECC_L2_INJS register field. */
7068#define ALT_SYSMGR_ECC_L2_INJS_WIDTH 1
7069/* The mask used to set the ALT_SYSMGR_ECC_L2_INJS register field value. */
7070#define ALT_SYSMGR_ECC_L2_INJS_SET_MSK 0x00000002
7071/* The mask used to clear the ALT_SYSMGR_ECC_L2_INJS register field value. */
7072#define ALT_SYSMGR_ECC_L2_INJS_CLR_MSK 0xfffffffd
7073/* The reset value of the ALT_SYSMGR_ECC_L2_INJS register field. */
7074#define ALT_SYSMGR_ECC_L2_INJS_RESET 0x0
7075/* Extracts the ALT_SYSMGR_ECC_L2_INJS field value from a register. */
7076#define ALT_SYSMGR_ECC_L2_INJS_GET(value) (((value) & 0x00000002) >> 1)
7077/* Produces a ALT_SYSMGR_ECC_L2_INJS register field value suitable for setting the register. */
7078#define ALT_SYSMGR_ECC_L2_INJS_SET(value) (((value) << 1) & 0x00000002)
7079
7080/*
7081 * Field : L2 Data RAM ECC inject double bit, non-correctable error - injd
7082 *
7083 * Changing this bit from zero to one injects a double, non-correctable error into
7084 * the L2 Data RAM. This only injects one double bit error into the L2 Data RAM.
7085 *
7086 * Field Access Macros:
7087 *
7088 */
7089/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_INJD register field. */
7090#define ALT_SYSMGR_ECC_L2_INJD_LSB 2
7091/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_INJD register field. */
7092#define ALT_SYSMGR_ECC_L2_INJD_MSB 2
7093/* The width in bits of the ALT_SYSMGR_ECC_L2_INJD register field. */
7094#define ALT_SYSMGR_ECC_L2_INJD_WIDTH 1
7095/* The mask used to set the ALT_SYSMGR_ECC_L2_INJD register field value. */
7096#define ALT_SYSMGR_ECC_L2_INJD_SET_MSK 0x00000004
7097/* The mask used to clear the ALT_SYSMGR_ECC_L2_INJD register field value. */
7098#define ALT_SYSMGR_ECC_L2_INJD_CLR_MSK 0xfffffffb
7099/* The reset value of the ALT_SYSMGR_ECC_L2_INJD register field. */
7100#define ALT_SYSMGR_ECC_L2_INJD_RESET 0x0
7101/* Extracts the ALT_SYSMGR_ECC_L2_INJD field value from a register. */
7102#define ALT_SYSMGR_ECC_L2_INJD_GET(value) (((value) & 0x00000004) >> 2)
7103/* Produces a ALT_SYSMGR_ECC_L2_INJD register field value suitable for setting the register. */
7104#define ALT_SYSMGR_ECC_L2_INJD_SET(value) (((value) << 2) & 0x00000004)
7105
7106#ifndef __ASSEMBLY__
7107/*
7108 * WARNING: The C register and register group struct declarations are provided for
7109 * convenience and illustrative purposes. They should, however, be used with
7110 * caution as the C language standard provides no guarantees about the alignment or
7111 * atomicity of device memory accesses. The recommended practice for writing
7112 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7113 * alt_write_word() functions.
7114 *
7115 * The struct declaration for register ALT_SYSMGR_ECC_L2.
7116 */
7117 struct ALT_SYSMGR_ECC_L2_s
7118{
7119 uint32_t en : 1; /* L2 Data RAM ECC Enable */
7120 uint32_t injs : 1; /* L2 Data RAM ECC inject single, correctable Error */
7121 uint32_t injd : 1; /* L2 Data RAM ECC inject double bit, non-correctable error */
7122 uint32_t : 29; /* *UNDEFINED* */
7123};
7124
7125/* The typedef declaration for register ALT_SYSMGR_ECC_L2. */
7126typedef volatile struct ALT_SYSMGR_ECC_L2_s ALT_SYSMGR_ECC_L2_t;
7127#endif /* __ASSEMBLY__ */
7128
7129/* The byte offset of the ALT_SYSMGR_ECC_L2 register from the beginning of the component. */
7130#define ALT_SYSMGR_ECC_L2_OFST 0x0
7131
7132/*
7133 * Register : On-chip RAM ECC Enable Register - ocram
7134 *
7135 * This register is used to enable ECC on the On-chip RAM. ECC errors can be
7136 * injected into the write path using bits in this register. This register contains
7137 * interrupt status of the ECC single/double bit error.
7138 *
7139 * Only reset by a cold reset (ignores warm reset).
7140 *
7141 * Register Layout
7142 *
7143 * Bits | Access | Reset | Description
7144 * :-------|:-------|:------|:-------------------------------------------------------------------
7145 * [0] | RW | 0x0 | On-chip RAM ECC Enable
7146 * [1] | RW | 0x0 | On-chip RAM ECC inject single, correctable Error
7147 * [2] | RW | 0x0 | On-chip RAM ECC inject double bit, non-correctable error
7148 * [3] | RW | 0x0 | On-chip RAM ECC single, correctable error interrupt status
7149 * [4] | RW | 0x0 | On-chip RAM ECC double bit, non-correctable error interrupt status
7150 * [31:5] | ??? | 0x0 | *UNDEFINED*
7151 *
7152 */
7153/*
7154 * Field : On-chip RAM ECC Enable - en
7155 *
7156 * Enable ECC for On-chip RAM
7157 *
7158 * Field Access Macros:
7159 *
7160 */
7161/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_EN register field. */
7162#define ALT_SYSMGR_ECC_OCRAM_EN_LSB 0
7163/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_EN register field. */
7164#define ALT_SYSMGR_ECC_OCRAM_EN_MSB 0
7165/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_EN register field. */
7166#define ALT_SYSMGR_ECC_OCRAM_EN_WIDTH 1
7167/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_EN register field value. */
7168#define ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK 0x00000001
7169/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_EN register field value. */
7170#define ALT_SYSMGR_ECC_OCRAM_EN_CLR_MSK 0xfffffffe
7171/* The reset value of the ALT_SYSMGR_ECC_OCRAM_EN register field. */
7172#define ALT_SYSMGR_ECC_OCRAM_EN_RESET 0x0
7173/* Extracts the ALT_SYSMGR_ECC_OCRAM_EN field value from a register. */
7174#define ALT_SYSMGR_ECC_OCRAM_EN_GET(value) (((value) & 0x00000001) >> 0)
7175/* Produces a ALT_SYSMGR_ECC_OCRAM_EN register field value suitable for setting the register. */
7176#define ALT_SYSMGR_ECC_OCRAM_EN_SET(value) (((value) << 0) & 0x00000001)
7177
7178/*
7179 * Field : On-chip RAM ECC inject single, correctable Error - injs
7180 *
7181 * Changing this bit from zero to one injects a single, correctable error into the
7182 * On-chip RAM. This only injects one error into the On-chip RAM.
7183 *
7184 * Field Access Macros:
7185 *
7186 */
7187/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */
7188#define ALT_SYSMGR_ECC_OCRAM_INJS_LSB 1
7189/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */
7190#define ALT_SYSMGR_ECC_OCRAM_INJS_MSB 1
7191/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */
7192#define ALT_SYSMGR_ECC_OCRAM_INJS_WIDTH 1
7193/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_INJS register field value. */
7194#define ALT_SYSMGR_ECC_OCRAM_INJS_SET_MSK 0x00000002
7195/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_INJS register field value. */
7196#define ALT_SYSMGR_ECC_OCRAM_INJS_CLR_MSK 0xfffffffd
7197/* The reset value of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */
7198#define ALT_SYSMGR_ECC_OCRAM_INJS_RESET 0x0
7199/* Extracts the ALT_SYSMGR_ECC_OCRAM_INJS field value from a register. */
7200#define ALT_SYSMGR_ECC_OCRAM_INJS_GET(value) (((value) & 0x00000002) >> 1)
7201/* Produces a ALT_SYSMGR_ECC_OCRAM_INJS register field value suitable for setting the register. */
7202#define ALT_SYSMGR_ECC_OCRAM_INJS_SET(value) (((value) << 1) & 0x00000002)
7203
7204/*
7205 * Field : On-chip RAM ECC inject double bit, non-correctable error - injd
7206 *
7207 * Changing this bit from zero to one injects a double, non-correctable error into
7208 * the On-chip RAM. This only injects one double bit error into the On-chip RAM.
7209 *
7210 * Field Access Macros:
7211 *
7212 */
7213/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */
7214#define ALT_SYSMGR_ECC_OCRAM_INJD_LSB 2
7215/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */
7216#define ALT_SYSMGR_ECC_OCRAM_INJD_MSB 2
7217/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */
7218#define ALT_SYSMGR_ECC_OCRAM_INJD_WIDTH 1
7219/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_INJD register field value. */
7220#define ALT_SYSMGR_ECC_OCRAM_INJD_SET_MSK 0x00000004
7221/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_INJD register field value. */
7222#define ALT_SYSMGR_ECC_OCRAM_INJD_CLR_MSK 0xfffffffb
7223/* The reset value of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */
7224#define ALT_SYSMGR_ECC_OCRAM_INJD_RESET 0x0
7225/* Extracts the ALT_SYSMGR_ECC_OCRAM_INJD field value from a register. */
7226#define ALT_SYSMGR_ECC_OCRAM_INJD_GET(value) (((value) & 0x00000004) >> 2)
7227/* Produces a ALT_SYSMGR_ECC_OCRAM_INJD register field value suitable for setting the register. */
7228#define ALT_SYSMGR_ECC_OCRAM_INJD_SET(value) (((value) << 2) & 0x00000004)
7229
7230/*
7231 * Field : On-chip RAM ECC single, correctable error interrupt status - serr
7232 *
7233 * This bit is an interrupt status bit for On-chip RAM ECC single, correctable
7234 * error. It is set by hardware when single, correctable error occurs in On-chip
7235 * RAM. Software needs to write 1 into this bit to clear the interrupt status.
7236 *
7237 * Field Access Macros:
7238 *
7239 */
7240/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */
7241#define ALT_SYSMGR_ECC_OCRAM_SERR_LSB 3
7242/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */
7243#define ALT_SYSMGR_ECC_OCRAM_SERR_MSB 3
7244/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */
7245#define ALT_SYSMGR_ECC_OCRAM_SERR_WIDTH 1
7246/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_SERR register field value. */
7247#define ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK 0x00000008
7248/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_SERR register field value. */
7249#define ALT_SYSMGR_ECC_OCRAM_SERR_CLR_MSK 0xfffffff7
7250/* The reset value of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */
7251#define ALT_SYSMGR_ECC_OCRAM_SERR_RESET 0x0
7252/* Extracts the ALT_SYSMGR_ECC_OCRAM_SERR field value from a register. */
7253#define ALT_SYSMGR_ECC_OCRAM_SERR_GET(value) (((value) & 0x00000008) >> 3)
7254/* Produces a ALT_SYSMGR_ECC_OCRAM_SERR register field value suitable for setting the register. */
7255#define ALT_SYSMGR_ECC_OCRAM_SERR_SET(value) (((value) << 3) & 0x00000008)
7256
7257/*
7258 * Field : On-chip RAM ECC double bit, non-correctable error interrupt status - derr
7259 *
7260 * This bit is an interrupt status bit for On-chip RAM ECC double bit, non-
7261 * correctable error. It is set by hardware when double bit, non-correctable error
7262 * occurs in On-chip RAM. Software needs to write 1 into this bit to clear the
7263 * interrupt status.
7264 *
7265 * Field Access Macros:
7266 *
7267 */
7268/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */
7269#define ALT_SYSMGR_ECC_OCRAM_DERR_LSB 4
7270/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */
7271#define ALT_SYSMGR_ECC_OCRAM_DERR_MSB 4
7272/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */
7273#define ALT_SYSMGR_ECC_OCRAM_DERR_WIDTH 1
7274/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_DERR register field value. */
7275#define ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK 0x00000010
7276/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_DERR register field value. */
7277#define ALT_SYSMGR_ECC_OCRAM_DERR_CLR_MSK 0xffffffef
7278/* The reset value of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */
7279#define ALT_SYSMGR_ECC_OCRAM_DERR_RESET 0x0
7280/* Extracts the ALT_SYSMGR_ECC_OCRAM_DERR field value from a register. */
7281#define ALT_SYSMGR_ECC_OCRAM_DERR_GET(value) (((value) & 0x00000010) >> 4)
7282/* Produces a ALT_SYSMGR_ECC_OCRAM_DERR register field value suitable for setting the register. */
7283#define ALT_SYSMGR_ECC_OCRAM_DERR_SET(value) (((value) << 4) & 0x00000010)
7284
7285#ifndef __ASSEMBLY__
7286/*
7287 * WARNING: The C register and register group struct declarations are provided for
7288 * convenience and illustrative purposes. They should, however, be used with
7289 * caution as the C language standard provides no guarantees about the alignment or
7290 * atomicity of device memory accesses. The recommended practice for writing
7291 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7292 * alt_write_word() functions.
7293 *
7294 * The struct declaration for register ALT_SYSMGR_ECC_OCRAM.
7295 */
7296 struct ALT_SYSMGR_ECC_OCRAM_s
7297{
7298 uint32_t en : 1; /* On-chip RAM ECC Enable */
7299 uint32_t injs : 1; /* On-chip RAM ECC inject single, correctable Error */
7300 uint32_t injd : 1; /* On-chip RAM ECC inject double bit, non-correctable error */
7301 uint32_t serr : 1; /* On-chip RAM ECC single, correctable error interrupt status */
7302 uint32_t derr : 1; /* On-chip RAM ECC double bit, non-correctable error interrupt status */
7303 uint32_t : 27; /* *UNDEFINED* */
7304};
7305
7306/* The typedef declaration for register ALT_SYSMGR_ECC_OCRAM. */
7307typedef volatile struct ALT_SYSMGR_ECC_OCRAM_s ALT_SYSMGR_ECC_OCRAM_t;
7308#endif /* __ASSEMBLY__ */
7309
7310/* The byte offset of the ALT_SYSMGR_ECC_OCRAM register from the beginning of the component. */
7311#define ALT_SYSMGR_ECC_OCRAM_OFST 0x4
7312
7313/*
7314 * Register : USB0 RAM ECC Enable Register - usb0
7315 *
7316 * This register is used to enable ECC on the USB0 RAM. ECC errors can be injected
7317 * into the write path using bits in this register. This register contains
7318 * interrupt status of the ECC single/double bit error.
7319 *
7320 * Only reset by a cold reset (ignores warm reset).
7321 *
7322 * Register Layout
7323 *
7324 * Bits | Access | Reset | Description
7325 * :-------|:-------|:------|:----------------------------------------------------------------
7326 * [0] | RW | 0x0 | USB0 RAM ECC Enable
7327 * [1] | RW | 0x0 | USB0 RAM ECC inject single, correctable Error
7328 * [2] | RW | 0x0 | USB0 RAM ECC inject double bit, non-correctable error
7329 * [3] | RW | 0x0 | USB0 RAM ECC single, correctable error interrupt status
7330 * [4] | RW | 0x0 | USB0 RAM ECC double bit, non-correctable error interrupt status
7331 * [31:5] | ??? | 0x0 | *UNDEFINED*
7332 *
7333 */
7334/*
7335 * Field : USB0 RAM ECC Enable - en
7336 *
7337 * Enable ECC for USB0 RAM
7338 *
7339 * Field Access Macros:
7340 *
7341 */
7342/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_EN register field. */
7343#define ALT_SYSMGR_ECC_USB0_EN_LSB 0
7344/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_EN register field. */
7345#define ALT_SYSMGR_ECC_USB0_EN_MSB 0
7346/* The width in bits of the ALT_SYSMGR_ECC_USB0_EN register field. */
7347#define ALT_SYSMGR_ECC_USB0_EN_WIDTH 1
7348/* The mask used to set the ALT_SYSMGR_ECC_USB0_EN register field value. */
7349#define ALT_SYSMGR_ECC_USB0_EN_SET_MSK 0x00000001
7350/* The mask used to clear the ALT_SYSMGR_ECC_USB0_EN register field value. */
7351#define ALT_SYSMGR_ECC_USB0_EN_CLR_MSK 0xfffffffe
7352/* The reset value of the ALT_SYSMGR_ECC_USB0_EN register field. */
7353#define ALT_SYSMGR_ECC_USB0_EN_RESET 0x0
7354/* Extracts the ALT_SYSMGR_ECC_USB0_EN field value from a register. */
7355#define ALT_SYSMGR_ECC_USB0_EN_GET(value) (((value) & 0x00000001) >> 0)
7356/* Produces a ALT_SYSMGR_ECC_USB0_EN register field value suitable for setting the register. */
7357#define ALT_SYSMGR_ECC_USB0_EN_SET(value) (((value) << 0) & 0x00000001)
7358
7359/*
7360 * Field : USB0 RAM ECC inject single, correctable Error - injs
7361 *
7362 * Changing this bit from zero to one injects a single, correctable error into the
7363 * USB0 RAM. This only injects one error into the USB0 RAM.
7364 *
7365 * Field Access Macros:
7366 *
7367 */
7368/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_INJS register field. */
7369#define ALT_SYSMGR_ECC_USB0_INJS_LSB 1
7370/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_INJS register field. */
7371#define ALT_SYSMGR_ECC_USB0_INJS_MSB 1
7372/* The width in bits of the ALT_SYSMGR_ECC_USB0_INJS register field. */
7373#define ALT_SYSMGR_ECC_USB0_INJS_WIDTH 1
7374/* The mask used to set the ALT_SYSMGR_ECC_USB0_INJS register field value. */
7375#define ALT_SYSMGR_ECC_USB0_INJS_SET_MSK 0x00000002
7376/* The mask used to clear the ALT_SYSMGR_ECC_USB0_INJS register field value. */
7377#define ALT_SYSMGR_ECC_USB0_INJS_CLR_MSK 0xfffffffd
7378/* The reset value of the ALT_SYSMGR_ECC_USB0_INJS register field. */
7379#define ALT_SYSMGR_ECC_USB0_INJS_RESET 0x0
7380/* Extracts the ALT_SYSMGR_ECC_USB0_INJS field value from a register. */
7381#define ALT_SYSMGR_ECC_USB0_INJS_GET(value) (((value) & 0x00000002) >> 1)
7382/* Produces a ALT_SYSMGR_ECC_USB0_INJS register field value suitable for setting the register. */
7383#define ALT_SYSMGR_ECC_USB0_INJS_SET(value) (((value) << 1) & 0x00000002)
7384
7385/*
7386 * Field : USB0 RAM ECC inject double bit, non-correctable error - injd
7387 *
7388 * Changing this bit from zero to one injects a double, non-correctable error into
7389 * the USB0 RAM. This only injects one double bit error into the USB0 RAM.
7390 *
7391 * Field Access Macros:
7392 *
7393 */
7394/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_INJD register field. */
7395#define ALT_SYSMGR_ECC_USB0_INJD_LSB 2
7396/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_INJD register field. */
7397#define ALT_SYSMGR_ECC_USB0_INJD_MSB 2
7398/* The width in bits of the ALT_SYSMGR_ECC_USB0_INJD register field. */
7399#define ALT_SYSMGR_ECC_USB0_INJD_WIDTH 1
7400/* The mask used to set the ALT_SYSMGR_ECC_USB0_INJD register field value. */
7401#define ALT_SYSMGR_ECC_USB0_INJD_SET_MSK 0x00000004
7402/* The mask used to clear the ALT_SYSMGR_ECC_USB0_INJD register field value. */
7403#define ALT_SYSMGR_ECC_USB0_INJD_CLR_MSK 0xfffffffb
7404/* The reset value of the ALT_SYSMGR_ECC_USB0_INJD register field. */
7405#define ALT_SYSMGR_ECC_USB0_INJD_RESET 0x0
7406/* Extracts the ALT_SYSMGR_ECC_USB0_INJD field value from a register. */
7407#define ALT_SYSMGR_ECC_USB0_INJD_GET(value) (((value) & 0x00000004) >> 2)
7408/* Produces a ALT_SYSMGR_ECC_USB0_INJD register field value suitable for setting the register. */
7409#define ALT_SYSMGR_ECC_USB0_INJD_SET(value) (((value) << 2) & 0x00000004)
7410
7411/*
7412 * Field : USB0 RAM ECC single, correctable error interrupt status - serr
7413 *
7414 * This bit is an interrupt status bit for USB0 RAM ECC single, correctable error.
7415 * It is set by hardware when single, correctable error occurs in USB0 RAM.
7416 * Software needs to write 1 into this bit to clear the interrupt status.
7417 *
7418 * Field Access Macros:
7419 *
7420 */
7421/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_SERR register field. */
7422#define ALT_SYSMGR_ECC_USB0_SERR_LSB 3
7423/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_SERR register field. */
7424#define ALT_SYSMGR_ECC_USB0_SERR_MSB 3
7425/* The width in bits of the ALT_SYSMGR_ECC_USB0_SERR register field. */
7426#define ALT_SYSMGR_ECC_USB0_SERR_WIDTH 1
7427/* The mask used to set the ALT_SYSMGR_ECC_USB0_SERR register field value. */
7428#define ALT_SYSMGR_ECC_USB0_SERR_SET_MSK 0x00000008
7429/* The mask used to clear the ALT_SYSMGR_ECC_USB0_SERR register field value. */
7430#define ALT_SYSMGR_ECC_USB0_SERR_CLR_MSK 0xfffffff7
7431/* The reset value of the ALT_SYSMGR_ECC_USB0_SERR register field. */
7432#define ALT_SYSMGR_ECC_USB0_SERR_RESET 0x0
7433/* Extracts the ALT_SYSMGR_ECC_USB0_SERR field value from a register. */
7434#define ALT_SYSMGR_ECC_USB0_SERR_GET(value) (((value) & 0x00000008) >> 3)
7435/* Produces a ALT_SYSMGR_ECC_USB0_SERR register field value suitable for setting the register. */
7436#define ALT_SYSMGR_ECC_USB0_SERR_SET(value) (((value) << 3) & 0x00000008)
7437
7438/*
7439 * Field : USB0 RAM ECC double bit, non-correctable error interrupt status - derr
7440 *
7441 * This bit is an interrupt status bit for USB0 RAM ECC double bit, non-correctable
7442 * error. It is set by hardware when double bit, non-correctable error occurs in
7443 * USB0 RAM. Software needs to write 1 into this bit to clear the interrupt status.
7444 *
7445 * Field Access Macros:
7446 *
7447 */
7448/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_DERR register field. */
7449#define ALT_SYSMGR_ECC_USB0_DERR_LSB 4
7450/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_DERR register field. */
7451#define ALT_SYSMGR_ECC_USB0_DERR_MSB 4
7452/* The width in bits of the ALT_SYSMGR_ECC_USB0_DERR register field. */
7453#define ALT_SYSMGR_ECC_USB0_DERR_WIDTH 1
7454/* The mask used to set the ALT_SYSMGR_ECC_USB0_DERR register field value. */
7455#define ALT_SYSMGR_ECC_USB0_DERR_SET_MSK 0x00000010
7456/* The mask used to clear the ALT_SYSMGR_ECC_USB0_DERR register field value. */
7457#define ALT_SYSMGR_ECC_USB0_DERR_CLR_MSK 0xffffffef
7458/* The reset value of the ALT_SYSMGR_ECC_USB0_DERR register field. */
7459#define ALT_SYSMGR_ECC_USB0_DERR_RESET 0x0
7460/* Extracts the ALT_SYSMGR_ECC_USB0_DERR field value from a register. */
7461#define ALT_SYSMGR_ECC_USB0_DERR_GET(value) (((value) & 0x00000010) >> 4)
7462/* Produces a ALT_SYSMGR_ECC_USB0_DERR register field value suitable for setting the register. */
7463#define ALT_SYSMGR_ECC_USB0_DERR_SET(value) (((value) << 4) & 0x00000010)
7464
7465#ifndef __ASSEMBLY__
7466/*
7467 * WARNING: The C register and register group struct declarations are provided for
7468 * convenience and illustrative purposes. They should, however, be used with
7469 * caution as the C language standard provides no guarantees about the alignment or
7470 * atomicity of device memory accesses. The recommended practice for writing
7471 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7472 * alt_write_word() functions.
7473 *
7474 * The struct declaration for register ALT_SYSMGR_ECC_USB0.
7475 */
7476 struct ALT_SYSMGR_ECC_USB0_s
7477{
7478 uint32_t en : 1; /* USB0 RAM ECC Enable */
7479 uint32_t injs : 1; /* USB0 RAM ECC inject single, correctable Error */
7480 uint32_t injd : 1; /* USB0 RAM ECC inject double bit, non-correctable error */
7481 uint32_t serr : 1; /* USB0 RAM ECC single, correctable error interrupt status */
7482 uint32_t derr : 1; /* USB0 RAM ECC double bit, non-correctable error interrupt status */
7483 uint32_t : 27; /* *UNDEFINED* */
7484};
7485
7486/* The typedef declaration for register ALT_SYSMGR_ECC_USB0. */
7487typedef volatile struct ALT_SYSMGR_ECC_USB0_s ALT_SYSMGR_ECC_USB0_t;
7488#endif /* __ASSEMBLY__ */
7489
7490/* The byte offset of the ALT_SYSMGR_ECC_USB0 register from the beginning of the component. */
7491#define ALT_SYSMGR_ECC_USB0_OFST 0x8
7492
7493/*
7494 * Register : USB1 RAM ECC Enable Register - usb1
7495 *
7496 * This register is used to enable ECC on the USB1 RAM. ECC errors can be injected
7497 * into the write path using bits in this register. This register contains
7498 * interrupt status of the ECC single/double bit error.
7499 *
7500 * Only reset by a cold reset (ignores warm reset).
7501 *
7502 * Register Layout
7503 *
7504 * Bits | Access | Reset | Description
7505 * :-------|:-------|:------|:----------------------------------------------------------------
7506 * [0] | RW | 0x0 | USB1 RAM ECC Enable
7507 * [1] | RW | 0x0 | USB1 RAM ECC inject single, correctable Error
7508 * [2] | RW | 0x0 | USB1 RAM ECC inject double bit, non-correctable error
7509 * [3] | RW | 0x0 | USB1 RAM ECC single, correctable error interrupt status
7510 * [4] | RW | 0x0 | USB1 RAM ECC double bit, non-correctable error interrupt status
7511 * [31:5] | ??? | 0x0 | *UNDEFINED*
7512 *
7513 */
7514/*
7515 * Field : USB1 RAM ECC Enable - en
7516 *
7517 * Enable ECC for USB1 RAM
7518 *
7519 * Field Access Macros:
7520 *
7521 */
7522/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_EN register field. */
7523#define ALT_SYSMGR_ECC_USB1_EN_LSB 0
7524/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_EN register field. */
7525#define ALT_SYSMGR_ECC_USB1_EN_MSB 0
7526/* The width in bits of the ALT_SYSMGR_ECC_USB1_EN register field. */
7527#define ALT_SYSMGR_ECC_USB1_EN_WIDTH 1
7528/* The mask used to set the ALT_SYSMGR_ECC_USB1_EN register field value. */
7529#define ALT_SYSMGR_ECC_USB1_EN_SET_MSK 0x00000001
7530/* The mask used to clear the ALT_SYSMGR_ECC_USB1_EN register field value. */
7531#define ALT_SYSMGR_ECC_USB1_EN_CLR_MSK 0xfffffffe
7532/* The reset value of the ALT_SYSMGR_ECC_USB1_EN register field. */
7533#define ALT_SYSMGR_ECC_USB1_EN_RESET 0x0
7534/* Extracts the ALT_SYSMGR_ECC_USB1_EN field value from a register. */
7535#define ALT_SYSMGR_ECC_USB1_EN_GET(value) (((value) & 0x00000001) >> 0)
7536/* Produces a ALT_SYSMGR_ECC_USB1_EN register field value suitable for setting the register. */
7537#define ALT_SYSMGR_ECC_USB1_EN_SET(value) (((value) << 0) & 0x00000001)
7538
7539/*
7540 * Field : USB1 RAM ECC inject single, correctable Error - injs
7541 *
7542 * Changing this bit from zero to one injects a single, correctable error into the
7543 * USB1 RAM. This only injects one error into the USB1 RAM.
7544 *
7545 * Field Access Macros:
7546 *
7547 */
7548/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_INJS register field. */
7549#define ALT_SYSMGR_ECC_USB1_INJS_LSB 1
7550/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_INJS register field. */
7551#define ALT_SYSMGR_ECC_USB1_INJS_MSB 1
7552/* The width in bits of the ALT_SYSMGR_ECC_USB1_INJS register field. */
7553#define ALT_SYSMGR_ECC_USB1_INJS_WIDTH 1
7554/* The mask used to set the ALT_SYSMGR_ECC_USB1_INJS register field value. */
7555#define ALT_SYSMGR_ECC_USB1_INJS_SET_MSK 0x00000002
7556/* The mask used to clear the ALT_SYSMGR_ECC_USB1_INJS register field value. */
7557#define ALT_SYSMGR_ECC_USB1_INJS_CLR_MSK 0xfffffffd
7558/* The reset value of the ALT_SYSMGR_ECC_USB1_INJS register field. */
7559#define ALT_SYSMGR_ECC_USB1_INJS_RESET 0x0
7560/* Extracts the ALT_SYSMGR_ECC_USB1_INJS field value from a register. */
7561#define ALT_SYSMGR_ECC_USB1_INJS_GET(value) (((value) & 0x00000002) >> 1)
7562/* Produces a ALT_SYSMGR_ECC_USB1_INJS register field value suitable for setting the register. */
7563#define ALT_SYSMGR_ECC_USB1_INJS_SET(value) (((value) << 1) & 0x00000002)
7564
7565/*
7566 * Field : USB1 RAM ECC inject double bit, non-correctable error - injd
7567 *
7568 * Changing this bit from zero to one injects a double, non-correctable error into
7569 * the USB1 RAM. This only injects one double bit error into the USB1 RAM.
7570 *
7571 * Field Access Macros:
7572 *
7573 */
7574/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_INJD register field. */
7575#define ALT_SYSMGR_ECC_USB1_INJD_LSB 2
7576/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_INJD register field. */
7577#define ALT_SYSMGR_ECC_USB1_INJD_MSB 2
7578/* The width in bits of the ALT_SYSMGR_ECC_USB1_INJD register field. */
7579#define ALT_SYSMGR_ECC_USB1_INJD_WIDTH 1
7580/* The mask used to set the ALT_SYSMGR_ECC_USB1_INJD register field value. */
7581#define ALT_SYSMGR_ECC_USB1_INJD_SET_MSK 0x00000004
7582/* The mask used to clear the ALT_SYSMGR_ECC_USB1_INJD register field value. */
7583#define ALT_SYSMGR_ECC_USB1_INJD_CLR_MSK 0xfffffffb
7584/* The reset value of the ALT_SYSMGR_ECC_USB1_INJD register field. */
7585#define ALT_SYSMGR_ECC_USB1_INJD_RESET 0x0
7586/* Extracts the ALT_SYSMGR_ECC_USB1_INJD field value from a register. */
7587#define ALT_SYSMGR_ECC_USB1_INJD_GET(value) (((value) & 0x00000004) >> 2)
7588/* Produces a ALT_SYSMGR_ECC_USB1_INJD register field value suitable for setting the register. */
7589#define ALT_SYSMGR_ECC_USB1_INJD_SET(value) (((value) << 2) & 0x00000004)
7590
7591/*
7592 * Field : USB1 RAM ECC single, correctable error interrupt status - serr
7593 *
7594 * This bit is an interrupt status bit for USB1 RAM ECC single, correctable error.
7595 * It is set by hardware when single, correctable error occurs in USB1 RAM.
7596 * Software needs to write 1 into this bit to clear the interrupt status.
7597 *
7598 * Field Access Macros:
7599 *
7600 */
7601/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_SERR register field. */
7602#define ALT_SYSMGR_ECC_USB1_SERR_LSB 3
7603/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_SERR register field. */
7604#define ALT_SYSMGR_ECC_USB1_SERR_MSB 3
7605/* The width in bits of the ALT_SYSMGR_ECC_USB1_SERR register field. */
7606#define ALT_SYSMGR_ECC_USB1_SERR_WIDTH 1
7607/* The mask used to set the ALT_SYSMGR_ECC_USB1_SERR register field value. */
7608#define ALT_SYSMGR_ECC_USB1_SERR_SET_MSK 0x00000008
7609/* The mask used to clear the ALT_SYSMGR_ECC_USB1_SERR register field value. */
7610#define ALT_SYSMGR_ECC_USB1_SERR_CLR_MSK 0xfffffff7
7611/* The reset value of the ALT_SYSMGR_ECC_USB1_SERR register field. */
7612#define ALT_SYSMGR_ECC_USB1_SERR_RESET 0x0
7613/* Extracts the ALT_SYSMGR_ECC_USB1_SERR field value from a register. */
7614#define ALT_SYSMGR_ECC_USB1_SERR_GET(value) (((value) & 0x00000008) >> 3)
7615/* Produces a ALT_SYSMGR_ECC_USB1_SERR register field value suitable for setting the register. */
7616#define ALT_SYSMGR_ECC_USB1_SERR_SET(value) (((value) << 3) & 0x00000008)
7617
7618/*
7619 * Field : USB1 RAM ECC double bit, non-correctable error interrupt status - derr
7620 *
7621 * This bit is an interrupt status bit for USB1 RAM ECC double bit, non-correctable
7622 * error. It is set by hardware when double bit, non-correctable error occurs in
7623 * USB1 RAM. Software needs to write 1 into this bit to clear the interrupt status.
7624 *
7625 * Field Access Macros:
7626 *
7627 */
7628/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_DERR register field. */
7629#define ALT_SYSMGR_ECC_USB1_DERR_LSB 4
7630/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_DERR register field. */
7631#define ALT_SYSMGR_ECC_USB1_DERR_MSB 4
7632/* The width in bits of the ALT_SYSMGR_ECC_USB1_DERR register field. */
7633#define ALT_SYSMGR_ECC_USB1_DERR_WIDTH 1
7634/* The mask used to set the ALT_SYSMGR_ECC_USB1_DERR register field value. */
7635#define ALT_SYSMGR_ECC_USB1_DERR_SET_MSK 0x00000010
7636/* The mask used to clear the ALT_SYSMGR_ECC_USB1_DERR register field value. */
7637#define ALT_SYSMGR_ECC_USB1_DERR_CLR_MSK 0xffffffef
7638/* The reset value of the ALT_SYSMGR_ECC_USB1_DERR register field. */
7639#define ALT_SYSMGR_ECC_USB1_DERR_RESET 0x0
7640/* Extracts the ALT_SYSMGR_ECC_USB1_DERR field value from a register. */
7641#define ALT_SYSMGR_ECC_USB1_DERR_GET(value) (((value) & 0x00000010) >> 4)
7642/* Produces a ALT_SYSMGR_ECC_USB1_DERR register field value suitable for setting the register. */
7643#define ALT_SYSMGR_ECC_USB1_DERR_SET(value) (((value) << 4) & 0x00000010)
7644
7645#ifndef __ASSEMBLY__
7646/*
7647 * WARNING: The C register and register group struct declarations are provided for
7648 * convenience and illustrative purposes. They should, however, be used with
7649 * caution as the C language standard provides no guarantees about the alignment or
7650 * atomicity of device memory accesses. The recommended practice for writing
7651 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7652 * alt_write_word() functions.
7653 *
7654 * The struct declaration for register ALT_SYSMGR_ECC_USB1.
7655 */
7656 struct ALT_SYSMGR_ECC_USB1_s
7657{
7658 uint32_t en : 1; /* USB1 RAM ECC Enable */
7659 uint32_t injs : 1; /* USB1 RAM ECC inject single, correctable Error */
7660 uint32_t injd : 1; /* USB1 RAM ECC inject double bit, non-correctable error */
7661 uint32_t serr : 1; /* USB1 RAM ECC single, correctable error interrupt status */
7662 uint32_t derr : 1; /* USB1 RAM ECC double bit, non-correctable error interrupt status */
7663 uint32_t : 27; /* *UNDEFINED* */
7664};
7665
7666/* The typedef declaration for register ALT_SYSMGR_ECC_USB1. */
7667typedef volatile struct ALT_SYSMGR_ECC_USB1_s ALT_SYSMGR_ECC_USB1_t;
7668#endif /* __ASSEMBLY__ */
7669
7670/* The byte offset of the ALT_SYSMGR_ECC_USB1 register from the beginning of the component. */
7671#define ALT_SYSMGR_ECC_USB1_OFST 0xc
7672
7673/*
7674 * Register : EMAC0 RAM ECC Enable Register - emac0
7675 *
7676 * This register is used to enable ECC on the EMAC0 RAM. ECC errors can be injected
7677 * into the write path using bits in this register. This register contains
7678 * interrupt status of the ECC single/double bit error.
7679 *
7680 * Only reset by a cold reset (ignores warm reset).
7681 *
7682 * Register Layout
7683 *
7684 * Bits | Access | Reset | Description
7685 * :-------|:-------|:------|:------------------------------------------------------------------------
7686 * [0] | RW | 0x0 | EMAC0 RAM ECC Enable
7687 * [1] | RW | 0x0 | EMAC0 TXFIFO RAM ECC inject single, correctable Error
7688 * [2] | RW | 0x0 | EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error
7689 * [3] | RW | 0x0 | EMAC0 RXFIFO RAM ECC inject single, correctable Error
7690 * [4] | RW | 0x0 | EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error
7691 * [5] | RW | 0x0 | EMAC0 TXFIFO RAM ECC single, correctable error interrupt status
7692 * [6] | RW | 0x0 | EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status
7693 * [7] | RW | 0x0 | EMAC0 RXFIFO RAM ECC single, correctable error interrupt status
7694 * [8] | RW | 0x0 | EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status
7695 * [31:9] | ??? | 0x0 | *UNDEFINED*
7696 *
7697 */
7698/*
7699 * Field : EMAC0 RAM ECC Enable - en
7700 *
7701 * Enable ECC for EMAC0 RAM
7702 *
7703 * Field Access Macros:
7704 *
7705 */
7706/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_EN register field. */
7707#define ALT_SYSMGR_ECC_EMAC0_EN_LSB 0
7708/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_EN register field. */
7709#define ALT_SYSMGR_ECC_EMAC0_EN_MSB 0
7710/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_EN register field. */
7711#define ALT_SYSMGR_ECC_EMAC0_EN_WIDTH 1
7712/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_EN register field value. */
7713#define ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK 0x00000001
7714/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_EN register field value. */
7715#define ALT_SYSMGR_ECC_EMAC0_EN_CLR_MSK 0xfffffffe
7716/* The reset value of the ALT_SYSMGR_ECC_EMAC0_EN register field. */
7717#define ALT_SYSMGR_ECC_EMAC0_EN_RESET 0x0
7718/* Extracts the ALT_SYSMGR_ECC_EMAC0_EN field value from a register. */
7719#define ALT_SYSMGR_ECC_EMAC0_EN_GET(value) (((value) & 0x00000001) >> 0)
7720/* Produces a ALT_SYSMGR_ECC_EMAC0_EN register field value suitable for setting the register. */
7721#define ALT_SYSMGR_ECC_EMAC0_EN_SET(value) (((value) << 0) & 0x00000001)
7722
7723/*
7724 * Field : EMAC0 TXFIFO RAM ECC inject single, correctable Error - txfifoinjs
7725 *
7726 * Changing this bit from zero to one injects a single, correctable error into the
7727 * EMAC0 TXFIFO RAM. This only injects one error into the EMAC0 TXFIFO RAM.
7728 *
7729 * Field Access Macros:
7730 *
7731 */
7732/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */
7733#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_LSB 1
7734/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */
7735#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_MSB 1
7736/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */
7737#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_WIDTH 1
7738/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value. */
7739#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET_MSK 0x00000002
7740/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value. */
7741#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_CLR_MSK 0xfffffffd
7742/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */
7743#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_RESET 0x0
7744/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS field value from a register. */
7745#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1)
7746/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value suitable for setting the register. */
7747#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002)
7748
7749/*
7750 * Field : EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error - txfifoinjd
7751 *
7752 * Changing this bit from zero to one injects a double, non-correctable error into
7753 * the EMAC0 TXFIFO RAM. This only injects one double bit error into the EMAC0
7754 * TXFIFO RAM.
7755 *
7756 * Field Access Macros:
7757 *
7758 */
7759/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */
7760#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_LSB 2
7761/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */
7762#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_MSB 2
7763/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */
7764#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_WIDTH 1
7765/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value. */
7766#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET_MSK 0x00000004
7767/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value. */
7768#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_CLR_MSK 0xfffffffb
7769/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */
7770#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_RESET 0x0
7771/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD field value from a register. */
7772#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2)
7773/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value suitable for setting the register. */
7774#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004)
7775
7776/*
7777 * Field : EMAC0 RXFIFO RAM ECC inject single, correctable Error - rxfifoinjs
7778 *
7779 * Changing this bit from zero to one injects a single, correctable error into the
7780 * EMAC0 RXFIFO RAM. This only injects one error into the EMAC0 RXFIFO RAM.
7781 *
7782 * Field Access Macros:
7783 *
7784 */
7785/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */
7786#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_LSB 3
7787/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */
7788#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_MSB 3
7789/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */
7790#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_WIDTH 1
7791/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value. */
7792#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET_MSK 0x00000008
7793/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value. */
7794#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_CLR_MSK 0xfffffff7
7795/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */
7796#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_RESET 0x0
7797/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS field value from a register. */
7798#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3)
7799/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value suitable for setting the register. */
7800#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008)
7801
7802/*
7803 * Field : EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error - rxfifoinjd
7804 *
7805 * Changing this bit from zero to one injects a double, non-correctable error into
7806 * the EMAC0 RXFIFO RAM. This only injects one double bit error into the EMAC0
7807 * RXFIFO RAM.
7808 *
7809 * Field Access Macros:
7810 *
7811 */
7812/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */
7813#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_LSB 4
7814/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */
7815#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_MSB 4
7816/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */
7817#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_WIDTH 1
7818/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value. */
7819#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET_MSK 0x00000010
7820/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value. */
7821#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_CLR_MSK 0xffffffef
7822/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */
7823#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_RESET 0x0
7824/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD field value from a register. */
7825#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4)
7826/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value suitable for setting the register. */
7827#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010)
7828
7829/*
7830 * Field : EMAC0 TXFIFO RAM ECC single, correctable error interrupt status - txfifoserr
7831 *
7832 * This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC single, correctable
7833 * error. It is set by hardware when single, correctable error occurs in EMAC0
7834 * TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt
7835 * status.
7836 *
7837 * Field Access Macros:
7838 *
7839 */
7840/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */
7841#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_LSB 5
7842/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */
7843#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_MSB 5
7844/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */
7845#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_WIDTH 1
7846/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value. */
7847#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK 0x00000020
7848/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value. */
7849#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_CLR_MSK 0xffffffdf
7850/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */
7851#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_RESET 0x0
7852/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR field value from a register. */
7853#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5)
7854/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value suitable for setting the register. */
7855#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020)
7856
7857/*
7858 * Field : EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status - txfifoderr
7859 *
7860 * This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC double bit, non-
7861 * correctable error. It is set by hardware when double bit, non-correctable error
7862 * occurs in EMAC0 TXFIFO RAM. Software needs to write 1 into this bit to clear the
7863 * interrupt status.
7864 *
7865 * Field Access Macros:
7866 *
7867 */
7868/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */
7869#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_LSB 6
7870/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */
7871#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_MSB 6
7872/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */
7873#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_WIDTH 1
7874/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value. */
7875#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK 0x00000040
7876/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value. */
7877#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_CLR_MSK 0xffffffbf
7878/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */
7879#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_RESET 0x0
7880/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR field value from a register. */
7881#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6)
7882/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value suitable for setting the register. */
7883#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040)
7884
7885/*
7886 * Field : EMAC0 RXFIFO RAM ECC single, correctable error interrupt status - rxfifoserr
7887 *
7888 * This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC single, correctable
7889 * error. It is set by hardware when single, correctable error occurs in EMAC0
7890 * RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt
7891 * status.
7892 *
7893 * Field Access Macros:
7894 *
7895 */
7896/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */
7897#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_LSB 7
7898/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */
7899#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_MSB 7
7900/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */
7901#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_WIDTH 1
7902/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value. */
7903#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK 0x00000080
7904/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value. */
7905#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_CLR_MSK 0xffffff7f
7906/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */
7907#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_RESET 0x0
7908/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR field value from a register. */
7909#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7)
7910/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value suitable for setting the register. */
7911#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080)
7912
7913/*
7914 * Field : EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status - rxfifoderr
7915 *
7916 * This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC double bit, non-
7917 * correctable error. It is set by hardware when double bit, non-correctable error
7918 * occurs in EMAC0 RXFIFO RAM. Software needs to write 1 into this bit to clear the
7919 * interrupt status.
7920 *
7921 * Field Access Macros:
7922 *
7923 */
7924/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */
7925#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_LSB 8
7926/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */
7927#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_MSB 8
7928/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */
7929#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_WIDTH 1
7930/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value. */
7931#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK 0x00000100
7932/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value. */
7933#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_CLR_MSK 0xfffffeff
7934/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */
7935#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_RESET 0x0
7936/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR field value from a register. */
7937#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8)
7938/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value suitable for setting the register. */
7939#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100)
7940
7941#ifndef __ASSEMBLY__
7942/*
7943 * WARNING: The C register and register group struct declarations are provided for
7944 * convenience and illustrative purposes. They should, however, be used with
7945 * caution as the C language standard provides no guarantees about the alignment or
7946 * atomicity of device memory accesses. The recommended practice for writing
7947 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7948 * alt_write_word() functions.
7949 *
7950 * The struct declaration for register ALT_SYSMGR_ECC_EMAC0.
7951 */
7952 struct ALT_SYSMGR_ECC_EMAC0_s
7953{
7954 uint32_t en : 1; /* EMAC0 RAM ECC Enable */
7955 uint32_t txfifoinjs : 1; /* EMAC0 TXFIFO RAM ECC inject single, correctable Error */
7956 uint32_t txfifoinjd : 1; /* EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error */
7957 uint32_t rxfifoinjs : 1; /* EMAC0 RXFIFO RAM ECC inject single, correctable Error */
7958 uint32_t rxfifoinjd : 1; /* EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error */
7959 uint32_t txfifoserr : 1; /* EMAC0 TXFIFO RAM ECC single, correctable error interrupt status */
7960 uint32_t txfifoderr : 1; /* EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status */
7961 uint32_t rxfifoserr : 1; /* EMAC0 RXFIFO RAM ECC single, correctable error interrupt status */
7962 uint32_t rxfifoderr : 1; /* EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status */
7963 uint32_t : 23; /* *UNDEFINED* */
7964};
7965
7966/* The typedef declaration for register ALT_SYSMGR_ECC_EMAC0. */
7967typedef volatile struct ALT_SYSMGR_ECC_EMAC0_s ALT_SYSMGR_ECC_EMAC0_t;
7968#endif /* __ASSEMBLY__ */
7969
7970/* The byte offset of the ALT_SYSMGR_ECC_EMAC0 register from the beginning of the component. */
7971#define ALT_SYSMGR_ECC_EMAC0_OFST 0x10
7972
7973/*
7974 * Register : EMAC1 RAM ECC Enable Register - emac1
7975 *
7976 * This register is used to enable ECC on the EMAC1 RAM. ECC errors can be injected
7977 * into the write path using bits in this register. This register contains
7978 * interrupt status of the ECC single/double bit error.
7979 *
7980 * Only reset by a cold reset (ignores warm reset).
7981 *
7982 * Register Layout
7983 *
7984 * Bits | Access | Reset | Description
7985 * :-------|:-------|:------|:------------------------------------------------------------------------
7986 * [0] | RW | 0x0 | EMAC1 RAM ECC Enable
7987 * [1] | RW | 0x0 | EMAC1 TXFIFO RAM ECC inject single, correctable Error
7988 * [2] | RW | 0x0 | EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error
7989 * [3] | RW | 0x0 | EMAC1 RXFIFO RAM ECC inject single, correctable Error
7990 * [4] | RW | 0x0 | EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error
7991 * [5] | RW | 0x0 | EMAC1 TXFIFO RAM ECC single, correctable error interrupt status
7992 * [6] | RW | 0x0 | EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status
7993 * [7] | RW | 0x0 | EMAC1 RXFIFO RAM ECC single, correctable error interrupt status
7994 * [8] | RW | 0x0 | EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status
7995 * [31:9] | ??? | 0x0 | *UNDEFINED*
7996 *
7997 */
7998/*
7999 * Field : EMAC1 RAM ECC Enable - en
8000 *
8001 * Enable ECC for EMAC1 RAM
8002 *
8003 * Field Access Macros:
8004 *
8005 */
8006/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_EN register field. */
8007#define ALT_SYSMGR_ECC_EMAC1_EN_LSB 0
8008/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_EN register field. */
8009#define ALT_SYSMGR_ECC_EMAC1_EN_MSB 0
8010/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_EN register field. */
8011#define ALT_SYSMGR_ECC_EMAC1_EN_WIDTH 1
8012/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_EN register field value. */
8013#define ALT_SYSMGR_ECC_EMAC1_EN_SET_MSK 0x00000001
8014/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_EN register field value. */
8015#define ALT_SYSMGR_ECC_EMAC1_EN_CLR_MSK 0xfffffffe
8016/* The reset value of the ALT_SYSMGR_ECC_EMAC1_EN register field. */
8017#define ALT_SYSMGR_ECC_EMAC1_EN_RESET 0x0
8018/* Extracts the ALT_SYSMGR_ECC_EMAC1_EN field value from a register. */
8019#define ALT_SYSMGR_ECC_EMAC1_EN_GET(value) (((value) & 0x00000001) >> 0)
8020/* Produces a ALT_SYSMGR_ECC_EMAC1_EN register field value suitable for setting the register. */
8021#define ALT_SYSMGR_ECC_EMAC1_EN_SET(value) (((value) << 0) & 0x00000001)
8022
8023/*
8024 * Field : EMAC1 TXFIFO RAM ECC inject single, correctable Error - txfifoinjs
8025 *
8026 * Changing this bit from zero to one injects a single, correctable error into the
8027 * EMAC1 TXFIFO RAM. This only injects one error into the EMAC1 TXFIFO RAM.
8028 *
8029 * Field Access Macros:
8030 *
8031 */
8032/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */
8033#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_LSB 1
8034/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */
8035#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_MSB 1
8036/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */
8037#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_WIDTH 1
8038/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value. */
8039#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET_MSK 0x00000002
8040/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value. */
8041#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_CLR_MSK 0xfffffffd
8042/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */
8043#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_RESET 0x0
8044/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS field value from a register. */
8045#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1)
8046/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value suitable for setting the register. */
8047#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002)
8048
8049/*
8050 * Field : EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error - txfifoinjd
8051 *
8052 * Changing this bit from zero to one injects a double, non-correctable error into
8053 * the EMAC1 TXFIFO RAM. This only injects one double bit error into the EMAC1
8054 * TXFIFO RAM.
8055 *
8056 * Field Access Macros:
8057 *
8058 */
8059/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */
8060#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_LSB 2
8061/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */
8062#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_MSB 2
8063/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */
8064#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_WIDTH 1
8065/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value. */
8066#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET_MSK 0x00000004
8067/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value. */
8068#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_CLR_MSK 0xfffffffb
8069/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */
8070#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_RESET 0x0
8071/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD field value from a register. */
8072#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2)
8073/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value suitable for setting the register. */
8074#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004)
8075
8076/*
8077 * Field : EMAC1 RXFIFO RAM ECC inject single, correctable Error - rxfifoinjs
8078 *
8079 * Changing this bit from zero to one injects a single, correctable error into the
8080 * EMAC1 RXFIFO RAM. This only injects one error into the EMAC1 RXFIFO RAM.
8081 *
8082 * Field Access Macros:
8083 *
8084 */
8085/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */
8086#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_LSB 3
8087/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */
8088#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_MSB 3
8089/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */
8090#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_WIDTH 1
8091/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value. */
8092#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET_MSK 0x00000008
8093/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value. */
8094#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_CLR_MSK 0xfffffff7
8095/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */
8096#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_RESET 0x0
8097/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS field value from a register. */
8098#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3)
8099/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value suitable for setting the register. */
8100#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008)
8101
8102/*
8103 * Field : EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error - rxfifoinjd
8104 *
8105 * Changing this bit from zero to one injects a double, non-correctable error into
8106 * the EMAC1 RXFIFO RAM. This only injects one double bit error into the EMAC1
8107 * RXFIFO RAM.
8108 *
8109 * Field Access Macros:
8110 *
8111 */
8112/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */
8113#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_LSB 4
8114/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */
8115#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_MSB 4
8116/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */
8117#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_WIDTH 1
8118/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value. */
8119#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET_MSK 0x00000010
8120/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value. */
8121#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_CLR_MSK 0xffffffef
8122/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */
8123#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_RESET 0x0
8124/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD field value from a register. */
8125#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4)
8126/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value suitable for setting the register. */
8127#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010)
8128
8129/*
8130 * Field : EMAC1 TXFIFO RAM ECC single, correctable error interrupt status - txfifoserr
8131 *
8132 * This bit is an interrupt status bit for EMAC1 TXFIFO RAM ECC single, correctable
8133 * error. It is set by hardware when single, correctable error occurs in EMAC1
8134 * TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt
8135 * status.
8136 *
8137 * Field Access Macros:
8138 *
8139 */
8140/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */
8141#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_LSB 5
8142/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */
8143#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_MSB 5
8144/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */
8145#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_WIDTH 1
8146/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value. */
8147#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET_MSK 0x00000020
8148/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value. */
8149#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_CLR_MSK 0xffffffdf
8150/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */
8151#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_RESET 0x0
8152/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR field value from a register. */
8153#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5)
8154/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value suitable for setting the register. */
8155#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020)
8156
8157/*
8158 * Field : EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status - txfifoderr
8159 *
8160 * This bit is an interrupt status bit for EMAC1 TXFIFO RAM ECC double bit, non-
8161 * correctable error. It is set by hardware when double bit, non-correctable error
8162 * occurs in EMAC1 TXFIFO RAM. Software needs to write 1 into this bit to clear the
8163 * interrupt status.
8164 *
8165 * Field Access Macros:
8166 *
8167 */
8168/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */
8169#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_LSB 6
8170/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */
8171#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_MSB 6
8172/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */
8173#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_WIDTH 1
8174/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value. */
8175#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET_MSK 0x00000040
8176/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value. */
8177#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_CLR_MSK 0xffffffbf
8178/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */
8179#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_RESET 0x0
8180/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR field value from a register. */
8181#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6)
8182/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value suitable for setting the register. */
8183#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040)
8184
8185/*
8186 * Field : EMAC1 RXFIFO RAM ECC single, correctable error interrupt status - rxfifoserr
8187 *
8188 * This bit is an interrupt status bit for EMAC1 RXFIFO RAM ECC single, correctable
8189 * error. It is set by hardware when single, correctable error occurs in EMAC1
8190 * RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt
8191 * status.
8192 *
8193 * Field Access Macros:
8194 *
8195 */
8196/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */
8197#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_LSB 7
8198/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */
8199#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_MSB 7
8200/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */
8201#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_WIDTH 1
8202/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value. */
8203#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET_MSK 0x00000080
8204/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value. */
8205#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_CLR_MSK 0xffffff7f
8206/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */
8207#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_RESET 0x0
8208/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR field value from a register. */
8209#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7)
8210/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value suitable for setting the register. */
8211#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080)
8212
8213/*
8214 * Field : EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status - rxfifoderr
8215 *
8216 * This bit is an interrupt status bit for EMAC1 RXFIFO RAM ECC double bit, non-
8217 * correctable error. It is set by hardware when double bit, non-correctable error
8218 * occurs in EMAC1 RXFIFO RAM. Software needs to write 1 into this bit to clear the
8219 * interrupt status.
8220 *
8221 * Field Access Macros:
8222 *
8223 */
8224/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */
8225#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_LSB 8
8226/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */
8227#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_MSB 8
8228/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */
8229#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_WIDTH 1
8230/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value. */
8231#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET_MSK 0x00000100
8232/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value. */
8233#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_CLR_MSK 0xfffffeff
8234/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */
8235#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_RESET 0x0
8236/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR field value from a register. */
8237#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8)
8238/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value suitable for setting the register. */
8239#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100)
8240
8241#ifndef __ASSEMBLY__
8242/*
8243 * WARNING: The C register and register group struct declarations are provided for
8244 * convenience and illustrative purposes. They should, however, be used with
8245 * caution as the C language standard provides no guarantees about the alignment or
8246 * atomicity of device memory accesses. The recommended practice for writing
8247 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8248 * alt_write_word() functions.
8249 *
8250 * The struct declaration for register ALT_SYSMGR_ECC_EMAC1.
8251 */
8252 struct ALT_SYSMGR_ECC_EMAC1_s
8253{
8254 uint32_t en : 1; /* EMAC1 RAM ECC Enable */
8255 uint32_t txfifoinjs : 1; /* EMAC1 TXFIFO RAM ECC inject single, correctable Error */
8256 uint32_t txfifoinjd : 1; /* EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error */
8257 uint32_t rxfifoinjs : 1; /* EMAC1 RXFIFO RAM ECC inject single, correctable Error */
8258 uint32_t rxfifoinjd : 1; /* EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error */
8259 uint32_t txfifoserr : 1; /* EMAC1 TXFIFO RAM ECC single, correctable error interrupt status */
8260 uint32_t txfifoderr : 1; /* EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status */
8261 uint32_t rxfifoserr : 1; /* EMAC1 RXFIFO RAM ECC single, correctable error interrupt status */
8262 uint32_t rxfifoderr : 1; /* EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status */
8263 uint32_t : 23; /* *UNDEFINED* */
8264};
8265
8266/* The typedef declaration for register ALT_SYSMGR_ECC_EMAC1. */
8267typedef volatile struct ALT_SYSMGR_ECC_EMAC1_s ALT_SYSMGR_ECC_EMAC1_t;
8268#endif /* __ASSEMBLY__ */
8269
8270/* The byte offset of the ALT_SYSMGR_ECC_EMAC1 register from the beginning of the component. */
8271#define ALT_SYSMGR_ECC_EMAC1_OFST 0x14
8272
8273/*
8274 * Register : DMA RAM ECC Enable Register - dma
8275 *
8276 * This register is used to enable ECC on the DMA RAM. ECC errors can be injected
8277 * into the write path using bits in this register. This register contains
8278 * interrupt status of the ECC single/double bit error.
8279 *
8280 * Only reset by a cold reset (ignores warm reset).
8281 *
8282 * Register Layout
8283 *
8284 * Bits | Access | Reset | Description
8285 * :-------|:-------|:------|:---------------------------------------------------------------
8286 * [0] | RW | 0x0 | DMA RAM ECC Enable
8287 * [1] | RW | 0x0 | DMA RAM ECC inject single, correctable Error
8288 * [2] | RW | 0x0 | DMA RAM ECC inject double bit, non-correctable error
8289 * [3] | RW | 0x0 | DMA RAM ECC single, correctable error interrupt status
8290 * [4] | RW | 0x0 | DMA RAM ECC double bit, non-correctable error interrupt status
8291 * [31:5] | ??? | 0x0 | *UNDEFINED*
8292 *
8293 */
8294/*
8295 * Field : DMA RAM ECC Enable - en
8296 *
8297 * Enable ECC for DMA RAM
8298 *
8299 * Field Access Macros:
8300 *
8301 */
8302/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_EN register field. */
8303#define ALT_SYSMGR_ECC_DMA_EN_LSB 0
8304/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_EN register field. */
8305#define ALT_SYSMGR_ECC_DMA_EN_MSB 0
8306/* The width in bits of the ALT_SYSMGR_ECC_DMA_EN register field. */
8307#define ALT_SYSMGR_ECC_DMA_EN_WIDTH 1
8308/* The mask used to set the ALT_SYSMGR_ECC_DMA_EN register field value. */
8309#define ALT_SYSMGR_ECC_DMA_EN_SET_MSK 0x00000001
8310/* The mask used to clear the ALT_SYSMGR_ECC_DMA_EN register field value. */
8311#define ALT_SYSMGR_ECC_DMA_EN_CLR_MSK 0xfffffffe
8312/* The reset value of the ALT_SYSMGR_ECC_DMA_EN register field. */
8313#define ALT_SYSMGR_ECC_DMA_EN_RESET 0x0
8314/* Extracts the ALT_SYSMGR_ECC_DMA_EN field value from a register. */
8315#define ALT_SYSMGR_ECC_DMA_EN_GET(value) (((value) & 0x00000001) >> 0)
8316/* Produces a ALT_SYSMGR_ECC_DMA_EN register field value suitable for setting the register. */
8317#define ALT_SYSMGR_ECC_DMA_EN_SET(value) (((value) << 0) & 0x00000001)
8318
8319/*
8320 * Field : DMA RAM ECC inject single, correctable Error - injs
8321 *
8322 * Changing this bit from zero to one injects a single, correctable error into the
8323 * DMA RAM. This only injects one error into the DMA RAM.
8324 *
8325 * Field Access Macros:
8326 *
8327 */
8328/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_INJS register field. */
8329#define ALT_SYSMGR_ECC_DMA_INJS_LSB 1
8330/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_INJS register field. */
8331#define ALT_SYSMGR_ECC_DMA_INJS_MSB 1
8332/* The width in bits of the ALT_SYSMGR_ECC_DMA_INJS register field. */
8333#define ALT_SYSMGR_ECC_DMA_INJS_WIDTH 1
8334/* The mask used to set the ALT_SYSMGR_ECC_DMA_INJS register field value. */
8335#define ALT_SYSMGR_ECC_DMA_INJS_SET_MSK 0x00000002
8336/* The mask used to clear the ALT_SYSMGR_ECC_DMA_INJS register field value. */
8337#define ALT_SYSMGR_ECC_DMA_INJS_CLR_MSK 0xfffffffd
8338/* The reset value of the ALT_SYSMGR_ECC_DMA_INJS register field. */
8339#define ALT_SYSMGR_ECC_DMA_INJS_RESET 0x0
8340/* Extracts the ALT_SYSMGR_ECC_DMA_INJS field value from a register. */
8341#define ALT_SYSMGR_ECC_DMA_INJS_GET(value) (((value) & 0x00000002) >> 1)
8342/* Produces a ALT_SYSMGR_ECC_DMA_INJS register field value suitable for setting the register. */
8343#define ALT_SYSMGR_ECC_DMA_INJS_SET(value) (((value) << 1) & 0x00000002)
8344
8345/*
8346 * Field : DMA RAM ECC inject double bit, non-correctable error - injd
8347 *
8348 * Changing this bit from zero to one injects a double, non-correctable error into
8349 * the DMA RAM. This only injects one double bit error into the DMA RAM.
8350 *
8351 * Field Access Macros:
8352 *
8353 */
8354/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_INJD register field. */
8355#define ALT_SYSMGR_ECC_DMA_INJD_LSB 2
8356/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_INJD register field. */
8357#define ALT_SYSMGR_ECC_DMA_INJD_MSB 2
8358/* The width in bits of the ALT_SYSMGR_ECC_DMA_INJD register field. */
8359#define ALT_SYSMGR_ECC_DMA_INJD_WIDTH 1
8360/* The mask used to set the ALT_SYSMGR_ECC_DMA_INJD register field value. */
8361#define ALT_SYSMGR_ECC_DMA_INJD_SET_MSK 0x00000004
8362/* The mask used to clear the ALT_SYSMGR_ECC_DMA_INJD register field value. */
8363#define ALT_SYSMGR_ECC_DMA_INJD_CLR_MSK 0xfffffffb
8364/* The reset value of the ALT_SYSMGR_ECC_DMA_INJD register field. */
8365#define ALT_SYSMGR_ECC_DMA_INJD_RESET 0x0
8366/* Extracts the ALT_SYSMGR_ECC_DMA_INJD field value from a register. */
8367#define ALT_SYSMGR_ECC_DMA_INJD_GET(value) (((value) & 0x00000004) >> 2)
8368/* Produces a ALT_SYSMGR_ECC_DMA_INJD register field value suitable for setting the register. */
8369#define ALT_SYSMGR_ECC_DMA_INJD_SET(value) (((value) << 2) & 0x00000004)
8370
8371/*
8372 * Field : DMA RAM ECC single, correctable error interrupt status - serr
8373 *
8374 * This bit is an interrupt status bit for DMA RAM ECC single, correctable error.
8375 * It is set by hardware when single, correctable error occurs in DMA RAM. Software
8376 * needs to write 1 into this bit to clear the interrupt status.
8377 *
8378 * Field Access Macros:
8379 *
8380 */
8381/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_SERR register field. */
8382#define ALT_SYSMGR_ECC_DMA_SERR_LSB 3
8383/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_SERR register field. */
8384#define ALT_SYSMGR_ECC_DMA_SERR_MSB 3
8385/* The width in bits of the ALT_SYSMGR_ECC_DMA_SERR register field. */
8386#define ALT_SYSMGR_ECC_DMA_SERR_WIDTH 1
8387/* The mask used to set the ALT_SYSMGR_ECC_DMA_SERR register field value. */
8388#define ALT_SYSMGR_ECC_DMA_SERR_SET_MSK 0x00000008
8389/* The mask used to clear the ALT_SYSMGR_ECC_DMA_SERR register field value. */
8390#define ALT_SYSMGR_ECC_DMA_SERR_CLR_MSK 0xfffffff7
8391/* The reset value of the ALT_SYSMGR_ECC_DMA_SERR register field. */
8392#define ALT_SYSMGR_ECC_DMA_SERR_RESET 0x0
8393/* Extracts the ALT_SYSMGR_ECC_DMA_SERR field value from a register. */
8394#define ALT_SYSMGR_ECC_DMA_SERR_GET(value) (((value) & 0x00000008) >> 3)
8395/* Produces a ALT_SYSMGR_ECC_DMA_SERR register field value suitable for setting the register. */
8396#define ALT_SYSMGR_ECC_DMA_SERR_SET(value) (((value) << 3) & 0x00000008)
8397
8398/*
8399 * Field : DMA RAM ECC double bit, non-correctable error interrupt status - derr
8400 *
8401 * This bit is an interrupt status bit for DMA RAM ECC double bit, non-correctable
8402 * error. It is set by hardware when double bit, non-correctable error occurs in
8403 * DMA RAM. Software needs to write 1 into this bit to clear the interrupt status.
8404 *
8405 * Field Access Macros:
8406 *
8407 */
8408/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_DERR register field. */
8409#define ALT_SYSMGR_ECC_DMA_DERR_LSB 4
8410/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_DERR register field. */
8411#define ALT_SYSMGR_ECC_DMA_DERR_MSB 4
8412/* The width in bits of the ALT_SYSMGR_ECC_DMA_DERR register field. */
8413#define ALT_SYSMGR_ECC_DMA_DERR_WIDTH 1
8414/* The mask used to set the ALT_SYSMGR_ECC_DMA_DERR register field value. */
8415#define ALT_SYSMGR_ECC_DMA_DERR_SET_MSK 0x00000010
8416/* The mask used to clear the ALT_SYSMGR_ECC_DMA_DERR register field value. */
8417#define ALT_SYSMGR_ECC_DMA_DERR_CLR_MSK 0xffffffef
8418/* The reset value of the ALT_SYSMGR_ECC_DMA_DERR register field. */
8419#define ALT_SYSMGR_ECC_DMA_DERR_RESET 0x0
8420/* Extracts the ALT_SYSMGR_ECC_DMA_DERR field value from a register. */
8421#define ALT_SYSMGR_ECC_DMA_DERR_GET(value) (((value) & 0x00000010) >> 4)
8422/* Produces a ALT_SYSMGR_ECC_DMA_DERR register field value suitable for setting the register. */
8423#define ALT_SYSMGR_ECC_DMA_DERR_SET(value) (((value) << 4) & 0x00000010)
8424
8425#ifndef __ASSEMBLY__
8426/*
8427 * WARNING: The C register and register group struct declarations are provided for
8428 * convenience and illustrative purposes. They should, however, be used with
8429 * caution as the C language standard provides no guarantees about the alignment or
8430 * atomicity of device memory accesses. The recommended practice for writing
8431 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8432 * alt_write_word() functions.
8433 *
8434 * The struct declaration for register ALT_SYSMGR_ECC_DMA.
8435 */
8436 struct ALT_SYSMGR_ECC_DMA_s
8437{
8438 uint32_t en : 1; /* DMA RAM ECC Enable */
8439 uint32_t injs : 1; /* DMA RAM ECC inject single, correctable Error */
8440 uint32_t injd : 1; /* DMA RAM ECC inject double bit, non-correctable error */
8441 uint32_t serr : 1; /* DMA RAM ECC single, correctable error interrupt status */
8442 uint32_t derr : 1; /* DMA RAM ECC double bit, non-correctable error interrupt status */
8443 uint32_t : 27; /* *UNDEFINED* */
8444};
8445
8446/* The typedef declaration for register ALT_SYSMGR_ECC_DMA. */
8447typedef volatile struct ALT_SYSMGR_ECC_DMA_s ALT_SYSMGR_ECC_DMA_t;
8448#endif /* __ASSEMBLY__ */
8449
8450/* The byte offset of the ALT_SYSMGR_ECC_DMA register from the beginning of the component. */
8451#define ALT_SYSMGR_ECC_DMA_OFST 0x18
8452
8453/*
8454 * Register : CAN0 RAM ECC Enable Register - can0
8455 *
8456 * This register is used to enable ECC on the CAN0 RAM. ECC errors can be injected
8457 * into the write path using bits in this register. This register contains
8458 * interrupt status of the ECC single/double bit error.
8459 *
8460 * Only reset by a cold reset (ignores warm reset).
8461 *
8462 * Register Layout
8463 *
8464 * Bits | Access | Reset | Description
8465 * :-------|:-------|:------|:----------------------------------------------------------------
8466 * [0] | RW | 0x0 | CAN0 RAM ECC Enable
8467 * [1] | RW | 0x0 | CAN0 RAM ECC inject single, correctable Error
8468 * [2] | RW | 0x0 | CAN0 RAM ECC inject double bit, non-correctable error
8469 * [3] | RW | 0x0 | CAN0 RAM ECC single, correctable error interrupt status
8470 * [4] | RW | 0x0 | CAN0 RAM ECC double bit, non-correctable error interrupt status
8471 * [31:5] | ??? | 0x0 | *UNDEFINED*
8472 *
8473 */
8474/*
8475 * Field : CAN0 RAM ECC Enable - en
8476 *
8477 * Enable ECC for CAN0 RAM
8478 *
8479 * Field Access Macros:
8480 *
8481 */
8482/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_EN register field. */
8483#define ALT_SYSMGR_ECC_CAN0_EN_LSB 0
8484/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_EN register field. */
8485#define ALT_SYSMGR_ECC_CAN0_EN_MSB 0
8486/* The width in bits of the ALT_SYSMGR_ECC_CAN0_EN register field. */
8487#define ALT_SYSMGR_ECC_CAN0_EN_WIDTH 1
8488/* The mask used to set the ALT_SYSMGR_ECC_CAN0_EN register field value. */
8489#define ALT_SYSMGR_ECC_CAN0_EN_SET_MSK 0x00000001
8490/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_EN register field value. */
8491#define ALT_SYSMGR_ECC_CAN0_EN_CLR_MSK 0xfffffffe
8492/* The reset value of the ALT_SYSMGR_ECC_CAN0_EN register field. */
8493#define ALT_SYSMGR_ECC_CAN0_EN_RESET 0x0
8494/* Extracts the ALT_SYSMGR_ECC_CAN0_EN field value from a register. */
8495#define ALT_SYSMGR_ECC_CAN0_EN_GET(value) (((value) & 0x00000001) >> 0)
8496/* Produces a ALT_SYSMGR_ECC_CAN0_EN register field value suitable for setting the register. */
8497#define ALT_SYSMGR_ECC_CAN0_EN_SET(value) (((value) << 0) & 0x00000001)
8498
8499/*
8500 * Field : CAN0 RAM ECC inject single, correctable Error - injs
8501 *
8502 * Changing this bit from zero to one injects a single, correctable error into the
8503 * CAN0 RAM. This only injects one error into the CAN0 RAM.
8504 *
8505 * Field Access Macros:
8506 *
8507 */
8508/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_INJS register field. */
8509#define ALT_SYSMGR_ECC_CAN0_INJS_LSB 1
8510/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_INJS register field. */
8511#define ALT_SYSMGR_ECC_CAN0_INJS_MSB 1
8512/* The width in bits of the ALT_SYSMGR_ECC_CAN0_INJS register field. */
8513#define ALT_SYSMGR_ECC_CAN0_INJS_WIDTH 1
8514/* The mask used to set the ALT_SYSMGR_ECC_CAN0_INJS register field value. */
8515#define ALT_SYSMGR_ECC_CAN0_INJS_SET_MSK 0x00000002
8516/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_INJS register field value. */
8517#define ALT_SYSMGR_ECC_CAN0_INJS_CLR_MSK 0xfffffffd
8518/* The reset value of the ALT_SYSMGR_ECC_CAN0_INJS register field. */
8519#define ALT_SYSMGR_ECC_CAN0_INJS_RESET 0x0
8520/* Extracts the ALT_SYSMGR_ECC_CAN0_INJS field value from a register. */
8521#define ALT_SYSMGR_ECC_CAN0_INJS_GET(value) (((value) & 0x00000002) >> 1)
8522/* Produces a ALT_SYSMGR_ECC_CAN0_INJS register field value suitable for setting the register. */
8523#define ALT_SYSMGR_ECC_CAN0_INJS_SET(value) (((value) << 1) & 0x00000002)
8524
8525/*
8526 * Field : CAN0 RAM ECC inject double bit, non-correctable error - injd
8527 *
8528 * Changing this bit from zero to one injects a double, non-correctable error into
8529 * the CAN0 RAM. This only injects one double bit error into the CAN0 RAM.
8530 *
8531 * Field Access Macros:
8532 *
8533 */
8534/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_INJD register field. */
8535#define ALT_SYSMGR_ECC_CAN0_INJD_LSB 2
8536/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_INJD register field. */
8537#define ALT_SYSMGR_ECC_CAN0_INJD_MSB 2
8538/* The width in bits of the ALT_SYSMGR_ECC_CAN0_INJD register field. */
8539#define ALT_SYSMGR_ECC_CAN0_INJD_WIDTH 1
8540/* The mask used to set the ALT_SYSMGR_ECC_CAN0_INJD register field value. */
8541#define ALT_SYSMGR_ECC_CAN0_INJD_SET_MSK 0x00000004
8542/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_INJD register field value. */
8543#define ALT_SYSMGR_ECC_CAN0_INJD_CLR_MSK 0xfffffffb
8544/* The reset value of the ALT_SYSMGR_ECC_CAN0_INJD register field. */
8545#define ALT_SYSMGR_ECC_CAN0_INJD_RESET 0x0
8546/* Extracts the ALT_SYSMGR_ECC_CAN0_INJD field value from a register. */
8547#define ALT_SYSMGR_ECC_CAN0_INJD_GET(value) (((value) & 0x00000004) >> 2)
8548/* Produces a ALT_SYSMGR_ECC_CAN0_INJD register field value suitable for setting the register. */
8549#define ALT_SYSMGR_ECC_CAN0_INJD_SET(value) (((value) << 2) & 0x00000004)
8550
8551/*
8552 * Field : CAN0 RAM ECC single, correctable error interrupt status - serr
8553 *
8554 * This bit is an interrupt status bit for CAN0 RAM ECC single, correctable error.
8555 * It is set by hardware when single, correctable error occurs in CAN0 RAM.
8556 * Software needs to write 1 into this bit to clear the interrupt status.
8557 *
8558 * Field Access Macros:
8559 *
8560 */
8561/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_SERR register field. */
8562#define ALT_SYSMGR_ECC_CAN0_SERR_LSB 3
8563/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_SERR register field. */
8564#define ALT_SYSMGR_ECC_CAN0_SERR_MSB 3
8565/* The width in bits of the ALT_SYSMGR_ECC_CAN0_SERR register field. */
8566#define ALT_SYSMGR_ECC_CAN0_SERR_WIDTH 1
8567/* The mask used to set the ALT_SYSMGR_ECC_CAN0_SERR register field value. */
8568#define ALT_SYSMGR_ECC_CAN0_SERR_SET_MSK 0x00000008
8569/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_SERR register field value. */
8570#define ALT_SYSMGR_ECC_CAN0_SERR_CLR_MSK 0xfffffff7
8571/* The reset value of the ALT_SYSMGR_ECC_CAN0_SERR register field. */
8572#define ALT_SYSMGR_ECC_CAN0_SERR_RESET 0x0
8573/* Extracts the ALT_SYSMGR_ECC_CAN0_SERR field value from a register. */
8574#define ALT_SYSMGR_ECC_CAN0_SERR_GET(value) (((value) & 0x00000008) >> 3)
8575/* Produces a ALT_SYSMGR_ECC_CAN0_SERR register field value suitable for setting the register. */
8576#define ALT_SYSMGR_ECC_CAN0_SERR_SET(value) (((value) << 3) & 0x00000008)
8577
8578/*
8579 * Field : CAN0 RAM ECC double bit, non-correctable error interrupt status - derr
8580 *
8581 * This bit is an interrupt status bit for CAN0 RAM ECC double bit, non-correctable
8582 * error. It is set by hardware when double bit, non-correctable error occurs in
8583 * CAN0 RAM. Software needs to write 1 into this bit to clear the interrupt status.
8584 *
8585 * Field Access Macros:
8586 *
8587 */
8588/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_DERR register field. */
8589#define ALT_SYSMGR_ECC_CAN0_DERR_LSB 4
8590/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_DERR register field. */
8591#define ALT_SYSMGR_ECC_CAN0_DERR_MSB 4
8592/* The width in bits of the ALT_SYSMGR_ECC_CAN0_DERR register field. */
8593#define ALT_SYSMGR_ECC_CAN0_DERR_WIDTH 1
8594/* The mask used to set the ALT_SYSMGR_ECC_CAN0_DERR register field value. */
8595#define ALT_SYSMGR_ECC_CAN0_DERR_SET_MSK 0x00000010
8596/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_DERR register field value. */
8597#define ALT_SYSMGR_ECC_CAN0_DERR_CLR_MSK 0xffffffef
8598/* The reset value of the ALT_SYSMGR_ECC_CAN0_DERR register field. */
8599#define ALT_SYSMGR_ECC_CAN0_DERR_RESET 0x0
8600/* Extracts the ALT_SYSMGR_ECC_CAN0_DERR field value from a register. */
8601#define ALT_SYSMGR_ECC_CAN0_DERR_GET(value) (((value) & 0x00000010) >> 4)
8602/* Produces a ALT_SYSMGR_ECC_CAN0_DERR register field value suitable for setting the register. */
8603#define ALT_SYSMGR_ECC_CAN0_DERR_SET(value) (((value) << 4) & 0x00000010)
8604
8605#ifndef __ASSEMBLY__
8606/*
8607 * WARNING: The C register and register group struct declarations are provided for
8608 * convenience and illustrative purposes. They should, however, be used with
8609 * caution as the C language standard provides no guarantees about the alignment or
8610 * atomicity of device memory accesses. The recommended practice for writing
8611 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8612 * alt_write_word() functions.
8613 *
8614 * The struct declaration for register ALT_SYSMGR_ECC_CAN0.
8615 */
8616 struct ALT_SYSMGR_ECC_CAN0_s
8617{
8618 uint32_t en : 1; /* CAN0 RAM ECC Enable */
8619 uint32_t injs : 1; /* CAN0 RAM ECC inject single, correctable Error */
8620 uint32_t injd : 1; /* CAN0 RAM ECC inject double bit, non-correctable error */
8621 uint32_t serr : 1; /* CAN0 RAM ECC single, correctable error interrupt status */
8622 uint32_t derr : 1; /* CAN0 RAM ECC double bit, non-correctable error interrupt status */
8623 uint32_t : 27; /* *UNDEFINED* */
8624};
8625
8626/* The typedef declaration for register ALT_SYSMGR_ECC_CAN0. */
8627typedef volatile struct ALT_SYSMGR_ECC_CAN0_s ALT_SYSMGR_ECC_CAN0_t;
8628#endif /* __ASSEMBLY__ */
8629
8630/* The byte offset of the ALT_SYSMGR_ECC_CAN0 register from the beginning of the component. */
8631#define ALT_SYSMGR_ECC_CAN0_OFST 0x1c
8632
8633/*
8634 * Register : CAN1 RAM ECC Enable Register - can1
8635 *
8636 * This register is used to enable ECC on the CAN1 RAM. ECC errors can be injected
8637 * into the write path using bits in this register. This register contains
8638 * interrupt status of the ECC single/double bit error.
8639 *
8640 * Only reset by a cold reset (ignores warm reset).
8641 *
8642 * Register Layout
8643 *
8644 * Bits | Access | Reset | Description
8645 * :-------|:-------|:------|:----------------------------------------------------------------
8646 * [0] | RW | 0x0 | CAN1 RAM ECC Enable
8647 * [1] | RW | 0x0 | CAN1 RAM ECC inject single, correctable Error
8648 * [2] | RW | 0x0 | CAN1 RAM ECC inject double bit, non-correctable error
8649 * [3] | RW | 0x0 | CAN1 RAM ECC single, correctable error interrupt status
8650 * [4] | RW | 0x0 | CAN1 RAM ECC double bit, non-correctable error interrupt status
8651 * [31:5] | ??? | 0x0 | *UNDEFINED*
8652 *
8653 */
8654/*
8655 * Field : CAN1 RAM ECC Enable - en
8656 *
8657 * Enable ECC for CAN1 RAM
8658 *
8659 * Field Access Macros:
8660 *
8661 */
8662/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_EN register field. */
8663#define ALT_SYSMGR_ECC_CAN1_EN_LSB 0
8664/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_EN register field. */
8665#define ALT_SYSMGR_ECC_CAN1_EN_MSB 0
8666/* The width in bits of the ALT_SYSMGR_ECC_CAN1_EN register field. */
8667#define ALT_SYSMGR_ECC_CAN1_EN_WIDTH 1
8668/* The mask used to set the ALT_SYSMGR_ECC_CAN1_EN register field value. */
8669#define ALT_SYSMGR_ECC_CAN1_EN_SET_MSK 0x00000001
8670/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_EN register field value. */
8671#define ALT_SYSMGR_ECC_CAN1_EN_CLR_MSK 0xfffffffe
8672/* The reset value of the ALT_SYSMGR_ECC_CAN1_EN register field. */
8673#define ALT_SYSMGR_ECC_CAN1_EN_RESET 0x0
8674/* Extracts the ALT_SYSMGR_ECC_CAN1_EN field value from a register. */
8675#define ALT_SYSMGR_ECC_CAN1_EN_GET(value) (((value) & 0x00000001) >> 0)
8676/* Produces a ALT_SYSMGR_ECC_CAN1_EN register field value suitable for setting the register. */
8677#define ALT_SYSMGR_ECC_CAN1_EN_SET(value) (((value) << 0) & 0x00000001)
8678
8679/*
8680 * Field : CAN1 RAM ECC inject single, correctable Error - injs
8681 *
8682 * Changing this bit from zero to one injects a single, correctable error into the
8683 * CAN1 RAM. This only injects one error into the CAN1 RAM.
8684 *
8685 * Field Access Macros:
8686 *
8687 */
8688/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_INJS register field. */
8689#define ALT_SYSMGR_ECC_CAN1_INJS_LSB 1
8690/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_INJS register field. */
8691#define ALT_SYSMGR_ECC_CAN1_INJS_MSB 1
8692/* The width in bits of the ALT_SYSMGR_ECC_CAN1_INJS register field. */
8693#define ALT_SYSMGR_ECC_CAN1_INJS_WIDTH 1
8694/* The mask used to set the ALT_SYSMGR_ECC_CAN1_INJS register field value. */
8695#define ALT_SYSMGR_ECC_CAN1_INJS_SET_MSK 0x00000002
8696/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_INJS register field value. */
8697#define ALT_SYSMGR_ECC_CAN1_INJS_CLR_MSK 0xfffffffd
8698/* The reset value of the ALT_SYSMGR_ECC_CAN1_INJS register field. */
8699#define ALT_SYSMGR_ECC_CAN1_INJS_RESET 0x0
8700/* Extracts the ALT_SYSMGR_ECC_CAN1_INJS field value from a register. */
8701#define ALT_SYSMGR_ECC_CAN1_INJS_GET(value) (((value) & 0x00000002) >> 1)
8702/* Produces a ALT_SYSMGR_ECC_CAN1_INJS register field value suitable for setting the register. */
8703#define ALT_SYSMGR_ECC_CAN1_INJS_SET(value) (((value) << 1) & 0x00000002)
8704
8705/*
8706 * Field : CAN1 RAM ECC inject double bit, non-correctable error - injd
8707 *
8708 * Changing this bit from zero to one injects a double, non-correctable error into
8709 * the CAN1 RAM. This only injects one double bit error into the CAN1 RAM.
8710 *
8711 * Field Access Macros:
8712 *
8713 */
8714/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_INJD register field. */
8715#define ALT_SYSMGR_ECC_CAN1_INJD_LSB 2
8716/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_INJD register field. */
8717#define ALT_SYSMGR_ECC_CAN1_INJD_MSB 2
8718/* The width in bits of the ALT_SYSMGR_ECC_CAN1_INJD register field. */
8719#define ALT_SYSMGR_ECC_CAN1_INJD_WIDTH 1
8720/* The mask used to set the ALT_SYSMGR_ECC_CAN1_INJD register field value. */
8721#define ALT_SYSMGR_ECC_CAN1_INJD_SET_MSK 0x00000004
8722/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_INJD register field value. */
8723#define ALT_SYSMGR_ECC_CAN1_INJD_CLR_MSK 0xfffffffb
8724/* The reset value of the ALT_SYSMGR_ECC_CAN1_INJD register field. */
8725#define ALT_SYSMGR_ECC_CAN1_INJD_RESET 0x0
8726/* Extracts the ALT_SYSMGR_ECC_CAN1_INJD field value from a register. */
8727#define ALT_SYSMGR_ECC_CAN1_INJD_GET(value) (((value) & 0x00000004) >> 2)
8728/* Produces a ALT_SYSMGR_ECC_CAN1_INJD register field value suitable for setting the register. */
8729#define ALT_SYSMGR_ECC_CAN1_INJD_SET(value) (((value) << 2) & 0x00000004)
8730
8731/*
8732 * Field : CAN1 RAM ECC single, correctable error interrupt status - serr
8733 *
8734 * This bit is an interrupt status bit for CAN1 RAM ECC single, correctable error.
8735 * It is set by hardware when single, correctable error occurs in CAN1 RAM.
8736 * Software needs to write 1 into this bit to clear the interrupt status.
8737 *
8738 * Field Access Macros:
8739 *
8740 */
8741/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_SERR register field. */
8742#define ALT_SYSMGR_ECC_CAN1_SERR_LSB 3
8743/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_SERR register field. */
8744#define ALT_SYSMGR_ECC_CAN1_SERR_MSB 3
8745/* The width in bits of the ALT_SYSMGR_ECC_CAN1_SERR register field. */
8746#define ALT_SYSMGR_ECC_CAN1_SERR_WIDTH 1
8747/* The mask used to set the ALT_SYSMGR_ECC_CAN1_SERR register field value. */
8748#define ALT_SYSMGR_ECC_CAN1_SERR_SET_MSK 0x00000008
8749/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_SERR register field value. */
8750#define ALT_SYSMGR_ECC_CAN1_SERR_CLR_MSK 0xfffffff7
8751/* The reset value of the ALT_SYSMGR_ECC_CAN1_SERR register field. */
8752#define ALT_SYSMGR_ECC_CAN1_SERR_RESET 0x0
8753/* Extracts the ALT_SYSMGR_ECC_CAN1_SERR field value from a register. */
8754#define ALT_SYSMGR_ECC_CAN1_SERR_GET(value) (((value) & 0x00000008) >> 3)
8755/* Produces a ALT_SYSMGR_ECC_CAN1_SERR register field value suitable for setting the register. */
8756#define ALT_SYSMGR_ECC_CAN1_SERR_SET(value) (((value) << 3) & 0x00000008)
8757
8758/*
8759 * Field : CAN1 RAM ECC double bit, non-correctable error interrupt status - derr
8760 *
8761 * This bit is an interrupt status bit for CAN1 RAM ECC double bit, non-correctable
8762 * error. It is set by hardware when double bit, non-correctable error occurs in
8763 * CAN1 RAM. Software needs to write 1 into this bit to clear the interrupt status.
8764 *
8765 * Field Access Macros:
8766 *
8767 */
8768/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_DERR register field. */
8769#define ALT_SYSMGR_ECC_CAN1_DERR_LSB 4
8770/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_DERR register field. */
8771#define ALT_SYSMGR_ECC_CAN1_DERR_MSB 4
8772/* The width in bits of the ALT_SYSMGR_ECC_CAN1_DERR register field. */
8773#define ALT_SYSMGR_ECC_CAN1_DERR_WIDTH 1
8774/* The mask used to set the ALT_SYSMGR_ECC_CAN1_DERR register field value. */
8775#define ALT_SYSMGR_ECC_CAN1_DERR_SET_MSK 0x00000010
8776/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_DERR register field value. */
8777#define ALT_SYSMGR_ECC_CAN1_DERR_CLR_MSK 0xffffffef
8778/* The reset value of the ALT_SYSMGR_ECC_CAN1_DERR register field. */
8779#define ALT_SYSMGR_ECC_CAN1_DERR_RESET 0x0
8780/* Extracts the ALT_SYSMGR_ECC_CAN1_DERR field value from a register. */
8781#define ALT_SYSMGR_ECC_CAN1_DERR_GET(value) (((value) & 0x00000010) >> 4)
8782/* Produces a ALT_SYSMGR_ECC_CAN1_DERR register field value suitable for setting the register. */
8783#define ALT_SYSMGR_ECC_CAN1_DERR_SET(value) (((value) << 4) & 0x00000010)
8784
8785#ifndef __ASSEMBLY__
8786/*
8787 * WARNING: The C register and register group struct declarations are provided for
8788 * convenience and illustrative purposes. They should, however, be used with
8789 * caution as the C language standard provides no guarantees about the alignment or
8790 * atomicity of device memory accesses. The recommended practice for writing
8791 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8792 * alt_write_word() functions.
8793 *
8794 * The struct declaration for register ALT_SYSMGR_ECC_CAN1.
8795 */
8796 struct ALT_SYSMGR_ECC_CAN1_s
8797{
8798 uint32_t en : 1; /* CAN1 RAM ECC Enable */
8799 uint32_t injs : 1; /* CAN1 RAM ECC inject single, correctable Error */
8800 uint32_t injd : 1; /* CAN1 RAM ECC inject double bit, non-correctable error */
8801 uint32_t serr : 1; /* CAN1 RAM ECC single, correctable error interrupt status */
8802 uint32_t derr : 1; /* CAN1 RAM ECC double bit, non-correctable error interrupt status */
8803 uint32_t : 27; /* *UNDEFINED* */
8804};
8805
8806/* The typedef declaration for register ALT_SYSMGR_ECC_CAN1. */
8807typedef volatile struct ALT_SYSMGR_ECC_CAN1_s ALT_SYSMGR_ECC_CAN1_t;
8808#endif /* __ASSEMBLY__ */
8809
8810/* The byte offset of the ALT_SYSMGR_ECC_CAN1 register from the beginning of the component. */
8811#define ALT_SYSMGR_ECC_CAN1_OFST 0x20
8812
8813/*
8814 * Register : NAND RAM ECC Enable Register - nand
8815 *
8816 * This register is used to enable ECC on the NAND RAM. ECC errors can be injected
8817 * into the write path using bits in this register. This register contains
8818 * interrupt status of the ECC single/double bit error.
8819 *
8820 * Only reset by a cold reset (ignores warm reset).
8821 *
8822 * Register Layout
8823 *
8824 * Bits | Access | Reset | Description
8825 * :--------|:-------|:------|:--------------------------------------------------------------------------
8826 * [0] | RW | 0x0 | NAND RAM ECC Enable
8827 * [1] | RW | 0x0 | NAND ECCBUFFER RAM ECC inject single, correctable Error
8828 * [2] | RW | 0x0 | NAND ECCBUFFER RAM ECC inject double bit, non-correctable error
8829 * [3] | RW | 0x0 | NAND WRFIFO RAM ECC inject single, correctable Error
8830 * [4] | RW | 0x0 | NAND WRFIFO RAM ECC inject double bit, non-correctable error
8831 * [5] | RW | 0x0 | NAND RDFIFO RAM ECC inject single, correctable Error
8832 * [6] | RW | 0x0 | NAND RDFIFO RAM ECC inject double bit, non-correctable error
8833 * [7] | RW | 0x0 | NAND ECCBUFFER RAM ECC single, correctable error interrupt status
8834 * [8] | RW | 0x0 | NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status
8835 * [9] | RW | 0x0 | NAND WRFIFO RAM ECC single, correctable error interrupt status
8836 * [10] | RW | 0x0 | NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status
8837 * [11] | RW | 0x0 | NAND RDFIFO RAM ECC single, correctable error interrupt status
8838 * [12] | RW | 0x0 | NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status
8839 * [31:13] | ??? | 0x0 | *UNDEFINED*
8840 *
8841 */
8842/*
8843 * Field : NAND RAM ECC Enable - en
8844 *
8845 * Enable ECC for NAND RAM
8846 *
8847 * Field Access Macros:
8848 *
8849 */
8850/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_EN register field. */
8851#define ALT_SYSMGR_ECC_NAND_EN_LSB 0
8852/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_EN register field. */
8853#define ALT_SYSMGR_ECC_NAND_EN_MSB 0
8854/* The width in bits of the ALT_SYSMGR_ECC_NAND_EN register field. */
8855#define ALT_SYSMGR_ECC_NAND_EN_WIDTH 1
8856/* The mask used to set the ALT_SYSMGR_ECC_NAND_EN register field value. */
8857#define ALT_SYSMGR_ECC_NAND_EN_SET_MSK 0x00000001
8858/* The mask used to clear the ALT_SYSMGR_ECC_NAND_EN register field value. */
8859#define ALT_SYSMGR_ECC_NAND_EN_CLR_MSK 0xfffffffe
8860/* The reset value of the ALT_SYSMGR_ECC_NAND_EN register field. */
8861#define ALT_SYSMGR_ECC_NAND_EN_RESET 0x0
8862/* Extracts the ALT_SYSMGR_ECC_NAND_EN field value from a register. */
8863#define ALT_SYSMGR_ECC_NAND_EN_GET(value) (((value) & 0x00000001) >> 0)
8864/* Produces a ALT_SYSMGR_ECC_NAND_EN register field value suitable for setting the register. */
8865#define ALT_SYSMGR_ECC_NAND_EN_SET(value) (((value) << 0) & 0x00000001)
8866
8867/*
8868 * Field : NAND ECCBUFFER RAM ECC inject single, correctable Error - eccbufinjs
8869 *
8870 * Changing this bit from zero to one injects a single, correctable error into the
8871 * NAND ECCBUFFER RAM. This only injects one error into the NAND ECCBUFFER RAM.
8872 *
8873 * Field Access Macros:
8874 *
8875 */
8876/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */
8877#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_LSB 1
8878/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */
8879#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_MSB 1
8880/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */
8881#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_WIDTH 1
8882/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value. */
8883#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET_MSK 0x00000002
8884/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value. */
8885#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_CLR_MSK 0xfffffffd
8886/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */
8887#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_RESET 0x0
8888/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFINJS field value from a register. */
8889#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_GET(value) (((value) & 0x00000002) >> 1)
8890/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value suitable for setting the register. */
8891#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET(value) (((value) << 1) & 0x00000002)
8892
8893/*
8894 * Field : NAND ECCBUFFER RAM ECC inject double bit, non-correctable error - eccbufinjd
8895 *
8896 * Changing this bit from zero to one injects a double, non-correctable error into
8897 * the NAND ECCBUFFER RAM. This only injects one double bit error into the NAND
8898 * ECCBUFFER RAM.
8899 *
8900 * Field Access Macros:
8901 *
8902 */
8903/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */
8904#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_LSB 2
8905/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */
8906#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_MSB 2
8907/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */
8908#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_WIDTH 1
8909/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value. */
8910#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET_MSK 0x00000004
8911/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value. */
8912#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_CLR_MSK 0xfffffffb
8913/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */
8914#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_RESET 0x0
8915/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFINJD field value from a register. */
8916#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_GET(value) (((value) & 0x00000004) >> 2)
8917/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value suitable for setting the register. */
8918#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET(value) (((value) << 2) & 0x00000004)
8919
8920/*
8921 * Field : NAND WRFIFO RAM ECC inject single, correctable Error - wrfifoinjs
8922 *
8923 * Changing this bit from zero to one injects a single, correctable error into the
8924 * NAND WRFIFO RAM. This only injects one error into the NAND WRFIFO RAM.
8925 *
8926 * Field Access Macros:
8927 *
8928 */
8929/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */
8930#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_LSB 3
8931/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */
8932#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_MSB 3
8933/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */
8934#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_WIDTH 1
8935/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value. */
8936#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET_MSK 0x00000008
8937/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value. */
8938#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_CLR_MSK 0xfffffff7
8939/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */
8940#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_RESET 0x0
8941/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOINJS field value from a register. */
8942#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_GET(value) (((value) & 0x00000008) >> 3)
8943/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value suitable for setting the register. */
8944#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET(value) (((value) << 3) & 0x00000008)
8945
8946/*
8947 * Field : NAND WRFIFO RAM ECC inject double bit, non-correctable error - wrfifoinjd
8948 *
8949 * Changing this bit from zero to one injects a double, non-correctable error into
8950 * the NAND WRFIFO RAM. This only injects one double bit error into the NAND WRFIFO
8951 * RAM.
8952 *
8953 * Field Access Macros:
8954 *
8955 */
8956/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */
8957#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_LSB 4
8958/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */
8959#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_MSB 4
8960/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */
8961#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_WIDTH 1
8962/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value. */
8963#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET_MSK 0x00000010
8964/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value. */
8965#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_CLR_MSK 0xffffffef
8966/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */
8967#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_RESET 0x0
8968/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOINJD field value from a register. */
8969#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_GET(value) (((value) & 0x00000010) >> 4)
8970/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value suitable for setting the register. */
8971#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET(value) (((value) << 4) & 0x00000010)
8972
8973/*
8974 * Field : NAND RDFIFO RAM ECC inject single, correctable Error - rdfifoinjs
8975 *
8976 * Changing this bit from zero to one injects a single, correctable error into the
8977 * NAND RDFIFO RAM. This only injects one error into the NAND RDFIFO RAM.
8978 *
8979 * Field Access Macros:
8980 *
8981 */
8982/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */
8983#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_LSB 5
8984/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */
8985#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_MSB 5
8986/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */
8987#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_WIDTH 1
8988/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value. */
8989#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET_MSK 0x00000020
8990/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value. */
8991#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_CLR_MSK 0xffffffdf
8992/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */
8993#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_RESET 0x0
8994/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOINJS field value from a register. */
8995#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_GET(value) (((value) & 0x00000020) >> 5)
8996/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value suitable for setting the register. */
8997#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET(value) (((value) << 5) & 0x00000020)
8998
8999/*
9000 * Field : NAND RDFIFO RAM ECC inject double bit, non-correctable error - rdfifoinjd
9001 *
9002 * Changing this bit from zero to one injects a double, non-correctable error into
9003 * the NAND RDFIFO RAM. This only injects one double bit error into the NAND RDFIFO
9004 * RAM.
9005 *
9006 * Field Access Macros:
9007 *
9008 */
9009/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */
9010#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_LSB 6
9011/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */
9012#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_MSB 6
9013/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */
9014#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_WIDTH 1
9015/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value. */
9016#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET_MSK 0x00000040
9017/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value. */
9018#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_CLR_MSK 0xffffffbf
9019/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */
9020#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_RESET 0x0
9021/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOINJD field value from a register. */
9022#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_GET(value) (((value) & 0x00000040) >> 6)
9023/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value suitable for setting the register. */
9024#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET(value) (((value) << 6) & 0x00000040)
9025
9026/*
9027 * Field : NAND ECCBUFFER RAM ECC single, correctable error interrupt status - eccbufserr
9028 *
9029 * This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC single,
9030 * correctable error. It is set by hardware when single, correctable error occurs
9031 * in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear the
9032 * interrupt status.
9033 *
9034 * Field Access Macros:
9035 *
9036 */
9037/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */
9038#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_LSB 7
9039/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */
9040#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_MSB 7
9041/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */
9042#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_WIDTH 1
9043/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value. */
9044#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK 0x00000080
9045/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value. */
9046#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_CLR_MSK 0xffffff7f
9047/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */
9048#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_RESET 0x0
9049/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFSERR field value from a register. */
9050#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_GET(value) (((value) & 0x00000080) >> 7)
9051/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value suitable for setting the register. */
9052#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET(value) (((value) << 7) & 0x00000080)
9053
9054/*
9055 * Field : NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status - eccbufderr
9056 *
9057 * This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC double bit, non-
9058 * correctable error. It is set by hardware when double bit, non-correctable error
9059 * occurs in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear
9060 * the interrupt status.
9061 *
9062 * Field Access Macros:
9063 *
9064 */
9065/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */
9066#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_LSB 8
9067/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */
9068#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_MSB 8
9069/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */
9070#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_WIDTH 1
9071/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value. */
9072#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK 0x00000100
9073/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value. */
9074#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_CLR_MSK 0xfffffeff
9075/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */
9076#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_RESET 0x0
9077/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFDERR field value from a register. */
9078#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_GET(value) (((value) & 0x00000100) >> 8)
9079/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value suitable for setting the register. */
9080#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET(value) (((value) << 8) & 0x00000100)
9081
9082/*
9083 * Field : NAND WRFIFO RAM ECC single, correctable error interrupt status - wrfifoserr
9084 *
9085 * This bit is an interrupt status bit for NAND WRFIFO RAM ECC single, correctable
9086 * error. It is set by hardware when single, correctable error occurs in NAND
9087 * WRFIFO RAM. Software needs to write 1 into this bit to clear the interrupt
9088 * status.
9089 *
9090 * Field Access Macros:
9091 *
9092 */
9093/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */
9094#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_LSB 9
9095/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */
9096#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_MSB 9
9097/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */
9098#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_WIDTH 1
9099/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value. */
9100#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK 0x00000200
9101/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value. */
9102#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_CLR_MSK 0xfffffdff
9103/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */
9104#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_RESET 0x0
9105/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOSERR field value from a register. */
9106#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_GET(value) (((value) & 0x00000200) >> 9)
9107/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value suitable for setting the register. */
9108#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET(value) (((value) << 9) & 0x00000200)
9109
9110/*
9111 * Field : NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status - wrfifoderr
9112 *
9113 * This bit is an interrupt status bit for NAND WRFIFO RAM ECC double bit, non-
9114 * correctable error. It is set by hardware when double bit, non-correctable error
9115 * occurs in NAND WRFIFO RAM. Software needs to write 1 into this bit to clear the
9116 * interrupt status.
9117 *
9118 * Field Access Macros:
9119 *
9120 */
9121/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */
9122#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_LSB 10
9123/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */
9124#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_MSB 10
9125/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */
9126#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_WIDTH 1
9127/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value. */
9128#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK 0x00000400
9129/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value. */
9130#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_CLR_MSK 0xfffffbff
9131/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */
9132#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_RESET 0x0
9133/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFODERR field value from a register. */
9134#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_GET(value) (((value) & 0x00000400) >> 10)
9135/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value suitable for setting the register. */
9136#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET(value) (((value) << 10) & 0x00000400)
9137
9138/*
9139 * Field : NAND RDFIFO RAM ECC single, correctable error interrupt status - rdfifoserr
9140 *
9141 * This bit is an interrupt status bit for NAND RDFIFO RAM ECC single, correctable
9142 * error. It is set by hardware when single, correctable error occurs in NAND
9143 * RDFIFO RAM. Software needs to write 1 into this bit to clear the interrupt
9144 * status.
9145 *
9146 * Field Access Macros:
9147 *
9148 */
9149/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */
9150#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_LSB 11
9151/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */
9152#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_MSB 11
9153/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */
9154#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_WIDTH 1
9155/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value. */
9156#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK 0x00000800
9157/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value. */
9158#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_CLR_MSK 0xfffff7ff
9159/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */
9160#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_RESET 0x0
9161/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOSERR field value from a register. */
9162#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_GET(value) (((value) & 0x00000800) >> 11)
9163/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value suitable for setting the register. */
9164#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET(value) (((value) << 11) & 0x00000800)
9165
9166/*
9167 * Field : NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status - rdfifoderr
9168 *
9169 * This bit is an interrupt status bit for NAND RDFIFO RAM ECC double bit, non-
9170 * correctable error. It is set by hardware when double bit, non-correctable error
9171 * occurs in NAND RDFIFO RAM. Software needs to write 1 into this bit to clear the
9172 * interrupt status.
9173 *
9174 * Field Access Macros:
9175 *
9176 */
9177/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */
9178#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_LSB 12
9179/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */
9180#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_MSB 12
9181/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */
9182#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_WIDTH 1
9183/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value. */
9184#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK 0x00001000
9185/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value. */
9186#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_CLR_MSK 0xffffefff
9187/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */
9188#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_RESET 0x0
9189/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFODERR field value from a register. */
9190#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_GET(value) (((value) & 0x00001000) >> 12)
9191/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value suitable for setting the register. */
9192#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET(value) (((value) << 12) & 0x00001000)
9193
9194#ifndef __ASSEMBLY__
9195/*
9196 * WARNING: The C register and register group struct declarations are provided for
9197 * convenience and illustrative purposes. They should, however, be used with
9198 * caution as the C language standard provides no guarantees about the alignment or
9199 * atomicity of device memory accesses. The recommended practice for writing
9200 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9201 * alt_write_word() functions.
9202 *
9203 * The struct declaration for register ALT_SYSMGR_ECC_NAND.
9204 */
9205 struct ALT_SYSMGR_ECC_NAND_s
9206{
9207 uint32_t en : 1; /* NAND RAM ECC Enable */
9208 uint32_t eccbufinjs : 1; /* NAND ECCBUFFER RAM ECC inject single, correctable Error */
9209 uint32_t eccbufinjd : 1; /* NAND ECCBUFFER RAM ECC inject double bit, non-correctable error */
9210 uint32_t wrfifoinjs : 1; /* NAND WRFIFO RAM ECC inject single, correctable Error */
9211 uint32_t wrfifoinjd : 1; /* NAND WRFIFO RAM ECC inject double bit, non-correctable error */
9212 uint32_t rdfifoinjs : 1; /* NAND RDFIFO RAM ECC inject single, correctable Error */
9213 uint32_t rdfifoinjd : 1; /* NAND RDFIFO RAM ECC inject double bit, non-correctable error */
9214 uint32_t eccbufserr : 1; /* NAND ECCBUFFER RAM ECC single, correctable error interrupt status */
9215 uint32_t eccbufderr : 1; /* NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status */
9216 uint32_t wrfifoserr : 1; /* NAND WRFIFO RAM ECC single, correctable error interrupt status */
9217 uint32_t wrfifoderr : 1; /* NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status */
9218 uint32_t rdfifoserr : 1; /* NAND RDFIFO RAM ECC single, correctable error interrupt status */
9219 uint32_t rdfifoderr : 1; /* NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status */
9220 uint32_t : 19; /* *UNDEFINED* */
9221};
9222
9223/* The typedef declaration for register ALT_SYSMGR_ECC_NAND. */
9224typedef volatile struct ALT_SYSMGR_ECC_NAND_s ALT_SYSMGR_ECC_NAND_t;
9225#endif /* __ASSEMBLY__ */
9226
9227/* The byte offset of the ALT_SYSMGR_ECC_NAND register from the beginning of the component. */
9228#define ALT_SYSMGR_ECC_NAND_OFST 0x24
9229
9230/*
9231 * Register : QSPI RAM ECC Enable Register - qspi
9232 *
9233 * This register is used to enable ECC on the QSPI RAM. ECC errors can be injected
9234 * into the write path using bits in this register. This register contains
9235 * interrupt status of the ECC single/double bit error.
9236 *
9237 * Only reset by a cold reset (ignores warm reset).
9238 *
9239 * Register Layout
9240 *
9241 * Bits | Access | Reset | Description
9242 * :-------|:-------|:------|:----------------------------------------------------------------
9243 * [0] | RW | 0x0 | QSPI RAM ECC Enable
9244 * [1] | RW | 0x0 | QSPI RAM ECC inject single, correctable Error
9245 * [2] | RW | 0x0 | QSPI RAM ECC inject double bit, non-correctable error
9246 * [3] | RW | 0x0 | QSPI RAM ECC single, correctable error interrupt status
9247 * [4] | RW | 0x0 | QSPI RAM ECC double bit, non-correctable error interrupt status
9248 * [31:5] | ??? | 0x0 | *UNDEFINED*
9249 *
9250 */
9251/*
9252 * Field : QSPI RAM ECC Enable - en
9253 *
9254 * Enable ECC for QSPI RAM
9255 *
9256 * Field Access Macros:
9257 *
9258 */
9259/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_EN register field. */
9260#define ALT_SYSMGR_ECC_QSPI_EN_LSB 0
9261/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_EN register field. */
9262#define ALT_SYSMGR_ECC_QSPI_EN_MSB 0
9263/* The width in bits of the ALT_SYSMGR_ECC_QSPI_EN register field. */
9264#define ALT_SYSMGR_ECC_QSPI_EN_WIDTH 1
9265/* The mask used to set the ALT_SYSMGR_ECC_QSPI_EN register field value. */
9266#define ALT_SYSMGR_ECC_QSPI_EN_SET_MSK 0x00000001
9267/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_EN register field value. */
9268#define ALT_SYSMGR_ECC_QSPI_EN_CLR_MSK 0xfffffffe
9269/* The reset value of the ALT_SYSMGR_ECC_QSPI_EN register field. */
9270#define ALT_SYSMGR_ECC_QSPI_EN_RESET 0x0
9271/* Extracts the ALT_SYSMGR_ECC_QSPI_EN field value from a register. */
9272#define ALT_SYSMGR_ECC_QSPI_EN_GET(value) (((value) & 0x00000001) >> 0)
9273/* Produces a ALT_SYSMGR_ECC_QSPI_EN register field value suitable for setting the register. */
9274#define ALT_SYSMGR_ECC_QSPI_EN_SET(value) (((value) << 0) & 0x00000001)
9275
9276/*
9277 * Field : QSPI RAM ECC inject single, correctable Error - injs
9278 *
9279 * Changing this bit from zero to one injects a single, correctable error into the
9280 * QSPI RAM. This only injects one error into the QSPI RAM.
9281 *
9282 * Field Access Macros:
9283 *
9284 */
9285/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_INJS register field. */
9286#define ALT_SYSMGR_ECC_QSPI_INJS_LSB 1
9287/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_INJS register field. */
9288#define ALT_SYSMGR_ECC_QSPI_INJS_MSB 1
9289/* The width in bits of the ALT_SYSMGR_ECC_QSPI_INJS register field. */
9290#define ALT_SYSMGR_ECC_QSPI_INJS_WIDTH 1
9291/* The mask used to set the ALT_SYSMGR_ECC_QSPI_INJS register field value. */
9292#define ALT_SYSMGR_ECC_QSPI_INJS_SET_MSK 0x00000002
9293/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_INJS register field value. */
9294#define ALT_SYSMGR_ECC_QSPI_INJS_CLR_MSK 0xfffffffd
9295/* The reset value of the ALT_SYSMGR_ECC_QSPI_INJS register field. */
9296#define ALT_SYSMGR_ECC_QSPI_INJS_RESET 0x0
9297/* Extracts the ALT_SYSMGR_ECC_QSPI_INJS field value from a register. */
9298#define ALT_SYSMGR_ECC_QSPI_INJS_GET(value) (((value) & 0x00000002) >> 1)
9299/* Produces a ALT_SYSMGR_ECC_QSPI_INJS register field value suitable for setting the register. */
9300#define ALT_SYSMGR_ECC_QSPI_INJS_SET(value) (((value) << 1) & 0x00000002)
9301
9302/*
9303 * Field : QSPI RAM ECC inject double bit, non-correctable error - injd
9304 *
9305 * Changing this bit from zero to one injects a double, non-correctable error into
9306 * the QSPI RAM. This only injects one double bit error into the QSPI RAM.
9307 *
9308 * Field Access Macros:
9309 *
9310 */
9311/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_INJD register field. */
9312#define ALT_SYSMGR_ECC_QSPI_INJD_LSB 2
9313/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_INJD register field. */
9314#define ALT_SYSMGR_ECC_QSPI_INJD_MSB 2
9315/* The width in bits of the ALT_SYSMGR_ECC_QSPI_INJD register field. */
9316#define ALT_SYSMGR_ECC_QSPI_INJD_WIDTH 1
9317/* The mask used to set the ALT_SYSMGR_ECC_QSPI_INJD register field value. */
9318#define ALT_SYSMGR_ECC_QSPI_INJD_SET_MSK 0x00000004
9319/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_INJD register field value. */
9320#define ALT_SYSMGR_ECC_QSPI_INJD_CLR_MSK 0xfffffffb
9321/* The reset value of the ALT_SYSMGR_ECC_QSPI_INJD register field. */
9322#define ALT_SYSMGR_ECC_QSPI_INJD_RESET 0x0
9323/* Extracts the ALT_SYSMGR_ECC_QSPI_INJD field value from a register. */
9324#define ALT_SYSMGR_ECC_QSPI_INJD_GET(value) (((value) & 0x00000004) >> 2)
9325/* Produces a ALT_SYSMGR_ECC_QSPI_INJD register field value suitable for setting the register. */
9326#define ALT_SYSMGR_ECC_QSPI_INJD_SET(value) (((value) << 2) & 0x00000004)
9327
9328/*
9329 * Field : QSPI RAM ECC single, correctable error interrupt status - serr
9330 *
9331 * This bit is an interrupt status bit for QSPI RAM ECC single, correctable error.
9332 * It is set by hardware when single, correctable error occurs in QSPI RAM.
9333 * Software needs to write 1 into this bit to clear the interrupt status.
9334 *
9335 * Field Access Macros:
9336 *
9337 */
9338/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_SERR register field. */
9339#define ALT_SYSMGR_ECC_QSPI_SERR_LSB 3
9340/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_SERR register field. */
9341#define ALT_SYSMGR_ECC_QSPI_SERR_MSB 3
9342/* The width in bits of the ALT_SYSMGR_ECC_QSPI_SERR register field. */
9343#define ALT_SYSMGR_ECC_QSPI_SERR_WIDTH 1
9344/* The mask used to set the ALT_SYSMGR_ECC_QSPI_SERR register field value. */
9345#define ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK 0x00000008
9346/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_SERR register field value. */
9347#define ALT_SYSMGR_ECC_QSPI_SERR_CLR_MSK 0xfffffff7
9348/* The reset value of the ALT_SYSMGR_ECC_QSPI_SERR register field. */
9349#define ALT_SYSMGR_ECC_QSPI_SERR_RESET 0x0
9350/* Extracts the ALT_SYSMGR_ECC_QSPI_SERR field value from a register. */
9351#define ALT_SYSMGR_ECC_QSPI_SERR_GET(value) (((value) & 0x00000008) >> 3)
9352/* Produces a ALT_SYSMGR_ECC_QSPI_SERR register field value suitable for setting the register. */
9353#define ALT_SYSMGR_ECC_QSPI_SERR_SET(value) (((value) << 3) & 0x00000008)
9354
9355/*
9356 * Field : QSPI RAM ECC double bit, non-correctable error interrupt status - derr
9357 *
9358 * This bit is an interrupt status bit for QSPI RAM ECC double bit, non-correctable
9359 * error. It is set by hardware when double bit, non-correctable error occurs in
9360 * QSPI RAM. Software needs to write 1 into this bit to clear the interrupt status.
9361 *
9362 * Field Access Macros:
9363 *
9364 */
9365/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_DERR register field. */
9366#define ALT_SYSMGR_ECC_QSPI_DERR_LSB 4
9367/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_DERR register field. */
9368#define ALT_SYSMGR_ECC_QSPI_DERR_MSB 4
9369/* The width in bits of the ALT_SYSMGR_ECC_QSPI_DERR register field. */
9370#define ALT_SYSMGR_ECC_QSPI_DERR_WIDTH 1
9371/* The mask used to set the ALT_SYSMGR_ECC_QSPI_DERR register field value. */
9372#define ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK 0x00000010
9373/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_DERR register field value. */
9374#define ALT_SYSMGR_ECC_QSPI_DERR_CLR_MSK 0xffffffef
9375/* The reset value of the ALT_SYSMGR_ECC_QSPI_DERR register field. */
9376#define ALT_SYSMGR_ECC_QSPI_DERR_RESET 0x0
9377/* Extracts the ALT_SYSMGR_ECC_QSPI_DERR field value from a register. */
9378#define ALT_SYSMGR_ECC_QSPI_DERR_GET(value) (((value) & 0x00000010) >> 4)
9379/* Produces a ALT_SYSMGR_ECC_QSPI_DERR register field value suitable for setting the register. */
9380#define ALT_SYSMGR_ECC_QSPI_DERR_SET(value) (((value) << 4) & 0x00000010)
9381
9382#ifndef __ASSEMBLY__
9383/*
9384 * WARNING: The C register and register group struct declarations are provided for
9385 * convenience and illustrative purposes. They should, however, be used with
9386 * caution as the C language standard provides no guarantees about the alignment or
9387 * atomicity of device memory accesses. The recommended practice for writing
9388 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9389 * alt_write_word() functions.
9390 *
9391 * The struct declaration for register ALT_SYSMGR_ECC_QSPI.
9392 */
9393 struct ALT_SYSMGR_ECC_QSPI_s
9394{
9395 uint32_t en : 1; /* QSPI RAM ECC Enable */
9396 uint32_t injs : 1; /* QSPI RAM ECC inject single, correctable Error */
9397 uint32_t injd : 1; /* QSPI RAM ECC inject double bit, non-correctable error */
9398 uint32_t serr : 1; /* QSPI RAM ECC single, correctable error interrupt status */
9399 uint32_t derr : 1; /* QSPI RAM ECC double bit, non-correctable error interrupt status */
9400 uint32_t : 27; /* *UNDEFINED* */
9401};
9402
9403/* The typedef declaration for register ALT_SYSMGR_ECC_QSPI. */
9404typedef volatile struct ALT_SYSMGR_ECC_QSPI_s ALT_SYSMGR_ECC_QSPI_t;
9405#endif /* __ASSEMBLY__ */
9406
9407/* The byte offset of the ALT_SYSMGR_ECC_QSPI register from the beginning of the component. */
9408#define ALT_SYSMGR_ECC_QSPI_OFST 0x28
9409
9410/*
9411 * Register : SDMMC RAM ECC Enable Register - sdmmc
9412 *
9413 * This register is used to enable ECC on the SDMMC RAM.ECC errors can be injected
9414 * into the write path using bits in this register.
9415 *
9416 * Only reset by a cold reset (ignores warm reset).
9417 *
9418 * Register Layout
9419 *
9420 * Bits | Access | Reset | Description
9421 * :-------|:-------|:------|:------------------------------------------------------------------------
9422 * [0] | RW | 0x0 | SDMMC RAM ECC Enable
9423 * [1] | RW | 0x0 | SDMMC Port A RAM ECC inject single, correctable Error at Port A
9424 * [2] | RW | 0x0 | SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A
9425 * [3] | RW | 0x0 | SDMMC Port B RAM ECC inject single, correctable Error at Port B
9426 * [4] | RW | 0x0 | SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B
9427 * [5] | RW | 0x0 | SDMMC Port A RAM ECC single, correctable error interrupt status
9428 * [6] | RW | 0x0 | SDMMC Port A RAM ECC double bit, non-correctable error interrupt status
9429 * [7] | RW | 0x0 | SDMMC Port B RAM ECC single, correctable error interrupt status
9430 * [8] | RW | 0x0 | SDMMC Port B RAM ECC double bit, non-correctable error interrupt status
9431 * [31:9] | ??? | 0x0 | *UNDEFINED*
9432 *
9433 */
9434/*
9435 * Field : SDMMC RAM ECC Enable - en
9436 *
9437 * Enable ECC for SDMMC RAM
9438 *
9439 * Field Access Macros:
9440 *
9441 */
9442/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_EN register field. */
9443#define ALT_SYSMGR_ECC_SDMMC_EN_LSB 0
9444/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_EN register field. */
9445#define ALT_SYSMGR_ECC_SDMMC_EN_MSB 0
9446/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_EN register field. */
9447#define ALT_SYSMGR_ECC_SDMMC_EN_WIDTH 1
9448/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_EN register field value. */
9449#define ALT_SYSMGR_ECC_SDMMC_EN_SET_MSK 0x00000001
9450/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_EN register field value. */
9451#define ALT_SYSMGR_ECC_SDMMC_EN_CLR_MSK 0xfffffffe
9452/* The reset value of the ALT_SYSMGR_ECC_SDMMC_EN register field. */
9453#define ALT_SYSMGR_ECC_SDMMC_EN_RESET 0x0
9454/* Extracts the ALT_SYSMGR_ECC_SDMMC_EN field value from a register. */
9455#define ALT_SYSMGR_ECC_SDMMC_EN_GET(value) (((value) & 0x00000001) >> 0)
9456/* Produces a ALT_SYSMGR_ECC_SDMMC_EN register field value suitable for setting the register. */
9457#define ALT_SYSMGR_ECC_SDMMC_EN_SET(value) (((value) << 0) & 0x00000001)
9458
9459/*
9460 * Field : SDMMC Port A RAM ECC inject single, correctable Error at Port A - injsporta
9461 *
9462 * Changing this bit from zero to one injects a single, correctable error into the
9463 * SDMMC RAM at Port A. This only injects one error into the SDMMC RAM at Port A.
9464 *
9465 * Field Access Macros:
9466 *
9467 */
9468/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */
9469#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_LSB 1
9470/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */
9471#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_MSB 1
9472/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */
9473#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_WIDTH 1
9474/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value. */
9475#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET_MSK 0x00000002
9476/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value. */
9477#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_CLR_MSK 0xfffffffd
9478/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */
9479#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_RESET 0x0
9480/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJSPORTA field value from a register. */
9481#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_GET(value) (((value) & 0x00000002) >> 1)
9482/* Produces a ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value suitable for setting the register. */
9483#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET(value) (((value) << 1) & 0x00000002)
9484
9485/*
9486 * Field : SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A - injdporta
9487 *
9488 * Changing this bit from zero to one injects a double, non-correctable error into
9489 * the SDMMC RAM at Port A. This only injects one double bit error into the SDMMC
9490 * RAM at Port A.
9491 *
9492 * Field Access Macros:
9493 *
9494 */
9495/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */
9496#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_LSB 2
9497/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */
9498#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_MSB 2
9499/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */
9500#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_WIDTH 1
9501/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value. */
9502#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET_MSK 0x00000004
9503/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value. */
9504#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_CLR_MSK 0xfffffffb
9505/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */
9506#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_RESET 0x0
9507/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJDPORTA field value from a register. */
9508#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_GET(value) (((value) & 0x00000004) >> 2)
9509/* Produces a ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value suitable for setting the register. */
9510#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET(value) (((value) << 2) & 0x00000004)
9511
9512/*
9513 * Field : SDMMC Port B RAM ECC inject single, correctable Error at Port B - injsportb
9514 *
9515 * Changing this bit from zero to one injects a single, correctable error into the
9516 * SDMMC RAM at Port B. This only injects one error into the SDMMC RAM at Port B.
9517 *
9518 * Field Access Macros:
9519 *
9520 */
9521/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */
9522#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_LSB 3
9523/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */
9524#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_MSB 3
9525/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */
9526#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_WIDTH 1
9527/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value. */
9528#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET_MSK 0x00000008
9529/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value. */
9530#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_CLR_MSK 0xfffffff7
9531/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */
9532#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_RESET 0x0
9533/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJSPORTB field value from a register. */
9534#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_GET(value) (((value) & 0x00000008) >> 3)
9535/* Produces a ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value suitable for setting the register. */
9536#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET(value) (((value) << 3) & 0x00000008)
9537
9538/*
9539 * Field : SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B - injdportb
9540 *
9541 * Changing this bit from zero to one injects a double, non-correctable error into
9542 * the SDMMC RAM at Port B. This only injects one double bit error into the SDMMC
9543 * RAM at Port B.
9544 *
9545 * Field Access Macros:
9546 *
9547 */
9548/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */
9549#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_LSB 4
9550/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */
9551#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_MSB 4
9552/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */
9553#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_WIDTH 1
9554/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value. */
9555#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET_MSK 0x00000010
9556/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value. */
9557#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_CLR_MSK 0xffffffef
9558/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */
9559#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_RESET 0x0
9560/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJDPORTB field value from a register. */
9561#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_GET(value) (((value) & 0x00000010) >> 4)
9562/* Produces a ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value suitable for setting the register. */
9563#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET(value) (((value) << 4) & 0x00000010)
9564
9565/*
9566 * Field : SDMMC Port A RAM ECC single, correctable error interrupt status - serrporta
9567 *
9568 * This bit is an interrupt status bit for SDMMC Port A RAM ECC single, correctable
9569 * error. It is set by hardware when single, correctable error occurs in SDMMC Port
9570 * A RAM. Software needs to write 1 into this bit to clear the interrupt status.
9571 *
9572 * Field Access Macros:
9573 *
9574 */
9575/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */
9576#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_LSB 5
9577/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */
9578#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_MSB 5
9579/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */
9580#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_WIDTH 1
9581/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value. */
9582#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET_MSK 0x00000020
9583/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value. */
9584#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_CLR_MSK 0xffffffdf
9585/* The reset value of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */
9586#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_RESET 0x0
9587/* Extracts the ALT_SYSMGR_ECC_SDMMC_SERRPORTA field value from a register. */
9588#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_GET(value) (((value) & 0x00000020) >> 5)
9589/* Produces a ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value suitable for setting the register. */
9590#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET(value) (((value) << 5) & 0x00000020)
9591
9592/*
9593 * Field : SDMMC Port A RAM ECC double bit, non-correctable error interrupt status - derrporta
9594 *
9595 * This bit is an interrupt status bit for SDMMC Port A RAM ECC double bit, non-
9596 * correctable error. It is set by hardware when double bit, non-correctable error
9597 * occurs in SDMMC Port A RAM. Software needs to write 1 into this bit to clear the
9598 * interrupt status.
9599 *
9600 * Field Access Macros:
9601 *
9602 */
9603/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */
9604#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_LSB 6
9605/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */
9606#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_MSB 6
9607/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */
9608#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_WIDTH 1
9609/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value. */
9610#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET_MSK 0x00000040
9611/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value. */
9612#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_CLR_MSK 0xffffffbf
9613/* The reset value of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */
9614#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_RESET 0x0
9615/* Extracts the ALT_SYSMGR_ECC_SDMMC_DERRPORTA field value from a register. */
9616#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_GET(value) (((value) & 0x00000040) >> 6)
9617/* Produces a ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value suitable for setting the register. */
9618#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET(value) (((value) << 6) & 0x00000040)
9619
9620/*
9621 * Field : SDMMC Port B RAM ECC single, correctable error interrupt status - serrportb
9622 *
9623 * This bit is an interrupt status bit for SDMMC Port B RAM ECC single, correctable
9624 * error. It is set by hardware when single, correctable error occurs in SDMMC Port
9625 * B RAM. Software needs to write 1 into this bit to clear the interrupt status.
9626 *
9627 * Field Access Macros:
9628 *
9629 */
9630/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */
9631#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_LSB 7
9632/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */
9633#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_MSB 7
9634/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */
9635#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_WIDTH 1
9636/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value. */
9637#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET_MSK 0x00000080
9638/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value. */
9639#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_CLR_MSK 0xffffff7f
9640/* The reset value of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */
9641#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_RESET 0x0
9642/* Extracts the ALT_SYSMGR_ECC_SDMMC_SERRPORTB field value from a register. */
9643#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_GET(value) (((value) & 0x00000080) >> 7)
9644/* Produces a ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value suitable for setting the register. */
9645#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET(value) (((value) << 7) & 0x00000080)
9646
9647/*
9648 * Field : SDMMC Port B RAM ECC double bit, non-correctable error interrupt status - derrportb
9649 *
9650 * This bit is an interrupt status bit for SDMMC Port B RAM ECC double bit, non-
9651 * correctable error. It is set by hardware when double bit, non-correctable error
9652 * occurs in SDMMC Port B RAM. Software needs to write 1 into this bit to clear the
9653 * interrupt status.
9654 *
9655 * Field Access Macros:
9656 *
9657 */
9658/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */
9659#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_LSB 8
9660/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */
9661#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_MSB 8
9662/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */
9663#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_WIDTH 1
9664/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value. */
9665#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET_MSK 0x00000100
9666/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value. */
9667#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_CLR_MSK 0xfffffeff
9668/* The reset value of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */
9669#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_RESET 0x0
9670/* Extracts the ALT_SYSMGR_ECC_SDMMC_DERRPORTB field value from a register. */
9671#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_GET(value) (((value) & 0x00000100) >> 8)
9672/* Produces a ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value suitable for setting the register. */
9673#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET(value) (((value) << 8) & 0x00000100)
9674
9675#ifndef __ASSEMBLY__
9676/*
9677 * WARNING: The C register and register group struct declarations are provided for
9678 * convenience and illustrative purposes. They should, however, be used with
9679 * caution as the C language standard provides no guarantees about the alignment or
9680 * atomicity of device memory accesses. The recommended practice for writing
9681 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9682 * alt_write_word() functions.
9683 *
9684 * The struct declaration for register ALT_SYSMGR_ECC_SDMMC.
9685 */
9686 struct ALT_SYSMGR_ECC_SDMMC_s
9687{
9688 uint32_t en : 1; /* SDMMC RAM ECC Enable */
9689 uint32_t injsporta : 1; /* SDMMC Port A RAM ECC inject single, correctable Error at Port A */
9690 uint32_t injdporta : 1; /* SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A */
9691 uint32_t injsportb : 1; /* SDMMC Port B RAM ECC inject single, correctable Error at Port B */
9692 uint32_t injdportb : 1; /* SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B */
9693 uint32_t serrporta : 1; /* SDMMC Port A RAM ECC single, correctable error interrupt status */
9694 uint32_t derrporta : 1; /* SDMMC Port A RAM ECC double bit, non-correctable error interrupt status */
9695 uint32_t serrportb : 1; /* SDMMC Port B RAM ECC single, correctable error interrupt status */
9696 uint32_t derrportb : 1; /* SDMMC Port B RAM ECC double bit, non-correctable error interrupt status */
9697 uint32_t : 23; /* *UNDEFINED* */
9698};
9699
9700/* The typedef declaration for register ALT_SYSMGR_ECC_SDMMC. */
9701typedef volatile struct ALT_SYSMGR_ECC_SDMMC_s ALT_SYSMGR_ECC_SDMMC_t;
9702#endif /* __ASSEMBLY__ */
9703
9704/* The byte offset of the ALT_SYSMGR_ECC_SDMMC register from the beginning of the component. */
9705#define ALT_SYSMGR_ECC_SDMMC_OFST 0x2c
9706
9707#ifndef __ASSEMBLY__
9708/*
9709 * WARNING: The C register and register group struct declarations are provided for
9710 * convenience and illustrative purposes. They should, however, be used with
9711 * caution as the C language standard provides no guarantees about the alignment or
9712 * atomicity of device memory accesses. The recommended practice for writing
9713 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9714 * alt_write_word() functions.
9715 *
9716 * The struct declaration for register group ALT_SYSMGR_ECC.
9717 */
9718 struct ALT_SYSMGR_ECC_s
9719{
9720 volatile ALT_SYSMGR_ECC_L2_t l2; /* ALT_SYSMGR_ECC_L2 */
9721 volatile ALT_SYSMGR_ECC_OCRAM_t ocram; /* ALT_SYSMGR_ECC_OCRAM */
9722 volatile ALT_SYSMGR_ECC_USB0_t usb0; /* ALT_SYSMGR_ECC_USB0 */
9723 volatile ALT_SYSMGR_ECC_USB1_t usb1; /* ALT_SYSMGR_ECC_USB1 */
9724 volatile ALT_SYSMGR_ECC_EMAC0_t emac0; /* ALT_SYSMGR_ECC_EMAC0 */
9725 volatile ALT_SYSMGR_ECC_EMAC1_t emac1; /* ALT_SYSMGR_ECC_EMAC1 */
9726 volatile ALT_SYSMGR_ECC_DMA_t dma; /* ALT_SYSMGR_ECC_DMA */
9727 volatile ALT_SYSMGR_ECC_CAN0_t can0; /* ALT_SYSMGR_ECC_CAN0 */
9728 volatile ALT_SYSMGR_ECC_CAN1_t can1; /* ALT_SYSMGR_ECC_CAN1 */
9729 volatile ALT_SYSMGR_ECC_NAND_t nand; /* ALT_SYSMGR_ECC_NAND */
9730 volatile ALT_SYSMGR_ECC_QSPI_t qspi; /* ALT_SYSMGR_ECC_QSPI */
9731 volatile ALT_SYSMGR_ECC_SDMMC_t sdmmc; /* ALT_SYSMGR_ECC_SDMMC */
9732 volatile uint32_t _pad_0x30_0x40[4]; /* *UNDEFINED* */
9733};
9734
9735/* The typedef declaration for register group ALT_SYSMGR_ECC. */
9736typedef volatile struct ALT_SYSMGR_ECC_s ALT_SYSMGR_ECC_t;
9737/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ECC. */
9738 struct ALT_SYSMGR_ECC_raw_s
9739{
9740 volatile uint32_t l2; /* ALT_SYSMGR_ECC_L2 */
9741 volatile uint32_t ocram; /* ALT_SYSMGR_ECC_OCRAM */
9742 volatile uint32_t usb0; /* ALT_SYSMGR_ECC_USB0 */
9743 volatile uint32_t usb1; /* ALT_SYSMGR_ECC_USB1 */
9744 volatile uint32_t emac0; /* ALT_SYSMGR_ECC_EMAC0 */
9745 volatile uint32_t emac1; /* ALT_SYSMGR_ECC_EMAC1 */
9746 volatile uint32_t dma; /* ALT_SYSMGR_ECC_DMA */
9747 volatile uint32_t can0; /* ALT_SYSMGR_ECC_CAN0 */
9748 volatile uint32_t can1; /* ALT_SYSMGR_ECC_CAN1 */
9749 volatile uint32_t nand; /* ALT_SYSMGR_ECC_NAND */
9750 volatile uint32_t qspi; /* ALT_SYSMGR_ECC_QSPI */
9751 volatile uint32_t sdmmc; /* ALT_SYSMGR_ECC_SDMMC */
9752 volatile uint32_t _pad_0x30_0x40[4]; /* *UNDEFINED* */
9753};
9754
9755/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ECC. */
9756typedef volatile struct ALT_SYSMGR_ECC_raw_s ALT_SYSMGR_ECC_raw_t;
9757#endif /* __ASSEMBLY__ */
9758
9759
9760/*
9761 * Register Group : Pin Mux Control Group - ALT_SYSMGR_PINMUX
9762 * Pin Mux Control Group
9763 *
9764 * Controls Pin Mux selections
9765 *
9766 * NOTE: These registers should not be modified after IO configuration.There is no
9767 * support for dynamically changing the Pin Mux selections.
9768 *
9769 */
9770/*
9771 * Register : emac0_tx_clk Mux Selection Register - EMACIO0
9772 *
9773 * This register is used to control the peripherals connected to emac0_tx_clk
9774 *
9775 * Only reset by a cold reset (ignores warm reset).
9776 *
9777 * NOTE: These registers should not be modified after IO configuration.There is no
9778 * support for dynamically changing the Pin Mux selections.
9779 *
9780 * Register Layout
9781 *
9782 * Bits | Access | Reset | Description
9783 * :-------|:-------|:------|:---------------------------------
9784 * [1:0] | RW | 0x0 | emac0_tx_clk Mux Selection Field
9785 * [31:2] | ??? | 0x0 | *UNDEFINED*
9786 *
9787 */
9788/*
9789 * Field : emac0_tx_clk Mux Selection Field - sel
9790 *
9791 * Select peripheral signals connected emac0_tx_clk.
9792 *
9793 * 0 : Pin is connected to GPIO/LoanIO number 0.
9794 *
9795 * 1 : Pin is connected to Peripheral signal not applicable.
9796 *
9797 * 2 : Pin is connected to Peripheral signal not applicable.
9798 *
9799 * 3 : Pin is connected to Peripheral signal RGMII0.TX_CLK.
9800 *
9801 * Field Access Macros:
9802 *
9803 */
9804/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */
9805#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_LSB 0
9806/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */
9807#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_MSB 1
9808/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */
9809#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_WIDTH 2
9810/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value. */
9811#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET_MSK 0x00000003
9812/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value. */
9813#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_CLR_MSK 0xfffffffc
9814/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */
9815#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_RESET 0x0
9816/* Extracts the ALT_SYSMGR_PINMUX_EMACIO0_SEL field value from a register. */
9817#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
9818/* Produces a ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value suitable for setting the register. */
9819#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET(value) (((value) << 0) & 0x00000003)
9820
9821#ifndef __ASSEMBLY__
9822/*
9823 * WARNING: The C register and register group struct declarations are provided for
9824 * convenience and illustrative purposes. They should, however, be used with
9825 * caution as the C language standard provides no guarantees about the alignment or
9826 * atomicity of device memory accesses. The recommended practice for writing
9827 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9828 * alt_write_word() functions.
9829 *
9830 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO0.
9831 */
9832 struct ALT_SYSMGR_PINMUX_EMACIO0_s
9833{
9834 uint32_t sel : 2; /* emac0_tx_clk Mux Selection Field */
9835 uint32_t : 30; /* *UNDEFINED* */
9836};
9837
9838/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO0. */
9839typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO0_s ALT_SYSMGR_PINMUX_EMACIO0_t;
9840#endif /* __ASSEMBLY__ */
9841
9842/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO0 register from the beginning of the component. */
9843#define ALT_SYSMGR_PINMUX_EMACIO0_OFST 0x0
9844
9845/*
9846 * Register : emac0_tx_d0 Mux Selection Register - EMACIO1
9847 *
9848 * This register is used to control the peripherals connected to emac0_tx_d0
9849 *
9850 * Only reset by a cold reset (ignores warm reset).
9851 *
9852 * NOTE: These registers should not be modified after IO configuration.There is no
9853 * support for dynamically changing the Pin Mux selections.
9854 *
9855 * Register Layout
9856 *
9857 * Bits | Access | Reset | Description
9858 * :-------|:-------|:------|:--------------------------------
9859 * [1:0] | RW | 0x0 | emac0_tx_d0 Mux Selection Field
9860 * [31:2] | ??? | 0x0 | *UNDEFINED*
9861 *
9862 */
9863/*
9864 * Field : emac0_tx_d0 Mux Selection Field - sel
9865 *
9866 * Select peripheral signals connected emac0_tx_d0.
9867 *
9868 * 0 : Pin is connected to GPIO/LoanIO number 1.
9869 *
9870 * 1 : Pin is connected to Peripheral signal not applicable.
9871 *
9872 * 2 : Pin is connected to Peripheral signal USB1.D0.
9873 *
9874 * 3 : Pin is connected to Peripheral signal RGMII0.TXD0.
9875 *
9876 * Field Access Macros:
9877 *
9878 */
9879/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */
9880#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_LSB 0
9881/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */
9882#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_MSB 1
9883/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */
9884#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_WIDTH 2
9885/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value. */
9886#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET_MSK 0x00000003
9887/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value. */
9888#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_CLR_MSK 0xfffffffc
9889/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */
9890#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_RESET 0x0
9891/* Extracts the ALT_SYSMGR_PINMUX_EMACIO1_SEL field value from a register. */
9892#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
9893/* Produces a ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value suitable for setting the register. */
9894#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET(value) (((value) << 0) & 0x00000003)
9895
9896#ifndef __ASSEMBLY__
9897/*
9898 * WARNING: The C register and register group struct declarations are provided for
9899 * convenience and illustrative purposes. They should, however, be used with
9900 * caution as the C language standard provides no guarantees about the alignment or
9901 * atomicity of device memory accesses. The recommended practice for writing
9902 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9903 * alt_write_word() functions.
9904 *
9905 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO1.
9906 */
9907 struct ALT_SYSMGR_PINMUX_EMACIO1_s
9908{
9909 uint32_t sel : 2; /* emac0_tx_d0 Mux Selection Field */
9910 uint32_t : 30; /* *UNDEFINED* */
9911};
9912
9913/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO1. */
9914typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO1_s ALT_SYSMGR_PINMUX_EMACIO1_t;
9915#endif /* __ASSEMBLY__ */
9916
9917/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO1 register from the beginning of the component. */
9918#define ALT_SYSMGR_PINMUX_EMACIO1_OFST 0x4
9919
9920/*
9921 * Register : emac0_tx_d1 Mux Selection Register - EMACIO2
9922 *
9923 * This register is used to control the peripherals connected to emac0_tx_d1
9924 *
9925 * Only reset by a cold reset (ignores warm reset).
9926 *
9927 * NOTE: These registers should not be modified after IO configuration.There is no
9928 * support for dynamically changing the Pin Mux selections.
9929 *
9930 * Register Layout
9931 *
9932 * Bits | Access | Reset | Description
9933 * :-------|:-------|:------|:--------------------------------
9934 * [1:0] | RW | 0x0 | emac0_tx_d1 Mux Selection Field
9935 * [31:2] | ??? | 0x0 | *UNDEFINED*
9936 *
9937 */
9938/*
9939 * Field : emac0_tx_d1 Mux Selection Field - sel
9940 *
9941 * Select peripheral signals connected emac0_tx_d1.
9942 *
9943 * 0 : Pin is connected to GPIO/LoanIO number 2.
9944 *
9945 * 1 : Pin is connected to Peripheral signal not applicable.
9946 *
9947 * 2 : Pin is connected to Peripheral signal USB1.D1.
9948 *
9949 * 3 : Pin is connected to Peripheral signal RGMII0.TXD1.
9950 *
9951 * Field Access Macros:
9952 *
9953 */
9954/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */
9955#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_LSB 0
9956/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */
9957#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_MSB 1
9958/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */
9959#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_WIDTH 2
9960/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value. */
9961#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET_MSK 0x00000003
9962/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value. */
9963#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_CLR_MSK 0xfffffffc
9964/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */
9965#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_RESET 0x0
9966/* Extracts the ALT_SYSMGR_PINMUX_EMACIO2_SEL field value from a register. */
9967#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
9968/* Produces a ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value suitable for setting the register. */
9969#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET(value) (((value) << 0) & 0x00000003)
9970
9971#ifndef __ASSEMBLY__
9972/*
9973 * WARNING: The C register and register group struct declarations are provided for
9974 * convenience and illustrative purposes. They should, however, be used with
9975 * caution as the C language standard provides no guarantees about the alignment or
9976 * atomicity of device memory accesses. The recommended practice for writing
9977 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9978 * alt_write_word() functions.
9979 *
9980 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO2.
9981 */
9982 struct ALT_SYSMGR_PINMUX_EMACIO2_s
9983{
9984 uint32_t sel : 2; /* emac0_tx_d1 Mux Selection Field */
9985 uint32_t : 30; /* *UNDEFINED* */
9986};
9987
9988/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO2. */
9989typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO2_s ALT_SYSMGR_PINMUX_EMACIO2_t;
9990#endif /* __ASSEMBLY__ */
9991
9992/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO2 register from the beginning of the component. */
9993#define ALT_SYSMGR_PINMUX_EMACIO2_OFST 0x8
9994
9995/*
9996 * Register : emac0_tx_d2 Mux Selection Register - EMACIO3
9997 *
9998 * This register is used to control the peripherals connected to emac0_tx_d2
9999 *
10000 * Only reset by a cold reset (ignores warm reset).
10001 *
10002 * NOTE: These registers should not be modified after IO configuration.There is no
10003 * support for dynamically changing the Pin Mux selections.
10004 *
10005 * Register Layout
10006 *
10007 * Bits | Access | Reset | Description
10008 * :-------|:-------|:------|:--------------------------------
10009 * [1:0] | RW | 0x0 | emac0_tx_d2 Mux Selection Field
10010 * [31:2] | ??? | 0x0 | *UNDEFINED*
10011 *
10012 */
10013/*
10014 * Field : emac0_tx_d2 Mux Selection Field - sel
10015 *
10016 * Select peripheral signals connected emac0_tx_d2.
10017 *
10018 * 0 : Pin is connected to GPIO/LoanIO number 3.
10019 *
10020 * 1 : Pin is connected to Peripheral signal not applicable.
10021 *
10022 * 2 : Pin is connected to Peripheral signal USB1.D2.
10023 *
10024 * 3 : Pin is connected to Peripheral signal RGMII0.TXD2.
10025 *
10026 * Field Access Macros:
10027 *
10028 */
10029/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */
10030#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_LSB 0
10031/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */
10032#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_MSB 1
10033/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */
10034#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_WIDTH 2
10035/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value. */
10036#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET_MSK 0x00000003
10037/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value. */
10038#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_CLR_MSK 0xfffffffc
10039/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */
10040#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_RESET 0x0
10041/* Extracts the ALT_SYSMGR_PINMUX_EMACIO3_SEL field value from a register. */
10042#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
10043/* Produces a ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value suitable for setting the register. */
10044#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET(value) (((value) << 0) & 0x00000003)
10045
10046#ifndef __ASSEMBLY__
10047/*
10048 * WARNING: The C register and register group struct declarations are provided for
10049 * convenience and illustrative purposes. They should, however, be used with
10050 * caution as the C language standard provides no guarantees about the alignment or
10051 * atomicity of device memory accesses. The recommended practice for writing
10052 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10053 * alt_write_word() functions.
10054 *
10055 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO3.
10056 */
10057 struct ALT_SYSMGR_PINMUX_EMACIO3_s
10058{
10059 uint32_t sel : 2; /* emac0_tx_d2 Mux Selection Field */
10060 uint32_t : 30; /* *UNDEFINED* */
10061};
10062
10063/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO3. */
10064typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO3_s ALT_SYSMGR_PINMUX_EMACIO3_t;
10065#endif /* __ASSEMBLY__ */
10066
10067/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO3 register from the beginning of the component. */
10068#define ALT_SYSMGR_PINMUX_EMACIO3_OFST 0xc
10069
10070/*
10071 * Register : emac0_tx_d3 Mux Selection Register - EMACIO4
10072 *
10073 * This register is used to control the peripherals connected to emac0_tx_d3
10074 *
10075 * Only reset by a cold reset (ignores warm reset).
10076 *
10077 * NOTE: These registers should not be modified after IO configuration.There is no
10078 * support for dynamically changing the Pin Mux selections.
10079 *
10080 * Register Layout
10081 *
10082 * Bits | Access | Reset | Description
10083 * :-------|:-------|:------|:--------------------------------
10084 * [1:0] | RW | 0x0 | emac0_tx_d3 Mux Selection Field
10085 * [31:2] | ??? | 0x0 | *UNDEFINED*
10086 *
10087 */
10088/*
10089 * Field : emac0_tx_d3 Mux Selection Field - sel
10090 *
10091 * Select peripheral signals connected emac0_tx_d3.
10092 *
10093 * 0 : Pin is connected to GPIO/LoanIO number 4.
10094 *
10095 * 1 : Pin is connected to Peripheral signal not applicable.
10096 *
10097 * 2 : Pin is connected to Peripheral signal USB1.D3.
10098 *
10099 * 3 : Pin is connected to Peripheral signal RGMII0.TXD3.
10100 *
10101 * Field Access Macros:
10102 *
10103 */
10104/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */
10105#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_LSB 0
10106/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */
10107#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_MSB 1
10108/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */
10109#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_WIDTH 2
10110/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value. */
10111#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET_MSK 0x00000003
10112/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value. */
10113#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_CLR_MSK 0xfffffffc
10114/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */
10115#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_RESET 0x0
10116/* Extracts the ALT_SYSMGR_PINMUX_EMACIO4_SEL field value from a register. */
10117#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
10118/* Produces a ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value suitable for setting the register. */
10119#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET(value) (((value) << 0) & 0x00000003)
10120
10121#ifndef __ASSEMBLY__
10122/*
10123 * WARNING: The C register and register group struct declarations are provided for
10124 * convenience and illustrative purposes. They should, however, be used with
10125 * caution as the C language standard provides no guarantees about the alignment or
10126 * atomicity of device memory accesses. The recommended practice for writing
10127 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10128 * alt_write_word() functions.
10129 *
10130 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO4.
10131 */
10132 struct ALT_SYSMGR_PINMUX_EMACIO4_s
10133{
10134 uint32_t sel : 2; /* emac0_tx_d3 Mux Selection Field */
10135 uint32_t : 30; /* *UNDEFINED* */
10136};
10137
10138/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO4. */
10139typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO4_s ALT_SYSMGR_PINMUX_EMACIO4_t;
10140#endif /* __ASSEMBLY__ */
10141
10142/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO4 register from the beginning of the component. */
10143#define ALT_SYSMGR_PINMUX_EMACIO4_OFST 0x10
10144
10145/*
10146 * Register : emac0_rx_d0 Mux Selection Register - EMACIO5
10147 *
10148 * This register is used to control the peripherals connected to emac0_rx_d0
10149 *
10150 * Only reset by a cold reset (ignores warm reset).
10151 *
10152 * NOTE: These registers should not be modified after IO configuration.There is no
10153 * support for dynamically changing the Pin Mux selections.
10154 *
10155 * Register Layout
10156 *
10157 * Bits | Access | Reset | Description
10158 * :-------|:-------|:------|:--------------------------------
10159 * [1:0] | RW | 0x0 | emac0_rx_d0 Mux Selection Field
10160 * [31:2] | ??? | 0x0 | *UNDEFINED*
10161 *
10162 */
10163/*
10164 * Field : emac0_rx_d0 Mux Selection Field - sel
10165 *
10166 * Select peripheral signals connected emac0_rx_d0.
10167 *
10168 * 0 : Pin is connected to GPIO/LoanIO number 5.
10169 *
10170 * 1 : Pin is connected to Peripheral signal not applicable.
10171 *
10172 * 2 : Pin is connected to Peripheral signal USB1.D4.
10173 *
10174 * 3 : Pin is connected to Peripheral signal RGMII0.RXD0.
10175 *
10176 * Field Access Macros:
10177 *
10178 */
10179/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */
10180#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_LSB 0
10181/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */
10182#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_MSB 1
10183/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */
10184#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_WIDTH 2
10185/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value. */
10186#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET_MSK 0x00000003
10187/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value. */
10188#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_CLR_MSK 0xfffffffc
10189/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */
10190#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_RESET 0x0
10191/* Extracts the ALT_SYSMGR_PINMUX_EMACIO5_SEL field value from a register. */
10192#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
10193/* Produces a ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value suitable for setting the register. */
10194#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET(value) (((value) << 0) & 0x00000003)
10195
10196#ifndef __ASSEMBLY__
10197/*
10198 * WARNING: The C register and register group struct declarations are provided for
10199 * convenience and illustrative purposes. They should, however, be used with
10200 * caution as the C language standard provides no guarantees about the alignment or
10201 * atomicity of device memory accesses. The recommended practice for writing
10202 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10203 * alt_write_word() functions.
10204 *
10205 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO5.
10206 */
10207 struct ALT_SYSMGR_PINMUX_EMACIO5_s
10208{
10209 uint32_t sel : 2; /* emac0_rx_d0 Mux Selection Field */
10210 uint32_t : 30; /* *UNDEFINED* */
10211};
10212
10213/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO5. */
10214typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO5_s ALT_SYSMGR_PINMUX_EMACIO5_t;
10215#endif /* __ASSEMBLY__ */
10216
10217/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO5 register from the beginning of the component. */
10218#define ALT_SYSMGR_PINMUX_EMACIO5_OFST 0x14
10219
10220/*
10221 * Register : emac0_mdio Mux Selection Register - EMACIO6
10222 *
10223 * This register is used to control the peripherals connected to emac0_mdio
10224 *
10225 * Only reset by a cold reset (ignores warm reset).
10226 *
10227 * NOTE: These registers should not be modified after IO configuration.There is no
10228 * support for dynamically changing the Pin Mux selections.
10229 *
10230 * Register Layout
10231 *
10232 * Bits | Access | Reset | Description
10233 * :-------|:-------|:------|:-------------------------------
10234 * [1:0] | RW | 0x0 | emac0_mdio Mux Selection Field
10235 * [31:2] | ??? | 0x0 | *UNDEFINED*
10236 *
10237 */
10238/*
10239 * Field : emac0_mdio Mux Selection Field - sel
10240 *
10241 * Select peripheral signals connected emac0_mdio.
10242 *
10243 * 0 : Pin is connected to GPIO/LoanIO number 6.
10244 *
10245 * 1 : Pin is connected to Peripheral signal I2C2.SDA.
10246 *
10247 * 2 : Pin is connected to Peripheral signal USB1.D5.
10248 *
10249 * 3 : Pin is connected to Peripheral signal RGMII0.MDIO.
10250 *
10251 * Field Access Macros:
10252 *
10253 */
10254/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */
10255#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_LSB 0
10256/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */
10257#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_MSB 1
10258/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */
10259#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_WIDTH 2
10260/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value. */
10261#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET_MSK 0x00000003
10262/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value. */
10263#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_CLR_MSK 0xfffffffc
10264/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */
10265#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_RESET 0x0
10266/* Extracts the ALT_SYSMGR_PINMUX_EMACIO6_SEL field value from a register. */
10267#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
10268/* Produces a ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value suitable for setting the register. */
10269#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET(value) (((value) << 0) & 0x00000003)
10270
10271#ifndef __ASSEMBLY__
10272/*
10273 * WARNING: The C register and register group struct declarations are provided for
10274 * convenience and illustrative purposes. They should, however, be used with
10275 * caution as the C language standard provides no guarantees about the alignment or
10276 * atomicity of device memory accesses. The recommended practice for writing
10277 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10278 * alt_write_word() functions.
10279 *
10280 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO6.
10281 */
10282 struct ALT_SYSMGR_PINMUX_EMACIO6_s
10283{
10284 uint32_t sel : 2; /* emac0_mdio Mux Selection Field */
10285 uint32_t : 30; /* *UNDEFINED* */
10286};
10287
10288/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO6. */
10289typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO6_s ALT_SYSMGR_PINMUX_EMACIO6_t;
10290#endif /* __ASSEMBLY__ */
10291
10292/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO6 register from the beginning of the component. */
10293#define ALT_SYSMGR_PINMUX_EMACIO6_OFST 0x18
10294
10295/*
10296 * Register : emac0_mdc Mux Selection Register - EMACIO7
10297 *
10298 * This register is used to control the peripherals connected to emac0_mdc
10299 *
10300 * Only reset by a cold reset (ignores warm reset).
10301 *
10302 * NOTE: These registers should not be modified after IO configuration.There is no
10303 * support for dynamically changing the Pin Mux selections.
10304 *
10305 * Register Layout
10306 *
10307 * Bits | Access | Reset | Description
10308 * :-------|:-------|:------|:------------------------------
10309 * [1:0] | RW | 0x0 | emac0_mdc Mux Selection Field
10310 * [31:2] | ??? | 0x0 | *UNDEFINED*
10311 *
10312 */
10313/*
10314 * Field : emac0_mdc Mux Selection Field - sel
10315 *
10316 * Select peripheral signals connected emac0_mdc.
10317 *
10318 * 0 : Pin is connected to GPIO/LoanIO number 7.
10319 *
10320 * 1 : Pin is connected to Peripheral signal I2C2.SCL.
10321 *
10322 * 2 : Pin is connected to Peripheral signal USB1.D6.
10323 *
10324 * 3 : Pin is connected to Peripheral signal RGMII0.MDC.
10325 *
10326 * Field Access Macros:
10327 *
10328 */
10329/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */
10330#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_LSB 0
10331/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */
10332#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_MSB 1
10333/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */
10334#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_WIDTH 2
10335/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value. */
10336#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET_MSK 0x00000003
10337/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value. */
10338#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_CLR_MSK 0xfffffffc
10339/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */
10340#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_RESET 0x0
10341/* Extracts the ALT_SYSMGR_PINMUX_EMACIO7_SEL field value from a register. */
10342#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
10343/* Produces a ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value suitable for setting the register. */
10344#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET(value) (((value) << 0) & 0x00000003)
10345
10346#ifndef __ASSEMBLY__
10347/*
10348 * WARNING: The C register and register group struct declarations are provided for
10349 * convenience and illustrative purposes. They should, however, be used with
10350 * caution as the C language standard provides no guarantees about the alignment or
10351 * atomicity of device memory accesses. The recommended practice for writing
10352 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10353 * alt_write_word() functions.
10354 *
10355 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO7.
10356 */
10357 struct ALT_SYSMGR_PINMUX_EMACIO7_s
10358{
10359 uint32_t sel : 2; /* emac0_mdc Mux Selection Field */
10360 uint32_t : 30; /* *UNDEFINED* */
10361};
10362
10363/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO7. */
10364typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO7_s ALT_SYSMGR_PINMUX_EMACIO7_t;
10365#endif /* __ASSEMBLY__ */
10366
10367/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO7 register from the beginning of the component. */
10368#define ALT_SYSMGR_PINMUX_EMACIO7_OFST 0x1c
10369
10370/*
10371 * Register : emac0_rx_ctl Mux Selection Register - EMACIO8
10372 *
10373 * This register is used to control the peripherals connected to emac0_rx_ctl
10374 *
10375 * Only reset by a cold reset (ignores warm reset).
10376 *
10377 * NOTE: These registers should not be modified after IO configuration.There is no
10378 * support for dynamically changing the Pin Mux selections.
10379 *
10380 * Register Layout
10381 *
10382 * Bits | Access | Reset | Description
10383 * :-------|:-------|:------|:---------------------------------
10384 * [1:0] | RW | 0x0 | emac0_rx_ctl Mux Selection Field
10385 * [31:2] | ??? | 0x0 | *UNDEFINED*
10386 *
10387 */
10388/*
10389 * Field : emac0_rx_ctl Mux Selection Field - sel
10390 *
10391 * Select peripheral signals connected emac0_rx_ctl.
10392 *
10393 * 0 : Pin is connected to GPIO/LoanIO number 8.
10394 *
10395 * 1 : Pin is connected to Peripheral signal not applicable.
10396 *
10397 * 2 : Pin is connected to Peripheral signal USB1.D7.
10398 *
10399 * 3 : Pin is connected to Peripheral signal RGMII0.RX_CTL.
10400 *
10401 * Field Access Macros:
10402 *
10403 */
10404/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */
10405#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_LSB 0
10406/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */
10407#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_MSB 1
10408/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */
10409#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_WIDTH 2
10410/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value. */
10411#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET_MSK 0x00000003
10412/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value. */
10413#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_CLR_MSK 0xfffffffc
10414/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */
10415#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_RESET 0x0
10416/* Extracts the ALT_SYSMGR_PINMUX_EMACIO8_SEL field value from a register. */
10417#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
10418/* Produces a ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value suitable for setting the register. */
10419#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET(value) (((value) << 0) & 0x00000003)
10420
10421#ifndef __ASSEMBLY__
10422/*
10423 * WARNING: The C register and register group struct declarations are provided for
10424 * convenience and illustrative purposes. They should, however, be used with
10425 * caution as the C language standard provides no guarantees about the alignment or
10426 * atomicity of device memory accesses. The recommended practice for writing
10427 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10428 * alt_write_word() functions.
10429 *
10430 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO8.
10431 */
10432 struct ALT_SYSMGR_PINMUX_EMACIO8_s
10433{
10434 uint32_t sel : 2; /* emac0_rx_ctl Mux Selection Field */
10435 uint32_t : 30; /* *UNDEFINED* */
10436};
10437
10438/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO8. */
10439typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO8_s ALT_SYSMGR_PINMUX_EMACIO8_t;
10440#endif /* __ASSEMBLY__ */
10441
10442/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO8 register from the beginning of the component. */
10443#define ALT_SYSMGR_PINMUX_EMACIO8_OFST 0x20
10444
10445/*
10446 * Register : emac0_tx_ctl Mux Selection Register - EMACIO9
10447 *
10448 * This register is used to control the peripherals connected to emac0_tx_ctl
10449 *
10450 * Only reset by a cold reset (ignores warm reset).
10451 *
10452 * NOTE: These registers should not be modified after IO configuration.There is no
10453 * support for dynamically changing the Pin Mux selections.
10454 *
10455 * Register Layout
10456 *
10457 * Bits | Access | Reset | Description
10458 * :-------|:-------|:------|:---------------------------------
10459 * [1:0] | RW | 0x0 | emac0_tx_ctl Mux Selection Field
10460 * [31:2] | ??? | 0x0 | *UNDEFINED*
10461 *
10462 */
10463/*
10464 * Field : emac0_tx_ctl Mux Selection Field - sel
10465 *
10466 * Select peripheral signals connected emac0_tx_ctl.
10467 *
10468 * 0 : Pin is connected to GPIO/LoanIO number 9.
10469 *
10470 * 1 : Pin is connected to Peripheral signal not applicable.
10471 *
10472 * 2 : Pin is connected to Peripheral signal not applicable.
10473 *
10474 * 3 : Pin is connected to Peripheral signal RGMII0.TX_CTL.
10475 *
10476 * Field Access Macros:
10477 *
10478 */
10479/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */
10480#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_LSB 0
10481/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */
10482#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_MSB 1
10483/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */
10484#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_WIDTH 2
10485/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value. */
10486#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET_MSK 0x00000003
10487/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value. */
10488#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_CLR_MSK 0xfffffffc
10489/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */
10490#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_RESET 0x0
10491/* Extracts the ALT_SYSMGR_PINMUX_EMACIO9_SEL field value from a register. */
10492#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
10493/* Produces a ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value suitable for setting the register. */
10494#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET(value) (((value) << 0) & 0x00000003)
10495
10496#ifndef __ASSEMBLY__
10497/*
10498 * WARNING: The C register and register group struct declarations are provided for
10499 * convenience and illustrative purposes. They should, however, be used with
10500 * caution as the C language standard provides no guarantees about the alignment or
10501 * atomicity of device memory accesses. The recommended practice for writing
10502 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10503 * alt_write_word() functions.
10504 *
10505 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO9.
10506 */
10507 struct ALT_SYSMGR_PINMUX_EMACIO9_s
10508{
10509 uint32_t sel : 2; /* emac0_tx_ctl Mux Selection Field */
10510 uint32_t : 30; /* *UNDEFINED* */
10511};
10512
10513/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO9. */
10514typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO9_s ALT_SYSMGR_PINMUX_EMACIO9_t;
10515#endif /* __ASSEMBLY__ */
10516
10517/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO9 register from the beginning of the component. */
10518#define ALT_SYSMGR_PINMUX_EMACIO9_OFST 0x24
10519
10520/*
10521 * Register : emac0_rx_clk Mux Selection Register - EMACIO10
10522 *
10523 * This register is used to control the peripherals connected to emac0_rx_clk
10524 *
10525 * Only reset by a cold reset (ignores warm reset).
10526 *
10527 * NOTE: These registers should not be modified after IO configuration.There is no
10528 * support for dynamically changing the Pin Mux selections.
10529 *
10530 * Register Layout
10531 *
10532 * Bits | Access | Reset | Description
10533 * :-------|:-------|:------|:---------------------------------
10534 * [1:0] | RW | 0x0 | emac0_rx_clk Mux Selection Field
10535 * [31:2] | ??? | 0x0 | *UNDEFINED*
10536 *
10537 */
10538/*
10539 * Field : emac0_rx_clk Mux Selection Field - sel
10540 *
10541 * Select peripheral signals connected emac0_rx_clk.
10542 *
10543 * 0 : Pin is connected to GPIO/LoanIO number 10.
10544 *
10545 * 1 : Pin is connected to Peripheral signal not applicable.
10546 *
10547 * 2 : Pin is connected to Peripheral signal USB1.CLK.
10548 *
10549 * 3 : Pin is connected to Peripheral signal RGMII0.RX_CLK.
10550 *
10551 * Field Access Macros:
10552 *
10553 */
10554/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */
10555#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_LSB 0
10556/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */
10557#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_MSB 1
10558/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */
10559#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_WIDTH 2
10560/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value. */
10561#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET_MSK 0x00000003
10562/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value. */
10563#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_CLR_MSK 0xfffffffc
10564/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */
10565#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_RESET 0x0
10566/* Extracts the ALT_SYSMGR_PINMUX_EMACIO10_SEL field value from a register. */
10567#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
10568/* Produces a ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value suitable for setting the register. */
10569#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET(value) (((value) << 0) & 0x00000003)
10570
10571#ifndef __ASSEMBLY__
10572/*
10573 * WARNING: The C register and register group struct declarations are provided for
10574 * convenience and illustrative purposes. They should, however, be used with
10575 * caution as the C language standard provides no guarantees about the alignment or
10576 * atomicity of device memory accesses. The recommended practice for writing
10577 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10578 * alt_write_word() functions.
10579 *
10580 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO10.
10581 */
10582 struct ALT_SYSMGR_PINMUX_EMACIO10_s
10583{
10584 uint32_t sel : 2; /* emac0_rx_clk Mux Selection Field */
10585 uint32_t : 30; /* *UNDEFINED* */
10586};
10587
10588/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO10. */
10589typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO10_s ALT_SYSMGR_PINMUX_EMACIO10_t;
10590#endif /* __ASSEMBLY__ */
10591
10592/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO10 register from the beginning of the component. */
10593#define ALT_SYSMGR_PINMUX_EMACIO10_OFST 0x28
10594
10595/*
10596 * Register : emac0_rx_d1 Mux Selection Register - EMACIO11
10597 *
10598 * This register is used to control the peripherals connected to emac0_rx_d1
10599 *
10600 * Only reset by a cold reset (ignores warm reset).
10601 *
10602 * NOTE: These registers should not be modified after IO configuration.There is no
10603 * support for dynamically changing the Pin Mux selections.
10604 *
10605 * Register Layout
10606 *
10607 * Bits | Access | Reset | Description
10608 * :-------|:-------|:------|:--------------------------------
10609 * [1:0] | RW | 0x0 | emac0_rx_d1 Mux Selection Field
10610 * [31:2] | ??? | 0x0 | *UNDEFINED*
10611 *
10612 */
10613/*
10614 * Field : emac0_rx_d1 Mux Selection Field - sel
10615 *
10616 * Select peripheral signals connected emac0_rx_d1.
10617 *
10618 * 0 : Pin is connected to GPIO/LoanIO number 11.
10619 *
10620 * 1 : Pin is connected to Peripheral signal not applicable.
10621 *
10622 * 2 : Pin is connected to Peripheral signal USB1.STP.
10623 *
10624 * 3 : Pin is connected to Peripheral signal RGMII0.RXD1.
10625 *
10626 * Field Access Macros:
10627 *
10628 */
10629/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */
10630#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_LSB 0
10631/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */
10632#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_MSB 1
10633/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */
10634#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_WIDTH 2
10635/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value. */
10636#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET_MSK 0x00000003
10637/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value. */
10638#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_CLR_MSK 0xfffffffc
10639/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */
10640#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_RESET 0x0
10641/* Extracts the ALT_SYSMGR_PINMUX_EMACIO11_SEL field value from a register. */
10642#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
10643/* Produces a ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value suitable for setting the register. */
10644#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET(value) (((value) << 0) & 0x00000003)
10645
10646#ifndef __ASSEMBLY__
10647/*
10648 * WARNING: The C register and register group struct declarations are provided for
10649 * convenience and illustrative purposes. They should, however, be used with
10650 * caution as the C language standard provides no guarantees about the alignment or
10651 * atomicity of device memory accesses. The recommended practice for writing
10652 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10653 * alt_write_word() functions.
10654 *
10655 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO11.
10656 */
10657 struct ALT_SYSMGR_PINMUX_EMACIO11_s
10658{
10659 uint32_t sel : 2; /* emac0_rx_d1 Mux Selection Field */
10660 uint32_t : 30; /* *UNDEFINED* */
10661};
10662
10663/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO11. */
10664typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO11_s ALT_SYSMGR_PINMUX_EMACIO11_t;
10665#endif /* __ASSEMBLY__ */
10666
10667/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO11 register from the beginning of the component. */
10668#define ALT_SYSMGR_PINMUX_EMACIO11_OFST 0x2c
10669
10670/*
10671 * Register : emac0_rx_d2 Mux Selection Register - EMACIO12
10672 *
10673 * This register is used to control the peripherals connected to emac0_rx_d2
10674 *
10675 * Only reset by a cold reset (ignores warm reset).
10676 *
10677 * NOTE: These registers should not be modified after IO configuration.There is no
10678 * support for dynamically changing the Pin Mux selections.
10679 *
10680 * Register Layout
10681 *
10682 * Bits | Access | Reset | Description
10683 * :-------|:-------|:------|:--------------------------------
10684 * [1:0] | RW | 0x0 | emac0_rx_d2 Mux Selection Field
10685 * [31:2] | ??? | 0x0 | *UNDEFINED*
10686 *
10687 */
10688/*
10689 * Field : emac0_rx_d2 Mux Selection Field - sel
10690 *
10691 * Select peripheral signals connected emac0_rx_d2.
10692 *
10693 * 0 : Pin is connected to GPIO/LoanIO number 12.
10694 *
10695 * 1 : Pin is connected to Peripheral signal not applicable.
10696 *
10697 * 2 : Pin is connected to Peripheral signal USB1.DIR.
10698 *
10699 * 3 : Pin is connected to Peripheral signal RGMII0.RXD2.
10700 *
10701 * Field Access Macros:
10702 *
10703 */
10704/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */
10705#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_LSB 0
10706/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */
10707#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_MSB 1
10708/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */
10709#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_WIDTH 2
10710/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value. */
10711#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET_MSK 0x00000003
10712/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value. */
10713#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_CLR_MSK 0xfffffffc
10714/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */
10715#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_RESET 0x0
10716/* Extracts the ALT_SYSMGR_PINMUX_EMACIO12_SEL field value from a register. */
10717#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_GET(value) (((value) & 0x00000003) >> 0)
10718/* Produces a ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value suitable for setting the register. */
10719#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET(value) (((value) << 0) & 0x00000003)
10720
10721#ifndef __ASSEMBLY__
10722/*
10723 * WARNING: The C register and register group struct declarations are provided for
10724 * convenience and illustrative purposes. They should, however, be used with
10725 * caution as the C language standard provides no guarantees about the alignment or
10726 * atomicity of device memory accesses. The recommended practice for writing
10727 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10728 * alt_write_word() functions.
10729 *
10730 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO12.
10731 */
10732 struct ALT_SYSMGR_PINMUX_EMACIO12_s
10733{
10734 uint32_t sel : 2; /* emac0_rx_d2 Mux Selection Field */
10735 uint32_t : 30; /* *UNDEFINED* */
10736};
10737
10738/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO12. */
10739typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO12_s ALT_SYSMGR_PINMUX_EMACIO12_t;
10740#endif /* __ASSEMBLY__ */
10741
10742/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO12 register from the beginning of the component. */
10743#define ALT_SYSMGR_PINMUX_EMACIO12_OFST 0x30
10744
10745/*
10746 * Register : emac0_rx_d3 Mux Selection Register - EMACIO13
10747 *
10748 * This register is used to control the peripherals connected to emac0_rx_d3
10749 *
10750 * Only reset by a cold reset (ignores warm reset).
10751 *
10752 * NOTE: These registers should not be modified after IO configuration.There is no
10753 * support for dynamically changing the Pin Mux selections.
10754 *
10755 * Register Layout
10756 *
10757 * Bits | Access | Reset | Description
10758 * :-------|:-------|:------|:--------------------------------
10759 * [1:0] | RW | 0x0 | emac0_rx_d3 Mux Selection Field
10760 * [31:2] | ??? | 0x0 | *UNDEFINED*
10761 *
10762 */
10763/*
10764 * Field : emac0_rx_d3 Mux Selection Field - sel
10765 *
10766 * Select peripheral signals connected emac0_rx_d3.
10767 *
10768 * 0 : Pin is connected to GPIO/LoanIO number 13.
10769 *
10770 * 1 : Pin is connected to Peripheral signal not applicable.
10771 *
10772 * 2 : Pin is connected to Peripheral signal USB1.NXT.
10773 *
10774 * 3 : Pin is connected to Peripheral signal RGMII0.RXD3.
10775 *
10776 * Field Access Macros:
10777 *
10778 */
10779/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */
10780#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_LSB 0
10781/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */
10782#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_MSB 1
10783/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */
10784#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_WIDTH 2
10785/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value. */
10786#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET_MSK 0x00000003
10787/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value. */
10788#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_CLR_MSK 0xfffffffc
10789/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */
10790#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_RESET 0x0
10791/* Extracts the ALT_SYSMGR_PINMUX_EMACIO13_SEL field value from a register. */
10792#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_GET(value) (((value) & 0x00000003) >> 0)
10793/* Produces a ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value suitable for setting the register. */
10794#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET(value) (((value) << 0) & 0x00000003)
10795
10796#ifndef __ASSEMBLY__
10797/*
10798 * WARNING: The C register and register group struct declarations are provided for
10799 * convenience and illustrative purposes. They should, however, be used with
10800 * caution as the C language standard provides no guarantees about the alignment or
10801 * atomicity of device memory accesses. The recommended practice for writing
10802 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10803 * alt_write_word() functions.
10804 *
10805 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO13.
10806 */
10807 struct ALT_SYSMGR_PINMUX_EMACIO13_s
10808{
10809 uint32_t sel : 2; /* emac0_rx_d3 Mux Selection Field */
10810 uint32_t : 30; /* *UNDEFINED* */
10811};
10812
10813/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO13. */
10814typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO13_s ALT_SYSMGR_PINMUX_EMACIO13_t;
10815#endif /* __ASSEMBLY__ */
10816
10817/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO13 register from the beginning of the component. */
10818#define ALT_SYSMGR_PINMUX_EMACIO13_OFST 0x34
10819
10820/*
10821 * Register : emac1_tx_clk Mux Selection Register - EMACIO14
10822 *
10823 * This register is used to control the peripherals connected to emac1_tx_clk
10824 *
10825 * Only reset by a cold reset (ignores warm reset).
10826 *
10827 * NOTE: These registers should not be modified after IO configuration.There is no
10828 * support for dynamically changing the Pin Mux selections.
10829 *
10830 * Register Layout
10831 *
10832 * Bits | Access | Reset | Description
10833 * :-------|:-------|:------|:---------------------------------
10834 * [1:0] | RW | 0x0 | emac1_tx_clk Mux Selection Field
10835 * [31:2] | ??? | 0x0 | *UNDEFINED*
10836 *
10837 */
10838/*
10839 * Field : emac1_tx_clk Mux Selection Field - sel
10840 *
10841 * Select peripheral signals connected emac1_tx_clk.
10842 *
10843 * 0 : Pin is connected to GPIO/LoanIO number 48.
10844 *
10845 * 1 : Pin is connected to Peripheral signal not applicable.
10846 *
10847 * 2 : Pin is connected to Peripheral signal not applicable.
10848 *
10849 * 3 : Pin is connected to Peripheral signal RGMII1.TX_CLK.
10850 *
10851 * Field Access Macros:
10852 *
10853 */
10854/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */
10855#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_LSB 0
10856/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */
10857#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_MSB 1
10858/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */
10859#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_WIDTH 2
10860/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value. */
10861#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET_MSK 0x00000003
10862/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value. */
10863#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_CLR_MSK 0xfffffffc
10864/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */
10865#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_RESET 0x0
10866/* Extracts the ALT_SYSMGR_PINMUX_EMACIO14_SEL field value from a register. */
10867#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_GET(value) (((value) & 0x00000003) >> 0)
10868/* Produces a ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value suitable for setting the register. */
10869#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET(value) (((value) << 0) & 0x00000003)
10870
10871#ifndef __ASSEMBLY__
10872/*
10873 * WARNING: The C register and register group struct declarations are provided for
10874 * convenience and illustrative purposes. They should, however, be used with
10875 * caution as the C language standard provides no guarantees about the alignment or
10876 * atomicity of device memory accesses. The recommended practice for writing
10877 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10878 * alt_write_word() functions.
10879 *
10880 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO14.
10881 */
10882 struct ALT_SYSMGR_PINMUX_EMACIO14_s
10883{
10884 uint32_t sel : 2; /* emac1_tx_clk Mux Selection Field */
10885 uint32_t : 30; /* *UNDEFINED* */
10886};
10887
10888/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO14. */
10889typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO14_s ALT_SYSMGR_PINMUX_EMACIO14_t;
10890#endif /* __ASSEMBLY__ */
10891
10892/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO14 register from the beginning of the component. */
10893#define ALT_SYSMGR_PINMUX_EMACIO14_OFST 0x38
10894
10895/*
10896 * Register : emac1_tx_d0 Mux Selection Register - EMACIO15
10897 *
10898 * This register is used to control the peripherals connected to emac1_tx_d0
10899 *
10900 * Only reset by a cold reset (ignores warm reset).
10901 *
10902 * NOTE: These registers should not be modified after IO configuration.There is no
10903 * support for dynamically changing the Pin Mux selections.
10904 *
10905 * Register Layout
10906 *
10907 * Bits | Access | Reset | Description
10908 * :-------|:-------|:------|:--------------------------------
10909 * [1:0] | RW | 0x0 | emac1_tx_d0 Mux Selection Field
10910 * [31:2] | ??? | 0x0 | *UNDEFINED*
10911 *
10912 */
10913/*
10914 * Field : emac1_tx_d0 Mux Selection Field - sel
10915 *
10916 * Select peripheral signals connected emac1_tx_d0.
10917 *
10918 * 0 : Pin is connected to GPIO/LoanIO number 49.
10919 *
10920 * 1 : Pin is connected to Peripheral signal not applicable.
10921 *
10922 * 2 : Pin is connected to Peripheral signal not applicable.
10923 *
10924 * 3 : Pin is connected to Peripheral signal RGMII1.TXD0.
10925 *
10926 * Field Access Macros:
10927 *
10928 */
10929/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */
10930#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_LSB 0
10931/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */
10932#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_MSB 1
10933/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */
10934#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_WIDTH 2
10935/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value. */
10936#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET_MSK 0x00000003
10937/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value. */
10938#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_CLR_MSK 0xfffffffc
10939/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */
10940#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_RESET 0x0
10941/* Extracts the ALT_SYSMGR_PINMUX_EMACIO15_SEL field value from a register. */
10942#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_GET(value) (((value) & 0x00000003) >> 0)
10943/* Produces a ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value suitable for setting the register. */
10944#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET(value) (((value) << 0) & 0x00000003)
10945
10946#ifndef __ASSEMBLY__
10947/*
10948 * WARNING: The C register and register group struct declarations are provided for
10949 * convenience and illustrative purposes. They should, however, be used with
10950 * caution as the C language standard provides no guarantees about the alignment or
10951 * atomicity of device memory accesses. The recommended practice for writing
10952 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10953 * alt_write_word() functions.
10954 *
10955 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO15.
10956 */
10957 struct ALT_SYSMGR_PINMUX_EMACIO15_s
10958{
10959 uint32_t sel : 2; /* emac1_tx_d0 Mux Selection Field */
10960 uint32_t : 30; /* *UNDEFINED* */
10961};
10962
10963/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO15. */
10964typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO15_s ALT_SYSMGR_PINMUX_EMACIO15_t;
10965#endif /* __ASSEMBLY__ */
10966
10967/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO15 register from the beginning of the component. */
10968#define ALT_SYSMGR_PINMUX_EMACIO15_OFST 0x3c
10969
10970/*
10971 * Register : emac1_tx_d1 Mux Selection Register - EMACIO16
10972 *
10973 * This register is used to control the peripherals connected to emac1_tx_d1
10974 *
10975 * Only reset by a cold reset (ignores warm reset).
10976 *
10977 * NOTE: These registers should not be modified after IO configuration.There is no
10978 * support for dynamically changing the Pin Mux selections.
10979 *
10980 * Register Layout
10981 *
10982 * Bits | Access | Reset | Description
10983 * :-------|:-------|:------|:--------------------------------
10984 * [1:0] | RW | 0x0 | emac1_tx_d1 Mux Selection Field
10985 * [31:2] | ??? | 0x0 | *UNDEFINED*
10986 *
10987 */
10988/*
10989 * Field : emac1_tx_d1 Mux Selection Field - sel
10990 *
10991 * Select peripheral signals connected emac1_tx_d1.
10992 *
10993 * 0 : Pin is connected to GPIO/LoanIO number 50.
10994 *
10995 * 1 : Pin is connected to Peripheral signal not applicable.
10996 *
10997 * 2 : Pin is connected to Peripheral signal not applicable.
10998 *
10999 * 3 : Pin is connected to Peripheral signal RGMII1.TXD1.
11000 *
11001 * Field Access Macros:
11002 *
11003 */
11004/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */
11005#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_LSB 0
11006/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */
11007#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_MSB 1
11008/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */
11009#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_WIDTH 2
11010/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value. */
11011#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET_MSK 0x00000003
11012/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value. */
11013#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_CLR_MSK 0xfffffffc
11014/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */
11015#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_RESET 0x0
11016/* Extracts the ALT_SYSMGR_PINMUX_EMACIO16_SEL field value from a register. */
11017#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_GET(value) (((value) & 0x00000003) >> 0)
11018/* Produces a ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value suitable for setting the register. */
11019#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET(value) (((value) << 0) & 0x00000003)
11020
11021#ifndef __ASSEMBLY__
11022/*
11023 * WARNING: The C register and register group struct declarations are provided for
11024 * convenience and illustrative purposes. They should, however, be used with
11025 * caution as the C language standard provides no guarantees about the alignment or
11026 * atomicity of device memory accesses. The recommended practice for writing
11027 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11028 * alt_write_word() functions.
11029 *
11030 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO16.
11031 */
11032 struct ALT_SYSMGR_PINMUX_EMACIO16_s
11033{
11034 uint32_t sel : 2; /* emac1_tx_d1 Mux Selection Field */
11035 uint32_t : 30; /* *UNDEFINED* */
11036};
11037
11038/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO16. */
11039typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO16_s ALT_SYSMGR_PINMUX_EMACIO16_t;
11040#endif /* __ASSEMBLY__ */
11041
11042/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO16 register from the beginning of the component. */
11043#define ALT_SYSMGR_PINMUX_EMACIO16_OFST 0x40
11044
11045/*
11046 * Register : emac1_tx_ctl Mux Selection Register - EMACIO17
11047 *
11048 * This register is used to control the peripherals connected to emac1_tx_ctl
11049 *
11050 * Only reset by a cold reset (ignores warm reset).
11051 *
11052 * NOTE: These registers should not be modified after IO configuration.There is no
11053 * support for dynamically changing the Pin Mux selections.
11054 *
11055 * Register Layout
11056 *
11057 * Bits | Access | Reset | Description
11058 * :-------|:-------|:------|:---------------------------------
11059 * [1:0] | RW | 0x0 | emac1_tx_ctl Mux Selection Field
11060 * [31:2] | ??? | 0x0 | *UNDEFINED*
11061 *
11062 */
11063/*
11064 * Field : emac1_tx_ctl Mux Selection Field - sel
11065 *
11066 * Select peripheral signals connected emac1_tx_ctl.
11067 *
11068 * 0 : Pin is connected to GPIO/LoanIO number 51.
11069 *
11070 * 1 : Pin is connected to Peripheral signal not applicable.
11071 *
11072 * 2 : Pin is connected to Peripheral signal not applicable.
11073 *
11074 * 3 : Pin is connected to Peripheral signal RGMII1.TX_CTL.
11075 *
11076 * Field Access Macros:
11077 *
11078 */
11079/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */
11080#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_LSB 0
11081/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */
11082#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_MSB 1
11083/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */
11084#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_WIDTH 2
11085/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value. */
11086#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET_MSK 0x00000003
11087/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value. */
11088#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_CLR_MSK 0xfffffffc
11089/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */
11090#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_RESET 0x0
11091/* Extracts the ALT_SYSMGR_PINMUX_EMACIO17_SEL field value from a register. */
11092#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_GET(value) (((value) & 0x00000003) >> 0)
11093/* Produces a ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value suitable for setting the register. */
11094#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET(value) (((value) << 0) & 0x00000003)
11095
11096#ifndef __ASSEMBLY__
11097/*
11098 * WARNING: The C register and register group struct declarations are provided for
11099 * convenience and illustrative purposes. They should, however, be used with
11100 * caution as the C language standard provides no guarantees about the alignment or
11101 * atomicity of device memory accesses. The recommended practice for writing
11102 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11103 * alt_write_word() functions.
11104 *
11105 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO17.
11106 */
11107 struct ALT_SYSMGR_PINMUX_EMACIO17_s
11108{
11109 uint32_t sel : 2; /* emac1_tx_ctl Mux Selection Field */
11110 uint32_t : 30; /* *UNDEFINED* */
11111};
11112
11113/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO17. */
11114typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO17_s ALT_SYSMGR_PINMUX_EMACIO17_t;
11115#endif /* __ASSEMBLY__ */
11116
11117/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO17 register from the beginning of the component. */
11118#define ALT_SYSMGR_PINMUX_EMACIO17_OFST 0x44
11119
11120/*
11121 * Register : emac1_rx_d0 Mux Selection Register - EMACIO18
11122 *
11123 * This register is used to control the peripherals connected to emac1_rx_d0
11124 *
11125 * Only reset by a cold reset (ignores warm reset).
11126 *
11127 * NOTE: These registers should not be modified after IO configuration.There is no
11128 * support for dynamically changing the Pin Mux selections.
11129 *
11130 * Register Layout
11131 *
11132 * Bits | Access | Reset | Description
11133 * :-------|:-------|:------|:--------------------------------
11134 * [1:0] | RW | 0x0 | emac1_rx_d0 Mux Selection Field
11135 * [31:2] | ??? | 0x0 | *UNDEFINED*
11136 *
11137 */
11138/*
11139 * Field : emac1_rx_d0 Mux Selection Field - sel
11140 *
11141 * Select peripheral signals connected emac1_rx_d0.
11142 *
11143 * 0 : Pin is connected to GPIO/LoanIO number 52.
11144 *
11145 * 1 : Pin is connected to Peripheral signal not applicable.
11146 *
11147 * 2 : Pin is connected to Peripheral signal not applicable.
11148 *
11149 * 3 : Pin is connected to Peripheral signal RGMII1.RXD0.
11150 *
11151 * Field Access Macros:
11152 *
11153 */
11154/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */
11155#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_LSB 0
11156/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */
11157#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_MSB 1
11158/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */
11159#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_WIDTH 2
11160/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value. */
11161#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET_MSK 0x00000003
11162/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value. */
11163#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_CLR_MSK 0xfffffffc
11164/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */
11165#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_RESET 0x0
11166/* Extracts the ALT_SYSMGR_PINMUX_EMACIO18_SEL field value from a register. */
11167#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_GET(value) (((value) & 0x00000003) >> 0)
11168/* Produces a ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value suitable for setting the register. */
11169#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET(value) (((value) << 0) & 0x00000003)
11170
11171#ifndef __ASSEMBLY__
11172/*
11173 * WARNING: The C register and register group struct declarations are provided for
11174 * convenience and illustrative purposes. They should, however, be used with
11175 * caution as the C language standard provides no guarantees about the alignment or
11176 * atomicity of device memory accesses. The recommended practice for writing
11177 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11178 * alt_write_word() functions.
11179 *
11180 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO18.
11181 */
11182 struct ALT_SYSMGR_PINMUX_EMACIO18_s
11183{
11184 uint32_t sel : 2; /* emac1_rx_d0 Mux Selection Field */
11185 uint32_t : 30; /* *UNDEFINED* */
11186};
11187
11188/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO18. */
11189typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO18_s ALT_SYSMGR_PINMUX_EMACIO18_t;
11190#endif /* __ASSEMBLY__ */
11191
11192/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO18 register from the beginning of the component. */
11193#define ALT_SYSMGR_PINMUX_EMACIO18_OFST 0x48
11194
11195/*
11196 * Register : emac1_rx_d1 Mux Selection Register - EMACIO19
11197 *
11198 * This register is used to control the peripherals connected to emac1_rx_d1
11199 *
11200 * Only reset by a cold reset (ignores warm reset).
11201 *
11202 * NOTE: These registers should not be modified after IO configuration.There is no
11203 * support for dynamically changing the Pin Mux selections.
11204 *
11205 * Register Layout
11206 *
11207 * Bits | Access | Reset | Description
11208 * :-------|:-------|:------|:--------------------------------
11209 * [1:0] | RW | 0x0 | emac1_rx_d1 Mux Selection Field
11210 * [31:2] | ??? | 0x0 | *UNDEFINED*
11211 *
11212 */
11213/*
11214 * Field : emac1_rx_d1 Mux Selection Field - sel
11215 *
11216 * Select peripheral signals connected emac1_rx_d1.
11217 *
11218 * 0 : Pin is connected to GPIO/LoanIO number 53.
11219 *
11220 * 1 : Pin is connected to Peripheral signal not applicable.
11221 *
11222 * 2 : Pin is connected to Peripheral signal not applicable.
11223 *
11224 * 3 : Pin is connected to Peripheral signal RGMII1.RXD1.
11225 *
11226 * Field Access Macros:
11227 *
11228 */
11229/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */
11230#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_LSB 0
11231/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */
11232#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_MSB 1
11233/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */
11234#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_WIDTH 2
11235/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value. */
11236#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET_MSK 0x00000003
11237/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value. */
11238#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_CLR_MSK 0xfffffffc
11239/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */
11240#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_RESET 0x0
11241/* Extracts the ALT_SYSMGR_PINMUX_EMACIO19_SEL field value from a register. */
11242#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_GET(value) (((value) & 0x00000003) >> 0)
11243/* Produces a ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value suitable for setting the register. */
11244#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET(value) (((value) << 0) & 0x00000003)
11245
11246#ifndef __ASSEMBLY__
11247/*
11248 * WARNING: The C register and register group struct declarations are provided for
11249 * convenience and illustrative purposes. They should, however, be used with
11250 * caution as the C language standard provides no guarantees about the alignment or
11251 * atomicity of device memory accesses. The recommended practice for writing
11252 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11253 * alt_write_word() functions.
11254 *
11255 * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO19.
11256 */
11257 struct ALT_SYSMGR_PINMUX_EMACIO19_s
11258{
11259 uint32_t sel : 2; /* emac1_rx_d1 Mux Selection Field */
11260 uint32_t : 30; /* *UNDEFINED* */
11261};
11262
11263/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO19. */
11264typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO19_s ALT_SYSMGR_PINMUX_EMACIO19_t;
11265#endif /* __ASSEMBLY__ */
11266
11267/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO19 register from the beginning of the component. */
11268#define ALT_SYSMGR_PINMUX_EMACIO19_OFST 0x4c
11269
11270/*
11271 * Register : sdmmc_cmd Mux Selection Register - FLASHIO0
11272 *
11273 * This register is used to control the peripherals connected to sdmmc_cmd
11274 *
11275 * Only reset by a cold reset (ignores warm reset).
11276 *
11277 * NOTE: These registers should not be modified after IO configuration.There is no
11278 * support for dynamically changing the Pin Mux selections.
11279 *
11280 * Register Layout
11281 *
11282 * Bits | Access | Reset | Description
11283 * :-------|:-------|:------|:------------------------------
11284 * [1:0] | RW | 0x0 | sdmmc_cmd Mux Selection Field
11285 * [31:2] | ??? | 0x0 | *UNDEFINED*
11286 *
11287 */
11288/*
11289 * Field : sdmmc_cmd Mux Selection Field - sel
11290 *
11291 * Select peripheral signals connected sdmmc_cmd.
11292 *
11293 * 0 : Pin is connected to GPIO/LoanIO number 36.
11294 *
11295 * 1 : Pin is connected to Peripheral signal not applicable.
11296 *
11297 * 2 : Pin is connected to Peripheral signal USB0.D0.
11298 *
11299 * 3 : Pin is connected to Peripheral signal SDMMC.CMD.
11300 *
11301 * Field Access Macros:
11302 *
11303 */
11304/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */
11305#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_LSB 0
11306/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */
11307#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_MSB 1
11308/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */
11309#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_WIDTH 2
11310/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value. */
11311#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET_MSK 0x00000003
11312/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value. */
11313#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_CLR_MSK 0xfffffffc
11314/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */
11315#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_RESET 0x0
11316/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO0_SEL field value from a register. */
11317#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
11318/* Produces a ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value suitable for setting the register. */
11319#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET(value) (((value) << 0) & 0x00000003)
11320
11321#ifndef __ASSEMBLY__
11322/*
11323 * WARNING: The C register and register group struct declarations are provided for
11324 * convenience and illustrative purposes. They should, however, be used with
11325 * caution as the C language standard provides no guarantees about the alignment or
11326 * atomicity of device memory accesses. The recommended practice for writing
11327 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11328 * alt_write_word() functions.
11329 *
11330 * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO0.
11331 */
11332 struct ALT_SYSMGR_PINMUX_FLSHIO0_s
11333{
11334 uint32_t sel : 2; /* sdmmc_cmd Mux Selection Field */
11335 uint32_t : 30; /* *UNDEFINED* */
11336};
11337
11338/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO0. */
11339typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO0_s ALT_SYSMGR_PINMUX_FLSHIO0_t;
11340#endif /* __ASSEMBLY__ */
11341
11342/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO0 register from the beginning of the component. */
11343#define ALT_SYSMGR_PINMUX_FLSHIO0_OFST 0x50
11344
11345/*
11346 * Register : sdmmc_pwren Mux Selection Register - FLASHIO1
11347 *
11348 * This register is used to control the peripherals connected to sdmmc_pwren
11349 *
11350 * Only reset by a cold reset (ignores warm reset).
11351 *
11352 * NOTE: These registers should not be modified after IO configuration.There is no
11353 * support for dynamically changing the Pin Mux selections.
11354 *
11355 * Register Layout
11356 *
11357 * Bits | Access | Reset | Description
11358 * :-------|:-------|:------|:--------------------------------
11359 * [1:0] | RW | 0x0 | sdmmc_pwren Mux Selection Field
11360 * [31:2] | ??? | 0x0 | *UNDEFINED*
11361 *
11362 */
11363/*
11364 * Field : sdmmc_pwren Mux Selection Field - sel
11365 *
11366 * Select peripheral signals connected sdmmc_pwren.
11367 *
11368 * 0 : Pin is connected to GPIO/LoanIO number 37.
11369 *
11370 * 1 : Pin is connected to Peripheral signal not applicable.
11371 *
11372 * 2 : Pin is connected to Peripheral signal USB0.D1.
11373 *
11374 * 3 : Pin is connected to Peripheral signal SDMMC.PWREN.
11375 *
11376 * Field Access Macros:
11377 *
11378 */
11379/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */
11380#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_LSB 0
11381/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */
11382#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_MSB 1
11383/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */
11384#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_WIDTH 2
11385/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value. */
11386#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET_MSK 0x00000003
11387/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value. */
11388#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_CLR_MSK 0xfffffffc
11389/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */
11390#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_RESET 0x0
11391/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO1_SEL field value from a register. */
11392#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
11393/* Produces a ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value suitable for setting the register. */
11394#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET(value) (((value) << 0) & 0x00000003)
11395
11396#ifndef __ASSEMBLY__
11397/*
11398 * WARNING: The C register and register group struct declarations are provided for
11399 * convenience and illustrative purposes. They should, however, be used with
11400 * caution as the C language standard provides no guarantees about the alignment or
11401 * atomicity of device memory accesses. The recommended practice for writing
11402 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11403 * alt_write_word() functions.
11404 *
11405 * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO1.
11406 */
11407 struct ALT_SYSMGR_PINMUX_FLSHIO1_s
11408{
11409 uint32_t sel : 2; /* sdmmc_pwren Mux Selection Field */
11410 uint32_t : 30; /* *UNDEFINED* */
11411};
11412
11413/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO1. */
11414typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO1_s ALT_SYSMGR_PINMUX_FLSHIO1_t;
11415#endif /* __ASSEMBLY__ */
11416
11417/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO1 register from the beginning of the component. */
11418#define ALT_SYSMGR_PINMUX_FLSHIO1_OFST 0x54
11419
11420/*
11421 * Register : sdmmc_d0 Mux Selection Register - FLASHIO2
11422 *
11423 * This register is used to control the peripherals connected to sdmmc_d0
11424 *
11425 * Only reset by a cold reset (ignores warm reset).
11426 *
11427 * NOTE: These registers should not be modified after IO configuration.There is no
11428 * support for dynamically changing the Pin Mux selections.
11429 *
11430 * Register Layout
11431 *
11432 * Bits | Access | Reset | Description
11433 * :-------|:-------|:------|:-----------------------------
11434 * [1:0] | RW | 0x0 | sdmmc_d0 Mux Selection Field
11435 * [31:2] | ??? | 0x0 | *UNDEFINED*
11436 *
11437 */
11438/*
11439 * Field : sdmmc_d0 Mux Selection Field - sel
11440 *
11441 * Select peripheral signals connected sdmmc_d0.
11442 *
11443 * 0 : Pin is connected to GPIO/LoanIO number 38.
11444 *
11445 * 1 : Pin is connected to Peripheral signal not applicable.
11446 *
11447 * 2 : Pin is connected to Peripheral signal USB0.D2.
11448 *
11449 * 3 : Pin is connected to Peripheral signal SDMMC.D0.
11450 *
11451 * Field Access Macros:
11452 *
11453 */
11454/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */
11455#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_LSB 0
11456/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */
11457#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_MSB 1
11458/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */
11459#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_WIDTH 2
11460/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value. */
11461#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET_MSK 0x00000003
11462/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value. */
11463#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_CLR_MSK 0xfffffffc
11464/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */
11465#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_RESET 0x0
11466/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO2_SEL field value from a register. */
11467#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
11468/* Produces a ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value suitable for setting the register. */
11469#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET(value) (((value) << 0) & 0x00000003)
11470
11471#ifndef __ASSEMBLY__
11472/*
11473 * WARNING: The C register and register group struct declarations are provided for
11474 * convenience and illustrative purposes. They should, however, be used with
11475 * caution as the C language standard provides no guarantees about the alignment or
11476 * atomicity of device memory accesses. The recommended practice for writing
11477 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11478 * alt_write_word() functions.
11479 *
11480 * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO2.
11481 */
11482 struct ALT_SYSMGR_PINMUX_FLSHIO2_s
11483{
11484 uint32_t sel : 2; /* sdmmc_d0 Mux Selection Field */
11485 uint32_t : 30; /* *UNDEFINED* */
11486};
11487
11488/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO2. */
11489typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO2_s ALT_SYSMGR_PINMUX_FLSHIO2_t;
11490#endif /* __ASSEMBLY__ */
11491
11492/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO2 register from the beginning of the component. */
11493#define ALT_SYSMGR_PINMUX_FLSHIO2_OFST 0x58
11494
11495/*
11496 * Register : sdmmc_d1 Mux Selection Register - FLASHIO3
11497 *
11498 * This register is used to control the peripherals connected to sdmmc_d1
11499 *
11500 * Only reset by a cold reset (ignores warm reset).
11501 *
11502 * NOTE: These registers should not be modified after IO configuration.There is no
11503 * support for dynamically changing the Pin Mux selections.
11504 *
11505 * Register Layout
11506 *
11507 * Bits | Access | Reset | Description
11508 * :-------|:-------|:------|:-----------------------------
11509 * [1:0] | RW | 0x0 | sdmmc_d1 Mux Selection Field
11510 * [31:2] | ??? | 0x0 | *UNDEFINED*
11511 *
11512 */
11513/*
11514 * Field : sdmmc_d1 Mux Selection Field - sel
11515 *
11516 * Select peripheral signals connected sdmmc_d1.
11517 *
11518 * 0 : Pin is connected to GPIO/LoanIO number 39.
11519 *
11520 * 1 : Pin is connected to Peripheral signal not applicable.
11521 *
11522 * 2 : Pin is connected to Peripheral signal USB0.D3.
11523 *
11524 * 3 : Pin is connected to Peripheral signal SDMMC.D1.
11525 *
11526 * Field Access Macros:
11527 *
11528 */
11529/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */
11530#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_LSB 0
11531/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */
11532#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_MSB 1
11533/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */
11534#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_WIDTH 2
11535/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value. */
11536#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET_MSK 0x00000003
11537/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value. */
11538#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_CLR_MSK 0xfffffffc
11539/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */
11540#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_RESET 0x0
11541/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO3_SEL field value from a register. */
11542#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
11543/* Produces a ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value suitable for setting the register. */
11544#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET(value) (((value) << 0) & 0x00000003)
11545
11546#ifndef __ASSEMBLY__
11547/*
11548 * WARNING: The C register and register group struct declarations are provided for
11549 * convenience and illustrative purposes. They should, however, be used with
11550 * caution as the C language standard provides no guarantees about the alignment or
11551 * atomicity of device memory accesses. The recommended practice for writing
11552 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11553 * alt_write_word() functions.
11554 *
11555 * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO3.
11556 */
11557 struct ALT_SYSMGR_PINMUX_FLSHIO3_s
11558{
11559 uint32_t sel : 2; /* sdmmc_d1 Mux Selection Field */
11560 uint32_t : 30; /* *UNDEFINED* */
11561};
11562
11563/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO3. */
11564typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO3_s ALT_SYSMGR_PINMUX_FLSHIO3_t;
11565#endif /* __ASSEMBLY__ */
11566
11567/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO3 register from the beginning of the component. */
11568#define ALT_SYSMGR_PINMUX_FLSHIO3_OFST 0x5c
11569
11570/*
11571 * Register : sdmmc_d4 Mux Selection Register - FLASHIO4
11572 *
11573 * This register is used to control the peripherals connected to sdmmc_d4
11574 *
11575 * Only reset by a cold reset (ignores warm reset).
11576 *
11577 * NOTE: These registers should not be modified after IO configuration.There is no
11578 * support for dynamically changing the Pin Mux selections.
11579 *
11580 * Register Layout
11581 *
11582 * Bits | Access | Reset | Description
11583 * :-------|:-------|:------|:-----------------------------
11584 * [1:0] | RW | 0x0 | sdmmc_d4 Mux Selection Field
11585 * [31:2] | ??? | 0x0 | *UNDEFINED*
11586 *
11587 */
11588/*
11589 * Field : sdmmc_d4 Mux Selection Field - sel
11590 *
11591 * Select peripheral signals connected sdmmc_d4.
11592 *
11593 * 0 : Pin is connected to GPIO/LoanIO number 40.
11594 *
11595 * 1 : Pin is connected to Peripheral signal not applicable.
11596 *
11597 * 2 : Pin is connected to Peripheral signal USB0.D4.
11598 *
11599 * 3 : Pin is connected to Peripheral signal SDMMC.D4.
11600 *
11601 * Field Access Macros:
11602 *
11603 */
11604/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */
11605#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_LSB 0
11606/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */
11607#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_MSB 1
11608/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */
11609#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_WIDTH 2
11610/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value. */
11611#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET_MSK 0x00000003
11612/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value. */
11613#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_CLR_MSK 0xfffffffc
11614/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */
11615#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_RESET 0x0
11616/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO4_SEL field value from a register. */
11617#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
11618/* Produces a ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value suitable for setting the register. */
11619#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET(value) (((value) << 0) & 0x00000003)
11620
11621#ifndef __ASSEMBLY__
11622/*
11623 * WARNING: The C register and register group struct declarations are provided for
11624 * convenience and illustrative purposes. They should, however, be used with
11625 * caution as the C language standard provides no guarantees about the alignment or
11626 * atomicity of device memory accesses. The recommended practice for writing
11627 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11628 * alt_write_word() functions.
11629 *
11630 * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO4.
11631 */
11632 struct ALT_SYSMGR_PINMUX_FLSHIO4_s
11633{
11634 uint32_t sel : 2; /* sdmmc_d4 Mux Selection Field */
11635 uint32_t : 30; /* *UNDEFINED* */
11636};
11637
11638/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO4. */
11639typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO4_s ALT_SYSMGR_PINMUX_FLSHIO4_t;
11640#endif /* __ASSEMBLY__ */
11641
11642/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO4 register from the beginning of the component. */
11643#define ALT_SYSMGR_PINMUX_FLSHIO4_OFST 0x60
11644
11645/*
11646 * Register : sdmmc_d5 Mux Selection Register - FLASHIO5
11647 *
11648 * This register is used to control the peripherals connected to sdmmc_d5
11649 *
11650 * Only reset by a cold reset (ignores warm reset).
11651 *
11652 * NOTE: These registers should not be modified after IO configuration.There is no
11653 * support for dynamically changing the Pin Mux selections.
11654 *
11655 * Register Layout
11656 *
11657 * Bits | Access | Reset | Description
11658 * :-------|:-------|:------|:-----------------------------
11659 * [1:0] | RW | 0x0 | sdmmc_d5 Mux Selection Field
11660 * [31:2] | ??? | 0x0 | *UNDEFINED*
11661 *
11662 */
11663/*
11664 * Field : sdmmc_d5 Mux Selection Field - sel
11665 *
11666 * Select peripheral signals connected sdmmc_d5.
11667 *
11668 * 0 : Pin is connected to GPIO/LoanIO number 41.
11669 *
11670 * 1 : Pin is connected to Peripheral signal not applicable.
11671 *
11672 * 2 : Pin is connected to Peripheral signal USB0.D5.
11673 *
11674 * 3 : Pin is connected to Peripheral signal SDMMC.D5.
11675 *
11676 * Field Access Macros:
11677 *
11678 */
11679/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */
11680#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_LSB 0
11681/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */
11682#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_MSB 1
11683/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */
11684#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_WIDTH 2
11685/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value. */
11686#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET_MSK 0x00000003
11687/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value. */
11688#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_CLR_MSK 0xfffffffc
11689/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */
11690#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_RESET 0x0
11691/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO5_SEL field value from a register. */
11692#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
11693/* Produces a ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value suitable for setting the register. */
11694#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET(value) (((value) << 0) & 0x00000003)
11695
11696#ifndef __ASSEMBLY__
11697/*
11698 * WARNING: The C register and register group struct declarations are provided for
11699 * convenience and illustrative purposes. They should, however, be used with
11700 * caution as the C language standard provides no guarantees about the alignment or
11701 * atomicity of device memory accesses. The recommended practice for writing
11702 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11703 * alt_write_word() functions.
11704 *
11705 * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO5.
11706 */
11707 struct ALT_SYSMGR_PINMUX_FLSHIO5_s
11708{
11709 uint32_t sel : 2; /* sdmmc_d5 Mux Selection Field */
11710 uint32_t : 30; /* *UNDEFINED* */
11711};
11712
11713/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO5. */
11714typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO5_s ALT_SYSMGR_PINMUX_FLSHIO5_t;
11715#endif /* __ASSEMBLY__ */
11716
11717/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO5 register from the beginning of the component. */
11718#define ALT_SYSMGR_PINMUX_FLSHIO5_OFST 0x64
11719
11720/*
11721 * Register : sdmmc_d6 Mux Selection Register - FLASHIO6
11722 *
11723 * This register is used to control the peripherals connected to sdmmc_d6
11724 *
11725 * Only reset by a cold reset (ignores warm reset).
11726 *
11727 * NOTE: These registers should not be modified after IO configuration.There is no
11728 * support for dynamically changing the Pin Mux selections.
11729 *
11730 * Register Layout
11731 *
11732 * Bits | Access | Reset | Description
11733 * :-------|:-------|:------|:-----------------------------
11734 * [1:0] | RW | 0x0 | sdmmc_d6 Mux Selection Field
11735 * [31:2] | ??? | 0x0 | *UNDEFINED*
11736 *
11737 */
11738/*
11739 * Field : sdmmc_d6 Mux Selection Field - sel
11740 *
11741 * Select peripheral signals connected sdmmc_d6.
11742 *
11743 * 0 : Pin is connected to GPIO/LoanIO number 42.
11744 *
11745 * 1 : Pin is connected to Peripheral signal not applicable.
11746 *
11747 * 2 : Pin is connected to Peripheral signal USB0.D6.
11748 *
11749 * 3 : Pin is connected to Peripheral signal SDMMC.D6.
11750 *
11751 * Field Access Macros:
11752 *
11753 */
11754/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */
11755#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_LSB 0
11756/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */
11757#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_MSB 1
11758/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */
11759#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_WIDTH 2
11760/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value. */
11761#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET_MSK 0x00000003
11762/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value. */
11763#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_CLR_MSK 0xfffffffc
11764/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */
11765#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_RESET 0x0
11766/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO6_SEL field value from a register. */
11767#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
11768/* Produces a ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value suitable for setting the register. */
11769#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET(value) (((value) << 0) & 0x00000003)
11770
11771#ifndef __ASSEMBLY__
11772/*
11773 * WARNING: The C register and register group struct declarations are provided for
11774 * convenience and illustrative purposes. They should, however, be used with
11775 * caution as the C language standard provides no guarantees about the alignment or
11776 * atomicity of device memory accesses. The recommended practice for writing
11777 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11778 * alt_write_word() functions.
11779 *
11780 * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO6.
11781 */
11782 struct ALT_SYSMGR_PINMUX_FLSHIO6_s
11783{
11784 uint32_t sel : 2; /* sdmmc_d6 Mux Selection Field */
11785 uint32_t : 30; /* *UNDEFINED* */
11786};
11787
11788/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO6. */
11789typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO6_s ALT_SYSMGR_PINMUX_FLSHIO6_t;
11790#endif /* __ASSEMBLY__ */
11791
11792/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO6 register from the beginning of the component. */
11793#define ALT_SYSMGR_PINMUX_FLSHIO6_OFST 0x68
11794
11795/*
11796 * Register : sdmmc_d7 Mux Selection Register - FLASHIO7
11797 *
11798 * This register is used to control the peripherals connected to sdmmc_d7
11799 *
11800 * Only reset by a cold reset (ignores warm reset).
11801 *
11802 * NOTE: These registers should not be modified after IO configuration.There is no
11803 * support for dynamically changing the Pin Mux selections.
11804 *
11805 * Register Layout
11806 *
11807 * Bits | Access | Reset | Description
11808 * :-------|:-------|:------|:-----------------------------
11809 * [1:0] | RW | 0x0 | sdmmc_d7 Mux Selection Field
11810 * [31:2] | ??? | 0x0 | *UNDEFINED*
11811 *
11812 */
11813/*
11814 * Field : sdmmc_d7 Mux Selection Field - sel
11815 *
11816 * Select peripheral signals connected sdmmc_d7.
11817 *
11818 * 0 : Pin is connected to GPIO/LoanIO number 43.
11819 *
11820 * 1 : Pin is connected to Peripheral signal not applicable.
11821 *
11822 * 2 : Pin is connected to Peripheral signal USB0.D7.
11823 *
11824 * 3 : Pin is connected to Peripheral signal SDMMC.D7.
11825 *
11826 * Field Access Macros:
11827 *
11828 */
11829/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */
11830#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_LSB 0
11831/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */
11832#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_MSB 1
11833/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */
11834#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_WIDTH 2
11835/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value. */
11836#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET_MSK 0x00000003
11837/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value. */
11838#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_CLR_MSK 0xfffffffc
11839/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */
11840#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_RESET 0x0
11841/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO7_SEL field value from a register. */
11842#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
11843/* Produces a ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value suitable for setting the register. */
11844#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET(value) (((value) << 0) & 0x00000003)
11845
11846#ifndef __ASSEMBLY__
11847/*
11848 * WARNING: The C register and register group struct declarations are provided for
11849 * convenience and illustrative purposes. They should, however, be used with
11850 * caution as the C language standard provides no guarantees about the alignment or
11851 * atomicity of device memory accesses. The recommended practice for writing
11852 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11853 * alt_write_word() functions.
11854 *
11855 * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO7.
11856 */
11857 struct ALT_SYSMGR_PINMUX_FLSHIO7_s
11858{
11859 uint32_t sel : 2; /* sdmmc_d7 Mux Selection Field */
11860 uint32_t : 30; /* *UNDEFINED* */
11861};
11862
11863/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO7. */
11864typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO7_s ALT_SYSMGR_PINMUX_FLSHIO7_t;
11865#endif /* __ASSEMBLY__ */
11866
11867/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO7 register from the beginning of the component. */
11868#define ALT_SYSMGR_PINMUX_FLSHIO7_OFST 0x6c
11869
11870/*
11871 * Register : sdmmc_clk_in Mux Selection Register - FLASHIO8
11872 *
11873 * This register is used to control the peripherals connected to sdmmc_clk_in
11874 *
11875 * Only reset by a cold reset (ignores warm reset).
11876 *
11877 * NOTE: These registers should not be modified after IO configuration.There is no
11878 * support for dynamically changing the Pin Mux selections.
11879 *
11880 * Register Layout
11881 *
11882 * Bits | Access | Reset | Description
11883 * :-------|:-------|:------|:---------------------------------
11884 * [1:0] | RW | 0x0 | sdmmc_clk_in Mux Selection Field
11885 * [31:2] | ??? | 0x0 | *UNDEFINED*
11886 *
11887 */
11888/*
11889 * Field : sdmmc_clk_in Mux Selection Field - sel
11890 *
11891 * Select peripheral signals connected sdmmc_clk_in.
11892 *
11893 * 0 : Pin is connected to GPIO/LoanIO number 44.
11894 *
11895 * 1 : Pin is connected to Peripheral signal not applicable.
11896 *
11897 * 2 : Pin is connected to Peripheral signal USB0.CLK.
11898 *
11899 * 3 : Pin is connected to Peripheral signal SDMMC.CLK_IN.
11900 *
11901 * Field Access Macros:
11902 *
11903 */
11904/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */
11905#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_LSB 0
11906/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */
11907#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_MSB 1
11908/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */
11909#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_WIDTH 2
11910/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value. */
11911#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET_MSK 0x00000003
11912/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value. */
11913#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_CLR_MSK 0xfffffffc
11914/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */
11915#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_RESET 0x0
11916/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO8_SEL field value from a register. */
11917#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
11918/* Produces a ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value suitable for setting the register. */
11919#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET(value) (((value) << 0) & 0x00000003)
11920
11921#ifndef __ASSEMBLY__
11922/*
11923 * WARNING: The C register and register group struct declarations are provided for
11924 * convenience and illustrative purposes. They should, however, be used with
11925 * caution as the C language standard provides no guarantees about the alignment or
11926 * atomicity of device memory accesses. The recommended practice for writing
11927 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11928 * alt_write_word() functions.
11929 *
11930 * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO8.
11931 */
11932 struct ALT_SYSMGR_PINMUX_FLSHIO8_s
11933{
11934 uint32_t sel : 2; /* sdmmc_clk_in Mux Selection Field */
11935 uint32_t : 30; /* *UNDEFINED* */
11936};
11937
11938/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO8. */
11939typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO8_s ALT_SYSMGR_PINMUX_FLSHIO8_t;
11940#endif /* __ASSEMBLY__ */
11941
11942/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO8 register from the beginning of the component. */
11943#define ALT_SYSMGR_PINMUX_FLSHIO8_OFST 0x70
11944
11945/*
11946 * Register : sdmmc_clk Mux Selection Register - FLASHIO9
11947 *
11948 * This register is used to control the peripherals connected to sdmmc_clk
11949 *
11950 * Only reset by a cold reset (ignores warm reset).
11951 *
11952 * NOTE: These registers should not be modified after IO configuration.There is no
11953 * support for dynamically changing the Pin Mux selections.
11954 *
11955 * Register Layout
11956 *
11957 * Bits | Access | Reset | Description
11958 * :-------|:-------|:------|:------------------------------
11959 * [1:0] | RW | 0x0 | sdmmc_clk Mux Selection Field
11960 * [31:2] | ??? | 0x0 | *UNDEFINED*
11961 *
11962 */
11963/*
11964 * Field : sdmmc_clk Mux Selection Field - sel
11965 *
11966 * Select peripheral signals connected sdmmc_clk.
11967 *
11968 * 0 : Pin is connected to GPIO/LoanIO number 45.
11969 *
11970 * 1 : Pin is connected to Peripheral signal not applicable.
11971 *
11972 * 2 : Pin is connected to Peripheral signal USB0.STP.
11973 *
11974 * 3 : Pin is connected to Peripheral signal SDMMC.CLK.
11975 *
11976 * Field Access Macros:
11977 *
11978 */
11979/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */
11980#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_LSB 0
11981/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */
11982#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_MSB 1
11983/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */
11984#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_WIDTH 2
11985/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value. */
11986#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET_MSK 0x00000003
11987/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value. */
11988#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_CLR_MSK 0xfffffffc
11989/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */
11990#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_RESET 0x0
11991/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO9_SEL field value from a register. */
11992#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
11993/* Produces a ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value suitable for setting the register. */
11994#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET(value) (((value) << 0) & 0x00000003)
11995
11996#ifndef __ASSEMBLY__
11997/*
11998 * WARNING: The C register and register group struct declarations are provided for
11999 * convenience and illustrative purposes. They should, however, be used with
12000 * caution as the C language standard provides no guarantees about the alignment or
12001 * atomicity of device memory accesses. The recommended practice for writing
12002 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12003 * alt_write_word() functions.
12004 *
12005 * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO9.
12006 */
12007 struct ALT_SYSMGR_PINMUX_FLSHIO9_s
12008{
12009 uint32_t sel : 2; /* sdmmc_clk Mux Selection Field */
12010 uint32_t : 30; /* *UNDEFINED* */
12011};
12012
12013/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO9. */
12014typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO9_s ALT_SYSMGR_PINMUX_FLSHIO9_t;
12015#endif /* __ASSEMBLY__ */
12016
12017/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO9 register from the beginning of the component. */
12018#define ALT_SYSMGR_PINMUX_FLSHIO9_OFST 0x74
12019
12020/*
12021 * Register : sdmmc_d2 Mux Selection Register - FLASHIO10
12022 *
12023 * This register is used to control the peripherals connected to sdmmc_d2
12024 *
12025 * Only reset by a cold reset (ignores warm reset).
12026 *
12027 * NOTE: These registers should not be modified after IO configuration.There is no
12028 * support for dynamically changing the Pin Mux selections.
12029 *
12030 * Register Layout
12031 *
12032 * Bits | Access | Reset | Description
12033 * :-------|:-------|:------|:-----------------------------
12034 * [1:0] | RW | 0x0 | sdmmc_d2 Mux Selection Field
12035 * [31:2] | ??? | 0x0 | *UNDEFINED*
12036 *
12037 */
12038/*
12039 * Field : sdmmc_d2 Mux Selection Field - sel
12040 *
12041 * Select peripheral signals connected sdmmc_d2.
12042 *
12043 * 0 : Pin is connected to GPIO/LoanIO number 46.
12044 *
12045 * 1 : Pin is connected to Peripheral signal not applicable.
12046 *
12047 * 2 : Pin is connected to Peripheral signal USB0.DIR.
12048 *
12049 * 3 : Pin is connected to Peripheral signal SDMMC.D2.
12050 *
12051 * Field Access Macros:
12052 *
12053 */
12054/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */
12055#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_LSB 0
12056/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */
12057#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_MSB 1
12058/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */
12059#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_WIDTH 2
12060/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value. */
12061#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET_MSK 0x00000003
12062/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value. */
12063#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_CLR_MSK 0xfffffffc
12064/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */
12065#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_RESET 0x0
12066/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO10_SEL field value from a register. */
12067#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
12068/* Produces a ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value suitable for setting the register. */
12069#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET(value) (((value) << 0) & 0x00000003)
12070
12071#ifndef __ASSEMBLY__
12072/*
12073 * WARNING: The C register and register group struct declarations are provided for
12074 * convenience and illustrative purposes. They should, however, be used with
12075 * caution as the C language standard provides no guarantees about the alignment or
12076 * atomicity of device memory accesses. The recommended practice for writing
12077 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12078 * alt_write_word() functions.
12079 *
12080 * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO10.
12081 */
12082 struct ALT_SYSMGR_PINMUX_FLSHIO10_s
12083{
12084 uint32_t sel : 2; /* sdmmc_d2 Mux Selection Field */
12085 uint32_t : 30; /* *UNDEFINED* */
12086};
12087
12088/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO10. */
12089typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO10_s ALT_SYSMGR_PINMUX_FLSHIO10_t;
12090#endif /* __ASSEMBLY__ */
12091
12092/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO10 register from the beginning of the component. */
12093#define ALT_SYSMGR_PINMUX_FLSHIO10_OFST 0x78
12094
12095/*
12096 * Register : sdmmc_d3 Mux Selection Register - FLASHIO11
12097 *
12098 * This register is used to control the peripherals connected to sdmmc_d3
12099 *
12100 * Only reset by a cold reset (ignores warm reset).
12101 *
12102 * NOTE: These registers should not be modified after IO configuration.There is no
12103 * support for dynamically changing the Pin Mux selections.
12104 *
12105 * Register Layout
12106 *
12107 * Bits | Access | Reset | Description
12108 * :-------|:-------|:------|:-----------------------------
12109 * [1:0] | RW | 0x0 | sdmmc_d3 Mux Selection Field
12110 * [31:2] | ??? | 0x0 | *UNDEFINED*
12111 *
12112 */
12113/*
12114 * Field : sdmmc_d3 Mux Selection Field - sel
12115 *
12116 * Select peripheral signals connected sdmmc_d3.
12117 *
12118 * 0 : Pin is connected to GPIO/LoanIO number 47.
12119 *
12120 * 1 : Pin is connected to Peripheral signal not applicable.
12121 *
12122 * 2 : Pin is connected to Peripheral signal USB0.NXT.
12123 *
12124 * 3 : Pin is connected to Peripheral signal SDMMC.D3.
12125 *
12126 * Field Access Macros:
12127 *
12128 */
12129/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */
12130#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_LSB 0
12131/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */
12132#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_MSB 1
12133/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */
12134#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_WIDTH 2
12135/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value. */
12136#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET_MSK 0x00000003
12137/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value. */
12138#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_CLR_MSK 0xfffffffc
12139/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */
12140#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_RESET 0x0
12141/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO11_SEL field value from a register. */
12142#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
12143/* Produces a ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value suitable for setting the register. */
12144#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET(value) (((value) << 0) & 0x00000003)
12145
12146#ifndef __ASSEMBLY__
12147/*
12148 * WARNING: The C register and register group struct declarations are provided for
12149 * convenience and illustrative purposes. They should, however, be used with
12150 * caution as the C language standard provides no guarantees about the alignment or
12151 * atomicity of device memory accesses. The recommended practice for writing
12152 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12153 * alt_write_word() functions.
12154 *
12155 * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO11.
12156 */
12157 struct ALT_SYSMGR_PINMUX_FLSHIO11_s
12158{
12159 uint32_t sel : 2; /* sdmmc_d3 Mux Selection Field */
12160 uint32_t : 30; /* *UNDEFINED* */
12161};
12162
12163/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO11. */
12164typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO11_s ALT_SYSMGR_PINMUX_FLSHIO11_t;
12165#endif /* __ASSEMBLY__ */
12166
12167/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO11 register from the beginning of the component. */
12168#define ALT_SYSMGR_PINMUX_FLSHIO11_OFST 0x7c
12169
12170/*
12171 * Register : trace_clk Mux Selection Register - GENERALIO0
12172 *
12173 * This register is used to control the peripherals connected to trace_clk
12174 *
12175 * Only reset by a cold reset (ignores warm reset).
12176 *
12177 * NOTE: These registers should not be modified after IO configuration.There is no
12178 * support for dynamically changing the Pin Mux selections.
12179 *
12180 * Register Layout
12181 *
12182 * Bits | Access | Reset | Description
12183 * :-------|:-------|:------|:------------------------------
12184 * [1:0] | RW | 0x0 | trace_clk Mux Selection Field
12185 * [31:2] | ??? | 0x0 | *UNDEFINED*
12186 *
12187 */
12188/*
12189 * Field : trace_clk Mux Selection Field - sel
12190 *
12191 * Select peripheral signals connected trace_clk.
12192 *
12193 * 0 : Pin is connected to GPIO/LoanIO number 48.
12194 *
12195 * 1 : Pin is connected to Peripheral signal not applicable.
12196 *
12197 * 2 : Pin is connected to Peripheral signal not applicable.
12198 *
12199 * 3 : Pin is connected to Peripheral signal TRACE.CLK.
12200 *
12201 * Field Access Macros:
12202 *
12203 */
12204/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */
12205#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_LSB 0
12206/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */
12207#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_MSB 1
12208/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */
12209#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_WIDTH 2
12210/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value. */
12211#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET_MSK 0x00000003
12212/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value. */
12213#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_CLR_MSK 0xfffffffc
12214/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */
12215#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_RESET 0x0
12216/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO0_SEL field value from a register. */
12217#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
12218/* Produces a ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value suitable for setting the register. */
12219#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET(value) (((value) << 0) & 0x00000003)
12220
12221#ifndef __ASSEMBLY__
12222/*
12223 * WARNING: The C register and register group struct declarations are provided for
12224 * convenience and illustrative purposes. They should, however, be used with
12225 * caution as the C language standard provides no guarantees about the alignment or
12226 * atomicity of device memory accesses. The recommended practice for writing
12227 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12228 * alt_write_word() functions.
12229 *
12230 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO0.
12231 */
12232 struct ALT_SYSMGR_PINMUX_GENERALIO0_s
12233{
12234 uint32_t sel : 2; /* trace_clk Mux Selection Field */
12235 uint32_t : 30; /* *UNDEFINED* */
12236};
12237
12238/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO0. */
12239typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO0_s ALT_SYSMGR_PINMUX_GENERALIO0_t;
12240#endif /* __ASSEMBLY__ */
12241
12242/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO0 register from the beginning of the component. */
12243#define ALT_SYSMGR_PINMUX_GENERALIO0_OFST 0x80
12244
12245/*
12246 * Register : trace_d0 Mux Selection Register - GENERALIO1
12247 *
12248 * This register is used to control the peripherals connected to trace_d0
12249 *
12250 * Only reset by a cold reset (ignores warm reset).
12251 *
12252 * NOTE: These registers should not be modified after IO configuration.There is no
12253 * support for dynamically changing the Pin Mux selections.
12254 *
12255 * Register Layout
12256 *
12257 * Bits | Access | Reset | Description
12258 * :-------|:-------|:------|:-----------------------------
12259 * [1:0] | RW | 0x0 | trace_d0 Mux Selection Field
12260 * [31:2] | ??? | 0x0 | *UNDEFINED*
12261 *
12262 */
12263/*
12264 * Field : trace_d0 Mux Selection Field - sel
12265 *
12266 * Select peripheral signals connected trace_d0.
12267 *
12268 * 0 : Pin is connected to GPIO/LoanIO number 49.
12269 *
12270 * 1 : Pin is connected to Peripheral signal UART0.RX.
12271 *
12272 * 2 : Pin is connected to Peripheral signal SPIS0.CLK.
12273 *
12274 * 3 : Pin is connected to Peripheral signal TRACE.D0.
12275 *
12276 * Field Access Macros:
12277 *
12278 */
12279/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */
12280#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_LSB 0
12281/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */
12282#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_MSB 1
12283/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */
12284#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_WIDTH 2
12285/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value. */
12286#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET_MSK 0x00000003
12287/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value. */
12288#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_CLR_MSK 0xfffffffc
12289/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */
12290#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_RESET 0x0
12291/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO1_SEL field value from a register. */
12292#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
12293/* Produces a ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value suitable for setting the register. */
12294#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET(value) (((value) << 0) & 0x00000003)
12295
12296#ifndef __ASSEMBLY__
12297/*
12298 * WARNING: The C register and register group struct declarations are provided for
12299 * convenience and illustrative purposes. They should, however, be used with
12300 * caution as the C language standard provides no guarantees about the alignment or
12301 * atomicity of device memory accesses. The recommended practice for writing
12302 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12303 * alt_write_word() functions.
12304 *
12305 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO1.
12306 */
12307 struct ALT_SYSMGR_PINMUX_GENERALIO1_s
12308{
12309 uint32_t sel : 2; /* trace_d0 Mux Selection Field */
12310 uint32_t : 30; /* *UNDEFINED* */
12311};
12312
12313/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO1. */
12314typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO1_s ALT_SYSMGR_PINMUX_GENERALIO1_t;
12315#endif /* __ASSEMBLY__ */
12316
12317/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO1 register from the beginning of the component. */
12318#define ALT_SYSMGR_PINMUX_GENERALIO1_OFST 0x84
12319
12320/*
12321 * Register : trace_d1 Mux Selection Register - GENERALIO2
12322 *
12323 * This register is used to control the peripherals connected to trace_d1
12324 *
12325 * Only reset by a cold reset (ignores warm reset).
12326 *
12327 * NOTE: These registers should not be modified after IO configuration.There is no
12328 * support for dynamically changing the Pin Mux selections.
12329 *
12330 * Register Layout
12331 *
12332 * Bits | Access | Reset | Description
12333 * :-------|:-------|:------|:-----------------------------
12334 * [1:0] | RW | 0x0 | trace_d1 Mux Selection Field
12335 * [31:2] | ??? | 0x0 | *UNDEFINED*
12336 *
12337 */
12338/*
12339 * Field : trace_d1 Mux Selection Field - sel
12340 *
12341 * Select peripheral signals connected trace_d1.
12342 *
12343 * 0 : Pin is connected to GPIO/LoanIO number 50.
12344 *
12345 * 1 : Pin is connected to Peripheral signal UART0.TX.
12346 *
12347 * 2 : Pin is connected to Peripheral signal SPIS0.MOSI.
12348 *
12349 * 3 : Pin is connected to Peripheral signal TRACE.D1.
12350 *
12351 * Field Access Macros:
12352 *
12353 */
12354/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */
12355#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_LSB 0
12356/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */
12357#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_MSB 1
12358/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */
12359#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_WIDTH 2
12360/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value. */
12361#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET_MSK 0x00000003
12362/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value. */
12363#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_CLR_MSK 0xfffffffc
12364/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */
12365#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_RESET 0x0
12366/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO2_SEL field value from a register. */
12367#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
12368/* Produces a ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value suitable for setting the register. */
12369#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET(value) (((value) << 0) & 0x00000003)
12370
12371#ifndef __ASSEMBLY__
12372/*
12373 * WARNING: The C register and register group struct declarations are provided for
12374 * convenience and illustrative purposes. They should, however, be used with
12375 * caution as the C language standard provides no guarantees about the alignment or
12376 * atomicity of device memory accesses. The recommended practice for writing
12377 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12378 * alt_write_word() functions.
12379 *
12380 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO2.
12381 */
12382 struct ALT_SYSMGR_PINMUX_GENERALIO2_s
12383{
12384 uint32_t sel : 2; /* trace_d1 Mux Selection Field */
12385 uint32_t : 30; /* *UNDEFINED* */
12386};
12387
12388/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO2. */
12389typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO2_s ALT_SYSMGR_PINMUX_GENERALIO2_t;
12390#endif /* __ASSEMBLY__ */
12391
12392/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO2 register from the beginning of the component. */
12393#define ALT_SYSMGR_PINMUX_GENERALIO2_OFST 0x88
12394
12395/*
12396 * Register : trace_d2 Mux Selection Register - GENERALIO3
12397 *
12398 * This register is used to control the peripherals connected to trace_d2
12399 *
12400 * Only reset by a cold reset (ignores warm reset).
12401 *
12402 * NOTE: These registers should not be modified after IO configuration.There is no
12403 * support for dynamically changing the Pin Mux selections.
12404 *
12405 * Register Layout
12406 *
12407 * Bits | Access | Reset | Description
12408 * :-------|:-------|:------|:-----------------------------
12409 * [1:0] | RW | 0x0 | trace_d2 Mux Selection Field
12410 * [31:2] | ??? | 0x0 | *UNDEFINED*
12411 *
12412 */
12413/*
12414 * Field : trace_d2 Mux Selection Field - sel
12415 *
12416 * Select peripheral signals connected trace_d2.
12417 *
12418 * 0 : Pin is connected to GPIO/LoanIO number 51.
12419 *
12420 * 1 : Pin is connected to Peripheral signal I2C1.SDA.
12421 *
12422 * 2 : Pin is connected to Peripheral signal SPIS0.MISO.
12423 *
12424 * 3 : Pin is connected to Peripheral signal TRACE.D2.
12425 *
12426 * Field Access Macros:
12427 *
12428 */
12429/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */
12430#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_LSB 0
12431/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */
12432#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_MSB 1
12433/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */
12434#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_WIDTH 2
12435/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value. */
12436#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET_MSK 0x00000003
12437/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value. */
12438#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_CLR_MSK 0xfffffffc
12439/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */
12440#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_RESET 0x0
12441/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO3_SEL field value from a register. */
12442#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
12443/* Produces a ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value suitable for setting the register. */
12444#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET(value) (((value) << 0) & 0x00000003)
12445
12446#ifndef __ASSEMBLY__
12447/*
12448 * WARNING: The C register and register group struct declarations are provided for
12449 * convenience and illustrative purposes. They should, however, be used with
12450 * caution as the C language standard provides no guarantees about the alignment or
12451 * atomicity of device memory accesses. The recommended practice for writing
12452 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12453 * alt_write_word() functions.
12454 *
12455 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO3.
12456 */
12457 struct ALT_SYSMGR_PINMUX_GENERALIO3_s
12458{
12459 uint32_t sel : 2; /* trace_d2 Mux Selection Field */
12460 uint32_t : 30; /* *UNDEFINED* */
12461};
12462
12463/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO3. */
12464typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO3_s ALT_SYSMGR_PINMUX_GENERALIO3_t;
12465#endif /* __ASSEMBLY__ */
12466
12467/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO3 register from the beginning of the component. */
12468#define ALT_SYSMGR_PINMUX_GENERALIO3_OFST 0x8c
12469
12470/*
12471 * Register : trace_d3 Mux Selection Register - GENERALIO4
12472 *
12473 * This register is used to control the peripherals connected to trace_d3
12474 *
12475 * Only reset by a cold reset (ignores warm reset).
12476 *
12477 * NOTE: These registers should not be modified after IO configuration.There is no
12478 * support for dynamically changing the Pin Mux selections.
12479 *
12480 * Register Layout
12481 *
12482 * Bits | Access | Reset | Description
12483 * :-------|:-------|:------|:-----------------------------
12484 * [1:0] | RW | 0x0 | trace_d3 Mux Selection Field
12485 * [31:2] | ??? | 0x0 | *UNDEFINED*
12486 *
12487 */
12488/*
12489 * Field : trace_d3 Mux Selection Field - sel
12490 *
12491 * Select peripheral signals connected trace_d3.
12492 *
12493 * 0 : Pin is connected to GPIO/LoanIO number 52.
12494 *
12495 * 1 : Pin is connected to Peripheral signal I2C1.SCL.
12496 *
12497 * 2 : Pin is connected to Peripheral signal SPIS0.SS0.
12498 *
12499 * 3 : Pin is connected to Peripheral signal TRACE.D3.
12500 *
12501 * Field Access Macros:
12502 *
12503 */
12504/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */
12505#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_LSB 0
12506/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */
12507#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_MSB 1
12508/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */
12509#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_WIDTH 2
12510/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value. */
12511#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET_MSK 0x00000003
12512/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value. */
12513#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_CLR_MSK 0xfffffffc
12514/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */
12515#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_RESET 0x0
12516/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO4_SEL field value from a register. */
12517#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
12518/* Produces a ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value suitable for setting the register. */
12519#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET(value) (((value) << 0) & 0x00000003)
12520
12521#ifndef __ASSEMBLY__
12522/*
12523 * WARNING: The C register and register group struct declarations are provided for
12524 * convenience and illustrative purposes. They should, however, be used with
12525 * caution as the C language standard provides no guarantees about the alignment or
12526 * atomicity of device memory accesses. The recommended practice for writing
12527 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12528 * alt_write_word() functions.
12529 *
12530 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO4.
12531 */
12532 struct ALT_SYSMGR_PINMUX_GENERALIO4_s
12533{
12534 uint32_t sel : 2; /* trace_d3 Mux Selection Field */
12535 uint32_t : 30; /* *UNDEFINED* */
12536};
12537
12538/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO4. */
12539typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO4_s ALT_SYSMGR_PINMUX_GENERALIO4_t;
12540#endif /* __ASSEMBLY__ */
12541
12542/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO4 register from the beginning of the component. */
12543#define ALT_SYSMGR_PINMUX_GENERALIO4_OFST 0x90
12544
12545/*
12546 * Register : trace_d4 Mux Selection Register - GENERALIO5
12547 *
12548 * This register is used to control the peripherals connected to trace_d4
12549 *
12550 * Only reset by a cold reset (ignores warm reset).
12551 *
12552 * NOTE: These registers should not be modified after IO configuration.There is no
12553 * support for dynamically changing the Pin Mux selections.
12554 *
12555 * Register Layout
12556 *
12557 * Bits | Access | Reset | Description
12558 * :-------|:-------|:------|:-----------------------------
12559 * [1:0] | RW | 0x0 | trace_d4 Mux Selection Field
12560 * [31:2] | ??? | 0x0 | *UNDEFINED*
12561 *
12562 */
12563/*
12564 * Field : trace_d4 Mux Selection Field - sel
12565 *
12566 * Select peripheral signals connected trace_d4.
12567 *
12568 * 0 : Pin is connected to GPIO/LoanIO number 53.
12569 *
12570 * 1 : Pin is connected to Peripheral signal CAN1.RX.
12571 *
12572 * 2 : Pin is connected to Peripheral signal SPIS1.CLK.
12573 *
12574 * 3 : Pin is connected to Peripheral signal TRACE.D4.
12575 *
12576 * Field Access Macros:
12577 *
12578 */
12579/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */
12580#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_LSB 0
12581/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */
12582#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_MSB 1
12583/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */
12584#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_WIDTH 2
12585/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value. */
12586#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET_MSK 0x00000003
12587/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value. */
12588#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_CLR_MSK 0xfffffffc
12589/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */
12590#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_RESET 0x0
12591/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO5_SEL field value from a register. */
12592#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
12593/* Produces a ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value suitable for setting the register. */
12594#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET(value) (((value) << 0) & 0x00000003)
12595
12596#ifndef __ASSEMBLY__
12597/*
12598 * WARNING: The C register and register group struct declarations are provided for
12599 * convenience and illustrative purposes. They should, however, be used with
12600 * caution as the C language standard provides no guarantees about the alignment or
12601 * atomicity of device memory accesses. The recommended practice for writing
12602 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12603 * alt_write_word() functions.
12604 *
12605 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO5.
12606 */
12607 struct ALT_SYSMGR_PINMUX_GENERALIO5_s
12608{
12609 uint32_t sel : 2; /* trace_d4 Mux Selection Field */
12610 uint32_t : 30; /* *UNDEFINED* */
12611};
12612
12613/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO5. */
12614typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO5_s ALT_SYSMGR_PINMUX_GENERALIO5_t;
12615#endif /* __ASSEMBLY__ */
12616
12617/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO5 register from the beginning of the component. */
12618#define ALT_SYSMGR_PINMUX_GENERALIO5_OFST 0x94
12619
12620/*
12621 * Register : trace_d5 Mux Selection Register - GENERALIO6
12622 *
12623 * This register is used to control the peripherals connected to trace_d5
12624 *
12625 * Only reset by a cold reset (ignores warm reset).
12626 *
12627 * NOTE: These registers should not be modified after IO configuration.There is no
12628 * support for dynamically changing the Pin Mux selections.
12629 *
12630 * Register Layout
12631 *
12632 * Bits | Access | Reset | Description
12633 * :-------|:-------|:------|:-----------------------------
12634 * [1:0] | RW | 0x0 | trace_d5 Mux Selection Field
12635 * [31:2] | ??? | 0x0 | *UNDEFINED*
12636 *
12637 */
12638/*
12639 * Field : trace_d5 Mux Selection Field - sel
12640 *
12641 * Select peripheral signals connected trace_d5.
12642 *
12643 * 0 : Pin is connected to GPIO/LoanIO number 54.
12644 *
12645 * 1 : Pin is connected to Peripheral signal CAN1.TX.
12646 *
12647 * 2 : Pin is connected to Peripheral signal SPIS1.MOSI.
12648 *
12649 * 3 : Pin is connected to Peripheral signal TRACE.D5.
12650 *
12651 * Field Access Macros:
12652 *
12653 */
12654/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */
12655#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_LSB 0
12656/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */
12657#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_MSB 1
12658/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */
12659#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_WIDTH 2
12660/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value. */
12661#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET_MSK 0x00000003
12662/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value. */
12663#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_CLR_MSK 0xfffffffc
12664/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */
12665#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_RESET 0x0
12666/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO6_SEL field value from a register. */
12667#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
12668/* Produces a ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value suitable for setting the register. */
12669#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET(value) (((value) << 0) & 0x00000003)
12670
12671#ifndef __ASSEMBLY__
12672/*
12673 * WARNING: The C register and register group struct declarations are provided for
12674 * convenience and illustrative purposes. They should, however, be used with
12675 * caution as the C language standard provides no guarantees about the alignment or
12676 * atomicity of device memory accesses. The recommended practice for writing
12677 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12678 * alt_write_word() functions.
12679 *
12680 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO6.
12681 */
12682 struct ALT_SYSMGR_PINMUX_GENERALIO6_s
12683{
12684 uint32_t sel : 2; /* trace_d5 Mux Selection Field */
12685 uint32_t : 30; /* *UNDEFINED* */
12686};
12687
12688/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO6. */
12689typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO6_s ALT_SYSMGR_PINMUX_GENERALIO6_t;
12690#endif /* __ASSEMBLY__ */
12691
12692/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO6 register from the beginning of the component. */
12693#define ALT_SYSMGR_PINMUX_GENERALIO6_OFST 0x98
12694
12695/*
12696 * Register : trace_d6 Mux Selection Register - GENERALIO7
12697 *
12698 * This register is used to control the peripherals connected to trace_d6
12699 *
12700 * Only reset by a cold reset (ignores warm reset).
12701 *
12702 * NOTE: These registers should not be modified after IO configuration.There is no
12703 * support for dynamically changing the Pin Mux selections.
12704 *
12705 * Register Layout
12706 *
12707 * Bits | Access | Reset | Description
12708 * :-------|:-------|:------|:-----------------------------
12709 * [1:0] | RW | 0x0 | trace_d6 Mux Selection Field
12710 * [31:2] | ??? | 0x0 | *UNDEFINED*
12711 *
12712 */
12713/*
12714 * Field : trace_d6 Mux Selection Field - sel
12715 *
12716 * Select peripheral signals connected trace_d6.
12717 *
12718 * 0 : Pin is connected to GPIO/LoanIO number 55.
12719 *
12720 * 1 : Pin is connected to Peripheral signal I2C0.SDA.
12721 *
12722 * 2 : Pin is connected to Peripheral signal SPIS1.SS0.
12723 *
12724 * 3 : Pin is connected to Peripheral signal TRACE.D6.
12725 *
12726 * Field Access Macros:
12727 *
12728 */
12729/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */
12730#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_LSB 0
12731/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */
12732#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_MSB 1
12733/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */
12734#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_WIDTH 2
12735/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value. */
12736#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET_MSK 0x00000003
12737/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value. */
12738#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_CLR_MSK 0xfffffffc
12739/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */
12740#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_RESET 0x0
12741/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO7_SEL field value from a register. */
12742#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
12743/* Produces a ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value suitable for setting the register. */
12744#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET(value) (((value) << 0) & 0x00000003)
12745
12746#ifndef __ASSEMBLY__
12747/*
12748 * WARNING: The C register and register group struct declarations are provided for
12749 * convenience and illustrative purposes. They should, however, be used with
12750 * caution as the C language standard provides no guarantees about the alignment or
12751 * atomicity of device memory accesses. The recommended practice for writing
12752 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12753 * alt_write_word() functions.
12754 *
12755 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO7.
12756 */
12757 struct ALT_SYSMGR_PINMUX_GENERALIO7_s
12758{
12759 uint32_t sel : 2; /* trace_d6 Mux Selection Field */
12760 uint32_t : 30; /* *UNDEFINED* */
12761};
12762
12763/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO7. */
12764typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO7_s ALT_SYSMGR_PINMUX_GENERALIO7_t;
12765#endif /* __ASSEMBLY__ */
12766
12767/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO7 register from the beginning of the component. */
12768#define ALT_SYSMGR_PINMUX_GENERALIO7_OFST 0x9c
12769
12770/*
12771 * Register : trace_d7 Mux Selection Register - GENERALIO8
12772 *
12773 * This register is used to control the peripherals connected to trace_d7
12774 *
12775 * Only reset by a cold reset (ignores warm reset).
12776 *
12777 * NOTE: These registers should not be modified after IO configuration.There is no
12778 * support for dynamically changing the Pin Mux selections.
12779 *
12780 * Register Layout
12781 *
12782 * Bits | Access | Reset | Description
12783 * :-------|:-------|:------|:-----------------------------
12784 * [1:0] | RW | 0x0 | trace_d7 Mux Selection Field
12785 * [31:2] | ??? | 0x0 | *UNDEFINED*
12786 *
12787 */
12788/*
12789 * Field : trace_d7 Mux Selection Field - sel
12790 *
12791 * Select peripheral signals connected trace_d7.
12792 *
12793 * 0 : Pin is connected to GPIO/LoanIO number 56.
12794 *
12795 * 1 : Pin is connected to Peripheral signal I2C0.SCL.
12796 *
12797 * 2 : Pin is connected to Peripheral signal SPIS1.MISO.
12798 *
12799 * 3 : Pin is connected to Peripheral signal TRACE.D7.
12800 *
12801 * Field Access Macros:
12802 *
12803 */
12804/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */
12805#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_LSB 0
12806/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */
12807#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_MSB 1
12808/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */
12809#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_WIDTH 2
12810/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value. */
12811#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET_MSK 0x00000003
12812/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value. */
12813#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_CLR_MSK 0xfffffffc
12814/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */
12815#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_RESET 0x0
12816/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO8_SEL field value from a register. */
12817#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
12818/* Produces a ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value suitable for setting the register. */
12819#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET(value) (((value) << 0) & 0x00000003)
12820
12821#ifndef __ASSEMBLY__
12822/*
12823 * WARNING: The C register and register group struct declarations are provided for
12824 * convenience and illustrative purposes. They should, however, be used with
12825 * caution as the C language standard provides no guarantees about the alignment or
12826 * atomicity of device memory accesses. The recommended practice for writing
12827 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12828 * alt_write_word() functions.
12829 *
12830 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO8.
12831 */
12832 struct ALT_SYSMGR_PINMUX_GENERALIO8_s
12833{
12834 uint32_t sel : 2; /* trace_d7 Mux Selection Field */
12835 uint32_t : 30; /* *UNDEFINED* */
12836};
12837
12838/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO8. */
12839typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO8_s ALT_SYSMGR_PINMUX_GENERALIO8_t;
12840#endif /* __ASSEMBLY__ */
12841
12842/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO8 register from the beginning of the component. */
12843#define ALT_SYSMGR_PINMUX_GENERALIO8_OFST 0xa0
12844
12845/*
12846 * Register : spim0_clk Mux Selection Register - GENERALIO9
12847 *
12848 * This register is used to control the peripherals connected to spim0_clk
12849 *
12850 * Only reset by a cold reset (ignores warm reset).
12851 *
12852 * NOTE: These registers should not be modified after IO configuration.There is no
12853 * support for dynamically changing the Pin Mux selections.
12854 *
12855 * Register Layout
12856 *
12857 * Bits | Access | Reset | Description
12858 * :-------|:-------|:------|:------------------------------
12859 * [1:0] | RW | 0x0 | spim0_clk Mux Selection Field
12860 * [31:2] | ??? | 0x0 | *UNDEFINED*
12861 *
12862 */
12863/*
12864 * Field : spim0_clk Mux Selection Field - sel
12865 *
12866 * Select peripheral signals connected spim0_clk.
12867 *
12868 * 0 : Pin is connected to GPIO/LoanIO number 57.
12869 *
12870 * 1 : Pin is connected to Peripheral signal UART0.CTS.
12871 *
12872 * 2 : Pin is connected to Peripheral signal I2C1.SDA.
12873 *
12874 * 3 : Pin is connected to Peripheral signal SPIM0.CLK.
12875 *
12876 * Field Access Macros:
12877 *
12878 */
12879/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */
12880#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_LSB 0
12881/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */
12882#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_MSB 1
12883/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */
12884#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_WIDTH 2
12885/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value. */
12886#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET_MSK 0x00000003
12887/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value. */
12888#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_CLR_MSK 0xfffffffc
12889/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */
12890#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_RESET 0x0
12891/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO9_SEL field value from a register. */
12892#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
12893/* Produces a ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value suitable for setting the register. */
12894#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET(value) (((value) << 0) & 0x00000003)
12895
12896#ifndef __ASSEMBLY__
12897/*
12898 * WARNING: The C register and register group struct declarations are provided for
12899 * convenience and illustrative purposes. They should, however, be used with
12900 * caution as the C language standard provides no guarantees about the alignment or
12901 * atomicity of device memory accesses. The recommended practice for writing
12902 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12903 * alt_write_word() functions.
12904 *
12905 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO9.
12906 */
12907 struct ALT_SYSMGR_PINMUX_GENERALIO9_s
12908{
12909 uint32_t sel : 2; /* spim0_clk Mux Selection Field */
12910 uint32_t : 30; /* *UNDEFINED* */
12911};
12912
12913/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO9. */
12914typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO9_s ALT_SYSMGR_PINMUX_GENERALIO9_t;
12915#endif /* __ASSEMBLY__ */
12916
12917/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO9 register from the beginning of the component. */
12918#define ALT_SYSMGR_PINMUX_GENERALIO9_OFST 0xa4
12919
12920/*
12921 * Register : spim0_mosi Mux Selection Register - GENERALIO10
12922 *
12923 * This register is used to control the peripherals connected to spim0_mosi
12924 *
12925 * Only reset by a cold reset (ignores warm reset).
12926 *
12927 * NOTE: These registers should not be modified after IO configuration.There is no
12928 * support for dynamically changing the Pin Mux selections.
12929 *
12930 * Register Layout
12931 *
12932 * Bits | Access | Reset | Description
12933 * :-------|:-------|:------|:-------------------------------
12934 * [1:0] | RW | 0x0 | spim0_mosi Mux Selection Field
12935 * [31:2] | ??? | 0x0 | *UNDEFINED*
12936 *
12937 */
12938/*
12939 * Field : spim0_mosi Mux Selection Field - sel
12940 *
12941 * Select peripheral signals connected spim0_mosi.
12942 *
12943 * 0 : Pin is connected to GPIO/LoanIO number 58.
12944 *
12945 * 1 : Pin is connected to Peripheral signal UART0.RTS.
12946 *
12947 * 2 : Pin is connected to Peripheral signal I2C1.SCL.
12948 *
12949 * 3 : Pin is connected to Peripheral signal SPIM0.MOSI.
12950 *
12951 * Field Access Macros:
12952 *
12953 */
12954/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */
12955#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_LSB 0
12956/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */
12957#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_MSB 1
12958/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */
12959#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_WIDTH 2
12960/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value. */
12961#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET_MSK 0x00000003
12962/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value. */
12963#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_CLR_MSK 0xfffffffc
12964/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */
12965#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_RESET 0x0
12966/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO10_SEL field value from a register. */
12967#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
12968/* Produces a ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value suitable for setting the register. */
12969#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET(value) (((value) << 0) & 0x00000003)
12970
12971#ifndef __ASSEMBLY__
12972/*
12973 * WARNING: The C register and register group struct declarations are provided for
12974 * convenience and illustrative purposes. They should, however, be used with
12975 * caution as the C language standard provides no guarantees about the alignment or
12976 * atomicity of device memory accesses. The recommended practice for writing
12977 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12978 * alt_write_word() functions.
12979 *
12980 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO10.
12981 */
12982 struct ALT_SYSMGR_PINMUX_GENERALIO10_s
12983{
12984 uint32_t sel : 2; /* spim0_mosi Mux Selection Field */
12985 uint32_t : 30; /* *UNDEFINED* */
12986};
12987
12988/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO10. */
12989typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO10_s ALT_SYSMGR_PINMUX_GENERALIO10_t;
12990#endif /* __ASSEMBLY__ */
12991
12992/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO10 register from the beginning of the component. */
12993#define ALT_SYSMGR_PINMUX_GENERALIO10_OFST 0xa8
12994
12995/*
12996 * Register : spim0_miso Mux Selection Register - GENERALIO11
12997 *
12998 * This register is used to control the peripherals connected to spim0_miso
12999 *
13000 * Only reset by a cold reset (ignores warm reset).
13001 *
13002 * NOTE: These registers should not be modified after IO configuration.There is no
13003 * support for dynamically changing the Pin Mux selections.
13004 *
13005 * Register Layout
13006 *
13007 * Bits | Access | Reset | Description
13008 * :-------|:-------|:------|:-------------------------------
13009 * [1:0] | RW | 0x0 | spim0_miso Mux Selection Field
13010 * [31:2] | ??? | 0x0 | *UNDEFINED*
13011 *
13012 */
13013/*
13014 * Field : spim0_miso Mux Selection Field - sel
13015 *
13016 * Select peripheral signals connected spim0_miso.
13017 *
13018 * 0 : Pin is connected to GPIO/LoanIO number 59.
13019 *
13020 * 1 : Pin is connected to Peripheral signal UART1.CTS.
13021 *
13022 * 2 : Pin is connected to Peripheral signal CAN1.RX.
13023 *
13024 * 3 : Pin is connected to Peripheral signal SPIM0.MISO.
13025 *
13026 * Field Access Macros:
13027 *
13028 */
13029/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */
13030#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_LSB 0
13031/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */
13032#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_MSB 1
13033/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */
13034#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_WIDTH 2
13035/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value. */
13036#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET_MSK 0x00000003
13037/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value. */
13038#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_CLR_MSK 0xfffffffc
13039/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */
13040#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_RESET 0x0
13041/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO11_SEL field value from a register. */
13042#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
13043/* Produces a ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value suitable for setting the register. */
13044#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET(value) (((value) << 0) & 0x00000003)
13045
13046#ifndef __ASSEMBLY__
13047/*
13048 * WARNING: The C register and register group struct declarations are provided for
13049 * convenience and illustrative purposes. They should, however, be used with
13050 * caution as the C language standard provides no guarantees about the alignment or
13051 * atomicity of device memory accesses. The recommended practice for writing
13052 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13053 * alt_write_word() functions.
13054 *
13055 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO11.
13056 */
13057 struct ALT_SYSMGR_PINMUX_GENERALIO11_s
13058{
13059 uint32_t sel : 2; /* spim0_miso Mux Selection Field */
13060 uint32_t : 30; /* *UNDEFINED* */
13061};
13062
13063/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO11. */
13064typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO11_s ALT_SYSMGR_PINMUX_GENERALIO11_t;
13065#endif /* __ASSEMBLY__ */
13066
13067/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO11 register from the beginning of the component. */
13068#define ALT_SYSMGR_PINMUX_GENERALIO11_OFST 0xac
13069
13070/*
13071 * Register : spim0_ss0 Mux Selection Register - GENERALIO12
13072 *
13073 * This register is used to control the peripherals connected to spim0_ss0
13074 *
13075 * Only reset by a cold reset (ignores warm reset).
13076 *
13077 * NOTE: These registers should not be modified after IO configuration.There is no
13078 * support for dynamically changing the Pin Mux selections.
13079 *
13080 * Register Layout
13081 *
13082 * Bits | Access | Reset | Description
13083 * :-------|:-------|:------|:------------------------------
13084 * [1:0] | RW | 0x0 | spim0_ss0 Mux Selection Field
13085 * [31:2] | ??? | 0x0 | *UNDEFINED*
13086 *
13087 */
13088/*
13089 * Field : spim0_ss0 Mux Selection Field - sel
13090 *
13091 * Select peripheral signals connected spim0_ss0.
13092 *
13093 * 0 : Pin is connected to GPIO/LoanIO number 60.
13094 *
13095 * 1 : Pin is connected to Peripheral signal UART1.RTS.
13096 *
13097 * 2 : Pin is connected to Peripheral signal CAN1.TX.
13098 *
13099 * 3 : Pin is connected to Peripheral signal SPIM0.SS0.
13100 *
13101 * Field Access Macros:
13102 *
13103 */
13104/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */
13105#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_LSB 0
13106/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */
13107#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_MSB 1
13108/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */
13109#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_WIDTH 2
13110/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value. */
13111#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET_MSK 0x00000003
13112/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value. */
13113#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_CLR_MSK 0xfffffffc
13114/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */
13115#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_RESET 0x0
13116/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO12_SEL field value from a register. */
13117#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_GET(value) (((value) & 0x00000003) >> 0)
13118/* Produces a ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value suitable for setting the register. */
13119#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET(value) (((value) << 0) & 0x00000003)
13120
13121#ifndef __ASSEMBLY__
13122/*
13123 * WARNING: The C register and register group struct declarations are provided for
13124 * convenience and illustrative purposes. They should, however, be used with
13125 * caution as the C language standard provides no guarantees about the alignment or
13126 * atomicity of device memory accesses. The recommended practice for writing
13127 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13128 * alt_write_word() functions.
13129 *
13130 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO12.
13131 */
13132 struct ALT_SYSMGR_PINMUX_GENERALIO12_s
13133{
13134 uint32_t sel : 2; /* spim0_ss0 Mux Selection Field */
13135 uint32_t : 30; /* *UNDEFINED* */
13136};
13137
13138/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO12. */
13139typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO12_s ALT_SYSMGR_PINMUX_GENERALIO12_t;
13140#endif /* __ASSEMBLY__ */
13141
13142/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO12 register from the beginning of the component. */
13143#define ALT_SYSMGR_PINMUX_GENERALIO12_OFST 0xb0
13144
13145/*
13146 * Register : uart0_rx Mux Selection Register - GENERALIO13
13147 *
13148 * This register is used to control the peripherals connected to uart0_rx
13149 *
13150 * Only reset by a cold reset (ignores warm reset).
13151 *
13152 * NOTE: These registers should not be modified after IO configuration.There is no
13153 * support for dynamically changing the Pin Mux selections.
13154 *
13155 * Register Layout
13156 *
13157 * Bits | Access | Reset | Description
13158 * :-------|:-------|:------|:-----------------------------
13159 * [1:0] | RW | 0x0 | uart0_rx Mux Selection Field
13160 * [31:2] | ??? | 0x0 | *UNDEFINED*
13161 *
13162 */
13163/*
13164 * Field : uart0_rx Mux Selection Field - sel
13165 *
13166 * Select peripheral signals connected uart0_rx.
13167 *
13168 * 0 : Pin is connected to GPIO/LoanIO number 61.
13169 *
13170 * 1 : Pin is connected to Peripheral signal SPIM0.SS1.
13171 *
13172 * 2 : Pin is connected to Peripheral signal CAN0.RX.
13173 *
13174 * 3 : Pin is connected to Peripheral signal UART0.RX.
13175 *
13176 * Field Access Macros:
13177 *
13178 */
13179/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */
13180#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_LSB 0
13181/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */
13182#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_MSB 1
13183/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */
13184#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_WIDTH 2
13185/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value. */
13186#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET_MSK 0x00000003
13187/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value. */
13188#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_CLR_MSK 0xfffffffc
13189/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */
13190#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_RESET 0x0
13191/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO13_SEL field value from a register. */
13192#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_GET(value) (((value) & 0x00000003) >> 0)
13193/* Produces a ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value suitable for setting the register. */
13194#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET(value) (((value) << 0) & 0x00000003)
13195
13196#ifndef __ASSEMBLY__
13197/*
13198 * WARNING: The C register and register group struct declarations are provided for
13199 * convenience and illustrative purposes. They should, however, be used with
13200 * caution as the C language standard provides no guarantees about the alignment or
13201 * atomicity of device memory accesses. The recommended practice for writing
13202 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13203 * alt_write_word() functions.
13204 *
13205 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO13.
13206 */
13207 struct ALT_SYSMGR_PINMUX_GENERALIO13_s
13208{
13209 uint32_t sel : 2; /* uart0_rx Mux Selection Field */
13210 uint32_t : 30; /* *UNDEFINED* */
13211};
13212
13213/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO13. */
13214typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO13_s ALT_SYSMGR_PINMUX_GENERALIO13_t;
13215#endif /* __ASSEMBLY__ */
13216
13217/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO13 register from the beginning of the component. */
13218#define ALT_SYSMGR_PINMUX_GENERALIO13_OFST 0xb4
13219
13220/*
13221 * Register : uart0_tx Mux Selection Register - GENERALIO14
13222 *
13223 * This register is used to control the peripherals connected to uart0_tx
13224 *
13225 * Only reset by a cold reset (ignores warm reset).
13226 *
13227 * NOTE: These registers should not be modified after IO configuration.There is no
13228 * support for dynamically changing the Pin Mux selections.
13229 *
13230 * Register Layout
13231 *
13232 * Bits | Access | Reset | Description
13233 * :-------|:-------|:------|:-----------------------------
13234 * [1:0] | RW | 0x0 | uart0_tx Mux Selection Field
13235 * [31:2] | ??? | 0x0 | *UNDEFINED*
13236 *
13237 */
13238/*
13239 * Field : uart0_tx Mux Selection Field - sel
13240 *
13241 * Select peripheral signals connected uart0_tx.
13242 *
13243 * 0 : Pin is connected to GPIO/LoanIO number 62.
13244 *
13245 * 1 : Pin is connected to Peripheral signal SPIM1.SS1.
13246 *
13247 * 2 : Pin is connected to Peripheral signal CAN0.TX.
13248 *
13249 * 3 : Pin is connected to Peripheral signal UART0.TX.
13250 *
13251 * Field Access Macros:
13252 *
13253 */
13254/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */
13255#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_LSB 0
13256/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */
13257#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_MSB 1
13258/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */
13259#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_WIDTH 2
13260/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value. */
13261#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET_MSK 0x00000003
13262/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value. */
13263#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_CLR_MSK 0xfffffffc
13264/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */
13265#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_RESET 0x0
13266/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO14_SEL field value from a register. */
13267#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_GET(value) (((value) & 0x00000003) >> 0)
13268/* Produces a ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value suitable for setting the register. */
13269#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET(value) (((value) << 0) & 0x00000003)
13270
13271#ifndef __ASSEMBLY__
13272/*
13273 * WARNING: The C register and register group struct declarations are provided for
13274 * convenience and illustrative purposes. They should, however, be used with
13275 * caution as the C language standard provides no guarantees about the alignment or
13276 * atomicity of device memory accesses. The recommended practice for writing
13277 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13278 * alt_write_word() functions.
13279 *
13280 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO14.
13281 */
13282 struct ALT_SYSMGR_PINMUX_GENERALIO14_s
13283{
13284 uint32_t sel : 2; /* uart0_tx Mux Selection Field */
13285 uint32_t : 30; /* *UNDEFINED* */
13286};
13287
13288/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO14. */
13289typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO14_s ALT_SYSMGR_PINMUX_GENERALIO14_t;
13290#endif /* __ASSEMBLY__ */
13291
13292/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO14 register from the beginning of the component. */
13293#define ALT_SYSMGR_PINMUX_GENERALIO14_OFST 0xb8
13294
13295/*
13296 * Register : i2c0_sda Mux Selection Register - GENERALIO15
13297 *
13298 * This register is used to control the peripherals connected to i2c0_sda
13299 *
13300 * Only reset by a cold reset (ignores warm reset).
13301 *
13302 * NOTE: These registers should not be modified after IO configuration.There is no
13303 * support for dynamically changing the Pin Mux selections.
13304 *
13305 * Register Layout
13306 *
13307 * Bits | Access | Reset | Description
13308 * :-------|:-------|:------|:-----------------------------
13309 * [1:0] | RW | 0x0 | i2c0_sda Mux Selection Field
13310 * [31:2] | ??? | 0x0 | *UNDEFINED*
13311 *
13312 */
13313/*
13314 * Field : i2c0_sda Mux Selection Field - sel
13315 *
13316 * Select peripheral signals connected i2c0_sda.
13317 *
13318 * 0 : Pin is connected to GPIO/LoanIO number 63.
13319 *
13320 * 1 : Pin is connected to Peripheral signal SPIM1.CLK.
13321 *
13322 * 2 : Pin is connected to Peripheral signal UART1.RX.
13323 *
13324 * 3 : Pin is connected to Peripheral signal I2C0.SDA.
13325 *
13326 * Field Access Macros:
13327 *
13328 */
13329/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */
13330#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_LSB 0
13331/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */
13332#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_MSB 1
13333/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */
13334#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_WIDTH 2
13335/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value. */
13336#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET_MSK 0x00000003
13337/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value. */
13338#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_CLR_MSK 0xfffffffc
13339/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */
13340#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_RESET 0x0
13341/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO15_SEL field value from a register. */
13342#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_GET(value) (((value) & 0x00000003) >> 0)
13343/* Produces a ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value suitable for setting the register. */
13344#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET(value) (((value) << 0) & 0x00000003)
13345
13346#ifndef __ASSEMBLY__
13347/*
13348 * WARNING: The C register and register group struct declarations are provided for
13349 * convenience and illustrative purposes. They should, however, be used with
13350 * caution as the C language standard provides no guarantees about the alignment or
13351 * atomicity of device memory accesses. The recommended practice for writing
13352 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13353 * alt_write_word() functions.
13354 *
13355 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO15.
13356 */
13357 struct ALT_SYSMGR_PINMUX_GENERALIO15_s
13358{
13359 uint32_t sel : 2; /* i2c0_sda Mux Selection Field */
13360 uint32_t : 30; /* *UNDEFINED* */
13361};
13362
13363/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO15. */
13364typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO15_s ALT_SYSMGR_PINMUX_GENERALIO15_t;
13365#endif /* __ASSEMBLY__ */
13366
13367/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO15 register from the beginning of the component. */
13368#define ALT_SYSMGR_PINMUX_GENERALIO15_OFST 0xbc
13369
13370/*
13371 * Register : i2c0_scl Mux Selection Register - GENERALIO16
13372 *
13373 * This register is used to control the peripherals connected to i2c0_scl
13374 *
13375 * Only reset by a cold reset (ignores warm reset).
13376 *
13377 * NOTE: These registers should not be modified after IO configuration.There is no
13378 * support for dynamically changing the Pin Mux selections.
13379 *
13380 * Register Layout
13381 *
13382 * Bits | Access | Reset | Description
13383 * :-------|:-------|:------|:-----------------------------
13384 * [1:0] | RW | 0x0 | i2c0_scl Mux Selection Field
13385 * [31:2] | ??? | 0x0 | *UNDEFINED*
13386 *
13387 */
13388/*
13389 * Field : i2c0_scl Mux Selection Field - sel
13390 *
13391 * Select peripheral signals connected i2c0_scl.
13392 *
13393 * 0 : Pin is connected to GPIO/LoanIO number 64.
13394 *
13395 * 1 : Pin is connected to Peripheral signal SPIM1.MOSI.
13396 *
13397 * 2 : Pin is connected to Peripheral signal UART1.TX.
13398 *
13399 * 3 : Pin is connected to Peripheral signal I2C0.SCL.
13400 *
13401 * Field Access Macros:
13402 *
13403 */
13404/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */
13405#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_LSB 0
13406/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */
13407#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_MSB 1
13408/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */
13409#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_WIDTH 2
13410/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value. */
13411#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET_MSK 0x00000003
13412/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value. */
13413#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_CLR_MSK 0xfffffffc
13414/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */
13415#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_RESET 0x0
13416/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO16_SEL field value from a register. */
13417#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_GET(value) (((value) & 0x00000003) >> 0)
13418/* Produces a ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value suitable for setting the register. */
13419#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET(value) (((value) << 0) & 0x00000003)
13420
13421#ifndef __ASSEMBLY__
13422/*
13423 * WARNING: The C register and register group struct declarations are provided for
13424 * convenience and illustrative purposes. They should, however, be used with
13425 * caution as the C language standard provides no guarantees about the alignment or
13426 * atomicity of device memory accesses. The recommended practice for writing
13427 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13428 * alt_write_word() functions.
13429 *
13430 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO16.
13431 */
13432 struct ALT_SYSMGR_PINMUX_GENERALIO16_s
13433{
13434 uint32_t sel : 2; /* i2c0_scl Mux Selection Field */
13435 uint32_t : 30; /* *UNDEFINED* */
13436};
13437
13438/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO16. */
13439typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO16_s ALT_SYSMGR_PINMUX_GENERALIO16_t;
13440#endif /* __ASSEMBLY__ */
13441
13442/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO16 register from the beginning of the component. */
13443#define ALT_SYSMGR_PINMUX_GENERALIO16_OFST 0xc0
13444
13445/*
13446 * Register : can0_rx Mux Selection Register - GENERALIO17
13447 *
13448 * This register is used to control the peripherals connected to can0_rx
13449 *
13450 * Only reset by a cold reset (ignores warm reset).
13451 *
13452 * NOTE: These registers should not be modified after IO configuration.There is no
13453 * support for dynamically changing the Pin Mux selections.
13454 *
13455 * Register Layout
13456 *
13457 * Bits | Access | Reset | Description
13458 * :-------|:-------|:------|:----------------------------
13459 * [1:0] | RW | 0x0 | can0_rx Mux Selection Field
13460 * [31:2] | ??? | 0x0 | *UNDEFINED*
13461 *
13462 */
13463/*
13464 * Field : can0_rx Mux Selection Field - sel
13465 *
13466 * Select peripheral signals connected can0_rx.
13467 *
13468 * 0 : Pin is connected to GPIO/LoanIO number 65.
13469 *
13470 * 1 : Pin is connected to Peripheral signal SPIM1.MISO.
13471 *
13472 * 2 : Pin is connected to Peripheral signal UART0.RX.
13473 *
13474 * 3 : Pin is connected to Peripheral signal CAN0.RX.
13475 *
13476 * Field Access Macros:
13477 *
13478 */
13479/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */
13480#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_LSB 0
13481/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */
13482#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_MSB 1
13483/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */
13484#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_WIDTH 2
13485/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value. */
13486#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET_MSK 0x00000003
13487/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value. */
13488#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_CLR_MSK 0xfffffffc
13489/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */
13490#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_RESET 0x0
13491/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO17_SEL field value from a register. */
13492#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_GET(value) (((value) & 0x00000003) >> 0)
13493/* Produces a ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value suitable for setting the register. */
13494#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET(value) (((value) << 0) & 0x00000003)
13495
13496#ifndef __ASSEMBLY__
13497/*
13498 * WARNING: The C register and register group struct declarations are provided for
13499 * convenience and illustrative purposes. They should, however, be used with
13500 * caution as the C language standard provides no guarantees about the alignment or
13501 * atomicity of device memory accesses. The recommended practice for writing
13502 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13503 * alt_write_word() functions.
13504 *
13505 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO17.
13506 */
13507 struct ALT_SYSMGR_PINMUX_GENERALIO17_s
13508{
13509 uint32_t sel : 2; /* can0_rx Mux Selection Field */
13510 uint32_t : 30; /* *UNDEFINED* */
13511};
13512
13513/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO17. */
13514typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO17_s ALT_SYSMGR_PINMUX_GENERALIO17_t;
13515#endif /* __ASSEMBLY__ */
13516
13517/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO17 register from the beginning of the component. */
13518#define ALT_SYSMGR_PINMUX_GENERALIO17_OFST 0xc4
13519
13520/*
13521 * Register : can0_tx Mux Selection Register - GENERALIO18
13522 *
13523 * This register is used to control the peripherals connected to can0_tx
13524 *
13525 * Only reset by a cold reset (ignores warm reset).
13526 *
13527 * NOTE: These registers should not be modified after IO configuration.There is no
13528 * support for dynamically changing the Pin Mux selections.
13529 *
13530 * Register Layout
13531 *
13532 * Bits | Access | Reset | Description
13533 * :-------|:-------|:------|:----------------------------
13534 * [1:0] | RW | 0x0 | can0_tx Mux Selection Field
13535 * [31:2] | ??? | 0x0 | *UNDEFINED*
13536 *
13537 */
13538/*
13539 * Field : can0_tx Mux Selection Field - sel
13540 *
13541 * Select peripheral signals connected can0_tx.
13542 *
13543 * 0 : Pin is connected to GPIO/LoanIO number 66.
13544 *
13545 * 1 : Pin is connected to Peripheral signal SPIM1.SS0.
13546 *
13547 * 2 : Pin is connected to Peripheral signal UART0.TX.
13548 *
13549 * 3 : Pin is connected to Peripheral signal CAN0.TX.
13550 *
13551 * Field Access Macros:
13552 *
13553 */
13554/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */
13555#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_LSB 0
13556/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */
13557#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_MSB 1
13558/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */
13559#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_WIDTH 2
13560/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value. */
13561#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET_MSK 0x00000003
13562/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value. */
13563#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_CLR_MSK 0xfffffffc
13564/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */
13565#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_RESET 0x0
13566/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO18_SEL field value from a register. */
13567#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_GET(value) (((value) & 0x00000003) >> 0)
13568/* Produces a ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value suitable for setting the register. */
13569#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET(value) (((value) << 0) & 0x00000003)
13570
13571#ifndef __ASSEMBLY__
13572/*
13573 * WARNING: The C register and register group struct declarations are provided for
13574 * convenience and illustrative purposes. They should, however, be used with
13575 * caution as the C language standard provides no guarantees about the alignment or
13576 * atomicity of device memory accesses. The recommended practice for writing
13577 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13578 * alt_write_word() functions.
13579 *
13580 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO18.
13581 */
13582 struct ALT_SYSMGR_PINMUX_GENERALIO18_s
13583{
13584 uint32_t sel : 2; /* can0_tx Mux Selection Field */
13585 uint32_t : 30; /* *UNDEFINED* */
13586};
13587
13588/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO18. */
13589typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO18_s ALT_SYSMGR_PINMUX_GENERALIO18_t;
13590#endif /* __ASSEMBLY__ */
13591
13592/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO18 register from the beginning of the component. */
13593#define ALT_SYSMGR_PINMUX_GENERALIO18_OFST 0xc8
13594
13595/*
13596 * Register : spis1_clk Mux Selection Register - GENERALIO19
13597 *
13598 * This register is used to control the peripherals connected to spis1_clk
13599 *
13600 * Only reset by a cold reset (ignores warm reset).
13601 *
13602 * NOTE: These registers should not be modified after IO configuration.There is no
13603 * support for dynamically changing the Pin Mux selections.
13604 *
13605 * Register Layout
13606 *
13607 * Bits | Access | Reset | Description
13608 * :-------|:-------|:------|:------------------------------
13609 * [1:0] | RW | 0x0 | spis1_clk Mux Selection Field
13610 * [31:2] | ??? | 0x0 | *UNDEFINED*
13611 *
13612 */
13613/*
13614 * Field : spis1_clk Mux Selection Field - sel
13615 *
13616 * Select peripheral signals connected spis1_clk.
13617 *
13618 * 0 : Pin is connected to GPIO/LoanIO number 67.
13619 *
13620 * 1 : Pin is connected to Peripheral signal not applicable.
13621 *
13622 * 2 : Pin is connected to Peripheral signal SPIM1.CLK.
13623 *
13624 * 3 : Pin is connected to Peripheral signal SPIS1.CLK.
13625 *
13626 * Field Access Macros:
13627 *
13628 */
13629/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */
13630#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_LSB 0
13631/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */
13632#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_MSB 1
13633/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */
13634#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_WIDTH 2
13635/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value. */
13636#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET_MSK 0x00000003
13637/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value. */
13638#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_CLR_MSK 0xfffffffc
13639/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */
13640#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_RESET 0x0
13641/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO19_SEL field value from a register. */
13642#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_GET(value) (((value) & 0x00000003) >> 0)
13643/* Produces a ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value suitable for setting the register. */
13644#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET(value) (((value) << 0) & 0x00000003)
13645
13646#ifndef __ASSEMBLY__
13647/*
13648 * WARNING: The C register and register group struct declarations are provided for
13649 * convenience and illustrative purposes. They should, however, be used with
13650 * caution as the C language standard provides no guarantees about the alignment or
13651 * atomicity of device memory accesses. The recommended practice for writing
13652 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13653 * alt_write_word() functions.
13654 *
13655 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO19.
13656 */
13657 struct ALT_SYSMGR_PINMUX_GENERALIO19_s
13658{
13659 uint32_t sel : 2; /* spis1_clk Mux Selection Field */
13660 uint32_t : 30; /* *UNDEFINED* */
13661};
13662
13663/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO19. */
13664typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO19_s ALT_SYSMGR_PINMUX_GENERALIO19_t;
13665#endif /* __ASSEMBLY__ */
13666
13667/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO19 register from the beginning of the component. */
13668#define ALT_SYSMGR_PINMUX_GENERALIO19_OFST 0xcc
13669
13670/*
13671 * Register : spis1_mosi Mux Selection Register - GENERALIO20
13672 *
13673 * This register is used to control the peripherals connected to spis1_mosi
13674 *
13675 * Only reset by a cold reset (ignores warm reset).
13676 *
13677 * NOTE: These registers should not be modified after IO configuration.There is no
13678 * support for dynamically changing the Pin Mux selections.
13679 *
13680 * Register Layout
13681 *
13682 * Bits | Access | Reset | Description
13683 * :-------|:-------|:------|:-------------------------------
13684 * [1:0] | RW | 0x0 | spis1_mosi Mux Selection Field
13685 * [31:2] | ??? | 0x0 | *UNDEFINED*
13686 *
13687 */
13688/*
13689 * Field : spis1_mosi Mux Selection Field - sel
13690 *
13691 * Select peripheral signals connected spis1_mosi.
13692 *
13693 * 0 : Pin is connected to GPIO/LoanIO number 68.
13694 *
13695 * 1 : Pin is connected to Peripheral signal not applicable.
13696 *
13697 * 2 : Pin is connected to Peripheral signal SPIM1.MOSI.
13698 *
13699 * 3 : Pin is connected to Peripheral signal SPIS1.MOSI.
13700 *
13701 * Field Access Macros:
13702 *
13703 */
13704/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */
13705#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_LSB 0
13706/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */
13707#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_MSB 1
13708/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */
13709#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_WIDTH 2
13710/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value. */
13711#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET_MSK 0x00000003
13712/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value. */
13713#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_CLR_MSK 0xfffffffc
13714/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */
13715#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_RESET 0x0
13716/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO20_SEL field value from a register. */
13717#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_GET(value) (((value) & 0x00000003) >> 0)
13718/* Produces a ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value suitable for setting the register. */
13719#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET(value) (((value) << 0) & 0x00000003)
13720
13721#ifndef __ASSEMBLY__
13722/*
13723 * WARNING: The C register and register group struct declarations are provided for
13724 * convenience and illustrative purposes. They should, however, be used with
13725 * caution as the C language standard provides no guarantees about the alignment or
13726 * atomicity of device memory accesses. The recommended practice for writing
13727 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13728 * alt_write_word() functions.
13729 *
13730 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO20.
13731 */
13732 struct ALT_SYSMGR_PINMUX_GENERALIO20_s
13733{
13734 uint32_t sel : 2; /* spis1_mosi Mux Selection Field */
13735 uint32_t : 30; /* *UNDEFINED* */
13736};
13737
13738/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO20. */
13739typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO20_s ALT_SYSMGR_PINMUX_GENERALIO20_t;
13740#endif /* __ASSEMBLY__ */
13741
13742/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO20 register from the beginning of the component. */
13743#define ALT_SYSMGR_PINMUX_GENERALIO20_OFST 0xd0
13744
13745/*
13746 * Register : spis1_miso Mux Selection Register - GENERALIO21
13747 *
13748 * This register is used to control the peripherals connected to spis1_miso
13749 *
13750 * Only reset by a cold reset (ignores warm reset).
13751 *
13752 * NOTE: These registers should not be modified after IO configuration.There is no
13753 * support for dynamically changing the Pin Mux selections.
13754 *
13755 * Register Layout
13756 *
13757 * Bits | Access | Reset | Description
13758 * :-------|:-------|:------|:-------------------------------
13759 * [1:0] | RW | 0x0 | spis1_miso Mux Selection Field
13760 * [31:2] | ??? | 0x0 | *UNDEFINED*
13761 *
13762 */
13763/*
13764 * Field : spis1_miso Mux Selection Field - sel
13765 *
13766 * Select peripheral signals connected spis1_miso.
13767 *
13768 * 0 : Pin is connected to GPIO/LoanIO number 69.
13769 *
13770 * 1 : Pin is connected to Peripheral signal not applicable.
13771 *
13772 * 2 : Pin is connected to Peripheral signal SPIM1.MISO.
13773 *
13774 * 3 : Pin is connected to Peripheral signal SPIS1.MISO.
13775 *
13776 * Field Access Macros:
13777 *
13778 */
13779/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */
13780#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_LSB 0
13781/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */
13782#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_MSB 1
13783/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */
13784#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_WIDTH 2
13785/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value. */
13786#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET_MSK 0x00000003
13787/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value. */
13788#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_CLR_MSK 0xfffffffc
13789/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */
13790#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_RESET 0x0
13791/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO21_SEL field value from a register. */
13792#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_GET(value) (((value) & 0x00000003) >> 0)
13793/* Produces a ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value suitable for setting the register. */
13794#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET(value) (((value) << 0) & 0x00000003)
13795
13796#ifndef __ASSEMBLY__
13797/*
13798 * WARNING: The C register and register group struct declarations are provided for
13799 * convenience and illustrative purposes. They should, however, be used with
13800 * caution as the C language standard provides no guarantees about the alignment or
13801 * atomicity of device memory accesses. The recommended practice for writing
13802 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13803 * alt_write_word() functions.
13804 *
13805 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO21.
13806 */
13807 struct ALT_SYSMGR_PINMUX_GENERALIO21_s
13808{
13809 uint32_t sel : 2; /* spis1_miso Mux Selection Field */
13810 uint32_t : 30; /* *UNDEFINED* */
13811};
13812
13813/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO21. */
13814typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO21_s ALT_SYSMGR_PINMUX_GENERALIO21_t;
13815#endif /* __ASSEMBLY__ */
13816
13817/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO21 register from the beginning of the component. */
13818#define ALT_SYSMGR_PINMUX_GENERALIO21_OFST 0xd4
13819
13820/*
13821 * Register : spis1_ss0 Mux Selection Register - GENERALIO22
13822 *
13823 * This register is used to control the peripherals connected to spis1_ss0
13824 *
13825 * Only reset by a cold reset (ignores warm reset).
13826 *
13827 * NOTE: These registers should not be modified after IO configuration.There is no
13828 * support for dynamically changing the Pin Mux selections.
13829 *
13830 * Register Layout
13831 *
13832 * Bits | Access | Reset | Description
13833 * :-------|:-------|:------|:------------------------------
13834 * [1:0] | RW | 0x0 | spis1_ss0 Mux Selection Field
13835 * [31:2] | ??? | 0x0 | *UNDEFINED*
13836 *
13837 */
13838/*
13839 * Field : spis1_ss0 Mux Selection Field - sel
13840 *
13841 * Select peripheral signals connected spis1_ss0.
13842 *
13843 * 0 : Pin is connected to GPIO/LoanIO number 70.
13844 *
13845 * 1 : Pin is connected to Peripheral signal not applicable.
13846 *
13847 * 2 : Pin is connected to Peripheral signal SPIM1.SS0.
13848 *
13849 * 3 : Pin is connected to Peripheral signal SPIS1.SS0.
13850 *
13851 * Field Access Macros:
13852 *
13853 */
13854/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */
13855#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_LSB 0
13856/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */
13857#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_MSB 1
13858/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */
13859#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_WIDTH 2
13860/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value. */
13861#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET_MSK 0x00000003
13862/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value. */
13863#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_CLR_MSK 0xfffffffc
13864/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */
13865#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_RESET 0x0
13866/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO22_SEL field value from a register. */
13867#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_GET(value) (((value) & 0x00000003) >> 0)
13868/* Produces a ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value suitable for setting the register. */
13869#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET(value) (((value) << 0) & 0x00000003)
13870
13871#ifndef __ASSEMBLY__
13872/*
13873 * WARNING: The C register and register group struct declarations are provided for
13874 * convenience and illustrative purposes. They should, however, be used with
13875 * caution as the C language standard provides no guarantees about the alignment or
13876 * atomicity of device memory accesses. The recommended practice for writing
13877 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13878 * alt_write_word() functions.
13879 *
13880 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO22.
13881 */
13882 struct ALT_SYSMGR_PINMUX_GENERALIO22_s
13883{
13884 uint32_t sel : 2; /* spis1_ss0 Mux Selection Field */
13885 uint32_t : 30; /* *UNDEFINED* */
13886};
13887
13888/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO22. */
13889typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO22_s ALT_SYSMGR_PINMUX_GENERALIO22_t;
13890#endif /* __ASSEMBLY__ */
13891
13892/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO22 register from the beginning of the component. */
13893#define ALT_SYSMGR_PINMUX_GENERALIO22_OFST 0xd8
13894
13895/*
13896 * Register : uart1_rx Mux Selection Register - GENERALIO23
13897 *
13898 * This register is used to control the peripherals connected to uart1_rx
13899 *
13900 * Only reset by a cold reset (ignores warm reset).
13901 *
13902 * NOTE: These registers should not be modified after IO configuration.There is no
13903 * support for dynamically changing the Pin Mux selections.
13904 *
13905 * Register Layout
13906 *
13907 * Bits | Access | Reset | Description
13908 * :-------|:-------|:------|:-----------------------------
13909 * [1:0] | RW | 0x0 | uart1_rx Mux Selection Field
13910 * [31:2] | ??? | 0x0 | *UNDEFINED*
13911 *
13912 */
13913/*
13914 * Field : uart1_rx Mux Selection Field - sel
13915 *
13916 * Select peripheral signals connected uart1_rx.
13917 *
13918 * 0 : Pin is connected to GPIO/LoanIO number 62.
13919 *
13920 * 1 : Pin is connected to Peripheral signal not applicable.
13921 *
13922 * 2 : Pin is connected to Peripheral signal SPIM1.SS1.
13923 *
13924 * 3 : Pin is connected to Peripheral signal UART1.RX.
13925 *
13926 * Field Access Macros:
13927 *
13928 */
13929/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */
13930#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_LSB 0
13931/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */
13932#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_MSB 1
13933/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */
13934#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_WIDTH 2
13935/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value. */
13936#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET_MSK 0x00000003
13937/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value. */
13938#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_CLR_MSK 0xfffffffc
13939/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */
13940#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_RESET 0x0
13941/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO23_SEL field value from a register. */
13942#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_GET(value) (((value) & 0x00000003) >> 0)
13943/* Produces a ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value suitable for setting the register. */
13944#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET(value) (((value) << 0) & 0x00000003)
13945
13946#ifndef __ASSEMBLY__
13947/*
13948 * WARNING: The C register and register group struct declarations are provided for
13949 * convenience and illustrative purposes. They should, however, be used with
13950 * caution as the C language standard provides no guarantees about the alignment or
13951 * atomicity of device memory accesses. The recommended practice for writing
13952 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13953 * alt_write_word() functions.
13954 *
13955 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO23.
13956 */
13957 struct ALT_SYSMGR_PINMUX_GENERALIO23_s
13958{
13959 uint32_t sel : 2; /* uart1_rx Mux Selection Field */
13960 uint32_t : 30; /* *UNDEFINED* */
13961};
13962
13963/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO23. */
13964typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO23_s ALT_SYSMGR_PINMUX_GENERALIO23_t;
13965#endif /* __ASSEMBLY__ */
13966
13967/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO23 register from the beginning of the component. */
13968#define ALT_SYSMGR_PINMUX_GENERALIO23_OFST 0xdc
13969
13970/*
13971 * Register : uart1_tx Mux Selection Register - GENERALIO24
13972 *
13973 * This register is used to control the peripherals connected to uart1_tx
13974 *
13975 * Only reset by a cold reset (ignores warm reset).
13976 *
13977 * NOTE: These registers should not be modified after IO configuration.There is no
13978 * support for dynamically changing the Pin Mux selections.
13979 *
13980 * Register Layout
13981 *
13982 * Bits | Access | Reset | Description
13983 * :-------|:-------|:------|:-----------------------------
13984 * [1:0] | RW | 0x0 | uart1_tx Mux Selection Field
13985 * [31:2] | ??? | 0x0 | *UNDEFINED*
13986 *
13987 */
13988/*
13989 * Field : uart1_tx Mux Selection Field - sel
13990 *
13991 * Select peripheral signals connected uart1_tx.
13992 *
13993 * 0 : Pin is connected to GPIO/LoanIO number 63.
13994 *
13995 * 1 : Pin is connected to Peripheral signal not applicable.
13996 *
13997 * 2 : Pin is connected to Peripheral signal SPIM0.CLK.
13998 *
13999 * 3 : Pin is connected to Peripheral signal UART1.TX.
14000 *
14001 * Field Access Macros:
14002 *
14003 */
14004/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */
14005#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_LSB 0
14006/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */
14007#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_MSB 1
14008/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */
14009#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_WIDTH 2
14010/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value. */
14011#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET_MSK 0x00000003
14012/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value. */
14013#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_CLR_MSK 0xfffffffc
14014/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */
14015#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_RESET 0x0
14016/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO24_SEL field value from a register. */
14017#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_GET(value) (((value) & 0x00000003) >> 0)
14018/* Produces a ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value suitable for setting the register. */
14019#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET(value) (((value) << 0) & 0x00000003)
14020
14021#ifndef __ASSEMBLY__
14022/*
14023 * WARNING: The C register and register group struct declarations are provided for
14024 * convenience and illustrative purposes. They should, however, be used with
14025 * caution as the C language standard provides no guarantees about the alignment or
14026 * atomicity of device memory accesses. The recommended practice for writing
14027 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14028 * alt_write_word() functions.
14029 *
14030 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO24.
14031 */
14032 struct ALT_SYSMGR_PINMUX_GENERALIO24_s
14033{
14034 uint32_t sel : 2; /* uart1_tx Mux Selection Field */
14035 uint32_t : 30; /* *UNDEFINED* */
14036};
14037
14038/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO24. */
14039typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO24_s ALT_SYSMGR_PINMUX_GENERALIO24_t;
14040#endif /* __ASSEMBLY__ */
14041
14042/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO24 register from the beginning of the component. */
14043#define ALT_SYSMGR_PINMUX_GENERALIO24_OFST 0xe0
14044
14045/*
14046 * Register : i2c1_sda Mux Selection Register - GENERALIO25
14047 *
14048 * This register is used to control the peripherals connected to i2c1_sda
14049 *
14050 * Only reset by a cold reset (ignores warm reset).
14051 *
14052 * NOTE: These registers should not be modified after IO configuration.There is no
14053 * support for dynamically changing the Pin Mux selections.
14054 *
14055 * Register Layout
14056 *
14057 * Bits | Access | Reset | Description
14058 * :-------|:-------|:------|:-----------------------------
14059 * [1:0] | RW | 0x0 | i2c1_sda Mux Selection Field
14060 * [31:2] | ??? | 0x0 | *UNDEFINED*
14061 *
14062 */
14063/*
14064 * Field : i2c1_sda Mux Selection Field - sel
14065 *
14066 * Select peripheral signals connected i2c1_sda.
14067 *
14068 * 0 : Pin is connected to GPIO/LoanIO number 64.
14069 *
14070 * 1 : Pin is connected to Peripheral signal not applicable.
14071 *
14072 * 2 : Pin is connected to Peripheral signal SPIM0.MOSI.
14073 *
14074 * 3 : Pin is connected to Peripheral signal I2C1.SDA.
14075 *
14076 * Field Access Macros:
14077 *
14078 */
14079/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */
14080#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_LSB 0
14081/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */
14082#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_MSB 1
14083/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */
14084#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_WIDTH 2
14085/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value. */
14086#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET_MSK 0x00000003
14087/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value. */
14088#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_CLR_MSK 0xfffffffc
14089/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */
14090#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_RESET 0x0
14091/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO25_SEL field value from a register. */
14092#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_GET(value) (((value) & 0x00000003) >> 0)
14093/* Produces a ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value suitable for setting the register. */
14094#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET(value) (((value) << 0) & 0x00000003)
14095
14096#ifndef __ASSEMBLY__
14097/*
14098 * WARNING: The C register and register group struct declarations are provided for
14099 * convenience and illustrative purposes. They should, however, be used with
14100 * caution as the C language standard provides no guarantees about the alignment or
14101 * atomicity of device memory accesses. The recommended practice for writing
14102 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14103 * alt_write_word() functions.
14104 *
14105 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO25.
14106 */
14107 struct ALT_SYSMGR_PINMUX_GENERALIO25_s
14108{
14109 uint32_t sel : 2; /* i2c1_sda Mux Selection Field */
14110 uint32_t : 30; /* *UNDEFINED* */
14111};
14112
14113/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO25. */
14114typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO25_s ALT_SYSMGR_PINMUX_GENERALIO25_t;
14115#endif /* __ASSEMBLY__ */
14116
14117/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO25 register from the beginning of the component. */
14118#define ALT_SYSMGR_PINMUX_GENERALIO25_OFST 0xe4
14119
14120/*
14121 * Register : i2c1_scl Mux Selection Register - GENERALIO26
14122 *
14123 * This register is used to control the peripherals connected to i2c1_scl
14124 *
14125 * Only reset by a cold reset (ignores warm reset).
14126 *
14127 * NOTE: These registers should not be modified after IO configuration.There is no
14128 * support for dynamically changing the Pin Mux selections.
14129 *
14130 * Register Layout
14131 *
14132 * Bits | Access | Reset | Description
14133 * :-------|:-------|:------|:-----------------------------
14134 * [1:0] | RW | 0x0 | i2c1_scl Mux Selection Field
14135 * [31:2] | ??? | 0x0 | *UNDEFINED*
14136 *
14137 */
14138/*
14139 * Field : i2c1_scl Mux Selection Field - sel
14140 *
14141 * Select peripheral signals connected i2c1_scl.
14142 *
14143 * 0 : Pin is connected to GPIO/LoanIO number 65.
14144 *
14145 * 1 : Pin is connected to Peripheral signal not applicable.
14146 *
14147 * 2 : Pin is connected to Peripheral signal SPIM0.MISO.
14148 *
14149 * 3 : Pin is connected to Peripheral signal I2C1.SCL.
14150 *
14151 * Field Access Macros:
14152 *
14153 */
14154/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */
14155#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_LSB 0
14156/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */
14157#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_MSB 1
14158/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */
14159#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_WIDTH 2
14160/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value. */
14161#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET_MSK 0x00000003
14162/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value. */
14163#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_CLR_MSK 0xfffffffc
14164/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */
14165#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_RESET 0x0
14166/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO26_SEL field value from a register. */
14167#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_GET(value) (((value) & 0x00000003) >> 0)
14168/* Produces a ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value suitable for setting the register. */
14169#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET(value) (((value) << 0) & 0x00000003)
14170
14171#ifndef __ASSEMBLY__
14172/*
14173 * WARNING: The C register and register group struct declarations are provided for
14174 * convenience and illustrative purposes. They should, however, be used with
14175 * caution as the C language standard provides no guarantees about the alignment or
14176 * atomicity of device memory accesses. The recommended practice for writing
14177 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14178 * alt_write_word() functions.
14179 *
14180 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO26.
14181 */
14182 struct ALT_SYSMGR_PINMUX_GENERALIO26_s
14183{
14184 uint32_t sel : 2; /* i2c1_scl Mux Selection Field */
14185 uint32_t : 30; /* *UNDEFINED* */
14186};
14187
14188/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO26. */
14189typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO26_s ALT_SYSMGR_PINMUX_GENERALIO26_t;
14190#endif /* __ASSEMBLY__ */
14191
14192/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO26 register from the beginning of the component. */
14193#define ALT_SYSMGR_PINMUX_GENERALIO26_OFST 0xe8
14194
14195/*
14196 * Register : spim0_ss0_alt Mux Selection Register - GENERALIO27
14197 *
14198 * This register is used to control the peripherals connected to spim0_ss0_alt
14199 *
14200 * Only reset by a cold reset (ignores warm reset).
14201 *
14202 * NOTE: These registers should not be modified after IO configuration.There is no
14203 * support for dynamically changing the Pin Mux selections.
14204 *
14205 * Register Layout
14206 *
14207 * Bits | Access | Reset | Description
14208 * :-------|:-------|:------|:----------------------------------
14209 * [1:0] | RW | 0x0 | spim0_ss0_alt Mux Selection Field
14210 * [31:2] | ??? | 0x0 | *UNDEFINED*
14211 *
14212 */
14213/*
14214 * Field : spim0_ss0_alt Mux Selection Field - sel
14215 *
14216 * Select peripheral signals connected spim0_ss0_alt.
14217 *
14218 * 0 : Pin is connected to GPIO/LoanIO number 66.
14219 *
14220 * 1 : Pin is connected to Peripheral signal not applicable.
14221 *
14222 * 2 : Pin is connected to Peripheral signal SPIM0.SS0.
14223 *
14224 * 3 : Pin is connected to Peripheral signal not applicable.
14225 *
14226 * Field Access Macros:
14227 *
14228 */
14229/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */
14230#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_LSB 0
14231/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */
14232#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_MSB 1
14233/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */
14234#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_WIDTH 2
14235/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value. */
14236#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET_MSK 0x00000003
14237/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value. */
14238#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_CLR_MSK 0xfffffffc
14239/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */
14240#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_RESET 0x0
14241/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO27_SEL field value from a register. */
14242#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_GET(value) (((value) & 0x00000003) >> 0)
14243/* Produces a ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value suitable for setting the register. */
14244#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET(value) (((value) << 0) & 0x00000003)
14245
14246#ifndef __ASSEMBLY__
14247/*
14248 * WARNING: The C register and register group struct declarations are provided for
14249 * convenience and illustrative purposes. They should, however, be used with
14250 * caution as the C language standard provides no guarantees about the alignment or
14251 * atomicity of device memory accesses. The recommended practice for writing
14252 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14253 * alt_write_word() functions.
14254 *
14255 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO27.
14256 */
14257 struct ALT_SYSMGR_PINMUX_GENERALIO27_s
14258{
14259 uint32_t sel : 2; /* spim0_ss0_alt Mux Selection Field */
14260 uint32_t : 30; /* *UNDEFINED* */
14261};
14262
14263/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO27. */
14264typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO27_s ALT_SYSMGR_PINMUX_GENERALIO27_t;
14265#endif /* __ASSEMBLY__ */
14266
14267/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO27 register from the beginning of the component. */
14268#define ALT_SYSMGR_PINMUX_GENERALIO27_OFST 0xec
14269
14270/*
14271 * Register : spis0_clk Mux Selection Register - GENERALIO28
14272 *
14273 * This register is used to control the peripherals connected to spis0_clk
14274 *
14275 * Only reset by a cold reset (ignores warm reset).
14276 *
14277 * NOTE: These registers should not be modified after IO configuration.There is no
14278 * support for dynamically changing the Pin Mux selections.
14279 *
14280 * Register Layout
14281 *
14282 * Bits | Access | Reset | Description
14283 * :-------|:-------|:------|:------------------------------
14284 * [1:0] | RW | 0x0 | spis0_clk Mux Selection Field
14285 * [31:2] | ??? | 0x0 | *UNDEFINED*
14286 *
14287 */
14288/*
14289 * Field : spis0_clk Mux Selection Field - sel
14290 *
14291 * Select peripheral signals connected spis0_clk.
14292 *
14293 * 0 : Pin is connected to GPIO/LoanIO number 67.
14294 *
14295 * 1 : Pin is connected to Peripheral signal not applicable.
14296 *
14297 * 2 : Pin is connected to Peripheral signal SPIM0.SS1.
14298 *
14299 * 3 : Pin is connected to Peripheral signal SPIS0.CLK.
14300 *
14301 * Field Access Macros:
14302 *
14303 */
14304/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */
14305#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_LSB 0
14306/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */
14307#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_MSB 1
14308/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */
14309#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_WIDTH 2
14310/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value. */
14311#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET_MSK 0x00000003
14312/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value. */
14313#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_CLR_MSK 0xfffffffc
14314/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */
14315#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_RESET 0x0
14316/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO28_SEL field value from a register. */
14317#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_GET(value) (((value) & 0x00000003) >> 0)
14318/* Produces a ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value suitable for setting the register. */
14319#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET(value) (((value) << 0) & 0x00000003)
14320
14321#ifndef __ASSEMBLY__
14322/*
14323 * WARNING: The C register and register group struct declarations are provided for
14324 * convenience and illustrative purposes. They should, however, be used with
14325 * caution as the C language standard provides no guarantees about the alignment or
14326 * atomicity of device memory accesses. The recommended practice for writing
14327 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14328 * alt_write_word() functions.
14329 *
14330 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO28.
14331 */
14332 struct ALT_SYSMGR_PINMUX_GENERALIO28_s
14333{
14334 uint32_t sel : 2; /* spis0_clk Mux Selection Field */
14335 uint32_t : 30; /* *UNDEFINED* */
14336};
14337
14338/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO28. */
14339typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO28_s ALT_SYSMGR_PINMUX_GENERALIO28_t;
14340#endif /* __ASSEMBLY__ */
14341
14342/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO28 register from the beginning of the component. */
14343#define ALT_SYSMGR_PINMUX_GENERALIO28_OFST 0xf0
14344
14345/*
14346 * Register : spis0_mosi Mux Selection Register - GENERALIO29
14347 *
14348 * This register is used to control the peripherals connected to spis0_mosi
14349 *
14350 * Only reset by a cold reset (ignores warm reset).
14351 *
14352 * NOTE: These registers should not be modified after IO configuration.There is no
14353 * support for dynamically changing the Pin Mux selections.
14354 *
14355 * Register Layout
14356 *
14357 * Bits | Access | Reset | Description
14358 * :-------|:-------|:------|:-------------------------------
14359 * [1:0] | RW | 0x0 | spis0_mosi Mux Selection Field
14360 * [31:2] | ??? | 0x0 | *UNDEFINED*
14361 *
14362 */
14363/*
14364 * Field : spis0_mosi Mux Selection Field - sel
14365 *
14366 * Select peripheral signals connected spis0_mosi.
14367 *
14368 * 0 : Pin is connected to GPIO/LoanIO number 68.
14369 *
14370 * 1 : Pin is connected to Peripheral signal not applicable.
14371 *
14372 * 2 : Pin is connected to Peripheral signal not applicable.
14373 *
14374 * 3 : Pin is connected to Peripheral signal SPIS0.MOSI.
14375 *
14376 * Field Access Macros:
14377 *
14378 */
14379/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */
14380#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_LSB 0
14381/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */
14382#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_MSB 1
14383/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */
14384#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_WIDTH 2
14385/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value. */
14386#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET_MSK 0x00000003
14387/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value. */
14388#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_CLR_MSK 0xfffffffc
14389/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */
14390#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_RESET 0x0
14391/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO29_SEL field value from a register. */
14392#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_GET(value) (((value) & 0x00000003) >> 0)
14393/* Produces a ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value suitable for setting the register. */
14394#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET(value) (((value) << 0) & 0x00000003)
14395
14396#ifndef __ASSEMBLY__
14397/*
14398 * WARNING: The C register and register group struct declarations are provided for
14399 * convenience and illustrative purposes. They should, however, be used with
14400 * caution as the C language standard provides no guarantees about the alignment or
14401 * atomicity of device memory accesses. The recommended practice for writing
14402 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14403 * alt_write_word() functions.
14404 *
14405 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO29.
14406 */
14407 struct ALT_SYSMGR_PINMUX_GENERALIO29_s
14408{
14409 uint32_t sel : 2; /* spis0_mosi Mux Selection Field */
14410 uint32_t : 30; /* *UNDEFINED* */
14411};
14412
14413/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO29. */
14414typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO29_s ALT_SYSMGR_PINMUX_GENERALIO29_t;
14415#endif /* __ASSEMBLY__ */
14416
14417/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO29 register from the beginning of the component. */
14418#define ALT_SYSMGR_PINMUX_GENERALIO29_OFST 0xf4
14419
14420/*
14421 * Register : spis0_miso Mux Selection Register - GENERALIO30
14422 *
14423 * This register is used to control the peripherals connected to spis0_miso
14424 *
14425 * Only reset by a cold reset (ignores warm reset).
14426 *
14427 * NOTE: These registers should not be modified after IO configuration.There is no
14428 * support for dynamically changing the Pin Mux selections.
14429 *
14430 * Register Layout
14431 *
14432 * Bits | Access | Reset | Description
14433 * :-------|:-------|:------|:-------------------------------
14434 * [1:0] | RW | 0x0 | spis0_miso Mux Selection Field
14435 * [31:2] | ??? | 0x0 | *UNDEFINED*
14436 *
14437 */
14438/*
14439 * Field : spis0_miso Mux Selection Field - sel
14440 *
14441 * Select peripheral signals connected spis0_miso.
14442 *
14443 * 0 : Pin is connected to GPIO/LoanIO number 69.
14444 *
14445 * 1 : Pin is connected to Peripheral signal not applicable.
14446 *
14447 * 2 : Pin is connected to Peripheral signal not applicable.
14448 *
14449 * 3 : Pin is connected to Peripheral signal SPIS0.MISO.
14450 *
14451 * Field Access Macros:
14452 *
14453 */
14454/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */
14455#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_LSB 0
14456/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */
14457#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_MSB 1
14458/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */
14459#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_WIDTH 2
14460/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value. */
14461#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET_MSK 0x00000003
14462/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value. */
14463#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_CLR_MSK 0xfffffffc
14464/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */
14465#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_RESET 0x0
14466/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO30_SEL field value from a register. */
14467#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_GET(value) (((value) & 0x00000003) >> 0)
14468/* Produces a ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value suitable for setting the register. */
14469#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET(value) (((value) << 0) & 0x00000003)
14470
14471#ifndef __ASSEMBLY__
14472/*
14473 * WARNING: The C register and register group struct declarations are provided for
14474 * convenience and illustrative purposes. They should, however, be used with
14475 * caution as the C language standard provides no guarantees about the alignment or
14476 * atomicity of device memory accesses. The recommended practice for writing
14477 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14478 * alt_write_word() functions.
14479 *
14480 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO30.
14481 */
14482 struct ALT_SYSMGR_PINMUX_GENERALIO30_s
14483{
14484 uint32_t sel : 2; /* spis0_miso Mux Selection Field */
14485 uint32_t : 30; /* *UNDEFINED* */
14486};
14487
14488/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO30. */
14489typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO30_s ALT_SYSMGR_PINMUX_GENERALIO30_t;
14490#endif /* __ASSEMBLY__ */
14491
14492/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO30 register from the beginning of the component. */
14493#define ALT_SYSMGR_PINMUX_GENERALIO30_OFST 0xf8
14494
14495/*
14496 * Register : spis0_ss0 Mux Selection Register - GENERALIO31
14497 *
14498 * This register is used to control the peripherals connected to spis0_ss0
14499 *
14500 * Only reset by a cold reset (ignores warm reset).
14501 *
14502 * NOTE: These registers should not be modified after IO configuration.There is no
14503 * support for dynamically changing the Pin Mux selections.
14504 *
14505 * Register Layout
14506 *
14507 * Bits | Access | Reset | Description
14508 * :-------|:-------|:------|:------------------------------
14509 * [1:0] | RW | 0x0 | spis0_ss0 Mux Selection Field
14510 * [31:2] | ??? | 0x0 | *UNDEFINED*
14511 *
14512 */
14513/*
14514 * Field : spis0_ss0 Mux Selection Field - sel
14515 *
14516 * Select peripheral signals connected spis0_ss0.
14517 *
14518 * 0 : Pin is connected to GPIO/LoanIO number 70.
14519 *
14520 * 1 : Pin is connected to Peripheral signal not applicable.
14521 *
14522 * 2 : Pin is connected to Peripheral signal not applicable.
14523 *
14524 * 3 : Pin is connected to Peripheral signal SPIS0.SS0.
14525 *
14526 * Field Access Macros:
14527 *
14528 */
14529/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */
14530#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_LSB 0
14531/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */
14532#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_MSB 1
14533/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */
14534#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_WIDTH 2
14535/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value. */
14536#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET_MSK 0x00000003
14537/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value. */
14538#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_CLR_MSK 0xfffffffc
14539/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */
14540#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_RESET 0x0
14541/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO31_SEL field value from a register. */
14542#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_GET(value) (((value) & 0x00000003) >> 0)
14543/* Produces a ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value suitable for setting the register. */
14544#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET(value) (((value) << 0) & 0x00000003)
14545
14546#ifndef __ASSEMBLY__
14547/*
14548 * WARNING: The C register and register group struct declarations are provided for
14549 * convenience and illustrative purposes. They should, however, be used with
14550 * caution as the C language standard provides no guarantees about the alignment or
14551 * atomicity of device memory accesses. The recommended practice for writing
14552 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14553 * alt_write_word() functions.
14554 *
14555 * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO31.
14556 */
14557 struct ALT_SYSMGR_PINMUX_GENERALIO31_s
14558{
14559 uint32_t sel : 2; /* spis0_ss0 Mux Selection Field */
14560 uint32_t : 30; /* *UNDEFINED* */
14561};
14562
14563/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO31. */
14564typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO31_s ALT_SYSMGR_PINMUX_GENERALIO31_t;
14565#endif /* __ASSEMBLY__ */
14566
14567/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO31 register from the beginning of the component. */
14568#define ALT_SYSMGR_PINMUX_GENERALIO31_OFST 0xfc
14569
14570/*
14571 * Register : nand_ale Mux Selection Register - MIXED1IO0
14572 *
14573 * This register is used to control the peripherals connected to nand_ale
14574 *
14575 * Only reset by a cold reset (ignores warm reset).
14576 *
14577 * NOTE: These registers should not be modified after IO configuration.There is no
14578 * support for dynamically changing the Pin Mux selections.
14579 *
14580 * Register Layout
14581 *
14582 * Bits | Access | Reset | Description
14583 * :-------|:-------|:------|:-----------------------------
14584 * [1:0] | RW | 0x0 | nand_ale Mux Selection Field
14585 * [31:2] | ??? | 0x0 | *UNDEFINED*
14586 *
14587 */
14588/*
14589 * Field : nand_ale Mux Selection Field - sel
14590 *
14591 * Select peripheral signals connected nand_ale.
14592 *
14593 * 0 : Pin is connected to GPIO/LoanIO number 14.
14594 *
14595 * 1 : Pin is connected to Peripheral signal QSPI.SS3.
14596 *
14597 * 2 : Pin is connected to Peripheral signal RGMII1.TX_CLK.
14598 *
14599 * 3 : Pin is connected to Peripheral signal NAND.ale.
14600 *
14601 * Field Access Macros:
14602 *
14603 */
14604/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */
14605#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_LSB 0
14606/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */
14607#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_MSB 1
14608/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */
14609#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_WIDTH 2
14610/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value. */
14611#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET_MSK 0x00000003
14612/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value. */
14613#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_CLR_MSK 0xfffffffc
14614/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */
14615#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_RESET 0x0
14616/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL field value from a register. */
14617#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
14618/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value suitable for setting the register. */
14619#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET(value) (((value) << 0) & 0x00000003)
14620
14621#ifndef __ASSEMBLY__
14622/*
14623 * WARNING: The C register and register group struct declarations are provided for
14624 * convenience and illustrative purposes. They should, however, be used with
14625 * caution as the C language standard provides no guarantees about the alignment or
14626 * atomicity of device memory accesses. The recommended practice for writing
14627 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14628 * alt_write_word() functions.
14629 *
14630 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO0.
14631 */
14632 struct ALT_SYSMGR_PINMUX_MIXED1IO0_s
14633{
14634 uint32_t sel : 2; /* nand_ale Mux Selection Field */
14635 uint32_t : 30; /* *UNDEFINED* */
14636};
14637
14638/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO0. */
14639typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO0_s ALT_SYSMGR_PINMUX_MIXED1IO0_t;
14640#endif /* __ASSEMBLY__ */
14641
14642/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO0 register from the beginning of the component. */
14643#define ALT_SYSMGR_PINMUX_MIXED1IO0_OFST 0x100
14644
14645/*
14646 * Register : nand_ce Mux Selection Register - MIXED1IO1
14647 *
14648 * This register is used to control the peripherals connected to nand_ce
14649 *
14650 * Only reset by a cold reset (ignores warm reset).
14651 *
14652 * NOTE: These registers should not be modified after IO configuration.There is no
14653 * support for dynamically changing the Pin Mux selections.
14654 *
14655 * Register Layout
14656 *
14657 * Bits | Access | Reset | Description
14658 * :-------|:-------|:------|:----------------------------
14659 * [1:0] | RW | 0x0 | nand_ce Mux Selection Field
14660 * [31:2] | ??? | 0x0 | *UNDEFINED*
14661 *
14662 */
14663/*
14664 * Field : nand_ce Mux Selection Field - sel
14665 *
14666 * Select peripheral signals connected nand_ce.
14667 *
14668 * 0 : Pin is connected to GPIO/LoanIO number 15.
14669 *
14670 * 1 : Pin is connected to Peripheral signal USB1.D0.
14671 *
14672 * 2 : Pin is connected to Peripheral signal RGMII1.TXD0.
14673 *
14674 * 3 : Pin is connected to Peripheral signal NAND.ce.
14675 *
14676 * Field Access Macros:
14677 *
14678 */
14679/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */
14680#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_LSB 0
14681/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */
14682#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_MSB 1
14683/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */
14684#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_WIDTH 2
14685/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value. */
14686#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET_MSK 0x00000003
14687/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value. */
14688#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_CLR_MSK 0xfffffffc
14689/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */
14690#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_RESET 0x0
14691/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL field value from a register. */
14692#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
14693/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value suitable for setting the register. */
14694#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET(value) (((value) << 0) & 0x00000003)
14695
14696#ifndef __ASSEMBLY__
14697/*
14698 * WARNING: The C register and register group struct declarations are provided for
14699 * convenience and illustrative purposes. They should, however, be used with
14700 * caution as the C language standard provides no guarantees about the alignment or
14701 * atomicity of device memory accesses. The recommended practice for writing
14702 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14703 * alt_write_word() functions.
14704 *
14705 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO1.
14706 */
14707 struct ALT_SYSMGR_PINMUX_MIXED1IO1_s
14708{
14709 uint32_t sel : 2; /* nand_ce Mux Selection Field */
14710 uint32_t : 30; /* *UNDEFINED* */
14711};
14712
14713/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO1. */
14714typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO1_s ALT_SYSMGR_PINMUX_MIXED1IO1_t;
14715#endif /* __ASSEMBLY__ */
14716
14717/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO1 register from the beginning of the component. */
14718#define ALT_SYSMGR_PINMUX_MIXED1IO1_OFST 0x104
14719
14720/*
14721 * Register : nand_cle Mux Selection Register - MIXED1IO2
14722 *
14723 * This register is used to control the peripherals connected to nand_cle
14724 *
14725 * Only reset by a cold reset (ignores warm reset).
14726 *
14727 * NOTE: These registers should not be modified after IO configuration.There is no
14728 * support for dynamically changing the Pin Mux selections.
14729 *
14730 * Register Layout
14731 *
14732 * Bits | Access | Reset | Description
14733 * :-------|:-------|:------|:-----------------------------
14734 * [1:0] | RW | 0x0 | nand_cle Mux Selection Field
14735 * [31:2] | ??? | 0x0 | *UNDEFINED*
14736 *
14737 */
14738/*
14739 * Field : nand_cle Mux Selection Field - sel
14740 *
14741 * Select peripheral signals connected nand_cle.
14742 *
14743 * 0 : Pin is connected to GPIO/LoanIO number 16.
14744 *
14745 * 1 : Pin is connected to Peripheral signal USB1.D1.
14746 *
14747 * 2 : Pin is connected to Peripheral signal RGMII1.TXD1.
14748 *
14749 * 3 : Pin is connected to Peripheral signal NAND.cle.
14750 *
14751 * Field Access Macros:
14752 *
14753 */
14754/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */
14755#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_LSB 0
14756/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */
14757#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_MSB 1
14758/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */
14759#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_WIDTH 2
14760/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value. */
14761#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET_MSK 0x00000003
14762/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value. */
14763#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_CLR_MSK 0xfffffffc
14764/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */
14765#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_RESET 0x0
14766/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL field value from a register. */
14767#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
14768/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value suitable for setting the register. */
14769#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET(value) (((value) << 0) & 0x00000003)
14770
14771#ifndef __ASSEMBLY__
14772/*
14773 * WARNING: The C register and register group struct declarations are provided for
14774 * convenience and illustrative purposes. They should, however, be used with
14775 * caution as the C language standard provides no guarantees about the alignment or
14776 * atomicity of device memory accesses. The recommended practice for writing
14777 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14778 * alt_write_word() functions.
14779 *
14780 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO2.
14781 */
14782 struct ALT_SYSMGR_PINMUX_MIXED1IO2_s
14783{
14784 uint32_t sel : 2; /* nand_cle Mux Selection Field */
14785 uint32_t : 30; /* *UNDEFINED* */
14786};
14787
14788/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO2. */
14789typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO2_s ALT_SYSMGR_PINMUX_MIXED1IO2_t;
14790#endif /* __ASSEMBLY__ */
14791
14792/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO2 register from the beginning of the component. */
14793#define ALT_SYSMGR_PINMUX_MIXED1IO2_OFST 0x108
14794
14795/*
14796 * Register : nand_re Mux Selection Register - MIXED1IO3
14797 *
14798 * This register is used to control the peripherals connected to nand_re
14799 *
14800 * Only reset by a cold reset (ignores warm reset).
14801 *
14802 * NOTE: These registers should not be modified after IO configuration.There is no
14803 * support for dynamically changing the Pin Mux selections.
14804 *
14805 * Register Layout
14806 *
14807 * Bits | Access | Reset | Description
14808 * :-------|:-------|:------|:----------------------------
14809 * [1:0] | RW | 0x0 | nand_re Mux Selection Field
14810 * [31:2] | ??? | 0x0 | *UNDEFINED*
14811 *
14812 */
14813/*
14814 * Field : nand_re Mux Selection Field - sel
14815 *
14816 * Select peripheral signals connected nand_re.
14817 *
14818 * 0 : Pin is connected to GPIO/LoanIO number 17.
14819 *
14820 * 1 : Pin is connected to Peripheral signal USB1.D2.
14821 *
14822 * 2 : Pin is connected to Peripheral signal RGMII1.TXD2.
14823 *
14824 * 3 : Pin is connected to Peripheral signal NAND.re.
14825 *
14826 * Field Access Macros:
14827 *
14828 */
14829/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */
14830#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_LSB 0
14831/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */
14832#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_MSB 1
14833/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */
14834#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_WIDTH 2
14835/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value. */
14836#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET_MSK 0x00000003
14837/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value. */
14838#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_CLR_MSK 0xfffffffc
14839/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */
14840#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_RESET 0x0
14841/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL field value from a register. */
14842#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
14843/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value suitable for setting the register. */
14844#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET(value) (((value) << 0) & 0x00000003)
14845
14846#ifndef __ASSEMBLY__
14847/*
14848 * WARNING: The C register and register group struct declarations are provided for
14849 * convenience and illustrative purposes. They should, however, be used with
14850 * caution as the C language standard provides no guarantees about the alignment or
14851 * atomicity of device memory accesses. The recommended practice for writing
14852 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14853 * alt_write_word() functions.
14854 *
14855 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO3.
14856 */
14857 struct ALT_SYSMGR_PINMUX_MIXED1IO3_s
14858{
14859 uint32_t sel : 2; /* nand_re Mux Selection Field */
14860 uint32_t : 30; /* *UNDEFINED* */
14861};
14862
14863/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO3. */
14864typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO3_s ALT_SYSMGR_PINMUX_MIXED1IO3_t;
14865#endif /* __ASSEMBLY__ */
14866
14867/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO3 register from the beginning of the component. */
14868#define ALT_SYSMGR_PINMUX_MIXED1IO3_OFST 0x10c
14869
14870/*
14871 * Register : nand_rb Mux Selection Register - MIXED1IO4
14872 *
14873 * This register is used to control the peripherals connected to nand_rb
14874 *
14875 * Only reset by a cold reset (ignores warm reset).
14876 *
14877 * NOTE: These registers should not be modified after IO configuration.There is no
14878 * support for dynamically changing the Pin Mux selections.
14879 *
14880 * Register Layout
14881 *
14882 * Bits | Access | Reset | Description
14883 * :-------|:-------|:------|:----------------------------
14884 * [1:0] | RW | 0x0 | nand_rb Mux Selection Field
14885 * [31:2] | ??? | 0x0 | *UNDEFINED*
14886 *
14887 */
14888/*
14889 * Field : nand_rb Mux Selection Field - sel
14890 *
14891 * Select peripheral signals connected nand_rb.
14892 *
14893 * 0 : Pin is connected to GPIO/LoanIO number 18.
14894 *
14895 * 1 : Pin is connected to Peripheral signal USB1.D3.
14896 *
14897 * 2 : Pin is connected to Peripheral signal RGMII1.TXD3.
14898 *
14899 * 3 : Pin is connected to Peripheral signal NAND.rb.
14900 *
14901 * Field Access Macros:
14902 *
14903 */
14904/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */
14905#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_LSB 0
14906/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */
14907#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_MSB 1
14908/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */
14909#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_WIDTH 2
14910/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value. */
14911#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET_MSK 0x00000003
14912/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value. */
14913#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_CLR_MSK 0xfffffffc
14914/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */
14915#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_RESET 0x0
14916/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL field value from a register. */
14917#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
14918/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value suitable for setting the register. */
14919#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET(value) (((value) << 0) & 0x00000003)
14920
14921#ifndef __ASSEMBLY__
14922/*
14923 * WARNING: The C register and register group struct declarations are provided for
14924 * convenience and illustrative purposes. They should, however, be used with
14925 * caution as the C language standard provides no guarantees about the alignment or
14926 * atomicity of device memory accesses. The recommended practice for writing
14927 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14928 * alt_write_word() functions.
14929 *
14930 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO4.
14931 */
14932 struct ALT_SYSMGR_PINMUX_MIXED1IO4_s
14933{
14934 uint32_t sel : 2; /* nand_rb Mux Selection Field */
14935 uint32_t : 30; /* *UNDEFINED* */
14936};
14937
14938/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO4. */
14939typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO4_s ALT_SYSMGR_PINMUX_MIXED1IO4_t;
14940#endif /* __ASSEMBLY__ */
14941
14942/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO4 register from the beginning of the component. */
14943#define ALT_SYSMGR_PINMUX_MIXED1IO4_OFST 0x110
14944
14945/*
14946 * Register : nand_dq0 Mux Selection Register - MIXED1IO5
14947 *
14948 * This register is used to control the peripherals connected to nand_dq0
14949 *
14950 * Only reset by a cold reset (ignores warm reset).
14951 *
14952 * NOTE: These registers should not be modified after IO configuration.There is no
14953 * support for dynamically changing the Pin Mux selections.
14954 *
14955 * Register Layout
14956 *
14957 * Bits | Access | Reset | Description
14958 * :-------|:-------|:------|:-----------------------------
14959 * [1:0] | RW | 0x0 | nand_dq0 Mux Selection Field
14960 * [31:2] | ??? | 0x0 | *UNDEFINED*
14961 *
14962 */
14963/*
14964 * Field : nand_dq0 Mux Selection Field - sel
14965 *
14966 * Select peripheral signals connected nand_dq0.
14967 *
14968 * 0 : Pin is connected to GPIO/LoanIO number 19.
14969 *
14970 * 1 : Pin is connected to Peripheral signal not applicable.
14971 *
14972 * 2 : Pin is connected to Peripheral signal RGMII1.RXD0.
14973 *
14974 * 3 : Pin is connected to Peripheral signal NAND.dq0.
14975 *
14976 * Field Access Macros:
14977 *
14978 */
14979/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */
14980#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_LSB 0
14981/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */
14982#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_MSB 1
14983/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */
14984#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_WIDTH 2
14985/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value. */
14986#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET_MSK 0x00000003
14987/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value. */
14988#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_CLR_MSK 0xfffffffc
14989/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */
14990#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_RESET 0x0
14991/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL field value from a register. */
14992#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
14993/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value suitable for setting the register. */
14994#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET(value) (((value) << 0) & 0x00000003)
14995
14996#ifndef __ASSEMBLY__
14997/*
14998 * WARNING: The C register and register group struct declarations are provided for
14999 * convenience and illustrative purposes. They should, however, be used with
15000 * caution as the C language standard provides no guarantees about the alignment or
15001 * atomicity of device memory accesses. The recommended practice for writing
15002 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15003 * alt_write_word() functions.
15004 *
15005 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO5.
15006 */
15007 struct ALT_SYSMGR_PINMUX_MIXED1IO5_s
15008{
15009 uint32_t sel : 2; /* nand_dq0 Mux Selection Field */
15010 uint32_t : 30; /* *UNDEFINED* */
15011};
15012
15013/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO5. */
15014typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO5_s ALT_SYSMGR_PINMUX_MIXED1IO5_t;
15015#endif /* __ASSEMBLY__ */
15016
15017/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO5 register from the beginning of the component. */
15018#define ALT_SYSMGR_PINMUX_MIXED1IO5_OFST 0x114
15019
15020/*
15021 * Register : nand_dq1 Mux Selection Register - MIXED1IO6
15022 *
15023 * This register is used to control the peripherals connected to nand_dq1
15024 *
15025 * Only reset by a cold reset (ignores warm reset).
15026 *
15027 * NOTE: These registers should not be modified after IO configuration.There is no
15028 * support for dynamically changing the Pin Mux selections.
15029 *
15030 * Register Layout
15031 *
15032 * Bits | Access | Reset | Description
15033 * :-------|:-------|:------|:-----------------------------
15034 * [1:0] | RW | 0x0 | nand_dq1 Mux Selection Field
15035 * [31:2] | ??? | 0x0 | *UNDEFINED*
15036 *
15037 */
15038/*
15039 * Field : nand_dq1 Mux Selection Field - sel
15040 *
15041 * Select peripheral signals connected nand_dq1.
15042 *
15043 * 0 : Pin is connected to GPIO/LoanIO number 20.
15044 *
15045 * 1 : Pin is connected to Peripheral signal I2C3.SDA.
15046 *
15047 * 2 : Pin is connected to Peripheral signal RGMII1.MDIO.
15048 *
15049 * 3 : Pin is connected to Peripheral signal NAND.dq1.
15050 *
15051 * Field Access Macros:
15052 *
15053 */
15054/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */
15055#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_LSB 0
15056/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */
15057#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_MSB 1
15058/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */
15059#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_WIDTH 2
15060/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value. */
15061#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET_MSK 0x00000003
15062/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value. */
15063#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_CLR_MSK 0xfffffffc
15064/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */
15065#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_RESET 0x0
15066/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL field value from a register. */
15067#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
15068/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value suitable for setting the register. */
15069#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET(value) (((value) << 0) & 0x00000003)
15070
15071#ifndef __ASSEMBLY__
15072/*
15073 * WARNING: The C register and register group struct declarations are provided for
15074 * convenience and illustrative purposes. They should, however, be used with
15075 * caution as the C language standard provides no guarantees about the alignment or
15076 * atomicity of device memory accesses. The recommended practice for writing
15077 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15078 * alt_write_word() functions.
15079 *
15080 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO6.
15081 */
15082 struct ALT_SYSMGR_PINMUX_MIXED1IO6_s
15083{
15084 uint32_t sel : 2; /* nand_dq1 Mux Selection Field */
15085 uint32_t : 30; /* *UNDEFINED* */
15086};
15087
15088/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO6. */
15089typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO6_s ALT_SYSMGR_PINMUX_MIXED1IO6_t;
15090#endif /* __ASSEMBLY__ */
15091
15092/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO6 register from the beginning of the component. */
15093#define ALT_SYSMGR_PINMUX_MIXED1IO6_OFST 0x118
15094
15095/*
15096 * Register : nand_dq2 Mux Selection Register - MIXED1IO7
15097 *
15098 * This register is used to control the peripherals connected to nand_dq2
15099 *
15100 * Only reset by a cold reset (ignores warm reset).
15101 *
15102 * NOTE: These registers should not be modified after IO configuration.There is no
15103 * support for dynamically changing the Pin Mux selections.
15104 *
15105 * Register Layout
15106 *
15107 * Bits | Access | Reset | Description
15108 * :-------|:-------|:------|:-----------------------------
15109 * [1:0] | RW | 0x0 | nand_dq2 Mux Selection Field
15110 * [31:2] | ??? | 0x0 | *UNDEFINED*
15111 *
15112 */
15113/*
15114 * Field : nand_dq2 Mux Selection Field - sel
15115 *
15116 * Select peripheral signals connected nand_dq2.
15117 *
15118 * 0 : Pin is connected to GPIO/LoanIO number 21.
15119 *
15120 * 1 : Pin is connected to Peripheral signal I2C3.SCL.
15121 *
15122 * 2 : Pin is connected to Peripheral signal RGMII1.MDC.
15123 *
15124 * 3 : Pin is connected to Peripheral signal NAND.dq2.
15125 *
15126 * Field Access Macros:
15127 *
15128 */
15129/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */
15130#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_LSB 0
15131/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */
15132#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_MSB 1
15133/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */
15134#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_WIDTH 2
15135/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value. */
15136#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET_MSK 0x00000003
15137/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value. */
15138#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_CLR_MSK 0xfffffffc
15139/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */
15140#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_RESET 0x0
15141/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL field value from a register. */
15142#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
15143/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value suitable for setting the register. */
15144#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET(value) (((value) << 0) & 0x00000003)
15145
15146#ifndef __ASSEMBLY__
15147/*
15148 * WARNING: The C register and register group struct declarations are provided for
15149 * convenience and illustrative purposes. They should, however, be used with
15150 * caution as the C language standard provides no guarantees about the alignment or
15151 * atomicity of device memory accesses. The recommended practice for writing
15152 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15153 * alt_write_word() functions.
15154 *
15155 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO7.
15156 */
15157 struct ALT_SYSMGR_PINMUX_MIXED1IO7_s
15158{
15159 uint32_t sel : 2; /* nand_dq2 Mux Selection Field */
15160 uint32_t : 30; /* *UNDEFINED* */
15161};
15162
15163/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO7. */
15164typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO7_s ALT_SYSMGR_PINMUX_MIXED1IO7_t;
15165#endif /* __ASSEMBLY__ */
15166
15167/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO7 register from the beginning of the component. */
15168#define ALT_SYSMGR_PINMUX_MIXED1IO7_OFST 0x11c
15169
15170/*
15171 * Register : nand_dq3 Mux Selection Register - MIXED1IO8
15172 *
15173 * This register is used to control the peripherals connected to nand_dq3
15174 *
15175 * Only reset by a cold reset (ignores warm reset).
15176 *
15177 * NOTE: These registers should not be modified after IO configuration.There is no
15178 * support for dynamically changing the Pin Mux selections.
15179 *
15180 * Register Layout
15181 *
15182 * Bits | Access | Reset | Description
15183 * :-------|:-------|:------|:-----------------------------
15184 * [1:0] | RW | 0x0 | nand_dq3 Mux Selection Field
15185 * [31:2] | ??? | 0x0 | *UNDEFINED*
15186 *
15187 */
15188/*
15189 * Field : nand_dq3 Mux Selection Field - sel
15190 *
15191 * Select peripheral signals connected nand_dq3.
15192 *
15193 * 0 : Pin is connected to GPIO/LoanIO number 22.
15194 *
15195 * 1 : Pin is connected to Peripheral signal USB1.D4.
15196 *
15197 * 2 : Pin is connected to Peripheral signal RGMII1.RX_CTL.
15198 *
15199 * 3 : Pin is connected to Peripheral signal NAND.dq3.
15200 *
15201 * Field Access Macros:
15202 *
15203 */
15204/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */
15205#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_LSB 0
15206/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */
15207#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_MSB 1
15208/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */
15209#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_WIDTH 2
15210/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value. */
15211#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET_MSK 0x00000003
15212/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value. */
15213#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_CLR_MSK 0xfffffffc
15214/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */
15215#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_RESET 0x0
15216/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL field value from a register. */
15217#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
15218/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value suitable for setting the register. */
15219#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET(value) (((value) << 0) & 0x00000003)
15220
15221#ifndef __ASSEMBLY__
15222/*
15223 * WARNING: The C register and register group struct declarations are provided for
15224 * convenience and illustrative purposes. They should, however, be used with
15225 * caution as the C language standard provides no guarantees about the alignment or
15226 * atomicity of device memory accesses. The recommended practice for writing
15227 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15228 * alt_write_word() functions.
15229 *
15230 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO8.
15231 */
15232 struct ALT_SYSMGR_PINMUX_MIXED1IO8_s
15233{
15234 uint32_t sel : 2; /* nand_dq3 Mux Selection Field */
15235 uint32_t : 30; /* *UNDEFINED* */
15236};
15237
15238/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO8. */
15239typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO8_s ALT_SYSMGR_PINMUX_MIXED1IO8_t;
15240#endif /* __ASSEMBLY__ */
15241
15242/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO8 register from the beginning of the component. */
15243#define ALT_SYSMGR_PINMUX_MIXED1IO8_OFST 0x120
15244
15245/*
15246 * Register : nand_dq4 Mux Selection Register - MIXED1IO9
15247 *
15248 * This register is used to control the peripherals connected to nand_dq4
15249 *
15250 * Only reset by a cold reset (ignores warm reset).
15251 *
15252 * NOTE: These registers should not be modified after IO configuration.There is no
15253 * support for dynamically changing the Pin Mux selections.
15254 *
15255 * Register Layout
15256 *
15257 * Bits | Access | Reset | Description
15258 * :-------|:-------|:------|:-----------------------------
15259 * [1:0] | RW | 0x0 | nand_dq4 Mux Selection Field
15260 * [31:2] | ??? | 0x0 | *UNDEFINED*
15261 *
15262 */
15263/*
15264 * Field : nand_dq4 Mux Selection Field - sel
15265 *
15266 * Select peripheral signals connected nand_dq4.
15267 *
15268 * 0 : Pin is connected to GPIO/LoanIO number 23.
15269 *
15270 * 1 : Pin is connected to Peripheral signal USB1.D5.
15271 *
15272 * 2 : Pin is connected to Peripheral signal RGMII1.TX_CTL.
15273 *
15274 * 3 : Pin is connected to Peripheral signal NAND.dq4.
15275 *
15276 * Field Access Macros:
15277 *
15278 */
15279/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */
15280#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_LSB 0
15281/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */
15282#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_MSB 1
15283/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */
15284#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_WIDTH 2
15285/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value. */
15286#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET_MSK 0x00000003
15287/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value. */
15288#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_CLR_MSK 0xfffffffc
15289/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */
15290#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_RESET 0x0
15291/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL field value from a register. */
15292#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
15293/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value suitable for setting the register. */
15294#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET(value) (((value) << 0) & 0x00000003)
15295
15296#ifndef __ASSEMBLY__
15297/*
15298 * WARNING: The C register and register group struct declarations are provided for
15299 * convenience and illustrative purposes. They should, however, be used with
15300 * caution as the C language standard provides no guarantees about the alignment or
15301 * atomicity of device memory accesses. The recommended practice for writing
15302 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15303 * alt_write_word() functions.
15304 *
15305 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO9.
15306 */
15307 struct ALT_SYSMGR_PINMUX_MIXED1IO9_s
15308{
15309 uint32_t sel : 2; /* nand_dq4 Mux Selection Field */
15310 uint32_t : 30; /* *UNDEFINED* */
15311};
15312
15313/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO9. */
15314typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO9_s ALT_SYSMGR_PINMUX_MIXED1IO9_t;
15315#endif /* __ASSEMBLY__ */
15316
15317/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO9 register from the beginning of the component. */
15318#define ALT_SYSMGR_PINMUX_MIXED1IO9_OFST 0x124
15319
15320/*
15321 * Register : nand_dq5 Mux Selection Register - MIXED1IO10
15322 *
15323 * This register is used to control the peripherals connected to nand_dq5
15324 *
15325 * Only reset by a cold reset (ignores warm reset).
15326 *
15327 * NOTE: These registers should not be modified after IO configuration.There is no
15328 * support for dynamically changing the Pin Mux selections.
15329 *
15330 * Register Layout
15331 *
15332 * Bits | Access | Reset | Description
15333 * :-------|:-------|:------|:-----------------------------
15334 * [1:0] | RW | 0x0 | nand_dq5 Mux Selection Field
15335 * [31:2] | ??? | 0x0 | *UNDEFINED*
15336 *
15337 */
15338/*
15339 * Field : nand_dq5 Mux Selection Field - sel
15340 *
15341 * Select peripheral signals connected nand_dq5.
15342 *
15343 * 0 : Pin is connected to GPIO/LoanIO number 24.
15344 *
15345 * 1 : Pin is connected to Peripheral signal USB1.D6.
15346 *
15347 * 2 : Pin is connected to Peripheral signal RGMII1.RX_CLK.
15348 *
15349 * 3 : Pin is connected to Peripheral signal NAND.dq5.
15350 *
15351 * Field Access Macros:
15352 *
15353 */
15354/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */
15355#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_LSB 0
15356/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */
15357#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_MSB 1
15358/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */
15359#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_WIDTH 2
15360/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value. */
15361#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET_MSK 0x00000003
15362/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value. */
15363#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_CLR_MSK 0xfffffffc
15364/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */
15365#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_RESET 0x0
15366/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL field value from a register. */
15367#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
15368/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value suitable for setting the register. */
15369#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET(value) (((value) << 0) & 0x00000003)
15370
15371#ifndef __ASSEMBLY__
15372/*
15373 * WARNING: The C register and register group struct declarations are provided for
15374 * convenience and illustrative purposes. They should, however, be used with
15375 * caution as the C language standard provides no guarantees about the alignment or
15376 * atomicity of device memory accesses. The recommended practice for writing
15377 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15378 * alt_write_word() functions.
15379 *
15380 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO10.
15381 */
15382 struct ALT_SYSMGR_PINMUX_MIXED1IO10_s
15383{
15384 uint32_t sel : 2; /* nand_dq5 Mux Selection Field */
15385 uint32_t : 30; /* *UNDEFINED* */
15386};
15387
15388/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO10. */
15389typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO10_s ALT_SYSMGR_PINMUX_MIXED1IO10_t;
15390#endif /* __ASSEMBLY__ */
15391
15392/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO10 register from the beginning of the component. */
15393#define ALT_SYSMGR_PINMUX_MIXED1IO10_OFST 0x128
15394
15395/*
15396 * Register : nand_dq6 Mux Selection Register - MIXED1IO11
15397 *
15398 * This register is used to control the peripherals connected to nand_dq6
15399 *
15400 * Only reset by a cold reset (ignores warm reset).
15401 *
15402 * NOTE: These registers should not be modified after IO configuration.There is no
15403 * support for dynamically changing the Pin Mux selections.
15404 *
15405 * Register Layout
15406 *
15407 * Bits | Access | Reset | Description
15408 * :-------|:-------|:------|:-----------------------------
15409 * [1:0] | RW | 0x0 | nand_dq6 Mux Selection Field
15410 * [31:2] | ??? | 0x0 | *UNDEFINED*
15411 *
15412 */
15413/*
15414 * Field : nand_dq6 Mux Selection Field - sel
15415 *
15416 * Select peripheral signals connected nand_dq6.
15417 *
15418 * 0 : Pin is connected to GPIO/LoanIO number 25.
15419 *
15420 * 1 : Pin is connected to Peripheral signal USB1.D7.
15421 *
15422 * 2 : Pin is connected to Peripheral signal RGMII1.RXD1.
15423 *
15424 * 3 : Pin is connected to Peripheral signal NAND.dq6.
15425 *
15426 * Field Access Macros:
15427 *
15428 */
15429/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */
15430#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_LSB 0
15431/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */
15432#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_MSB 1
15433/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */
15434#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_WIDTH 2
15435/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value. */
15436#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET_MSK 0x00000003
15437/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value. */
15438#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_CLR_MSK 0xfffffffc
15439/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */
15440#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_RESET 0x0
15441/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL field value from a register. */
15442#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
15443/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value suitable for setting the register. */
15444#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET(value) (((value) << 0) & 0x00000003)
15445
15446#ifndef __ASSEMBLY__
15447/*
15448 * WARNING: The C register and register group struct declarations are provided for
15449 * convenience and illustrative purposes. They should, however, be used with
15450 * caution as the C language standard provides no guarantees about the alignment or
15451 * atomicity of device memory accesses. The recommended practice for writing
15452 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15453 * alt_write_word() functions.
15454 *
15455 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO11.
15456 */
15457 struct ALT_SYSMGR_PINMUX_MIXED1IO11_s
15458{
15459 uint32_t sel : 2; /* nand_dq6 Mux Selection Field */
15460 uint32_t : 30; /* *UNDEFINED* */
15461};
15462
15463/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO11. */
15464typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO11_s ALT_SYSMGR_PINMUX_MIXED1IO11_t;
15465#endif /* __ASSEMBLY__ */
15466
15467/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO11 register from the beginning of the component. */
15468#define ALT_SYSMGR_PINMUX_MIXED1IO11_OFST 0x12c
15469
15470/*
15471 * Register : nand_dq7 Mux Selection Register - MIXED1IO12
15472 *
15473 * This register is used to control the peripherals connected to nand_dq7
15474 *
15475 * Only reset by a cold reset (ignores warm reset).
15476 *
15477 * NOTE: These registers should not be modified after IO configuration.There is no
15478 * support for dynamically changing the Pin Mux selections.
15479 *
15480 * Register Layout
15481 *
15482 * Bits | Access | Reset | Description
15483 * :-------|:-------|:------|:-----------------------------
15484 * [1:0] | RW | 0x0 | nand_dq7 Mux Selection Field
15485 * [31:2] | ??? | 0x0 | *UNDEFINED*
15486 *
15487 */
15488/*
15489 * Field : nand_dq7 Mux Selection Field - sel
15490 *
15491 * Select peripheral signals connected nand_dq7.
15492 *
15493 * 0 : Pin is connected to GPIO/LoanIO number 26.
15494 *
15495 * 1 : Pin is connected to Peripheral signal not applicable.
15496 *
15497 * 2 : Pin is connected to Peripheral signal RGMII1.RXD2.
15498 *
15499 * 3 : Pin is connected to Peripheral signal NAND.dq7.
15500 *
15501 * Field Access Macros:
15502 *
15503 */
15504/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */
15505#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_LSB 0
15506/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */
15507#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_MSB 1
15508/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */
15509#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_WIDTH 2
15510/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value. */
15511#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET_MSK 0x00000003
15512/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value. */
15513#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_CLR_MSK 0xfffffffc
15514/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */
15515#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_RESET 0x0
15516/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL field value from a register. */
15517#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_GET(value) (((value) & 0x00000003) >> 0)
15518/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value suitable for setting the register. */
15519#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET(value) (((value) << 0) & 0x00000003)
15520
15521#ifndef __ASSEMBLY__
15522/*
15523 * WARNING: The C register and register group struct declarations are provided for
15524 * convenience and illustrative purposes. They should, however, be used with
15525 * caution as the C language standard provides no guarantees about the alignment or
15526 * atomicity of device memory accesses. The recommended practice for writing
15527 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15528 * alt_write_word() functions.
15529 *
15530 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO12.
15531 */
15532 struct ALT_SYSMGR_PINMUX_MIXED1IO12_s
15533{
15534 uint32_t sel : 2; /* nand_dq7 Mux Selection Field */
15535 uint32_t : 30; /* *UNDEFINED* */
15536};
15537
15538/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO12. */
15539typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO12_s ALT_SYSMGR_PINMUX_MIXED1IO12_t;
15540#endif /* __ASSEMBLY__ */
15541
15542/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO12 register from the beginning of the component. */
15543#define ALT_SYSMGR_PINMUX_MIXED1IO12_OFST 0x130
15544
15545/*
15546 * Register : nand_wp Mux Selection Register - MIXED1IO13
15547 *
15548 * This register is used to control the peripherals connected to nand_wp
15549 *
15550 * Only reset by a cold reset (ignores warm reset).
15551 *
15552 * NOTE: These registers should not be modified after IO configuration.There is no
15553 * support for dynamically changing the Pin Mux selections.
15554 *
15555 * Register Layout
15556 *
15557 * Bits | Access | Reset | Description
15558 * :-------|:-------|:------|:----------------------------
15559 * [1:0] | RW | 0x0 | nand_wp Mux Selection Field
15560 * [31:2] | ??? | 0x0 | *UNDEFINED*
15561 *
15562 */
15563/*
15564 * Field : nand_wp Mux Selection Field - sel
15565 *
15566 * Select peripheral signals connected nand_wp.
15567 *
15568 * 0 : Pin is connected to GPIO/LoanIO number 27.
15569 *
15570 * 1 : Pin is connected to Peripheral signal QSPI.SS2.
15571 *
15572 * 2 : Pin is connected to Peripheral signal RGMII1.RXD3.
15573 *
15574 * 3 : Pin is connected to Peripheral signal NAND.wp.
15575 *
15576 * Field Access Macros:
15577 *
15578 */
15579/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */
15580#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_LSB 0
15581/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */
15582#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_MSB 1
15583/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */
15584#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_WIDTH 2
15585/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value. */
15586#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET_MSK 0x00000003
15587/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value. */
15588#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_CLR_MSK 0xfffffffc
15589/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */
15590#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_RESET 0x0
15591/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL field value from a register. */
15592#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_GET(value) (((value) & 0x00000003) >> 0)
15593/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value suitable for setting the register. */
15594#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET(value) (((value) << 0) & 0x00000003)
15595
15596#ifndef __ASSEMBLY__
15597/*
15598 * WARNING: The C register and register group struct declarations are provided for
15599 * convenience and illustrative purposes. They should, however, be used with
15600 * caution as the C language standard provides no guarantees about the alignment or
15601 * atomicity of device memory accesses. The recommended practice for writing
15602 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15603 * alt_write_word() functions.
15604 *
15605 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO13.
15606 */
15607 struct ALT_SYSMGR_PINMUX_MIXED1IO13_s
15608{
15609 uint32_t sel : 2; /* nand_wp Mux Selection Field */
15610 uint32_t : 30; /* *UNDEFINED* */
15611};
15612
15613/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO13. */
15614typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO13_s ALT_SYSMGR_PINMUX_MIXED1IO13_t;
15615#endif /* __ASSEMBLY__ */
15616
15617/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO13 register from the beginning of the component. */
15618#define ALT_SYSMGR_PINMUX_MIXED1IO13_OFST 0x134
15619
15620/*
15621 * Register : nand_we Mux Selection Register - MIXED1IO14
15622 *
15623 * This register is used to control the peripherals connected to nand_we
15624 *
15625 * Only reset by a cold reset (ignores warm reset).
15626 *
15627 * NOTE: These registers should not be modified after IO configuration.There is no
15628 * support for dynamically changing the Pin Mux selections.
15629 *
15630 * Register Layout
15631 *
15632 * Bits | Access | Reset | Description
15633 * :-------|:-------|:------|:----------------------------
15634 * [1:0] | RW | 0x0 | nand_we Mux Selection Field
15635 * [31:2] | ??? | 0x0 | *UNDEFINED*
15636 *
15637 */
15638/*
15639 * Field : nand_we Mux Selection Field - sel
15640 *
15641 * Select peripheral signals connected nand_we.
15642 *
15643 * 0 : Pin is connected to GPIO/LoanIO number 28.
15644 *
15645 * 1 : Pin is connected to Peripheral signal not applicable.
15646 *
15647 * 2 : Pin is connected to Peripheral signal QSPI.SS1.
15648 *
15649 * 3 : Pin is connected to Peripheral signal NAND.we.
15650 *
15651 * Field Access Macros:
15652 *
15653 */
15654/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */
15655#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_LSB 0
15656/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */
15657#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_MSB 1
15658/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */
15659#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_WIDTH 2
15660/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value. */
15661#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET_MSK 0x00000003
15662/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value. */
15663#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_CLR_MSK 0xfffffffc
15664/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */
15665#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_RESET 0x0
15666/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL field value from a register. */
15667#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_GET(value) (((value) & 0x00000003) >> 0)
15668/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value suitable for setting the register. */
15669#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET(value) (((value) << 0) & 0x00000003)
15670
15671#ifndef __ASSEMBLY__
15672/*
15673 * WARNING: The C register and register group struct declarations are provided for
15674 * convenience and illustrative purposes. They should, however, be used with
15675 * caution as the C language standard provides no guarantees about the alignment or
15676 * atomicity of device memory accesses. The recommended practice for writing
15677 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15678 * alt_write_word() functions.
15679 *
15680 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO14.
15681 */
15682 struct ALT_SYSMGR_PINMUX_MIXED1IO14_s
15683{
15684 uint32_t sel : 2; /* nand_we Mux Selection Field */
15685 uint32_t : 30; /* *UNDEFINED* */
15686};
15687
15688/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO14. */
15689typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO14_s ALT_SYSMGR_PINMUX_MIXED1IO14_t;
15690#endif /* __ASSEMBLY__ */
15691
15692/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO14 register from the beginning of the component. */
15693#define ALT_SYSMGR_PINMUX_MIXED1IO14_OFST 0x138
15694
15695/*
15696 * Register : qspi_io0 Mux Selection Register - MIXED1IO15
15697 *
15698 * This register is used to control the peripherals connected to qspi_io0
15699 *
15700 * Only reset by a cold reset (ignores warm reset).
15701 *
15702 * NOTE: These registers should not be modified after IO configuration.There is no
15703 * support for dynamically changing the Pin Mux selections.
15704 *
15705 * Register Layout
15706 *
15707 * Bits | Access | Reset | Description
15708 * :-------|:-------|:------|:-----------------------------
15709 * [1:0] | RW | 0x0 | qspi_io0 Mux Selection Field
15710 * [31:2] | ??? | 0x0 | *UNDEFINED*
15711 *
15712 */
15713/*
15714 * Field : qspi_io0 Mux Selection Field - sel
15715 *
15716 * Select peripheral signals connected qspi_io0.
15717 *
15718 * 0 : Pin is connected to GPIO/LoanIO number 29.
15719 *
15720 * 1 : Pin is connected to Peripheral signal USB1.CLK.
15721 *
15722 * 2 : Pin is connected to Peripheral signal not applicable.
15723 *
15724 * 3 : Pin is connected to Peripheral signal QSPI.IO0.
15725 *
15726 * Field Access Macros:
15727 *
15728 */
15729/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */
15730#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_LSB 0
15731/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */
15732#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_MSB 1
15733/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */
15734#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_WIDTH 2
15735/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value. */
15736#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET_MSK 0x00000003
15737/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value. */
15738#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_CLR_MSK 0xfffffffc
15739/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */
15740#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_RESET 0x0
15741/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL field value from a register. */
15742#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_GET(value) (((value) & 0x00000003) >> 0)
15743/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value suitable for setting the register. */
15744#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET(value) (((value) << 0) & 0x00000003)
15745
15746#ifndef __ASSEMBLY__
15747/*
15748 * WARNING: The C register and register group struct declarations are provided for
15749 * convenience and illustrative purposes. They should, however, be used with
15750 * caution as the C language standard provides no guarantees about the alignment or
15751 * atomicity of device memory accesses. The recommended practice for writing
15752 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15753 * alt_write_word() functions.
15754 *
15755 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO15.
15756 */
15757 struct ALT_SYSMGR_PINMUX_MIXED1IO15_s
15758{
15759 uint32_t sel : 2; /* qspi_io0 Mux Selection Field */
15760 uint32_t : 30; /* *UNDEFINED* */
15761};
15762
15763/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO15. */
15764typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO15_s ALT_SYSMGR_PINMUX_MIXED1IO15_t;
15765#endif /* __ASSEMBLY__ */
15766
15767/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO15 register from the beginning of the component. */
15768#define ALT_SYSMGR_PINMUX_MIXED1IO15_OFST 0x13c
15769
15770/*
15771 * Register : qspi_io1 Mux Selection Register - MIXED1IO16
15772 *
15773 * This register is used to control the peripherals connected to qspi_io1
15774 *
15775 * Only reset by a cold reset (ignores warm reset).
15776 *
15777 * NOTE: These registers should not be modified after IO configuration.There is no
15778 * support for dynamically changing the Pin Mux selections.
15779 *
15780 * Register Layout
15781 *
15782 * Bits | Access | Reset | Description
15783 * :-------|:-------|:------|:-----------------------------
15784 * [1:0] | RW | 0x0 | qspi_io1 Mux Selection Field
15785 * [31:2] | ??? | 0x0 | *UNDEFINED*
15786 *
15787 */
15788/*
15789 * Field : qspi_io1 Mux Selection Field - sel
15790 *
15791 * Select peripheral signals connected qspi_io1.
15792 *
15793 * 0 : Pin is connected to GPIO/LoanIO number 30.
15794 *
15795 * 1 : Pin is connected to Peripheral signal USB1.STP.
15796 *
15797 * 2 : Pin is connected to Peripheral signal not applicable.
15798 *
15799 * 3 : Pin is connected to Peripheral signal QSPI.IO1.
15800 *
15801 * Field Access Macros:
15802 *
15803 */
15804/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */
15805#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_LSB 0
15806/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */
15807#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_MSB 1
15808/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */
15809#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_WIDTH 2
15810/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value. */
15811#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET_MSK 0x00000003
15812/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value. */
15813#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_CLR_MSK 0xfffffffc
15814/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */
15815#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_RESET 0x0
15816/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL field value from a register. */
15817#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_GET(value) (((value) & 0x00000003) >> 0)
15818/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value suitable for setting the register. */
15819#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET(value) (((value) << 0) & 0x00000003)
15820
15821#ifndef __ASSEMBLY__
15822/*
15823 * WARNING: The C register and register group struct declarations are provided for
15824 * convenience and illustrative purposes. They should, however, be used with
15825 * caution as the C language standard provides no guarantees about the alignment or
15826 * atomicity of device memory accesses. The recommended practice for writing
15827 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15828 * alt_write_word() functions.
15829 *
15830 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO16.
15831 */
15832 struct ALT_SYSMGR_PINMUX_MIXED1IO16_s
15833{
15834 uint32_t sel : 2; /* qspi_io1 Mux Selection Field */
15835 uint32_t : 30; /* *UNDEFINED* */
15836};
15837
15838/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO16. */
15839typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO16_s ALT_SYSMGR_PINMUX_MIXED1IO16_t;
15840#endif /* __ASSEMBLY__ */
15841
15842/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO16 register from the beginning of the component. */
15843#define ALT_SYSMGR_PINMUX_MIXED1IO16_OFST 0x140
15844
15845/*
15846 * Register : qspi_io2 Mux Selection Register - MIXED1IO17
15847 *
15848 * This register is used to control the peripherals connected to qspi_io2
15849 *
15850 * Only reset by a cold reset (ignores warm reset).
15851 *
15852 * NOTE: These registers should not be modified after IO configuration.There is no
15853 * support for dynamically changing the Pin Mux selections.
15854 *
15855 * Register Layout
15856 *
15857 * Bits | Access | Reset | Description
15858 * :-------|:-------|:------|:-----------------------------
15859 * [1:0] | RW | 0x0 | qspi_io2 Mux Selection Field
15860 * [31:2] | ??? | 0x0 | *UNDEFINED*
15861 *
15862 */
15863/*
15864 * Field : qspi_io2 Mux Selection Field - sel
15865 *
15866 * Select peripheral signals connected qspi_io2.
15867 *
15868 * 0 : Pin is connected to GPIO/LoanIO number 31.
15869 *
15870 * 1 : Pin is connected to Peripheral signal USB1.DIR.
15871 *
15872 * 2 : Pin is connected to Peripheral signal not applicable.
15873 *
15874 * 3 : Pin is connected to Peripheral signal QSPI.IO2.
15875 *
15876 * Field Access Macros:
15877 *
15878 */
15879/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */
15880#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_LSB 0
15881/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */
15882#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_MSB 1
15883/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */
15884#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_WIDTH 2
15885/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value. */
15886#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET_MSK 0x00000003
15887/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value. */
15888#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_CLR_MSK 0xfffffffc
15889/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */
15890#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_RESET 0x0
15891/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL field value from a register. */
15892#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_GET(value) (((value) & 0x00000003) >> 0)
15893/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value suitable for setting the register. */
15894#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET(value) (((value) << 0) & 0x00000003)
15895
15896#ifndef __ASSEMBLY__
15897/*
15898 * WARNING: The C register and register group struct declarations are provided for
15899 * convenience and illustrative purposes. They should, however, be used with
15900 * caution as the C language standard provides no guarantees about the alignment or
15901 * atomicity of device memory accesses. The recommended practice for writing
15902 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15903 * alt_write_word() functions.
15904 *
15905 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO17.
15906 */
15907 struct ALT_SYSMGR_PINMUX_MIXED1IO17_s
15908{
15909 uint32_t sel : 2; /* qspi_io2 Mux Selection Field */
15910 uint32_t : 30; /* *UNDEFINED* */
15911};
15912
15913/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO17. */
15914typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO17_s ALT_SYSMGR_PINMUX_MIXED1IO17_t;
15915#endif /* __ASSEMBLY__ */
15916
15917/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO17 register from the beginning of the component. */
15918#define ALT_SYSMGR_PINMUX_MIXED1IO17_OFST 0x144
15919
15920/*
15921 * Register : qspi_io3 Mux Selection Register - MIXED1IO18
15922 *
15923 * This register is used to control the peripherals connected to qspi_io3
15924 *
15925 * Only reset by a cold reset (ignores warm reset).
15926 *
15927 * NOTE: These registers should not be modified after IO configuration.There is no
15928 * support for dynamically changing the Pin Mux selections.
15929 *
15930 * Register Layout
15931 *
15932 * Bits | Access | Reset | Description
15933 * :-------|:-------|:------|:-----------------------------
15934 * [1:0] | RW | 0x0 | qspi_io3 Mux Selection Field
15935 * [31:2] | ??? | 0x0 | *UNDEFINED*
15936 *
15937 */
15938/*
15939 * Field : qspi_io3 Mux Selection Field - sel
15940 *
15941 * Select peripheral signals connected qspi_io3.
15942 *
15943 * 0 : Pin is connected to GPIO/LoanIO number 32.
15944 *
15945 * 1 : Pin is connected to Peripheral signal USB1.NXT.
15946 *
15947 * 2 : Pin is connected to Peripheral signal not applicable.
15948 *
15949 * 3 : Pin is connected to Peripheral signal QSPI.IO3.
15950 *
15951 * Field Access Macros:
15952 *
15953 */
15954/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */
15955#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_LSB 0
15956/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */
15957#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_MSB 1
15958/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */
15959#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_WIDTH 2
15960/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value. */
15961#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET_MSK 0x00000003
15962/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value. */
15963#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_CLR_MSK 0xfffffffc
15964/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */
15965#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_RESET 0x0
15966/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL field value from a register. */
15967#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_GET(value) (((value) & 0x00000003) >> 0)
15968/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value suitable for setting the register. */
15969#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET(value) (((value) << 0) & 0x00000003)
15970
15971#ifndef __ASSEMBLY__
15972/*
15973 * WARNING: The C register and register group struct declarations are provided for
15974 * convenience and illustrative purposes. They should, however, be used with
15975 * caution as the C language standard provides no guarantees about the alignment or
15976 * atomicity of device memory accesses. The recommended practice for writing
15977 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15978 * alt_write_word() functions.
15979 *
15980 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO18.
15981 */
15982 struct ALT_SYSMGR_PINMUX_MIXED1IO18_s
15983{
15984 uint32_t sel : 2; /* qspi_io3 Mux Selection Field */
15985 uint32_t : 30; /* *UNDEFINED* */
15986};
15987
15988/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO18. */
15989typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO18_s ALT_SYSMGR_PINMUX_MIXED1IO18_t;
15990#endif /* __ASSEMBLY__ */
15991
15992/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO18 register from the beginning of the component. */
15993#define ALT_SYSMGR_PINMUX_MIXED1IO18_OFST 0x148
15994
15995/*
15996 * Register : qspi_ss0 Mux Selection Register - MIXED1IO19
15997 *
15998 * This register is used to control the peripherals connected to qspi_ss0
15999 *
16000 * Only reset by a cold reset (ignores warm reset).
16001 *
16002 * NOTE: These registers should not be modified after IO configuration.There is no
16003 * support for dynamically changing the Pin Mux selections.
16004 *
16005 * Register Layout
16006 *
16007 * Bits | Access | Reset | Description
16008 * :-------|:-------|:------|:-----------------------------
16009 * [1:0] | RW | 0x0 | qspi_ss0 Mux Selection Field
16010 * [31:2] | ??? | 0x0 | *UNDEFINED*
16011 *
16012 */
16013/*
16014 * Field : qspi_ss0 Mux Selection Field - sel
16015 *
16016 * Select peripheral signals connected qspi_ss0.
16017 *
16018 * 0 : Pin is connected to GPIO/LoanIO number 33.
16019 *
16020 * 1 : Pin is connected to Peripheral signal not applicable.
16021 *
16022 * 2 : Pin is connected to Peripheral signal not applicable.
16023 *
16024 * 3 : Pin is connected to Peripheral signal QSPI.SS0.
16025 *
16026 * Field Access Macros:
16027 *
16028 */
16029/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */
16030#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_LSB 0
16031/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */
16032#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_MSB 1
16033/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */
16034#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_WIDTH 2
16035/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value. */
16036#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET_MSK 0x00000003
16037/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value. */
16038#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_CLR_MSK 0xfffffffc
16039/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */
16040#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_RESET 0x0
16041/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL field value from a register. */
16042#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_GET(value) (((value) & 0x00000003) >> 0)
16043/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value suitable for setting the register. */
16044#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET(value) (((value) << 0) & 0x00000003)
16045
16046#ifndef __ASSEMBLY__
16047/*
16048 * WARNING: The C register and register group struct declarations are provided for
16049 * convenience and illustrative purposes. They should, however, be used with
16050 * caution as the C language standard provides no guarantees about the alignment or
16051 * atomicity of device memory accesses. The recommended practice for writing
16052 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16053 * alt_write_word() functions.
16054 *
16055 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO19.
16056 */
16057 struct ALT_SYSMGR_PINMUX_MIXED1IO19_s
16058{
16059 uint32_t sel : 2; /* qspi_ss0 Mux Selection Field */
16060 uint32_t : 30; /* *UNDEFINED* */
16061};
16062
16063/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO19. */
16064typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO19_s ALT_SYSMGR_PINMUX_MIXED1IO19_t;
16065#endif /* __ASSEMBLY__ */
16066
16067/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO19 register from the beginning of the component. */
16068#define ALT_SYSMGR_PINMUX_MIXED1IO19_OFST 0x14c
16069
16070/*
16071 * Register : qpsi_clk Mux Selection Register - MIXED1IO20
16072 *
16073 * This register is used to control the peripherals connected to qpsi_clk
16074 *
16075 * Only reset by a cold reset (ignores warm reset).
16076 *
16077 * NOTE: These registers should not be modified after IO configuration.There is no
16078 * support for dynamically changing the Pin Mux selections.
16079 *
16080 * Register Layout
16081 *
16082 * Bits | Access | Reset | Description
16083 * :-------|:-------|:------|:-----------------------------
16084 * [1:0] | RW | 0x0 | qpsi_clk Mux Selection Field
16085 * [31:2] | ??? | 0x0 | *UNDEFINED*
16086 *
16087 */
16088/*
16089 * Field : qpsi_clk Mux Selection Field - sel
16090 *
16091 * Select peripheral signals connected qpsi_clk.
16092 *
16093 * 0 : Pin is connected to GPIO/LoanIO number 34.
16094 *
16095 * 1 : Pin is connected to Peripheral signal not applicable.
16096 *
16097 * 2 : Pin is connected to Peripheral signal not applicable.
16098 *
16099 * 3 : Pin is connected to Peripheral signal QSPI.CLK.
16100 *
16101 * Field Access Macros:
16102 *
16103 */
16104/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */
16105#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_LSB 0
16106/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */
16107#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_MSB 1
16108/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */
16109#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_WIDTH 2
16110/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value. */
16111#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET_MSK 0x00000003
16112/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value. */
16113#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_CLR_MSK 0xfffffffc
16114/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */
16115#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_RESET 0x0
16116/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL field value from a register. */
16117#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_GET(value) (((value) & 0x00000003) >> 0)
16118/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value suitable for setting the register. */
16119#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET(value) (((value) << 0) & 0x00000003)
16120
16121#ifndef __ASSEMBLY__
16122/*
16123 * WARNING: The C register and register group struct declarations are provided for
16124 * convenience and illustrative purposes. They should, however, be used with
16125 * caution as the C language standard provides no guarantees about the alignment or
16126 * atomicity of device memory accesses. The recommended practice for writing
16127 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16128 * alt_write_word() functions.
16129 *
16130 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO20.
16131 */
16132 struct ALT_SYSMGR_PINMUX_MIXED1IO20_s
16133{
16134 uint32_t sel : 2; /* qpsi_clk Mux Selection Field */
16135 uint32_t : 30; /* *UNDEFINED* */
16136};
16137
16138/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO20. */
16139typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO20_s ALT_SYSMGR_PINMUX_MIXED1IO20_t;
16140#endif /* __ASSEMBLY__ */
16141
16142/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO20 register from the beginning of the component. */
16143#define ALT_SYSMGR_PINMUX_MIXED1IO20_OFST 0x150
16144
16145/*
16146 * Register : qspi_ss1 Mux Selection Register - MIXED1IO21
16147 *
16148 * This register is used to control the peripherals connected to qspi_ss1
16149 *
16150 * Only reset by a cold reset (ignores warm reset).
16151 *
16152 * NOTE: These registers should not be modified after IO configuration.There is no
16153 * support for dynamically changing the Pin Mux selections.
16154 *
16155 * Register Layout
16156 *
16157 * Bits | Access | Reset | Description
16158 * :-------|:-------|:------|:-----------------------------
16159 * [1:0] | RW | 0x0 | qspi_ss1 Mux Selection Field
16160 * [31:2] | ??? | 0x0 | *UNDEFINED*
16161 *
16162 */
16163/*
16164 * Field : qspi_ss1 Mux Selection Field - sel
16165 *
16166 * Select peripheral signals connected qspi_ss1.
16167 *
16168 * 0 : Pin is connected to GPIO/LoanIO number 35.
16169 *
16170 * 1 : Pin is connected to Peripheral signal not applicable.
16171 *
16172 * 2 : Pin is connected to Peripheral signal not applicable.
16173 *
16174 * 3 : Pin is connected to Peripheral signal QSPI.SS1.
16175 *
16176 * Field Access Macros:
16177 *
16178 */
16179/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */
16180#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_LSB 0
16181/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */
16182#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_MSB 1
16183/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */
16184#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_WIDTH 2
16185/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value. */
16186#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET_MSK 0x00000003
16187/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value. */
16188#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_CLR_MSK 0xfffffffc
16189/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */
16190#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_RESET 0x0
16191/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL field value from a register. */
16192#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_GET(value) (((value) & 0x00000003) >> 0)
16193/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value suitable for setting the register. */
16194#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET(value) (((value) << 0) & 0x00000003)
16195
16196#ifndef __ASSEMBLY__
16197/*
16198 * WARNING: The C register and register group struct declarations are provided for
16199 * convenience and illustrative purposes. They should, however, be used with
16200 * caution as the C language standard provides no guarantees about the alignment or
16201 * atomicity of device memory accesses. The recommended practice for writing
16202 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16203 * alt_write_word() functions.
16204 *
16205 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO21.
16206 */
16207 struct ALT_SYSMGR_PINMUX_MIXED1IO21_s
16208{
16209 uint32_t sel : 2; /* qspi_ss1 Mux Selection Field */
16210 uint32_t : 30; /* *UNDEFINED* */
16211};
16212
16213/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO21. */
16214typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO21_s ALT_SYSMGR_PINMUX_MIXED1IO21_t;
16215#endif /* __ASSEMBLY__ */
16216
16217/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO21 register from the beginning of the component. */
16218#define ALT_SYSMGR_PINMUX_MIXED1IO21_OFST 0x154
16219
16220/*
16221 * Register : emac1_mdio Mux Selection Register - MIXED2IO0
16222 *
16223 * This register is used to control the peripherals connected to emac1_mdio
16224 *
16225 * Only reset by a cold reset (ignores warm reset).
16226 *
16227 * NOTE: These registers should not be modified after IO configuration.There is no
16228 * support for dynamically changing the Pin Mux selections.
16229 *
16230 * Register Layout
16231 *
16232 * Bits | Access | Reset | Description
16233 * :-------|:-------|:------|:-------------------------------
16234 * [1:0] | RW | 0x0 | emac1_mdio Mux Selection Field
16235 * [31:2] | ??? | 0x0 | *UNDEFINED*
16236 *
16237 */
16238/*
16239 * Field : emac1_mdio Mux Selection Field - sel
16240 *
16241 * Select peripheral signals connected emac1_mdio.
16242 *
16243 * 0 : Pin is connected to GPIO/LoanIO number 54.
16244 *
16245 * 1 : Pin is connected to Peripheral signal SPIS0.CLK.
16246 *
16247 * 2 : Pin is connected to Peripheral signal SPIM0.CLK.
16248 *
16249 * 3 : Pin is connected to Peripheral signal RGMII1.MDIO.
16250 *
16251 * Field Access Macros:
16252 *
16253 */
16254/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */
16255#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_LSB 0
16256/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */
16257#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_MSB 1
16258/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */
16259#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_WIDTH 2
16260/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value. */
16261#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET_MSK 0x00000003
16262/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value. */
16263#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_CLR_MSK 0xfffffffc
16264/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */
16265#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_RESET 0x0
16266/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL field value from a register. */
16267#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
16268/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value suitable for setting the register. */
16269#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET(value) (((value) << 0) & 0x00000003)
16270
16271#ifndef __ASSEMBLY__
16272/*
16273 * WARNING: The C register and register group struct declarations are provided for
16274 * convenience and illustrative purposes. They should, however, be used with
16275 * caution as the C language standard provides no guarantees about the alignment or
16276 * atomicity of device memory accesses. The recommended practice for writing
16277 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16278 * alt_write_word() functions.
16279 *
16280 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO0.
16281 */
16282 struct ALT_SYSMGR_PINMUX_MIXED2IO0_s
16283{
16284 uint32_t sel : 2; /* emac1_mdio Mux Selection Field */
16285 uint32_t : 30; /* *UNDEFINED* */
16286};
16287
16288/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO0. */
16289typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO0_s ALT_SYSMGR_PINMUX_MIXED2IO0_t;
16290#endif /* __ASSEMBLY__ */
16291
16292/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO0 register from the beginning of the component. */
16293#define ALT_SYSMGR_PINMUX_MIXED2IO0_OFST 0x158
16294
16295/*
16296 * Register : emac1_mdc Mux Selection Register - MIXED2IO1
16297 *
16298 * This register is used to control the peripherals connected to emac1_mdc
16299 *
16300 * Only reset by a cold reset (ignores warm reset).
16301 *
16302 * NOTE: These registers should not be modified after IO configuration.There is no
16303 * support for dynamically changing the Pin Mux selections.
16304 *
16305 * Register Layout
16306 *
16307 * Bits | Access | Reset | Description
16308 * :-------|:-------|:------|:------------------------------
16309 * [1:0] | RW | 0x0 | emac1_mdc Mux Selection Field
16310 * [31:2] | ??? | 0x0 | *UNDEFINED*
16311 *
16312 */
16313/*
16314 * Field : emac1_mdc Mux Selection Field - sel
16315 *
16316 * Select peripheral signals connected emac1_mdc.
16317 *
16318 * 0 : Pin is connected to GPIO/LoanIO number 55.
16319 *
16320 * 1 : Pin is connected to Peripheral signal SPIS0.MOSI.
16321 *
16322 * 2 : Pin is connected to Peripheral signal SPIM0.MOSI.
16323 *
16324 * 3 : Pin is connected to Peripheral signal RGMII1.MDC.
16325 *
16326 * Field Access Macros:
16327 *
16328 */
16329/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */
16330#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_LSB 0
16331/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */
16332#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_MSB 1
16333/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */
16334#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_WIDTH 2
16335/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value. */
16336#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET_MSK 0x00000003
16337/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value. */
16338#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_CLR_MSK 0xfffffffc
16339/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */
16340#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_RESET 0x0
16341/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL field value from a register. */
16342#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
16343/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value suitable for setting the register. */
16344#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET(value) (((value) << 0) & 0x00000003)
16345
16346#ifndef __ASSEMBLY__
16347/*
16348 * WARNING: The C register and register group struct declarations are provided for
16349 * convenience and illustrative purposes. They should, however, be used with
16350 * caution as the C language standard provides no guarantees about the alignment or
16351 * atomicity of device memory accesses. The recommended practice for writing
16352 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16353 * alt_write_word() functions.
16354 *
16355 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO1.
16356 */
16357 struct ALT_SYSMGR_PINMUX_MIXED2IO1_s
16358{
16359 uint32_t sel : 2; /* emac1_mdc Mux Selection Field */
16360 uint32_t : 30; /* *UNDEFINED* */
16361};
16362
16363/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO1. */
16364typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO1_s ALT_SYSMGR_PINMUX_MIXED2IO1_t;
16365#endif /* __ASSEMBLY__ */
16366
16367/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO1 register from the beginning of the component. */
16368#define ALT_SYSMGR_PINMUX_MIXED2IO1_OFST 0x15c
16369
16370/*
16371 * Register : emac1_tx_d2 Mux Selection Register - MIXED2IO2
16372 *
16373 * This register is used to control the peripherals connected to emac1_tx_d2
16374 *
16375 * Only reset by a cold reset (ignores warm reset).
16376 *
16377 * NOTE: These registers should not be modified after IO configuration.There is no
16378 * support for dynamically changing the Pin Mux selections.
16379 *
16380 * Register Layout
16381 *
16382 * Bits | Access | Reset | Description
16383 * :-------|:-------|:------|:--------------------------------
16384 * [1:0] | RW | 0x0 | emac1_tx_d2 Mux Selection Field
16385 * [31:2] | ??? | 0x0 | *UNDEFINED*
16386 *
16387 */
16388/*
16389 * Field : emac1_tx_d2 Mux Selection Field - sel
16390 *
16391 * Select peripheral signals connected emac1_tx_d2.
16392 *
16393 * 0 : Pin is connected to GPIO/LoanIO number 56.
16394 *
16395 * 1 : Pin is connected to Peripheral signal SPIS0.MISO.
16396 *
16397 * 2 : Pin is connected to Peripheral signal SPIM0.MISO.
16398 *
16399 * 3 : Pin is connected to Peripheral signal RGMII1.TXD2.
16400 *
16401 * Field Access Macros:
16402 *
16403 */
16404/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */
16405#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_LSB 0
16406/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */
16407#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_MSB 1
16408/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */
16409#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_WIDTH 2
16410/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value. */
16411#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET_MSK 0x00000003
16412/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value. */
16413#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_CLR_MSK 0xfffffffc
16414/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */
16415#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_RESET 0x0
16416/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL field value from a register. */
16417#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
16418/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value suitable for setting the register. */
16419#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET(value) (((value) << 0) & 0x00000003)
16420
16421#ifndef __ASSEMBLY__
16422/*
16423 * WARNING: The C register and register group struct declarations are provided for
16424 * convenience and illustrative purposes. They should, however, be used with
16425 * caution as the C language standard provides no guarantees about the alignment or
16426 * atomicity of device memory accesses. The recommended practice for writing
16427 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16428 * alt_write_word() functions.
16429 *
16430 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO2.
16431 */
16432 struct ALT_SYSMGR_PINMUX_MIXED2IO2_s
16433{
16434 uint32_t sel : 2; /* emac1_tx_d2 Mux Selection Field */
16435 uint32_t : 30; /* *UNDEFINED* */
16436};
16437
16438/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO2. */
16439typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO2_s ALT_SYSMGR_PINMUX_MIXED2IO2_t;
16440#endif /* __ASSEMBLY__ */
16441
16442/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO2 register from the beginning of the component. */
16443#define ALT_SYSMGR_PINMUX_MIXED2IO2_OFST 0x160
16444
16445/*
16446 * Register : emac1_tx_d3 Mux Selection Register - MIXED2IO3
16447 *
16448 * This register is used to control the peripherals connected to emac1_tx_d3
16449 *
16450 * Only reset by a cold reset (ignores warm reset).
16451 *
16452 * NOTE: These registers should not be modified after IO configuration.There is no
16453 * support for dynamically changing the Pin Mux selections.
16454 *
16455 * Register Layout
16456 *
16457 * Bits | Access | Reset | Description
16458 * :-------|:-------|:------|:--------------------------------
16459 * [1:0] | RW | 0x0 | emac1_tx_d3 Mux Selection Field
16460 * [31:2] | ??? | 0x0 | *UNDEFINED*
16461 *
16462 */
16463/*
16464 * Field : emac1_tx_d3 Mux Selection Field - sel
16465 *
16466 * Select peripheral signals connected emac1_tx_d3.
16467 *
16468 * 0 : Pin is connected to GPIO/LoanIO number 57.
16469 *
16470 * 1 : Pin is connected to Peripheral signal SPIS0.SS0.
16471 *
16472 * 2 : Pin is connected to Peripheral signal SPIM0.SS0.
16473 *
16474 * 3 : Pin is connected to Peripheral signal RGMII1.TXD3.
16475 *
16476 * Field Access Macros:
16477 *
16478 */
16479/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */
16480#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_LSB 0
16481/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */
16482#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_MSB 1
16483/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */
16484#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_WIDTH 2
16485/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value. */
16486#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET_MSK 0x00000003
16487/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value. */
16488#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_CLR_MSK 0xfffffffc
16489/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */
16490#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_RESET 0x0
16491/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL field value from a register. */
16492#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
16493/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value suitable for setting the register. */
16494#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET(value) (((value) << 0) & 0x00000003)
16495
16496#ifndef __ASSEMBLY__
16497/*
16498 * WARNING: The C register and register group struct declarations are provided for
16499 * convenience and illustrative purposes. They should, however, be used with
16500 * caution as the C language standard provides no guarantees about the alignment or
16501 * atomicity of device memory accesses. The recommended practice for writing
16502 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16503 * alt_write_word() functions.
16504 *
16505 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO3.
16506 */
16507 struct ALT_SYSMGR_PINMUX_MIXED2IO3_s
16508{
16509 uint32_t sel : 2; /* emac1_tx_d3 Mux Selection Field */
16510 uint32_t : 30; /* *UNDEFINED* */
16511};
16512
16513/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO3. */
16514typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO3_s ALT_SYSMGR_PINMUX_MIXED2IO3_t;
16515#endif /* __ASSEMBLY__ */
16516
16517/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO3 register from the beginning of the component. */
16518#define ALT_SYSMGR_PINMUX_MIXED2IO3_OFST 0x164
16519
16520/*
16521 * Register : emac1_rx_clk Mux Selection Register - MIXED2IO4
16522 *
16523 * This register is used to control the peripherals connected to emac1_rx_clk
16524 *
16525 * Only reset by a cold reset (ignores warm reset).
16526 *
16527 * NOTE: These registers should not be modified after IO configuration.There is no
16528 * support for dynamically changing the Pin Mux selections.
16529 *
16530 * Register Layout
16531 *
16532 * Bits | Access | Reset | Description
16533 * :-------|:-------|:------|:---------------------------------
16534 * [1:0] | RW | 0x0 | emac1_rx_clk Mux Selection Field
16535 * [31:2] | ??? | 0x0 | *UNDEFINED*
16536 *
16537 */
16538/*
16539 * Field : emac1_rx_clk Mux Selection Field - sel
16540 *
16541 * Select peripheral signals connected emac1_rx_clk.
16542 *
16543 * 0 : Pin is connected to GPIO/LoanIO number 58.
16544 *
16545 * 1 : Pin is connected to Peripheral signal SPIM1.CLK.
16546 *
16547 * 2 : Pin is connected to Peripheral signal SPIS1.CLK.
16548 *
16549 * 3 : Pin is connected to Peripheral signal RGMII1.RX_CLK.
16550 *
16551 * Field Access Macros:
16552 *
16553 */
16554/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */
16555#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_LSB 0
16556/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */
16557#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_MSB 1
16558/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */
16559#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_WIDTH 2
16560/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value. */
16561#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET_MSK 0x00000003
16562/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value. */
16563#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_CLR_MSK 0xfffffffc
16564/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */
16565#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_RESET 0x0
16566/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL field value from a register. */
16567#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
16568/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value suitable for setting the register. */
16569#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET(value) (((value) << 0) & 0x00000003)
16570
16571#ifndef __ASSEMBLY__
16572/*
16573 * WARNING: The C register and register group struct declarations are provided for
16574 * convenience and illustrative purposes. They should, however, be used with
16575 * caution as the C language standard provides no guarantees about the alignment or
16576 * atomicity of device memory accesses. The recommended practice for writing
16577 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16578 * alt_write_word() functions.
16579 *
16580 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO4.
16581 */
16582 struct ALT_SYSMGR_PINMUX_MIXED2IO4_s
16583{
16584 uint32_t sel : 2; /* emac1_rx_clk Mux Selection Field */
16585 uint32_t : 30; /* *UNDEFINED* */
16586};
16587
16588/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO4. */
16589typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO4_s ALT_SYSMGR_PINMUX_MIXED2IO4_t;
16590#endif /* __ASSEMBLY__ */
16591
16592/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO4 register from the beginning of the component. */
16593#define ALT_SYSMGR_PINMUX_MIXED2IO4_OFST 0x168
16594
16595/*
16596 * Register : emac1_rx_ctl Mux Selection Register - MIXED2IO5
16597 *
16598 * This register is used to control the peripherals connected to emac1_rx_ctl
16599 *
16600 * Only reset by a cold reset (ignores warm reset).
16601 *
16602 * NOTE: These registers should not be modified after IO configuration.There is no
16603 * support for dynamically changing the Pin Mux selections.
16604 *
16605 * Register Layout
16606 *
16607 * Bits | Access | Reset | Description
16608 * :-------|:-------|:------|:---------------------------------
16609 * [1:0] | RW | 0x0 | emac1_rx_ctl Mux Selection Field
16610 * [31:2] | ??? | 0x0 | *UNDEFINED*
16611 *
16612 */
16613/*
16614 * Field : emac1_rx_ctl Mux Selection Field - sel
16615 *
16616 * Select peripheral signals connected emac1_rx_ctl.
16617 *
16618 * 0 : Pin is connected to GPIO/LoanIO number 59.
16619 *
16620 * 1 : Pin is connected to Peripheral signal SPIM1.MOSI.
16621 *
16622 * 2 : Pin is connected to Peripheral signal SPIS1.MOSI.
16623 *
16624 * 3 : Pin is connected to Peripheral signal RGMII1.RX_CTL.
16625 *
16626 * Field Access Macros:
16627 *
16628 */
16629/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */
16630#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_LSB 0
16631/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */
16632#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_MSB 1
16633/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */
16634#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_WIDTH 2
16635/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value. */
16636#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET_MSK 0x00000003
16637/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value. */
16638#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_CLR_MSK 0xfffffffc
16639/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */
16640#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_RESET 0x0
16641/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL field value from a register. */
16642#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
16643/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value suitable for setting the register. */
16644#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET(value) (((value) << 0) & 0x00000003)
16645
16646#ifndef __ASSEMBLY__
16647/*
16648 * WARNING: The C register and register group struct declarations are provided for
16649 * convenience and illustrative purposes. They should, however, be used with
16650 * caution as the C language standard provides no guarantees about the alignment or
16651 * atomicity of device memory accesses. The recommended practice for writing
16652 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16653 * alt_write_word() functions.
16654 *
16655 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO5.
16656 */
16657 struct ALT_SYSMGR_PINMUX_MIXED2IO5_s
16658{
16659 uint32_t sel : 2; /* emac1_rx_ctl Mux Selection Field */
16660 uint32_t : 30; /* *UNDEFINED* */
16661};
16662
16663/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO5. */
16664typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO5_s ALT_SYSMGR_PINMUX_MIXED2IO5_t;
16665#endif /* __ASSEMBLY__ */
16666
16667/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO5 register from the beginning of the component. */
16668#define ALT_SYSMGR_PINMUX_MIXED2IO5_OFST 0x16c
16669
16670/*
16671 * Register : emac1_rx_d2 Mux Selection Register - MIXED2IO6
16672 *
16673 * This register is used to control the peripherals connected to emac1_rx_d2
16674 *
16675 * Only reset by a cold reset (ignores warm reset).
16676 *
16677 * NOTE: These registers should not be modified after IO configuration.There is no
16678 * support for dynamically changing the Pin Mux selections.
16679 *
16680 * Register Layout
16681 *
16682 * Bits | Access | Reset | Description
16683 * :-------|:-------|:------|:--------------------------------
16684 * [1:0] | RW | 0x0 | emac1_rx_d2 Mux Selection Field
16685 * [31:2] | ??? | 0x0 | *UNDEFINED*
16686 *
16687 */
16688/*
16689 * Field : emac1_rx_d2 Mux Selection Field - sel
16690 *
16691 * Select peripheral signals connected emac1_rx_d2.
16692 *
16693 * 0 : Pin is connected to GPIO/LoanIO number 60.
16694 *
16695 * 1 : Pin is connected to Peripheral signal SPIM1.MISO.
16696 *
16697 * 2 : Pin is connected to Peripheral signal SPIS1.MISO.
16698 *
16699 * 3 : Pin is connected to Peripheral signal RGMII1.RXD2.
16700 *
16701 * Field Access Macros:
16702 *
16703 */
16704/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */
16705#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_LSB 0
16706/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */
16707#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_MSB 1
16708/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */
16709#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_WIDTH 2
16710/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value. */
16711#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET_MSK 0x00000003
16712/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value. */
16713#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_CLR_MSK 0xfffffffc
16714/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */
16715#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_RESET 0x0
16716/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL field value from a register. */
16717#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
16718/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value suitable for setting the register. */
16719#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET(value) (((value) << 0) & 0x00000003)
16720
16721#ifndef __ASSEMBLY__
16722/*
16723 * WARNING: The C register and register group struct declarations are provided for
16724 * convenience and illustrative purposes. They should, however, be used with
16725 * caution as the C language standard provides no guarantees about the alignment or
16726 * atomicity of device memory accesses. The recommended practice for writing
16727 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16728 * alt_write_word() functions.
16729 *
16730 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO6.
16731 */
16732 struct ALT_SYSMGR_PINMUX_MIXED2IO6_s
16733{
16734 uint32_t sel : 2; /* emac1_rx_d2 Mux Selection Field */
16735 uint32_t : 30; /* *UNDEFINED* */
16736};
16737
16738/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO6. */
16739typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO6_s ALT_SYSMGR_PINMUX_MIXED2IO6_t;
16740#endif /* __ASSEMBLY__ */
16741
16742/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO6 register from the beginning of the component. */
16743#define ALT_SYSMGR_PINMUX_MIXED2IO6_OFST 0x170
16744
16745/*
16746 * Register : emac1_rx_d3 Mux Selection Register - MIXED2IO7
16747 *
16748 * This register is used to control the peripherals connected to emac1_rx_d3
16749 *
16750 * Only reset by a cold reset (ignores warm reset).
16751 *
16752 * NOTE: These registers should not be modified after IO configuration.There is no
16753 * support for dynamically changing the Pin Mux selections.
16754 *
16755 * Register Layout
16756 *
16757 * Bits | Access | Reset | Description
16758 * :-------|:-------|:------|:--------------------------------
16759 * [1:0] | RW | 0x0 | emac1_rx_d3 Mux Selection Field
16760 * [31:2] | ??? | 0x0 | *UNDEFINED*
16761 *
16762 */
16763/*
16764 * Field : emac1_rx_d3 Mux Selection Field - sel
16765 *
16766 * Select peripheral signals connected emac1_rx_d3.
16767 *
16768 * 0 : Pin is connected to GPIO/LoanIO number 61.
16769 *
16770 * 1 : Pin is connected to Peripheral signal SPIM1.SS0.
16771 *
16772 * 2 : Pin is connected to Peripheral signal SPIS1.SS0.
16773 *
16774 * 3 : Pin is connected to Peripheral signal RGMII1.RXD3.
16775 *
16776 * Field Access Macros:
16777 *
16778 */
16779/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */
16780#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_LSB 0
16781/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */
16782#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_MSB 1
16783/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */
16784#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_WIDTH 2
16785/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value. */
16786#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET_MSK 0x00000003
16787/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value. */
16788#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_CLR_MSK 0xfffffffc
16789/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */
16790#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_RESET 0x0
16791/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL field value from a register. */
16792#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
16793/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value suitable for setting the register. */
16794#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET(value) (((value) << 0) & 0x00000003)
16795
16796#ifndef __ASSEMBLY__
16797/*
16798 * WARNING: The C register and register group struct declarations are provided for
16799 * convenience and illustrative purposes. They should, however, be used with
16800 * caution as the C language standard provides no guarantees about the alignment or
16801 * atomicity of device memory accesses. The recommended practice for writing
16802 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16803 * alt_write_word() functions.
16804 *
16805 * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO7.
16806 */
16807 struct ALT_SYSMGR_PINMUX_MIXED2IO7_s
16808{
16809 uint32_t sel : 2; /* emac1_rx_d3 Mux Selection Field */
16810 uint32_t : 30; /* *UNDEFINED* */
16811};
16812
16813/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO7. */
16814typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO7_s ALT_SYSMGR_PINMUX_MIXED2IO7_t;
16815#endif /* __ASSEMBLY__ */
16816
16817/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO7 register from the beginning of the component. */
16818#define ALT_SYSMGR_PINMUX_MIXED2IO7_OFST 0x174
16819
16820/*
16821 * Register : GPIO/LoanIO 48 Input Mux Selection Register - GPLINMUX48
16822 *
16823 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
16824 * the input signal for GPIO/LoanIO 48.
16825 *
16826 * Only reset by a cold reset (ignores warm reset).
16827 *
16828 * NOTE: These registers should not be modified after IO configuration.There is no
16829 * support for dynamically changing the Pin Mux selections.
16830 *
16831 * Register Layout
16832 *
16833 * Bits | Access | Reset | Description
16834 * :-------|:-------|:------|:----------------------------------------
16835 * [0] | RW | 0x0 | GPIO/Loan IO48Input Mux Selection Field
16836 * [31:1] | ??? | 0x0 | *UNDEFINED*
16837 *
16838 */
16839/*
16840 * Field : GPIO/Loan IO48Input Mux Selection Field - sel
16841 *
16842 * Select source for GPIO/LoanIO 48.
16843 *
16844 * 0 : Source for GPIO/LoanIO 48 is GENERALIO0.
16845 *
16846 * 1 : Source for GPIO/LoanIO 48 is EMACIO14.
16847 *
16848 * Field Access Macros:
16849 *
16850 */
16851/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */
16852#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_LSB 0
16853/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */
16854#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_MSB 0
16855/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */
16856#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_WIDTH 1
16857/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value. */
16858#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET_MSK 0x00000001
16859/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value. */
16860#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_CLR_MSK 0xfffffffe
16861/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */
16862#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_RESET 0x0
16863/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL field value from a register. */
16864#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0)
16865/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value suitable for setting the register. */
16866#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET(value) (((value) << 0) & 0x00000001)
16867
16868#ifndef __ASSEMBLY__
16869/*
16870 * WARNING: The C register and register group struct declarations are provided for
16871 * convenience and illustrative purposes. They should, however, be used with
16872 * caution as the C language standard provides no guarantees about the alignment or
16873 * atomicity of device memory accesses. The recommended practice for writing
16874 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16875 * alt_write_word() functions.
16876 *
16877 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX48.
16878 */
16879 struct ALT_SYSMGR_PINMUX_GPLINMUX48_s
16880{
16881 uint32_t sel : 1; /* GPIO/Loan IO48Input Mux Selection Field */
16882 uint32_t : 31; /* *UNDEFINED* */
16883};
16884
16885/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX48. */
16886typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX48_s ALT_SYSMGR_PINMUX_GPLINMUX48_t;
16887#endif /* __ASSEMBLY__ */
16888
16889/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX48 register from the beginning of the component. */
16890#define ALT_SYSMGR_PINMUX_GPLINMUX48_OFST 0x178
16891
16892/*
16893 * Register : GPIO/LoanIO 49 Input Mux Selection Register - GPLINMUX49
16894 *
16895 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
16896 * the input signal for GPIO/LoanIO 49.
16897 *
16898 * Only reset by a cold reset (ignores warm reset).
16899 *
16900 * NOTE: These registers should not be modified after IO configuration.There is no
16901 * support for dynamically changing the Pin Mux selections.
16902 *
16903 * Register Layout
16904 *
16905 * Bits | Access | Reset | Description
16906 * :-------|:-------|:------|:----------------------------------------
16907 * [0] | RW | 0x0 | GPIO/Loan IO49Input Mux Selection Field
16908 * [31:1] | ??? | 0x0 | *UNDEFINED*
16909 *
16910 */
16911/*
16912 * Field : GPIO/Loan IO49Input Mux Selection Field - sel
16913 *
16914 * Select source for GPIO/LoanIO 49.
16915 *
16916 * 0 : Source for GPIO/LoanIO 49 is GENERALIO1.
16917 *
16918 * 1 : Source for GPIO/LoanIO 49 is EMACIO15.
16919 *
16920 * Field Access Macros:
16921 *
16922 */
16923/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */
16924#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_LSB 0
16925/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */
16926#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_MSB 0
16927/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */
16928#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_WIDTH 1
16929/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value. */
16930#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET_MSK 0x00000001
16931/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value. */
16932#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_CLR_MSK 0xfffffffe
16933/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */
16934#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_RESET 0x0
16935/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL field value from a register. */
16936#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0)
16937/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value suitable for setting the register. */
16938#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET(value) (((value) << 0) & 0x00000001)
16939
16940#ifndef __ASSEMBLY__
16941/*
16942 * WARNING: The C register and register group struct declarations are provided for
16943 * convenience and illustrative purposes. They should, however, be used with
16944 * caution as the C language standard provides no guarantees about the alignment or
16945 * atomicity of device memory accesses. The recommended practice for writing
16946 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16947 * alt_write_word() functions.
16948 *
16949 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX49.
16950 */
16951 struct ALT_SYSMGR_PINMUX_GPLINMUX49_s
16952{
16953 uint32_t sel : 1; /* GPIO/Loan IO49Input Mux Selection Field */
16954 uint32_t : 31; /* *UNDEFINED* */
16955};
16956
16957/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX49. */
16958typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX49_s ALT_SYSMGR_PINMUX_GPLINMUX49_t;
16959#endif /* __ASSEMBLY__ */
16960
16961/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX49 register from the beginning of the component. */
16962#define ALT_SYSMGR_PINMUX_GPLINMUX49_OFST 0x17c
16963
16964/*
16965 * Register : GPIO/LoanIO 50 Input Mux Selection Register - GPLINMUX50
16966 *
16967 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
16968 * the input signal for GPIO/LoanIO 50.
16969 *
16970 * Only reset by a cold reset (ignores warm reset).
16971 *
16972 * NOTE: These registers should not be modified after IO configuration.There is no
16973 * support for dynamically changing the Pin Mux selections.
16974 *
16975 * Register Layout
16976 *
16977 * Bits | Access | Reset | Description
16978 * :-------|:-------|:------|:----------------------------------------
16979 * [0] | RW | 0x0 | GPIO/Loan IO50Input Mux Selection Field
16980 * [31:1] | ??? | 0x0 | *UNDEFINED*
16981 *
16982 */
16983/*
16984 * Field : GPIO/Loan IO50Input Mux Selection Field - sel
16985 *
16986 * Select source for GPIO/LoanIO 50.
16987 *
16988 * 0 : Source for GPIO/LoanIO 50 is GENERALIO2.
16989 *
16990 * 1 : Source for GPIO/LoanIO 50 is EMACIO16.
16991 *
16992 * Field Access Macros:
16993 *
16994 */
16995/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */
16996#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_LSB 0
16997/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */
16998#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_MSB 0
16999/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */
17000#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_WIDTH 1
17001/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value. */
17002#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET_MSK 0x00000001
17003/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value. */
17004#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_CLR_MSK 0xfffffffe
17005/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */
17006#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_RESET 0x0
17007/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL field value from a register. */
17008#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0)
17009/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value suitable for setting the register. */
17010#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET(value) (((value) << 0) & 0x00000001)
17011
17012#ifndef __ASSEMBLY__
17013/*
17014 * WARNING: The C register and register group struct declarations are provided for
17015 * convenience and illustrative purposes. They should, however, be used with
17016 * caution as the C language standard provides no guarantees about the alignment or
17017 * atomicity of device memory accesses. The recommended practice for writing
17018 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17019 * alt_write_word() functions.
17020 *
17021 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX50.
17022 */
17023 struct ALT_SYSMGR_PINMUX_GPLINMUX50_s
17024{
17025 uint32_t sel : 1; /* GPIO/Loan IO50Input Mux Selection Field */
17026 uint32_t : 31; /* *UNDEFINED* */
17027};
17028
17029/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX50. */
17030typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX50_s ALT_SYSMGR_PINMUX_GPLINMUX50_t;
17031#endif /* __ASSEMBLY__ */
17032
17033/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX50 register from the beginning of the component. */
17034#define ALT_SYSMGR_PINMUX_GPLINMUX50_OFST 0x180
17035
17036/*
17037 * Register : GPIO/LoanIO 51 Input Mux Selection Register - GPLINMUX51
17038 *
17039 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17040 * the input signal for GPIO/LoanIO 51.
17041 *
17042 * Only reset by a cold reset (ignores warm reset).
17043 *
17044 * NOTE: These registers should not be modified after IO configuration.There is no
17045 * support for dynamically changing the Pin Mux selections.
17046 *
17047 * Register Layout
17048 *
17049 * Bits | Access | Reset | Description
17050 * :-------|:-------|:------|:----------------------------------------
17051 * [0] | RW | 0x0 | GPIO/Loan IO51Input Mux Selection Field
17052 * [31:1] | ??? | 0x0 | *UNDEFINED*
17053 *
17054 */
17055/*
17056 * Field : GPIO/Loan IO51Input Mux Selection Field - sel
17057 *
17058 * Select source for GPIO/LoanIO 51.
17059 *
17060 * 0 : Source for GPIO/LoanIO 51 is GENERALIO3.
17061 *
17062 * 1 : Source for GPIO/LoanIO 51 is EMACIO17.
17063 *
17064 * Field Access Macros:
17065 *
17066 */
17067/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */
17068#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_LSB 0
17069/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */
17070#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_MSB 0
17071/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */
17072#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_WIDTH 1
17073/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value. */
17074#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET_MSK 0x00000001
17075/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value. */
17076#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_CLR_MSK 0xfffffffe
17077/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */
17078#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_RESET 0x0
17079/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL field value from a register. */
17080#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0)
17081/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value suitable for setting the register. */
17082#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET(value) (((value) << 0) & 0x00000001)
17083
17084#ifndef __ASSEMBLY__
17085/*
17086 * WARNING: The C register and register group struct declarations are provided for
17087 * convenience and illustrative purposes. They should, however, be used with
17088 * caution as the C language standard provides no guarantees about the alignment or
17089 * atomicity of device memory accesses. The recommended practice for writing
17090 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17091 * alt_write_word() functions.
17092 *
17093 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX51.
17094 */
17095 struct ALT_SYSMGR_PINMUX_GPLINMUX51_s
17096{
17097 uint32_t sel : 1; /* GPIO/Loan IO51Input Mux Selection Field */
17098 uint32_t : 31; /* *UNDEFINED* */
17099};
17100
17101/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX51. */
17102typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX51_s ALT_SYSMGR_PINMUX_GPLINMUX51_t;
17103#endif /* __ASSEMBLY__ */
17104
17105/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX51 register from the beginning of the component. */
17106#define ALT_SYSMGR_PINMUX_GPLINMUX51_OFST 0x184
17107
17108/*
17109 * Register : GPIO/LoanIO 52 Input Mux Selection Register - GPLINMUX52
17110 *
17111 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17112 * the input signal for GPIO/LoanIO 52.
17113 *
17114 * Only reset by a cold reset (ignores warm reset).
17115 *
17116 * NOTE: These registers should not be modified after IO configuration.There is no
17117 * support for dynamically changing the Pin Mux selections.
17118 *
17119 * Register Layout
17120 *
17121 * Bits | Access | Reset | Description
17122 * :-------|:-------|:------|:----------------------------------------
17123 * [0] | RW | 0x0 | GPIO/Loan IO52Input Mux Selection Field
17124 * [31:1] | ??? | 0x0 | *UNDEFINED*
17125 *
17126 */
17127/*
17128 * Field : GPIO/Loan IO52Input Mux Selection Field - sel
17129 *
17130 * Select source for GPIO/LoanIO 52.
17131 *
17132 * 0 : Source for GPIO/LoanIO 52 is GENERALIO4.
17133 *
17134 * 1 : Source for GPIO/LoanIO 52 is EMACIO18.
17135 *
17136 * Field Access Macros:
17137 *
17138 */
17139/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */
17140#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_LSB 0
17141/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */
17142#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_MSB 0
17143/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */
17144#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_WIDTH 1
17145/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value. */
17146#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET_MSK 0x00000001
17147/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value. */
17148#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_CLR_MSK 0xfffffffe
17149/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */
17150#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_RESET 0x0
17151/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL field value from a register. */
17152#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0)
17153/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value suitable for setting the register. */
17154#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET(value) (((value) << 0) & 0x00000001)
17155
17156#ifndef __ASSEMBLY__
17157/*
17158 * WARNING: The C register and register group struct declarations are provided for
17159 * convenience and illustrative purposes. They should, however, be used with
17160 * caution as the C language standard provides no guarantees about the alignment or
17161 * atomicity of device memory accesses. The recommended practice for writing
17162 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17163 * alt_write_word() functions.
17164 *
17165 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX52.
17166 */
17167 struct ALT_SYSMGR_PINMUX_GPLINMUX52_s
17168{
17169 uint32_t sel : 1; /* GPIO/Loan IO52Input Mux Selection Field */
17170 uint32_t : 31; /* *UNDEFINED* */
17171};
17172
17173/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX52. */
17174typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX52_s ALT_SYSMGR_PINMUX_GPLINMUX52_t;
17175#endif /* __ASSEMBLY__ */
17176
17177/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX52 register from the beginning of the component. */
17178#define ALT_SYSMGR_PINMUX_GPLINMUX52_OFST 0x188
17179
17180/*
17181 * Register : GPIO/LoanIO 53 Input Mux Selection Register - GPLINMUX53
17182 *
17183 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17184 * the input signal for GPIO/LoanIO 53.
17185 *
17186 * Only reset by a cold reset (ignores warm reset).
17187 *
17188 * NOTE: These registers should not be modified after IO configuration.There is no
17189 * support for dynamically changing the Pin Mux selections.
17190 *
17191 * Register Layout
17192 *
17193 * Bits | Access | Reset | Description
17194 * :-------|:-------|:------|:----------------------------------------
17195 * [0] | RW | 0x0 | GPIO/Loan IO53Input Mux Selection Field
17196 * [31:1] | ??? | 0x0 | *UNDEFINED*
17197 *
17198 */
17199/*
17200 * Field : GPIO/Loan IO53Input Mux Selection Field - sel
17201 *
17202 * Select source for GPIO/LoanIO 53.
17203 *
17204 * 0 : Source for GPIO/LoanIO 53 is GENERALIO5.
17205 *
17206 * 1 : Source for GPIO/LoanIO 53 is EMACIO19.
17207 *
17208 * Field Access Macros:
17209 *
17210 */
17211/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */
17212#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_LSB 0
17213/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */
17214#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_MSB 0
17215/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */
17216#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_WIDTH 1
17217/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value. */
17218#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET_MSK 0x00000001
17219/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value. */
17220#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_CLR_MSK 0xfffffffe
17221/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */
17222#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_RESET 0x0
17223/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL field value from a register. */
17224#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0)
17225/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value suitable for setting the register. */
17226#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET(value) (((value) << 0) & 0x00000001)
17227
17228#ifndef __ASSEMBLY__
17229/*
17230 * WARNING: The C register and register group struct declarations are provided for
17231 * convenience and illustrative purposes. They should, however, be used with
17232 * caution as the C language standard provides no guarantees about the alignment or
17233 * atomicity of device memory accesses. The recommended practice for writing
17234 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17235 * alt_write_word() functions.
17236 *
17237 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX53.
17238 */
17239 struct ALT_SYSMGR_PINMUX_GPLINMUX53_s
17240{
17241 uint32_t sel : 1; /* GPIO/Loan IO53Input Mux Selection Field */
17242 uint32_t : 31; /* *UNDEFINED* */
17243};
17244
17245/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX53. */
17246typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX53_s ALT_SYSMGR_PINMUX_GPLINMUX53_t;
17247#endif /* __ASSEMBLY__ */
17248
17249/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX53 register from the beginning of the component. */
17250#define ALT_SYSMGR_PINMUX_GPLINMUX53_OFST 0x18c
17251
17252/*
17253 * Register : GPIO/LoanIO 54 Input Mux Selection Register - GPLINMUX54
17254 *
17255 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17256 * the input signal for GPIO/LoanIO 54.
17257 *
17258 * Only reset by a cold reset (ignores warm reset).
17259 *
17260 * NOTE: These registers should not be modified after IO configuration.There is no
17261 * support for dynamically changing the Pin Mux selections.
17262 *
17263 * Register Layout
17264 *
17265 * Bits | Access | Reset | Description
17266 * :-------|:-------|:------|:----------------------------------------
17267 * [0] | RW | 0x0 | GPIO/Loan IO54Input Mux Selection Field
17268 * [31:1] | ??? | 0x0 | *UNDEFINED*
17269 *
17270 */
17271/*
17272 * Field : GPIO/Loan IO54Input Mux Selection Field - sel
17273 *
17274 * Select source for GPIO/LoanIO 54.
17275 *
17276 * 0 : Source for GPIO/LoanIO 54 is GENERALIO6.
17277 *
17278 * 1 : Source for GPIO/LoanIO 54 is MIXED2IO0.
17279 *
17280 * Field Access Macros:
17281 *
17282 */
17283/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */
17284#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_LSB 0
17285/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */
17286#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_MSB 0
17287/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */
17288#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_WIDTH 1
17289/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value. */
17290#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET_MSK 0x00000001
17291/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value. */
17292#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_CLR_MSK 0xfffffffe
17293/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */
17294#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_RESET 0x0
17295/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL field value from a register. */
17296#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0)
17297/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value suitable for setting the register. */
17298#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET(value) (((value) << 0) & 0x00000001)
17299
17300#ifndef __ASSEMBLY__
17301/*
17302 * WARNING: The C register and register group struct declarations are provided for
17303 * convenience and illustrative purposes. They should, however, be used with
17304 * caution as the C language standard provides no guarantees about the alignment or
17305 * atomicity of device memory accesses. The recommended practice for writing
17306 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17307 * alt_write_word() functions.
17308 *
17309 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX54.
17310 */
17311 struct ALT_SYSMGR_PINMUX_GPLINMUX54_s
17312{
17313 uint32_t sel : 1; /* GPIO/Loan IO54Input Mux Selection Field */
17314 uint32_t : 31; /* *UNDEFINED* */
17315};
17316
17317/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX54. */
17318typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX54_s ALT_SYSMGR_PINMUX_GPLINMUX54_t;
17319#endif /* __ASSEMBLY__ */
17320
17321/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX54 register from the beginning of the component. */
17322#define ALT_SYSMGR_PINMUX_GPLINMUX54_OFST 0x190
17323
17324/*
17325 * Register : GPIO/LoanIO 55 Input Mux Selection Register - GPLINMUX55
17326 *
17327 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17328 * the input signal for GPIO/LoanIO 55.
17329 *
17330 * Only reset by a cold reset (ignores warm reset).
17331 *
17332 * NOTE: These registers should not be modified after IO configuration.There is no
17333 * support for dynamically changing the Pin Mux selections.
17334 *
17335 * Register Layout
17336 *
17337 * Bits | Access | Reset | Description
17338 * :-------|:-------|:------|:----------------------------------------
17339 * [0] | RW | 0x0 | GPIO/Loan IO55Input Mux Selection Field
17340 * [31:1] | ??? | 0x0 | *UNDEFINED*
17341 *
17342 */
17343/*
17344 * Field : GPIO/Loan IO55Input Mux Selection Field - sel
17345 *
17346 * Select source for GPIO/LoanIO 55.
17347 *
17348 * 0 : Source for GPIO/LoanIO 55 is GENERALIO7.
17349 *
17350 * 1 : Source for GPIO/LoanIO 55 is MIXED2IO1.
17351 *
17352 * Field Access Macros:
17353 *
17354 */
17355/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */
17356#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_LSB 0
17357/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */
17358#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_MSB 0
17359/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */
17360#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_WIDTH 1
17361/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value. */
17362#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET_MSK 0x00000001
17363/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value. */
17364#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_CLR_MSK 0xfffffffe
17365/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */
17366#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_RESET 0x0
17367/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL field value from a register. */
17368#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0)
17369/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value suitable for setting the register. */
17370#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET(value) (((value) << 0) & 0x00000001)
17371
17372#ifndef __ASSEMBLY__
17373/*
17374 * WARNING: The C register and register group struct declarations are provided for
17375 * convenience and illustrative purposes. They should, however, be used with
17376 * caution as the C language standard provides no guarantees about the alignment or
17377 * atomicity of device memory accesses. The recommended practice for writing
17378 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17379 * alt_write_word() functions.
17380 *
17381 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX55.
17382 */
17383 struct ALT_SYSMGR_PINMUX_GPLINMUX55_s
17384{
17385 uint32_t sel : 1; /* GPIO/Loan IO55Input Mux Selection Field */
17386 uint32_t : 31; /* *UNDEFINED* */
17387};
17388
17389/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX55. */
17390typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX55_s ALT_SYSMGR_PINMUX_GPLINMUX55_t;
17391#endif /* __ASSEMBLY__ */
17392
17393/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX55 register from the beginning of the component. */
17394#define ALT_SYSMGR_PINMUX_GPLINMUX55_OFST 0x194
17395
17396/*
17397 * Register : GPIO/LoanIO 56 Input Mux Selection Register - GPLINMUX56
17398 *
17399 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17400 * the input signal for GPIO/LoanIO 56.
17401 *
17402 * Only reset by a cold reset (ignores warm reset).
17403 *
17404 * NOTE: These registers should not be modified after IO configuration.There is no
17405 * support for dynamically changing the Pin Mux selections.
17406 *
17407 * Register Layout
17408 *
17409 * Bits | Access | Reset | Description
17410 * :-------|:-------|:------|:----------------------------------------
17411 * [0] | RW | 0x0 | GPIO/Loan IO56Input Mux Selection Field
17412 * [31:1] | ??? | 0x0 | *UNDEFINED*
17413 *
17414 */
17415/*
17416 * Field : GPIO/Loan IO56Input Mux Selection Field - sel
17417 *
17418 * Select source for GPIO/LoanIO 56.
17419 *
17420 * 0 : Source for GPIO/LoanIO 56 is GENERALIO8.
17421 *
17422 * 1 : Source for GPIO/LoanIO 56 is MIXED2IO2.
17423 *
17424 * Field Access Macros:
17425 *
17426 */
17427/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */
17428#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_LSB 0
17429/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */
17430#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_MSB 0
17431/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */
17432#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_WIDTH 1
17433/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value. */
17434#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET_MSK 0x00000001
17435/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value. */
17436#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_CLR_MSK 0xfffffffe
17437/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */
17438#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_RESET 0x0
17439/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL field value from a register. */
17440#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0)
17441/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value suitable for setting the register. */
17442#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET(value) (((value) << 0) & 0x00000001)
17443
17444#ifndef __ASSEMBLY__
17445/*
17446 * WARNING: The C register and register group struct declarations are provided for
17447 * convenience and illustrative purposes. They should, however, be used with
17448 * caution as the C language standard provides no guarantees about the alignment or
17449 * atomicity of device memory accesses. The recommended practice for writing
17450 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17451 * alt_write_word() functions.
17452 *
17453 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX56.
17454 */
17455 struct ALT_SYSMGR_PINMUX_GPLINMUX56_s
17456{
17457 uint32_t sel : 1; /* GPIO/Loan IO56Input Mux Selection Field */
17458 uint32_t : 31; /* *UNDEFINED* */
17459};
17460
17461/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX56. */
17462typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX56_s ALT_SYSMGR_PINMUX_GPLINMUX56_t;
17463#endif /* __ASSEMBLY__ */
17464
17465/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX56 register from the beginning of the component. */
17466#define ALT_SYSMGR_PINMUX_GPLINMUX56_OFST 0x198
17467
17468/*
17469 * Register : GPIO/LoanIO 57 Input Mux Selection Register - GPLINMUX57
17470 *
17471 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17472 * the input signal for GPIO/LoanIO 57.
17473 *
17474 * Only reset by a cold reset (ignores warm reset).
17475 *
17476 * NOTE: These registers should not be modified after IO configuration.There is no
17477 * support for dynamically changing the Pin Mux selections.
17478 *
17479 * Register Layout
17480 *
17481 * Bits | Access | Reset | Description
17482 * :-------|:-------|:------|:----------------------------------------
17483 * [0] | RW | 0x0 | GPIO/Loan IO57Input Mux Selection Field
17484 * [31:1] | ??? | 0x0 | *UNDEFINED*
17485 *
17486 */
17487/*
17488 * Field : GPIO/Loan IO57Input Mux Selection Field - sel
17489 *
17490 * Select source for GPIO/LoanIO 57.
17491 *
17492 * 0 : Source for GPIO/LoanIO 57 is GENERALIO9.
17493 *
17494 * 1 : Source for GPIO/LoanIO 57 is MIXED2IO3.
17495 *
17496 * Field Access Macros:
17497 *
17498 */
17499/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */
17500#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_LSB 0
17501/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */
17502#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_MSB 0
17503/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */
17504#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_WIDTH 1
17505/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value. */
17506#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET_MSK 0x00000001
17507/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value. */
17508#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_CLR_MSK 0xfffffffe
17509/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */
17510#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_RESET 0x0
17511/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL field value from a register. */
17512#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0)
17513/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value suitable for setting the register. */
17514#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET(value) (((value) << 0) & 0x00000001)
17515
17516#ifndef __ASSEMBLY__
17517/*
17518 * WARNING: The C register and register group struct declarations are provided for
17519 * convenience and illustrative purposes. They should, however, be used with
17520 * caution as the C language standard provides no guarantees about the alignment or
17521 * atomicity of device memory accesses. The recommended practice for writing
17522 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17523 * alt_write_word() functions.
17524 *
17525 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX57.
17526 */
17527 struct ALT_SYSMGR_PINMUX_GPLINMUX57_s
17528{
17529 uint32_t sel : 1; /* GPIO/Loan IO57Input Mux Selection Field */
17530 uint32_t : 31; /* *UNDEFINED* */
17531};
17532
17533/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX57. */
17534typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX57_s ALT_SYSMGR_PINMUX_GPLINMUX57_t;
17535#endif /* __ASSEMBLY__ */
17536
17537/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX57 register from the beginning of the component. */
17538#define ALT_SYSMGR_PINMUX_GPLINMUX57_OFST 0x19c
17539
17540/*
17541 * Register : GPIO/LoanIO 58 Input Mux Selection Register - GPLINMUX58
17542 *
17543 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17544 * the input signal for GPIO/LoanIO 58.
17545 *
17546 * Only reset by a cold reset (ignores warm reset).
17547 *
17548 * NOTE: These registers should not be modified after IO configuration.There is no
17549 * support for dynamically changing the Pin Mux selections.
17550 *
17551 * Register Layout
17552 *
17553 * Bits | Access | Reset | Description
17554 * :-------|:-------|:------|:----------------------------------------
17555 * [0] | RW | 0x0 | GPIO/Loan IO58Input Mux Selection Field
17556 * [31:1] | ??? | 0x0 | *UNDEFINED*
17557 *
17558 */
17559/*
17560 * Field : GPIO/Loan IO58Input Mux Selection Field - sel
17561 *
17562 * Select source for GPIO/LoanIO 58.
17563 *
17564 * 0 : Source for GPIO/LoanIO 58 is GENERALIO10.
17565 *
17566 * 1 : Source for GPIO/LoanIO 58 is MIXED2IO4.
17567 *
17568 * Field Access Macros:
17569 *
17570 */
17571/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */
17572#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_LSB 0
17573/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */
17574#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_MSB 0
17575/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */
17576#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_WIDTH 1
17577/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value. */
17578#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET_MSK 0x00000001
17579/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value. */
17580#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_CLR_MSK 0xfffffffe
17581/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */
17582#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_RESET 0x0
17583/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL field value from a register. */
17584#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0)
17585/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value suitable for setting the register. */
17586#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET(value) (((value) << 0) & 0x00000001)
17587
17588#ifndef __ASSEMBLY__
17589/*
17590 * WARNING: The C register and register group struct declarations are provided for
17591 * convenience and illustrative purposes. They should, however, be used with
17592 * caution as the C language standard provides no guarantees about the alignment or
17593 * atomicity of device memory accesses. The recommended practice for writing
17594 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17595 * alt_write_word() functions.
17596 *
17597 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX58.
17598 */
17599 struct ALT_SYSMGR_PINMUX_GPLINMUX58_s
17600{
17601 uint32_t sel : 1; /* GPIO/Loan IO58Input Mux Selection Field */
17602 uint32_t : 31; /* *UNDEFINED* */
17603};
17604
17605/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX58. */
17606typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX58_s ALT_SYSMGR_PINMUX_GPLINMUX58_t;
17607#endif /* __ASSEMBLY__ */
17608
17609/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX58 register from the beginning of the component. */
17610#define ALT_SYSMGR_PINMUX_GPLINMUX58_OFST 0x1a0
17611
17612/*
17613 * Register : GPIO/LoanIO 59 Input Mux Selection Register - GPLINMUX59
17614 *
17615 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17616 * the input signal for GPIO/LoanIO 59.
17617 *
17618 * Only reset by a cold reset (ignores warm reset).
17619 *
17620 * NOTE: These registers should not be modified after IO configuration.There is no
17621 * support for dynamically changing the Pin Mux selections.
17622 *
17623 * Register Layout
17624 *
17625 * Bits | Access | Reset | Description
17626 * :-------|:-------|:------|:----------------------------------------
17627 * [0] | RW | 0x0 | GPIO/Loan IO59Input Mux Selection Field
17628 * [31:1] | ??? | 0x0 | *UNDEFINED*
17629 *
17630 */
17631/*
17632 * Field : GPIO/Loan IO59Input Mux Selection Field - sel
17633 *
17634 * Select source for GPIO/LoanIO 59.
17635 *
17636 * 0 : Source for GPIO/LoanIO 59 is GENERALIO11.
17637 *
17638 * 1 : Source for GPIO/LoanIO 59 is MIXED2IO5.
17639 *
17640 * Field Access Macros:
17641 *
17642 */
17643/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */
17644#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_LSB 0
17645/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */
17646#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_MSB 0
17647/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */
17648#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_WIDTH 1
17649/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value. */
17650#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET_MSK 0x00000001
17651/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value. */
17652#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_CLR_MSK 0xfffffffe
17653/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */
17654#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_RESET 0x0
17655/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL field value from a register. */
17656#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0)
17657/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value suitable for setting the register. */
17658#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET(value) (((value) << 0) & 0x00000001)
17659
17660#ifndef __ASSEMBLY__
17661/*
17662 * WARNING: The C register and register group struct declarations are provided for
17663 * convenience and illustrative purposes. They should, however, be used with
17664 * caution as the C language standard provides no guarantees about the alignment or
17665 * atomicity of device memory accesses. The recommended practice for writing
17666 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17667 * alt_write_word() functions.
17668 *
17669 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX59.
17670 */
17671 struct ALT_SYSMGR_PINMUX_GPLINMUX59_s
17672{
17673 uint32_t sel : 1; /* GPIO/Loan IO59Input Mux Selection Field */
17674 uint32_t : 31; /* *UNDEFINED* */
17675};
17676
17677/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX59. */
17678typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX59_s ALT_SYSMGR_PINMUX_GPLINMUX59_t;
17679#endif /* __ASSEMBLY__ */
17680
17681/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX59 register from the beginning of the component. */
17682#define ALT_SYSMGR_PINMUX_GPLINMUX59_OFST 0x1a4
17683
17684/*
17685 * Register : GPIO/LoanIO 60 Input Mux Selection Register - GPLINMUX60
17686 *
17687 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17688 * the input signal for GPIO/LoanIO 60.
17689 *
17690 * Only reset by a cold reset (ignores warm reset).
17691 *
17692 * NOTE: These registers should not be modified after IO configuration.There is no
17693 * support for dynamically changing the Pin Mux selections.
17694 *
17695 * Register Layout
17696 *
17697 * Bits | Access | Reset | Description
17698 * :-------|:-------|:------|:----------------------------------------
17699 * [0] | RW | 0x0 | GPIO/Loan IO60Input Mux Selection Field
17700 * [31:1] | ??? | 0x0 | *UNDEFINED*
17701 *
17702 */
17703/*
17704 * Field : GPIO/Loan IO60Input Mux Selection Field - sel
17705 *
17706 * Select source for GPIO/LoanIO 60.
17707 *
17708 * 0 : Source for GPIO/LoanIO 60 is GENERALIO12.
17709 *
17710 * 1 : Source for GPIO/LoanIO 60 is MIXED2IO6.
17711 *
17712 * Field Access Macros:
17713 *
17714 */
17715/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */
17716#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_LSB 0
17717/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */
17718#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_MSB 0
17719/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */
17720#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_WIDTH 1
17721/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value. */
17722#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET_MSK 0x00000001
17723/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value. */
17724#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_CLR_MSK 0xfffffffe
17725/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */
17726#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_RESET 0x0
17727/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL field value from a register. */
17728#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0)
17729/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value suitable for setting the register. */
17730#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET(value) (((value) << 0) & 0x00000001)
17731
17732#ifndef __ASSEMBLY__
17733/*
17734 * WARNING: The C register and register group struct declarations are provided for
17735 * convenience and illustrative purposes. They should, however, be used with
17736 * caution as the C language standard provides no guarantees about the alignment or
17737 * atomicity of device memory accesses. The recommended practice for writing
17738 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17739 * alt_write_word() functions.
17740 *
17741 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX60.
17742 */
17743 struct ALT_SYSMGR_PINMUX_GPLINMUX60_s
17744{
17745 uint32_t sel : 1; /* GPIO/Loan IO60Input Mux Selection Field */
17746 uint32_t : 31; /* *UNDEFINED* */
17747};
17748
17749/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX60. */
17750typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX60_s ALT_SYSMGR_PINMUX_GPLINMUX60_t;
17751#endif /* __ASSEMBLY__ */
17752
17753/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX60 register from the beginning of the component. */
17754#define ALT_SYSMGR_PINMUX_GPLINMUX60_OFST 0x1a8
17755
17756/*
17757 * Register : GPIO/LoanIO 61 Input Mux Selection Register - GPLINMUX61
17758 *
17759 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17760 * the input signal for GPIO/LoanIO 61.
17761 *
17762 * Only reset by a cold reset (ignores warm reset).
17763 *
17764 * NOTE: These registers should not be modified after IO configuration.There is no
17765 * support for dynamically changing the Pin Mux selections.
17766 *
17767 * Register Layout
17768 *
17769 * Bits | Access | Reset | Description
17770 * :-------|:-------|:------|:----------------------------------------
17771 * [0] | RW | 0x0 | GPIO/Loan IO61Input Mux Selection Field
17772 * [31:1] | ??? | 0x0 | *UNDEFINED*
17773 *
17774 */
17775/*
17776 * Field : GPIO/Loan IO61Input Mux Selection Field - sel
17777 *
17778 * Select source for GPIO/LoanIO 61.
17779 *
17780 * 0 : Source for GPIO/LoanIO 61 is GENERALIO13.
17781 *
17782 * 1 : Source for GPIO/LoanIO 61 is MIXED2IO7.
17783 *
17784 * Field Access Macros:
17785 *
17786 */
17787/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */
17788#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_LSB 0
17789/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */
17790#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_MSB 0
17791/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */
17792#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_WIDTH 1
17793/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value. */
17794#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET_MSK 0x00000001
17795/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value. */
17796#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_CLR_MSK 0xfffffffe
17797/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */
17798#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_RESET 0x0
17799/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL field value from a register. */
17800#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0)
17801/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value suitable for setting the register. */
17802#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET(value) (((value) << 0) & 0x00000001)
17803
17804#ifndef __ASSEMBLY__
17805/*
17806 * WARNING: The C register and register group struct declarations are provided for
17807 * convenience and illustrative purposes. They should, however, be used with
17808 * caution as the C language standard provides no guarantees about the alignment or
17809 * atomicity of device memory accesses. The recommended practice for writing
17810 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17811 * alt_write_word() functions.
17812 *
17813 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX61.
17814 */
17815 struct ALT_SYSMGR_PINMUX_GPLINMUX61_s
17816{
17817 uint32_t sel : 1; /* GPIO/Loan IO61Input Mux Selection Field */
17818 uint32_t : 31; /* *UNDEFINED* */
17819};
17820
17821/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX61. */
17822typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX61_s ALT_SYSMGR_PINMUX_GPLINMUX61_t;
17823#endif /* __ASSEMBLY__ */
17824
17825/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX61 register from the beginning of the component. */
17826#define ALT_SYSMGR_PINMUX_GPLINMUX61_OFST 0x1ac
17827
17828/*
17829 * Register : GPIO/LoanIO 62 Input Mux Selection Register - GPLINMUX62
17830 *
17831 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17832 * the input signal for GPIO/LoanIO 62.
17833 *
17834 * Only reset by a cold reset (ignores warm reset).
17835 *
17836 * NOTE: These registers should not be modified after IO configuration.There is no
17837 * support for dynamically changing the Pin Mux selections.
17838 *
17839 * Register Layout
17840 *
17841 * Bits | Access | Reset | Description
17842 * :-------|:-------|:------|:----------------------------------------
17843 * [0] | RW | 0x0 | GPIO/Loan IO62Input Mux Selection Field
17844 * [31:1] | ??? | 0x0 | *UNDEFINED*
17845 *
17846 */
17847/*
17848 * Field : GPIO/Loan IO62Input Mux Selection Field - sel
17849 *
17850 * Select source for GPIO/LoanIO 62.
17851 *
17852 * 0 : Source for GPIO/LoanIO 62 is GENERALIO14.
17853 *
17854 * 1 : Source for GPIO/LoanIO 62 is GENERALIO23.
17855 *
17856 * Field Access Macros:
17857 *
17858 */
17859/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */
17860#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_LSB 0
17861/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */
17862#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_MSB 0
17863/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */
17864#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_WIDTH 1
17865/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value. */
17866#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET_MSK 0x00000001
17867/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value. */
17868#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_CLR_MSK 0xfffffffe
17869/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */
17870#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_RESET 0x0
17871/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL field value from a register. */
17872#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0)
17873/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value suitable for setting the register. */
17874#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET(value) (((value) << 0) & 0x00000001)
17875
17876#ifndef __ASSEMBLY__
17877/*
17878 * WARNING: The C register and register group struct declarations are provided for
17879 * convenience and illustrative purposes. They should, however, be used with
17880 * caution as the C language standard provides no guarantees about the alignment or
17881 * atomicity of device memory accesses. The recommended practice for writing
17882 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17883 * alt_write_word() functions.
17884 *
17885 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX62.
17886 */
17887 struct ALT_SYSMGR_PINMUX_GPLINMUX62_s
17888{
17889 uint32_t sel : 1; /* GPIO/Loan IO62Input Mux Selection Field */
17890 uint32_t : 31; /* *UNDEFINED* */
17891};
17892
17893/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX62. */
17894typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX62_s ALT_SYSMGR_PINMUX_GPLINMUX62_t;
17895#endif /* __ASSEMBLY__ */
17896
17897/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX62 register from the beginning of the component. */
17898#define ALT_SYSMGR_PINMUX_GPLINMUX62_OFST 0x1b0
17899
17900/*
17901 * Register : GPIO/LoanIO 63 Input Mux Selection Register - GPLINMUX63
17902 *
17903 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17904 * the input signal for GPIO/LoanIO 63.
17905 *
17906 * Only reset by a cold reset (ignores warm reset).
17907 *
17908 * NOTE: These registers should not be modified after IO configuration.There is no
17909 * support for dynamically changing the Pin Mux selections.
17910 *
17911 * Register Layout
17912 *
17913 * Bits | Access | Reset | Description
17914 * :-------|:-------|:------|:----------------------------------------
17915 * [0] | RW | 0x0 | GPIO/Loan IO63Input Mux Selection Field
17916 * [31:1] | ??? | 0x0 | *UNDEFINED*
17917 *
17918 */
17919/*
17920 * Field : GPIO/Loan IO63Input Mux Selection Field - sel
17921 *
17922 * Select source for GPIO/LoanIO 63.
17923 *
17924 * 0 : Source for GPIO/LoanIO 63 is GENERALIO15.
17925 *
17926 * 1 : Source for GPIO/LoanIO 63 is GENERALIO24.
17927 *
17928 * Field Access Macros:
17929 *
17930 */
17931/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */
17932#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_LSB 0
17933/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */
17934#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_MSB 0
17935/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */
17936#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_WIDTH 1
17937/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value. */
17938#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET_MSK 0x00000001
17939/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value. */
17940#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_CLR_MSK 0xfffffffe
17941/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */
17942#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_RESET 0x0
17943/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL field value from a register. */
17944#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0)
17945/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value suitable for setting the register. */
17946#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET(value) (((value) << 0) & 0x00000001)
17947
17948#ifndef __ASSEMBLY__
17949/*
17950 * WARNING: The C register and register group struct declarations are provided for
17951 * convenience and illustrative purposes. They should, however, be used with
17952 * caution as the C language standard provides no guarantees about the alignment or
17953 * atomicity of device memory accesses. The recommended practice for writing
17954 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17955 * alt_write_word() functions.
17956 *
17957 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX63.
17958 */
17959 struct ALT_SYSMGR_PINMUX_GPLINMUX63_s
17960{
17961 uint32_t sel : 1; /* GPIO/Loan IO63Input Mux Selection Field */
17962 uint32_t : 31; /* *UNDEFINED* */
17963};
17964
17965/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX63. */
17966typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX63_s ALT_SYSMGR_PINMUX_GPLINMUX63_t;
17967#endif /* __ASSEMBLY__ */
17968
17969/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX63 register from the beginning of the component. */
17970#define ALT_SYSMGR_PINMUX_GPLINMUX63_OFST 0x1b4
17971
17972/*
17973 * Register : GPIO/LoanIO 64 Input Mux Selection Register - GPLINMUX64
17974 *
17975 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17976 * the input signal for GPIO/LoanIO 64.
17977 *
17978 * Only reset by a cold reset (ignores warm reset).
17979 *
17980 * NOTE: These registers should not be modified after IO configuration.There is no
17981 * support for dynamically changing the Pin Mux selections.
17982 *
17983 * Register Layout
17984 *
17985 * Bits | Access | Reset | Description
17986 * :-------|:-------|:------|:----------------------------------------
17987 * [0] | RW | 0x0 | GPIO/Loan IO64Input Mux Selection Field
17988 * [31:1] | ??? | 0x0 | *UNDEFINED*
17989 *
17990 */
17991/*
17992 * Field : GPIO/Loan IO64Input Mux Selection Field - sel
17993 *
17994 * Select source for GPIO/LoanIO 64.
17995 *
17996 * 0 : Source for GPIO/LoanIO 64 is GENERALIO16.
17997 *
17998 * 1 : Source for GPIO/LoanIO 64 is GENERALIO25.
17999 *
18000 * Field Access Macros:
18001 *
18002 */
18003/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */
18004#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_LSB 0
18005/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */
18006#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_MSB 0
18007/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */
18008#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_WIDTH 1
18009/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value. */
18010#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET_MSK 0x00000001
18011/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value. */
18012#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_CLR_MSK 0xfffffffe
18013/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */
18014#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_RESET 0x0
18015/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL field value from a register. */
18016#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0)
18017/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value suitable for setting the register. */
18018#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET(value) (((value) << 0) & 0x00000001)
18019
18020#ifndef __ASSEMBLY__
18021/*
18022 * WARNING: The C register and register group struct declarations are provided for
18023 * convenience and illustrative purposes. They should, however, be used with
18024 * caution as the C language standard provides no guarantees about the alignment or
18025 * atomicity of device memory accesses. The recommended practice for writing
18026 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18027 * alt_write_word() functions.
18028 *
18029 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX64.
18030 */
18031 struct ALT_SYSMGR_PINMUX_GPLINMUX64_s
18032{
18033 uint32_t sel : 1; /* GPIO/Loan IO64Input Mux Selection Field */
18034 uint32_t : 31; /* *UNDEFINED* */
18035};
18036
18037/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX64. */
18038typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX64_s ALT_SYSMGR_PINMUX_GPLINMUX64_t;
18039#endif /* __ASSEMBLY__ */
18040
18041/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX64 register from the beginning of the component. */
18042#define ALT_SYSMGR_PINMUX_GPLINMUX64_OFST 0x1b8
18043
18044/*
18045 * Register : GPIO/LoanIO 65 Input Mux Selection Register - GPLINMUX65
18046 *
18047 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
18048 * the input signal for GPIO/LoanIO 65.
18049 *
18050 * Only reset by a cold reset (ignores warm reset).
18051 *
18052 * NOTE: These registers should not be modified after IO configuration.There is no
18053 * support for dynamically changing the Pin Mux selections.
18054 *
18055 * Register Layout
18056 *
18057 * Bits | Access | Reset | Description
18058 * :-------|:-------|:------|:----------------------------------------
18059 * [0] | RW | 0x0 | GPIO/Loan IO65Input Mux Selection Field
18060 * [31:1] | ??? | 0x0 | *UNDEFINED*
18061 *
18062 */
18063/*
18064 * Field : GPIO/Loan IO65Input Mux Selection Field - sel
18065 *
18066 * Select source for GPIO/LoanIO 65.
18067 *
18068 * 0 : Source for GPIO/LoanIO 65 is GENERALIO17.
18069 *
18070 * 1 : Source for GPIO/LoanIO 65 is GENERALIO26.
18071 *
18072 * Field Access Macros:
18073 *
18074 */
18075/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */
18076#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_LSB 0
18077/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */
18078#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_MSB 0
18079/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */
18080#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_WIDTH 1
18081/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value. */
18082#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET_MSK 0x00000001
18083/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value. */
18084#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_CLR_MSK 0xfffffffe
18085/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */
18086#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_RESET 0x0
18087/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL field value from a register. */
18088#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0)
18089/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value suitable for setting the register. */
18090#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET(value) (((value) << 0) & 0x00000001)
18091
18092#ifndef __ASSEMBLY__
18093/*
18094 * WARNING: The C register and register group struct declarations are provided for
18095 * convenience and illustrative purposes. They should, however, be used with
18096 * caution as the C language standard provides no guarantees about the alignment or
18097 * atomicity of device memory accesses. The recommended practice for writing
18098 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18099 * alt_write_word() functions.
18100 *
18101 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX65.
18102 */
18103 struct ALT_SYSMGR_PINMUX_GPLINMUX65_s
18104{
18105 uint32_t sel : 1; /* GPIO/Loan IO65Input Mux Selection Field */
18106 uint32_t : 31; /* *UNDEFINED* */
18107};
18108
18109/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX65. */
18110typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX65_s ALT_SYSMGR_PINMUX_GPLINMUX65_t;
18111#endif /* __ASSEMBLY__ */
18112
18113/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX65 register from the beginning of the component. */
18114#define ALT_SYSMGR_PINMUX_GPLINMUX65_OFST 0x1bc
18115
18116/*
18117 * Register : GPIO/LoanIO 66 Input Mux Selection Register - GPLINMUX66
18118 *
18119 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
18120 * the input signal for GPIO/LoanIO 66.
18121 *
18122 * Only reset by a cold reset (ignores warm reset).
18123 *
18124 * NOTE: These registers should not be modified after IO configuration.There is no
18125 * support for dynamically changing the Pin Mux selections.
18126 *
18127 * Register Layout
18128 *
18129 * Bits | Access | Reset | Description
18130 * :-------|:-------|:------|:----------------------------------------
18131 * [0] | RW | 0x0 | GPIO/Loan IO66Input Mux Selection Field
18132 * [31:1] | ??? | 0x0 | *UNDEFINED*
18133 *
18134 */
18135/*
18136 * Field : GPIO/Loan IO66Input Mux Selection Field - sel
18137 *
18138 * Select source for GPIO/LoanIO 66.
18139 *
18140 * 0 : Source for GPIO/LoanIO 66 is GENERALIO18.
18141 *
18142 * 1 : Source for GPIO/LoanIO 66 is GENERALIO27.
18143 *
18144 * Field Access Macros:
18145 *
18146 */
18147/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */
18148#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_LSB 0
18149/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */
18150#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_MSB 0
18151/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */
18152#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_WIDTH 1
18153/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value. */
18154#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET_MSK 0x00000001
18155/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value. */
18156#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_CLR_MSK 0xfffffffe
18157/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */
18158#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_RESET 0x0
18159/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL field value from a register. */
18160#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0)
18161/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value suitable for setting the register. */
18162#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET(value) (((value) << 0) & 0x00000001)
18163
18164#ifndef __ASSEMBLY__
18165/*
18166 * WARNING: The C register and register group struct declarations are provided for
18167 * convenience and illustrative purposes. They should, however, be used with
18168 * caution as the C language standard provides no guarantees about the alignment or
18169 * atomicity of device memory accesses. The recommended practice for writing
18170 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18171 * alt_write_word() functions.
18172 *
18173 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX66.
18174 */
18175 struct ALT_SYSMGR_PINMUX_GPLINMUX66_s
18176{
18177 uint32_t sel : 1; /* GPIO/Loan IO66Input Mux Selection Field */
18178 uint32_t : 31; /* *UNDEFINED* */
18179};
18180
18181/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX66. */
18182typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX66_s ALT_SYSMGR_PINMUX_GPLINMUX66_t;
18183#endif /* __ASSEMBLY__ */
18184
18185/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX66 register from the beginning of the component. */
18186#define ALT_SYSMGR_PINMUX_GPLINMUX66_OFST 0x1c0
18187
18188/*
18189 * Register : GPIO/LoanIO 67 Input Mux Selection Register - GPLINMUX67
18190 *
18191 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
18192 * the input signal for GPIO/LoanIO 67.
18193 *
18194 * Only reset by a cold reset (ignores warm reset).
18195 *
18196 * NOTE: These registers should not be modified after IO configuration.There is no
18197 * support for dynamically changing the Pin Mux selections.
18198 *
18199 * Register Layout
18200 *
18201 * Bits | Access | Reset | Description
18202 * :-------|:-------|:------|:----------------------------------------
18203 * [0] | RW | 0x0 | GPIO/Loan IO67Input Mux Selection Field
18204 * [31:1] | ??? | 0x0 | *UNDEFINED*
18205 *
18206 */
18207/*
18208 * Field : GPIO/Loan IO67Input Mux Selection Field - sel
18209 *
18210 * Select source for GPIO/LoanIO 67.
18211 *
18212 * 0 : Source for GPIO/LoanIO 67 is GENERALIO19.
18213 *
18214 * 1 : Source for GPIO/LoanIO 67 is GENERALIO28.
18215 *
18216 * Field Access Macros:
18217 *
18218 */
18219/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */
18220#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_LSB 0
18221/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */
18222#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_MSB 0
18223/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */
18224#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_WIDTH 1
18225/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value. */
18226#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET_MSK 0x00000001
18227/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value. */
18228#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_CLR_MSK 0xfffffffe
18229/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */
18230#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_RESET 0x0
18231/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL field value from a register. */
18232#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0)
18233/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value suitable for setting the register. */
18234#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET(value) (((value) << 0) & 0x00000001)
18235
18236#ifndef __ASSEMBLY__
18237/*
18238 * WARNING: The C register and register group struct declarations are provided for
18239 * convenience and illustrative purposes. They should, however, be used with
18240 * caution as the C language standard provides no guarantees about the alignment or
18241 * atomicity of device memory accesses. The recommended practice for writing
18242 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18243 * alt_write_word() functions.
18244 *
18245 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX67.
18246 */
18247 struct ALT_SYSMGR_PINMUX_GPLINMUX67_s
18248{
18249 uint32_t sel : 1; /* GPIO/Loan IO67Input Mux Selection Field */
18250 uint32_t : 31; /* *UNDEFINED* */
18251};
18252
18253/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX67. */
18254typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX67_s ALT_SYSMGR_PINMUX_GPLINMUX67_t;
18255#endif /* __ASSEMBLY__ */
18256
18257/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX67 register from the beginning of the component. */
18258#define ALT_SYSMGR_PINMUX_GPLINMUX67_OFST 0x1c4
18259
18260/*
18261 * Register : GPIO/LoanIO 68 Input Mux Selection Register - GPLINMUX68
18262 *
18263 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
18264 * the input signal for GPIO/LoanIO 68.
18265 *
18266 * Only reset by a cold reset (ignores warm reset).
18267 *
18268 * NOTE: These registers should not be modified after IO configuration.There is no
18269 * support for dynamically changing the Pin Mux selections.
18270 *
18271 * Register Layout
18272 *
18273 * Bits | Access | Reset | Description
18274 * :-------|:-------|:------|:----------------------------------------
18275 * [0] | RW | 0x0 | GPIO/Loan IO68Input Mux Selection Field
18276 * [31:1] | ??? | 0x0 | *UNDEFINED*
18277 *
18278 */
18279/*
18280 * Field : GPIO/Loan IO68Input Mux Selection Field - sel
18281 *
18282 * Select source for GPIO/LoanIO 68.
18283 *
18284 * 0 : Source for GPIO/LoanIO 68 is GENERALIO20.
18285 *
18286 * 1 : Source for GPIO/LoanIO 68 is GENERALIO29.
18287 *
18288 * Field Access Macros:
18289 *
18290 */
18291/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */
18292#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_LSB 0
18293/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */
18294#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_MSB 0
18295/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */
18296#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_WIDTH 1
18297/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value. */
18298#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET_MSK 0x00000001
18299/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value. */
18300#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_CLR_MSK 0xfffffffe
18301/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */
18302#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_RESET 0x0
18303/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL field value from a register. */
18304#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0)
18305/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value suitable for setting the register. */
18306#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET(value) (((value) << 0) & 0x00000001)
18307
18308#ifndef __ASSEMBLY__
18309/*
18310 * WARNING: The C register and register group struct declarations are provided for
18311 * convenience and illustrative purposes. They should, however, be used with
18312 * caution as the C language standard provides no guarantees about the alignment or
18313 * atomicity of device memory accesses. The recommended practice for writing
18314 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18315 * alt_write_word() functions.
18316 *
18317 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX68.
18318 */
18319 struct ALT_SYSMGR_PINMUX_GPLINMUX68_s
18320{
18321 uint32_t sel : 1; /* GPIO/Loan IO68Input Mux Selection Field */
18322 uint32_t : 31; /* *UNDEFINED* */
18323};
18324
18325/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX68. */
18326typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX68_s ALT_SYSMGR_PINMUX_GPLINMUX68_t;
18327#endif /* __ASSEMBLY__ */
18328
18329/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX68 register from the beginning of the component. */
18330#define ALT_SYSMGR_PINMUX_GPLINMUX68_OFST 0x1c8
18331
18332/*
18333 * Register : GPIO/LoanIO 69 Input Mux Selection Register - GPLINMUX69
18334 *
18335 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
18336 * the input signal for GPIO/LoanIO 69.
18337 *
18338 * Only reset by a cold reset (ignores warm reset).
18339 *
18340 * NOTE: These registers should not be modified after IO configuration.There is no
18341 * support for dynamically changing the Pin Mux selections.
18342 *
18343 * Register Layout
18344 *
18345 * Bits | Access | Reset | Description
18346 * :-------|:-------|:------|:----------------------------------------
18347 * [0] | RW | 0x0 | GPIO/Loan IO69Input Mux Selection Field
18348 * [31:1] | ??? | 0x0 | *UNDEFINED*
18349 *
18350 */
18351/*
18352 * Field : GPIO/Loan IO69Input Mux Selection Field - sel
18353 *
18354 * Select source for GPIO/LoanIO 69.
18355 *
18356 * 0 : Source for GPIO/LoanIO 69 is GENERALIO21.
18357 *
18358 * 1 : Source for GPIO/LoanIO 69 is GENERALIO30.
18359 *
18360 * Field Access Macros:
18361 *
18362 */
18363/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */
18364#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_LSB 0
18365/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */
18366#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_MSB 0
18367/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */
18368#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_WIDTH 1
18369/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value. */
18370#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET_MSK 0x00000001
18371/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value. */
18372#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_CLR_MSK 0xfffffffe
18373/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */
18374#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_RESET 0x0
18375/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL field value from a register. */
18376#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0)
18377/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value suitable for setting the register. */
18378#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET(value) (((value) << 0) & 0x00000001)
18379
18380#ifndef __ASSEMBLY__
18381/*
18382 * WARNING: The C register and register group struct declarations are provided for
18383 * convenience and illustrative purposes. They should, however, be used with
18384 * caution as the C language standard provides no guarantees about the alignment or
18385 * atomicity of device memory accesses. The recommended practice for writing
18386 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18387 * alt_write_word() functions.
18388 *
18389 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX69.
18390 */
18391 struct ALT_SYSMGR_PINMUX_GPLINMUX69_s
18392{
18393 uint32_t sel : 1; /* GPIO/Loan IO69Input Mux Selection Field */
18394 uint32_t : 31; /* *UNDEFINED* */
18395};
18396
18397/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX69. */
18398typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX69_s ALT_SYSMGR_PINMUX_GPLINMUX69_t;
18399#endif /* __ASSEMBLY__ */
18400
18401/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX69 register from the beginning of the component. */
18402#define ALT_SYSMGR_PINMUX_GPLINMUX69_OFST 0x1cc
18403
18404/*
18405 * Register : GPIO/LoanIO 70 Input Mux Selection Register - GPLINMUX70
18406 *
18407 * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
18408 * the input signal for GPIO/LoanIO 70.
18409 *
18410 * Only reset by a cold reset (ignores warm reset).
18411 *
18412 * NOTE: These registers should not be modified after IO configuration.There is no
18413 * support for dynamically changing the Pin Mux selections.
18414 *
18415 * Register Layout
18416 *
18417 * Bits | Access | Reset | Description
18418 * :-------|:-------|:------|:----------------------------------------
18419 * [0] | RW | 0x0 | GPIO/Loan IO70Input Mux Selection Field
18420 * [31:1] | ??? | 0x0 | *UNDEFINED*
18421 *
18422 */
18423/*
18424 * Field : GPIO/Loan IO70Input Mux Selection Field - sel
18425 *
18426 * Select source for GPIO/LoanIO 70.
18427 *
18428 * 0 : Source for GPIO/LoanIO 70 is GENERALIO22.
18429 *
18430 * 1 : Source for GPIO/LoanIO 70 is GENERALIO31.
18431 *
18432 * Field Access Macros:
18433 *
18434 */
18435/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */
18436#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_LSB 0
18437/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */
18438#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_MSB 0
18439/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */
18440#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_WIDTH 1
18441/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value. */
18442#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET_MSK 0x00000001
18443/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value. */
18444#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_CLR_MSK 0xfffffffe
18445/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */
18446#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_RESET 0x0
18447/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL field value from a register. */
18448#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0)
18449/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value suitable for setting the register. */
18450#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET(value) (((value) << 0) & 0x00000001)
18451
18452#ifndef __ASSEMBLY__
18453/*
18454 * WARNING: The C register and register group struct declarations are provided for
18455 * convenience and illustrative purposes. They should, however, be used with
18456 * caution as the C language standard provides no guarantees about the alignment or
18457 * atomicity of device memory accesses. The recommended practice for writing
18458 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18459 * alt_write_word() functions.
18460 *
18461 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX70.
18462 */
18463 struct ALT_SYSMGR_PINMUX_GPLINMUX70_s
18464{
18465 uint32_t sel : 1; /* GPIO/Loan IO70Input Mux Selection Field */
18466 uint32_t : 31; /* *UNDEFINED* */
18467};
18468
18469/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX70. */
18470typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX70_s ALT_SYSMGR_PINMUX_GPLINMUX70_t;
18471#endif /* __ASSEMBLY__ */
18472
18473/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX70 register from the beginning of the component. */
18474#define ALT_SYSMGR_PINMUX_GPLINMUX70_OFST 0x1d0
18475
18476/*
18477 * Register : GPIO/LoanIO 0 Output/Output Enable Mux Selection Register - GPLMUX0
18478 *
18479 * Selection between GPIO and LoanIO output and output enable for GPIO0 and
18480 * LoanIO0. These signals drive the Pin Mux. The Pin Mux must be configured to use
18481 * GPIO/LoanIO in addition to these settings
18482 *
18483 * Only reset by a cold reset (ignores warm reset).
18484 *
18485 * NOTE: These registers should not be modified after IO configuration.There is no
18486 * support for dynamically changing the Pin Mux selections.
18487 *
18488 * Register Layout
18489 *
18490 * Bits | Access | Reset | Description
18491 * :-------|:-------|:------|:---------------------------------------
18492 * [0] | RW | 0x0 | GPIO/Loan IO0Input Mux Selection Field
18493 * [31:1] | ??? | 0x0 | *UNDEFINED*
18494 *
18495 */
18496/*
18497 * Field : GPIO/Loan IO0Input Mux Selection Field - sel
18498 *
18499 * Select source for GPIO/LoanIO 0.
18500 *
18501 * 0 : LoanIO 0 controls GPIO/LOANIO[0] output and output enable signals.
18502 *
18503 * 1 : GPIO 0 controls GPIO/LOANI[0] output and output enable signals.
18504 *
18505 * Field Access Macros:
18506 *
18507 */
18508/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */
18509#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_LSB 0
18510/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */
18511#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_MSB 0
18512/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */
18513#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_WIDTH 1
18514/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value. */
18515#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET_MSK 0x00000001
18516/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value. */
18517#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_CLR_MSK 0xfffffffe
18518/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */
18519#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_RESET 0x0
18520/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX0_SEL field value from a register. */
18521#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_GET(value) (((value) & 0x00000001) >> 0)
18522/* Produces a ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value suitable for setting the register. */
18523#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET(value) (((value) << 0) & 0x00000001)
18524
18525#ifndef __ASSEMBLY__
18526/*
18527 * WARNING: The C register and register group struct declarations are provided for
18528 * convenience and illustrative purposes. They should, however, be used with
18529 * caution as the C language standard provides no guarantees about the alignment or
18530 * atomicity of device memory accesses. The recommended practice for writing
18531 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18532 * alt_write_word() functions.
18533 *
18534 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX0.
18535 */
18536 struct ALT_SYSMGR_PINMUX_GPLMUX0_s
18537{
18538 uint32_t sel : 1; /* GPIO/Loan IO0Input Mux Selection Field */
18539 uint32_t : 31; /* *UNDEFINED* */
18540};
18541
18542/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX0. */
18543typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX0_s ALT_SYSMGR_PINMUX_GPLMUX0_t;
18544#endif /* __ASSEMBLY__ */
18545
18546/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX0 register from the beginning of the component. */
18547#define ALT_SYSMGR_PINMUX_GPLMUX0_OFST 0x1d4
18548
18549/*
18550 * Register : GPIO/LoanIO 1 Output/Output Enable Mux Selection Register - GPLMUX1
18551 *
18552 * Selection between GPIO and LoanIO output and output enable for GPIO1 and
18553 * LoanIO1. These signals drive the Pin Mux. The Pin Mux must be configured to use
18554 * GPIO/LoanIO in addition to these settings
18555 *
18556 * Only reset by a cold reset (ignores warm reset).
18557 *
18558 * NOTE: These registers should not be modified after IO configuration.There is no
18559 * support for dynamically changing the Pin Mux selections.
18560 *
18561 * Register Layout
18562 *
18563 * Bits | Access | Reset | Description
18564 * :-------|:-------|:------|:---------------------------------------
18565 * [0] | RW | 0x0 | GPIO/Loan IO1Input Mux Selection Field
18566 * [31:1] | ??? | 0x0 | *UNDEFINED*
18567 *
18568 */
18569/*
18570 * Field : GPIO/Loan IO1Input Mux Selection Field - sel
18571 *
18572 * Select source for GPIO/LoanIO 1.
18573 *
18574 * 0 : LoanIO 1 controls GPIO/LOANIO[1] output and output enable signals.
18575 *
18576 * 1 : GPIO 1 controls GPIO/LOANI[1] output and output enable signals.
18577 *
18578 * Field Access Macros:
18579 *
18580 */
18581/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */
18582#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_LSB 0
18583/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */
18584#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_MSB 0
18585/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */
18586#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_WIDTH 1
18587/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value. */
18588#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET_MSK 0x00000001
18589/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value. */
18590#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_CLR_MSK 0xfffffffe
18591/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */
18592#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_RESET 0x0
18593/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX1_SEL field value from a register. */
18594#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_GET(value) (((value) & 0x00000001) >> 0)
18595/* Produces a ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value suitable for setting the register. */
18596#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET(value) (((value) << 0) & 0x00000001)
18597
18598#ifndef __ASSEMBLY__
18599/*
18600 * WARNING: The C register and register group struct declarations are provided for
18601 * convenience and illustrative purposes. They should, however, be used with
18602 * caution as the C language standard provides no guarantees about the alignment or
18603 * atomicity of device memory accesses. The recommended practice for writing
18604 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18605 * alt_write_word() functions.
18606 *
18607 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX1.
18608 */
18609 struct ALT_SYSMGR_PINMUX_GPLMUX1_s
18610{
18611 uint32_t sel : 1; /* GPIO/Loan IO1Input Mux Selection Field */
18612 uint32_t : 31; /* *UNDEFINED* */
18613};
18614
18615/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX1. */
18616typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX1_s ALT_SYSMGR_PINMUX_GPLMUX1_t;
18617#endif /* __ASSEMBLY__ */
18618
18619/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX1 register from the beginning of the component. */
18620#define ALT_SYSMGR_PINMUX_GPLMUX1_OFST 0x1d8
18621
18622/*
18623 * Register : GPIO/LoanIO 2 Output/Output Enable Mux Selection Register - GPLMUX2
18624 *
18625 * Selection between GPIO and LoanIO output and output enable for GPIO2 and
18626 * LoanIO2. These signals drive the Pin Mux. The Pin Mux must be configured to use
18627 * GPIO/LoanIO in addition to these settings
18628 *
18629 * Only reset by a cold reset (ignores warm reset).
18630 *
18631 * NOTE: These registers should not be modified after IO configuration.There is no
18632 * support for dynamically changing the Pin Mux selections.
18633 *
18634 * Register Layout
18635 *
18636 * Bits | Access | Reset | Description
18637 * :-------|:-------|:------|:---------------------------------------
18638 * [0] | RW | 0x0 | GPIO/Loan IO2Input Mux Selection Field
18639 * [31:1] | ??? | 0x0 | *UNDEFINED*
18640 *
18641 */
18642/*
18643 * Field : GPIO/Loan IO2Input Mux Selection Field - sel
18644 *
18645 * Select source for GPIO/LoanIO 2.
18646 *
18647 * 0 : LoanIO 2 controls GPIO/LOANIO[2] output and output enable signals.
18648 *
18649 * 1 : GPIO 2 controls GPIO/LOANI[2] output and output enable signals.
18650 *
18651 * Field Access Macros:
18652 *
18653 */
18654/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */
18655#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_LSB 0
18656/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */
18657#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_MSB 0
18658/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */
18659#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_WIDTH 1
18660/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value. */
18661#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET_MSK 0x00000001
18662/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value. */
18663#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_CLR_MSK 0xfffffffe
18664/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */
18665#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_RESET 0x0
18666/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX2_SEL field value from a register. */
18667#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_GET(value) (((value) & 0x00000001) >> 0)
18668/* Produces a ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value suitable for setting the register. */
18669#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET(value) (((value) << 0) & 0x00000001)
18670
18671#ifndef __ASSEMBLY__
18672/*
18673 * WARNING: The C register and register group struct declarations are provided for
18674 * convenience and illustrative purposes. They should, however, be used with
18675 * caution as the C language standard provides no guarantees about the alignment or
18676 * atomicity of device memory accesses. The recommended practice for writing
18677 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18678 * alt_write_word() functions.
18679 *
18680 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX2.
18681 */
18682 struct ALT_SYSMGR_PINMUX_GPLMUX2_s
18683{
18684 uint32_t sel : 1; /* GPIO/Loan IO2Input Mux Selection Field */
18685 uint32_t : 31; /* *UNDEFINED* */
18686};
18687
18688/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX2. */
18689typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX2_s ALT_SYSMGR_PINMUX_GPLMUX2_t;
18690#endif /* __ASSEMBLY__ */
18691
18692/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX2 register from the beginning of the component. */
18693#define ALT_SYSMGR_PINMUX_GPLMUX2_OFST 0x1dc
18694
18695/*
18696 * Register : GPIO/LoanIO 3 Output/Output Enable Mux Selection Register - GPLMUX3
18697 *
18698 * Selection between GPIO and LoanIO output and output enable for GPIO3 and
18699 * LoanIO3. These signals drive the Pin Mux. The Pin Mux must be configured to use
18700 * GPIO/LoanIO in addition to these settings
18701 *
18702 * Only reset by a cold reset (ignores warm reset).
18703 *
18704 * NOTE: These registers should not be modified after IO configuration.There is no
18705 * support for dynamically changing the Pin Mux selections.
18706 *
18707 * Register Layout
18708 *
18709 * Bits | Access | Reset | Description
18710 * :-------|:-------|:------|:---------------------------------------
18711 * [0] | RW | 0x0 | GPIO/Loan IO3Input Mux Selection Field
18712 * [31:1] | ??? | 0x0 | *UNDEFINED*
18713 *
18714 */
18715/*
18716 * Field : GPIO/Loan IO3Input Mux Selection Field - sel
18717 *
18718 * Select source for GPIO/LoanIO 3.
18719 *
18720 * 0 : LoanIO 3 controls GPIO/LOANIO[3] output and output enable signals.
18721 *
18722 * 1 : GPIO 3 controls GPIO/LOANI[3] output and output enable signals.
18723 *
18724 * Field Access Macros:
18725 *
18726 */
18727/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */
18728#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_LSB 0
18729/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */
18730#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_MSB 0
18731/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */
18732#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_WIDTH 1
18733/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value. */
18734#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET_MSK 0x00000001
18735/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value. */
18736#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_CLR_MSK 0xfffffffe
18737/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */
18738#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_RESET 0x0
18739/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX3_SEL field value from a register. */
18740#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_GET(value) (((value) & 0x00000001) >> 0)
18741/* Produces a ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value suitable for setting the register. */
18742#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET(value) (((value) << 0) & 0x00000001)
18743
18744#ifndef __ASSEMBLY__
18745/*
18746 * WARNING: The C register and register group struct declarations are provided for
18747 * convenience and illustrative purposes. They should, however, be used with
18748 * caution as the C language standard provides no guarantees about the alignment or
18749 * atomicity of device memory accesses. The recommended practice for writing
18750 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18751 * alt_write_word() functions.
18752 *
18753 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX3.
18754 */
18755 struct ALT_SYSMGR_PINMUX_GPLMUX3_s
18756{
18757 uint32_t sel : 1; /* GPIO/Loan IO3Input Mux Selection Field */
18758 uint32_t : 31; /* *UNDEFINED* */
18759};
18760
18761/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX3. */
18762typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX3_s ALT_SYSMGR_PINMUX_GPLMUX3_t;
18763#endif /* __ASSEMBLY__ */
18764
18765/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX3 register from the beginning of the component. */
18766#define ALT_SYSMGR_PINMUX_GPLMUX3_OFST 0x1e0
18767
18768/*
18769 * Register : GPIO/LoanIO 4 Output/Output Enable Mux Selection Register - GPLMUX4
18770 *
18771 * Selection between GPIO and LoanIO output and output enable for GPIO4 and
18772 * LoanIO4. These signals drive the Pin Mux. The Pin Mux must be configured to use
18773 * GPIO/LoanIO in addition to these settings
18774 *
18775 * Only reset by a cold reset (ignores warm reset).
18776 *
18777 * NOTE: These registers should not be modified after IO configuration.There is no
18778 * support for dynamically changing the Pin Mux selections.
18779 *
18780 * Register Layout
18781 *
18782 * Bits | Access | Reset | Description
18783 * :-------|:-------|:------|:---------------------------------------
18784 * [0] | RW | 0x0 | GPIO/Loan IO4Input Mux Selection Field
18785 * [31:1] | ??? | 0x0 | *UNDEFINED*
18786 *
18787 */
18788/*
18789 * Field : GPIO/Loan IO4Input Mux Selection Field - sel
18790 *
18791 * Select source for GPIO/LoanIO 4.
18792 *
18793 * 0 : LoanIO 4 controls GPIO/LOANIO[4] output and output enable signals.
18794 *
18795 * 1 : GPIO 4 controls GPIO/LOANI[4] output and output enable signals.
18796 *
18797 * Field Access Macros:
18798 *
18799 */
18800/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */
18801#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_LSB 0
18802/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */
18803#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_MSB 0
18804/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */
18805#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_WIDTH 1
18806/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value. */
18807#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET_MSK 0x00000001
18808/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value. */
18809#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_CLR_MSK 0xfffffffe
18810/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */
18811#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_RESET 0x0
18812/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX4_SEL field value from a register. */
18813#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_GET(value) (((value) & 0x00000001) >> 0)
18814/* Produces a ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value suitable for setting the register. */
18815#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET(value) (((value) << 0) & 0x00000001)
18816
18817#ifndef __ASSEMBLY__
18818/*
18819 * WARNING: The C register and register group struct declarations are provided for
18820 * convenience and illustrative purposes. They should, however, be used with
18821 * caution as the C language standard provides no guarantees about the alignment or
18822 * atomicity of device memory accesses. The recommended practice for writing
18823 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18824 * alt_write_word() functions.
18825 *
18826 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX4.
18827 */
18828 struct ALT_SYSMGR_PINMUX_GPLMUX4_s
18829{
18830 uint32_t sel : 1; /* GPIO/Loan IO4Input Mux Selection Field */
18831 uint32_t : 31; /* *UNDEFINED* */
18832};
18833
18834/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX4. */
18835typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX4_s ALT_SYSMGR_PINMUX_GPLMUX4_t;
18836#endif /* __ASSEMBLY__ */
18837
18838/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX4 register from the beginning of the component. */
18839#define ALT_SYSMGR_PINMUX_GPLMUX4_OFST 0x1e4
18840
18841/*
18842 * Register : GPIO/LoanIO 5 Output/Output Enable Mux Selection Register - GPLMUX5
18843 *
18844 * Selection between GPIO and LoanIO output and output enable for GPIO5 and
18845 * LoanIO5. These signals drive the Pin Mux. The Pin Mux must be configured to use
18846 * GPIO/LoanIO in addition to these settings
18847 *
18848 * Only reset by a cold reset (ignores warm reset).
18849 *
18850 * NOTE: These registers should not be modified after IO configuration.There is no
18851 * support for dynamically changing the Pin Mux selections.
18852 *
18853 * Register Layout
18854 *
18855 * Bits | Access | Reset | Description
18856 * :-------|:-------|:------|:---------------------------------------
18857 * [0] | RW | 0x0 | GPIO/Loan IO5Input Mux Selection Field
18858 * [31:1] | ??? | 0x0 | *UNDEFINED*
18859 *
18860 */
18861/*
18862 * Field : GPIO/Loan IO5Input Mux Selection Field - sel
18863 *
18864 * Select source for GPIO/LoanIO 5.
18865 *
18866 * 0 : LoanIO 5 controls GPIO/LOANIO[5] output and output enable signals.
18867 *
18868 * 1 : GPIO 5 controls GPIO/LOANI[5] output and output enable signals.
18869 *
18870 * Field Access Macros:
18871 *
18872 */
18873/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */
18874#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_LSB 0
18875/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */
18876#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_MSB 0
18877/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */
18878#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_WIDTH 1
18879/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value. */
18880#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET_MSK 0x00000001
18881/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value. */
18882#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_CLR_MSK 0xfffffffe
18883/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */
18884#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_RESET 0x0
18885/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX5_SEL field value from a register. */
18886#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_GET(value) (((value) & 0x00000001) >> 0)
18887/* Produces a ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value suitable for setting the register. */
18888#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET(value) (((value) << 0) & 0x00000001)
18889
18890#ifndef __ASSEMBLY__
18891/*
18892 * WARNING: The C register and register group struct declarations are provided for
18893 * convenience and illustrative purposes. They should, however, be used with
18894 * caution as the C language standard provides no guarantees about the alignment or
18895 * atomicity of device memory accesses. The recommended practice for writing
18896 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18897 * alt_write_word() functions.
18898 *
18899 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX5.
18900 */
18901 struct ALT_SYSMGR_PINMUX_GPLMUX5_s
18902{
18903 uint32_t sel : 1; /* GPIO/Loan IO5Input Mux Selection Field */
18904 uint32_t : 31; /* *UNDEFINED* */
18905};
18906
18907/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX5. */
18908typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX5_s ALT_SYSMGR_PINMUX_GPLMUX5_t;
18909#endif /* __ASSEMBLY__ */
18910
18911/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX5 register from the beginning of the component. */
18912#define ALT_SYSMGR_PINMUX_GPLMUX5_OFST 0x1e8
18913
18914/*
18915 * Register : GPIO/LoanIO 6 Output/Output Enable Mux Selection Register - GPLMUX6
18916 *
18917 * Selection between GPIO and LoanIO output and output enable for GPIO6 and
18918 * LoanIO6. These signals drive the Pin Mux. The Pin Mux must be configured to use
18919 * GPIO/LoanIO in addition to these settings
18920 *
18921 * Only reset by a cold reset (ignores warm reset).
18922 *
18923 * NOTE: These registers should not be modified after IO configuration.There is no
18924 * support for dynamically changing the Pin Mux selections.
18925 *
18926 * Register Layout
18927 *
18928 * Bits | Access | Reset | Description
18929 * :-------|:-------|:------|:---------------------------------------
18930 * [0] | RW | 0x0 | GPIO/Loan IO6Input Mux Selection Field
18931 * [31:1] | ??? | 0x0 | *UNDEFINED*
18932 *
18933 */
18934/*
18935 * Field : GPIO/Loan IO6Input Mux Selection Field - sel
18936 *
18937 * Select source for GPIO/LoanIO 6.
18938 *
18939 * 0 : LoanIO 6 controls GPIO/LOANIO[6] output and output enable signals.
18940 *
18941 * 1 : GPIO 6 controls GPIO/LOANI[6] output and output enable signals.
18942 *
18943 * Field Access Macros:
18944 *
18945 */
18946/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */
18947#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_LSB 0
18948/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */
18949#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_MSB 0
18950/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */
18951#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_WIDTH 1
18952/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value. */
18953#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET_MSK 0x00000001
18954/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value. */
18955#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_CLR_MSK 0xfffffffe
18956/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */
18957#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_RESET 0x0
18958/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX6_SEL field value from a register. */
18959#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_GET(value) (((value) & 0x00000001) >> 0)
18960/* Produces a ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value suitable for setting the register. */
18961#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET(value) (((value) << 0) & 0x00000001)
18962
18963#ifndef __ASSEMBLY__
18964/*
18965 * WARNING: The C register and register group struct declarations are provided for
18966 * convenience and illustrative purposes. They should, however, be used with
18967 * caution as the C language standard provides no guarantees about the alignment or
18968 * atomicity of device memory accesses. The recommended practice for writing
18969 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18970 * alt_write_word() functions.
18971 *
18972 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX6.
18973 */
18974 struct ALT_SYSMGR_PINMUX_GPLMUX6_s
18975{
18976 uint32_t sel : 1; /* GPIO/Loan IO6Input Mux Selection Field */
18977 uint32_t : 31; /* *UNDEFINED* */
18978};
18979
18980/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX6. */
18981typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX6_s ALT_SYSMGR_PINMUX_GPLMUX6_t;
18982#endif /* __ASSEMBLY__ */
18983
18984/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX6 register from the beginning of the component. */
18985#define ALT_SYSMGR_PINMUX_GPLMUX6_OFST 0x1ec
18986
18987/*
18988 * Register : GPIO/LoanIO 7 Output/Output Enable Mux Selection Register - GPLMUX7
18989 *
18990 * Selection between GPIO and LoanIO output and output enable for GPIO7 and
18991 * LoanIO7. These signals drive the Pin Mux. The Pin Mux must be configured to use
18992 * GPIO/LoanIO in addition to these settings
18993 *
18994 * Only reset by a cold reset (ignores warm reset).
18995 *
18996 * NOTE: These registers should not be modified after IO configuration.There is no
18997 * support for dynamically changing the Pin Mux selections.
18998 *
18999 * Register Layout
19000 *
19001 * Bits | Access | Reset | Description
19002 * :-------|:-------|:------|:---------------------------------------
19003 * [0] | RW | 0x0 | GPIO/Loan IO7Input Mux Selection Field
19004 * [31:1] | ??? | 0x0 | *UNDEFINED*
19005 *
19006 */
19007/*
19008 * Field : GPIO/Loan IO7Input Mux Selection Field - sel
19009 *
19010 * Select source for GPIO/LoanIO 7.
19011 *
19012 * 0 : LoanIO 7 controls GPIO/LOANIO[7] output and output enable signals.
19013 *
19014 * 1 : GPIO 7 controls GPIO/LOANI[7] output and output enable signals.
19015 *
19016 * Field Access Macros:
19017 *
19018 */
19019/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */
19020#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_LSB 0
19021/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */
19022#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_MSB 0
19023/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */
19024#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_WIDTH 1
19025/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value. */
19026#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET_MSK 0x00000001
19027/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value. */
19028#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_CLR_MSK 0xfffffffe
19029/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */
19030#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_RESET 0x0
19031/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX7_SEL field value from a register. */
19032#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_GET(value) (((value) & 0x00000001) >> 0)
19033/* Produces a ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value suitable for setting the register. */
19034#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET(value) (((value) << 0) & 0x00000001)
19035
19036#ifndef __ASSEMBLY__
19037/*
19038 * WARNING: The C register and register group struct declarations are provided for
19039 * convenience and illustrative purposes. They should, however, be used with
19040 * caution as the C language standard provides no guarantees about the alignment or
19041 * atomicity of device memory accesses. The recommended practice for writing
19042 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19043 * alt_write_word() functions.
19044 *
19045 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX7.
19046 */
19047 struct ALT_SYSMGR_PINMUX_GPLMUX7_s
19048{
19049 uint32_t sel : 1; /* GPIO/Loan IO7Input Mux Selection Field */
19050 uint32_t : 31; /* *UNDEFINED* */
19051};
19052
19053/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX7. */
19054typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX7_s ALT_SYSMGR_PINMUX_GPLMUX7_t;
19055#endif /* __ASSEMBLY__ */
19056
19057/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX7 register from the beginning of the component. */
19058#define ALT_SYSMGR_PINMUX_GPLMUX7_OFST 0x1f0
19059
19060/*
19061 * Register : GPIO/LoanIO 8 Output/Output Enable Mux Selection Register - GPLMUX8
19062 *
19063 * Selection between GPIO and LoanIO output and output enable for GPIO8 and
19064 * LoanIO8. These signals drive the Pin Mux. The Pin Mux must be configured to use
19065 * GPIO/LoanIO in addition to these settings
19066 *
19067 * Only reset by a cold reset (ignores warm reset).
19068 *
19069 * NOTE: These registers should not be modified after IO configuration.There is no
19070 * support for dynamically changing the Pin Mux selections.
19071 *
19072 * Register Layout
19073 *
19074 * Bits | Access | Reset | Description
19075 * :-------|:-------|:------|:---------------------------------------
19076 * [0] | RW | 0x0 | GPIO/Loan IO8Input Mux Selection Field
19077 * [31:1] | ??? | 0x0 | *UNDEFINED*
19078 *
19079 */
19080/*
19081 * Field : GPIO/Loan IO8Input Mux Selection Field - sel
19082 *
19083 * Select source for GPIO/LoanIO 8.
19084 *
19085 * 0 : LoanIO 8 controls GPIO/LOANIO[8] output and output enable signals.
19086 *
19087 * 1 : GPIO 8 controls GPIO/LOANI[8] output and output enable signals.
19088 *
19089 * Field Access Macros:
19090 *
19091 */
19092/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */
19093#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_LSB 0
19094/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */
19095#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_MSB 0
19096/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */
19097#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_WIDTH 1
19098/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value. */
19099#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET_MSK 0x00000001
19100/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value. */
19101#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_CLR_MSK 0xfffffffe
19102/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */
19103#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_RESET 0x0
19104/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX8_SEL field value from a register. */
19105#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_GET(value) (((value) & 0x00000001) >> 0)
19106/* Produces a ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value suitable for setting the register. */
19107#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET(value) (((value) << 0) & 0x00000001)
19108
19109#ifndef __ASSEMBLY__
19110/*
19111 * WARNING: The C register and register group struct declarations are provided for
19112 * convenience and illustrative purposes. They should, however, be used with
19113 * caution as the C language standard provides no guarantees about the alignment or
19114 * atomicity of device memory accesses. The recommended practice for writing
19115 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19116 * alt_write_word() functions.
19117 *
19118 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX8.
19119 */
19120 struct ALT_SYSMGR_PINMUX_GPLMUX8_s
19121{
19122 uint32_t sel : 1; /* GPIO/Loan IO8Input Mux Selection Field */
19123 uint32_t : 31; /* *UNDEFINED* */
19124};
19125
19126/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX8. */
19127typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX8_s ALT_SYSMGR_PINMUX_GPLMUX8_t;
19128#endif /* __ASSEMBLY__ */
19129
19130/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX8 register from the beginning of the component. */
19131#define ALT_SYSMGR_PINMUX_GPLMUX8_OFST 0x1f4
19132
19133/*
19134 * Register : GPIO/LoanIO 9 Output/Output Enable Mux Selection Register - GPLMUX9
19135 *
19136 * Selection between GPIO and LoanIO output and output enable for GPIO9 and
19137 * LoanIO9. These signals drive the Pin Mux. The Pin Mux must be configured to use
19138 * GPIO/LoanIO in addition to these settings
19139 *
19140 * Only reset by a cold reset (ignores warm reset).
19141 *
19142 * NOTE: These registers should not be modified after IO configuration.There is no
19143 * support for dynamically changing the Pin Mux selections.
19144 *
19145 * Register Layout
19146 *
19147 * Bits | Access | Reset | Description
19148 * :-------|:-------|:------|:---------------------------------------
19149 * [0] | RW | 0x0 | GPIO/Loan IO9Input Mux Selection Field
19150 * [31:1] | ??? | 0x0 | *UNDEFINED*
19151 *
19152 */
19153/*
19154 * Field : GPIO/Loan IO9Input Mux Selection Field - sel
19155 *
19156 * Select source for GPIO/LoanIO 9.
19157 *
19158 * 0 : LoanIO 9 controls GPIO/LOANIO[9] output and output enable signals.
19159 *
19160 * 1 : GPIO 9 controls GPIO/LOANI[9] output and output enable signals.
19161 *
19162 * Field Access Macros:
19163 *
19164 */
19165/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */
19166#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_LSB 0
19167/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */
19168#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_MSB 0
19169/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */
19170#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_WIDTH 1
19171/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value. */
19172#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET_MSK 0x00000001
19173/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value. */
19174#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_CLR_MSK 0xfffffffe
19175/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */
19176#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_RESET 0x0
19177/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX9_SEL field value from a register. */
19178#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_GET(value) (((value) & 0x00000001) >> 0)
19179/* Produces a ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value suitable for setting the register. */
19180#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET(value) (((value) << 0) & 0x00000001)
19181
19182#ifndef __ASSEMBLY__
19183/*
19184 * WARNING: The C register and register group struct declarations are provided for
19185 * convenience and illustrative purposes. They should, however, be used with
19186 * caution as the C language standard provides no guarantees about the alignment or
19187 * atomicity of device memory accesses. The recommended practice for writing
19188 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19189 * alt_write_word() functions.
19190 *
19191 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX9.
19192 */
19193 struct ALT_SYSMGR_PINMUX_GPLMUX9_s
19194{
19195 uint32_t sel : 1; /* GPIO/Loan IO9Input Mux Selection Field */
19196 uint32_t : 31; /* *UNDEFINED* */
19197};
19198
19199/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX9. */
19200typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX9_s ALT_SYSMGR_PINMUX_GPLMUX9_t;
19201#endif /* __ASSEMBLY__ */
19202
19203/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX9 register from the beginning of the component. */
19204#define ALT_SYSMGR_PINMUX_GPLMUX9_OFST 0x1f8
19205
19206/*
19207 * Register : GPIO/LoanIO 10 Output/Output Enable Mux Selection Register - GPLMUX10
19208 *
19209 * Selection between GPIO and LoanIO output and output enable for GPIO10 and
19210 * LoanIO10. These signals drive the Pin Mux. The Pin Mux must be configured to use
19211 * GPIO/LoanIO in addition to these settings
19212 *
19213 * Only reset by a cold reset (ignores warm reset).
19214 *
19215 * NOTE: These registers should not be modified after IO configuration.There is no
19216 * support for dynamically changing the Pin Mux selections.
19217 *
19218 * Register Layout
19219 *
19220 * Bits | Access | Reset | Description
19221 * :-------|:-------|:------|:----------------------------------------
19222 * [0] | RW | 0x0 | GPIO/Loan IO10Input Mux Selection Field
19223 * [31:1] | ??? | 0x0 | *UNDEFINED*
19224 *
19225 */
19226/*
19227 * Field : GPIO/Loan IO10Input Mux Selection Field - sel
19228 *
19229 * Select source for GPIO/LoanIO 10.
19230 *
19231 * 0 : LoanIO 10 controls GPIO/LOANIO[10] output and output enable signals.
19232 *
19233 * 1 : GPIO 10 controls GPIO/LOANI[10] output and output enable signals.
19234 *
19235 * Field Access Macros:
19236 *
19237 */
19238/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */
19239#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_LSB 0
19240/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */
19241#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_MSB 0
19242/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */
19243#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_WIDTH 1
19244/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value. */
19245#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET_MSK 0x00000001
19246/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value. */
19247#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_CLR_MSK 0xfffffffe
19248/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */
19249#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_RESET 0x0
19250/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX10_SEL field value from a register. */
19251#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_GET(value) (((value) & 0x00000001) >> 0)
19252/* Produces a ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value suitable for setting the register. */
19253#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET(value) (((value) << 0) & 0x00000001)
19254
19255#ifndef __ASSEMBLY__
19256/*
19257 * WARNING: The C register and register group struct declarations are provided for
19258 * convenience and illustrative purposes. They should, however, be used with
19259 * caution as the C language standard provides no guarantees about the alignment or
19260 * atomicity of device memory accesses. The recommended practice for writing
19261 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19262 * alt_write_word() functions.
19263 *
19264 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX10.
19265 */
19266 struct ALT_SYSMGR_PINMUX_GPLMUX10_s
19267{
19268 uint32_t sel : 1; /* GPIO/Loan IO10Input Mux Selection Field */
19269 uint32_t : 31; /* *UNDEFINED* */
19270};
19271
19272/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX10. */
19273typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX10_s ALT_SYSMGR_PINMUX_GPLMUX10_t;
19274#endif /* __ASSEMBLY__ */
19275
19276/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX10 register from the beginning of the component. */
19277#define ALT_SYSMGR_PINMUX_GPLMUX10_OFST 0x1fc
19278
19279/*
19280 * Register : GPIO/LoanIO 11 Output/Output Enable Mux Selection Register - GPLMUX11
19281 *
19282 * Selection between GPIO and LoanIO output and output enable for GPIO11 and
19283 * LoanIO11. These signals drive the Pin Mux. The Pin Mux must be configured to use
19284 * GPIO/LoanIO in addition to these settings
19285 *
19286 * Only reset by a cold reset (ignores warm reset).
19287 *
19288 * NOTE: These registers should not be modified after IO configuration.There is no
19289 * support for dynamically changing the Pin Mux selections.
19290 *
19291 * Register Layout
19292 *
19293 * Bits | Access | Reset | Description
19294 * :-------|:-------|:------|:----------------------------------------
19295 * [0] | RW | 0x0 | GPIO/Loan IO11Input Mux Selection Field
19296 * [31:1] | ??? | 0x0 | *UNDEFINED*
19297 *
19298 */
19299/*
19300 * Field : GPIO/Loan IO11Input Mux Selection Field - sel
19301 *
19302 * Select source for GPIO/LoanIO 11.
19303 *
19304 * 0 : LoanIO 11 controls GPIO/LOANIO[11] output and output enable signals.
19305 *
19306 * 1 : GPIO 11 controls GPIO/LOANI[11] output and output enable signals.
19307 *
19308 * Field Access Macros:
19309 *
19310 */
19311/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */
19312#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_LSB 0
19313/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */
19314#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_MSB 0
19315/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */
19316#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_WIDTH 1
19317/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value. */
19318#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET_MSK 0x00000001
19319/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value. */
19320#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_CLR_MSK 0xfffffffe
19321/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */
19322#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_RESET 0x0
19323/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX11_SEL field value from a register. */
19324#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_GET(value) (((value) & 0x00000001) >> 0)
19325/* Produces a ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value suitable for setting the register. */
19326#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET(value) (((value) << 0) & 0x00000001)
19327
19328#ifndef __ASSEMBLY__
19329/*
19330 * WARNING: The C register and register group struct declarations are provided for
19331 * convenience and illustrative purposes. They should, however, be used with
19332 * caution as the C language standard provides no guarantees about the alignment or
19333 * atomicity of device memory accesses. The recommended practice for writing
19334 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19335 * alt_write_word() functions.
19336 *
19337 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX11.
19338 */
19339 struct ALT_SYSMGR_PINMUX_GPLMUX11_s
19340{
19341 uint32_t sel : 1; /* GPIO/Loan IO11Input Mux Selection Field */
19342 uint32_t : 31; /* *UNDEFINED* */
19343};
19344
19345/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX11. */
19346typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX11_s ALT_SYSMGR_PINMUX_GPLMUX11_t;
19347#endif /* __ASSEMBLY__ */
19348
19349/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX11 register from the beginning of the component. */
19350#define ALT_SYSMGR_PINMUX_GPLMUX11_OFST 0x200
19351
19352/*
19353 * Register : GPIO/LoanIO 12 Output/Output Enable Mux Selection Register - GPLMUX12
19354 *
19355 * Selection between GPIO and LoanIO output and output enable for GPIO12 and
19356 * LoanIO12. These signals drive the Pin Mux. The Pin Mux must be configured to use
19357 * GPIO/LoanIO in addition to these settings
19358 *
19359 * Only reset by a cold reset (ignores warm reset).
19360 *
19361 * NOTE: These registers should not be modified after IO configuration.There is no
19362 * support for dynamically changing the Pin Mux selections.
19363 *
19364 * Register Layout
19365 *
19366 * Bits | Access | Reset | Description
19367 * :-------|:-------|:------|:----------------------------------------
19368 * [0] | RW | 0x0 | GPIO/Loan IO12Input Mux Selection Field
19369 * [31:1] | ??? | 0x0 | *UNDEFINED*
19370 *
19371 */
19372/*
19373 * Field : GPIO/Loan IO12Input Mux Selection Field - sel
19374 *
19375 * Select source for GPIO/LoanIO 12.
19376 *
19377 * 0 : LoanIO 12 controls GPIO/LOANIO[12] output and output enable signals.
19378 *
19379 * 1 : GPIO 12 controls GPIO/LOANI[12] output and output enable signals.
19380 *
19381 * Field Access Macros:
19382 *
19383 */
19384/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */
19385#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_LSB 0
19386/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */
19387#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_MSB 0
19388/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */
19389#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_WIDTH 1
19390/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value. */
19391#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET_MSK 0x00000001
19392/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value. */
19393#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_CLR_MSK 0xfffffffe
19394/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */
19395#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_RESET 0x0
19396/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX12_SEL field value from a register. */
19397#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_GET(value) (((value) & 0x00000001) >> 0)
19398/* Produces a ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value suitable for setting the register. */
19399#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET(value) (((value) << 0) & 0x00000001)
19400
19401#ifndef __ASSEMBLY__
19402/*
19403 * WARNING: The C register and register group struct declarations are provided for
19404 * convenience and illustrative purposes. They should, however, be used with
19405 * caution as the C language standard provides no guarantees about the alignment or
19406 * atomicity of device memory accesses. The recommended practice for writing
19407 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19408 * alt_write_word() functions.
19409 *
19410 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX12.
19411 */
19412 struct ALT_SYSMGR_PINMUX_GPLMUX12_s
19413{
19414 uint32_t sel : 1; /* GPIO/Loan IO12Input Mux Selection Field */
19415 uint32_t : 31; /* *UNDEFINED* */
19416};
19417
19418/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX12. */
19419typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX12_s ALT_SYSMGR_PINMUX_GPLMUX12_t;
19420#endif /* __ASSEMBLY__ */
19421
19422/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX12 register from the beginning of the component. */
19423#define ALT_SYSMGR_PINMUX_GPLMUX12_OFST 0x204
19424
19425/*
19426 * Register : GPIO/LoanIO 13 Output/Output Enable Mux Selection Register - GPLMUX13
19427 *
19428 * Selection between GPIO and LoanIO output and output enable for GPIO13 and
19429 * LoanIO13. These signals drive the Pin Mux. The Pin Mux must be configured to use
19430 * GPIO/LoanIO in addition to these settings
19431 *
19432 * Only reset by a cold reset (ignores warm reset).
19433 *
19434 * NOTE: These registers should not be modified after IO configuration.There is no
19435 * support for dynamically changing the Pin Mux selections.
19436 *
19437 * Register Layout
19438 *
19439 * Bits | Access | Reset | Description
19440 * :-------|:-------|:------|:----------------------------------------
19441 * [0] | RW | 0x0 | GPIO/Loan IO13Input Mux Selection Field
19442 * [31:1] | ??? | 0x0 | *UNDEFINED*
19443 *
19444 */
19445/*
19446 * Field : GPIO/Loan IO13Input Mux Selection Field - sel
19447 *
19448 * Select source for GPIO/LoanIO 13.
19449 *
19450 * 0 : LoanIO 13 controls GPIO/LOANIO[13] output and output enable signals.
19451 *
19452 * 1 : GPIO 13 controls GPIO/LOANI[13] output and output enable signals.
19453 *
19454 * Field Access Macros:
19455 *
19456 */
19457/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */
19458#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_LSB 0
19459/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */
19460#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_MSB 0
19461/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */
19462#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_WIDTH 1
19463/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value. */
19464#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET_MSK 0x00000001
19465/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value. */
19466#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_CLR_MSK 0xfffffffe
19467/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */
19468#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_RESET 0x0
19469/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX13_SEL field value from a register. */
19470#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_GET(value) (((value) & 0x00000001) >> 0)
19471/* Produces a ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value suitable for setting the register. */
19472#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET(value) (((value) << 0) & 0x00000001)
19473
19474#ifndef __ASSEMBLY__
19475/*
19476 * WARNING: The C register and register group struct declarations are provided for
19477 * convenience and illustrative purposes. They should, however, be used with
19478 * caution as the C language standard provides no guarantees about the alignment or
19479 * atomicity of device memory accesses. The recommended practice for writing
19480 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19481 * alt_write_word() functions.
19482 *
19483 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX13.
19484 */
19485 struct ALT_SYSMGR_PINMUX_GPLMUX13_s
19486{
19487 uint32_t sel : 1; /* GPIO/Loan IO13Input Mux Selection Field */
19488 uint32_t : 31; /* *UNDEFINED* */
19489};
19490
19491/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX13. */
19492typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX13_s ALT_SYSMGR_PINMUX_GPLMUX13_t;
19493#endif /* __ASSEMBLY__ */
19494
19495/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX13 register from the beginning of the component. */
19496#define ALT_SYSMGR_PINMUX_GPLMUX13_OFST 0x208
19497
19498/*
19499 * Register : GPIO/LoanIO 14 Output/Output Enable Mux Selection Register - GPLMUX14
19500 *
19501 * Selection between GPIO and LoanIO output and output enable for GPIO14 and
19502 * LoanIO14. These signals drive the Pin Mux. The Pin Mux must be configured to use
19503 * GPIO/LoanIO in addition to these settings
19504 *
19505 * Only reset by a cold reset (ignores warm reset).
19506 *
19507 * NOTE: These registers should not be modified after IO configuration.There is no
19508 * support for dynamically changing the Pin Mux selections.
19509 *
19510 * Register Layout
19511 *
19512 * Bits | Access | Reset | Description
19513 * :-------|:-------|:------|:----------------------------------------
19514 * [0] | RW | 0x0 | GPIO/Loan IO14Input Mux Selection Field
19515 * [31:1] | ??? | 0x0 | *UNDEFINED*
19516 *
19517 */
19518/*
19519 * Field : GPIO/Loan IO14Input Mux Selection Field - sel
19520 *
19521 * Select source for GPIO/LoanIO 14.
19522 *
19523 * 0 : LoanIO 14 controls GPIO/LOANIO[14] output and output enable signals.
19524 *
19525 * 1 : GPIO 14 controls GPIO/LOANI[14] output and output enable signals.
19526 *
19527 * Field Access Macros:
19528 *
19529 */
19530/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */
19531#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_LSB 0
19532/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */
19533#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_MSB 0
19534/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */
19535#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_WIDTH 1
19536/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value. */
19537#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET_MSK 0x00000001
19538/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value. */
19539#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_CLR_MSK 0xfffffffe
19540/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */
19541#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_RESET 0x0
19542/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX14_SEL field value from a register. */
19543#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_GET(value) (((value) & 0x00000001) >> 0)
19544/* Produces a ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value suitable for setting the register. */
19545#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET(value) (((value) << 0) & 0x00000001)
19546
19547#ifndef __ASSEMBLY__
19548/*
19549 * WARNING: The C register and register group struct declarations are provided for
19550 * convenience and illustrative purposes. They should, however, be used with
19551 * caution as the C language standard provides no guarantees about the alignment or
19552 * atomicity of device memory accesses. The recommended practice for writing
19553 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19554 * alt_write_word() functions.
19555 *
19556 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX14.
19557 */
19558 struct ALT_SYSMGR_PINMUX_GPLMUX14_s
19559{
19560 uint32_t sel : 1; /* GPIO/Loan IO14Input Mux Selection Field */
19561 uint32_t : 31; /* *UNDEFINED* */
19562};
19563
19564/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX14. */
19565typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX14_s ALT_SYSMGR_PINMUX_GPLMUX14_t;
19566#endif /* __ASSEMBLY__ */
19567
19568/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX14 register from the beginning of the component. */
19569#define ALT_SYSMGR_PINMUX_GPLMUX14_OFST 0x20c
19570
19571/*
19572 * Register : GPIO/LoanIO 15 Output/Output Enable Mux Selection Register - GPLMUX15
19573 *
19574 * Selection between GPIO and LoanIO output and output enable for GPIO15 and
19575 * LoanIO15. These signals drive the Pin Mux. The Pin Mux must be configured to use
19576 * GPIO/LoanIO in addition to these settings
19577 *
19578 * Only reset by a cold reset (ignores warm reset).
19579 *
19580 * NOTE: These registers should not be modified after IO configuration.There is no
19581 * support for dynamically changing the Pin Mux selections.
19582 *
19583 * Register Layout
19584 *
19585 * Bits | Access | Reset | Description
19586 * :-------|:-------|:------|:----------------------------------------
19587 * [0] | RW | 0x0 | GPIO/Loan IO15Input Mux Selection Field
19588 * [31:1] | ??? | 0x0 | *UNDEFINED*
19589 *
19590 */
19591/*
19592 * Field : GPIO/Loan IO15Input Mux Selection Field - sel
19593 *
19594 * Select source for GPIO/LoanIO 15.
19595 *
19596 * 0 : LoanIO 15 controls GPIO/LOANIO[15] output and output enable signals.
19597 *
19598 * 1 : GPIO 15 controls GPIO/LOANI[15] output and output enable signals.
19599 *
19600 * Field Access Macros:
19601 *
19602 */
19603/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */
19604#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_LSB 0
19605/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */
19606#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_MSB 0
19607/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */
19608#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_WIDTH 1
19609/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value. */
19610#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET_MSK 0x00000001
19611/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value. */
19612#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_CLR_MSK 0xfffffffe
19613/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */
19614#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_RESET 0x0
19615/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX15_SEL field value from a register. */
19616#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_GET(value) (((value) & 0x00000001) >> 0)
19617/* Produces a ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value suitable for setting the register. */
19618#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET(value) (((value) << 0) & 0x00000001)
19619
19620#ifndef __ASSEMBLY__
19621/*
19622 * WARNING: The C register and register group struct declarations are provided for
19623 * convenience and illustrative purposes. They should, however, be used with
19624 * caution as the C language standard provides no guarantees about the alignment or
19625 * atomicity of device memory accesses. The recommended practice for writing
19626 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19627 * alt_write_word() functions.
19628 *
19629 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX15.
19630 */
19631 struct ALT_SYSMGR_PINMUX_GPLMUX15_s
19632{
19633 uint32_t sel : 1; /* GPIO/Loan IO15Input Mux Selection Field */
19634 uint32_t : 31; /* *UNDEFINED* */
19635};
19636
19637/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX15. */
19638typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX15_s ALT_SYSMGR_PINMUX_GPLMUX15_t;
19639#endif /* __ASSEMBLY__ */
19640
19641/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX15 register from the beginning of the component. */
19642#define ALT_SYSMGR_PINMUX_GPLMUX15_OFST 0x210
19643
19644/*
19645 * Register : GPIO/LoanIO 16 Output/Output Enable Mux Selection Register - GPLMUX16
19646 *
19647 * Selection between GPIO and LoanIO output and output enable for GPIO16 and
19648 * LoanIO16. These signals drive the Pin Mux. The Pin Mux must be configured to use
19649 * GPIO/LoanIO in addition to these settings
19650 *
19651 * Only reset by a cold reset (ignores warm reset).
19652 *
19653 * NOTE: These registers should not be modified after IO configuration.There is no
19654 * support for dynamically changing the Pin Mux selections.
19655 *
19656 * Register Layout
19657 *
19658 * Bits | Access | Reset | Description
19659 * :-------|:-------|:------|:----------------------------------------
19660 * [0] | RW | 0x0 | GPIO/Loan IO16Input Mux Selection Field
19661 * [31:1] | ??? | 0x0 | *UNDEFINED*
19662 *
19663 */
19664/*
19665 * Field : GPIO/Loan IO16Input Mux Selection Field - sel
19666 *
19667 * Select source for GPIO/LoanIO 16.
19668 *
19669 * 0 : LoanIO 16 controls GPIO/LOANIO[16] output and output enable signals.
19670 *
19671 * 1 : GPIO 16 controls GPIO/LOANI[16] output and output enable signals.
19672 *
19673 * Field Access Macros:
19674 *
19675 */
19676/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */
19677#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_LSB 0
19678/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */
19679#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_MSB 0
19680/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */
19681#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_WIDTH 1
19682/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value. */
19683#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET_MSK 0x00000001
19684/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value. */
19685#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_CLR_MSK 0xfffffffe
19686/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */
19687#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_RESET 0x0
19688/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX16_SEL field value from a register. */
19689#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_GET(value) (((value) & 0x00000001) >> 0)
19690/* Produces a ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value suitable for setting the register. */
19691#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET(value) (((value) << 0) & 0x00000001)
19692
19693#ifndef __ASSEMBLY__
19694/*
19695 * WARNING: The C register and register group struct declarations are provided for
19696 * convenience and illustrative purposes. They should, however, be used with
19697 * caution as the C language standard provides no guarantees about the alignment or
19698 * atomicity of device memory accesses. The recommended practice for writing
19699 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19700 * alt_write_word() functions.
19701 *
19702 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX16.
19703 */
19704 struct ALT_SYSMGR_PINMUX_GPLMUX16_s
19705{
19706 uint32_t sel : 1; /* GPIO/Loan IO16Input Mux Selection Field */
19707 uint32_t : 31; /* *UNDEFINED* */
19708};
19709
19710/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX16. */
19711typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX16_s ALT_SYSMGR_PINMUX_GPLMUX16_t;
19712#endif /* __ASSEMBLY__ */
19713
19714/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX16 register from the beginning of the component. */
19715#define ALT_SYSMGR_PINMUX_GPLMUX16_OFST 0x214
19716
19717/*
19718 * Register : GPIO/LoanIO 17 Output/Output Enable Mux Selection Register - GPLMUX17
19719 *
19720 * Selection between GPIO and LoanIO output and output enable for GPIO17 and
19721 * LoanIO17. These signals drive the Pin Mux. The Pin Mux must be configured to use
19722 * GPIO/LoanIO in addition to these settings
19723 *
19724 * Only reset by a cold reset (ignores warm reset).
19725 *
19726 * NOTE: These registers should not be modified after IO configuration.There is no
19727 * support for dynamically changing the Pin Mux selections.
19728 *
19729 * Register Layout
19730 *
19731 * Bits | Access | Reset | Description
19732 * :-------|:-------|:------|:----------------------------------------
19733 * [0] | RW | 0x0 | GPIO/Loan IO17Input Mux Selection Field
19734 * [31:1] | ??? | 0x0 | *UNDEFINED*
19735 *
19736 */
19737/*
19738 * Field : GPIO/Loan IO17Input Mux Selection Field - sel
19739 *
19740 * Select source for GPIO/LoanIO 17.
19741 *
19742 * 0 : LoanIO 17 controls GPIO/LOANIO[17] output and output enable signals.
19743 *
19744 * 1 : GPIO 17 controls GPIO/LOANI[17] output and output enable signals.
19745 *
19746 * Field Access Macros:
19747 *
19748 */
19749/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */
19750#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_LSB 0
19751/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */
19752#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_MSB 0
19753/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */
19754#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_WIDTH 1
19755/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value. */
19756#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET_MSK 0x00000001
19757/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value. */
19758#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_CLR_MSK 0xfffffffe
19759/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */
19760#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_RESET 0x0
19761/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX17_SEL field value from a register. */
19762#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_GET(value) (((value) & 0x00000001) >> 0)
19763/* Produces a ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value suitable for setting the register. */
19764#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET(value) (((value) << 0) & 0x00000001)
19765
19766#ifndef __ASSEMBLY__
19767/*
19768 * WARNING: The C register and register group struct declarations are provided for
19769 * convenience and illustrative purposes. They should, however, be used with
19770 * caution as the C language standard provides no guarantees about the alignment or
19771 * atomicity of device memory accesses. The recommended practice for writing
19772 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19773 * alt_write_word() functions.
19774 *
19775 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX17.
19776 */
19777 struct ALT_SYSMGR_PINMUX_GPLMUX17_s
19778{
19779 uint32_t sel : 1; /* GPIO/Loan IO17Input Mux Selection Field */
19780 uint32_t : 31; /* *UNDEFINED* */
19781};
19782
19783/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX17. */
19784typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX17_s ALT_SYSMGR_PINMUX_GPLMUX17_t;
19785#endif /* __ASSEMBLY__ */
19786
19787/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX17 register from the beginning of the component. */
19788#define ALT_SYSMGR_PINMUX_GPLMUX17_OFST 0x218
19789
19790/*
19791 * Register : GPIO/LoanIO 18 Output/Output Enable Mux Selection Register - GPLMUX18
19792 *
19793 * Selection between GPIO and LoanIO output and output enable for GPIO18 and
19794 * LoanIO18. These signals drive the Pin Mux. The Pin Mux must be configured to use
19795 * GPIO/LoanIO in addition to these settings
19796 *
19797 * Only reset by a cold reset (ignores warm reset).
19798 *
19799 * NOTE: These registers should not be modified after IO configuration.There is no
19800 * support for dynamically changing the Pin Mux selections.
19801 *
19802 * Register Layout
19803 *
19804 * Bits | Access | Reset | Description
19805 * :-------|:-------|:------|:----------------------------------------
19806 * [0] | RW | 0x0 | GPIO/Loan IO18Input Mux Selection Field
19807 * [31:1] | ??? | 0x0 | *UNDEFINED*
19808 *
19809 */
19810/*
19811 * Field : GPIO/Loan IO18Input Mux Selection Field - sel
19812 *
19813 * Select source for GPIO/LoanIO 18.
19814 *
19815 * 0 : LoanIO 18 controls GPIO/LOANIO[18] output and output enable signals.
19816 *
19817 * 1 : GPIO 18 controls GPIO/LOANI[18] output and output enable signals.
19818 *
19819 * Field Access Macros:
19820 *
19821 */
19822/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */
19823#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_LSB 0
19824/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */
19825#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_MSB 0
19826/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */
19827#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_WIDTH 1
19828/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value. */
19829#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET_MSK 0x00000001
19830/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value. */
19831#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_CLR_MSK 0xfffffffe
19832/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */
19833#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_RESET 0x0
19834/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX18_SEL field value from a register. */
19835#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_GET(value) (((value) & 0x00000001) >> 0)
19836/* Produces a ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value suitable for setting the register. */
19837#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET(value) (((value) << 0) & 0x00000001)
19838
19839#ifndef __ASSEMBLY__
19840/*
19841 * WARNING: The C register and register group struct declarations are provided for
19842 * convenience and illustrative purposes. They should, however, be used with
19843 * caution as the C language standard provides no guarantees about the alignment or
19844 * atomicity of device memory accesses. The recommended practice for writing
19845 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19846 * alt_write_word() functions.
19847 *
19848 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX18.
19849 */
19850 struct ALT_SYSMGR_PINMUX_GPLMUX18_s
19851{
19852 uint32_t sel : 1; /* GPIO/Loan IO18Input Mux Selection Field */
19853 uint32_t : 31; /* *UNDEFINED* */
19854};
19855
19856/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX18. */
19857typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX18_s ALT_SYSMGR_PINMUX_GPLMUX18_t;
19858#endif /* __ASSEMBLY__ */
19859
19860/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX18 register from the beginning of the component. */
19861#define ALT_SYSMGR_PINMUX_GPLMUX18_OFST 0x21c
19862
19863/*
19864 * Register : GPIO/LoanIO 19 Output/Output Enable Mux Selection Register - GPLMUX19
19865 *
19866 * Selection between GPIO and LoanIO output and output enable for GPIO19 and
19867 * LoanIO19. These signals drive the Pin Mux. The Pin Mux must be configured to use
19868 * GPIO/LoanIO in addition to these settings
19869 *
19870 * Only reset by a cold reset (ignores warm reset).
19871 *
19872 * NOTE: These registers should not be modified after IO configuration.There is no
19873 * support for dynamically changing the Pin Mux selections.
19874 *
19875 * Register Layout
19876 *
19877 * Bits | Access | Reset | Description
19878 * :-------|:-------|:------|:----------------------------------------
19879 * [0] | RW | 0x0 | GPIO/Loan IO19Input Mux Selection Field
19880 * [31:1] | ??? | 0x0 | *UNDEFINED*
19881 *
19882 */
19883/*
19884 * Field : GPIO/Loan IO19Input Mux Selection Field - sel
19885 *
19886 * Select source for GPIO/LoanIO 19.
19887 *
19888 * 0 : LoanIO 19 controls GPIO/LOANIO[19] output and output enable signals.
19889 *
19890 * 1 : GPIO 19 controls GPIO/LOANI[19] output and output enable signals.
19891 *
19892 * Field Access Macros:
19893 *
19894 */
19895/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */
19896#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_LSB 0
19897/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */
19898#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_MSB 0
19899/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */
19900#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_WIDTH 1
19901/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value. */
19902#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET_MSK 0x00000001
19903/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value. */
19904#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_CLR_MSK 0xfffffffe
19905/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */
19906#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_RESET 0x0
19907/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX19_SEL field value from a register. */
19908#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_GET(value) (((value) & 0x00000001) >> 0)
19909/* Produces a ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value suitable for setting the register. */
19910#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET(value) (((value) << 0) & 0x00000001)
19911
19912#ifndef __ASSEMBLY__
19913/*
19914 * WARNING: The C register and register group struct declarations are provided for
19915 * convenience and illustrative purposes. They should, however, be used with
19916 * caution as the C language standard provides no guarantees about the alignment or
19917 * atomicity of device memory accesses. The recommended practice for writing
19918 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19919 * alt_write_word() functions.
19920 *
19921 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX19.
19922 */
19923 struct ALT_SYSMGR_PINMUX_GPLMUX19_s
19924{
19925 uint32_t sel : 1; /* GPIO/Loan IO19Input Mux Selection Field */
19926 uint32_t : 31; /* *UNDEFINED* */
19927};
19928
19929/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX19. */
19930typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX19_s ALT_SYSMGR_PINMUX_GPLMUX19_t;
19931#endif /* __ASSEMBLY__ */
19932
19933/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX19 register from the beginning of the component. */
19934#define ALT_SYSMGR_PINMUX_GPLMUX19_OFST 0x220
19935
19936/*
19937 * Register : GPIO/LoanIO 20 Output/Output Enable Mux Selection Register - GPLMUX20
19938 *
19939 * Selection between GPIO and LoanIO output and output enable for GPIO20 and
19940 * LoanIO20. These signals drive the Pin Mux. The Pin Mux must be configured to use
19941 * GPIO/LoanIO in addition to these settings
19942 *
19943 * Only reset by a cold reset (ignores warm reset).
19944 *
19945 * NOTE: These registers should not be modified after IO configuration.There is no
19946 * support for dynamically changing the Pin Mux selections.
19947 *
19948 * Register Layout
19949 *
19950 * Bits | Access | Reset | Description
19951 * :-------|:-------|:------|:----------------------------------------
19952 * [0] | RW | 0x0 | GPIO/Loan IO20Input Mux Selection Field
19953 * [31:1] | ??? | 0x0 | *UNDEFINED*
19954 *
19955 */
19956/*
19957 * Field : GPIO/Loan IO20Input Mux Selection Field - sel
19958 *
19959 * Select source for GPIO/LoanIO 20.
19960 *
19961 * 0 : LoanIO 20 controls GPIO/LOANIO[20] output and output enable signals.
19962 *
19963 * 1 : GPIO 20 controls GPIO/LOANI[20] output and output enable signals.
19964 *
19965 * Field Access Macros:
19966 *
19967 */
19968/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */
19969#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_LSB 0
19970/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */
19971#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_MSB 0
19972/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */
19973#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_WIDTH 1
19974/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value. */
19975#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET_MSK 0x00000001
19976/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value. */
19977#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_CLR_MSK 0xfffffffe
19978/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */
19979#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_RESET 0x0
19980/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX20_SEL field value from a register. */
19981#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_GET(value) (((value) & 0x00000001) >> 0)
19982/* Produces a ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value suitable for setting the register. */
19983#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET(value) (((value) << 0) & 0x00000001)
19984
19985#ifndef __ASSEMBLY__
19986/*
19987 * WARNING: The C register and register group struct declarations are provided for
19988 * convenience and illustrative purposes. They should, however, be used with
19989 * caution as the C language standard provides no guarantees about the alignment or
19990 * atomicity of device memory accesses. The recommended practice for writing
19991 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19992 * alt_write_word() functions.
19993 *
19994 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX20.
19995 */
19996 struct ALT_SYSMGR_PINMUX_GPLMUX20_s
19997{
19998 uint32_t sel : 1; /* GPIO/Loan IO20Input Mux Selection Field */
19999 uint32_t : 31; /* *UNDEFINED* */
20000};
20001
20002/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX20. */
20003typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX20_s ALT_SYSMGR_PINMUX_GPLMUX20_t;
20004#endif /* __ASSEMBLY__ */
20005
20006/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX20 register from the beginning of the component. */
20007#define ALT_SYSMGR_PINMUX_GPLMUX20_OFST 0x224
20008
20009/*
20010 * Register : GPIO/LoanIO 21 Output/Output Enable Mux Selection Register - GPLMUX21
20011 *
20012 * Selection between GPIO and LoanIO output and output enable for GPIO21 and
20013 * LoanIO21. These signals drive the Pin Mux. The Pin Mux must be configured to use
20014 * GPIO/LoanIO in addition to these settings
20015 *
20016 * Only reset by a cold reset (ignores warm reset).
20017 *
20018 * NOTE: These registers should not be modified after IO configuration.There is no
20019 * support for dynamically changing the Pin Mux selections.
20020 *
20021 * Register Layout
20022 *
20023 * Bits | Access | Reset | Description
20024 * :-------|:-------|:------|:----------------------------------------
20025 * [0] | RW | 0x0 | GPIO/Loan IO21Input Mux Selection Field
20026 * [31:1] | ??? | 0x0 | *UNDEFINED*
20027 *
20028 */
20029/*
20030 * Field : GPIO/Loan IO21Input Mux Selection Field - sel
20031 *
20032 * Select source for GPIO/LoanIO 21.
20033 *
20034 * 0 : LoanIO 21 controls GPIO/LOANIO[21] output and output enable signals.
20035 *
20036 * 1 : GPIO 21 controls GPIO/LOANI[21] output and output enable signals.
20037 *
20038 * Field Access Macros:
20039 *
20040 */
20041/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */
20042#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_LSB 0
20043/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */
20044#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_MSB 0
20045/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */
20046#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_WIDTH 1
20047/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value. */
20048#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET_MSK 0x00000001
20049/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value. */
20050#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_CLR_MSK 0xfffffffe
20051/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */
20052#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_RESET 0x0
20053/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX21_SEL field value from a register. */
20054#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_GET(value) (((value) & 0x00000001) >> 0)
20055/* Produces a ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value suitable for setting the register. */
20056#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET(value) (((value) << 0) & 0x00000001)
20057
20058#ifndef __ASSEMBLY__
20059/*
20060 * WARNING: The C register and register group struct declarations are provided for
20061 * convenience and illustrative purposes. They should, however, be used with
20062 * caution as the C language standard provides no guarantees about the alignment or
20063 * atomicity of device memory accesses. The recommended practice for writing
20064 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20065 * alt_write_word() functions.
20066 *
20067 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX21.
20068 */
20069 struct ALT_SYSMGR_PINMUX_GPLMUX21_s
20070{
20071 uint32_t sel : 1; /* GPIO/Loan IO21Input Mux Selection Field */
20072 uint32_t : 31; /* *UNDEFINED* */
20073};
20074
20075/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX21. */
20076typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX21_s ALT_SYSMGR_PINMUX_GPLMUX21_t;
20077#endif /* __ASSEMBLY__ */
20078
20079/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX21 register from the beginning of the component. */
20080#define ALT_SYSMGR_PINMUX_GPLMUX21_OFST 0x228
20081
20082/*
20083 * Register : GPIO/LoanIO 22 Output/Output Enable Mux Selection Register - GPLMUX22
20084 *
20085 * Selection between GPIO and LoanIO output and output enable for GPIO22 and
20086 * LoanIO22. These signals drive the Pin Mux. The Pin Mux must be configured to use
20087 * GPIO/LoanIO in addition to these settings
20088 *
20089 * Only reset by a cold reset (ignores warm reset).
20090 *
20091 * NOTE: These registers should not be modified after IO configuration.There is no
20092 * support for dynamically changing the Pin Mux selections.
20093 *
20094 * Register Layout
20095 *
20096 * Bits | Access | Reset | Description
20097 * :-------|:-------|:------|:----------------------------------------
20098 * [0] | RW | 0x0 | GPIO/Loan IO22Input Mux Selection Field
20099 * [31:1] | ??? | 0x0 | *UNDEFINED*
20100 *
20101 */
20102/*
20103 * Field : GPIO/Loan IO22Input Mux Selection Field - sel
20104 *
20105 * Select source for GPIO/LoanIO 22.
20106 *
20107 * 0 : LoanIO 22 controls GPIO/LOANIO[22] output and output enable signals.
20108 *
20109 * 1 : GPIO 22 controls GPIO/LOANI[22] output and output enable signals.
20110 *
20111 * Field Access Macros:
20112 *
20113 */
20114/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */
20115#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_LSB 0
20116/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */
20117#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_MSB 0
20118/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */
20119#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_WIDTH 1
20120/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value. */
20121#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET_MSK 0x00000001
20122/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value. */
20123#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_CLR_MSK 0xfffffffe
20124/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */
20125#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_RESET 0x0
20126/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX22_SEL field value from a register. */
20127#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_GET(value) (((value) & 0x00000001) >> 0)
20128/* Produces a ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value suitable for setting the register. */
20129#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET(value) (((value) << 0) & 0x00000001)
20130
20131#ifndef __ASSEMBLY__
20132/*
20133 * WARNING: The C register and register group struct declarations are provided for
20134 * convenience and illustrative purposes. They should, however, be used with
20135 * caution as the C language standard provides no guarantees about the alignment or
20136 * atomicity of device memory accesses. The recommended practice for writing
20137 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20138 * alt_write_word() functions.
20139 *
20140 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX22.
20141 */
20142 struct ALT_SYSMGR_PINMUX_GPLMUX22_s
20143{
20144 uint32_t sel : 1; /* GPIO/Loan IO22Input Mux Selection Field */
20145 uint32_t : 31; /* *UNDEFINED* */
20146};
20147
20148/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX22. */
20149typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX22_s ALT_SYSMGR_PINMUX_GPLMUX22_t;
20150#endif /* __ASSEMBLY__ */
20151
20152/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX22 register from the beginning of the component. */
20153#define ALT_SYSMGR_PINMUX_GPLMUX22_OFST 0x22c
20154
20155/*
20156 * Register : GPIO/LoanIO 23 Output/Output Enable Mux Selection Register - GPLMUX23
20157 *
20158 * Selection between GPIO and LoanIO output and output enable for GPIO23 and
20159 * LoanIO23. These signals drive the Pin Mux. The Pin Mux must be configured to use
20160 * GPIO/LoanIO in addition to these settings
20161 *
20162 * Only reset by a cold reset (ignores warm reset).
20163 *
20164 * NOTE: These registers should not be modified after IO configuration.There is no
20165 * support for dynamically changing the Pin Mux selections.
20166 *
20167 * Register Layout
20168 *
20169 * Bits | Access | Reset | Description
20170 * :-------|:-------|:------|:----------------------------------------
20171 * [0] | RW | 0x0 | GPIO/Loan IO23Input Mux Selection Field
20172 * [31:1] | ??? | 0x0 | *UNDEFINED*
20173 *
20174 */
20175/*
20176 * Field : GPIO/Loan IO23Input Mux Selection Field - sel
20177 *
20178 * Select source for GPIO/LoanIO 23.
20179 *
20180 * 0 : LoanIO 23 controls GPIO/LOANIO[23] output and output enable signals.
20181 *
20182 * 1 : GPIO 23 controls GPIO/LOANI[23] output and output enable signals.
20183 *
20184 * Field Access Macros:
20185 *
20186 */
20187/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */
20188#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_LSB 0
20189/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */
20190#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_MSB 0
20191/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */
20192#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_WIDTH 1
20193/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value. */
20194#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET_MSK 0x00000001
20195/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value. */
20196#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_CLR_MSK 0xfffffffe
20197/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */
20198#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_RESET 0x0
20199/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX23_SEL field value from a register. */
20200#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_GET(value) (((value) & 0x00000001) >> 0)
20201/* Produces a ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value suitable for setting the register. */
20202#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET(value) (((value) << 0) & 0x00000001)
20203
20204#ifndef __ASSEMBLY__
20205/*
20206 * WARNING: The C register and register group struct declarations are provided for
20207 * convenience and illustrative purposes. They should, however, be used with
20208 * caution as the C language standard provides no guarantees about the alignment or
20209 * atomicity of device memory accesses. The recommended practice for writing
20210 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20211 * alt_write_word() functions.
20212 *
20213 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX23.
20214 */
20215 struct ALT_SYSMGR_PINMUX_GPLMUX23_s
20216{
20217 uint32_t sel : 1; /* GPIO/Loan IO23Input Mux Selection Field */
20218 uint32_t : 31; /* *UNDEFINED* */
20219};
20220
20221/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX23. */
20222typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX23_s ALT_SYSMGR_PINMUX_GPLMUX23_t;
20223#endif /* __ASSEMBLY__ */
20224
20225/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX23 register from the beginning of the component. */
20226#define ALT_SYSMGR_PINMUX_GPLMUX23_OFST 0x230
20227
20228/*
20229 * Register : GPIO/LoanIO 24 Output/Output Enable Mux Selection Register - GPLMUX24
20230 *
20231 * Selection between GPIO and LoanIO output and output enable for GPIO24 and
20232 * LoanIO24. These signals drive the Pin Mux. The Pin Mux must be configured to use
20233 * GPIO/LoanIO in addition to these settings
20234 *
20235 * Only reset by a cold reset (ignores warm reset).
20236 *
20237 * NOTE: These registers should not be modified after IO configuration.There is no
20238 * support for dynamically changing the Pin Mux selections.
20239 *
20240 * Register Layout
20241 *
20242 * Bits | Access | Reset | Description
20243 * :-------|:-------|:------|:----------------------------------------
20244 * [0] | RW | 0x0 | GPIO/Loan IO24Input Mux Selection Field
20245 * [31:1] | ??? | 0x0 | *UNDEFINED*
20246 *
20247 */
20248/*
20249 * Field : GPIO/Loan IO24Input Mux Selection Field - sel
20250 *
20251 * Select source for GPIO/LoanIO 24.
20252 *
20253 * 0 : LoanIO 24 controls GPIO/LOANIO[24] output and output enable signals.
20254 *
20255 * 1 : GPIO 24 controls GPIO/LOANI[24] output and output enable signals.
20256 *
20257 * Field Access Macros:
20258 *
20259 */
20260/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */
20261#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_LSB 0
20262/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */
20263#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_MSB 0
20264/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */
20265#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_WIDTH 1
20266/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value. */
20267#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET_MSK 0x00000001
20268/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value. */
20269#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_CLR_MSK 0xfffffffe
20270/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */
20271#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_RESET 0x0
20272/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX24_SEL field value from a register. */
20273#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_GET(value) (((value) & 0x00000001) >> 0)
20274/* Produces a ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value suitable for setting the register. */
20275#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET(value) (((value) << 0) & 0x00000001)
20276
20277#ifndef __ASSEMBLY__
20278/*
20279 * WARNING: The C register and register group struct declarations are provided for
20280 * convenience and illustrative purposes. They should, however, be used with
20281 * caution as the C language standard provides no guarantees about the alignment or
20282 * atomicity of device memory accesses. The recommended practice for writing
20283 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20284 * alt_write_word() functions.
20285 *
20286 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX24.
20287 */
20288 struct ALT_SYSMGR_PINMUX_GPLMUX24_s
20289{
20290 uint32_t sel : 1; /* GPIO/Loan IO24Input Mux Selection Field */
20291 uint32_t : 31; /* *UNDEFINED* */
20292};
20293
20294/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX24. */
20295typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX24_s ALT_SYSMGR_PINMUX_GPLMUX24_t;
20296#endif /* __ASSEMBLY__ */
20297
20298/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX24 register from the beginning of the component. */
20299#define ALT_SYSMGR_PINMUX_GPLMUX24_OFST 0x234
20300
20301/*
20302 * Register : GPIO/LoanIO 25 Output/Output Enable Mux Selection Register - GPLMUX25
20303 *
20304 * Selection between GPIO and LoanIO output and output enable for GPIO25 and
20305 * LoanIO25. These signals drive the Pin Mux. The Pin Mux must be configured to use
20306 * GPIO/LoanIO in addition to these settings
20307 *
20308 * Only reset by a cold reset (ignores warm reset).
20309 *
20310 * NOTE: These registers should not be modified after IO configuration.There is no
20311 * support for dynamically changing the Pin Mux selections.
20312 *
20313 * Register Layout
20314 *
20315 * Bits | Access | Reset | Description
20316 * :-------|:-------|:------|:----------------------------------------
20317 * [0] | RW | 0x0 | GPIO/Loan IO25Input Mux Selection Field
20318 * [31:1] | ??? | 0x0 | *UNDEFINED*
20319 *
20320 */
20321/*
20322 * Field : GPIO/Loan IO25Input Mux Selection Field - sel
20323 *
20324 * Select source for GPIO/LoanIO 25.
20325 *
20326 * 0 : LoanIO 25 controls GPIO/LOANIO[25] output and output enable signals.
20327 *
20328 * 1 : GPIO 25 controls GPIO/LOANI[25] output and output enable signals.
20329 *
20330 * Field Access Macros:
20331 *
20332 */
20333/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */
20334#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_LSB 0
20335/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */
20336#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_MSB 0
20337/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */
20338#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_WIDTH 1
20339/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value. */
20340#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET_MSK 0x00000001
20341/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value. */
20342#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_CLR_MSK 0xfffffffe
20343/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */
20344#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_RESET 0x0
20345/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX25_SEL field value from a register. */
20346#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_GET(value) (((value) & 0x00000001) >> 0)
20347/* Produces a ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value suitable for setting the register. */
20348#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET(value) (((value) << 0) & 0x00000001)
20349
20350#ifndef __ASSEMBLY__
20351/*
20352 * WARNING: The C register and register group struct declarations are provided for
20353 * convenience and illustrative purposes. They should, however, be used with
20354 * caution as the C language standard provides no guarantees about the alignment or
20355 * atomicity of device memory accesses. The recommended practice for writing
20356 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20357 * alt_write_word() functions.
20358 *
20359 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX25.
20360 */
20361 struct ALT_SYSMGR_PINMUX_GPLMUX25_s
20362{
20363 uint32_t sel : 1; /* GPIO/Loan IO25Input Mux Selection Field */
20364 uint32_t : 31; /* *UNDEFINED* */
20365};
20366
20367/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX25. */
20368typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX25_s ALT_SYSMGR_PINMUX_GPLMUX25_t;
20369#endif /* __ASSEMBLY__ */
20370
20371/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX25 register from the beginning of the component. */
20372#define ALT_SYSMGR_PINMUX_GPLMUX25_OFST 0x238
20373
20374/*
20375 * Register : GPIO/LoanIO 26 Output/Output Enable Mux Selection Register - GPLMUX26
20376 *
20377 * Selection between GPIO and LoanIO output and output enable for GPIO26 and
20378 * LoanIO26. These signals drive the Pin Mux. The Pin Mux must be configured to use
20379 * GPIO/LoanIO in addition to these settings
20380 *
20381 * Only reset by a cold reset (ignores warm reset).
20382 *
20383 * NOTE: These registers should not be modified after IO configuration.There is no
20384 * support for dynamically changing the Pin Mux selections.
20385 *
20386 * Register Layout
20387 *
20388 * Bits | Access | Reset | Description
20389 * :-------|:-------|:------|:----------------------------------------
20390 * [0] | RW | 0x0 | GPIO/Loan IO26Input Mux Selection Field
20391 * [31:1] | ??? | 0x0 | *UNDEFINED*
20392 *
20393 */
20394/*
20395 * Field : GPIO/Loan IO26Input Mux Selection Field - sel
20396 *
20397 * Select source for GPIO/LoanIO 26.
20398 *
20399 * 0 : LoanIO 26 controls GPIO/LOANIO[26] output and output enable signals.
20400 *
20401 * 1 : GPIO 26 controls GPIO/LOANI[26] output and output enable signals.
20402 *
20403 * Field Access Macros:
20404 *
20405 */
20406/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */
20407#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_LSB 0
20408/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */
20409#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_MSB 0
20410/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */
20411#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_WIDTH 1
20412/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value. */
20413#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET_MSK 0x00000001
20414/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value. */
20415#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_CLR_MSK 0xfffffffe
20416/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */
20417#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_RESET 0x0
20418/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX26_SEL field value from a register. */
20419#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_GET(value) (((value) & 0x00000001) >> 0)
20420/* Produces a ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value suitable for setting the register. */
20421#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET(value) (((value) << 0) & 0x00000001)
20422
20423#ifndef __ASSEMBLY__
20424/*
20425 * WARNING: The C register and register group struct declarations are provided for
20426 * convenience and illustrative purposes. They should, however, be used with
20427 * caution as the C language standard provides no guarantees about the alignment or
20428 * atomicity of device memory accesses. The recommended practice for writing
20429 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20430 * alt_write_word() functions.
20431 *
20432 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX26.
20433 */
20434 struct ALT_SYSMGR_PINMUX_GPLMUX26_s
20435{
20436 uint32_t sel : 1; /* GPIO/Loan IO26Input Mux Selection Field */
20437 uint32_t : 31; /* *UNDEFINED* */
20438};
20439
20440/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX26. */
20441typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX26_s ALT_SYSMGR_PINMUX_GPLMUX26_t;
20442#endif /* __ASSEMBLY__ */
20443
20444/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX26 register from the beginning of the component. */
20445#define ALT_SYSMGR_PINMUX_GPLMUX26_OFST 0x23c
20446
20447/*
20448 * Register : GPIO/LoanIO 27 Output/Output Enable Mux Selection Register - GPLMUX27
20449 *
20450 * Selection between GPIO and LoanIO output and output enable for GPIO27 and
20451 * LoanIO27. These signals drive the Pin Mux. The Pin Mux must be configured to use
20452 * GPIO/LoanIO in addition to these settings
20453 *
20454 * Only reset by a cold reset (ignores warm reset).
20455 *
20456 * NOTE: These registers should not be modified after IO configuration.There is no
20457 * support for dynamically changing the Pin Mux selections.
20458 *
20459 * Register Layout
20460 *
20461 * Bits | Access | Reset | Description
20462 * :-------|:-------|:------|:----------------------------------------
20463 * [0] | RW | 0x0 | GPIO/Loan IO27Input Mux Selection Field
20464 * [31:1] | ??? | 0x0 | *UNDEFINED*
20465 *
20466 */
20467/*
20468 * Field : GPIO/Loan IO27Input Mux Selection Field - sel
20469 *
20470 * Select source for GPIO/LoanIO 27.
20471 *
20472 * 0 : LoanIO 27 controls GPIO/LOANIO[27] output and output enable signals.
20473 *
20474 * 1 : GPIO 27 controls GPIO/LOANI[27] output and output enable signals.
20475 *
20476 * Field Access Macros:
20477 *
20478 */
20479/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */
20480#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_LSB 0
20481/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */
20482#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_MSB 0
20483/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */
20484#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_WIDTH 1
20485/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value. */
20486#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET_MSK 0x00000001
20487/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value. */
20488#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_CLR_MSK 0xfffffffe
20489/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */
20490#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_RESET 0x0
20491/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX27_SEL field value from a register. */
20492#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_GET(value) (((value) & 0x00000001) >> 0)
20493/* Produces a ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value suitable for setting the register. */
20494#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET(value) (((value) << 0) & 0x00000001)
20495
20496#ifndef __ASSEMBLY__
20497/*
20498 * WARNING: The C register and register group struct declarations are provided for
20499 * convenience and illustrative purposes. They should, however, be used with
20500 * caution as the C language standard provides no guarantees about the alignment or
20501 * atomicity of device memory accesses. The recommended practice for writing
20502 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20503 * alt_write_word() functions.
20504 *
20505 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX27.
20506 */
20507 struct ALT_SYSMGR_PINMUX_GPLMUX27_s
20508{
20509 uint32_t sel : 1; /* GPIO/Loan IO27Input Mux Selection Field */
20510 uint32_t : 31; /* *UNDEFINED* */
20511};
20512
20513/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX27. */
20514typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX27_s ALT_SYSMGR_PINMUX_GPLMUX27_t;
20515#endif /* __ASSEMBLY__ */
20516
20517/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX27 register from the beginning of the component. */
20518#define ALT_SYSMGR_PINMUX_GPLMUX27_OFST 0x240
20519
20520/*
20521 * Register : GPIO/LoanIO 28 Output/Output Enable Mux Selection Register - GPLMUX28
20522 *
20523 * Selection between GPIO and LoanIO output and output enable for GPIO28 and
20524 * LoanIO28. These signals drive the Pin Mux. The Pin Mux must be configured to use
20525 * GPIO/LoanIO in addition to these settings
20526 *
20527 * Only reset by a cold reset (ignores warm reset).
20528 *
20529 * NOTE: These registers should not be modified after IO configuration.There is no
20530 * support for dynamically changing the Pin Mux selections.
20531 *
20532 * Register Layout
20533 *
20534 * Bits | Access | Reset | Description
20535 * :-------|:-------|:------|:----------------------------------------
20536 * [0] | RW | 0x0 | GPIO/Loan IO28Input Mux Selection Field
20537 * [31:1] | ??? | 0x0 | *UNDEFINED*
20538 *
20539 */
20540/*
20541 * Field : GPIO/Loan IO28Input Mux Selection Field - sel
20542 *
20543 * Select source for GPIO/LoanIO 28.
20544 *
20545 * 0 : LoanIO 28 controls GPIO/LOANIO[28] output and output enable signals.
20546 *
20547 * 1 : GPIO 28 controls GPIO/LOANI[28] output and output enable signals.
20548 *
20549 * Field Access Macros:
20550 *
20551 */
20552/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */
20553#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_LSB 0
20554/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */
20555#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_MSB 0
20556/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */
20557#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_WIDTH 1
20558/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value. */
20559#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET_MSK 0x00000001
20560/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value. */
20561#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_CLR_MSK 0xfffffffe
20562/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */
20563#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_RESET 0x0
20564/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX28_SEL field value from a register. */
20565#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_GET(value) (((value) & 0x00000001) >> 0)
20566/* Produces a ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value suitable for setting the register. */
20567#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET(value) (((value) << 0) & 0x00000001)
20568
20569#ifndef __ASSEMBLY__
20570/*
20571 * WARNING: The C register and register group struct declarations are provided for
20572 * convenience and illustrative purposes. They should, however, be used with
20573 * caution as the C language standard provides no guarantees about the alignment or
20574 * atomicity of device memory accesses. The recommended practice for writing
20575 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20576 * alt_write_word() functions.
20577 *
20578 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX28.
20579 */
20580 struct ALT_SYSMGR_PINMUX_GPLMUX28_s
20581{
20582 uint32_t sel : 1; /* GPIO/Loan IO28Input Mux Selection Field */
20583 uint32_t : 31; /* *UNDEFINED* */
20584};
20585
20586/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX28. */
20587typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX28_s ALT_SYSMGR_PINMUX_GPLMUX28_t;
20588#endif /* __ASSEMBLY__ */
20589
20590/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX28 register from the beginning of the component. */
20591#define ALT_SYSMGR_PINMUX_GPLMUX28_OFST 0x244
20592
20593/*
20594 * Register : GPIO/LoanIO 29 Output/Output Enable Mux Selection Register - GPLMUX29
20595 *
20596 * Selection between GPIO and LoanIO output and output enable for GPIO29 and
20597 * LoanIO29. These signals drive the Pin Mux. The Pin Mux must be configured to use
20598 * GPIO/LoanIO in addition to these settings
20599 *
20600 * Only reset by a cold reset (ignores warm reset).
20601 *
20602 * NOTE: These registers should not be modified after IO configuration.There is no
20603 * support for dynamically changing the Pin Mux selections.
20604 *
20605 * Register Layout
20606 *
20607 * Bits | Access | Reset | Description
20608 * :-------|:-------|:------|:----------------------------------------
20609 * [0] | RW | 0x0 | GPIO/Loan IO29Input Mux Selection Field
20610 * [31:1] | ??? | 0x0 | *UNDEFINED*
20611 *
20612 */
20613/*
20614 * Field : GPIO/Loan IO29Input Mux Selection Field - sel
20615 *
20616 * Select source for GPIO/LoanIO 29.
20617 *
20618 * 0 : LoanIO 29 controls GPIO/LOANIO[29] output and output enable signals.
20619 *
20620 * 1 : GPIO 29 controls GPIO/LOANI[29] output and output enable signals.
20621 *
20622 * Field Access Macros:
20623 *
20624 */
20625/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */
20626#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_LSB 0
20627/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */
20628#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_MSB 0
20629/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */
20630#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_WIDTH 1
20631/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value. */
20632#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET_MSK 0x00000001
20633/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value. */
20634#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_CLR_MSK 0xfffffffe
20635/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */
20636#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_RESET 0x0
20637/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX29_SEL field value from a register. */
20638#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_GET(value) (((value) & 0x00000001) >> 0)
20639/* Produces a ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value suitable for setting the register. */
20640#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET(value) (((value) << 0) & 0x00000001)
20641
20642#ifndef __ASSEMBLY__
20643/*
20644 * WARNING: The C register and register group struct declarations are provided for
20645 * convenience and illustrative purposes. They should, however, be used with
20646 * caution as the C language standard provides no guarantees about the alignment or
20647 * atomicity of device memory accesses. The recommended practice for writing
20648 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20649 * alt_write_word() functions.
20650 *
20651 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX29.
20652 */
20653 struct ALT_SYSMGR_PINMUX_GPLMUX29_s
20654{
20655 uint32_t sel : 1; /* GPIO/Loan IO29Input Mux Selection Field */
20656 uint32_t : 31; /* *UNDEFINED* */
20657};
20658
20659/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX29. */
20660typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX29_s ALT_SYSMGR_PINMUX_GPLMUX29_t;
20661#endif /* __ASSEMBLY__ */
20662
20663/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX29 register from the beginning of the component. */
20664#define ALT_SYSMGR_PINMUX_GPLMUX29_OFST 0x248
20665
20666/*
20667 * Register : GPIO/LoanIO 30 Output/Output Enable Mux Selection Register - GPLMUX30
20668 *
20669 * Selection between GPIO and LoanIO output and output enable for GPIO30 and
20670 * LoanIO30. These signals drive the Pin Mux. The Pin Mux must be configured to use
20671 * GPIO/LoanIO in addition to these settings
20672 *
20673 * Only reset by a cold reset (ignores warm reset).
20674 *
20675 * NOTE: These registers should not be modified after IO configuration.There is no
20676 * support for dynamically changing the Pin Mux selections.
20677 *
20678 * Register Layout
20679 *
20680 * Bits | Access | Reset | Description
20681 * :-------|:-------|:------|:----------------------------------------
20682 * [0] | RW | 0x0 | GPIO/Loan IO30Input Mux Selection Field
20683 * [31:1] | ??? | 0x0 | *UNDEFINED*
20684 *
20685 */
20686/*
20687 * Field : GPIO/Loan IO30Input Mux Selection Field - sel
20688 *
20689 * Select source for GPIO/LoanIO 30.
20690 *
20691 * 0 : LoanIO 30 controls GPIO/LOANIO[30] output and output enable signals.
20692 *
20693 * 1 : GPIO 30 controls GPIO/LOANI[30] output and output enable signals.
20694 *
20695 * Field Access Macros:
20696 *
20697 */
20698/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */
20699#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_LSB 0
20700/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */
20701#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_MSB 0
20702/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */
20703#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_WIDTH 1
20704/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value. */
20705#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET_MSK 0x00000001
20706/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value. */
20707#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_CLR_MSK 0xfffffffe
20708/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */
20709#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_RESET 0x0
20710/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX30_SEL field value from a register. */
20711#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_GET(value) (((value) & 0x00000001) >> 0)
20712/* Produces a ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value suitable for setting the register. */
20713#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET(value) (((value) << 0) & 0x00000001)
20714
20715#ifndef __ASSEMBLY__
20716/*
20717 * WARNING: The C register and register group struct declarations are provided for
20718 * convenience and illustrative purposes. They should, however, be used with
20719 * caution as the C language standard provides no guarantees about the alignment or
20720 * atomicity of device memory accesses. The recommended practice for writing
20721 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20722 * alt_write_word() functions.
20723 *
20724 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX30.
20725 */
20726 struct ALT_SYSMGR_PINMUX_GPLMUX30_s
20727{
20728 uint32_t sel : 1; /* GPIO/Loan IO30Input Mux Selection Field */
20729 uint32_t : 31; /* *UNDEFINED* */
20730};
20731
20732/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX30. */
20733typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX30_s ALT_SYSMGR_PINMUX_GPLMUX30_t;
20734#endif /* __ASSEMBLY__ */
20735
20736/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX30 register from the beginning of the component. */
20737#define ALT_SYSMGR_PINMUX_GPLMUX30_OFST 0x24c
20738
20739/*
20740 * Register : GPIO/LoanIO 31 Output/Output Enable Mux Selection Register - GPLMUX31
20741 *
20742 * Selection between GPIO and LoanIO output and output enable for GPIO31 and
20743 * LoanIO31. These signals drive the Pin Mux. The Pin Mux must be configured to use
20744 * GPIO/LoanIO in addition to these settings
20745 *
20746 * Only reset by a cold reset (ignores warm reset).
20747 *
20748 * NOTE: These registers should not be modified after IO configuration.There is no
20749 * support for dynamically changing the Pin Mux selections.
20750 *
20751 * Register Layout
20752 *
20753 * Bits | Access | Reset | Description
20754 * :-------|:-------|:------|:----------------------------------------
20755 * [0] | RW | 0x0 | GPIO/Loan IO31Input Mux Selection Field
20756 * [31:1] | ??? | 0x0 | *UNDEFINED*
20757 *
20758 */
20759/*
20760 * Field : GPIO/Loan IO31Input Mux Selection Field - sel
20761 *
20762 * Select source for GPIO/LoanIO 31.
20763 *
20764 * 0 : LoanIO 31 controls GPIO/LOANIO[31] output and output enable signals.
20765 *
20766 * 1 : GPIO 31 controls GPIO/LOANI[31] output and output enable signals.
20767 *
20768 * Field Access Macros:
20769 *
20770 */
20771/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */
20772#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_LSB 0
20773/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */
20774#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_MSB 0
20775/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */
20776#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_WIDTH 1
20777/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value. */
20778#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET_MSK 0x00000001
20779/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value. */
20780#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_CLR_MSK 0xfffffffe
20781/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */
20782#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_RESET 0x0
20783/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX31_SEL field value from a register. */
20784#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_GET(value) (((value) & 0x00000001) >> 0)
20785/* Produces a ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value suitable for setting the register. */
20786#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET(value) (((value) << 0) & 0x00000001)
20787
20788#ifndef __ASSEMBLY__
20789/*
20790 * WARNING: The C register and register group struct declarations are provided for
20791 * convenience and illustrative purposes. They should, however, be used with
20792 * caution as the C language standard provides no guarantees about the alignment or
20793 * atomicity of device memory accesses. The recommended practice for writing
20794 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20795 * alt_write_word() functions.
20796 *
20797 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX31.
20798 */
20799 struct ALT_SYSMGR_PINMUX_GPLMUX31_s
20800{
20801 uint32_t sel : 1; /* GPIO/Loan IO31Input Mux Selection Field */
20802 uint32_t : 31; /* *UNDEFINED* */
20803};
20804
20805/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX31. */
20806typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX31_s ALT_SYSMGR_PINMUX_GPLMUX31_t;
20807#endif /* __ASSEMBLY__ */
20808
20809/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX31 register from the beginning of the component. */
20810#define ALT_SYSMGR_PINMUX_GPLMUX31_OFST 0x250
20811
20812/*
20813 * Register : GPIO/LoanIO 32 Output/Output Enable Mux Selection Register - GPLMUX32
20814 *
20815 * Selection between GPIO and LoanIO output and output enable for GPIO32 and
20816 * LoanIO32. These signals drive the Pin Mux. The Pin Mux must be configured to use
20817 * GPIO/LoanIO in addition to these settings
20818 *
20819 * Only reset by a cold reset (ignores warm reset).
20820 *
20821 * NOTE: These registers should not be modified after IO configuration.There is no
20822 * support for dynamically changing the Pin Mux selections.
20823 *
20824 * Register Layout
20825 *
20826 * Bits | Access | Reset | Description
20827 * :-------|:-------|:------|:----------------------------------------
20828 * [0] | RW | 0x0 | GPIO/Loan IO32Input Mux Selection Field
20829 * [31:1] | ??? | 0x0 | *UNDEFINED*
20830 *
20831 */
20832/*
20833 * Field : GPIO/Loan IO32Input Mux Selection Field - sel
20834 *
20835 * Select source for GPIO/LoanIO 32.
20836 *
20837 * 0 : LoanIO 32 controls GPIO/LOANIO[32] output and output enable signals.
20838 *
20839 * 1 : GPIO 32 controls GPIO/LOANI[32] output and output enable signals.
20840 *
20841 * Field Access Macros:
20842 *
20843 */
20844/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */
20845#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_LSB 0
20846/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */
20847#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_MSB 0
20848/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */
20849#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_WIDTH 1
20850/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value. */
20851#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET_MSK 0x00000001
20852/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value. */
20853#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_CLR_MSK 0xfffffffe
20854/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */
20855#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_RESET 0x0
20856/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX32_SEL field value from a register. */
20857#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_GET(value) (((value) & 0x00000001) >> 0)
20858/* Produces a ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value suitable for setting the register. */
20859#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET(value) (((value) << 0) & 0x00000001)
20860
20861#ifndef __ASSEMBLY__
20862/*
20863 * WARNING: The C register and register group struct declarations are provided for
20864 * convenience and illustrative purposes. They should, however, be used with
20865 * caution as the C language standard provides no guarantees about the alignment or
20866 * atomicity of device memory accesses. The recommended practice for writing
20867 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20868 * alt_write_word() functions.
20869 *
20870 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX32.
20871 */
20872 struct ALT_SYSMGR_PINMUX_GPLMUX32_s
20873{
20874 uint32_t sel : 1; /* GPIO/Loan IO32Input Mux Selection Field */
20875 uint32_t : 31; /* *UNDEFINED* */
20876};
20877
20878/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX32. */
20879typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX32_s ALT_SYSMGR_PINMUX_GPLMUX32_t;
20880#endif /* __ASSEMBLY__ */
20881
20882/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX32 register from the beginning of the component. */
20883#define ALT_SYSMGR_PINMUX_GPLMUX32_OFST 0x254
20884
20885/*
20886 * Register : GPIO/LoanIO 33 Output/Output Enable Mux Selection Register - GPLMUX33
20887 *
20888 * Selection between GPIO and LoanIO output and output enable for GPIO33 and
20889 * LoanIO33. These signals drive the Pin Mux. The Pin Mux must be configured to use
20890 * GPIO/LoanIO in addition to these settings
20891 *
20892 * Only reset by a cold reset (ignores warm reset).
20893 *
20894 * NOTE: These registers should not be modified after IO configuration.There is no
20895 * support for dynamically changing the Pin Mux selections.
20896 *
20897 * Register Layout
20898 *
20899 * Bits | Access | Reset | Description
20900 * :-------|:-------|:------|:----------------------------------------
20901 * [0] | RW | 0x0 | GPIO/Loan IO33Input Mux Selection Field
20902 * [31:1] | ??? | 0x0 | *UNDEFINED*
20903 *
20904 */
20905/*
20906 * Field : GPIO/Loan IO33Input Mux Selection Field - sel
20907 *
20908 * Select source for GPIO/LoanIO 33.
20909 *
20910 * 0 : LoanIO 33 controls GPIO/LOANIO[33] output and output enable signals.
20911 *
20912 * 1 : GPIO 33 controls GPIO/LOANI[33] output and output enable signals.
20913 *
20914 * Field Access Macros:
20915 *
20916 */
20917/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */
20918#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_LSB 0
20919/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */
20920#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_MSB 0
20921/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */
20922#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_WIDTH 1
20923/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value. */
20924#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET_MSK 0x00000001
20925/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value. */
20926#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_CLR_MSK 0xfffffffe
20927/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */
20928#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_RESET 0x0
20929/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX33_SEL field value from a register. */
20930#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_GET(value) (((value) & 0x00000001) >> 0)
20931/* Produces a ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value suitable for setting the register. */
20932#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET(value) (((value) << 0) & 0x00000001)
20933
20934#ifndef __ASSEMBLY__
20935/*
20936 * WARNING: The C register and register group struct declarations are provided for
20937 * convenience and illustrative purposes. They should, however, be used with
20938 * caution as the C language standard provides no guarantees about the alignment or
20939 * atomicity of device memory accesses. The recommended practice for writing
20940 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20941 * alt_write_word() functions.
20942 *
20943 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX33.
20944 */
20945 struct ALT_SYSMGR_PINMUX_GPLMUX33_s
20946{
20947 uint32_t sel : 1; /* GPIO/Loan IO33Input Mux Selection Field */
20948 uint32_t : 31; /* *UNDEFINED* */
20949};
20950
20951/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX33. */
20952typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX33_s ALT_SYSMGR_PINMUX_GPLMUX33_t;
20953#endif /* __ASSEMBLY__ */
20954
20955/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX33 register from the beginning of the component. */
20956#define ALT_SYSMGR_PINMUX_GPLMUX33_OFST 0x258
20957
20958/*
20959 * Register : GPIO/LoanIO 34 Output/Output Enable Mux Selection Register - GPLMUX34
20960 *
20961 * Selection between GPIO and LoanIO output and output enable for GPIO34 and
20962 * LoanIO34. These signals drive the Pin Mux. The Pin Mux must be configured to use
20963 * GPIO/LoanIO in addition to these settings
20964 *
20965 * Only reset by a cold reset (ignores warm reset).
20966 *
20967 * NOTE: These registers should not be modified after IO configuration.There is no
20968 * support for dynamically changing the Pin Mux selections.
20969 *
20970 * Register Layout
20971 *
20972 * Bits | Access | Reset | Description
20973 * :-------|:-------|:------|:----------------------------------------
20974 * [0] | RW | 0x0 | GPIO/Loan IO34Input Mux Selection Field
20975 * [31:1] | ??? | 0x0 | *UNDEFINED*
20976 *
20977 */
20978/*
20979 * Field : GPIO/Loan IO34Input Mux Selection Field - sel
20980 *
20981 * Select source for GPIO/LoanIO 34.
20982 *
20983 * 0 : LoanIO 34 controls GPIO/LOANIO[34] output and output enable signals.
20984 *
20985 * 1 : GPIO 34 controls GPIO/LOANI[34] output and output enable signals.
20986 *
20987 * Field Access Macros:
20988 *
20989 */
20990/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */
20991#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_LSB 0
20992/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */
20993#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_MSB 0
20994/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */
20995#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_WIDTH 1
20996/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value. */
20997#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET_MSK 0x00000001
20998/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value. */
20999#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_CLR_MSK 0xfffffffe
21000/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */
21001#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_RESET 0x0
21002/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX34_SEL field value from a register. */
21003#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_GET(value) (((value) & 0x00000001) >> 0)
21004/* Produces a ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value suitable for setting the register. */
21005#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET(value) (((value) << 0) & 0x00000001)
21006
21007#ifndef __ASSEMBLY__
21008/*
21009 * WARNING: The C register and register group struct declarations are provided for
21010 * convenience and illustrative purposes. They should, however, be used with
21011 * caution as the C language standard provides no guarantees about the alignment or
21012 * atomicity of device memory accesses. The recommended practice for writing
21013 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21014 * alt_write_word() functions.
21015 *
21016 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX34.
21017 */
21018 struct ALT_SYSMGR_PINMUX_GPLMUX34_s
21019{
21020 uint32_t sel : 1; /* GPIO/Loan IO34Input Mux Selection Field */
21021 uint32_t : 31; /* *UNDEFINED* */
21022};
21023
21024/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX34. */
21025typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX34_s ALT_SYSMGR_PINMUX_GPLMUX34_t;
21026#endif /* __ASSEMBLY__ */
21027
21028/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX34 register from the beginning of the component. */
21029#define ALT_SYSMGR_PINMUX_GPLMUX34_OFST 0x25c
21030
21031/*
21032 * Register : GPIO/LoanIO 35 Output/Output Enable Mux Selection Register - GPLMUX35
21033 *
21034 * Selection between GPIO and LoanIO output and output enable for GPIO35 and
21035 * LoanIO35. These signals drive the Pin Mux. The Pin Mux must be configured to use
21036 * GPIO/LoanIO in addition to these settings
21037 *
21038 * Only reset by a cold reset (ignores warm reset).
21039 *
21040 * NOTE: These registers should not be modified after IO configuration.There is no
21041 * support for dynamically changing the Pin Mux selections.
21042 *
21043 * Register Layout
21044 *
21045 * Bits | Access | Reset | Description
21046 * :-------|:-------|:------|:----------------------------------------
21047 * [0] | RW | 0x0 | GPIO/Loan IO35Input Mux Selection Field
21048 * [31:1] | ??? | 0x0 | *UNDEFINED*
21049 *
21050 */
21051/*
21052 * Field : GPIO/Loan IO35Input Mux Selection Field - sel
21053 *
21054 * Select source for GPIO/LoanIO 35.
21055 *
21056 * 0 : LoanIO 35 controls GPIO/LOANIO[35] output and output enable signals.
21057 *
21058 * 1 : GPIO 35 controls GPIO/LOANI[35] output and output enable signals.
21059 *
21060 * Field Access Macros:
21061 *
21062 */
21063/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */
21064#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_LSB 0
21065/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */
21066#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_MSB 0
21067/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */
21068#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_WIDTH 1
21069/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value. */
21070#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET_MSK 0x00000001
21071/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value. */
21072#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_CLR_MSK 0xfffffffe
21073/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */
21074#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_RESET 0x0
21075/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX35_SEL field value from a register. */
21076#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_GET(value) (((value) & 0x00000001) >> 0)
21077/* Produces a ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value suitable for setting the register. */
21078#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET(value) (((value) << 0) & 0x00000001)
21079
21080#ifndef __ASSEMBLY__
21081/*
21082 * WARNING: The C register and register group struct declarations are provided for
21083 * convenience and illustrative purposes. They should, however, be used with
21084 * caution as the C language standard provides no guarantees about the alignment or
21085 * atomicity of device memory accesses. The recommended practice for writing
21086 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21087 * alt_write_word() functions.
21088 *
21089 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX35.
21090 */
21091 struct ALT_SYSMGR_PINMUX_GPLMUX35_s
21092{
21093 uint32_t sel : 1; /* GPIO/Loan IO35Input Mux Selection Field */
21094 uint32_t : 31; /* *UNDEFINED* */
21095};
21096
21097/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX35. */
21098typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX35_s ALT_SYSMGR_PINMUX_GPLMUX35_t;
21099#endif /* __ASSEMBLY__ */
21100
21101/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX35 register from the beginning of the component. */
21102#define ALT_SYSMGR_PINMUX_GPLMUX35_OFST 0x260
21103
21104/*
21105 * Register : GPIO/LoanIO 36 Output/Output Enable Mux Selection Register - GPLMUX36
21106 *
21107 * Selection between GPIO and LoanIO output and output enable for GPIO36 and
21108 * LoanIO36. These signals drive the Pin Mux. The Pin Mux must be configured to use
21109 * GPIO/LoanIO in addition to these settings
21110 *
21111 * Only reset by a cold reset (ignores warm reset).
21112 *
21113 * NOTE: These registers should not be modified after IO configuration.There is no
21114 * support for dynamically changing the Pin Mux selections.
21115 *
21116 * Register Layout
21117 *
21118 * Bits | Access | Reset | Description
21119 * :-------|:-------|:------|:----------------------------------------
21120 * [0] | RW | 0x0 | GPIO/Loan IO36Input Mux Selection Field
21121 * [31:1] | ??? | 0x0 | *UNDEFINED*
21122 *
21123 */
21124/*
21125 * Field : GPIO/Loan IO36Input Mux Selection Field - sel
21126 *
21127 * Select source for GPIO/LoanIO 36.
21128 *
21129 * 0 : LoanIO 36 controls GPIO/LOANIO[36] output and output enable signals.
21130 *
21131 * 1 : GPIO 36 controls GPIO/LOANI[36] output and output enable signals.
21132 *
21133 * Field Access Macros:
21134 *
21135 */
21136/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */
21137#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_LSB 0
21138/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */
21139#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_MSB 0
21140/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */
21141#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_WIDTH 1
21142/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value. */
21143#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET_MSK 0x00000001
21144/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value. */
21145#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_CLR_MSK 0xfffffffe
21146/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */
21147#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_RESET 0x0
21148/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX36_SEL field value from a register. */
21149#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_GET(value) (((value) & 0x00000001) >> 0)
21150/* Produces a ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value suitable for setting the register. */
21151#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET(value) (((value) << 0) & 0x00000001)
21152
21153#ifndef __ASSEMBLY__
21154/*
21155 * WARNING: The C register and register group struct declarations are provided for
21156 * convenience and illustrative purposes. They should, however, be used with
21157 * caution as the C language standard provides no guarantees about the alignment or
21158 * atomicity of device memory accesses. The recommended practice for writing
21159 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21160 * alt_write_word() functions.
21161 *
21162 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX36.
21163 */
21164 struct ALT_SYSMGR_PINMUX_GPLMUX36_s
21165{
21166 uint32_t sel : 1; /* GPIO/Loan IO36Input Mux Selection Field */
21167 uint32_t : 31; /* *UNDEFINED* */
21168};
21169
21170/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX36. */
21171typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX36_s ALT_SYSMGR_PINMUX_GPLMUX36_t;
21172#endif /* __ASSEMBLY__ */
21173
21174/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX36 register from the beginning of the component. */
21175#define ALT_SYSMGR_PINMUX_GPLMUX36_OFST 0x264
21176
21177/*
21178 * Register : GPIO/LoanIO 37 Output/Output Enable Mux Selection Register - GPLMUX37
21179 *
21180 * Selection between GPIO and LoanIO output and output enable for GPIO37 and
21181 * LoanIO37. These signals drive the Pin Mux. The Pin Mux must be configured to use
21182 * GPIO/LoanIO in addition to these settings
21183 *
21184 * Only reset by a cold reset (ignores warm reset).
21185 *
21186 * NOTE: These registers should not be modified after IO configuration.There is no
21187 * support for dynamically changing the Pin Mux selections.
21188 *
21189 * Register Layout
21190 *
21191 * Bits | Access | Reset | Description
21192 * :-------|:-------|:------|:----------------------------------------
21193 * [0] | RW | 0x0 | GPIO/Loan IO37Input Mux Selection Field
21194 * [31:1] | ??? | 0x0 | *UNDEFINED*
21195 *
21196 */
21197/*
21198 * Field : GPIO/Loan IO37Input Mux Selection Field - sel
21199 *
21200 * Select source for GPIO/LoanIO 37.
21201 *
21202 * 0 : LoanIO 37 controls GPIO/LOANIO[37] output and output enable signals.
21203 *
21204 * 1 : GPIO 37 controls GPIO/LOANI[37] output and output enable signals.
21205 *
21206 * Field Access Macros:
21207 *
21208 */
21209/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */
21210#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_LSB 0
21211/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */
21212#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_MSB 0
21213/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */
21214#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_WIDTH 1
21215/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value. */
21216#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET_MSK 0x00000001
21217/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value. */
21218#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_CLR_MSK 0xfffffffe
21219/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */
21220#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_RESET 0x0
21221/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX37_SEL field value from a register. */
21222#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_GET(value) (((value) & 0x00000001) >> 0)
21223/* Produces a ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value suitable for setting the register. */
21224#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET(value) (((value) << 0) & 0x00000001)
21225
21226#ifndef __ASSEMBLY__
21227/*
21228 * WARNING: The C register and register group struct declarations are provided for
21229 * convenience and illustrative purposes. They should, however, be used with
21230 * caution as the C language standard provides no guarantees about the alignment or
21231 * atomicity of device memory accesses. The recommended practice for writing
21232 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21233 * alt_write_word() functions.
21234 *
21235 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX37.
21236 */
21237 struct ALT_SYSMGR_PINMUX_GPLMUX37_s
21238{
21239 uint32_t sel : 1; /* GPIO/Loan IO37Input Mux Selection Field */
21240 uint32_t : 31; /* *UNDEFINED* */
21241};
21242
21243/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX37. */
21244typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX37_s ALT_SYSMGR_PINMUX_GPLMUX37_t;
21245#endif /* __ASSEMBLY__ */
21246
21247/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX37 register from the beginning of the component. */
21248#define ALT_SYSMGR_PINMUX_GPLMUX37_OFST 0x268
21249
21250/*
21251 * Register : GPIO/LoanIO 38 Output/Output Enable Mux Selection Register - GPLMUX38
21252 *
21253 * Selection between GPIO and LoanIO output and output enable for GPIO38 and
21254 * LoanIO38. These signals drive the Pin Mux. The Pin Mux must be configured to use
21255 * GPIO/LoanIO in addition to these settings
21256 *
21257 * Only reset by a cold reset (ignores warm reset).
21258 *
21259 * NOTE: These registers should not be modified after IO configuration.There is no
21260 * support for dynamically changing the Pin Mux selections.
21261 *
21262 * Register Layout
21263 *
21264 * Bits | Access | Reset | Description
21265 * :-------|:-------|:------|:----------------------------------------
21266 * [0] | RW | 0x0 | GPIO/Loan IO38Input Mux Selection Field
21267 * [31:1] | ??? | 0x0 | *UNDEFINED*
21268 *
21269 */
21270/*
21271 * Field : GPIO/Loan IO38Input Mux Selection Field - sel
21272 *
21273 * Select source for GPIO/LoanIO 38.
21274 *
21275 * 0 : LoanIO 38 controls GPIO/LOANIO[38] output and output enable signals.
21276 *
21277 * 1 : GPIO 38 controls GPIO/LOANI[38] output and output enable signals.
21278 *
21279 * Field Access Macros:
21280 *
21281 */
21282/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */
21283#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_LSB 0
21284/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */
21285#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_MSB 0
21286/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */
21287#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_WIDTH 1
21288/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value. */
21289#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET_MSK 0x00000001
21290/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value. */
21291#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_CLR_MSK 0xfffffffe
21292/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */
21293#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_RESET 0x0
21294/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX38_SEL field value from a register. */
21295#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_GET(value) (((value) & 0x00000001) >> 0)
21296/* Produces a ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value suitable for setting the register. */
21297#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET(value) (((value) << 0) & 0x00000001)
21298
21299#ifndef __ASSEMBLY__
21300/*
21301 * WARNING: The C register and register group struct declarations are provided for
21302 * convenience and illustrative purposes. They should, however, be used with
21303 * caution as the C language standard provides no guarantees about the alignment or
21304 * atomicity of device memory accesses. The recommended practice for writing
21305 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21306 * alt_write_word() functions.
21307 *
21308 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX38.
21309 */
21310 struct ALT_SYSMGR_PINMUX_GPLMUX38_s
21311{
21312 uint32_t sel : 1; /* GPIO/Loan IO38Input Mux Selection Field */
21313 uint32_t : 31; /* *UNDEFINED* */
21314};
21315
21316/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX38. */
21317typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX38_s ALT_SYSMGR_PINMUX_GPLMUX38_t;
21318#endif /* __ASSEMBLY__ */
21319
21320/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX38 register from the beginning of the component. */
21321#define ALT_SYSMGR_PINMUX_GPLMUX38_OFST 0x26c
21322
21323/*
21324 * Register : GPIO/LoanIO 39 Output/Output Enable Mux Selection Register - GPLMUX39
21325 *
21326 * Selection between GPIO and LoanIO output and output enable for GPIO39 and
21327 * LoanIO39. These signals drive the Pin Mux. The Pin Mux must be configured to use
21328 * GPIO/LoanIO in addition to these settings
21329 *
21330 * Only reset by a cold reset (ignores warm reset).
21331 *
21332 * NOTE: These registers should not be modified after IO configuration.There is no
21333 * support for dynamically changing the Pin Mux selections.
21334 *
21335 * Register Layout
21336 *
21337 * Bits | Access | Reset | Description
21338 * :-------|:-------|:------|:----------------------------------------
21339 * [0] | RW | 0x0 | GPIO/Loan IO39Input Mux Selection Field
21340 * [31:1] | ??? | 0x0 | *UNDEFINED*
21341 *
21342 */
21343/*
21344 * Field : GPIO/Loan IO39Input Mux Selection Field - sel
21345 *
21346 * Select source for GPIO/LoanIO 39.
21347 *
21348 * 0 : LoanIO 39 controls GPIO/LOANIO[39] output and output enable signals.
21349 *
21350 * 1 : GPIO 39 controls GPIO/LOANI[39] output and output enable signals.
21351 *
21352 * Field Access Macros:
21353 *
21354 */
21355/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */
21356#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_LSB 0
21357/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */
21358#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_MSB 0
21359/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */
21360#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_WIDTH 1
21361/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value. */
21362#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET_MSK 0x00000001
21363/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value. */
21364#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_CLR_MSK 0xfffffffe
21365/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */
21366#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_RESET 0x0
21367/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX39_SEL field value from a register. */
21368#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_GET(value) (((value) & 0x00000001) >> 0)
21369/* Produces a ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value suitable for setting the register. */
21370#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET(value) (((value) << 0) & 0x00000001)
21371
21372#ifndef __ASSEMBLY__
21373/*
21374 * WARNING: The C register and register group struct declarations are provided for
21375 * convenience and illustrative purposes. They should, however, be used with
21376 * caution as the C language standard provides no guarantees about the alignment or
21377 * atomicity of device memory accesses. The recommended practice for writing
21378 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21379 * alt_write_word() functions.
21380 *
21381 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX39.
21382 */
21383 struct ALT_SYSMGR_PINMUX_GPLMUX39_s
21384{
21385 uint32_t sel : 1; /* GPIO/Loan IO39Input Mux Selection Field */
21386 uint32_t : 31; /* *UNDEFINED* */
21387};
21388
21389/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX39. */
21390typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX39_s ALT_SYSMGR_PINMUX_GPLMUX39_t;
21391#endif /* __ASSEMBLY__ */
21392
21393/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX39 register from the beginning of the component. */
21394#define ALT_SYSMGR_PINMUX_GPLMUX39_OFST 0x270
21395
21396/*
21397 * Register : GPIO/LoanIO 40 Output/Output Enable Mux Selection Register - GPLMUX40
21398 *
21399 * Selection between GPIO and LoanIO output and output enable for GPIO40 and
21400 * LoanIO40. These signals drive the Pin Mux. The Pin Mux must be configured to use
21401 * GPIO/LoanIO in addition to these settings
21402 *
21403 * Only reset by a cold reset (ignores warm reset).
21404 *
21405 * NOTE: These registers should not be modified after IO configuration.There is no
21406 * support for dynamically changing the Pin Mux selections.
21407 *
21408 * Register Layout
21409 *
21410 * Bits | Access | Reset | Description
21411 * :-------|:-------|:------|:----------------------------------------
21412 * [0] | RW | 0x0 | GPIO/Loan IO40Input Mux Selection Field
21413 * [31:1] | ??? | 0x0 | *UNDEFINED*
21414 *
21415 */
21416/*
21417 * Field : GPIO/Loan IO40Input Mux Selection Field - sel
21418 *
21419 * Select source for GPIO/LoanIO 40.
21420 *
21421 * 0 : LoanIO 40 controls GPIO/LOANIO[40] output and output enable signals.
21422 *
21423 * 1 : GPIO 40 controls GPIO/LOANI[40] output and output enable signals.
21424 *
21425 * Field Access Macros:
21426 *
21427 */
21428/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */
21429#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_LSB 0
21430/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */
21431#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_MSB 0
21432/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */
21433#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_WIDTH 1
21434/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value. */
21435#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET_MSK 0x00000001
21436/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value. */
21437#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_CLR_MSK 0xfffffffe
21438/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */
21439#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_RESET 0x0
21440/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX40_SEL field value from a register. */
21441#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_GET(value) (((value) & 0x00000001) >> 0)
21442/* Produces a ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value suitable for setting the register. */
21443#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET(value) (((value) << 0) & 0x00000001)
21444
21445#ifndef __ASSEMBLY__
21446/*
21447 * WARNING: The C register and register group struct declarations are provided for
21448 * convenience and illustrative purposes. They should, however, be used with
21449 * caution as the C language standard provides no guarantees about the alignment or
21450 * atomicity of device memory accesses. The recommended practice for writing
21451 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21452 * alt_write_word() functions.
21453 *
21454 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX40.
21455 */
21456 struct ALT_SYSMGR_PINMUX_GPLMUX40_s
21457{
21458 uint32_t sel : 1; /* GPIO/Loan IO40Input Mux Selection Field */
21459 uint32_t : 31; /* *UNDEFINED* */
21460};
21461
21462/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX40. */
21463typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX40_s ALT_SYSMGR_PINMUX_GPLMUX40_t;
21464#endif /* __ASSEMBLY__ */
21465
21466/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX40 register from the beginning of the component. */
21467#define ALT_SYSMGR_PINMUX_GPLMUX40_OFST 0x274
21468
21469/*
21470 * Register : GPIO/LoanIO 41 Output/Output Enable Mux Selection Register - GPLMUX41
21471 *
21472 * Selection between GPIO and LoanIO output and output enable for GPIO41 and
21473 * LoanIO41. These signals drive the Pin Mux. The Pin Mux must be configured to use
21474 * GPIO/LoanIO in addition to these settings
21475 *
21476 * Only reset by a cold reset (ignores warm reset).
21477 *
21478 * NOTE: These registers should not be modified after IO configuration.There is no
21479 * support for dynamically changing the Pin Mux selections.
21480 *
21481 * Register Layout
21482 *
21483 * Bits | Access | Reset | Description
21484 * :-------|:-------|:------|:----------------------------------------
21485 * [0] | RW | 0x0 | GPIO/Loan IO41Input Mux Selection Field
21486 * [31:1] | ??? | 0x0 | *UNDEFINED*
21487 *
21488 */
21489/*
21490 * Field : GPIO/Loan IO41Input Mux Selection Field - sel
21491 *
21492 * Select source for GPIO/LoanIO 41.
21493 *
21494 * 0 : LoanIO 41 controls GPIO/LOANIO[41] output and output enable signals.
21495 *
21496 * 1 : GPIO 41 controls GPIO/LOANI[41] output and output enable signals.
21497 *
21498 * Field Access Macros:
21499 *
21500 */
21501/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */
21502#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_LSB 0
21503/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */
21504#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_MSB 0
21505/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */
21506#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_WIDTH 1
21507/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value. */
21508#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET_MSK 0x00000001
21509/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value. */
21510#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_CLR_MSK 0xfffffffe
21511/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */
21512#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_RESET 0x0
21513/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX41_SEL field value from a register. */
21514#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_GET(value) (((value) & 0x00000001) >> 0)
21515/* Produces a ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value suitable for setting the register. */
21516#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET(value) (((value) << 0) & 0x00000001)
21517
21518#ifndef __ASSEMBLY__
21519/*
21520 * WARNING: The C register and register group struct declarations are provided for
21521 * convenience and illustrative purposes. They should, however, be used with
21522 * caution as the C language standard provides no guarantees about the alignment or
21523 * atomicity of device memory accesses. The recommended practice for writing
21524 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21525 * alt_write_word() functions.
21526 *
21527 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX41.
21528 */
21529 struct ALT_SYSMGR_PINMUX_GPLMUX41_s
21530{
21531 uint32_t sel : 1; /* GPIO/Loan IO41Input Mux Selection Field */
21532 uint32_t : 31; /* *UNDEFINED* */
21533};
21534
21535/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX41. */
21536typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX41_s ALT_SYSMGR_PINMUX_GPLMUX41_t;
21537#endif /* __ASSEMBLY__ */
21538
21539/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX41 register from the beginning of the component. */
21540#define ALT_SYSMGR_PINMUX_GPLMUX41_OFST 0x278
21541
21542/*
21543 * Register : GPIO/LoanIO 42 Output/Output Enable Mux Selection Register - GPLMUX42
21544 *
21545 * Selection between GPIO and LoanIO output and output enable for GPIO42 and
21546 * LoanIO42. These signals drive the Pin Mux. The Pin Mux must be configured to use
21547 * GPIO/LoanIO in addition to these settings
21548 *
21549 * Only reset by a cold reset (ignores warm reset).
21550 *
21551 * NOTE: These registers should not be modified after IO configuration.There is no
21552 * support for dynamically changing the Pin Mux selections.
21553 *
21554 * Register Layout
21555 *
21556 * Bits | Access | Reset | Description
21557 * :-------|:-------|:------|:----------------------------------------
21558 * [0] | RW | 0x0 | GPIO/Loan IO42Input Mux Selection Field
21559 * [31:1] | ??? | 0x0 | *UNDEFINED*
21560 *
21561 */
21562/*
21563 * Field : GPIO/Loan IO42Input Mux Selection Field - sel
21564 *
21565 * Select source for GPIO/LoanIO 42.
21566 *
21567 * 0 : LoanIO 42 controls GPIO/LOANIO[42] output and output enable signals.
21568 *
21569 * 1 : GPIO 42 controls GPIO/LOANI[42] output and output enable signals.
21570 *
21571 * Field Access Macros:
21572 *
21573 */
21574/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */
21575#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_LSB 0
21576/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */
21577#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_MSB 0
21578/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */
21579#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_WIDTH 1
21580/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value. */
21581#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET_MSK 0x00000001
21582/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value. */
21583#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_CLR_MSK 0xfffffffe
21584/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */
21585#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_RESET 0x0
21586/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX42_SEL field value from a register. */
21587#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_GET(value) (((value) & 0x00000001) >> 0)
21588/* Produces a ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value suitable for setting the register. */
21589#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET(value) (((value) << 0) & 0x00000001)
21590
21591#ifndef __ASSEMBLY__
21592/*
21593 * WARNING: The C register and register group struct declarations are provided for
21594 * convenience and illustrative purposes. They should, however, be used with
21595 * caution as the C language standard provides no guarantees about the alignment or
21596 * atomicity of device memory accesses. The recommended practice for writing
21597 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21598 * alt_write_word() functions.
21599 *
21600 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX42.
21601 */
21602 struct ALT_SYSMGR_PINMUX_GPLMUX42_s
21603{
21604 uint32_t sel : 1; /* GPIO/Loan IO42Input Mux Selection Field */
21605 uint32_t : 31; /* *UNDEFINED* */
21606};
21607
21608/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX42. */
21609typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX42_s ALT_SYSMGR_PINMUX_GPLMUX42_t;
21610#endif /* __ASSEMBLY__ */
21611
21612/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX42 register from the beginning of the component. */
21613#define ALT_SYSMGR_PINMUX_GPLMUX42_OFST 0x27c
21614
21615/*
21616 * Register : GPIO/LoanIO 43 Output/Output Enable Mux Selection Register - GPLMUX43
21617 *
21618 * Selection between GPIO and LoanIO output and output enable for GPIO43 and
21619 * LoanIO43. These signals drive the Pin Mux. The Pin Mux must be configured to use
21620 * GPIO/LoanIO in addition to these settings
21621 *
21622 * Only reset by a cold reset (ignores warm reset).
21623 *
21624 * NOTE: These registers should not be modified after IO configuration.There is no
21625 * support for dynamically changing the Pin Mux selections.
21626 *
21627 * Register Layout
21628 *
21629 * Bits | Access | Reset | Description
21630 * :-------|:-------|:------|:----------------------------------------
21631 * [0] | RW | 0x0 | GPIO/Loan IO43Input Mux Selection Field
21632 * [31:1] | ??? | 0x0 | *UNDEFINED*
21633 *
21634 */
21635/*
21636 * Field : GPIO/Loan IO43Input Mux Selection Field - sel
21637 *
21638 * Select source for GPIO/LoanIO 43.
21639 *
21640 * 0 : LoanIO 43 controls GPIO/LOANIO[43] output and output enable signals.
21641 *
21642 * 1 : GPIO 43 controls GPIO/LOANI[43] output and output enable signals.
21643 *
21644 * Field Access Macros:
21645 *
21646 */
21647/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */
21648#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_LSB 0
21649/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */
21650#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_MSB 0
21651/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */
21652#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_WIDTH 1
21653/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value. */
21654#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET_MSK 0x00000001
21655/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value. */
21656#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_CLR_MSK 0xfffffffe
21657/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */
21658#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_RESET 0x0
21659/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX43_SEL field value from a register. */
21660#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_GET(value) (((value) & 0x00000001) >> 0)
21661/* Produces a ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value suitable for setting the register. */
21662#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET(value) (((value) << 0) & 0x00000001)
21663
21664#ifndef __ASSEMBLY__
21665/*
21666 * WARNING: The C register and register group struct declarations are provided for
21667 * convenience and illustrative purposes. They should, however, be used with
21668 * caution as the C language standard provides no guarantees about the alignment or
21669 * atomicity of device memory accesses. The recommended practice for writing
21670 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21671 * alt_write_word() functions.
21672 *
21673 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX43.
21674 */
21675 struct ALT_SYSMGR_PINMUX_GPLMUX43_s
21676{
21677 uint32_t sel : 1; /* GPIO/Loan IO43Input Mux Selection Field */
21678 uint32_t : 31; /* *UNDEFINED* */
21679};
21680
21681/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX43. */
21682typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX43_s ALT_SYSMGR_PINMUX_GPLMUX43_t;
21683#endif /* __ASSEMBLY__ */
21684
21685/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX43 register from the beginning of the component. */
21686#define ALT_SYSMGR_PINMUX_GPLMUX43_OFST 0x280
21687
21688/*
21689 * Register : GPIO/LoanIO 44 Output/Output Enable Mux Selection Register - GPLMUX44
21690 *
21691 * Selection between GPIO and LoanIO output and output enable for GPIO44 and
21692 * LoanIO44. These signals drive the Pin Mux. The Pin Mux must be configured to use
21693 * GPIO/LoanIO in addition to these settings
21694 *
21695 * Only reset by a cold reset (ignores warm reset).
21696 *
21697 * NOTE: These registers should not be modified after IO configuration.There is no
21698 * support for dynamically changing the Pin Mux selections.
21699 *
21700 * Register Layout
21701 *
21702 * Bits | Access | Reset | Description
21703 * :-------|:-------|:------|:----------------------------------------
21704 * [0] | RW | 0x0 | GPIO/Loan IO44Input Mux Selection Field
21705 * [31:1] | ??? | 0x0 | *UNDEFINED*
21706 *
21707 */
21708/*
21709 * Field : GPIO/Loan IO44Input Mux Selection Field - sel
21710 *
21711 * Select source for GPIO/LoanIO 44.
21712 *
21713 * 0 : LoanIO 44 controls GPIO/LOANIO[44] output and output enable signals.
21714 *
21715 * 1 : GPIO 44 controls GPIO/LOANI[44] output and output enable signals.
21716 *
21717 * Field Access Macros:
21718 *
21719 */
21720/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */
21721#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_LSB 0
21722/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */
21723#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_MSB 0
21724/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */
21725#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_WIDTH 1
21726/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value. */
21727#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET_MSK 0x00000001
21728/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value. */
21729#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_CLR_MSK 0xfffffffe
21730/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */
21731#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_RESET 0x0
21732/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX44_SEL field value from a register. */
21733#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_GET(value) (((value) & 0x00000001) >> 0)
21734/* Produces a ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value suitable for setting the register. */
21735#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET(value) (((value) << 0) & 0x00000001)
21736
21737#ifndef __ASSEMBLY__
21738/*
21739 * WARNING: The C register and register group struct declarations are provided for
21740 * convenience and illustrative purposes. They should, however, be used with
21741 * caution as the C language standard provides no guarantees about the alignment or
21742 * atomicity of device memory accesses. The recommended practice for writing
21743 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21744 * alt_write_word() functions.
21745 *
21746 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX44.
21747 */
21748 struct ALT_SYSMGR_PINMUX_GPLMUX44_s
21749{
21750 uint32_t sel : 1; /* GPIO/Loan IO44Input Mux Selection Field */
21751 uint32_t : 31; /* *UNDEFINED* */
21752};
21753
21754/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX44. */
21755typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX44_s ALT_SYSMGR_PINMUX_GPLMUX44_t;
21756#endif /* __ASSEMBLY__ */
21757
21758/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX44 register from the beginning of the component. */
21759#define ALT_SYSMGR_PINMUX_GPLMUX44_OFST 0x284
21760
21761/*
21762 * Register : GPIO/LoanIO 45 Output/Output Enable Mux Selection Register - GPLMUX45
21763 *
21764 * Selection between GPIO and LoanIO output and output enable for GPIO45 and
21765 * LoanIO45. These signals drive the Pin Mux. The Pin Mux must be configured to use
21766 * GPIO/LoanIO in addition to these settings
21767 *
21768 * Only reset by a cold reset (ignores warm reset).
21769 *
21770 * NOTE: These registers should not be modified after IO configuration.There is no
21771 * support for dynamically changing the Pin Mux selections.
21772 *
21773 * Register Layout
21774 *
21775 * Bits | Access | Reset | Description
21776 * :-------|:-------|:------|:----------------------------------------
21777 * [0] | RW | 0x0 | GPIO/Loan IO45Input Mux Selection Field
21778 * [31:1] | ??? | 0x0 | *UNDEFINED*
21779 *
21780 */
21781/*
21782 * Field : GPIO/Loan IO45Input Mux Selection Field - sel
21783 *
21784 * Select source for GPIO/LoanIO 45.
21785 *
21786 * 0 : LoanIO 45 controls GPIO/LOANIO[45] output and output enable signals.
21787 *
21788 * 1 : GPIO 45 controls GPIO/LOANI[45] output and output enable signals.
21789 *
21790 * Field Access Macros:
21791 *
21792 */
21793/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */
21794#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_LSB 0
21795/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */
21796#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_MSB 0
21797/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */
21798#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_WIDTH 1
21799/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value. */
21800#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET_MSK 0x00000001
21801/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value. */
21802#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_CLR_MSK 0xfffffffe
21803/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */
21804#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_RESET 0x0
21805/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX45_SEL field value from a register. */
21806#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_GET(value) (((value) & 0x00000001) >> 0)
21807/* Produces a ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value suitable for setting the register. */
21808#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET(value) (((value) << 0) & 0x00000001)
21809
21810#ifndef __ASSEMBLY__
21811/*
21812 * WARNING: The C register and register group struct declarations are provided for
21813 * convenience and illustrative purposes. They should, however, be used with
21814 * caution as the C language standard provides no guarantees about the alignment or
21815 * atomicity of device memory accesses. The recommended practice for writing
21816 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21817 * alt_write_word() functions.
21818 *
21819 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX45.
21820 */
21821 struct ALT_SYSMGR_PINMUX_GPLMUX45_s
21822{
21823 uint32_t sel : 1; /* GPIO/Loan IO45Input Mux Selection Field */
21824 uint32_t : 31; /* *UNDEFINED* */
21825};
21826
21827/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX45. */
21828typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX45_s ALT_SYSMGR_PINMUX_GPLMUX45_t;
21829#endif /* __ASSEMBLY__ */
21830
21831/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX45 register from the beginning of the component. */
21832#define ALT_SYSMGR_PINMUX_GPLMUX45_OFST 0x288
21833
21834/*
21835 * Register : GPIO/LoanIO 46 Output/Output Enable Mux Selection Register - GPLMUX46
21836 *
21837 * Selection between GPIO and LoanIO output and output enable for GPIO46 and
21838 * LoanIO46. These signals drive the Pin Mux. The Pin Mux must be configured to use
21839 * GPIO/LoanIO in addition to these settings
21840 *
21841 * Only reset by a cold reset (ignores warm reset).
21842 *
21843 * NOTE: These registers should not be modified after IO configuration.There is no
21844 * support for dynamically changing the Pin Mux selections.
21845 *
21846 * Register Layout
21847 *
21848 * Bits | Access | Reset | Description
21849 * :-------|:-------|:------|:----------------------------------------
21850 * [0] | RW | 0x0 | GPIO/Loan IO46Input Mux Selection Field
21851 * [31:1] | ??? | 0x0 | *UNDEFINED*
21852 *
21853 */
21854/*
21855 * Field : GPIO/Loan IO46Input Mux Selection Field - sel
21856 *
21857 * Select source for GPIO/LoanIO 46.
21858 *
21859 * 0 : LoanIO 46 controls GPIO/LOANIO[46] output and output enable signals.
21860 *
21861 * 1 : GPIO 46 controls GPIO/LOANI[46] output and output enable signals.
21862 *
21863 * Field Access Macros:
21864 *
21865 */
21866/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */
21867#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_LSB 0
21868/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */
21869#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_MSB 0
21870/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */
21871#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_WIDTH 1
21872/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value. */
21873#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET_MSK 0x00000001
21874/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value. */
21875#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_CLR_MSK 0xfffffffe
21876/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */
21877#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_RESET 0x0
21878/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX46_SEL field value from a register. */
21879#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_GET(value) (((value) & 0x00000001) >> 0)
21880/* Produces a ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value suitable for setting the register. */
21881#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET(value) (((value) << 0) & 0x00000001)
21882
21883#ifndef __ASSEMBLY__
21884/*
21885 * WARNING: The C register and register group struct declarations are provided for
21886 * convenience and illustrative purposes. They should, however, be used with
21887 * caution as the C language standard provides no guarantees about the alignment or
21888 * atomicity of device memory accesses. The recommended practice for writing
21889 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21890 * alt_write_word() functions.
21891 *
21892 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX46.
21893 */
21894 struct ALT_SYSMGR_PINMUX_GPLMUX46_s
21895{
21896 uint32_t sel : 1; /* GPIO/Loan IO46Input Mux Selection Field */
21897 uint32_t : 31; /* *UNDEFINED* */
21898};
21899
21900/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX46. */
21901typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX46_s ALT_SYSMGR_PINMUX_GPLMUX46_t;
21902#endif /* __ASSEMBLY__ */
21903
21904/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX46 register from the beginning of the component. */
21905#define ALT_SYSMGR_PINMUX_GPLMUX46_OFST 0x28c
21906
21907/*
21908 * Register : GPIO/LoanIO 47 Output/Output Enable Mux Selection Register - GPLMUX47
21909 *
21910 * Selection between GPIO and LoanIO output and output enable for GPIO47 and
21911 * LoanIO47. These signals drive the Pin Mux. The Pin Mux must be configured to use
21912 * GPIO/LoanIO in addition to these settings
21913 *
21914 * Only reset by a cold reset (ignores warm reset).
21915 *
21916 * NOTE: These registers should not be modified after IO configuration.There is no
21917 * support for dynamically changing the Pin Mux selections.
21918 *
21919 * Register Layout
21920 *
21921 * Bits | Access | Reset | Description
21922 * :-------|:-------|:------|:----------------------------------------
21923 * [0] | RW | 0x0 | GPIO/Loan IO47Input Mux Selection Field
21924 * [31:1] | ??? | 0x0 | *UNDEFINED*
21925 *
21926 */
21927/*
21928 * Field : GPIO/Loan IO47Input Mux Selection Field - sel
21929 *
21930 * Select source for GPIO/LoanIO 47.
21931 *
21932 * 0 : LoanIO 47 controls GPIO/LOANIO[47] output and output enable signals.
21933 *
21934 * 1 : GPIO 47 controls GPIO/LOANI[47] output and output enable signals.
21935 *
21936 * Field Access Macros:
21937 *
21938 */
21939/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */
21940#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_LSB 0
21941/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */
21942#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_MSB 0
21943/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */
21944#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_WIDTH 1
21945/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value. */
21946#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET_MSK 0x00000001
21947/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value. */
21948#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_CLR_MSK 0xfffffffe
21949/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */
21950#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_RESET 0x0
21951/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX47_SEL field value from a register. */
21952#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_GET(value) (((value) & 0x00000001) >> 0)
21953/* Produces a ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value suitable for setting the register. */
21954#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET(value) (((value) << 0) & 0x00000001)
21955
21956#ifndef __ASSEMBLY__
21957/*
21958 * WARNING: The C register and register group struct declarations are provided for
21959 * convenience and illustrative purposes. They should, however, be used with
21960 * caution as the C language standard provides no guarantees about the alignment or
21961 * atomicity of device memory accesses. The recommended practice for writing
21962 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21963 * alt_write_word() functions.
21964 *
21965 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX47.
21966 */
21967 struct ALT_SYSMGR_PINMUX_GPLMUX47_s
21968{
21969 uint32_t sel : 1; /* GPIO/Loan IO47Input Mux Selection Field */
21970 uint32_t : 31; /* *UNDEFINED* */
21971};
21972
21973/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX47. */
21974typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX47_s ALT_SYSMGR_PINMUX_GPLMUX47_t;
21975#endif /* __ASSEMBLY__ */
21976
21977/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX47 register from the beginning of the component. */
21978#define ALT_SYSMGR_PINMUX_GPLMUX47_OFST 0x290
21979
21980/*
21981 * Register : GPIO/LoanIO 48 Output/Output Enable Mux Selection Register - GPLMUX48
21982 *
21983 * Selection between GPIO and LoanIO output and output enable for GPIO48 and
21984 * LoanIO48. These signals drive the Pin Mux. The Pin Mux must be configured to use
21985 * GPIO/LoanIO in addition to these settings
21986 *
21987 * Only reset by a cold reset (ignores warm reset).
21988 *
21989 * NOTE: These registers should not be modified after IO configuration.There is no
21990 * support for dynamically changing the Pin Mux selections.
21991 *
21992 * Register Layout
21993 *
21994 * Bits | Access | Reset | Description
21995 * :-------|:-------|:------|:----------------------------------------
21996 * [0] | RW | 0x0 | GPIO/Loan IO48Input Mux Selection Field
21997 * [31:1] | ??? | 0x0 | *UNDEFINED*
21998 *
21999 */
22000/*
22001 * Field : GPIO/Loan IO48Input Mux Selection Field - sel
22002 *
22003 * Select source for GPIO/LoanIO 48.
22004 *
22005 * 0 : LoanIO 48 controls GPIO/LOANIO[48] output and output enable signals.
22006 *
22007 * 1 : GPIO 48 controls GPIO/LOANI[48] output and output enable signals.
22008 *
22009 * Field Access Macros:
22010 *
22011 */
22012/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */
22013#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_LSB 0
22014/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */
22015#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_MSB 0
22016/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */
22017#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_WIDTH 1
22018/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value. */
22019#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET_MSK 0x00000001
22020/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value. */
22021#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_CLR_MSK 0xfffffffe
22022/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */
22023#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_RESET 0x0
22024/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX48_SEL field value from a register. */
22025#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0)
22026/* Produces a ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value suitable for setting the register. */
22027#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET(value) (((value) << 0) & 0x00000001)
22028
22029#ifndef __ASSEMBLY__
22030/*
22031 * WARNING: The C register and register group struct declarations are provided for
22032 * convenience and illustrative purposes. They should, however, be used with
22033 * caution as the C language standard provides no guarantees about the alignment or
22034 * atomicity of device memory accesses. The recommended practice for writing
22035 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22036 * alt_write_word() functions.
22037 *
22038 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX48.
22039 */
22040 struct ALT_SYSMGR_PINMUX_GPLMUX48_s
22041{
22042 uint32_t sel : 1; /* GPIO/Loan IO48Input Mux Selection Field */
22043 uint32_t : 31; /* *UNDEFINED* */
22044};
22045
22046/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX48. */
22047typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX48_s ALT_SYSMGR_PINMUX_GPLMUX48_t;
22048#endif /* __ASSEMBLY__ */
22049
22050/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX48 register from the beginning of the component. */
22051#define ALT_SYSMGR_PINMUX_GPLMUX48_OFST 0x294
22052
22053/*
22054 * Register : GPIO/LoanIO 49 Output/Output Enable Mux Selection Register - GPLMUX49
22055 *
22056 * Selection between GPIO and LoanIO output and output enable for GPIO49 and
22057 * LoanIO49. These signals drive the Pin Mux. The Pin Mux must be configured to use
22058 * GPIO/LoanIO in addition to these settings
22059 *
22060 * Only reset by a cold reset (ignores warm reset).
22061 *
22062 * NOTE: These registers should not be modified after IO configuration.There is no
22063 * support for dynamically changing the Pin Mux selections.
22064 *
22065 * Register Layout
22066 *
22067 * Bits | Access | Reset | Description
22068 * :-------|:-------|:------|:----------------------------------------
22069 * [0] | RW | 0x0 | GPIO/Loan IO49Input Mux Selection Field
22070 * [31:1] | ??? | 0x0 | *UNDEFINED*
22071 *
22072 */
22073/*
22074 * Field : GPIO/Loan IO49Input Mux Selection Field - sel
22075 *
22076 * Select source for GPIO/LoanIO 49.
22077 *
22078 * 0 : LoanIO 49 controls GPIO/LOANIO[49] output and output enable signals.
22079 *
22080 * 1 : GPIO 49 controls GPIO/LOANI[49] output and output enable signals.
22081 *
22082 * Field Access Macros:
22083 *
22084 */
22085/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */
22086#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_LSB 0
22087/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */
22088#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_MSB 0
22089/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */
22090#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_WIDTH 1
22091/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value. */
22092#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET_MSK 0x00000001
22093/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value. */
22094#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_CLR_MSK 0xfffffffe
22095/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */
22096#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_RESET 0x0
22097/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX49_SEL field value from a register. */
22098#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0)
22099/* Produces a ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value suitable for setting the register. */
22100#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET(value) (((value) << 0) & 0x00000001)
22101
22102#ifndef __ASSEMBLY__
22103/*
22104 * WARNING: The C register and register group struct declarations are provided for
22105 * convenience and illustrative purposes. They should, however, be used with
22106 * caution as the C language standard provides no guarantees about the alignment or
22107 * atomicity of device memory accesses. The recommended practice for writing
22108 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22109 * alt_write_word() functions.
22110 *
22111 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX49.
22112 */
22113 struct ALT_SYSMGR_PINMUX_GPLMUX49_s
22114{
22115 uint32_t sel : 1; /* GPIO/Loan IO49Input Mux Selection Field */
22116 uint32_t : 31; /* *UNDEFINED* */
22117};
22118
22119/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX49. */
22120typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX49_s ALT_SYSMGR_PINMUX_GPLMUX49_t;
22121#endif /* __ASSEMBLY__ */
22122
22123/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX49 register from the beginning of the component. */
22124#define ALT_SYSMGR_PINMUX_GPLMUX49_OFST 0x298
22125
22126/*
22127 * Register : GPIO/LoanIO 50 Output/Output Enable Mux Selection Register - GPLMUX50
22128 *
22129 * Selection between GPIO and LoanIO output and output enable for GPIO50 and
22130 * LoanIO50. These signals drive the Pin Mux. The Pin Mux must be configured to use
22131 * GPIO/LoanIO in addition to these settings
22132 *
22133 * Only reset by a cold reset (ignores warm reset).
22134 *
22135 * NOTE: These registers should not be modified after IO configuration.There is no
22136 * support for dynamically changing the Pin Mux selections.
22137 *
22138 * Register Layout
22139 *
22140 * Bits | Access | Reset | Description
22141 * :-------|:-------|:------|:----------------------------------------
22142 * [0] | RW | 0x0 | GPIO/Loan IO50Input Mux Selection Field
22143 * [31:1] | ??? | 0x0 | *UNDEFINED*
22144 *
22145 */
22146/*
22147 * Field : GPIO/Loan IO50Input Mux Selection Field - sel
22148 *
22149 * Select source for GPIO/LoanIO 50.
22150 *
22151 * 0 : LoanIO 50 controls GPIO/LOANIO[50] output and output enable signals.
22152 *
22153 * 1 : GPIO 50 controls GPIO/LOANI[50] output and output enable signals.
22154 *
22155 * Field Access Macros:
22156 *
22157 */
22158/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */
22159#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_LSB 0
22160/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */
22161#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_MSB 0
22162/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */
22163#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_WIDTH 1
22164/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value. */
22165#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET_MSK 0x00000001
22166/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value. */
22167#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_CLR_MSK 0xfffffffe
22168/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */
22169#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_RESET 0x0
22170/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX50_SEL field value from a register. */
22171#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0)
22172/* Produces a ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value suitable for setting the register. */
22173#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET(value) (((value) << 0) & 0x00000001)
22174
22175#ifndef __ASSEMBLY__
22176/*
22177 * WARNING: The C register and register group struct declarations are provided for
22178 * convenience and illustrative purposes. They should, however, be used with
22179 * caution as the C language standard provides no guarantees about the alignment or
22180 * atomicity of device memory accesses. The recommended practice for writing
22181 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22182 * alt_write_word() functions.
22183 *
22184 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX50.
22185 */
22186 struct ALT_SYSMGR_PINMUX_GPLMUX50_s
22187{
22188 uint32_t sel : 1; /* GPIO/Loan IO50Input Mux Selection Field */
22189 uint32_t : 31; /* *UNDEFINED* */
22190};
22191
22192/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX50. */
22193typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX50_s ALT_SYSMGR_PINMUX_GPLMUX50_t;
22194#endif /* __ASSEMBLY__ */
22195
22196/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX50 register from the beginning of the component. */
22197#define ALT_SYSMGR_PINMUX_GPLMUX50_OFST 0x29c
22198
22199/*
22200 * Register : GPIO/LoanIO 51 Output/Output Enable Mux Selection Register - GPLMUX51
22201 *
22202 * Selection between GPIO and LoanIO output and output enable for GPIO51 and
22203 * LoanIO51. These signals drive the Pin Mux. The Pin Mux must be configured to use
22204 * GPIO/LoanIO in addition to these settings
22205 *
22206 * Only reset by a cold reset (ignores warm reset).
22207 *
22208 * NOTE: These registers should not be modified after IO configuration.There is no
22209 * support for dynamically changing the Pin Mux selections.
22210 *
22211 * Register Layout
22212 *
22213 * Bits | Access | Reset | Description
22214 * :-------|:-------|:------|:----------------------------------------
22215 * [0] | RW | 0x0 | GPIO/Loan IO51Input Mux Selection Field
22216 * [31:1] | ??? | 0x0 | *UNDEFINED*
22217 *
22218 */
22219/*
22220 * Field : GPIO/Loan IO51Input Mux Selection Field - sel
22221 *
22222 * Select source for GPIO/LoanIO 51.
22223 *
22224 * 0 : LoanIO 51 controls GPIO/LOANIO[51] output and output enable signals.
22225 *
22226 * 1 : GPIO 51 controls GPIO/LOANI[51] output and output enable signals.
22227 *
22228 * Field Access Macros:
22229 *
22230 */
22231/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */
22232#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_LSB 0
22233/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */
22234#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_MSB 0
22235/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */
22236#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_WIDTH 1
22237/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value. */
22238#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET_MSK 0x00000001
22239/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value. */
22240#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_CLR_MSK 0xfffffffe
22241/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */
22242#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_RESET 0x0
22243/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX51_SEL field value from a register. */
22244#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0)
22245/* Produces a ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value suitable for setting the register. */
22246#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET(value) (((value) << 0) & 0x00000001)
22247
22248#ifndef __ASSEMBLY__
22249/*
22250 * WARNING: The C register and register group struct declarations are provided for
22251 * convenience and illustrative purposes. They should, however, be used with
22252 * caution as the C language standard provides no guarantees about the alignment or
22253 * atomicity of device memory accesses. The recommended practice for writing
22254 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22255 * alt_write_word() functions.
22256 *
22257 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX51.
22258 */
22259 struct ALT_SYSMGR_PINMUX_GPLMUX51_s
22260{
22261 uint32_t sel : 1; /* GPIO/Loan IO51Input Mux Selection Field */
22262 uint32_t : 31; /* *UNDEFINED* */
22263};
22264
22265/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX51. */
22266typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX51_s ALT_SYSMGR_PINMUX_GPLMUX51_t;
22267#endif /* __ASSEMBLY__ */
22268
22269/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX51 register from the beginning of the component. */
22270#define ALT_SYSMGR_PINMUX_GPLMUX51_OFST 0x2a0
22271
22272/*
22273 * Register : GPIO/LoanIO 52 Output/Output Enable Mux Selection Register - GPLMUX52
22274 *
22275 * Selection between GPIO and LoanIO output and output enable for GPIO52 and
22276 * LoanIO52. These signals drive the Pin Mux. The Pin Mux must be configured to use
22277 * GPIO/LoanIO in addition to these settings
22278 *
22279 * Only reset by a cold reset (ignores warm reset).
22280 *
22281 * NOTE: These registers should not be modified after IO configuration.There is no
22282 * support for dynamically changing the Pin Mux selections.
22283 *
22284 * Register Layout
22285 *
22286 * Bits | Access | Reset | Description
22287 * :-------|:-------|:------|:----------------------------------------
22288 * [0] | RW | 0x0 | GPIO/Loan IO52Input Mux Selection Field
22289 * [31:1] | ??? | 0x0 | *UNDEFINED*
22290 *
22291 */
22292/*
22293 * Field : GPIO/Loan IO52Input Mux Selection Field - sel
22294 *
22295 * Select source for GPIO/LoanIO 52.
22296 *
22297 * 0 : LoanIO 52 controls GPIO/LOANIO[52] output and output enable signals.
22298 *
22299 * 1 : GPIO 52 controls GPIO/LOANI[52] output and output enable signals.
22300 *
22301 * Field Access Macros:
22302 *
22303 */
22304/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */
22305#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_LSB 0
22306/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */
22307#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_MSB 0
22308/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */
22309#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_WIDTH 1
22310/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value. */
22311#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET_MSK 0x00000001
22312/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value. */
22313#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_CLR_MSK 0xfffffffe
22314/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */
22315#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_RESET 0x0
22316/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX52_SEL field value from a register. */
22317#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0)
22318/* Produces a ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value suitable for setting the register. */
22319#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET(value) (((value) << 0) & 0x00000001)
22320
22321#ifndef __ASSEMBLY__
22322/*
22323 * WARNING: The C register and register group struct declarations are provided for
22324 * convenience and illustrative purposes. They should, however, be used with
22325 * caution as the C language standard provides no guarantees about the alignment or
22326 * atomicity of device memory accesses. The recommended practice for writing
22327 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22328 * alt_write_word() functions.
22329 *
22330 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX52.
22331 */
22332 struct ALT_SYSMGR_PINMUX_GPLMUX52_s
22333{
22334 uint32_t sel : 1; /* GPIO/Loan IO52Input Mux Selection Field */
22335 uint32_t : 31; /* *UNDEFINED* */
22336};
22337
22338/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX52. */
22339typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX52_s ALT_SYSMGR_PINMUX_GPLMUX52_t;
22340#endif /* __ASSEMBLY__ */
22341
22342/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX52 register from the beginning of the component. */
22343#define ALT_SYSMGR_PINMUX_GPLMUX52_OFST 0x2a4
22344
22345/*
22346 * Register : GPIO/LoanIO 53 Output/Output Enable Mux Selection Register - GPLMUX53
22347 *
22348 * Selection between GPIO and LoanIO output and output enable for GPIO53 and
22349 * LoanIO53. These signals drive the Pin Mux. The Pin Mux must be configured to use
22350 * GPIO/LoanIO in addition to these settings
22351 *
22352 * Only reset by a cold reset (ignores warm reset).
22353 *
22354 * NOTE: These registers should not be modified after IO configuration.There is no
22355 * support for dynamically changing the Pin Mux selections.
22356 *
22357 * Register Layout
22358 *
22359 * Bits | Access | Reset | Description
22360 * :-------|:-------|:------|:----------------------------------------
22361 * [0] | RW | 0x0 | GPIO/Loan IO53Input Mux Selection Field
22362 * [31:1] | ??? | 0x0 | *UNDEFINED*
22363 *
22364 */
22365/*
22366 * Field : GPIO/Loan IO53Input Mux Selection Field - sel
22367 *
22368 * Select source for GPIO/LoanIO 53.
22369 *
22370 * 0 : LoanIO 53 controls GPIO/LOANIO[53] output and output enable signals.
22371 *
22372 * 1 : GPIO 53 controls GPIO/LOANI[53] output and output enable signals.
22373 *
22374 * Field Access Macros:
22375 *
22376 */
22377/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */
22378#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_LSB 0
22379/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */
22380#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_MSB 0
22381/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */
22382#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_WIDTH 1
22383/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value. */
22384#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET_MSK 0x00000001
22385/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value. */
22386#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_CLR_MSK 0xfffffffe
22387/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */
22388#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_RESET 0x0
22389/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX53_SEL field value from a register. */
22390#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0)
22391/* Produces a ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value suitable for setting the register. */
22392#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET(value) (((value) << 0) & 0x00000001)
22393
22394#ifndef __ASSEMBLY__
22395/*
22396 * WARNING: The C register and register group struct declarations are provided for
22397 * convenience and illustrative purposes. They should, however, be used with
22398 * caution as the C language standard provides no guarantees about the alignment or
22399 * atomicity of device memory accesses. The recommended practice for writing
22400 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22401 * alt_write_word() functions.
22402 *
22403 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX53.
22404 */
22405 struct ALT_SYSMGR_PINMUX_GPLMUX53_s
22406{
22407 uint32_t sel : 1; /* GPIO/Loan IO53Input Mux Selection Field */
22408 uint32_t : 31; /* *UNDEFINED* */
22409};
22410
22411/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX53. */
22412typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX53_s ALT_SYSMGR_PINMUX_GPLMUX53_t;
22413#endif /* __ASSEMBLY__ */
22414
22415/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX53 register from the beginning of the component. */
22416#define ALT_SYSMGR_PINMUX_GPLMUX53_OFST 0x2a8
22417
22418/*
22419 * Register : GPIO/LoanIO 54 Output/Output Enable Mux Selection Register - GPLMUX54
22420 *
22421 * Selection between GPIO and LoanIO output and output enable for GPIO54 and
22422 * LoanIO54. These signals drive the Pin Mux. The Pin Mux must be configured to use
22423 * GPIO/LoanIO in addition to these settings
22424 *
22425 * Only reset by a cold reset (ignores warm reset).
22426 *
22427 * NOTE: These registers should not be modified after IO configuration.There is no
22428 * support for dynamically changing the Pin Mux selections.
22429 *
22430 * Register Layout
22431 *
22432 * Bits | Access | Reset | Description
22433 * :-------|:-------|:------|:----------------------------------------
22434 * [0] | RW | 0x0 | GPIO/Loan IO54Input Mux Selection Field
22435 * [31:1] | ??? | 0x0 | *UNDEFINED*
22436 *
22437 */
22438/*
22439 * Field : GPIO/Loan IO54Input Mux Selection Field - sel
22440 *
22441 * Select source for GPIO/LoanIO 54.
22442 *
22443 * 0 : LoanIO 54 controls GPIO/LOANIO[54] output and output enable signals.
22444 *
22445 * 1 : GPIO 54 controls GPIO/LOANI[54] output and output enable signals.
22446 *
22447 * Field Access Macros:
22448 *
22449 */
22450/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */
22451#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_LSB 0
22452/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */
22453#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_MSB 0
22454/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */
22455#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_WIDTH 1
22456/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value. */
22457#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET_MSK 0x00000001
22458/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value. */
22459#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_CLR_MSK 0xfffffffe
22460/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */
22461#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_RESET 0x0
22462/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX54_SEL field value from a register. */
22463#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0)
22464/* Produces a ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value suitable for setting the register. */
22465#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET(value) (((value) << 0) & 0x00000001)
22466
22467#ifndef __ASSEMBLY__
22468/*
22469 * WARNING: The C register and register group struct declarations are provided for
22470 * convenience and illustrative purposes. They should, however, be used with
22471 * caution as the C language standard provides no guarantees about the alignment or
22472 * atomicity of device memory accesses. The recommended practice for writing
22473 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22474 * alt_write_word() functions.
22475 *
22476 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX54.
22477 */
22478 struct ALT_SYSMGR_PINMUX_GPLMUX54_s
22479{
22480 uint32_t sel : 1; /* GPIO/Loan IO54Input Mux Selection Field */
22481 uint32_t : 31; /* *UNDEFINED* */
22482};
22483
22484/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX54. */
22485typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX54_s ALT_SYSMGR_PINMUX_GPLMUX54_t;
22486#endif /* __ASSEMBLY__ */
22487
22488/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX54 register from the beginning of the component. */
22489#define ALT_SYSMGR_PINMUX_GPLMUX54_OFST 0x2ac
22490
22491/*
22492 * Register : GPIO/LoanIO 55 Output/Output Enable Mux Selection Register - GPLMUX55
22493 *
22494 * Selection between GPIO and LoanIO output and output enable for GPIO55 and
22495 * LoanIO55. These signals drive the Pin Mux. The Pin Mux must be configured to use
22496 * GPIO/LoanIO in addition to these settings
22497 *
22498 * Only reset by a cold reset (ignores warm reset).
22499 *
22500 * NOTE: These registers should not be modified after IO configuration.There is no
22501 * support for dynamically changing the Pin Mux selections.
22502 *
22503 * Register Layout
22504 *
22505 * Bits | Access | Reset | Description
22506 * :-------|:-------|:------|:----------------------------------------
22507 * [0] | RW | 0x0 | GPIO/Loan IO55Input Mux Selection Field
22508 * [31:1] | ??? | 0x0 | *UNDEFINED*
22509 *
22510 */
22511/*
22512 * Field : GPIO/Loan IO55Input Mux Selection Field - sel
22513 *
22514 * Select source for GPIO/LoanIO 55.
22515 *
22516 * 0 : LoanIO 55 controls GPIO/LOANIO[55] output and output enable signals.
22517 *
22518 * 1 : GPIO 55 controls GPIO/LOANI[55] output and output enable signals.
22519 *
22520 * Field Access Macros:
22521 *
22522 */
22523/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */
22524#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_LSB 0
22525/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */
22526#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_MSB 0
22527/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */
22528#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_WIDTH 1
22529/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value. */
22530#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET_MSK 0x00000001
22531/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value. */
22532#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_CLR_MSK 0xfffffffe
22533/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */
22534#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_RESET 0x0
22535/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX55_SEL field value from a register. */
22536#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0)
22537/* Produces a ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value suitable for setting the register. */
22538#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET(value) (((value) << 0) & 0x00000001)
22539
22540#ifndef __ASSEMBLY__
22541/*
22542 * WARNING: The C register and register group struct declarations are provided for
22543 * convenience and illustrative purposes. They should, however, be used with
22544 * caution as the C language standard provides no guarantees about the alignment or
22545 * atomicity of device memory accesses. The recommended practice for writing
22546 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22547 * alt_write_word() functions.
22548 *
22549 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX55.
22550 */
22551 struct ALT_SYSMGR_PINMUX_GPLMUX55_s
22552{
22553 uint32_t sel : 1; /* GPIO/Loan IO55Input Mux Selection Field */
22554 uint32_t : 31; /* *UNDEFINED* */
22555};
22556
22557/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX55. */
22558typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX55_s ALT_SYSMGR_PINMUX_GPLMUX55_t;
22559#endif /* __ASSEMBLY__ */
22560
22561/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX55 register from the beginning of the component. */
22562#define ALT_SYSMGR_PINMUX_GPLMUX55_OFST 0x2b0
22563
22564/*
22565 * Register : GPIO/LoanIO 56 Output/Output Enable Mux Selection Register - GPLMUX56
22566 *
22567 * Selection between GPIO and LoanIO output and output enable for GPIO56 and
22568 * LoanIO56. These signals drive the Pin Mux. The Pin Mux must be configured to use
22569 * GPIO/LoanIO in addition to these settings
22570 *
22571 * Only reset by a cold reset (ignores warm reset).
22572 *
22573 * NOTE: These registers should not be modified after IO configuration.There is no
22574 * support for dynamically changing the Pin Mux selections.
22575 *
22576 * Register Layout
22577 *
22578 * Bits | Access | Reset | Description
22579 * :-------|:-------|:------|:----------------------------------------
22580 * [0] | RW | 0x0 | GPIO/Loan IO56Input Mux Selection Field
22581 * [31:1] | ??? | 0x0 | *UNDEFINED*
22582 *
22583 */
22584/*
22585 * Field : GPIO/Loan IO56Input Mux Selection Field - sel
22586 *
22587 * Select source for GPIO/LoanIO 56.
22588 *
22589 * 0 : LoanIO 56 controls GPIO/LOANIO[56] output and output enable signals.
22590 *
22591 * 1 : GPIO 56 controls GPIO/LOANI[56] output and output enable signals.
22592 *
22593 * Field Access Macros:
22594 *
22595 */
22596/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */
22597#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_LSB 0
22598/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */
22599#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_MSB 0
22600/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */
22601#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_WIDTH 1
22602/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value. */
22603#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET_MSK 0x00000001
22604/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value. */
22605#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_CLR_MSK 0xfffffffe
22606/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */
22607#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_RESET 0x0
22608/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX56_SEL field value from a register. */
22609#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0)
22610/* Produces a ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value suitable for setting the register. */
22611#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET(value) (((value) << 0) & 0x00000001)
22612
22613#ifndef __ASSEMBLY__
22614/*
22615 * WARNING: The C register and register group struct declarations are provided for
22616 * convenience and illustrative purposes. They should, however, be used with
22617 * caution as the C language standard provides no guarantees about the alignment or
22618 * atomicity of device memory accesses. The recommended practice for writing
22619 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22620 * alt_write_word() functions.
22621 *
22622 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX56.
22623 */
22624 struct ALT_SYSMGR_PINMUX_GPLMUX56_s
22625{
22626 uint32_t sel : 1; /* GPIO/Loan IO56Input Mux Selection Field */
22627 uint32_t : 31; /* *UNDEFINED* */
22628};
22629
22630/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX56. */
22631typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX56_s ALT_SYSMGR_PINMUX_GPLMUX56_t;
22632#endif /* __ASSEMBLY__ */
22633
22634/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX56 register from the beginning of the component. */
22635#define ALT_SYSMGR_PINMUX_GPLMUX56_OFST 0x2b4
22636
22637/*
22638 * Register : GPIO/LoanIO 57 Output/Output Enable Mux Selection Register - GPLMUX57
22639 *
22640 * Selection between GPIO and LoanIO output and output enable for GPIO57 and
22641 * LoanIO57. These signals drive the Pin Mux. The Pin Mux must be configured to use
22642 * GPIO/LoanIO in addition to these settings
22643 *
22644 * Only reset by a cold reset (ignores warm reset).
22645 *
22646 * NOTE: These registers should not be modified after IO configuration.There is no
22647 * support for dynamically changing the Pin Mux selections.
22648 *
22649 * Register Layout
22650 *
22651 * Bits | Access | Reset | Description
22652 * :-------|:-------|:------|:----------------------------------------
22653 * [0] | RW | 0x0 | GPIO/Loan IO57Input Mux Selection Field
22654 * [31:1] | ??? | 0x0 | *UNDEFINED*
22655 *
22656 */
22657/*
22658 * Field : GPIO/Loan IO57Input Mux Selection Field - sel
22659 *
22660 * Select source for GPIO/LoanIO 57.
22661 *
22662 * 0 : LoanIO 57 controls GPIO/LOANIO[57] output and output enable signals.
22663 *
22664 * 1 : GPIO 57 controls GPIO/LOANI[57] output and output enable signals.
22665 *
22666 * Field Access Macros:
22667 *
22668 */
22669/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */
22670#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_LSB 0
22671/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */
22672#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_MSB 0
22673/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */
22674#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_WIDTH 1
22675/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value. */
22676#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET_MSK 0x00000001
22677/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value. */
22678#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_CLR_MSK 0xfffffffe
22679/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */
22680#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_RESET 0x0
22681/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX57_SEL field value from a register. */
22682#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0)
22683/* Produces a ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value suitable for setting the register. */
22684#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET(value) (((value) << 0) & 0x00000001)
22685
22686#ifndef __ASSEMBLY__
22687/*
22688 * WARNING: The C register and register group struct declarations are provided for
22689 * convenience and illustrative purposes. They should, however, be used with
22690 * caution as the C language standard provides no guarantees about the alignment or
22691 * atomicity of device memory accesses. The recommended practice for writing
22692 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22693 * alt_write_word() functions.
22694 *
22695 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX57.
22696 */
22697 struct ALT_SYSMGR_PINMUX_GPLMUX57_s
22698{
22699 uint32_t sel : 1; /* GPIO/Loan IO57Input Mux Selection Field */
22700 uint32_t : 31; /* *UNDEFINED* */
22701};
22702
22703/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX57. */
22704typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX57_s ALT_SYSMGR_PINMUX_GPLMUX57_t;
22705#endif /* __ASSEMBLY__ */
22706
22707/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX57 register from the beginning of the component. */
22708#define ALT_SYSMGR_PINMUX_GPLMUX57_OFST 0x2b8
22709
22710/*
22711 * Register : GPIO/LoanIO 58 Output/Output Enable Mux Selection Register - GPLMUX58
22712 *
22713 * Selection between GPIO and LoanIO output and output enable for GPIO58 and
22714 * LoanIO58. These signals drive the Pin Mux. The Pin Mux must be configured to use
22715 * GPIO/LoanIO in addition to these settings
22716 *
22717 * Only reset by a cold reset (ignores warm reset).
22718 *
22719 * NOTE: These registers should not be modified after IO configuration.There is no
22720 * support for dynamically changing the Pin Mux selections.
22721 *
22722 * Register Layout
22723 *
22724 * Bits | Access | Reset | Description
22725 * :-------|:-------|:------|:----------------------------------------
22726 * [0] | RW | 0x0 | GPIO/Loan IO58Input Mux Selection Field
22727 * [31:1] | ??? | 0x0 | *UNDEFINED*
22728 *
22729 */
22730/*
22731 * Field : GPIO/Loan IO58Input Mux Selection Field - sel
22732 *
22733 * Select source for GPIO/LoanIO 58.
22734 *
22735 * 0 : LoanIO 58 controls GPIO/LOANIO[58] output and output enable signals.
22736 *
22737 * 1 : GPIO 58 controls GPIO/LOANI[58] output and output enable signals.
22738 *
22739 * Field Access Macros:
22740 *
22741 */
22742/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */
22743#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_LSB 0
22744/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */
22745#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_MSB 0
22746/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */
22747#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_WIDTH 1
22748/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value. */
22749#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET_MSK 0x00000001
22750/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value. */
22751#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_CLR_MSK 0xfffffffe
22752/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */
22753#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_RESET 0x0
22754/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX58_SEL field value from a register. */
22755#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0)
22756/* Produces a ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value suitable for setting the register. */
22757#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET(value) (((value) << 0) & 0x00000001)
22758
22759#ifndef __ASSEMBLY__
22760/*
22761 * WARNING: The C register and register group struct declarations are provided for
22762 * convenience and illustrative purposes. They should, however, be used with
22763 * caution as the C language standard provides no guarantees about the alignment or
22764 * atomicity of device memory accesses. The recommended practice for writing
22765 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22766 * alt_write_word() functions.
22767 *
22768 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX58.
22769 */
22770 struct ALT_SYSMGR_PINMUX_GPLMUX58_s
22771{
22772 uint32_t sel : 1; /* GPIO/Loan IO58Input Mux Selection Field */
22773 uint32_t : 31; /* *UNDEFINED* */
22774};
22775
22776/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX58. */
22777typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX58_s ALT_SYSMGR_PINMUX_GPLMUX58_t;
22778#endif /* __ASSEMBLY__ */
22779
22780/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX58 register from the beginning of the component. */
22781#define ALT_SYSMGR_PINMUX_GPLMUX58_OFST 0x2bc
22782
22783/*
22784 * Register : GPIO/LoanIO 59 Output/Output Enable Mux Selection Register - GPLMUX59
22785 *
22786 * Selection between GPIO and LoanIO output and output enable for GPIO59 and
22787 * LoanIO59. These signals drive the Pin Mux. The Pin Mux must be configured to use
22788 * GPIO/LoanIO in addition to these settings
22789 *
22790 * Only reset by a cold reset (ignores warm reset).
22791 *
22792 * NOTE: These registers should not be modified after IO configuration.There is no
22793 * support for dynamically changing the Pin Mux selections.
22794 *
22795 * Register Layout
22796 *
22797 * Bits | Access | Reset | Description
22798 * :-------|:-------|:------|:----------------------------------------
22799 * [0] | RW | 0x0 | GPIO/Loan IO59Input Mux Selection Field
22800 * [31:1] | ??? | 0x0 | *UNDEFINED*
22801 *
22802 */
22803/*
22804 * Field : GPIO/Loan IO59Input Mux Selection Field - sel
22805 *
22806 * Select source for GPIO/LoanIO 59.
22807 *
22808 * 0 : LoanIO 59 controls GPIO/LOANIO[59] output and output enable signals.
22809 *
22810 * 1 : GPIO 59 controls GPIO/LOANI[59] output and output enable signals.
22811 *
22812 * Field Access Macros:
22813 *
22814 */
22815/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */
22816#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_LSB 0
22817/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */
22818#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_MSB 0
22819/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */
22820#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_WIDTH 1
22821/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value. */
22822#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET_MSK 0x00000001
22823/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value. */
22824#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_CLR_MSK 0xfffffffe
22825/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */
22826#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_RESET 0x0
22827/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX59_SEL field value from a register. */
22828#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0)
22829/* Produces a ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value suitable for setting the register. */
22830#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET(value) (((value) << 0) & 0x00000001)
22831
22832#ifndef __ASSEMBLY__
22833/*
22834 * WARNING: The C register and register group struct declarations are provided for
22835 * convenience and illustrative purposes. They should, however, be used with
22836 * caution as the C language standard provides no guarantees about the alignment or
22837 * atomicity of device memory accesses. The recommended practice for writing
22838 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22839 * alt_write_word() functions.
22840 *
22841 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX59.
22842 */
22843 struct ALT_SYSMGR_PINMUX_GPLMUX59_s
22844{
22845 uint32_t sel : 1; /* GPIO/Loan IO59Input Mux Selection Field */
22846 uint32_t : 31; /* *UNDEFINED* */
22847};
22848
22849/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX59. */
22850typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX59_s ALT_SYSMGR_PINMUX_GPLMUX59_t;
22851#endif /* __ASSEMBLY__ */
22852
22853/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX59 register from the beginning of the component. */
22854#define ALT_SYSMGR_PINMUX_GPLMUX59_OFST 0x2c0
22855
22856/*
22857 * Register : GPIO/LoanIO 60 Output/Output Enable Mux Selection Register - GPLMUX60
22858 *
22859 * Selection between GPIO and LoanIO output and output enable for GPIO60 and
22860 * LoanIO60. These signals drive the Pin Mux. The Pin Mux must be configured to use
22861 * GPIO/LoanIO in addition to these settings
22862 *
22863 * Only reset by a cold reset (ignores warm reset).
22864 *
22865 * NOTE: These registers should not be modified after IO configuration.There is no
22866 * support for dynamically changing the Pin Mux selections.
22867 *
22868 * Register Layout
22869 *
22870 * Bits | Access | Reset | Description
22871 * :-------|:-------|:------|:----------------------------------------
22872 * [0] | RW | 0x0 | GPIO/Loan IO60Input Mux Selection Field
22873 * [31:1] | ??? | 0x0 | *UNDEFINED*
22874 *
22875 */
22876/*
22877 * Field : GPIO/Loan IO60Input Mux Selection Field - sel
22878 *
22879 * Select source for GPIO/LoanIO 60.
22880 *
22881 * 0 : LoanIO 60 controls GPIO/LOANIO[60] output and output enable signals.
22882 *
22883 * 1 : GPIO 60 controls GPIO/LOANI[60] output and output enable signals.
22884 *
22885 * Field Access Macros:
22886 *
22887 */
22888/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */
22889#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_LSB 0
22890/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */
22891#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_MSB 0
22892/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */
22893#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_WIDTH 1
22894/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value. */
22895#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET_MSK 0x00000001
22896/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value. */
22897#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_CLR_MSK 0xfffffffe
22898/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */
22899#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_RESET 0x0
22900/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX60_SEL field value from a register. */
22901#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0)
22902/* Produces a ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value suitable for setting the register. */
22903#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET(value) (((value) << 0) & 0x00000001)
22904
22905#ifndef __ASSEMBLY__
22906/*
22907 * WARNING: The C register and register group struct declarations are provided for
22908 * convenience and illustrative purposes. They should, however, be used with
22909 * caution as the C language standard provides no guarantees about the alignment or
22910 * atomicity of device memory accesses. The recommended practice for writing
22911 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22912 * alt_write_word() functions.
22913 *
22914 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX60.
22915 */
22916 struct ALT_SYSMGR_PINMUX_GPLMUX60_s
22917{
22918 uint32_t sel : 1; /* GPIO/Loan IO60Input Mux Selection Field */
22919 uint32_t : 31; /* *UNDEFINED* */
22920};
22921
22922/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX60. */
22923typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX60_s ALT_SYSMGR_PINMUX_GPLMUX60_t;
22924#endif /* __ASSEMBLY__ */
22925
22926/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX60 register from the beginning of the component. */
22927#define ALT_SYSMGR_PINMUX_GPLMUX60_OFST 0x2c4
22928
22929/*
22930 * Register : GPIO/LoanIO 61 Output/Output Enable Mux Selection Register - GPLMUX61
22931 *
22932 * Selection between GPIO and LoanIO output and output enable for GPIO61 and
22933 * LoanIO61. These signals drive the Pin Mux. The Pin Mux must be configured to use
22934 * GPIO/LoanIO in addition to these settings
22935 *
22936 * Only reset by a cold reset (ignores warm reset).
22937 *
22938 * NOTE: These registers should not be modified after IO configuration.There is no
22939 * support for dynamically changing the Pin Mux selections.
22940 *
22941 * Register Layout
22942 *
22943 * Bits | Access | Reset | Description
22944 * :-------|:-------|:------|:----------------------------------------
22945 * [0] | RW | 0x0 | GPIO/Loan IO61Input Mux Selection Field
22946 * [31:1] | ??? | 0x0 | *UNDEFINED*
22947 *
22948 */
22949/*
22950 * Field : GPIO/Loan IO61Input Mux Selection Field - sel
22951 *
22952 * Select source for GPIO/LoanIO 61.
22953 *
22954 * 0 : LoanIO 61 controls GPIO/LOANIO[61] output and output enable signals.
22955 *
22956 * 1 : GPIO 61 controls GPIO/LOANI[61] output and output enable signals.
22957 *
22958 * Field Access Macros:
22959 *
22960 */
22961/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */
22962#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_LSB 0
22963/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */
22964#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_MSB 0
22965/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */
22966#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_WIDTH 1
22967/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value. */
22968#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET_MSK 0x00000001
22969/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value. */
22970#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_CLR_MSK 0xfffffffe
22971/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */
22972#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_RESET 0x0
22973/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX61_SEL field value from a register. */
22974#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0)
22975/* Produces a ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value suitable for setting the register. */
22976#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET(value) (((value) << 0) & 0x00000001)
22977
22978#ifndef __ASSEMBLY__
22979/*
22980 * WARNING: The C register and register group struct declarations are provided for
22981 * convenience and illustrative purposes. They should, however, be used with
22982 * caution as the C language standard provides no guarantees about the alignment or
22983 * atomicity of device memory accesses. The recommended practice for writing
22984 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22985 * alt_write_word() functions.
22986 *
22987 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX61.
22988 */
22989 struct ALT_SYSMGR_PINMUX_GPLMUX61_s
22990{
22991 uint32_t sel : 1; /* GPIO/Loan IO61Input Mux Selection Field */
22992 uint32_t : 31; /* *UNDEFINED* */
22993};
22994
22995/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX61. */
22996typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX61_s ALT_SYSMGR_PINMUX_GPLMUX61_t;
22997#endif /* __ASSEMBLY__ */
22998
22999/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX61 register from the beginning of the component. */
23000#define ALT_SYSMGR_PINMUX_GPLMUX61_OFST 0x2c8
23001
23002/*
23003 * Register : GPIO/LoanIO 62 Output/Output Enable Mux Selection Register - GPLMUX62
23004 *
23005 * Selection between GPIO and LoanIO output and output enable for GPIO62 and
23006 * LoanIO62. These signals drive the Pin Mux. The Pin Mux must be configured to use
23007 * GPIO/LoanIO in addition to these settings
23008 *
23009 * Only reset by a cold reset (ignores warm reset).
23010 *
23011 * NOTE: These registers should not be modified after IO configuration.There is no
23012 * support for dynamically changing the Pin Mux selections.
23013 *
23014 * Register Layout
23015 *
23016 * Bits | Access | Reset | Description
23017 * :-------|:-------|:------|:----------------------------------------
23018 * [0] | RW | 0x0 | GPIO/Loan IO62Input Mux Selection Field
23019 * [31:1] | ??? | 0x0 | *UNDEFINED*
23020 *
23021 */
23022/*
23023 * Field : GPIO/Loan IO62Input Mux Selection Field - sel
23024 *
23025 * Select source for GPIO/LoanIO 62.
23026 *
23027 * 0 : LoanIO 62 controls GPIO/LOANIO[62] output and output enable signals.
23028 *
23029 * 1 : GPIO 62 controls GPIO/LOANI[62] output and output enable signals.
23030 *
23031 * Field Access Macros:
23032 *
23033 */
23034/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */
23035#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_LSB 0
23036/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */
23037#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_MSB 0
23038/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */
23039#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_WIDTH 1
23040/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value. */
23041#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET_MSK 0x00000001
23042/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value. */
23043#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_CLR_MSK 0xfffffffe
23044/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */
23045#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_RESET 0x0
23046/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX62_SEL field value from a register. */
23047#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0)
23048/* Produces a ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value suitable for setting the register. */
23049#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET(value) (((value) << 0) & 0x00000001)
23050
23051#ifndef __ASSEMBLY__
23052/*
23053 * WARNING: The C register and register group struct declarations are provided for
23054 * convenience and illustrative purposes. They should, however, be used with
23055 * caution as the C language standard provides no guarantees about the alignment or
23056 * atomicity of device memory accesses. The recommended practice for writing
23057 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23058 * alt_write_word() functions.
23059 *
23060 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX62.
23061 */
23062 struct ALT_SYSMGR_PINMUX_GPLMUX62_s
23063{
23064 uint32_t sel : 1; /* GPIO/Loan IO62Input Mux Selection Field */
23065 uint32_t : 31; /* *UNDEFINED* */
23066};
23067
23068/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX62. */
23069typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX62_s ALT_SYSMGR_PINMUX_GPLMUX62_t;
23070#endif /* __ASSEMBLY__ */
23071
23072/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX62 register from the beginning of the component. */
23073#define ALT_SYSMGR_PINMUX_GPLMUX62_OFST 0x2cc
23074
23075/*
23076 * Register : GPIO/LoanIO 63 Output/Output Enable Mux Selection Register - GPLMUX63
23077 *
23078 * Selection between GPIO and LoanIO output and output enable for GPIO63 and
23079 * LoanIO63. These signals drive the Pin Mux. The Pin Mux must be configured to use
23080 * GPIO/LoanIO in addition to these settings
23081 *
23082 * Only reset by a cold reset (ignores warm reset).
23083 *
23084 * NOTE: These registers should not be modified after IO configuration.There is no
23085 * support for dynamically changing the Pin Mux selections.
23086 *
23087 * Register Layout
23088 *
23089 * Bits | Access | Reset | Description
23090 * :-------|:-------|:------|:----------------------------------------
23091 * [0] | RW | 0x0 | GPIO/Loan IO63Input Mux Selection Field
23092 * [31:1] | ??? | 0x0 | *UNDEFINED*
23093 *
23094 */
23095/*
23096 * Field : GPIO/Loan IO63Input Mux Selection Field - sel
23097 *
23098 * Select source for GPIO/LoanIO 63.
23099 *
23100 * 0 : LoanIO 63 controls GPIO/LOANIO[63] output and output enable signals.
23101 *
23102 * 1 : GPIO 63 controls GPIO/LOANI[63] output and output enable signals.
23103 *
23104 * Field Access Macros:
23105 *
23106 */
23107/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */
23108#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_LSB 0
23109/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */
23110#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_MSB 0
23111/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */
23112#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_WIDTH 1
23113/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value. */
23114#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET_MSK 0x00000001
23115/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value. */
23116#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_CLR_MSK 0xfffffffe
23117/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */
23118#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_RESET 0x0
23119/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX63_SEL field value from a register. */
23120#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0)
23121/* Produces a ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value suitable for setting the register. */
23122#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET(value) (((value) << 0) & 0x00000001)
23123
23124#ifndef __ASSEMBLY__
23125/*
23126 * WARNING: The C register and register group struct declarations are provided for
23127 * convenience and illustrative purposes. They should, however, be used with
23128 * caution as the C language standard provides no guarantees about the alignment or
23129 * atomicity of device memory accesses. The recommended practice for writing
23130 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23131 * alt_write_word() functions.
23132 *
23133 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX63.
23134 */
23135 struct ALT_SYSMGR_PINMUX_GPLMUX63_s
23136{
23137 uint32_t sel : 1; /* GPIO/Loan IO63Input Mux Selection Field */
23138 uint32_t : 31; /* *UNDEFINED* */
23139};
23140
23141/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX63. */
23142typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX63_s ALT_SYSMGR_PINMUX_GPLMUX63_t;
23143#endif /* __ASSEMBLY__ */
23144
23145/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX63 register from the beginning of the component. */
23146#define ALT_SYSMGR_PINMUX_GPLMUX63_OFST 0x2d0
23147
23148/*
23149 * Register : GPIO/LoanIO 64 Output/Output Enable Mux Selection Register - GPLMUX64
23150 *
23151 * Selection between GPIO and LoanIO output and output enable for GPIO64 and
23152 * LoanIO64. These signals drive the Pin Mux. The Pin Mux must be configured to use
23153 * GPIO/LoanIO in addition to these settings
23154 *
23155 * Only reset by a cold reset (ignores warm reset).
23156 *
23157 * NOTE: These registers should not be modified after IO configuration.There is no
23158 * support for dynamically changing the Pin Mux selections.
23159 *
23160 * Register Layout
23161 *
23162 * Bits | Access | Reset | Description
23163 * :-------|:-------|:------|:----------------------------------------
23164 * [0] | RW | 0x0 | GPIO/Loan IO64Input Mux Selection Field
23165 * [31:1] | ??? | 0x0 | *UNDEFINED*
23166 *
23167 */
23168/*
23169 * Field : GPIO/Loan IO64Input Mux Selection Field - sel
23170 *
23171 * Select source for GPIO/LoanIO 64.
23172 *
23173 * 0 : LoanIO 64 controls GPIO/LOANIO[64] output and output enable signals.
23174 *
23175 * 1 : GPIO 64 controls GPIO/LOANI[64] output and output enable signals.
23176 *
23177 * Field Access Macros:
23178 *
23179 */
23180/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */
23181#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_LSB 0
23182/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */
23183#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_MSB 0
23184/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */
23185#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_WIDTH 1
23186/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value. */
23187#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET_MSK 0x00000001
23188/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value. */
23189#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_CLR_MSK 0xfffffffe
23190/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */
23191#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_RESET 0x0
23192/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX64_SEL field value from a register. */
23193#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0)
23194/* Produces a ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value suitable for setting the register. */
23195#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET(value) (((value) << 0) & 0x00000001)
23196
23197#ifndef __ASSEMBLY__
23198/*
23199 * WARNING: The C register and register group struct declarations are provided for
23200 * convenience and illustrative purposes. They should, however, be used with
23201 * caution as the C language standard provides no guarantees about the alignment or
23202 * atomicity of device memory accesses. The recommended practice for writing
23203 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23204 * alt_write_word() functions.
23205 *
23206 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX64.
23207 */
23208 struct ALT_SYSMGR_PINMUX_GPLMUX64_s
23209{
23210 uint32_t sel : 1; /* GPIO/Loan IO64Input Mux Selection Field */
23211 uint32_t : 31; /* *UNDEFINED* */
23212};
23213
23214/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX64. */
23215typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX64_s ALT_SYSMGR_PINMUX_GPLMUX64_t;
23216#endif /* __ASSEMBLY__ */
23217
23218/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX64 register from the beginning of the component. */
23219#define ALT_SYSMGR_PINMUX_GPLMUX64_OFST 0x2d4
23220
23221/*
23222 * Register : GPIO/LoanIO 65 Output/Output Enable Mux Selection Register - GPLMUX65
23223 *
23224 * Selection between GPIO and LoanIO output and output enable for GPIO65 and
23225 * LoanIO65. These signals drive the Pin Mux. The Pin Mux must be configured to use
23226 * GPIO/LoanIO in addition to these settings
23227 *
23228 * Only reset by a cold reset (ignores warm reset).
23229 *
23230 * NOTE: These registers should not be modified after IO configuration.There is no
23231 * support for dynamically changing the Pin Mux selections.
23232 *
23233 * Register Layout
23234 *
23235 * Bits | Access | Reset | Description
23236 * :-------|:-------|:------|:----------------------------------------
23237 * [0] | RW | 0x0 | GPIO/Loan IO65Input Mux Selection Field
23238 * [31:1] | ??? | 0x0 | *UNDEFINED*
23239 *
23240 */
23241/*
23242 * Field : GPIO/Loan IO65Input Mux Selection Field - sel
23243 *
23244 * Select source for GPIO/LoanIO 65.
23245 *
23246 * 0 : LoanIO 65 controls GPIO/LOANIO[65] output and output enable signals.
23247 *
23248 * 1 : GPIO 65 controls GPIO/LOANI[65] output and output enable signals.
23249 *
23250 * Field Access Macros:
23251 *
23252 */
23253/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */
23254#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_LSB 0
23255/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */
23256#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_MSB 0
23257/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */
23258#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_WIDTH 1
23259/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value. */
23260#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET_MSK 0x00000001
23261/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value. */
23262#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_CLR_MSK 0xfffffffe
23263/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */
23264#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_RESET 0x0
23265/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX65_SEL field value from a register. */
23266#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0)
23267/* Produces a ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value suitable for setting the register. */
23268#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET(value) (((value) << 0) & 0x00000001)
23269
23270#ifndef __ASSEMBLY__
23271/*
23272 * WARNING: The C register and register group struct declarations are provided for
23273 * convenience and illustrative purposes. They should, however, be used with
23274 * caution as the C language standard provides no guarantees about the alignment or
23275 * atomicity of device memory accesses. The recommended practice for writing
23276 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23277 * alt_write_word() functions.
23278 *
23279 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX65.
23280 */
23281 struct ALT_SYSMGR_PINMUX_GPLMUX65_s
23282{
23283 uint32_t sel : 1; /* GPIO/Loan IO65Input Mux Selection Field */
23284 uint32_t : 31; /* *UNDEFINED* */
23285};
23286
23287/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX65. */
23288typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX65_s ALT_SYSMGR_PINMUX_GPLMUX65_t;
23289#endif /* __ASSEMBLY__ */
23290
23291/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX65 register from the beginning of the component. */
23292#define ALT_SYSMGR_PINMUX_GPLMUX65_OFST 0x2d8
23293
23294/*
23295 * Register : GPIO/LoanIO 66 Output/Output Enable Mux Selection Register - GPLMUX66
23296 *
23297 * Selection between GPIO and LoanIO output and output enable for GPIO66 and
23298 * LoanIO66. These signals drive the Pin Mux. The Pin Mux must be configured to use
23299 * GPIO/LoanIO in addition to these settings
23300 *
23301 * Only reset by a cold reset (ignores warm reset).
23302 *
23303 * NOTE: These registers should not be modified after IO configuration.There is no
23304 * support for dynamically changing the Pin Mux selections.
23305 *
23306 * Register Layout
23307 *
23308 * Bits | Access | Reset | Description
23309 * :-------|:-------|:------|:----------------------------------------
23310 * [0] | RW | 0x0 | GPIO/Loan IO66Input Mux Selection Field
23311 * [31:1] | ??? | 0x0 | *UNDEFINED*
23312 *
23313 */
23314/*
23315 * Field : GPIO/Loan IO66Input Mux Selection Field - sel
23316 *
23317 * Select source for GPIO/LoanIO 66.
23318 *
23319 * 0 : LoanIO 66 controls GPIO/LOANIO[66] output and output enable signals.
23320 *
23321 * 1 : GPIO 66 controls GPIO/LOANI[66] output and output enable signals.
23322 *
23323 * Field Access Macros:
23324 *
23325 */
23326/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */
23327#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_LSB 0
23328/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */
23329#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_MSB 0
23330/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */
23331#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_WIDTH 1
23332/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value. */
23333#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET_MSK 0x00000001
23334/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value. */
23335#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_CLR_MSK 0xfffffffe
23336/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */
23337#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_RESET 0x0
23338/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX66_SEL field value from a register. */
23339#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0)
23340/* Produces a ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value suitable for setting the register. */
23341#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET(value) (((value) << 0) & 0x00000001)
23342
23343#ifndef __ASSEMBLY__
23344/*
23345 * WARNING: The C register and register group struct declarations are provided for
23346 * convenience and illustrative purposes. They should, however, be used with
23347 * caution as the C language standard provides no guarantees about the alignment or
23348 * atomicity of device memory accesses. The recommended practice for writing
23349 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23350 * alt_write_word() functions.
23351 *
23352 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX66.
23353 */
23354 struct ALT_SYSMGR_PINMUX_GPLMUX66_s
23355{
23356 uint32_t sel : 1; /* GPIO/Loan IO66Input Mux Selection Field */
23357 uint32_t : 31; /* *UNDEFINED* */
23358};
23359
23360/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX66. */
23361typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX66_s ALT_SYSMGR_PINMUX_GPLMUX66_t;
23362#endif /* __ASSEMBLY__ */
23363
23364/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX66 register from the beginning of the component. */
23365#define ALT_SYSMGR_PINMUX_GPLMUX66_OFST 0x2dc
23366
23367/*
23368 * Register : GPIO/LoanIO 67 Output/Output Enable Mux Selection Register - GPLMUX67
23369 *
23370 * Selection between GPIO and LoanIO output and output enable for GPIO67 and
23371 * LoanIO67. These signals drive the Pin Mux. The Pin Mux must be configured to use
23372 * GPIO/LoanIO in addition to these settings
23373 *
23374 * Only reset by a cold reset (ignores warm reset).
23375 *
23376 * NOTE: These registers should not be modified after IO configuration.There is no
23377 * support for dynamically changing the Pin Mux selections.
23378 *
23379 * Register Layout
23380 *
23381 * Bits | Access | Reset | Description
23382 * :-------|:-------|:------|:----------------------------------------
23383 * [0] | RW | 0x0 | GPIO/Loan IO67Input Mux Selection Field
23384 * [31:1] | ??? | 0x0 | *UNDEFINED*
23385 *
23386 */
23387/*
23388 * Field : GPIO/Loan IO67Input Mux Selection Field - sel
23389 *
23390 * Select source for GPIO/LoanIO 67.
23391 *
23392 * 0 : LoanIO 67 controls GPIO/LOANIO[67] output and output enable signals.
23393 *
23394 * 1 : GPIO 67 controls GPIO/LOANI[67] output and output enable signals.
23395 *
23396 * Field Access Macros:
23397 *
23398 */
23399/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */
23400#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_LSB 0
23401/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */
23402#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_MSB 0
23403/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */
23404#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_WIDTH 1
23405/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value. */
23406#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET_MSK 0x00000001
23407/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value. */
23408#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_CLR_MSK 0xfffffffe
23409/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */
23410#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_RESET 0x0
23411/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX67_SEL field value from a register. */
23412#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0)
23413/* Produces a ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value suitable for setting the register. */
23414#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET(value) (((value) << 0) & 0x00000001)
23415
23416#ifndef __ASSEMBLY__
23417/*
23418 * WARNING: The C register and register group struct declarations are provided for
23419 * convenience and illustrative purposes. They should, however, be used with
23420 * caution as the C language standard provides no guarantees about the alignment or
23421 * atomicity of device memory accesses. The recommended practice for writing
23422 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23423 * alt_write_word() functions.
23424 *
23425 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX67.
23426 */
23427 struct ALT_SYSMGR_PINMUX_GPLMUX67_s
23428{
23429 uint32_t sel : 1; /* GPIO/Loan IO67Input Mux Selection Field */
23430 uint32_t : 31; /* *UNDEFINED* */
23431};
23432
23433/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX67. */
23434typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX67_s ALT_SYSMGR_PINMUX_GPLMUX67_t;
23435#endif /* __ASSEMBLY__ */
23436
23437/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX67 register from the beginning of the component. */
23438#define ALT_SYSMGR_PINMUX_GPLMUX67_OFST 0x2e0
23439
23440/*
23441 * Register : GPIO/LoanIO 68 Output/Output Enable Mux Selection Register - GPLMUX68
23442 *
23443 * Selection between GPIO and LoanIO output and output enable for GPIO68 and
23444 * LoanIO68. These signals drive the Pin Mux. The Pin Mux must be configured to use
23445 * GPIO/LoanIO in addition to these settings
23446 *
23447 * Only reset by a cold reset (ignores warm reset).
23448 *
23449 * NOTE: These registers should not be modified after IO configuration.There is no
23450 * support for dynamically changing the Pin Mux selections.
23451 *
23452 * Register Layout
23453 *
23454 * Bits | Access | Reset | Description
23455 * :-------|:-------|:------|:----------------------------------------
23456 * [0] | RW | 0x0 | GPIO/Loan IO68Input Mux Selection Field
23457 * [31:1] | ??? | 0x0 | *UNDEFINED*
23458 *
23459 */
23460/*
23461 * Field : GPIO/Loan IO68Input Mux Selection Field - sel
23462 *
23463 * Select source for GPIO/LoanIO 68.
23464 *
23465 * 0 : LoanIO 68 controls GPIO/LOANIO[68] output and output enable signals.
23466 *
23467 * 1 : GPIO 68 controls GPIO/LOANI[68] output and output enable signals.
23468 *
23469 * Field Access Macros:
23470 *
23471 */
23472/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */
23473#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_LSB 0
23474/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */
23475#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_MSB 0
23476/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */
23477#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_WIDTH 1
23478/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value. */
23479#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET_MSK 0x00000001
23480/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value. */
23481#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_CLR_MSK 0xfffffffe
23482/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */
23483#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_RESET 0x0
23484/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX68_SEL field value from a register. */
23485#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0)
23486/* Produces a ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value suitable for setting the register. */
23487#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET(value) (((value) << 0) & 0x00000001)
23488
23489#ifndef __ASSEMBLY__
23490/*
23491 * WARNING: The C register and register group struct declarations are provided for
23492 * convenience and illustrative purposes. They should, however, be used with
23493 * caution as the C language standard provides no guarantees about the alignment or
23494 * atomicity of device memory accesses. The recommended practice for writing
23495 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23496 * alt_write_word() functions.
23497 *
23498 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX68.
23499 */
23500 struct ALT_SYSMGR_PINMUX_GPLMUX68_s
23501{
23502 uint32_t sel : 1; /* GPIO/Loan IO68Input Mux Selection Field */
23503 uint32_t : 31; /* *UNDEFINED* */
23504};
23505
23506/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX68. */
23507typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX68_s ALT_SYSMGR_PINMUX_GPLMUX68_t;
23508#endif /* __ASSEMBLY__ */
23509
23510/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX68 register from the beginning of the component. */
23511#define ALT_SYSMGR_PINMUX_GPLMUX68_OFST 0x2e4
23512
23513/*
23514 * Register : GPIO/LoanIO 69 Output/Output Enable Mux Selection Register - GPLMUX69
23515 *
23516 * Selection between GPIO and LoanIO output and output enable for GPIO69 and
23517 * LoanIO69. These signals drive the Pin Mux. The Pin Mux must be configured to use
23518 * GPIO/LoanIO in addition to these settings
23519 *
23520 * Only reset by a cold reset (ignores warm reset).
23521 *
23522 * NOTE: These registers should not be modified after IO configuration.There is no
23523 * support for dynamically changing the Pin Mux selections.
23524 *
23525 * Register Layout
23526 *
23527 * Bits | Access | Reset | Description
23528 * :-------|:-------|:------|:----------------------------------------
23529 * [0] | RW | 0x0 | GPIO/Loan IO69Input Mux Selection Field
23530 * [31:1] | ??? | 0x0 | *UNDEFINED*
23531 *
23532 */
23533/*
23534 * Field : GPIO/Loan IO69Input Mux Selection Field - sel
23535 *
23536 * Select source for GPIO/LoanIO 69.
23537 *
23538 * 0 : LoanIO 69 controls GPIO/LOANIO[69] output and output enable signals.
23539 *
23540 * 1 : GPIO 69 controls GPIO/LOANI[69] output and output enable signals.
23541 *
23542 * Field Access Macros:
23543 *
23544 */
23545/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */
23546#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_LSB 0
23547/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */
23548#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_MSB 0
23549/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */
23550#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_WIDTH 1
23551/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value. */
23552#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET_MSK 0x00000001
23553/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value. */
23554#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_CLR_MSK 0xfffffffe
23555/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */
23556#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_RESET 0x0
23557/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX69_SEL field value from a register. */
23558#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0)
23559/* Produces a ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value suitable for setting the register. */
23560#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET(value) (((value) << 0) & 0x00000001)
23561
23562#ifndef __ASSEMBLY__
23563/*
23564 * WARNING: The C register and register group struct declarations are provided for
23565 * convenience and illustrative purposes. They should, however, be used with
23566 * caution as the C language standard provides no guarantees about the alignment or
23567 * atomicity of device memory accesses. The recommended practice for writing
23568 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23569 * alt_write_word() functions.
23570 *
23571 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX69.
23572 */
23573 struct ALT_SYSMGR_PINMUX_GPLMUX69_s
23574{
23575 uint32_t sel : 1; /* GPIO/Loan IO69Input Mux Selection Field */
23576 uint32_t : 31; /* *UNDEFINED* */
23577};
23578
23579/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX69. */
23580typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX69_s ALT_SYSMGR_PINMUX_GPLMUX69_t;
23581#endif /* __ASSEMBLY__ */
23582
23583/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX69 register from the beginning of the component. */
23584#define ALT_SYSMGR_PINMUX_GPLMUX69_OFST 0x2e8
23585
23586/*
23587 * Register : GPIO/LoanIO 70 Output/Output Enable Mux Selection Register - GPLMUX70
23588 *
23589 * Selection between GPIO and LoanIO output and output enable for GPIO70 and
23590 * LoanIO70. These signals drive the Pin Mux. The Pin Mux must be configured to use
23591 * GPIO/LoanIO in addition to these settings
23592 *
23593 * Only reset by a cold reset (ignores warm reset).
23594 *
23595 * NOTE: These registers should not be modified after IO configuration.There is no
23596 * support for dynamically changing the Pin Mux selections.
23597 *
23598 * Register Layout
23599 *
23600 * Bits | Access | Reset | Description
23601 * :-------|:-------|:------|:----------------------------------------
23602 * [0] | RW | 0x0 | GPIO/Loan IO70Input Mux Selection Field
23603 * [31:1] | ??? | 0x0 | *UNDEFINED*
23604 *
23605 */
23606/*
23607 * Field : GPIO/Loan IO70Input Mux Selection Field - sel
23608 *
23609 * Select source for GPIO/LoanIO 70.
23610 *
23611 * 0 : LoanIO 70 controls GPIO/LOANIO[70] output and output enable signals.
23612 *
23613 * 1 : GPIO 70 controls GPIO/LOANI[70] output and output enable signals.
23614 *
23615 * Field Access Macros:
23616 *
23617 */
23618/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */
23619#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_LSB 0
23620/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */
23621#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_MSB 0
23622/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */
23623#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_WIDTH 1
23624/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value. */
23625#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET_MSK 0x00000001
23626/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value. */
23627#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_CLR_MSK 0xfffffffe
23628/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */
23629#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_RESET 0x0
23630/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX70_SEL field value from a register. */
23631#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0)
23632/* Produces a ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value suitable for setting the register. */
23633#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET(value) (((value) << 0) & 0x00000001)
23634
23635#ifndef __ASSEMBLY__
23636/*
23637 * WARNING: The C register and register group struct declarations are provided for
23638 * convenience and illustrative purposes. They should, however, be used with
23639 * caution as the C language standard provides no guarantees about the alignment or
23640 * atomicity of device memory accesses. The recommended practice for writing
23641 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23642 * alt_write_word() functions.
23643 *
23644 * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX70.
23645 */
23646 struct ALT_SYSMGR_PINMUX_GPLMUX70_s
23647{
23648 uint32_t sel : 1; /* GPIO/Loan IO70Input Mux Selection Field */
23649 uint32_t : 31; /* *UNDEFINED* */
23650};
23651
23652/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX70. */
23653typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX70_s ALT_SYSMGR_PINMUX_GPLMUX70_t;
23654#endif /* __ASSEMBLY__ */
23655
23656/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX70 register from the beginning of the component. */
23657#define ALT_SYSMGR_PINMUX_GPLMUX70_OFST 0x2ec
23658
23659/*
23660 * Register : Select source for NAND signals (HPS Pins or FPGA Interface) - NANDUSEFPGA
23661 *
23662 * Selection between HPS Pins and FPGA Interface for NAND signals.
23663 *
23664 * Only reset by a cold reset (ignores warm reset).
23665 *
23666 * NOTE: These registers should not be modified after IO configuration.There is no
23667 * support for dynamically changing the Pin Mux selections.
23668 *
23669 * Register Layout
23670 *
23671 * Bits | Access | Reset | Description
23672 * :-------|:-------|:------|:---------------------------
23673 * [0] | RW | 0x0 | Selection for NAND signals
23674 * [31:1] | ??? | 0x0 | *UNDEFINED*
23675 *
23676 */
23677/*
23678 * Field : Selection for NAND signals - sel
23679 *
23680 * Select connection for NAND.
23681 *
23682 * 0 : NAND uses HPS Pins.
23683 *
23684 * 1 : NAND uses the FPGA Inteface.
23685 *
23686 * Field Access Macros:
23687 *
23688 */
23689/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */
23690#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_LSB 0
23691/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */
23692#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_MSB 0
23693/* The width in bits of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */
23694#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_WIDTH 1
23695/* The mask used to set the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value. */
23696#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET_MSK 0x00000001
23697/* The mask used to clear the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value. */
23698#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_CLR_MSK 0xfffffffe
23699/* The reset value of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */
23700#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_RESET 0x0
23701/* Extracts the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL field value from a register. */
23702#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
23703/* Produces a ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value suitable for setting the register. */
23704#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
23705
23706#ifndef __ASSEMBLY__
23707/*
23708 * WARNING: The C register and register group struct declarations are provided for
23709 * convenience and illustrative purposes. They should, however, be used with
23710 * caution as the C language standard provides no guarantees about the alignment or
23711 * atomicity of device memory accesses. The recommended practice for writing
23712 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23713 * alt_write_word() functions.
23714 *
23715 * The struct declaration for register ALT_SYSMGR_PINMUX_NANDUSEFPGA.
23716 */
23717 struct ALT_SYSMGR_PINMUX_NANDUSEFPGA_s
23718{
23719 uint32_t sel : 1; /* Selection for NAND signals */
23720 uint32_t : 31; /* *UNDEFINED* */
23721};
23722
23723/* The typedef declaration for register ALT_SYSMGR_PINMUX_NANDUSEFPGA. */
23724typedef volatile struct ALT_SYSMGR_PINMUX_NANDUSEFPGA_s ALT_SYSMGR_PINMUX_NANDUSEFPGA_t;
23725#endif /* __ASSEMBLY__ */
23726
23727/* The byte offset of the ALT_SYSMGR_PINMUX_NANDUSEFPGA register from the beginning of the component. */
23728#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_OFST 0x2f0
23729
23730/*
23731 * Register : Select source for RGMII1 signals (HPS Pins or FPGA Interface) - RGMII1USEFPGA
23732 *
23733 * Selection between HPS Pins and FPGA Interface for RGMII1 signals.
23734 *
23735 * Only reset by a cold reset (ignores warm reset).
23736 *
23737 * NOTE: These registers should not be modified after IO configuration.There is no
23738 * support for dynamically changing the Pin Mux selections.
23739 *
23740 * Register Layout
23741 *
23742 * Bits | Access | Reset | Description
23743 * :-------|:-------|:------|:-----------------------------
23744 * [0] | RW | 0x0 | Selection for RGMII1 signals
23745 * [31:1] | ??? | 0x0 | *UNDEFINED*
23746 *
23747 */
23748/*
23749 * Field : Selection for RGMII1 signals - sel
23750 *
23751 * Select connection for RGMII1.
23752 *
23753 * 0 : RGMII1 uses HPS Pins.
23754 *
23755 * 1 : RGMII1 uses the FPGA Inteface.
23756 *
23757 * Field Access Macros:
23758 *
23759 */
23760/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */
23761#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_LSB 0
23762/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */
23763#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_MSB 0
23764/* The width in bits of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */
23765#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_WIDTH 1
23766/* The mask used to set the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value. */
23767#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET_MSK 0x00000001
23768/* The mask used to clear the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value. */
23769#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_CLR_MSK 0xfffffffe
23770/* The reset value of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */
23771#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_RESET 0x0
23772/* Extracts the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL field value from a register. */
23773#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
23774/* Produces a ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value suitable for setting the register. */
23775#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
23776
23777#ifndef __ASSEMBLY__
23778/*
23779 * WARNING: The C register and register group struct declarations are provided for
23780 * convenience and illustrative purposes. They should, however, be used with
23781 * caution as the C language standard provides no guarantees about the alignment or
23782 * atomicity of device memory accesses. The recommended practice for writing
23783 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23784 * alt_write_word() functions.
23785 *
23786 * The struct declaration for register ALT_SYSMGR_PINMUX_RGMII1USEFPGA.
23787 */
23788 struct ALT_SYSMGR_PINMUX_RGMII1USEFPGA_s
23789{
23790 uint32_t sel : 1; /* Selection for RGMII1 signals */
23791 uint32_t : 31; /* *UNDEFINED* */
23792};
23793
23794/* The typedef declaration for register ALT_SYSMGR_PINMUX_RGMII1USEFPGA. */
23795typedef volatile struct ALT_SYSMGR_PINMUX_RGMII1USEFPGA_s ALT_SYSMGR_PINMUX_RGMII1USEFPGA_t;
23796#endif /* __ASSEMBLY__ */
23797
23798/* The byte offset of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA register from the beginning of the component. */
23799#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_OFST 0x2f8
23800
23801/*
23802 * Register : Select source for I2C0 signals (HPS Pins or FPGA Interface) - I2C0USEFPGA
23803 *
23804 * Selection between HPS Pins and FPGA Interface for I2C0 signals.
23805 *
23806 * Only reset by a cold reset (ignores warm reset).
23807 *
23808 * NOTE: These registers should not be modified after IO configuration.There is no
23809 * support for dynamically changing the Pin Mux selections.
23810 *
23811 * Register Layout
23812 *
23813 * Bits | Access | Reset | Description
23814 * :-------|:-------|:------|:---------------------------
23815 * [0] | RW | 0x0 | Selection for I2C0 signals
23816 * [31:1] | ??? | 0x0 | *UNDEFINED*
23817 *
23818 */
23819/*
23820 * Field : Selection for I2C0 signals - sel
23821 *
23822 * Select connection for I2C0.
23823 *
23824 * 0 : I2C0 uses HPS Pins.
23825 *
23826 * 1 : I2C0 uses the FPGA Inteface.
23827 *
23828 * Field Access Macros:
23829 *
23830 */
23831/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */
23832#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_LSB 0
23833/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */
23834#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_MSB 0
23835/* The width in bits of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */
23836#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_WIDTH 1
23837/* The mask used to set the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value. */
23838#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET_MSK 0x00000001
23839/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value. */
23840#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_CLR_MSK 0xfffffffe
23841/* The reset value of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */
23842#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_RESET 0x0
23843/* Extracts the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL field value from a register. */
23844#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
23845/* Produces a ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value suitable for setting the register. */
23846#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
23847
23848#ifndef __ASSEMBLY__
23849/*
23850 * WARNING: The C register and register group struct declarations are provided for
23851 * convenience and illustrative purposes. They should, however, be used with
23852 * caution as the C language standard provides no guarantees about the alignment or
23853 * atomicity of device memory accesses. The recommended practice for writing
23854 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23855 * alt_write_word() functions.
23856 *
23857 * The struct declaration for register ALT_SYSMGR_PINMUX_I2C0USEFPGA.
23858 */
23859 struct ALT_SYSMGR_PINMUX_I2C0USEFPGA_s
23860{
23861 uint32_t sel : 1; /* Selection for I2C0 signals */
23862 uint32_t : 31; /* *UNDEFINED* */
23863};
23864
23865/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C0USEFPGA. */
23866typedef volatile struct ALT_SYSMGR_PINMUX_I2C0USEFPGA_s ALT_SYSMGR_PINMUX_I2C0USEFPGA_t;
23867#endif /* __ASSEMBLY__ */
23868
23869/* The byte offset of the ALT_SYSMGR_PINMUX_I2C0USEFPGA register from the beginning of the component. */
23870#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_OFST 0x304
23871
23872/*
23873 * Register : Select source for RGMII0 signals (HPS Pins or FPGA Interface) - RGMII0USEFPGA
23874 *
23875 * Selection between HPS Pins and FPGA Interface for RGMII0 signals.
23876 *
23877 * Only reset by a cold reset (ignores warm reset).
23878 *
23879 * NOTE: These registers should not be modified after IO configuration.There is no
23880 * support for dynamically changing the Pin Mux selections.
23881 *
23882 * Register Layout
23883 *
23884 * Bits | Access | Reset | Description
23885 * :-------|:-------|:------|:-----------------------------
23886 * [0] | RW | 0x0 | Selection for RGMII0 signals
23887 * [31:1] | ??? | 0x0 | *UNDEFINED*
23888 *
23889 */
23890/*
23891 * Field : Selection for RGMII0 signals - sel
23892 *
23893 * Select connection for RGMII0.
23894 *
23895 * 0 : RGMII0 uses HPS Pins.
23896 *
23897 * 1 : RGMII0 uses the FPGA Inteface.
23898 *
23899 * Field Access Macros:
23900 *
23901 */
23902/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */
23903#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_LSB 0
23904/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */
23905#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_MSB 0
23906/* The width in bits of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */
23907#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_WIDTH 1
23908/* The mask used to set the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value. */
23909#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET_MSK 0x00000001
23910/* The mask used to clear the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value. */
23911#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_CLR_MSK 0xfffffffe
23912/* The reset value of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */
23913#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_RESET 0x0
23914/* Extracts the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL field value from a register. */
23915#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
23916/* Produces a ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value suitable for setting the register. */
23917#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
23918
23919#ifndef __ASSEMBLY__
23920/*
23921 * WARNING: The C register and register group struct declarations are provided for
23922 * convenience and illustrative purposes. They should, however, be used with
23923 * caution as the C language standard provides no guarantees about the alignment or
23924 * atomicity of device memory accesses. The recommended practice for writing
23925 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23926 * alt_write_word() functions.
23927 *
23928 * The struct declaration for register ALT_SYSMGR_PINMUX_RGMII0USEFPGA.
23929 */
23930 struct ALT_SYSMGR_PINMUX_RGMII0USEFPGA_s
23931{
23932 uint32_t sel : 1; /* Selection for RGMII0 signals */
23933 uint32_t : 31; /* *UNDEFINED* */
23934};
23935
23936/* The typedef declaration for register ALT_SYSMGR_PINMUX_RGMII0USEFPGA. */
23937typedef volatile struct ALT_SYSMGR_PINMUX_RGMII0USEFPGA_s ALT_SYSMGR_PINMUX_RGMII0USEFPGA_t;
23938#endif /* __ASSEMBLY__ */
23939
23940/* The byte offset of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA register from the beginning of the component. */
23941#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_OFST 0x314
23942
23943/*
23944 * Register : Select source for I2C3 signals (HPS Pins or FPGA Interface) - I2C3USEFPGA
23945 *
23946 * Selection between HPS Pins and FPGA Interface for I2C3 signals.
23947 *
23948 * Only reset by a cold reset (ignores warm reset).
23949 *
23950 * NOTE: These registers should not be modified after IO configuration.There is no
23951 * support for dynamically changing the Pin Mux selections.
23952 *
23953 * Register Layout
23954 *
23955 * Bits | Access | Reset | Description
23956 * :-------|:-------|:------|:---------------------------
23957 * [0] | RW | 0x0 | Selection for I2C3 signals
23958 * [31:1] | ??? | 0x0 | *UNDEFINED*
23959 *
23960 */
23961/*
23962 * Field : Selection for I2C3 signals - sel
23963 *
23964 * Select connection for I2C3.
23965 *
23966 * 0 : I2C3 uses HPS Pins.
23967 *
23968 * 1 : I2C3 uses the FPGA Inteface.
23969 *
23970 * Field Access Macros:
23971 *
23972 */
23973/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */
23974#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_LSB 0
23975/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */
23976#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_MSB 0
23977/* The width in bits of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */
23978#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_WIDTH 1
23979/* The mask used to set the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value. */
23980#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET_MSK 0x00000001
23981/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value. */
23982#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_CLR_MSK 0xfffffffe
23983/* The reset value of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */
23984#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_RESET 0x0
23985/* Extracts the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL field value from a register. */
23986#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
23987/* Produces a ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value suitable for setting the register. */
23988#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
23989
23990#ifndef __ASSEMBLY__
23991/*
23992 * WARNING: The C register and register group struct declarations are provided for
23993 * convenience and illustrative purposes. They should, however, be used with
23994 * caution as the C language standard provides no guarantees about the alignment or
23995 * atomicity of device memory accesses. The recommended practice for writing
23996 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23997 * alt_write_word() functions.
23998 *
23999 * The struct declaration for register ALT_SYSMGR_PINMUX_I2C3USEFPGA.
24000 */
24001 struct ALT_SYSMGR_PINMUX_I2C3USEFPGA_s
24002{
24003 uint32_t sel : 1; /* Selection for I2C3 signals */
24004 uint32_t : 31; /* *UNDEFINED* */
24005};
24006
24007/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C3USEFPGA. */
24008typedef volatile struct ALT_SYSMGR_PINMUX_I2C3USEFPGA_s ALT_SYSMGR_PINMUX_I2C3USEFPGA_t;
24009#endif /* __ASSEMBLY__ */
24010
24011/* The byte offset of the ALT_SYSMGR_PINMUX_I2C3USEFPGA register from the beginning of the component. */
24012#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_OFST 0x324
24013
24014/*
24015 * Register : Select source for I2C2 signals (HPS Pins or FPGA Interface) - I2C2USEFPGA
24016 *
24017 * Selection between HPS Pins and FPGA Interface for I2C2 signals.
24018 *
24019 * Only reset by a cold reset (ignores warm reset).
24020 *
24021 * NOTE: These registers should not be modified after IO configuration.There is no
24022 * support for dynamically changing the Pin Mux selections.
24023 *
24024 * Register Layout
24025 *
24026 * Bits | Access | Reset | Description
24027 * :-------|:-------|:------|:---------------------------
24028 * [0] | RW | 0x0 | Selection for I2C2 signals
24029 * [31:1] | ??? | 0x0 | *UNDEFINED*
24030 *
24031 */
24032/*
24033 * Field : Selection for I2C2 signals - sel
24034 *
24035 * Select connection for I2C2.
24036 *
24037 * 0 : I2C2 uses HPS Pins.
24038 *
24039 * 1 : I2C2 uses the FPGA Inteface.
24040 *
24041 * Field Access Macros:
24042 *
24043 */
24044/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */
24045#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_LSB 0
24046/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */
24047#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_MSB 0
24048/* The width in bits of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */
24049#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_WIDTH 1
24050/* The mask used to set the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value. */
24051#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET_MSK 0x00000001
24052/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value. */
24053#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_CLR_MSK 0xfffffffe
24054/* The reset value of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */
24055#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_RESET 0x0
24056/* Extracts the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL field value from a register. */
24057#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
24058/* Produces a ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value suitable for setting the register. */
24059#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
24060
24061#ifndef __ASSEMBLY__
24062/*
24063 * WARNING: The C register and register group struct declarations are provided for
24064 * convenience and illustrative purposes. They should, however, be used with
24065 * caution as the C language standard provides no guarantees about the alignment or
24066 * atomicity of device memory accesses. The recommended practice for writing
24067 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24068 * alt_write_word() functions.
24069 *
24070 * The struct declaration for register ALT_SYSMGR_PINMUX_I2C2USEFPGA.
24071 */
24072 struct ALT_SYSMGR_PINMUX_I2C2USEFPGA_s
24073{
24074 uint32_t sel : 1; /* Selection for I2C2 signals */
24075 uint32_t : 31; /* *UNDEFINED* */
24076};
24077
24078/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C2USEFPGA. */
24079typedef volatile struct ALT_SYSMGR_PINMUX_I2C2USEFPGA_s ALT_SYSMGR_PINMUX_I2C2USEFPGA_t;
24080#endif /* __ASSEMBLY__ */
24081
24082/* The byte offset of the ALT_SYSMGR_PINMUX_I2C2USEFPGA register from the beginning of the component. */
24083#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_OFST 0x328
24084
24085/*
24086 * Register : Select source for I2C1 signals (HPS Pins or FPGA Interface) - I2C1USEFPGA
24087 *
24088 * Selection between HPS Pins and FPGA Interface for I2C1 signals.
24089 *
24090 * Only reset by a cold reset (ignores warm reset).
24091 *
24092 * NOTE: These registers should not be modified after IO configuration.There is no
24093 * support for dynamically changing the Pin Mux selections.
24094 *
24095 * Register Layout
24096 *
24097 * Bits | Access | Reset | Description
24098 * :-------|:-------|:------|:---------------------------
24099 * [0] | RW | 0x0 | Selection for I2C1 signals
24100 * [31:1] | ??? | 0x0 | *UNDEFINED*
24101 *
24102 */
24103/*
24104 * Field : Selection for I2C1 signals - sel
24105 *
24106 * Select connection for I2C1.
24107 *
24108 * 0 : I2C1 uses HPS Pins.
24109 *
24110 * 1 : I2C1 uses the FPGA Inteface.
24111 *
24112 * Field Access Macros:
24113 *
24114 */
24115/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */
24116#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_LSB 0
24117/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */
24118#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_MSB 0
24119/* The width in bits of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */
24120#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_WIDTH 1
24121/* The mask used to set the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value. */
24122#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET_MSK 0x00000001
24123/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value. */
24124#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_CLR_MSK 0xfffffffe
24125/* The reset value of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */
24126#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_RESET 0x0
24127/* Extracts the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL field value from a register. */
24128#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
24129/* Produces a ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value suitable for setting the register. */
24130#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
24131
24132#ifndef __ASSEMBLY__
24133/*
24134 * WARNING: The C register and register group struct declarations are provided for
24135 * convenience and illustrative purposes. They should, however, be used with
24136 * caution as the C language standard provides no guarantees about the alignment or
24137 * atomicity of device memory accesses. The recommended practice for writing
24138 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24139 * alt_write_word() functions.
24140 *
24141 * The struct declaration for register ALT_SYSMGR_PINMUX_I2C1USEFPGA.
24142 */
24143 struct ALT_SYSMGR_PINMUX_I2C1USEFPGA_s
24144{
24145 uint32_t sel : 1; /* Selection for I2C1 signals */
24146 uint32_t : 31; /* *UNDEFINED* */
24147};
24148
24149/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C1USEFPGA. */
24150typedef volatile struct ALT_SYSMGR_PINMUX_I2C1USEFPGA_s ALT_SYSMGR_PINMUX_I2C1USEFPGA_t;
24151#endif /* __ASSEMBLY__ */
24152
24153/* The byte offset of the ALT_SYSMGR_PINMUX_I2C1USEFPGA register from the beginning of the component. */
24154#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_OFST 0x32c
24155
24156/*
24157 * Register : Select source for SPIM1 signals (HPS Pins or FPGA Interface) - SPIM1USEFPGA
24158 *
24159 * Selection between HPS Pins and FPGA Interface for SPIM1 signals.
24160 *
24161 * Only reset by a cold reset (ignores warm reset).
24162 *
24163 * NOTE: These registers should not be modified after IO configuration.There is no
24164 * support for dynamically changing the Pin Mux selections.
24165 *
24166 * Register Layout
24167 *
24168 * Bits | Access | Reset | Description
24169 * :-------|:-------|:------|:----------------------------
24170 * [0] | RW | 0x0 | Selection for SPIM1 signals
24171 * [31:1] | ??? | 0x0 | *UNDEFINED*
24172 *
24173 */
24174/*
24175 * Field : Selection for SPIM1 signals - sel
24176 *
24177 * Select connection for SPIM1.
24178 *
24179 * 0 : SPIM1 uses HPS Pins.
24180 *
24181 * 1 : SPIM1 uses the FPGA Inteface.
24182 *
24183 * Field Access Macros:
24184 *
24185 */
24186/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */
24187#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_LSB 0
24188/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */
24189#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_MSB 0
24190/* The width in bits of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */
24191#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_WIDTH 1
24192/* The mask used to set the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value. */
24193#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET_MSK 0x00000001
24194/* The mask used to clear the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value. */
24195#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_CLR_MSK 0xfffffffe
24196/* The reset value of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */
24197#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_RESET 0x0
24198/* Extracts the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL field value from a register. */
24199#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
24200/* Produces a ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value suitable for setting the register. */
24201#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
24202
24203#ifndef __ASSEMBLY__
24204/*
24205 * WARNING: The C register and register group struct declarations are provided for
24206 * convenience and illustrative purposes. They should, however, be used with
24207 * caution as the C language standard provides no guarantees about the alignment or
24208 * atomicity of device memory accesses. The recommended practice for writing
24209 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24210 * alt_write_word() functions.
24211 *
24212 * The struct declaration for register ALT_SYSMGR_PINMUX_SPIM1USEFPGA.
24213 */
24214 struct ALT_SYSMGR_PINMUX_SPIM1USEFPGA_s
24215{
24216 uint32_t sel : 1; /* Selection for SPIM1 signals */
24217 uint32_t : 31; /* *UNDEFINED* */
24218};
24219
24220/* The typedef declaration for register ALT_SYSMGR_PINMUX_SPIM1USEFPGA. */
24221typedef volatile struct ALT_SYSMGR_PINMUX_SPIM1USEFPGA_s ALT_SYSMGR_PINMUX_SPIM1USEFPGA_t;
24222#endif /* __ASSEMBLY__ */
24223
24224/* The byte offset of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA register from the beginning of the component. */
24225#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_OFST 0x330
24226
24227/*
24228 * Register : Select source for SPIM0 signals (HPS Pins or FPGA Interface) - SPIM0USEFPGA
24229 *
24230 * Selection between HPS Pins and FPGA Interface for SPIM0 signals.
24231 *
24232 * Only reset by a cold reset (ignores warm reset).
24233 *
24234 * NOTE: These registers should not be modified after IO configuration.There is no
24235 * support for dynamically changing the Pin Mux selections.
24236 *
24237 * Register Layout
24238 *
24239 * Bits | Access | Reset | Description
24240 * :-------|:-------|:------|:----------------------------
24241 * [0] | RW | 0x0 | Selection for SPIM0 signals
24242 * [31:1] | ??? | 0x0 | *UNDEFINED*
24243 *
24244 */
24245/*
24246 * Field : Selection for SPIM0 signals - sel
24247 *
24248 * Select connection for SPIM0.
24249 *
24250 * 0 : SPIM0 uses HPS Pins.
24251 *
24252 * 1 : SPIM0 uses the FPGA Inteface.
24253 *
24254 * Field Access Macros:
24255 *
24256 */
24257/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */
24258#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_LSB 0
24259/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */
24260#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_MSB 0
24261/* The width in bits of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */
24262#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_WIDTH 1
24263/* The mask used to set the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value. */
24264#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET_MSK 0x00000001
24265/* The mask used to clear the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value. */
24266#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_CLR_MSK 0xfffffffe
24267/* The reset value of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */
24268#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_RESET 0x0
24269/* Extracts the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL field value from a register. */
24270#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
24271/* Produces a ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value suitable for setting the register. */
24272#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
24273
24274#ifndef __ASSEMBLY__
24275/*
24276 * WARNING: The C register and register group struct declarations are provided for
24277 * convenience and illustrative purposes. They should, however, be used with
24278 * caution as the C language standard provides no guarantees about the alignment or
24279 * atomicity of device memory accesses. The recommended practice for writing
24280 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24281 * alt_write_word() functions.
24282 *
24283 * The struct declaration for register ALT_SYSMGR_PINMUX_SPIM0USEFPGA.
24284 */
24285 struct ALT_SYSMGR_PINMUX_SPIM0USEFPGA_s
24286{
24287 uint32_t sel : 1; /* Selection for SPIM0 signals */
24288 uint32_t : 31; /* *UNDEFINED* */
24289};
24290
24291/* The typedef declaration for register ALT_SYSMGR_PINMUX_SPIM0USEFPGA. */
24292typedef volatile struct ALT_SYSMGR_PINMUX_SPIM0USEFPGA_s ALT_SYSMGR_PINMUX_SPIM0USEFPGA_t;
24293#endif /* __ASSEMBLY__ */
24294
24295/* The byte offset of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA register from the beginning of the component. */
24296#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_OFST 0x338
24297
24298#ifndef __ASSEMBLY__
24299/*
24300 * WARNING: The C register and register group struct declarations are provided for
24301 * convenience and illustrative purposes. They should, however, be used with
24302 * caution as the C language standard provides no guarantees about the alignment or
24303 * atomicity of device memory accesses. The recommended practice for writing
24304 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24305 * alt_write_word() functions.
24306 *
24307 * The struct declaration for register group ALT_SYSMGR_PINMUX.
24308 */
24309 struct ALT_SYSMGR_PINMUX_s
24310{
24311 volatile ALT_SYSMGR_PINMUX_EMACIO0_t EMACIO0; /* ALT_SYSMGR_PINMUX_EMACIO0 */
24312 volatile ALT_SYSMGR_PINMUX_EMACIO1_t EMACIO1; /* ALT_SYSMGR_PINMUX_EMACIO1 */
24313 volatile ALT_SYSMGR_PINMUX_EMACIO2_t EMACIO2; /* ALT_SYSMGR_PINMUX_EMACIO2 */
24314 volatile ALT_SYSMGR_PINMUX_EMACIO3_t EMACIO3; /* ALT_SYSMGR_PINMUX_EMACIO3 */
24315 volatile ALT_SYSMGR_PINMUX_EMACIO4_t EMACIO4; /* ALT_SYSMGR_PINMUX_EMACIO4 */
24316 volatile ALT_SYSMGR_PINMUX_EMACIO5_t EMACIO5; /* ALT_SYSMGR_PINMUX_EMACIO5 */
24317 volatile ALT_SYSMGR_PINMUX_EMACIO6_t EMACIO6; /* ALT_SYSMGR_PINMUX_EMACIO6 */
24318 volatile ALT_SYSMGR_PINMUX_EMACIO7_t EMACIO7; /* ALT_SYSMGR_PINMUX_EMACIO7 */
24319 volatile ALT_SYSMGR_PINMUX_EMACIO8_t EMACIO8; /* ALT_SYSMGR_PINMUX_EMACIO8 */
24320 volatile ALT_SYSMGR_PINMUX_EMACIO9_t EMACIO9; /* ALT_SYSMGR_PINMUX_EMACIO9 */
24321 volatile ALT_SYSMGR_PINMUX_EMACIO10_t EMACIO10; /* ALT_SYSMGR_PINMUX_EMACIO10 */
24322 volatile ALT_SYSMGR_PINMUX_EMACIO11_t EMACIO11; /* ALT_SYSMGR_PINMUX_EMACIO11 */
24323 volatile ALT_SYSMGR_PINMUX_EMACIO12_t EMACIO12; /* ALT_SYSMGR_PINMUX_EMACIO12 */
24324 volatile ALT_SYSMGR_PINMUX_EMACIO13_t EMACIO13; /* ALT_SYSMGR_PINMUX_EMACIO13 */
24325 volatile ALT_SYSMGR_PINMUX_EMACIO14_t EMACIO14; /* ALT_SYSMGR_PINMUX_EMACIO14 */
24326 volatile ALT_SYSMGR_PINMUX_EMACIO15_t EMACIO15; /* ALT_SYSMGR_PINMUX_EMACIO15 */
24327 volatile ALT_SYSMGR_PINMUX_EMACIO16_t EMACIO16; /* ALT_SYSMGR_PINMUX_EMACIO16 */
24328 volatile ALT_SYSMGR_PINMUX_EMACIO17_t EMACIO17; /* ALT_SYSMGR_PINMUX_EMACIO17 */
24329 volatile ALT_SYSMGR_PINMUX_EMACIO18_t EMACIO18; /* ALT_SYSMGR_PINMUX_EMACIO18 */
24330 volatile ALT_SYSMGR_PINMUX_EMACIO19_t EMACIO19; /* ALT_SYSMGR_PINMUX_EMACIO19 */
24331 volatile ALT_SYSMGR_PINMUX_FLSHIO0_t FLASHIO0; /* ALT_SYSMGR_PINMUX_FLSHIO0 */
24332 volatile ALT_SYSMGR_PINMUX_FLSHIO1_t FLASHIO1; /* ALT_SYSMGR_PINMUX_FLSHIO1 */
24333 volatile ALT_SYSMGR_PINMUX_FLSHIO2_t FLASHIO2; /* ALT_SYSMGR_PINMUX_FLSHIO2 */
24334 volatile ALT_SYSMGR_PINMUX_FLSHIO3_t FLASHIO3; /* ALT_SYSMGR_PINMUX_FLSHIO3 */
24335 volatile ALT_SYSMGR_PINMUX_FLSHIO4_t FLASHIO4; /* ALT_SYSMGR_PINMUX_FLSHIO4 */
24336 volatile ALT_SYSMGR_PINMUX_FLSHIO5_t FLASHIO5; /* ALT_SYSMGR_PINMUX_FLSHIO5 */
24337 volatile ALT_SYSMGR_PINMUX_FLSHIO6_t FLASHIO6; /* ALT_SYSMGR_PINMUX_FLSHIO6 */
24338 volatile ALT_SYSMGR_PINMUX_FLSHIO7_t FLASHIO7; /* ALT_SYSMGR_PINMUX_FLSHIO7 */
24339 volatile ALT_SYSMGR_PINMUX_FLSHIO8_t FLASHIO8; /* ALT_SYSMGR_PINMUX_FLSHIO8 */
24340 volatile ALT_SYSMGR_PINMUX_FLSHIO9_t FLASHIO9; /* ALT_SYSMGR_PINMUX_FLSHIO9 */
24341 volatile ALT_SYSMGR_PINMUX_FLSHIO10_t FLASHIO10; /* ALT_SYSMGR_PINMUX_FLSHIO10 */
24342 volatile ALT_SYSMGR_PINMUX_FLSHIO11_t FLASHIO11; /* ALT_SYSMGR_PINMUX_FLSHIO11 */
24343 volatile ALT_SYSMGR_PINMUX_GENERALIO0_t GENERALIO0; /* ALT_SYSMGR_PINMUX_GENERALIO0 */
24344 volatile ALT_SYSMGR_PINMUX_GENERALIO1_t GENERALIO1; /* ALT_SYSMGR_PINMUX_GENERALIO1 */
24345 volatile ALT_SYSMGR_PINMUX_GENERALIO2_t GENERALIO2; /* ALT_SYSMGR_PINMUX_GENERALIO2 */
24346 volatile ALT_SYSMGR_PINMUX_GENERALIO3_t GENERALIO3; /* ALT_SYSMGR_PINMUX_GENERALIO3 */
24347 volatile ALT_SYSMGR_PINMUX_GENERALIO4_t GENERALIO4; /* ALT_SYSMGR_PINMUX_GENERALIO4 */
24348 volatile ALT_SYSMGR_PINMUX_GENERALIO5_t GENERALIO5; /* ALT_SYSMGR_PINMUX_GENERALIO5 */
24349 volatile ALT_SYSMGR_PINMUX_GENERALIO6_t GENERALIO6; /* ALT_SYSMGR_PINMUX_GENERALIO6 */
24350 volatile ALT_SYSMGR_PINMUX_GENERALIO7_t GENERALIO7; /* ALT_SYSMGR_PINMUX_GENERALIO7 */
24351 volatile ALT_SYSMGR_PINMUX_GENERALIO8_t GENERALIO8; /* ALT_SYSMGR_PINMUX_GENERALIO8 */
24352 volatile ALT_SYSMGR_PINMUX_GENERALIO9_t GENERALIO9; /* ALT_SYSMGR_PINMUX_GENERALIO9 */
24353 volatile ALT_SYSMGR_PINMUX_GENERALIO10_t GENERALIO10; /* ALT_SYSMGR_PINMUX_GENERALIO10 */
24354 volatile ALT_SYSMGR_PINMUX_GENERALIO11_t GENERALIO11; /* ALT_SYSMGR_PINMUX_GENERALIO11 */
24355 volatile ALT_SYSMGR_PINMUX_GENERALIO12_t GENERALIO12; /* ALT_SYSMGR_PINMUX_GENERALIO12 */
24356 volatile ALT_SYSMGR_PINMUX_GENERALIO13_t GENERALIO13; /* ALT_SYSMGR_PINMUX_GENERALIO13 */
24357 volatile ALT_SYSMGR_PINMUX_GENERALIO14_t GENERALIO14; /* ALT_SYSMGR_PINMUX_GENERALIO14 */
24358 volatile ALT_SYSMGR_PINMUX_GENERALIO15_t GENERALIO15; /* ALT_SYSMGR_PINMUX_GENERALIO15 */
24359 volatile ALT_SYSMGR_PINMUX_GENERALIO16_t GENERALIO16; /* ALT_SYSMGR_PINMUX_GENERALIO16 */
24360 volatile ALT_SYSMGR_PINMUX_GENERALIO17_t GENERALIO17; /* ALT_SYSMGR_PINMUX_GENERALIO17 */
24361 volatile ALT_SYSMGR_PINMUX_GENERALIO18_t GENERALIO18; /* ALT_SYSMGR_PINMUX_GENERALIO18 */
24362 volatile ALT_SYSMGR_PINMUX_GENERALIO19_t GENERALIO19; /* ALT_SYSMGR_PINMUX_GENERALIO19 */
24363 volatile ALT_SYSMGR_PINMUX_GENERALIO20_t GENERALIO20; /* ALT_SYSMGR_PINMUX_GENERALIO20 */
24364 volatile ALT_SYSMGR_PINMUX_GENERALIO21_t GENERALIO21; /* ALT_SYSMGR_PINMUX_GENERALIO21 */
24365 volatile ALT_SYSMGR_PINMUX_GENERALIO22_t GENERALIO22; /* ALT_SYSMGR_PINMUX_GENERALIO22 */
24366 volatile ALT_SYSMGR_PINMUX_GENERALIO23_t GENERALIO23; /* ALT_SYSMGR_PINMUX_GENERALIO23 */
24367 volatile ALT_SYSMGR_PINMUX_GENERALIO24_t GENERALIO24; /* ALT_SYSMGR_PINMUX_GENERALIO24 */
24368 volatile ALT_SYSMGR_PINMUX_GENERALIO25_t GENERALIO25; /* ALT_SYSMGR_PINMUX_GENERALIO25 */
24369 volatile ALT_SYSMGR_PINMUX_GENERALIO26_t GENERALIO26; /* ALT_SYSMGR_PINMUX_GENERALIO26 */
24370 volatile ALT_SYSMGR_PINMUX_GENERALIO27_t GENERALIO27; /* ALT_SYSMGR_PINMUX_GENERALIO27 */
24371 volatile ALT_SYSMGR_PINMUX_GENERALIO28_t GENERALIO28; /* ALT_SYSMGR_PINMUX_GENERALIO28 */
24372 volatile ALT_SYSMGR_PINMUX_GENERALIO29_t GENERALIO29; /* ALT_SYSMGR_PINMUX_GENERALIO29 */
24373 volatile ALT_SYSMGR_PINMUX_GENERALIO30_t GENERALIO30; /* ALT_SYSMGR_PINMUX_GENERALIO30 */
24374 volatile ALT_SYSMGR_PINMUX_GENERALIO31_t GENERALIO31; /* ALT_SYSMGR_PINMUX_GENERALIO31 */
24375 volatile ALT_SYSMGR_PINMUX_MIXED1IO0_t MIXED1IO0; /* ALT_SYSMGR_PINMUX_MIXED1IO0 */
24376 volatile ALT_SYSMGR_PINMUX_MIXED1IO1_t MIXED1IO1; /* ALT_SYSMGR_PINMUX_MIXED1IO1 */
24377 volatile ALT_SYSMGR_PINMUX_MIXED1IO2_t MIXED1IO2; /* ALT_SYSMGR_PINMUX_MIXED1IO2 */
24378 volatile ALT_SYSMGR_PINMUX_MIXED1IO3_t MIXED1IO3; /* ALT_SYSMGR_PINMUX_MIXED1IO3 */
24379 volatile ALT_SYSMGR_PINMUX_MIXED1IO4_t MIXED1IO4; /* ALT_SYSMGR_PINMUX_MIXED1IO4 */
24380 volatile ALT_SYSMGR_PINMUX_MIXED1IO5_t MIXED1IO5; /* ALT_SYSMGR_PINMUX_MIXED1IO5 */
24381 volatile ALT_SYSMGR_PINMUX_MIXED1IO6_t MIXED1IO6; /* ALT_SYSMGR_PINMUX_MIXED1IO6 */
24382 volatile ALT_SYSMGR_PINMUX_MIXED1IO7_t MIXED1IO7; /* ALT_SYSMGR_PINMUX_MIXED1IO7 */
24383 volatile ALT_SYSMGR_PINMUX_MIXED1IO8_t MIXED1IO8; /* ALT_SYSMGR_PINMUX_MIXED1IO8 */
24384 volatile ALT_SYSMGR_PINMUX_MIXED1IO9_t MIXED1IO9; /* ALT_SYSMGR_PINMUX_MIXED1IO9 */
24385 volatile ALT_SYSMGR_PINMUX_MIXED1IO10_t MIXED1IO10; /* ALT_SYSMGR_PINMUX_MIXED1IO10 */
24386 volatile ALT_SYSMGR_PINMUX_MIXED1IO11_t MIXED1IO11; /* ALT_SYSMGR_PINMUX_MIXED1IO11 */
24387 volatile ALT_SYSMGR_PINMUX_MIXED1IO12_t MIXED1IO12; /* ALT_SYSMGR_PINMUX_MIXED1IO12 */
24388 volatile ALT_SYSMGR_PINMUX_MIXED1IO13_t MIXED1IO13; /* ALT_SYSMGR_PINMUX_MIXED1IO13 */
24389 volatile ALT_SYSMGR_PINMUX_MIXED1IO14_t MIXED1IO14; /* ALT_SYSMGR_PINMUX_MIXED1IO14 */
24390 volatile ALT_SYSMGR_PINMUX_MIXED1IO15_t MIXED1IO15; /* ALT_SYSMGR_PINMUX_MIXED1IO15 */
24391 volatile ALT_SYSMGR_PINMUX_MIXED1IO16_t MIXED1IO16; /* ALT_SYSMGR_PINMUX_MIXED1IO16 */
24392 volatile ALT_SYSMGR_PINMUX_MIXED1IO17_t MIXED1IO17; /* ALT_SYSMGR_PINMUX_MIXED1IO17 */
24393 volatile ALT_SYSMGR_PINMUX_MIXED1IO18_t MIXED1IO18; /* ALT_SYSMGR_PINMUX_MIXED1IO18 */
24394 volatile ALT_SYSMGR_PINMUX_MIXED1IO19_t MIXED1IO19; /* ALT_SYSMGR_PINMUX_MIXED1IO19 */
24395 volatile ALT_SYSMGR_PINMUX_MIXED1IO20_t MIXED1IO20; /* ALT_SYSMGR_PINMUX_MIXED1IO20 */
24396 volatile ALT_SYSMGR_PINMUX_MIXED1IO21_t MIXED1IO21; /* ALT_SYSMGR_PINMUX_MIXED1IO21 */
24397 volatile ALT_SYSMGR_PINMUX_MIXED2IO0_t MIXED2IO0; /* ALT_SYSMGR_PINMUX_MIXED2IO0 */
24398 volatile ALT_SYSMGR_PINMUX_MIXED2IO1_t MIXED2IO1; /* ALT_SYSMGR_PINMUX_MIXED2IO1 */
24399 volatile ALT_SYSMGR_PINMUX_MIXED2IO2_t MIXED2IO2; /* ALT_SYSMGR_PINMUX_MIXED2IO2 */
24400 volatile ALT_SYSMGR_PINMUX_MIXED2IO3_t MIXED2IO3; /* ALT_SYSMGR_PINMUX_MIXED2IO3 */
24401 volatile ALT_SYSMGR_PINMUX_MIXED2IO4_t MIXED2IO4; /* ALT_SYSMGR_PINMUX_MIXED2IO4 */
24402 volatile ALT_SYSMGR_PINMUX_MIXED2IO5_t MIXED2IO5; /* ALT_SYSMGR_PINMUX_MIXED2IO5 */
24403 volatile ALT_SYSMGR_PINMUX_MIXED2IO6_t MIXED2IO6; /* ALT_SYSMGR_PINMUX_MIXED2IO6 */
24404 volatile ALT_SYSMGR_PINMUX_MIXED2IO7_t MIXED2IO7; /* ALT_SYSMGR_PINMUX_MIXED2IO7 */
24405 volatile ALT_SYSMGR_PINMUX_GPLINMUX48_t GPLINMUX48; /* ALT_SYSMGR_PINMUX_GPLINMUX48 */
24406 volatile ALT_SYSMGR_PINMUX_GPLINMUX49_t GPLINMUX49; /* ALT_SYSMGR_PINMUX_GPLINMUX49 */
24407 volatile ALT_SYSMGR_PINMUX_GPLINMUX50_t GPLINMUX50; /* ALT_SYSMGR_PINMUX_GPLINMUX50 */
24408 volatile ALT_SYSMGR_PINMUX_GPLINMUX51_t GPLINMUX51; /* ALT_SYSMGR_PINMUX_GPLINMUX51 */
24409 volatile ALT_SYSMGR_PINMUX_GPLINMUX52_t GPLINMUX52; /* ALT_SYSMGR_PINMUX_GPLINMUX52 */
24410 volatile ALT_SYSMGR_PINMUX_GPLINMUX53_t GPLINMUX53; /* ALT_SYSMGR_PINMUX_GPLINMUX53 */
24411 volatile ALT_SYSMGR_PINMUX_GPLINMUX54_t GPLINMUX54; /* ALT_SYSMGR_PINMUX_GPLINMUX54 */
24412 volatile ALT_SYSMGR_PINMUX_GPLINMUX55_t GPLINMUX55; /* ALT_SYSMGR_PINMUX_GPLINMUX55 */
24413 volatile ALT_SYSMGR_PINMUX_GPLINMUX56_t GPLINMUX56; /* ALT_SYSMGR_PINMUX_GPLINMUX56 */
24414 volatile ALT_SYSMGR_PINMUX_GPLINMUX57_t GPLINMUX57; /* ALT_SYSMGR_PINMUX_GPLINMUX57 */
24415 volatile ALT_SYSMGR_PINMUX_GPLINMUX58_t GPLINMUX58; /* ALT_SYSMGR_PINMUX_GPLINMUX58 */
24416 volatile ALT_SYSMGR_PINMUX_GPLINMUX59_t GPLINMUX59; /* ALT_SYSMGR_PINMUX_GPLINMUX59 */
24417 volatile ALT_SYSMGR_PINMUX_GPLINMUX60_t GPLINMUX60; /* ALT_SYSMGR_PINMUX_GPLINMUX60 */
24418 volatile ALT_SYSMGR_PINMUX_GPLINMUX61_t GPLINMUX61; /* ALT_SYSMGR_PINMUX_GPLINMUX61 */
24419 volatile ALT_SYSMGR_PINMUX_GPLINMUX62_t GPLINMUX62; /* ALT_SYSMGR_PINMUX_GPLINMUX62 */
24420 volatile ALT_SYSMGR_PINMUX_GPLINMUX63_t GPLINMUX63; /* ALT_SYSMGR_PINMUX_GPLINMUX63 */
24421 volatile ALT_SYSMGR_PINMUX_GPLINMUX64_t GPLINMUX64; /* ALT_SYSMGR_PINMUX_GPLINMUX64 */
24422 volatile ALT_SYSMGR_PINMUX_GPLINMUX65_t GPLINMUX65; /* ALT_SYSMGR_PINMUX_GPLINMUX65 */
24423 volatile ALT_SYSMGR_PINMUX_GPLINMUX66_t GPLINMUX66; /* ALT_SYSMGR_PINMUX_GPLINMUX66 */
24424 volatile ALT_SYSMGR_PINMUX_GPLINMUX67_t GPLINMUX67; /* ALT_SYSMGR_PINMUX_GPLINMUX67 */
24425 volatile ALT_SYSMGR_PINMUX_GPLINMUX68_t GPLINMUX68; /* ALT_SYSMGR_PINMUX_GPLINMUX68 */
24426 volatile ALT_SYSMGR_PINMUX_GPLINMUX69_t GPLINMUX69; /* ALT_SYSMGR_PINMUX_GPLINMUX69 */
24427 volatile ALT_SYSMGR_PINMUX_GPLINMUX70_t GPLINMUX70; /* ALT_SYSMGR_PINMUX_GPLINMUX70 */
24428 volatile ALT_SYSMGR_PINMUX_GPLMUX0_t GPLMUX0; /* ALT_SYSMGR_PINMUX_GPLMUX0 */
24429 volatile ALT_SYSMGR_PINMUX_GPLMUX1_t GPLMUX1; /* ALT_SYSMGR_PINMUX_GPLMUX1 */
24430 volatile ALT_SYSMGR_PINMUX_GPLMUX2_t GPLMUX2; /* ALT_SYSMGR_PINMUX_GPLMUX2 */
24431 volatile ALT_SYSMGR_PINMUX_GPLMUX3_t GPLMUX3; /* ALT_SYSMGR_PINMUX_GPLMUX3 */
24432 volatile ALT_SYSMGR_PINMUX_GPLMUX4_t GPLMUX4; /* ALT_SYSMGR_PINMUX_GPLMUX4 */
24433 volatile ALT_SYSMGR_PINMUX_GPLMUX5_t GPLMUX5; /* ALT_SYSMGR_PINMUX_GPLMUX5 */
24434 volatile ALT_SYSMGR_PINMUX_GPLMUX6_t GPLMUX6; /* ALT_SYSMGR_PINMUX_GPLMUX6 */
24435 volatile ALT_SYSMGR_PINMUX_GPLMUX7_t GPLMUX7; /* ALT_SYSMGR_PINMUX_GPLMUX7 */
24436 volatile ALT_SYSMGR_PINMUX_GPLMUX8_t GPLMUX8; /* ALT_SYSMGR_PINMUX_GPLMUX8 */
24437 volatile ALT_SYSMGR_PINMUX_GPLMUX9_t GPLMUX9; /* ALT_SYSMGR_PINMUX_GPLMUX9 */
24438 volatile ALT_SYSMGR_PINMUX_GPLMUX10_t GPLMUX10; /* ALT_SYSMGR_PINMUX_GPLMUX10 */
24439 volatile ALT_SYSMGR_PINMUX_GPLMUX11_t GPLMUX11; /* ALT_SYSMGR_PINMUX_GPLMUX11 */
24440 volatile ALT_SYSMGR_PINMUX_GPLMUX12_t GPLMUX12; /* ALT_SYSMGR_PINMUX_GPLMUX12 */
24441 volatile ALT_SYSMGR_PINMUX_GPLMUX13_t GPLMUX13; /* ALT_SYSMGR_PINMUX_GPLMUX13 */
24442 volatile ALT_SYSMGR_PINMUX_GPLMUX14_t GPLMUX14; /* ALT_SYSMGR_PINMUX_GPLMUX14 */
24443 volatile ALT_SYSMGR_PINMUX_GPLMUX15_t GPLMUX15; /* ALT_SYSMGR_PINMUX_GPLMUX15 */
24444 volatile ALT_SYSMGR_PINMUX_GPLMUX16_t GPLMUX16; /* ALT_SYSMGR_PINMUX_GPLMUX16 */
24445 volatile ALT_SYSMGR_PINMUX_GPLMUX17_t GPLMUX17; /* ALT_SYSMGR_PINMUX_GPLMUX17 */
24446 volatile ALT_SYSMGR_PINMUX_GPLMUX18_t GPLMUX18; /* ALT_SYSMGR_PINMUX_GPLMUX18 */
24447 volatile ALT_SYSMGR_PINMUX_GPLMUX19_t GPLMUX19; /* ALT_SYSMGR_PINMUX_GPLMUX19 */
24448 volatile ALT_SYSMGR_PINMUX_GPLMUX20_t GPLMUX20; /* ALT_SYSMGR_PINMUX_GPLMUX20 */
24449 volatile ALT_SYSMGR_PINMUX_GPLMUX21_t GPLMUX21; /* ALT_SYSMGR_PINMUX_GPLMUX21 */
24450 volatile ALT_SYSMGR_PINMUX_GPLMUX22_t GPLMUX22; /* ALT_SYSMGR_PINMUX_GPLMUX22 */
24451 volatile ALT_SYSMGR_PINMUX_GPLMUX23_t GPLMUX23; /* ALT_SYSMGR_PINMUX_GPLMUX23 */
24452 volatile ALT_SYSMGR_PINMUX_GPLMUX24_t GPLMUX24; /* ALT_SYSMGR_PINMUX_GPLMUX24 */
24453 volatile ALT_SYSMGR_PINMUX_GPLMUX25_t GPLMUX25; /* ALT_SYSMGR_PINMUX_GPLMUX25 */
24454 volatile ALT_SYSMGR_PINMUX_GPLMUX26_t GPLMUX26; /* ALT_SYSMGR_PINMUX_GPLMUX26 */
24455 volatile ALT_SYSMGR_PINMUX_GPLMUX27_t GPLMUX27; /* ALT_SYSMGR_PINMUX_GPLMUX27 */
24456 volatile ALT_SYSMGR_PINMUX_GPLMUX28_t GPLMUX28; /* ALT_SYSMGR_PINMUX_GPLMUX28 */
24457 volatile ALT_SYSMGR_PINMUX_GPLMUX29_t GPLMUX29; /* ALT_SYSMGR_PINMUX_GPLMUX29 */
24458 volatile ALT_SYSMGR_PINMUX_GPLMUX30_t GPLMUX30; /* ALT_SYSMGR_PINMUX_GPLMUX30 */
24459 volatile ALT_SYSMGR_PINMUX_GPLMUX31_t GPLMUX31; /* ALT_SYSMGR_PINMUX_GPLMUX31 */
24460 volatile ALT_SYSMGR_PINMUX_GPLMUX32_t GPLMUX32; /* ALT_SYSMGR_PINMUX_GPLMUX32 */
24461 volatile ALT_SYSMGR_PINMUX_GPLMUX33_t GPLMUX33; /* ALT_SYSMGR_PINMUX_GPLMUX33 */
24462 volatile ALT_SYSMGR_PINMUX_GPLMUX34_t GPLMUX34; /* ALT_SYSMGR_PINMUX_GPLMUX34 */
24463 volatile ALT_SYSMGR_PINMUX_GPLMUX35_t GPLMUX35; /* ALT_SYSMGR_PINMUX_GPLMUX35 */
24464 volatile ALT_SYSMGR_PINMUX_GPLMUX36_t GPLMUX36; /* ALT_SYSMGR_PINMUX_GPLMUX36 */
24465 volatile ALT_SYSMGR_PINMUX_GPLMUX37_t GPLMUX37; /* ALT_SYSMGR_PINMUX_GPLMUX37 */
24466 volatile ALT_SYSMGR_PINMUX_GPLMUX38_t GPLMUX38; /* ALT_SYSMGR_PINMUX_GPLMUX38 */
24467 volatile ALT_SYSMGR_PINMUX_GPLMUX39_t GPLMUX39; /* ALT_SYSMGR_PINMUX_GPLMUX39 */
24468 volatile ALT_SYSMGR_PINMUX_GPLMUX40_t GPLMUX40; /* ALT_SYSMGR_PINMUX_GPLMUX40 */
24469 volatile ALT_SYSMGR_PINMUX_GPLMUX41_t GPLMUX41; /* ALT_SYSMGR_PINMUX_GPLMUX41 */
24470 volatile ALT_SYSMGR_PINMUX_GPLMUX42_t GPLMUX42; /* ALT_SYSMGR_PINMUX_GPLMUX42 */
24471 volatile ALT_SYSMGR_PINMUX_GPLMUX43_t GPLMUX43; /* ALT_SYSMGR_PINMUX_GPLMUX43 */
24472 volatile ALT_SYSMGR_PINMUX_GPLMUX44_t GPLMUX44; /* ALT_SYSMGR_PINMUX_GPLMUX44 */
24473 volatile ALT_SYSMGR_PINMUX_GPLMUX45_t GPLMUX45; /* ALT_SYSMGR_PINMUX_GPLMUX45 */
24474 volatile ALT_SYSMGR_PINMUX_GPLMUX46_t GPLMUX46; /* ALT_SYSMGR_PINMUX_GPLMUX46 */
24475 volatile ALT_SYSMGR_PINMUX_GPLMUX47_t GPLMUX47; /* ALT_SYSMGR_PINMUX_GPLMUX47 */
24476 volatile ALT_SYSMGR_PINMUX_GPLMUX48_t GPLMUX48; /* ALT_SYSMGR_PINMUX_GPLMUX48 */
24477 volatile ALT_SYSMGR_PINMUX_GPLMUX49_t GPLMUX49; /* ALT_SYSMGR_PINMUX_GPLMUX49 */
24478 volatile ALT_SYSMGR_PINMUX_GPLMUX50_t GPLMUX50; /* ALT_SYSMGR_PINMUX_GPLMUX50 */
24479 volatile ALT_SYSMGR_PINMUX_GPLMUX51_t GPLMUX51; /* ALT_SYSMGR_PINMUX_GPLMUX51 */
24480 volatile ALT_SYSMGR_PINMUX_GPLMUX52_t GPLMUX52; /* ALT_SYSMGR_PINMUX_GPLMUX52 */
24481 volatile ALT_SYSMGR_PINMUX_GPLMUX53_t GPLMUX53; /* ALT_SYSMGR_PINMUX_GPLMUX53 */
24482 volatile ALT_SYSMGR_PINMUX_GPLMUX54_t GPLMUX54; /* ALT_SYSMGR_PINMUX_GPLMUX54 */
24483 volatile ALT_SYSMGR_PINMUX_GPLMUX55_t GPLMUX55; /* ALT_SYSMGR_PINMUX_GPLMUX55 */
24484 volatile ALT_SYSMGR_PINMUX_GPLMUX56_t GPLMUX56; /* ALT_SYSMGR_PINMUX_GPLMUX56 */
24485 volatile ALT_SYSMGR_PINMUX_GPLMUX57_t GPLMUX57; /* ALT_SYSMGR_PINMUX_GPLMUX57 */
24486 volatile ALT_SYSMGR_PINMUX_GPLMUX58_t GPLMUX58; /* ALT_SYSMGR_PINMUX_GPLMUX58 */
24487 volatile ALT_SYSMGR_PINMUX_GPLMUX59_t GPLMUX59; /* ALT_SYSMGR_PINMUX_GPLMUX59 */
24488 volatile ALT_SYSMGR_PINMUX_GPLMUX60_t GPLMUX60; /* ALT_SYSMGR_PINMUX_GPLMUX60 */
24489 volatile ALT_SYSMGR_PINMUX_GPLMUX61_t GPLMUX61; /* ALT_SYSMGR_PINMUX_GPLMUX61 */
24490 volatile ALT_SYSMGR_PINMUX_GPLMUX62_t GPLMUX62; /* ALT_SYSMGR_PINMUX_GPLMUX62 */
24491 volatile ALT_SYSMGR_PINMUX_GPLMUX63_t GPLMUX63; /* ALT_SYSMGR_PINMUX_GPLMUX63 */
24492 volatile ALT_SYSMGR_PINMUX_GPLMUX64_t GPLMUX64; /* ALT_SYSMGR_PINMUX_GPLMUX64 */
24493 volatile ALT_SYSMGR_PINMUX_GPLMUX65_t GPLMUX65; /* ALT_SYSMGR_PINMUX_GPLMUX65 */
24494 volatile ALT_SYSMGR_PINMUX_GPLMUX66_t GPLMUX66; /* ALT_SYSMGR_PINMUX_GPLMUX66 */
24495 volatile ALT_SYSMGR_PINMUX_GPLMUX67_t GPLMUX67; /* ALT_SYSMGR_PINMUX_GPLMUX67 */
24496 volatile ALT_SYSMGR_PINMUX_GPLMUX68_t GPLMUX68; /* ALT_SYSMGR_PINMUX_GPLMUX68 */
24497 volatile ALT_SYSMGR_PINMUX_GPLMUX69_t GPLMUX69; /* ALT_SYSMGR_PINMUX_GPLMUX69 */
24498 volatile ALT_SYSMGR_PINMUX_GPLMUX70_t GPLMUX70; /* ALT_SYSMGR_PINMUX_GPLMUX70 */
24499 volatile ALT_SYSMGR_PINMUX_NANDUSEFPGA_t NANDUSEFPGA; /* ALT_SYSMGR_PINMUX_NANDUSEFPGA */
24500 volatile uint32_t _pad_0x2f4_0x2f7; /* *UNDEFINED* */
24501 volatile ALT_SYSMGR_PINMUX_RGMII1USEFPGA_t RGMII1USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII1USEFPGA */
24502 volatile uint32_t _pad_0x2fc_0x303[2]; /* *UNDEFINED* */
24503 volatile ALT_SYSMGR_PINMUX_I2C0USEFPGA_t I2C0USEFPGA; /* ALT_SYSMGR_PINMUX_I2C0USEFPGA */
24504 volatile uint32_t _pad_0x308_0x313[3]; /* *UNDEFINED* */
24505 volatile ALT_SYSMGR_PINMUX_RGMII0USEFPGA_t RGMII0USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII0USEFPGA */
24506 volatile uint32_t _pad_0x318_0x323[3]; /* *UNDEFINED* */
24507 volatile ALT_SYSMGR_PINMUX_I2C3USEFPGA_t I2C3USEFPGA; /* ALT_SYSMGR_PINMUX_I2C3USEFPGA */
24508 volatile ALT_SYSMGR_PINMUX_I2C2USEFPGA_t I2C2USEFPGA; /* ALT_SYSMGR_PINMUX_I2C2USEFPGA */
24509 volatile ALT_SYSMGR_PINMUX_I2C1USEFPGA_t I2C1USEFPGA; /* ALT_SYSMGR_PINMUX_I2C1USEFPGA */
24510 volatile ALT_SYSMGR_PINMUX_SPIM1USEFPGA_t SPIM1USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM1USEFPGA */
24511 volatile uint32_t _pad_0x334_0x337; /* *UNDEFINED* */
24512 volatile ALT_SYSMGR_PINMUX_SPIM0USEFPGA_t SPIM0USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM0USEFPGA */
24513 volatile uint32_t _pad_0x33c_0x400[49]; /* *UNDEFINED* */
24514};
24515
24516/* The typedef declaration for register group ALT_SYSMGR_PINMUX. */
24517typedef volatile struct ALT_SYSMGR_PINMUX_s ALT_SYSMGR_PINMUX_t;
24518/* The struct declaration for the raw register contents of register group ALT_SYSMGR_PINMUX. */
24519 struct ALT_SYSMGR_PINMUX_raw_s
24520{
24521 volatile uint32_t EMACIO0; /* ALT_SYSMGR_PINMUX_EMACIO0 */
24522 volatile uint32_t EMACIO1; /* ALT_SYSMGR_PINMUX_EMACIO1 */
24523 volatile uint32_t EMACIO2; /* ALT_SYSMGR_PINMUX_EMACIO2 */
24524 volatile uint32_t EMACIO3; /* ALT_SYSMGR_PINMUX_EMACIO3 */
24525 volatile uint32_t EMACIO4; /* ALT_SYSMGR_PINMUX_EMACIO4 */
24526 volatile uint32_t EMACIO5; /* ALT_SYSMGR_PINMUX_EMACIO5 */
24527 volatile uint32_t EMACIO6; /* ALT_SYSMGR_PINMUX_EMACIO6 */
24528 volatile uint32_t EMACIO7; /* ALT_SYSMGR_PINMUX_EMACIO7 */
24529 volatile uint32_t EMACIO8; /* ALT_SYSMGR_PINMUX_EMACIO8 */
24530 volatile uint32_t EMACIO9; /* ALT_SYSMGR_PINMUX_EMACIO9 */
24531 volatile uint32_t EMACIO10; /* ALT_SYSMGR_PINMUX_EMACIO10 */
24532 volatile uint32_t EMACIO11; /* ALT_SYSMGR_PINMUX_EMACIO11 */
24533 volatile uint32_t EMACIO12; /* ALT_SYSMGR_PINMUX_EMACIO12 */
24534 volatile uint32_t EMACIO13; /* ALT_SYSMGR_PINMUX_EMACIO13 */
24535 volatile uint32_t EMACIO14; /* ALT_SYSMGR_PINMUX_EMACIO14 */
24536 volatile uint32_t EMACIO15; /* ALT_SYSMGR_PINMUX_EMACIO15 */
24537 volatile uint32_t EMACIO16; /* ALT_SYSMGR_PINMUX_EMACIO16 */
24538 volatile uint32_t EMACIO17; /* ALT_SYSMGR_PINMUX_EMACIO17 */
24539 volatile uint32_t EMACIO18; /* ALT_SYSMGR_PINMUX_EMACIO18 */
24540 volatile uint32_t EMACIO19; /* ALT_SYSMGR_PINMUX_EMACIO19 */
24541 volatile uint32_t FLASHIO0; /* ALT_SYSMGR_PINMUX_FLSHIO0 */
24542 volatile uint32_t FLASHIO1; /* ALT_SYSMGR_PINMUX_FLSHIO1 */
24543 volatile uint32_t FLASHIO2; /* ALT_SYSMGR_PINMUX_FLSHIO2 */
24544 volatile uint32_t FLASHIO3; /* ALT_SYSMGR_PINMUX_FLSHIO3 */
24545 volatile uint32_t FLASHIO4; /* ALT_SYSMGR_PINMUX_FLSHIO4 */
24546 volatile uint32_t FLASHIO5; /* ALT_SYSMGR_PINMUX_FLSHIO5 */
24547 volatile uint32_t FLASHIO6; /* ALT_SYSMGR_PINMUX_FLSHIO6 */
24548 volatile uint32_t FLASHIO7; /* ALT_SYSMGR_PINMUX_FLSHIO7 */
24549 volatile uint32_t FLASHIO8; /* ALT_SYSMGR_PINMUX_FLSHIO8 */
24550 volatile uint32_t FLASHIO9; /* ALT_SYSMGR_PINMUX_FLSHIO9 */
24551 volatile uint32_t FLASHIO10; /* ALT_SYSMGR_PINMUX_FLSHIO10 */
24552 volatile uint32_t FLASHIO11; /* ALT_SYSMGR_PINMUX_FLSHIO11 */
24553 volatile uint32_t GENERALIO0; /* ALT_SYSMGR_PINMUX_GENERALIO0 */
24554 volatile uint32_t GENERALIO1; /* ALT_SYSMGR_PINMUX_GENERALIO1 */
24555 volatile uint32_t GENERALIO2; /* ALT_SYSMGR_PINMUX_GENERALIO2 */
24556 volatile uint32_t GENERALIO3; /* ALT_SYSMGR_PINMUX_GENERALIO3 */
24557 volatile uint32_t GENERALIO4; /* ALT_SYSMGR_PINMUX_GENERALIO4 */
24558 volatile uint32_t GENERALIO5; /* ALT_SYSMGR_PINMUX_GENERALIO5 */
24559 volatile uint32_t GENERALIO6; /* ALT_SYSMGR_PINMUX_GENERALIO6 */
24560 volatile uint32_t GENERALIO7; /* ALT_SYSMGR_PINMUX_GENERALIO7 */
24561 volatile uint32_t GENERALIO8; /* ALT_SYSMGR_PINMUX_GENERALIO8 */
24562 volatile uint32_t GENERALIO9; /* ALT_SYSMGR_PINMUX_GENERALIO9 */
24563 volatile uint32_t GENERALIO10; /* ALT_SYSMGR_PINMUX_GENERALIO10 */
24564 volatile uint32_t GENERALIO11; /* ALT_SYSMGR_PINMUX_GENERALIO11 */
24565 volatile uint32_t GENERALIO12; /* ALT_SYSMGR_PINMUX_GENERALIO12 */
24566 volatile uint32_t GENERALIO13; /* ALT_SYSMGR_PINMUX_GENERALIO13 */
24567 volatile uint32_t GENERALIO14; /* ALT_SYSMGR_PINMUX_GENERALIO14 */
24568 volatile uint32_t GENERALIO15; /* ALT_SYSMGR_PINMUX_GENERALIO15 */
24569 volatile uint32_t GENERALIO16; /* ALT_SYSMGR_PINMUX_GENERALIO16 */
24570 volatile uint32_t GENERALIO17; /* ALT_SYSMGR_PINMUX_GENERALIO17 */
24571 volatile uint32_t GENERALIO18; /* ALT_SYSMGR_PINMUX_GENERALIO18 */
24572 volatile uint32_t GENERALIO19; /* ALT_SYSMGR_PINMUX_GENERALIO19 */
24573 volatile uint32_t GENERALIO20; /* ALT_SYSMGR_PINMUX_GENERALIO20 */
24574 volatile uint32_t GENERALIO21; /* ALT_SYSMGR_PINMUX_GENERALIO21 */
24575 volatile uint32_t GENERALIO22; /* ALT_SYSMGR_PINMUX_GENERALIO22 */
24576 volatile uint32_t GENERALIO23; /* ALT_SYSMGR_PINMUX_GENERALIO23 */
24577 volatile uint32_t GENERALIO24; /* ALT_SYSMGR_PINMUX_GENERALIO24 */
24578 volatile uint32_t GENERALIO25; /* ALT_SYSMGR_PINMUX_GENERALIO25 */
24579 volatile uint32_t GENERALIO26; /* ALT_SYSMGR_PINMUX_GENERALIO26 */
24580 volatile uint32_t GENERALIO27; /* ALT_SYSMGR_PINMUX_GENERALIO27 */
24581 volatile uint32_t GENERALIO28; /* ALT_SYSMGR_PINMUX_GENERALIO28 */
24582 volatile uint32_t GENERALIO29; /* ALT_SYSMGR_PINMUX_GENERALIO29 */
24583 volatile uint32_t GENERALIO30; /* ALT_SYSMGR_PINMUX_GENERALIO30 */
24584 volatile uint32_t GENERALIO31; /* ALT_SYSMGR_PINMUX_GENERALIO31 */
24585 volatile uint32_t MIXED1IO0; /* ALT_SYSMGR_PINMUX_MIXED1IO0 */
24586 volatile uint32_t MIXED1IO1; /* ALT_SYSMGR_PINMUX_MIXED1IO1 */
24587 volatile uint32_t MIXED1IO2; /* ALT_SYSMGR_PINMUX_MIXED1IO2 */
24588 volatile uint32_t MIXED1IO3; /* ALT_SYSMGR_PINMUX_MIXED1IO3 */
24589 volatile uint32_t MIXED1IO4; /* ALT_SYSMGR_PINMUX_MIXED1IO4 */
24590 volatile uint32_t MIXED1IO5; /* ALT_SYSMGR_PINMUX_MIXED1IO5 */
24591 volatile uint32_t MIXED1IO6; /* ALT_SYSMGR_PINMUX_MIXED1IO6 */
24592 volatile uint32_t MIXED1IO7; /* ALT_SYSMGR_PINMUX_MIXED1IO7 */
24593 volatile uint32_t MIXED1IO8; /* ALT_SYSMGR_PINMUX_MIXED1IO8 */
24594 volatile uint32_t MIXED1IO9; /* ALT_SYSMGR_PINMUX_MIXED1IO9 */
24595 volatile uint32_t MIXED1IO10; /* ALT_SYSMGR_PINMUX_MIXED1IO10 */
24596 volatile uint32_t MIXED1IO11; /* ALT_SYSMGR_PINMUX_MIXED1IO11 */
24597 volatile uint32_t MIXED1IO12; /* ALT_SYSMGR_PINMUX_MIXED1IO12 */
24598 volatile uint32_t MIXED1IO13; /* ALT_SYSMGR_PINMUX_MIXED1IO13 */
24599 volatile uint32_t MIXED1IO14; /* ALT_SYSMGR_PINMUX_MIXED1IO14 */
24600 volatile uint32_t MIXED1IO15; /* ALT_SYSMGR_PINMUX_MIXED1IO15 */
24601 volatile uint32_t MIXED1IO16; /* ALT_SYSMGR_PINMUX_MIXED1IO16 */
24602 volatile uint32_t MIXED1IO17; /* ALT_SYSMGR_PINMUX_MIXED1IO17 */
24603 volatile uint32_t MIXED1IO18; /* ALT_SYSMGR_PINMUX_MIXED1IO18 */
24604 volatile uint32_t MIXED1IO19; /* ALT_SYSMGR_PINMUX_MIXED1IO19 */
24605 volatile uint32_t MIXED1IO20; /* ALT_SYSMGR_PINMUX_MIXED1IO20 */
24606 volatile uint32_t MIXED1IO21; /* ALT_SYSMGR_PINMUX_MIXED1IO21 */
24607 volatile uint32_t MIXED2IO0; /* ALT_SYSMGR_PINMUX_MIXED2IO0 */
24608 volatile uint32_t MIXED2IO1; /* ALT_SYSMGR_PINMUX_MIXED2IO1 */
24609 volatile uint32_t MIXED2IO2; /* ALT_SYSMGR_PINMUX_MIXED2IO2 */
24610 volatile uint32_t MIXED2IO3; /* ALT_SYSMGR_PINMUX_MIXED2IO3 */
24611 volatile uint32_t MIXED2IO4; /* ALT_SYSMGR_PINMUX_MIXED2IO4 */
24612 volatile uint32_t MIXED2IO5; /* ALT_SYSMGR_PINMUX_MIXED2IO5 */
24613 volatile uint32_t MIXED2IO6; /* ALT_SYSMGR_PINMUX_MIXED2IO6 */
24614 volatile uint32_t MIXED2IO7; /* ALT_SYSMGR_PINMUX_MIXED2IO7 */
24615 volatile uint32_t GPLINMUX48; /* ALT_SYSMGR_PINMUX_GPLINMUX48 */
24616 volatile uint32_t GPLINMUX49; /* ALT_SYSMGR_PINMUX_GPLINMUX49 */
24617 volatile uint32_t GPLINMUX50; /* ALT_SYSMGR_PINMUX_GPLINMUX50 */
24618 volatile uint32_t GPLINMUX51; /* ALT_SYSMGR_PINMUX_GPLINMUX51 */
24619 volatile uint32_t GPLINMUX52; /* ALT_SYSMGR_PINMUX_GPLINMUX52 */
24620 volatile uint32_t GPLINMUX53; /* ALT_SYSMGR_PINMUX_GPLINMUX53 */
24621 volatile uint32_t GPLINMUX54; /* ALT_SYSMGR_PINMUX_GPLINMUX54 */
24622 volatile uint32_t GPLINMUX55; /* ALT_SYSMGR_PINMUX_GPLINMUX55 */
24623 volatile uint32_t GPLINMUX56; /* ALT_SYSMGR_PINMUX_GPLINMUX56 */
24624 volatile uint32_t GPLINMUX57; /* ALT_SYSMGR_PINMUX_GPLINMUX57 */
24625 volatile uint32_t GPLINMUX58; /* ALT_SYSMGR_PINMUX_GPLINMUX58 */
24626 volatile uint32_t GPLINMUX59; /* ALT_SYSMGR_PINMUX_GPLINMUX59 */
24627 volatile uint32_t GPLINMUX60; /* ALT_SYSMGR_PINMUX_GPLINMUX60 */
24628 volatile uint32_t GPLINMUX61; /* ALT_SYSMGR_PINMUX_GPLINMUX61 */
24629 volatile uint32_t GPLINMUX62; /* ALT_SYSMGR_PINMUX_GPLINMUX62 */
24630 volatile uint32_t GPLINMUX63; /* ALT_SYSMGR_PINMUX_GPLINMUX63 */
24631 volatile uint32_t GPLINMUX64; /* ALT_SYSMGR_PINMUX_GPLINMUX64 */
24632 volatile uint32_t GPLINMUX65; /* ALT_SYSMGR_PINMUX_GPLINMUX65 */
24633 volatile uint32_t GPLINMUX66; /* ALT_SYSMGR_PINMUX_GPLINMUX66 */
24634 volatile uint32_t GPLINMUX67; /* ALT_SYSMGR_PINMUX_GPLINMUX67 */
24635 volatile uint32_t GPLINMUX68; /* ALT_SYSMGR_PINMUX_GPLINMUX68 */
24636 volatile uint32_t GPLINMUX69; /* ALT_SYSMGR_PINMUX_GPLINMUX69 */
24637 volatile uint32_t GPLINMUX70; /* ALT_SYSMGR_PINMUX_GPLINMUX70 */
24638 volatile uint32_t GPLMUX0; /* ALT_SYSMGR_PINMUX_GPLMUX0 */
24639 volatile uint32_t GPLMUX1; /* ALT_SYSMGR_PINMUX_GPLMUX1 */
24640 volatile uint32_t GPLMUX2; /* ALT_SYSMGR_PINMUX_GPLMUX2 */
24641 volatile uint32_t GPLMUX3; /* ALT_SYSMGR_PINMUX_GPLMUX3 */
24642 volatile uint32_t GPLMUX4; /* ALT_SYSMGR_PINMUX_GPLMUX4 */
24643 volatile uint32_t GPLMUX5; /* ALT_SYSMGR_PINMUX_GPLMUX5 */
24644 volatile uint32_t GPLMUX6; /* ALT_SYSMGR_PINMUX_GPLMUX6 */
24645 volatile uint32_t GPLMUX7; /* ALT_SYSMGR_PINMUX_GPLMUX7 */
24646 volatile uint32_t GPLMUX8; /* ALT_SYSMGR_PINMUX_GPLMUX8 */
24647 volatile uint32_t GPLMUX9; /* ALT_SYSMGR_PINMUX_GPLMUX9 */
24648 volatile uint32_t GPLMUX10; /* ALT_SYSMGR_PINMUX_GPLMUX10 */
24649 volatile uint32_t GPLMUX11; /* ALT_SYSMGR_PINMUX_GPLMUX11 */
24650 volatile uint32_t GPLMUX12; /* ALT_SYSMGR_PINMUX_GPLMUX12 */
24651 volatile uint32_t GPLMUX13; /* ALT_SYSMGR_PINMUX_GPLMUX13 */
24652 volatile uint32_t GPLMUX14; /* ALT_SYSMGR_PINMUX_GPLMUX14 */
24653 volatile uint32_t GPLMUX15; /* ALT_SYSMGR_PINMUX_GPLMUX15 */
24654 volatile uint32_t GPLMUX16; /* ALT_SYSMGR_PINMUX_GPLMUX16 */
24655 volatile uint32_t GPLMUX17; /* ALT_SYSMGR_PINMUX_GPLMUX17 */
24656 volatile uint32_t GPLMUX18; /* ALT_SYSMGR_PINMUX_GPLMUX18 */
24657 volatile uint32_t GPLMUX19; /* ALT_SYSMGR_PINMUX_GPLMUX19 */
24658 volatile uint32_t GPLMUX20; /* ALT_SYSMGR_PINMUX_GPLMUX20 */
24659 volatile uint32_t GPLMUX21; /* ALT_SYSMGR_PINMUX_GPLMUX21 */
24660 volatile uint32_t GPLMUX22; /* ALT_SYSMGR_PINMUX_GPLMUX22 */
24661 volatile uint32_t GPLMUX23; /* ALT_SYSMGR_PINMUX_GPLMUX23 */
24662 volatile uint32_t GPLMUX24; /* ALT_SYSMGR_PINMUX_GPLMUX24 */
24663 volatile uint32_t GPLMUX25; /* ALT_SYSMGR_PINMUX_GPLMUX25 */
24664 volatile uint32_t GPLMUX26; /* ALT_SYSMGR_PINMUX_GPLMUX26 */
24665 volatile uint32_t GPLMUX27; /* ALT_SYSMGR_PINMUX_GPLMUX27 */
24666 volatile uint32_t GPLMUX28; /* ALT_SYSMGR_PINMUX_GPLMUX28 */
24667 volatile uint32_t GPLMUX29; /* ALT_SYSMGR_PINMUX_GPLMUX29 */
24668 volatile uint32_t GPLMUX30; /* ALT_SYSMGR_PINMUX_GPLMUX30 */
24669 volatile uint32_t GPLMUX31; /* ALT_SYSMGR_PINMUX_GPLMUX31 */
24670 volatile uint32_t GPLMUX32; /* ALT_SYSMGR_PINMUX_GPLMUX32 */
24671 volatile uint32_t GPLMUX33; /* ALT_SYSMGR_PINMUX_GPLMUX33 */
24672 volatile uint32_t GPLMUX34; /* ALT_SYSMGR_PINMUX_GPLMUX34 */
24673 volatile uint32_t GPLMUX35; /* ALT_SYSMGR_PINMUX_GPLMUX35 */
24674 volatile uint32_t GPLMUX36; /* ALT_SYSMGR_PINMUX_GPLMUX36 */
24675 volatile uint32_t GPLMUX37; /* ALT_SYSMGR_PINMUX_GPLMUX37 */
24676 volatile uint32_t GPLMUX38; /* ALT_SYSMGR_PINMUX_GPLMUX38 */
24677 volatile uint32_t GPLMUX39; /* ALT_SYSMGR_PINMUX_GPLMUX39 */
24678 volatile uint32_t GPLMUX40; /* ALT_SYSMGR_PINMUX_GPLMUX40 */
24679 volatile uint32_t GPLMUX41; /* ALT_SYSMGR_PINMUX_GPLMUX41 */
24680 volatile uint32_t GPLMUX42; /* ALT_SYSMGR_PINMUX_GPLMUX42 */
24681 volatile uint32_t GPLMUX43; /* ALT_SYSMGR_PINMUX_GPLMUX43 */
24682 volatile uint32_t GPLMUX44; /* ALT_SYSMGR_PINMUX_GPLMUX44 */
24683 volatile uint32_t GPLMUX45; /* ALT_SYSMGR_PINMUX_GPLMUX45 */
24684 volatile uint32_t GPLMUX46; /* ALT_SYSMGR_PINMUX_GPLMUX46 */
24685 volatile uint32_t GPLMUX47; /* ALT_SYSMGR_PINMUX_GPLMUX47 */
24686 volatile uint32_t GPLMUX48; /* ALT_SYSMGR_PINMUX_GPLMUX48 */
24687 volatile uint32_t GPLMUX49; /* ALT_SYSMGR_PINMUX_GPLMUX49 */
24688 volatile uint32_t GPLMUX50; /* ALT_SYSMGR_PINMUX_GPLMUX50 */
24689 volatile uint32_t GPLMUX51; /* ALT_SYSMGR_PINMUX_GPLMUX51 */
24690 volatile uint32_t GPLMUX52; /* ALT_SYSMGR_PINMUX_GPLMUX52 */
24691 volatile uint32_t GPLMUX53; /* ALT_SYSMGR_PINMUX_GPLMUX53 */
24692 volatile uint32_t GPLMUX54; /* ALT_SYSMGR_PINMUX_GPLMUX54 */
24693 volatile uint32_t GPLMUX55; /* ALT_SYSMGR_PINMUX_GPLMUX55 */
24694 volatile uint32_t GPLMUX56; /* ALT_SYSMGR_PINMUX_GPLMUX56 */
24695 volatile uint32_t GPLMUX57; /* ALT_SYSMGR_PINMUX_GPLMUX57 */
24696 volatile uint32_t GPLMUX58; /* ALT_SYSMGR_PINMUX_GPLMUX58 */
24697 volatile uint32_t GPLMUX59; /* ALT_SYSMGR_PINMUX_GPLMUX59 */
24698 volatile uint32_t GPLMUX60; /* ALT_SYSMGR_PINMUX_GPLMUX60 */
24699 volatile uint32_t GPLMUX61; /* ALT_SYSMGR_PINMUX_GPLMUX61 */
24700 volatile uint32_t GPLMUX62; /* ALT_SYSMGR_PINMUX_GPLMUX62 */
24701 volatile uint32_t GPLMUX63; /* ALT_SYSMGR_PINMUX_GPLMUX63 */
24702 volatile uint32_t GPLMUX64; /* ALT_SYSMGR_PINMUX_GPLMUX64 */
24703 volatile uint32_t GPLMUX65; /* ALT_SYSMGR_PINMUX_GPLMUX65 */
24704 volatile uint32_t GPLMUX66; /* ALT_SYSMGR_PINMUX_GPLMUX66 */
24705 volatile uint32_t GPLMUX67; /* ALT_SYSMGR_PINMUX_GPLMUX67 */
24706 volatile uint32_t GPLMUX68; /* ALT_SYSMGR_PINMUX_GPLMUX68 */
24707 volatile uint32_t GPLMUX69; /* ALT_SYSMGR_PINMUX_GPLMUX69 */
24708 volatile uint32_t GPLMUX70; /* ALT_SYSMGR_PINMUX_GPLMUX70 */
24709 volatile uint32_t NANDUSEFPGA; /* ALT_SYSMGR_PINMUX_NANDUSEFPGA */
24710 volatile uint32_t _pad_0x2f4_0x2f7; /* *UNDEFINED* */
24711 volatile uint32_t RGMII1USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII1USEFPGA */
24712 volatile uint32_t _pad_0x2fc_0x303[2]; /* *UNDEFINED* */
24713 volatile uint32_t I2C0USEFPGA; /* ALT_SYSMGR_PINMUX_I2C0USEFPGA */
24714 volatile uint32_t _pad_0x308_0x313[3]; /* *UNDEFINED* */
24715 volatile uint32_t RGMII0USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII0USEFPGA */
24716 volatile uint32_t _pad_0x318_0x323[3]; /* *UNDEFINED* */
24717 volatile uint32_t I2C3USEFPGA; /* ALT_SYSMGR_PINMUX_I2C3USEFPGA */
24718 volatile uint32_t I2C2USEFPGA; /* ALT_SYSMGR_PINMUX_I2C2USEFPGA */
24719 volatile uint32_t I2C1USEFPGA; /* ALT_SYSMGR_PINMUX_I2C1USEFPGA */
24720 volatile uint32_t SPIM1USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM1USEFPGA */
24721 volatile uint32_t _pad_0x334_0x337; /* *UNDEFINED* */
24722 volatile uint32_t SPIM0USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM0USEFPGA */
24723 volatile uint32_t _pad_0x33c_0x400[49]; /* *UNDEFINED* */
24724};
24725
24726/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_PINMUX. */
24727typedef volatile struct ALT_SYSMGR_PINMUX_raw_s ALT_SYSMGR_PINMUX_raw_t;
24728#endif /* __ASSEMBLY__ */
24729
24730
24731#ifndef __ASSEMBLY__
24732/*
24733 * WARNING: The C register and register group struct declarations are provided for
24734 * convenience and illustrative purposes. They should, however, be used with
24735 * caution as the C language standard provides no guarantees about the alignment or
24736 * atomicity of device memory accesses. The recommended practice for writing
24737 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24738 * alt_write_word() functions.
24739 *
24740 * The struct declaration for register group ALT_SYSMGR.
24741 */
24742 struct ALT_SYSMGR_s
24743{
24744 volatile ALT_SYSMGR_SILICONID1_t siliconid1; /* ALT_SYSMGR_SILICONID1 */
24745 volatile ALT_SYSMGR_SILICONID2_t siliconid2; /* ALT_SYSMGR_SILICONID2 */
24746 volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */
24747 volatile ALT_SYSMGR_WDDBG_t wddbg; /* ALT_SYSMGR_WDDBG */
24748 volatile ALT_SYSMGR_BOOT_t bootinfo; /* ALT_SYSMGR_BOOT */
24749 volatile ALT_SYSMGR_HPSINFO_t hpsinfo; /* ALT_SYSMGR_HPSINFO */
24750 volatile ALT_SYSMGR_PARITYINJ_t parityinj; /* ALT_SYSMGR_PARITYINJ */
24751 volatile ALT_SYSMGR_FPGAINTF_t fpgaintfgrp; /* ALT_SYSMGR_FPGAINTF */
24752 volatile ALT_SYSMGR_SCANMGR_t scanmgrgrp; /* ALT_SYSMGR_SCANMGR */
24753 volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
24754 volatile ALT_SYSMGR_FRZCTL_t frzctrl; /* ALT_SYSMGR_FRZCTL */
24755 volatile ALT_SYSMGR_EMAC_t emacgrp; /* ALT_SYSMGR_EMAC */
24756 volatile ALT_SYSMGR_DMA_t dmagrp; /* ALT_SYSMGR_DMA */
24757 volatile uint32_t _pad_0x78_0x7f[2]; /* *UNDEFINED* */
24758 volatile ALT_SYSMGR_ISW_t iswgrp; /* ALT_SYSMGR_ISW */
24759 volatile uint32_t _pad_0xa0_0xbf[8]; /* *UNDEFINED* */
24760 volatile ALT_SYSMGR_ROMCODE_t romcodegrp; /* ALT_SYSMGR_ROMCODE */
24761 volatile ALT_SYSMGR_ROMHW_t romhwgrp; /* ALT_SYSMGR_ROMHW */
24762 volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */
24763 volatile ALT_SYSMGR_SDMMC_t sdmmcgrp; /* ALT_SYSMGR_SDMMC */
24764 volatile ALT_SYSMGR_NAND_t nandgrp; /* ALT_SYSMGR_NAND */
24765 volatile ALT_SYSMGR_USB_t usbgrp; /* ALT_SYSMGR_USB */
24766 volatile uint32_t _pad_0x11c_0x13f[9]; /* *UNDEFINED* */
24767 volatile ALT_SYSMGR_ECC_t eccgrp; /* ALT_SYSMGR_ECC */
24768 volatile uint32_t _pad_0x180_0x3ff[160]; /* *UNDEFINED* */
24769 volatile ALT_SYSMGR_PINMUX_t pinmuxgrp; /* ALT_SYSMGR_PINMUX */
24770 volatile uint32_t _pad_0x800_0x4000[3584]; /* *UNDEFINED* */
24771};
24772
24773/* The typedef declaration for register group ALT_SYSMGR. */
24774typedef volatile struct ALT_SYSMGR_s ALT_SYSMGR_t;
24775/* The struct declaration for the raw register contents of register group ALT_SYSMGR. */
24776 struct ALT_SYSMGR_raw_s
24777{
24778 volatile uint32_t siliconid1; /* ALT_SYSMGR_SILICONID1 */
24779 volatile uint32_t siliconid2; /* ALT_SYSMGR_SILICONID2 */
24780 volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */
24781 volatile uint32_t wddbg; /* ALT_SYSMGR_WDDBG */
24782 volatile uint32_t bootinfo; /* ALT_SYSMGR_BOOT */
24783 volatile uint32_t hpsinfo; /* ALT_SYSMGR_HPSINFO */
24784 volatile uint32_t parityinj; /* ALT_SYSMGR_PARITYINJ */
24785 volatile ALT_SYSMGR_FPGAINTF_raw_t fpgaintfgrp; /* ALT_SYSMGR_FPGAINTF */
24786 volatile ALT_SYSMGR_SCANMGR_raw_t scanmgrgrp; /* ALT_SYSMGR_SCANMGR */
24787 volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
24788 volatile ALT_SYSMGR_FRZCTL_raw_t frzctrl; /* ALT_SYSMGR_FRZCTL */
24789 volatile ALT_SYSMGR_EMAC_raw_t emacgrp; /* ALT_SYSMGR_EMAC */
24790 volatile ALT_SYSMGR_DMA_raw_t dmagrp; /* ALT_SYSMGR_DMA */
24791 volatile uint32_t _pad_0x78_0x7f[2]; /* *UNDEFINED* */
24792 volatile ALT_SYSMGR_ISW_raw_t iswgrp; /* ALT_SYSMGR_ISW */
24793 volatile uint32_t _pad_0xa0_0xbf[8]; /* *UNDEFINED* */
24794 volatile ALT_SYSMGR_ROMCODE_raw_t romcodegrp; /* ALT_SYSMGR_ROMCODE */
24795 volatile ALT_SYSMGR_ROMHW_raw_t romhwgrp; /* ALT_SYSMGR_ROMHW */
24796 volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */
24797 volatile ALT_SYSMGR_SDMMC_raw_t sdmmcgrp; /* ALT_SYSMGR_SDMMC */
24798 volatile ALT_SYSMGR_NAND_raw_t nandgrp; /* ALT_SYSMGR_NAND */
24799 volatile ALT_SYSMGR_USB_raw_t usbgrp; /* ALT_SYSMGR_USB */
24800 volatile uint32_t _pad_0x11c_0x13f[9]; /* *UNDEFINED* */
24801 volatile ALT_SYSMGR_ECC_raw_t eccgrp; /* ALT_SYSMGR_ECC */
24802 volatile uint32_t _pad_0x180_0x3ff[160]; /* *UNDEFINED* */
24803 volatile ALT_SYSMGR_PINMUX_raw_t pinmuxgrp; /* ALT_SYSMGR_PINMUX */
24804 volatile uint32_t _pad_0x800_0x4000[3584]; /* *UNDEFINED* */
24805};
24806
24807/* The typedef declaration for the raw register contents of register group ALT_SYSMGR. */
24808typedef volatile struct ALT_SYSMGR_raw_s ALT_SYSMGR_raw_t;
24809#endif /* __ASSEMBLY__ */
24810
24811
24812#ifdef __cplusplus
24813}
24814#endif /* __cplusplus */
24815#endif /* __ALTERA_ALT_SYSMGR_H__ */
24816
ALT_SYSMGR_BOOT_s
Definition: alt_sysmgr.h:650
ALT_SYSMGR_DMA_CTL_s
Definition: alt_sysmgr.h:4392
ALT_SYSMGR_DMA_PERSECURITY_s
Definition: alt_sysmgr.h:4469
ALT_SYSMGR_DMA_raw_s
Definition: alt_sysmgr.h:4501
ALT_SYSMGR_DMA_s
Definition: alt_sysmgr.h:4492
ALT_SYSMGR_ECC_CAN0_s
Definition: alt_sysmgr.h:8617
ALT_SYSMGR_ECC_CAN1_s
Definition: alt_sysmgr.h:8797
ALT_SYSMGR_ECC_DMA_s
Definition: alt_sysmgr.h:8437
ALT_SYSMGR_ECC_EMAC0_s
Definition: alt_sysmgr.h:7953
ALT_SYSMGR_ECC_EMAC1_s
Definition: alt_sysmgr.h:8253
ALT_SYSMGR_ECC_L2_s
Definition: alt_sysmgr.h:7118
ALT_SYSMGR_ECC_NAND_s
Definition: alt_sysmgr.h:9206
ALT_SYSMGR_ECC_OCRAM_s
Definition: alt_sysmgr.h:7297
ALT_SYSMGR_ECC_QSPI_s
Definition: alt_sysmgr.h:9394
ALT_SYSMGR_ECC_SDMMC_s
Definition: alt_sysmgr.h:9687
ALT_SYSMGR_ECC_USB0_s
Definition: alt_sysmgr.h:7477
ALT_SYSMGR_ECC_USB1_s
Definition: alt_sysmgr.h:7657
ALT_SYSMGR_ECC_raw_s
Definition: alt_sysmgr.h:9739
ALT_SYSMGR_ECC_s
Definition: alt_sysmgr.h:9719
ALT_SYSMGR_EMAC_CTL_s
Definition: alt_sysmgr.h:3411
ALT_SYSMGR_EMAC_L3MST_s
Definition: alt_sysmgr.h:4052
ALT_SYSMGR_EMAC_raw_s
Definition: alt_sysmgr.h:4089
ALT_SYSMGR_EMAC_s
Definition: alt_sysmgr.h:4079
ALT_SYSMGR_FPGAINTF_GBL_s
Definition: alt_sysmgr.h:1376
ALT_SYSMGR_FPGAINTF_INDIV_s
Definition: alt_sysmgr.h:1781
ALT_SYSMGR_FPGAINTF_MODULE_s
Definition: alt_sysmgr.h:1927
ALT_SYSMGR_FPGAINTF_raw_s
Definition: alt_sysmgr.h:1964
ALT_SYSMGR_FPGAINTF_s
Definition: alt_sysmgr.h:1953
ALT_SYSMGR_FRZCTL_HIOCTL_s
Definition: alt_sysmgr.h:2852
ALT_SYSMGR_FRZCTL_HWCTL_s
Definition: alt_sysmgr.h:3122
ALT_SYSMGR_FRZCTL_SRC_s
Definition: alt_sysmgr.h:2956
ALT_SYSMGR_FRZCTL_VIOCTL_s
Definition: alt_sysmgr.h:2382
ALT_SYSMGR_FRZCTL_raw_s
Definition: alt_sysmgr.h:3160
ALT_SYSMGR_FRZCTL_s
Definition: alt_sysmgr.h:3147
ALT_SYSMGR_HPSINFO_s
Definition: alt_sysmgr.h:781
ALT_SYSMGR_ISW_HANDOFF_s
Definition: alt_sysmgr.h:4571
ALT_SYSMGR_ISW_raw_s
Definition: alt_sysmgr.h:4602
ALT_SYSMGR_ISW_s
Definition: alt_sysmgr.h:4594
ALT_SYSMGR_NAND_BOOTSTRAP_s
Definition: alt_sysmgr.h:6270
ALT_SYSMGR_NAND_L3MST_s
Definition: alt_sysmgr.h:6609
ALT_SYSMGR_NAND_raw_s
Definition: alt_sysmgr.h:6643
ALT_SYSMGR_NAND_s
Definition: alt_sysmgr.h:6634
ALT_SYSMGR_PARITYINJ_s
Definition: alt_sysmgr.h:1254
ALT_SYSMGR_PINMUX_EMACIO0_s
Definition: alt_sysmgr.h:9833
ALT_SYSMGR_PINMUX_EMACIO10_s
Definition: alt_sysmgr.h:10583
ALT_SYSMGR_PINMUX_EMACIO11_s
Definition: alt_sysmgr.h:10658
ALT_SYSMGR_PINMUX_EMACIO12_s
Definition: alt_sysmgr.h:10733
ALT_SYSMGR_PINMUX_EMACIO13_s
Definition: alt_sysmgr.h:10808
ALT_SYSMGR_PINMUX_EMACIO14_s
Definition: alt_sysmgr.h:10883
ALT_SYSMGR_PINMUX_EMACIO15_s
Definition: alt_sysmgr.h:10958
ALT_SYSMGR_PINMUX_EMACIO16_s
Definition: alt_sysmgr.h:11033
ALT_SYSMGR_PINMUX_EMACIO17_s
Definition: alt_sysmgr.h:11108
ALT_SYSMGR_PINMUX_EMACIO18_s
Definition: alt_sysmgr.h:11183
ALT_SYSMGR_PINMUX_EMACIO19_s
Definition: alt_sysmgr.h:11258
ALT_SYSMGR_PINMUX_EMACIO1_s
Definition: alt_sysmgr.h:9908
ALT_SYSMGR_PINMUX_EMACIO2_s
Definition: alt_sysmgr.h:9983
ALT_SYSMGR_PINMUX_EMACIO3_s
Definition: alt_sysmgr.h:10058
ALT_SYSMGR_PINMUX_EMACIO4_s
Definition: alt_sysmgr.h:10133
ALT_SYSMGR_PINMUX_EMACIO5_s
Definition: alt_sysmgr.h:10208
ALT_SYSMGR_PINMUX_EMACIO6_s
Definition: alt_sysmgr.h:10283
ALT_SYSMGR_PINMUX_EMACIO7_s
Definition: alt_sysmgr.h:10358
ALT_SYSMGR_PINMUX_EMACIO8_s
Definition: alt_sysmgr.h:10433
ALT_SYSMGR_PINMUX_EMACIO9_s
Definition: alt_sysmgr.h:10508
ALT_SYSMGR_PINMUX_FLSHIO0_s
Definition: alt_sysmgr.h:11333
ALT_SYSMGR_PINMUX_FLSHIO10_s
Definition: alt_sysmgr.h:12083
ALT_SYSMGR_PINMUX_FLSHIO11_s
Definition: alt_sysmgr.h:12158
ALT_SYSMGR_PINMUX_FLSHIO1_s
Definition: alt_sysmgr.h:11408
ALT_SYSMGR_PINMUX_FLSHIO2_s
Definition: alt_sysmgr.h:11483
ALT_SYSMGR_PINMUX_FLSHIO3_s
Definition: alt_sysmgr.h:11558
ALT_SYSMGR_PINMUX_FLSHIO4_s
Definition: alt_sysmgr.h:11633
ALT_SYSMGR_PINMUX_FLSHIO5_s
Definition: alt_sysmgr.h:11708
ALT_SYSMGR_PINMUX_FLSHIO6_s
Definition: alt_sysmgr.h:11783
ALT_SYSMGR_PINMUX_FLSHIO7_s
Definition: alt_sysmgr.h:11858
ALT_SYSMGR_PINMUX_FLSHIO8_s
Definition: alt_sysmgr.h:11933
ALT_SYSMGR_PINMUX_FLSHIO9_s
Definition: alt_sysmgr.h:12008
ALT_SYSMGR_PINMUX_GENERALIO0_s
Definition: alt_sysmgr.h:12233
ALT_SYSMGR_PINMUX_GENERALIO10_s
Definition: alt_sysmgr.h:12983
ALT_SYSMGR_PINMUX_GENERALIO11_s
Definition: alt_sysmgr.h:13058
ALT_SYSMGR_PINMUX_GENERALIO12_s
Definition: alt_sysmgr.h:13133
ALT_SYSMGR_PINMUX_GENERALIO13_s
Definition: alt_sysmgr.h:13208
ALT_SYSMGR_PINMUX_GENERALIO14_s
Definition: alt_sysmgr.h:13283
ALT_SYSMGR_PINMUX_GENERALIO15_s
Definition: alt_sysmgr.h:13358
ALT_SYSMGR_PINMUX_GENERALIO16_s
Definition: alt_sysmgr.h:13433
ALT_SYSMGR_PINMUX_GENERALIO17_s
Definition: alt_sysmgr.h:13508
ALT_SYSMGR_PINMUX_GENERALIO18_s
Definition: alt_sysmgr.h:13583
ALT_SYSMGR_PINMUX_GENERALIO19_s
Definition: alt_sysmgr.h:13658
ALT_SYSMGR_PINMUX_GENERALIO1_s
Definition: alt_sysmgr.h:12308
ALT_SYSMGR_PINMUX_GENERALIO20_s
Definition: alt_sysmgr.h:13733
ALT_SYSMGR_PINMUX_GENERALIO21_s
Definition: alt_sysmgr.h:13808
ALT_SYSMGR_PINMUX_GENERALIO22_s
Definition: alt_sysmgr.h:13883
ALT_SYSMGR_PINMUX_GENERALIO23_s
Definition: alt_sysmgr.h:13958
ALT_SYSMGR_PINMUX_GENERALIO24_s
Definition: alt_sysmgr.h:14033
ALT_SYSMGR_PINMUX_GENERALIO25_s
Definition: alt_sysmgr.h:14108
ALT_SYSMGR_PINMUX_GENERALIO26_s
Definition: alt_sysmgr.h:14183
ALT_SYSMGR_PINMUX_GENERALIO27_s
Definition: alt_sysmgr.h:14258
ALT_SYSMGR_PINMUX_GENERALIO28_s
Definition: alt_sysmgr.h:14333
ALT_SYSMGR_PINMUX_GENERALIO29_s
Definition: alt_sysmgr.h:14408
ALT_SYSMGR_PINMUX_GENERALIO2_s
Definition: alt_sysmgr.h:12383
ALT_SYSMGR_PINMUX_GENERALIO30_s
Definition: alt_sysmgr.h:14483
ALT_SYSMGR_PINMUX_GENERALIO31_s
Definition: alt_sysmgr.h:14558
ALT_SYSMGR_PINMUX_GENERALIO3_s
Definition: alt_sysmgr.h:12458
ALT_SYSMGR_PINMUX_GENERALIO4_s
Definition: alt_sysmgr.h:12533
ALT_SYSMGR_PINMUX_GENERALIO5_s
Definition: alt_sysmgr.h:12608
ALT_SYSMGR_PINMUX_GENERALIO6_s
Definition: alt_sysmgr.h:12683
ALT_SYSMGR_PINMUX_GENERALIO7_s
Definition: alt_sysmgr.h:12758
ALT_SYSMGR_PINMUX_GENERALIO8_s
Definition: alt_sysmgr.h:12833
ALT_SYSMGR_PINMUX_GENERALIO9_s
Definition: alt_sysmgr.h:12908
ALT_SYSMGR_PINMUX_GPLINMUX48_s
Definition: alt_sysmgr.h:16880
ALT_SYSMGR_PINMUX_GPLINMUX49_s
Definition: alt_sysmgr.h:16952
ALT_SYSMGR_PINMUX_GPLINMUX50_s
Definition: alt_sysmgr.h:17024
ALT_SYSMGR_PINMUX_GPLINMUX51_s
Definition: alt_sysmgr.h:17096
ALT_SYSMGR_PINMUX_GPLINMUX52_s
Definition: alt_sysmgr.h:17168
ALT_SYSMGR_PINMUX_GPLINMUX53_s
Definition: alt_sysmgr.h:17240
ALT_SYSMGR_PINMUX_GPLINMUX54_s
Definition: alt_sysmgr.h:17312
ALT_SYSMGR_PINMUX_GPLINMUX55_s
Definition: alt_sysmgr.h:17384
ALT_SYSMGR_PINMUX_GPLINMUX56_s
Definition: alt_sysmgr.h:17456
ALT_SYSMGR_PINMUX_GPLINMUX57_s
Definition: alt_sysmgr.h:17528
ALT_SYSMGR_PINMUX_GPLINMUX58_s
Definition: alt_sysmgr.h:17600
ALT_SYSMGR_PINMUX_GPLINMUX59_s
Definition: alt_sysmgr.h:17672
ALT_SYSMGR_PINMUX_GPLINMUX60_s
Definition: alt_sysmgr.h:17744
ALT_SYSMGR_PINMUX_GPLINMUX61_s
Definition: alt_sysmgr.h:17816
ALT_SYSMGR_PINMUX_GPLINMUX62_s
Definition: alt_sysmgr.h:17888
ALT_SYSMGR_PINMUX_GPLINMUX63_s
Definition: alt_sysmgr.h:17960
ALT_SYSMGR_PINMUX_GPLINMUX64_s
Definition: alt_sysmgr.h:18032
ALT_SYSMGR_PINMUX_GPLINMUX65_s
Definition: alt_sysmgr.h:18104
ALT_SYSMGR_PINMUX_GPLINMUX66_s
Definition: alt_sysmgr.h:18176
ALT_SYSMGR_PINMUX_GPLINMUX67_s
Definition: alt_sysmgr.h:18248
ALT_SYSMGR_PINMUX_GPLINMUX68_s
Definition: alt_sysmgr.h:18320
ALT_SYSMGR_PINMUX_GPLINMUX69_s
Definition: alt_sysmgr.h:18392
ALT_SYSMGR_PINMUX_GPLINMUX70_s
Definition: alt_sysmgr.h:18464
ALT_SYSMGR_PINMUX_GPLMUX0_s
Definition: alt_sysmgr.h:18537
ALT_SYSMGR_PINMUX_GPLMUX10_s
Definition: alt_sysmgr.h:19267
ALT_SYSMGR_PINMUX_GPLMUX11_s
Definition: alt_sysmgr.h:19340
ALT_SYSMGR_PINMUX_GPLMUX12_s
Definition: alt_sysmgr.h:19413
ALT_SYSMGR_PINMUX_GPLMUX13_s
Definition: alt_sysmgr.h:19486
ALT_SYSMGR_PINMUX_GPLMUX14_s
Definition: alt_sysmgr.h:19559
ALT_SYSMGR_PINMUX_GPLMUX15_s
Definition: alt_sysmgr.h:19632
ALT_SYSMGR_PINMUX_GPLMUX16_s
Definition: alt_sysmgr.h:19705
ALT_SYSMGR_PINMUX_GPLMUX17_s
Definition: alt_sysmgr.h:19778
ALT_SYSMGR_PINMUX_GPLMUX18_s
Definition: alt_sysmgr.h:19851
ALT_SYSMGR_PINMUX_GPLMUX19_s
Definition: alt_sysmgr.h:19924
ALT_SYSMGR_PINMUX_GPLMUX1_s
Definition: alt_sysmgr.h:18610
ALT_SYSMGR_PINMUX_GPLMUX20_s
Definition: alt_sysmgr.h:19997
ALT_SYSMGR_PINMUX_GPLMUX21_s
Definition: alt_sysmgr.h:20070
ALT_SYSMGR_PINMUX_GPLMUX22_s
Definition: alt_sysmgr.h:20143
ALT_SYSMGR_PINMUX_GPLMUX23_s
Definition: alt_sysmgr.h:20216
ALT_SYSMGR_PINMUX_GPLMUX24_s
Definition: alt_sysmgr.h:20289
ALT_SYSMGR_PINMUX_GPLMUX25_s
Definition: alt_sysmgr.h:20362
ALT_SYSMGR_PINMUX_GPLMUX26_s
Definition: alt_sysmgr.h:20435
ALT_SYSMGR_PINMUX_GPLMUX27_s
Definition: alt_sysmgr.h:20508
ALT_SYSMGR_PINMUX_GPLMUX28_s
Definition: alt_sysmgr.h:20581
ALT_SYSMGR_PINMUX_GPLMUX29_s
Definition: alt_sysmgr.h:20654
ALT_SYSMGR_PINMUX_GPLMUX2_s
Definition: alt_sysmgr.h:18683
ALT_SYSMGR_PINMUX_GPLMUX30_s
Definition: alt_sysmgr.h:20727
ALT_SYSMGR_PINMUX_GPLMUX31_s
Definition: alt_sysmgr.h:20800
ALT_SYSMGR_PINMUX_GPLMUX32_s
Definition: alt_sysmgr.h:20873
ALT_SYSMGR_PINMUX_GPLMUX33_s
Definition: alt_sysmgr.h:20946
ALT_SYSMGR_PINMUX_GPLMUX34_s
Definition: alt_sysmgr.h:21019
ALT_SYSMGR_PINMUX_GPLMUX35_s
Definition: alt_sysmgr.h:21092
ALT_SYSMGR_PINMUX_GPLMUX36_s
Definition: alt_sysmgr.h:21165
ALT_SYSMGR_PINMUX_GPLMUX37_s
Definition: alt_sysmgr.h:21238
ALT_SYSMGR_PINMUX_GPLMUX38_s
Definition: alt_sysmgr.h:21311
ALT_SYSMGR_PINMUX_GPLMUX39_s
Definition: alt_sysmgr.h:21384
ALT_SYSMGR_PINMUX_GPLMUX3_s
Definition: alt_sysmgr.h:18756
ALT_SYSMGR_PINMUX_GPLMUX40_s
Definition: alt_sysmgr.h:21457
ALT_SYSMGR_PINMUX_GPLMUX41_s
Definition: alt_sysmgr.h:21530
ALT_SYSMGR_PINMUX_GPLMUX42_s
Definition: alt_sysmgr.h:21603
ALT_SYSMGR_PINMUX_GPLMUX43_s
Definition: alt_sysmgr.h:21676
ALT_SYSMGR_PINMUX_GPLMUX44_s
Definition: alt_sysmgr.h:21749
ALT_SYSMGR_PINMUX_GPLMUX45_s
Definition: alt_sysmgr.h:21822
ALT_SYSMGR_PINMUX_GPLMUX46_s
Definition: alt_sysmgr.h:21895
ALT_SYSMGR_PINMUX_GPLMUX47_s
Definition: alt_sysmgr.h:21968
ALT_SYSMGR_PINMUX_GPLMUX48_s
Definition: alt_sysmgr.h:22041
ALT_SYSMGR_PINMUX_GPLMUX49_s
Definition: alt_sysmgr.h:22114
ALT_SYSMGR_PINMUX_GPLMUX4_s
Definition: alt_sysmgr.h:18829
ALT_SYSMGR_PINMUX_GPLMUX50_s
Definition: alt_sysmgr.h:22187
ALT_SYSMGR_PINMUX_GPLMUX51_s
Definition: alt_sysmgr.h:22260
ALT_SYSMGR_PINMUX_GPLMUX52_s
Definition: alt_sysmgr.h:22333
ALT_SYSMGR_PINMUX_GPLMUX53_s
Definition: alt_sysmgr.h:22406
ALT_SYSMGR_PINMUX_GPLMUX54_s
Definition: alt_sysmgr.h:22479
ALT_SYSMGR_PINMUX_GPLMUX55_s
Definition: alt_sysmgr.h:22552
ALT_SYSMGR_PINMUX_GPLMUX56_s
Definition: alt_sysmgr.h:22625
ALT_SYSMGR_PINMUX_GPLMUX57_s
Definition: alt_sysmgr.h:22698
ALT_SYSMGR_PINMUX_GPLMUX58_s
Definition: alt_sysmgr.h:22771
ALT_SYSMGR_PINMUX_GPLMUX59_s
Definition: alt_sysmgr.h:22844
ALT_SYSMGR_PINMUX_GPLMUX5_s
Definition: alt_sysmgr.h:18902
ALT_SYSMGR_PINMUX_GPLMUX60_s
Definition: alt_sysmgr.h:22917
ALT_SYSMGR_PINMUX_GPLMUX61_s
Definition: alt_sysmgr.h:22990
ALT_SYSMGR_PINMUX_GPLMUX62_s
Definition: alt_sysmgr.h:23063
ALT_SYSMGR_PINMUX_GPLMUX63_s
Definition: alt_sysmgr.h:23136
ALT_SYSMGR_PINMUX_GPLMUX64_s
Definition: alt_sysmgr.h:23209
ALT_SYSMGR_PINMUX_GPLMUX65_s
Definition: alt_sysmgr.h:23282
ALT_SYSMGR_PINMUX_GPLMUX66_s
Definition: alt_sysmgr.h:23355
ALT_SYSMGR_PINMUX_GPLMUX67_s
Definition: alt_sysmgr.h:23428
ALT_SYSMGR_PINMUX_GPLMUX68_s
Definition: alt_sysmgr.h:23501
ALT_SYSMGR_PINMUX_GPLMUX69_s
Definition: alt_sysmgr.h:23574
ALT_SYSMGR_PINMUX_GPLMUX6_s
Definition: alt_sysmgr.h:18975
ALT_SYSMGR_PINMUX_GPLMUX70_s
Definition: alt_sysmgr.h:23647
ALT_SYSMGR_PINMUX_GPLMUX7_s
Definition: alt_sysmgr.h:19048
ALT_SYSMGR_PINMUX_GPLMUX8_s
Definition: alt_sysmgr.h:19121
ALT_SYSMGR_PINMUX_GPLMUX9_s
Definition: alt_sysmgr.h:19194
ALT_SYSMGR_PINMUX_I2C0USEFPGA_s
Definition: alt_sysmgr.h:23860
ALT_SYSMGR_PINMUX_I2C1USEFPGA_s
Definition: alt_sysmgr.h:24144
ALT_SYSMGR_PINMUX_I2C2USEFPGA_s
Definition: alt_sysmgr.h:24073
ALT_SYSMGR_PINMUX_I2C3USEFPGA_s
Definition: alt_sysmgr.h:24002
ALT_SYSMGR_PINMUX_MIXED1IO0_s
Definition: alt_sysmgr.h:14633
ALT_SYSMGR_PINMUX_MIXED1IO10_s
Definition: alt_sysmgr.h:15383
ALT_SYSMGR_PINMUX_MIXED1IO11_s
Definition: alt_sysmgr.h:15458
ALT_SYSMGR_PINMUX_MIXED1IO12_s
Definition: alt_sysmgr.h:15533
ALT_SYSMGR_PINMUX_MIXED1IO13_s
Definition: alt_sysmgr.h:15608
ALT_SYSMGR_PINMUX_MIXED1IO14_s
Definition: alt_sysmgr.h:15683
ALT_SYSMGR_PINMUX_MIXED1IO15_s
Definition: alt_sysmgr.h:15758
ALT_SYSMGR_PINMUX_MIXED1IO16_s
Definition: alt_sysmgr.h:15833
ALT_SYSMGR_PINMUX_MIXED1IO17_s
Definition: alt_sysmgr.h:15908
ALT_SYSMGR_PINMUX_MIXED1IO18_s
Definition: alt_sysmgr.h:15983
ALT_SYSMGR_PINMUX_MIXED1IO19_s
Definition: alt_sysmgr.h:16058
ALT_SYSMGR_PINMUX_MIXED1IO1_s
Definition: alt_sysmgr.h:14708
ALT_SYSMGR_PINMUX_MIXED1IO20_s
Definition: alt_sysmgr.h:16133
ALT_SYSMGR_PINMUX_MIXED1IO21_s
Definition: alt_sysmgr.h:16208
ALT_SYSMGR_PINMUX_MIXED1IO2_s
Definition: alt_sysmgr.h:14783
ALT_SYSMGR_PINMUX_MIXED1IO3_s
Definition: alt_sysmgr.h:14858
ALT_SYSMGR_PINMUX_MIXED1IO4_s
Definition: alt_sysmgr.h:14933
ALT_SYSMGR_PINMUX_MIXED1IO5_s
Definition: alt_sysmgr.h:15008
ALT_SYSMGR_PINMUX_MIXED1IO6_s
Definition: alt_sysmgr.h:15083
ALT_SYSMGR_PINMUX_MIXED1IO7_s
Definition: alt_sysmgr.h:15158
ALT_SYSMGR_PINMUX_MIXED1IO8_s
Definition: alt_sysmgr.h:15233
ALT_SYSMGR_PINMUX_MIXED1IO9_s
Definition: alt_sysmgr.h:15308
ALT_SYSMGR_PINMUX_MIXED2IO0_s
Definition: alt_sysmgr.h:16283
ALT_SYSMGR_PINMUX_MIXED2IO1_s
Definition: alt_sysmgr.h:16358
ALT_SYSMGR_PINMUX_MIXED2IO2_s
Definition: alt_sysmgr.h:16433
ALT_SYSMGR_PINMUX_MIXED2IO3_s
Definition: alt_sysmgr.h:16508
ALT_SYSMGR_PINMUX_MIXED2IO4_s
Definition: alt_sysmgr.h:16583
ALT_SYSMGR_PINMUX_MIXED2IO5_s
Definition: alt_sysmgr.h:16658
ALT_SYSMGR_PINMUX_MIXED2IO6_s
Definition: alt_sysmgr.h:16733
ALT_SYSMGR_PINMUX_MIXED2IO7_s
Definition: alt_sysmgr.h:16808
ALT_SYSMGR_PINMUX_NANDUSEFPGA_s
Definition: alt_sysmgr.h:23718
ALT_SYSMGR_PINMUX_RGMII0USEFPGA_s
Definition: alt_sysmgr.h:23931
ALT_SYSMGR_PINMUX_RGMII1USEFPGA_s
Definition: alt_sysmgr.h:23789
ALT_SYSMGR_PINMUX_SPIM0USEFPGA_s
Definition: alt_sysmgr.h:24286
ALT_SYSMGR_PINMUX_SPIM1USEFPGA_s
Definition: alt_sysmgr.h:24215
ALT_SYSMGR_PINMUX_raw_s
Definition: alt_sysmgr.h:24520
ALT_SYSMGR_PINMUX_s
Definition: alt_sysmgr.h:24310
ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_s
Definition: alt_sysmgr.h:5015
ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s
Definition: alt_sysmgr.h:4812
ALT_SYSMGR_ROMCODE_CTL_s
Definition: alt_sysmgr.h:4747
ALT_SYSMGR_ROMCODE_INITSWLASTLD_s
Definition: alt_sysmgr.h:4953
ALT_SYSMGR_ROMCODE_INITSWSTATE_s
Definition: alt_sysmgr.h:4891
ALT_SYSMGR_ROMCODE_WARMRAM_CRC_s
Definition: alt_sysmgr.h:5396
ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_s
Definition: alt_sysmgr.h:5176
ALT_SYSMGR_ROMCODE_WARMRAM_EN_s
Definition: alt_sysmgr.h:5110
ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_s
Definition: alt_sysmgr.h:5318
ALT_SYSMGR_ROMCODE_WARMRAM_LEN_s
Definition: alt_sysmgr.h:5251
ALT_SYSMGR_ROMCODE_WARMRAM_raw_s
Definition: alt_sysmgr.h:5434
ALT_SYSMGR_ROMCODE_WARMRAM_s
Definition: alt_sysmgr.h:5421
ALT_SYSMGR_ROMCODE_raw_s
Definition: alt_sysmgr.h:5474
ALT_SYSMGR_ROMCODE_s
Definition: alt_sysmgr.h:5460
ALT_SYSMGR_ROMHW_CTL_s
Definition: alt_sysmgr.h:5629
ALT_SYSMGR_ROMHW_raw_s
Definition: alt_sysmgr.h:5662
ALT_SYSMGR_ROMHW_s
Definition: alt_sysmgr.h:5654
ALT_SYSMGR_SCANMGR_CTL_s
Definition: alt_sysmgr.h:2057
ALT_SYSMGR_SCANMGR_raw_s
Definition: alt_sysmgr.h:2089
ALT_SYSMGR_SCANMGR_s
Definition: alt_sysmgr.h:2081
ALT_SYSMGR_SDMMC_CTL_s
Definition: alt_sysmgr.h:5914
ALT_SYSMGR_SDMMC_L3MST_s
Definition: alt_sysmgr.h:6082
ALT_SYSMGR_SDMMC_raw_s
Definition: alt_sysmgr.h:6118
ALT_SYSMGR_SDMMC_s
Definition: alt_sysmgr.h:6109
ALT_SYSMGR_SILICONID1_s
Definition: alt_sysmgr.h:155
ALT_SYSMGR_SILICONID2_s
Definition: alt_sysmgr.h:216
ALT_SYSMGR_USB_L3MST_s
Definition: alt_sysmgr.h:6955
ALT_SYSMGR_USB_raw_s
Definition: alt_sysmgr.h:6994
ALT_SYSMGR_USB_s
Definition: alt_sysmgr.h:6986
ALT_SYSMGR_WDDBG_s
Definition: alt_sysmgr.h:384
ALT_SYSMGR_raw_s
Definition: alt_sysmgr.h:24777
ALT_SYSMGR_s
Definition: alt_sysmgr.h:24743