RTEMS: cpukit/score/cpu/m68k/include/rtems/m68k/m68302.h Source File

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m68302.h
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1
14/*
15 * COPYRIGHT 1995 David W. Glessner.
16 *
17 * Redistribution and use in source and binary forms are permitted
18 * provided that the following conditions are met:
19 * 1. Redistribution of source code and documentation must retain
20 * the above copyright notice, this list of conditions and the
21 * following disclaimer.
22 * 2. The name of the author may not be used to endorse or promote
23 * products derived from this software without specific prior
24 * written permission.
25 *
26 * This software is provided "AS IS" without warranty of any kind,
27 * either expressed or implied, including, but not limited to, the
28 * implied warranties of merchantability, title and fitness for a
29 * particular purpose.
30 *
31 *------------------------------------------------------------------
32 */
33
34#ifndef _RTEMS_M68K_M68302_H
35#define _RTEMS_M68K_M68302_H
36
37/*
38 * BAR - Base Address Register
39 * Section 2.7
40 */
41#define M302_BAR (*((volatile uint16_t *) 0xf2))
42
43/*
44 * SCR - System Control Register
45 * Section 3.8.1
46 */
47#define M302_SCR (*((volatile uint32_t *) 0xf4))
48/*
49 * SCR bits
50 */
51#define RBIT_SCR_IPA 0x08000000
52#define RBIT_SCR_HWT 0x04000000
53#define RBIT_SCR_WPV 0x02000000
54#define RBIT_SCR_ADC 0x01000000
55
56#define RBIT_SCR_ERRE 0x00400000
57#define RBIT_SCR_VGE 0x00200000
58#define RBIT_SCR_WPVE 0x00100000
59#define RBIT_SCR_RMCST 0x00080000
60#define RBIT_SCR_EMWS 0x00040000
61#define RBIT_SCR_ADCE 0x00020000
62#define RBIT_SCR_BCLM 0x00010000
63
64#define RBIT_SCR_FRZW 0x00008000
65#define RBIT_SCR_FRZ2 0x00004000
66#define RBIT_SCR_FRZ1 0x00002000
67#define RBIT_SCR_SAM 0x00001000
68#define RBIT_SCR_HWDEN 0x00000800
69#define RBIT_SCR_HWDCN2 0x00000400
70#define RBIT_SCR_HWDCN1 0x00000200 /* 512 clocks */
71#define RBIT_SCR_HWDCN0 0x00000100 /* 128 clocks */
72
73#define RBIT_SCR_LPREC 0x00000080
74#define RBIT_SCR_LPP16 0x00000040
75#define RBIT_SCR_LPEN 0x00000020
76#define RBIT_SCR_LPCLKDIV 0x0000001f
77
78
79/*
80 * 68000 interrupt and trap vector numbers
81 */
82#define M68K_IVEC_BUS_ERROR 2
83#define M68K_IVEC_ADDRESS_ERROR 3
84#define M68K_IVEC_ILLEGAL_OPCODE 4
85#define M68K_IVEC_ZERO_DIVIDE 5
86#define M68K_IVEC_CHK 6
87#define M68K_IVEC_TRAPV 7
88#define M68K_IVEC_PRIVILEGE 8
89#define M68K_IVEC_TRACE 9
90#define M68K_IVEC_LINE_A 10
91#define M68K_IVEC_LINE_F 11
92/* Unassigned, Reserved 12-14 */
93#define M68K_IVEC_UNINITIALIZED_INT 15
94/* Unassigned, Reserved 16-23 */
95#define M68K_IVEC_SPURIOUS_INT 24
96
97#define M68K_IVEC_LEVEL1_AUTOVECTOR 25
98#define M68K_IVEC_LEVEL2_AUTOVECTOR 26
99#define M68K_IVEC_LEVEL3_AUTOVECTOR 27
100#define M68K_IVEC_LEVEL4_AUTOVECTOR 28
101#define M68K_IVEC_LEVEL5_AUTOVECTOR 29
102#define M68K_IVEC_LEVEL6_AUTOVECTOR 30
103#define M68K_IVEC_LEVEL7_AUTOVECTOR 31
104
105#define M68K_IVEC_TRAP0 32
106#define M68K_IVEC_TRAP1 33
107#define M68K_IVEC_TRAP2 34
108#define M68K_IVEC_TRAP3 35
109#define M68K_IVEC_TRAP4 36
110#define M68K_IVEC_TRAP5 37
111#define M68K_IVEC_TRAP6 38
112#define M68K_IVEC_TRAP7 39
113#define M68K_IVEC_TRAP8 40
114#define M68K_IVEC_TRAP9 41
115#define M68K_IVEC_TRAP10 42
116#define M68K_IVEC_TRAP11 43
117#define M68K_IVEC_TRAP12 44
118#define M68K_IVEC_TRAP13 45
119#define M68K_IVEC_TRAP14 46
120#define M68K_IVEC_TRAP15 47
121/*
122 * Unassigned, Reserved 48-59
123 *
124 * Note: Vectors 60-63 are used by the MC68302 (e.g. BAR, SCR).
125 */
126
127/*
128 * MC68302 Interrupt Vectors
129 * Section 3.2
130 */
131enum m68302_ivec_e {
132 M302_IVEC_ERR =0,
133 M302_IVEC_PB8 =1, /* General-Purpose Interrupt 0 */
134 M302_IVEC_SMC2 =2,
135 M302_IVEC_SMC1 =3,
136 M302_IVEC_TIMER3 =4,
137 M302_IVEC_SCP =5,
138 M302_IVEC_TIMER2 =6,
139 M302_IVEC_PB9 =7, /* General-Purpose Interrupt 1 */
140 M302_IVEC_SCC3 =8,
141 M302_IVEC_TIMER1 =9,
142 M302_IVEC_SCC2 =10,
143 M302_IVEC_IDMA =11,
144 M302_IVEC_SDMA =12, /* SDMA Channels Bus Error */
145 M302_IVEC_SCC1 =13,
146 M302_IVEC_PB10 =14, /* General-Purpose Interrupt 2 */
147 M302_IVEC_PB11 =15, /* General-Purpose Interrupt 3 */
148 M302_IVEC_IRQ1 =17, /* External Device */
149 M302_IVEC_IRQ6 =22, /* External Device */
150 M302_IVEC_IRQ7 =23 /* External Device */
151};
152
153
154/*
155 * GIMR - Global Interrupt Mode Register
156 * Section 3.2.5.1
157 */
158#define RBIT_GIMR_MOD (1<<15)
159#define RBIT_GIMR_IV7 (1<<14)
160#define RBIT_GIMR_IV6 (1<<13)
161#define RBIT_GIMR_IV1 (1<<12)
162#define RBIT_GIMR_ET7 (1<<10)
163#define RBIT_GIMR_ET6 (1<<9)
164#define RBIT_GIMR_ET1 (1<<8)
165#define RBIT_GIMR_VECTOR (7<<5)
166
167/*
168 * IPR - Interrupt Pending Register (Section 3.2.5.2)
169 * IMR - Interrupt Mask Register (Section 3.2.5.3)
170 * ISR - Interrupt In-Service Register (Section 3.2.5.4)
171 */
172#define RBIT_IPR_PB11 (1<<15)
173#define RBIT_IPR_PB10 (1<<14)
174#define RBIT_IPR_SCC1 (1<<13)
175#define RBIT_IPR_SDMA (1<<12)
176#define RBIT_IPR_IDMA (1<<11)
177#define RBIT_IPR_SCC2 (1<<10)
178#define RBIT_IPR_TIMER1 (1<<9)
179#define RBIT_IPR_SCC3 (1<<8)
180#define RBIT_IPR_PB9 (1<<7)
181#define RBIT_IPR_TIMER2 (1<<6)
182#define RBIT_IPR_SCP (1<<5)
183#define RBIT_IPR_TIMER3 (1<<4)
184#define RBIT_IPR_SMC1 (1<<3)
185#define RBIT_IPR_SMC2 (1<<2)
186#define RBIT_IPR_PB8 (1<<1)
187#define RBIT_IPR_ERR (1<<0)
188
189#define RBIT_ISR_PB11 (1<<15)
190#define RBIT_ISR_PB10 (1<<14)
191#define RBIT_ISR_SCC1 (1<<13)
192#define RBIT_ISR_SDMA (1<<12)
193#define RBIT_ISR_IDMA (1<<11)
194#define RBIT_ISR_SCC2 (1<<10)
195#define RBIT_ISR_TIMER1 (1<<9)
196#define RBIT_ISR_SCC3 (1<<8)
197#define RBIT_ISR_PB9 (1<<7)
198#define RBIT_ISR_TIMER2 (1<<6)
199#define RBIT_ISR_SCP (1<<5)
200#define RBIT_ISR_TIMER3 (1<<4)
201#define RBIT_ISR_SMC1 (1<<3)
202#define RBIT_ISR_SMC2 (1<<2)
203#define RBIT_ISR_PB8 (1<<1)
204
205#define RBIT_IMR_PB11 (1<<15) /* PB11 Interrupt Mask */
206#define RBIT_IMR_PB10 (1<<14) /* PB10 Interrupt Mask */
207#define RBIT_IMR_SCC1 (1<<13) /* SCC1 Interrupt Mask */
208#define RBIT_IMR_SDMA (1<<12) /* SDMA Interrupt Mask */
209#define RBIT_IMR_IDMA (1<<11) /* IDMA Interrupt Mask */
210#define RBIT_IMR_SCC2 (1<<10) /* SCC2 Interrupt Mask */
211#define RBIT_IMR_TIMER1 (1<<9) /* TIMER1 Interrupt Mask */
212#define RBIT_IMR_SCC3 (1<<8) /* SCC3 Interrupt Mask */
213#define RBIT_IMR_PB9 (1<<7) /* PB9 Interrupt Mask */
214#define RBIT_IMR_TIMER2 (1<<6) /* TIMER2 Interrupt Mask */
215#define RBIT_IMR_SCP (1<<5) /* SCP Interrupt Mask */
216#define RBIT_IMR_TIMER3 (1<<4) /* TIMER3 Interrupt Mask */
217#define RBIT_IMR_SMC1 (1<<3) /* SMC1 Interrupt Mask */
218#define RBIT_IMR_SMC2 (1<<2) /* SMC2 Interrupt Mask */
219#define RBIT_IMR_PB8 (1<<1) /* PB8 Interrupt Mask */
220
221
222/*
223 * DRAM Refresh
224 * Section 3.9
225 *
226 * The DRAM refresh memory map replaces the SCC2 Tx BD 6 and Tx BD 7
227 * structures in the parameter RAM.
228 *
229 * Access to the DRAM registers can be accomplished by
230 * the following approach:
231 *
232 * volatile m302_DRAM_refresh_t *dram;
233 * dram = (volatile m302_DRAM_refresh_t *) &m302.scc2.bd.tx[6];
234 *
235 * Then simply use pointer references (e.g. dram->count = 3).
236 */
237 typedef struct {
238 uint16_t dram_high; /* DRAM high address and FC */
239 uint16_t dram_low; /* DRAM low address */
240 uint16_t increment; /* increment step (bytes/row) */
241 uint16_t count; /* RAM refresh cycle count (#rows) */
242 uint16_t t_ptr_h; /* temporary refresh high addr & FC */
243 uint16_t t_ptr_l; /* temporary refresh low address */
244 uint16_t t_count; /* temporary refresh cycles count */
245 uint16_t res; /* reserved */
246} m302_DRAM_refresh_t;
247
248
249/*
250 * TMR - Timer Mode Register (for timers 1 and 2)
251 * Section 3.5.2.1
252 */
253#define RBIT_TMR_ICLK_STOP (0<<1)
254#define RBIT_TMR_ICLK_MASTER (1<<1)
255#define RBIT_TMR_ICLK_MASTER16 (2<<1)
256#define RBIT_TMR_ICLK_TIN (3<<1)
257
258#define RBIT_TMR_OM (1<<5)
259#define RBIT_TMR_ORI (1<<4)
260#define RBIT_TMR_FRR (1<<3)
261#define RBIT_TMR_RST (1<<0)
262
263
264/*
265 * TER - Timer Event Register (for timers 1 and 2)
266 * Section 3.5.2.5
267 */
268#define RBIT_TER_REF (1<<1) /* Output Reference Event */
269#define RBIT_TER_CAP (1<<0) /* Capture Event */
270
271
272/*
273 * SCC Buffer Descriptors and Buffer Descriptors Table
274 * Section 4.5.5
275 */
276 typedef struct m302_SCC_bd {
277 uint16_t status; /* status and control */
278 uint16_t length; /* data length */
279 volatile uint8_t *buffer; /* data buffer pointer */
280} m302_SCC_bd_t;
281
282 typedef struct {
283 m302_SCC_bd_t rx[8]; /* receive buffer descriptors */
284 m302_SCC_bd_t tx[8]; /* transmit buffer descriptors */
285} m302_SCC_bd_table_t;
286
287
288/*
289 * SCC Parameter RAM (offset 0x080 from an SCC Base)
290 * Section 4.5.6
291 *
292 * Each SCC parameter RAM area begins at offset 0x80 from each SCC base
293 * area (0x400, 0x500, or 0x600 from the dual-port RAM base).
294 *
295 * Offsets 0x9c-0xbf from each SCC base area compose the protocol-specific
296 * portion of the SCC parameter RAM.
297 */
298 typedef struct {
299 uint8_t rfcr; /* Rx Function Code */
300 uint8_t tfcr; /* Tx Function Code */
301 uint16_t mrblr; /* Maximum Rx Buffer Length */
302 uint16_t _rstate; /* Rx Internal State */
303 uint8_t res2;
304 uint8_t rbd; /* Rx Internal Buffer Number */
305 uint32_t _rdptr; /* Rx Internal Data Pointer */
306 uint16_t _rcount; /* Rx Internal Byte Count */
307 uint16_t _rtmp; /* Rx Temp */
308 uint16_t _tstate; /* Tx Internal State */
309 uint8_t res7;
310 uint8_t tbd; /* Tx Internal Buffer Number */
311 uint32_t _tdptr; /* Tx Internal Data Pointer */
312 uint16_t _tcount; /* Tx Internal Byte Count */
313 uint16_t _ttmp; /* Tx Temp */
314} m302_SCC_parameters_t;
315
316/*
317 * UART-Specific SCC Parameter RAM
318 * Section 4.5.11.3
319 */
320 typedef struct {
321 uint16_t max_idl; /* Maximum IDLE Characters (rx) */
322 uint16_t idlc; /* Temporary rx IDLE counter */
323 uint16_t brkcr; /* Break Count Register (tx) */
324 uint16_t parec; /* Receive Parity Error Counter */
325 uint16_t frmec; /* Receive Framing Error Counter */
326 uint16_t nosec; /* Receive Noise Counter */
327 uint16_t brkec; /* Receive Break Condition Counter */
328 uint16_t uaddr1; /* UART ADDRESS Character 1 */
329 uint16_t uaddr2; /* UART ADDRESS Character 2 */
330 uint16_t rccr; /* Receive Control Character Register */
331 uint16_t character[8]; /* Control Characters 1 through 8*/
332} m302_SCC_UartSpecific_t;
333/*
334 * This definition allows for the checking of receive buffers
335 * for errors.
336 */
337
338#define RCV_ERR 0x003F
339
340/*
341 * UART receive buffer descriptor bit definitions.
342 * Section 4.5.11.14
343 */
344#define RBIT_UART_CTRL (1<<11) /* buffer contains a control char */
345#define RBIT_UART_ADDR (1<<10) /* first byte contains an address */
346#define RBIT_UART_MATCH (1<<9) /* indicates which addr char matched */
347#define RBIT_UART_IDLE (1<<8) /* buffer closed due to IDLE sequence */
348#define RBIT_UART_BR (1<<5) /* break sequence was received */
349#define RBIT_UART_FR (1<<4) /* framing error was received */
350#define RBIT_UART_PR (1<<3) /* parity error was received */
351#define RBIT_UART_OV (1<<1) /* receiver overrun occurred */
352#define RBIT_UART_CD (1<<0) /* carrier detect lost */
353#define RBIT_UART_STATUS 0x003B /* all status bits */
354
355/*
356 * UART transmit buffer descriptor bit definitions.
357 * Section 4.5.11.15
358 */
359#define RBIT_UART_CR (1<<11) /* clear-to-send report
360 * this results in two idle bits
361 * between back-to-back frames
362 */
363#define RBIT_UART_A (1<<10) /* buffer contains address characters
364 * only valid in multidrop mode (UM0=1)
365 */
366#define RBIT_UART_PREAMBLE (1<<9) /* send preamble before data */
367#define RBIT_UART_CTS_LOST (1<<0) /* CTS lost */
368
369/*
370 * UART event register
371 * Section 4.5.11.16
372 */
373#define M302_UART_EV_CTS (1<<7) /* CTS status changed */
374#define M302_UART_EV_CD (1<<6) /* carrier detect status changed */
375#define M302_UART_EV_IDL (1<<5) /* IDLE sequence status changed */
376#define M302_UART_EV_BRK (1<<4) /* break character was received */
377#define M302_UART_EV_CCR (1<<3) /* control character received */
378#define M302_UART_EV_TX (1<<1) /* buffer has been transmitted */
379#define M302_UART_EV_RX (1<<0) /* buffer has been received */
380
381
382/*
383 * HDLC-Specific SCC Parameter RAM
384 * Section 4.5.12.3
385 *
386 * c_mask_l should be 0xF0B8 for 16-bit CRC, 0xdebb for 32-bit CRC
387 * c_mask_h is a don't care for 16-bit CRC, 0x20E2 for 32-bit CRC
388 */
389typedef struct {
390 uint16_t rcrc_l; /* Temp Receive CRC Low */
391 uint16_t rcrc_h; /* Temp Receive CRC High */
392 uint16_t c_mask_l; /* CRC Mask Low */
393 uint16_t c_mask_h; /* CRC Mask High */
394 uint16_t tcrc_l; /* Temp Transmit CRC Low */
395 uint16_t tcrc_h; /* Temp Transmit CRC High */
396
397 uint16_t disfc; /* Discard Frame Counter */
398 uint16_t crcec; /* CRC Error Counter */
399 uint16_t abtsc; /* Abort Sequence Counter */
400 uint16_t nmarc; /* Nonmatching Address Received Cntr */
401 uint16_t retrc; /* Frame Retransmission Counter */
402
403 uint16_t mflr; /* Maximum Frame Length Register */
404 uint16_t max_cnt; /* Maximum_Length Counter */
405
406 uint16_t hmask; /* User Defined Frame Address Mask */
407 uint16_t haddr1; /* User Defined Frame Address */
408 uint16_t haddr2; /* " */
409 uint16_t haddr3; /* " */
410 uint16_t haddr4; /* " */
411} m302_SCC_HdlcSpecific_t;
412/*
413 * HDLC receiver buffer descriptor bit definitions
414 * Section 4.5.12.10
415 */
416#define RBIT_HDLC_EMPTY_BIT 0x8000 /* buffer associated with BD is empty */
417#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in a frame */
418#define RBIT_HDLC_FIRST_BIT 0x0400 /* buffer is first in a frame */
419#define RBIT_HDLC_FRAME_LEN 0x0020 /* receiver frame length violation */
420#define RBIT_HDLC_NONOCT_Rx 0x0010 /* received non-octet aligned frame */
421#define RBIT_HDLC_ABORT_SEQ 0x0008 /* received abort sequence */
422#define RBIT_HDLC_CRC_ERROR 0x0004 /* frame contains a CRC error */
423#define RBIT_HDLC_OVERRUN 0x0002 /* receiver overrun occurred */
424#define RBIT_HDLC_CD_LOST 0x0001 /* carrier detect lost */
425
426/*
427 * HDLC transmit buffer descriptor bit definitions
428 * Section 4.5.12.11
429 */
430#define RBIT_HDLC_READY_BIT 0x8000 /* buffer is ready to transmit */
431#define RBIT_HDLC_EXT_BUFFER 0x4000 /* buffer is in external memory */
432#define RBIT_HDLC_WRAP_BIT 0x2000 /* last buffer in bd table, so wrap */
433#define RBIT_HDLC_WAKE_UP 0x1000 /* interrupt when buffer serviced */
434#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in the frame */
435#define RBIT_HDLC_TxCRC_BIT 0x0400 /* transmit a CRC sequence */
436#define RBIT_HDLC_UNDERRUN 0x0002 /* transmitter underrun */
437#define RBIT_HDLC_CTS_LOST 0x0001 /* CTS lost */
438
439/*
440 * HDLC event register bit definitions
441 * Section 4.5.12.12
442 */
443#define RBIT_HDLC_CTS 0x80 /* CTS status changed */
444#define RBIT_HDLC_CD 0x40 /* carrier detect status changed */
445#define RBIT_HDLC_IDL 0x20 /* IDLE sequence status changed */
446#define RBIT_HDLC_TXE 0x10 /* transmit error */
447#define RBIT_HDLC_RXF 0x08 /* received frame */
448#define RBIT_HDLC_BSY 0x04 /* frame rcvd and discarded due to
449 * lack of buffers
450 */
451#define RBIT_HDLC_TXB 0x02 /* buffer has been transmitted */
452#define RBIT_HDLC_RXB 0x01 /* received buffer */
453
454
455
456typedef struct {
457 m302_SCC_bd_table_t bd; /* +000 Buffer Descriptor Table */
458 m302_SCC_parameters_t parm; /* +080 Common Parameter RAM */
459 union { /* +09C Protocol-Specific Parm RAM */
460 m302_SCC_UartSpecific_t uart;
461 m302_SCC_HdlcSpecific_t hdlc;
462 } prot;
463 uint8_t res[0x040]; /* +0C0 reserved, (not implemented) */
464} m302_SCC_t;
465
466
467/*
468 * Common SCC Registers
469 */
470typedef struct {
471 uint16_t res1;
472 uint16_t scon; /* SCC Configuration Register 4.5.2 */
473 uint16_t scm; /* SCC Mode Register 4.5.3 */
474 uint16_t dsr; /* SCC Data Synchronization Register 4.5.4 */
475 uint8_t scce; /* SCC Event Register 4.5.8.1 */
476 uint8_t res2;
477 uint8_t sccm; /* SCC Mask Register 4.5.8.2 */
478 uint8_t res3;
479 uint8_t sccs; /* SCC Status Register 4.5.8.3 */
480 uint8_t res4;
481 uint16_t res5;
482} m302_SCC_Registers_t;
483
484/*
485 * SCON - SCC Configuration Register
486 * Section 4.5.2
487 */
488#define RBIT_SCON_WOMS (1<<15) /* Wired-OR Mode Select (NMSI mode only)
489 * When set, the TXD driver is an
490 * open-drain output */
491#define RBIT_SCON_EXTC (1<<14) /* External Clock Source */
492#define RBIT_SCON_TCS (1<<13) /* Transmit Clock Source */
493#define RBIT_SCON_RCS (1<<12) /* Receive Clock Source */
494
495/*
496 * SCM - SCC Mode Register bit definitions
497 * Section 4.5.3
498 * The parameter-specific mode bits occupy bits 15 through 6.
499 */
500#define RBIT_SCM_ENR (1<<3) /* Enable receiver */
501#define RBIT_SCM_ENT (1<<2) /* Enable transmitter */
502
503
504/*
505 * Internal MC68302 Registers
506 * starts at offset 0x800 from dual-port RAM base
507 * Section 2.8
508 */
509typedef struct {
510 /* offset +800 */
511 uint16_t res0;
512 uint16_t cmr; /* IDMA Channel Mode Register */
513 uint32_t sapr; /* IDMA Source Address Pointer */
514 uint32_t dapr; /* IDMA Destination Address Pointer */
515 uint16_t bcr; /* IDMA Byte Count Register */
516 uint8_t csr; /* IDMA Channel Status Register */
517 uint8_t res1;
518 uint8_t fcr; /* IDMA Function Code Register */
519 uint8_t res2;
520
521 /* offset +812 */
522 uint16_t gimr; /* Global Interrupt Mode Register */
523 uint16_t ipr; /* Interrupt Pending Register */
524 uint16_t imr; /* Interrupt Mask Register */
525 uint16_t isr; /* Interrupt In-Service Register */
526 uint16_t res3;
527 uint16_t res4;
528
529 /* offset +81e */
530 uint16_t pacnt; /* Port A Control Register */
531 uint16_t paddr; /* Port A Data Direction Register */
532 uint16_t padat; /* Port A Data Register */
533 uint16_t pbcnt; /* Port B Control Register */
534 uint16_t pbddr; /* Port B Data Direction Register */
535 uint16_t pbdat; /* Port B Data Register */
536 uint16_t res5;
537
538 /* offset +82c */
539 uint16_t res6;
540 uint16_t res7;
541
542 uint16_t br0; /* Base Register (CS0) */
543 uint16_t or0; /* Option Register (CS0) */
544 uint16_t br1; /* Base Register (CS1) */
545 uint16_t or1; /* Option Register (CS1) */
546 uint16_t br2; /* Base Register (CS2) */
547 uint16_t or2; /* Option Register (CS2) */
548 uint16_t br3; /* Base Register (CS3) */
549 uint16_t or3; /* Option Register (CS3) */
550
551 /* offset +840 */
552 uint16_t tmr1; /* Timer Unit 1 Mode Register */
553 uint16_t trr1; /* Timer Unit 1 Reference Register */
554 uint16_t tcr1; /* Timer Unit 1 Capture Register */
555 uint16_t tcn1; /* Timer Unit 1 Counter */
556 uint8_t res8;
557 uint8_t ter1; /* Timer Unit 1 Event Register */
558 uint16_t wrr; /* Watchdog Reference Register */
559 uint16_t wcn; /* Watchdog Counter */
560 uint16_t res9;
561 uint16_t tmr2; /* Timer Unit 2 Mode Register */
562 uint16_t trr2; /* Timer Unit 2 Reference Register */
563 uint16_t tcr2; /* Timer Unit 2 Capture Register */
564 uint16_t tcn2; /* Timer Unit 2 Counter */
565 uint8_t resa;
566 uint8_t ter2; /* Timer Unit 2 Event Register */
567 uint16_t resb;
568 uint16_t resc;
569 uint16_t resd;
570
571 /* offset +860 */
572 uint8_t cr; /* Command Register */
573 uint8_t rese[0x1f];
574
575 /* offset +880, +890, +8a0 */
576 m302_SCC_Registers_t scc[3]; /* SCC1, SCC2, SCC3 Registers */
577
578 /* offset +8b0 */
579 uint16_t spmode; /* SCP,SMC Mode and Clock Cntrl Reg */
580 uint16_t simask; /* Serial Interface Mask Register */
581 uint16_t simode; /* Serial Interface Mode Register */
582} m302_internalReg_t ;
583
584
585/*
586 * MC68302 dual-port RAM structure.
587 * (Includes System RAM, Parameter RAM, and Internal Registers).
588 * Section 2.8
589 */
590typedef struct {
591 uint8_t mem[0x240]; /* +000 User Data Memory */
592 uint8_t res1[0x1c0]; /* +240 reserved, (not implemented) */
593 m302_SCC_t scc1; /* +400 SCC1 */
594 m302_SCC_t scc2; /* +500 SCC2 */
595 m302_SCC_t scc3; /* +600 SCC3 */
596 uint8_t res2[0x100]; /* +700 reserved, (not implemented) */
597 m302_internalReg_t reg; /* +800 68302 Internal Registers */
598} m302_dualPortRAM_t;
599
600/* some useful defines the some of the registers above */
601
602
603/* ----
604 MC68302 Chip Select Registers
605 p3-46 2nd Edition
606
607 */
608#define BR_ENABLED 1
609#define BR_DISABLED 0
610#define BR_FC_NULL 0
611#define BR_READ_ONLY 0
612#define BR_READ_WRITE 2
613#define OR_DTACK_0 0x0000
614#define OR_DTACK_1 0x2000
615#define OR_DTACK_2 0x4000
616#define OR_DTACK_3 0x6000
617#define OR_DTACK_4 0x8000
618#define OR_DTACK_5 0xA000
619#define OR_DTACK_6 0xC000
620#define OR_DTACK_EXT 0xE000
621#define OR_SIZE_64K 0x1FE0
622#define OR_SIZE_128K 0x1FC0
623#define OR_SIZE_256K 0x1F80
624#define OR_SIZE_512K 0x1F00
625#define OR_SIZE_1M 0x1E00
626#define OR_SIZE_2M 0x1C00
627#define OR_MASK_RW 0x0000
628#define OR_NO_MASK_RW 0x0002
629#define OR_MASK_FC 0x0000
630#define OR_NO_MASK_FC 0x0001
631
632#define MAKE_BR(base_address, enable, rw, fc) \
633 ((base_address >> 11) | fc | rw | enable)
634
635#define MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask) \
636 (DtAck | ((~(bsize - 1) & 0x00FFFFFF) >> 11) | FC_Mask | RW_Mask)
637
638#define __REG_CAT(r, n) r ## n
639#define WRITE_BR(csel, base_address, enable, rw, fc) \
640 __REG_CAT(m302.reg.br, csel) = MAKE_BR(base_address, enable, rw, fc)
641#define WRITE_OR(csel, bsize, DtAck, RW_Mask, FC_Mask) \
642 __REG_CAT(m302.reg.or, csel) = MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask)
643
644/* ----
645 MC68302 Watchdog Timer Enable Bit
646
647 */
648#define WATCHDOG_ENABLE (1)
649#define WATCHDOG_TRIGGER() (m302.reg.wrr = 0x10 | WATCHDOG_ENABLE, m302.reg.wcn = 0)
650#define WATCHDOG_TOGGLE() (m302.reg.wcn = WATCHDOG_TIMEOUT_PERIOD)
651#define DISABLE_WATCHDOG() (m302.reg.wrr = 0)
652
653/*
654 * Declare the variable that's used to reference the variables in
655 * the dual-port RAM.
656 */
657extern volatile m302_dualPortRAM_t m302;
658
659#endif
m302_DRAM_refresh_t
Definition: m68302.h:237
m302_SCC_HdlcSpecific_t
Definition: m68302.h:384
m302_SCC_Registers_t
Definition: m68302.h:463
m302_SCC_UartSpecific_t
Definition: m68302.h:320
m302_SCC_bd_table_t
Definition: m68302.h:282
m302_SCC_bd
Definition: m68302.h:276
m302_SCC_parameters_t
Definition: m68302.h:298
m302_SCC_t
Definition: m68302.h:449
m302_dualPortRAM_t
Definition: m68302.h:581
m302_internalReg_t
Definition: m68302.h:500
scc
Definition: 8xx_immap.h:312