RTEMS: bsps/arm/atsam/include/libchip/include/sams70/component/component_isi.h Source File

| RTEMS 5.4-rc2

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component_isi.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70_ISI_COMPONENT_
31#define _SAMS70_ISI_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __IO uint32_t ISI_CFG1;
43 __IO uint32_t ISI_CFG2;
44 __IO uint32_t ISI_PSIZE;
45 __IO uint32_t ISI_PDECF;
46 __IO uint32_t ISI_Y2R_SET0;
47 __IO uint32_t ISI_Y2R_SET1;
48 __IO uint32_t ISI_R2Y_SET0;
49 __IO uint32_t ISI_R2Y_SET1;
50 __IO uint32_t ISI_R2Y_SET2;
51 __O uint32_t ISI_CR;
52 __I uint32_t ISI_SR;
53 __O uint32_t ISI_IER;
54 __O uint32_t ISI_IDR;
55 __I uint32_t ISI_IMR;
56 __O uint32_t ISI_DMA_CHER;
57 __O uint32_t ISI_DMA_CHDR;
58 __I uint32_t ISI_DMA_CHSR;
59 __IO uint32_t ISI_DMA_P_ADDR;
60 __IO uint32_t ISI_DMA_P_CTRL;
61 __IO uint32_t ISI_DMA_P_DSCR;
62 __IO uint32_t ISI_DMA_C_ADDR;
63 __IO uint32_t ISI_DMA_C_CTRL;
64 __IO uint32_t ISI_DMA_C_DSCR;
65 __I uint32_t Reserved1[34];
66 __IO uint32_t ISI_WPMR;
67 __I uint32_t ISI_WPSR;
68} Isi;
69#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
70/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */
71#define ISI_CFG1_HSYNC_POL (0x1u << 2)
72#define ISI_CFG1_VSYNC_POL (0x1u << 3)
73#define ISI_CFG1_PIXCLK_POL (0x1u << 4)
74#define ISI_CFG1_EMB_SYNC (0x1u << 6)
75#define ISI_CFG1_CRC_SYNC (0x1u << 7)
76#define ISI_CFG1_FRATE_Pos 8
77#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos)
78#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos)))
79#define ISI_CFG1_DISCR (0x1u << 11)
80#define ISI_CFG1_FULL (0x1u << 12)
81#define ISI_CFG1_THMASK_Pos 13
82#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos)
83#define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos)))
84#define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13)
85#define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13)
86#define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13)
87#define ISI_CFG1_SLD_Pos 16
88#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos)
89#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos)))
90#define ISI_CFG1_SFD_Pos 24
91#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos)
92#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos)))
93/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */
94#define ISI_CFG2_IM_VSIZE_Pos 0
95#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos)
96#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos)))
97#define ISI_CFG2_GS_MODE (0x1u << 11)
98#define ISI_CFG2_RGB_MODE (0x1u << 12)
99#define ISI_CFG2_GRAYSCALE (0x1u << 13)
100#define ISI_CFG2_RGB_SWAP (0x1u << 14)
101#define ISI_CFG2_COL_SPACE (0x1u << 15)
102#define ISI_CFG2_IM_HSIZE_Pos 16
103#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos)
104#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos)))
105#define ISI_CFG2_YCC_SWAP_Pos 28
106#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos)
107#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos)))
108#define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28)
109#define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28)
110#define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28)
111#define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28)
112#define ISI_CFG2_RGB_CFG_Pos 30
113#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos)
114#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos)))
115#define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30)
116#define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30)
117#define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30)
118#define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30)
119/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */
120#define ISI_PSIZE_PREV_VSIZE_Pos 0
121#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos)
122#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos)))
123#define ISI_PSIZE_PREV_HSIZE_Pos 16
124#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos)
125#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos)))
126/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */
127#define ISI_PDECF_DEC_FACTOR_Pos 0
128#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos)
129#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos)))
130/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */
131#define ISI_Y2R_SET0_C0_Pos 0
132#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos)
133#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos)))
134#define ISI_Y2R_SET0_C1_Pos 8
135#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos)
136#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos)))
137#define ISI_Y2R_SET0_C2_Pos 16
138#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos)
139#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos)))
140#define ISI_Y2R_SET0_C3_Pos 24
141#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos)
142#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos)))
143/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */
144#define ISI_Y2R_SET1_C4_Pos 0
145#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos)
146#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos)))
147#define ISI_Y2R_SET1_Yoff (0x1u << 12)
148#define ISI_Y2R_SET1_Croff (0x1u << 13)
149#define ISI_Y2R_SET1_Cboff (0x1u << 14)
150/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */
151#define ISI_R2Y_SET0_C0_Pos 0
152#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos)
153#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos)))
154#define ISI_R2Y_SET0_C1_Pos 8
155#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos)
156#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos)))
157#define ISI_R2Y_SET0_C2_Pos 16
158#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos)
159#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos)))
160#define ISI_R2Y_SET0_Roff (0x1u << 24)
161/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */
162#define ISI_R2Y_SET1_C3_Pos 0
163#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos)
164#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos)))
165#define ISI_R2Y_SET1_C4_Pos 8
166#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos)
167#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos)))
168#define ISI_R2Y_SET1_C5_Pos 16
169#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos)
170#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos)))
171#define ISI_R2Y_SET1_Goff (0x1u << 24)
172/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */
173#define ISI_R2Y_SET2_C6_Pos 0
174#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos)
175#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos)))
176#define ISI_R2Y_SET2_C7_Pos 8
177#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos)
178#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos)))
179#define ISI_R2Y_SET2_C8_Pos 16
180#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos)
181#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos)))
182#define ISI_R2Y_SET2_Boff (0x1u << 24)
183/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */
184#define ISI_CR_ISI_EN (0x1u << 0)
185#define ISI_CR_ISI_DIS (0x1u << 1)
186#define ISI_CR_ISI_SRST (0x1u << 2)
187#define ISI_CR_ISI_CDC (0x1u << 8)
188/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */
189#define ISI_SR_ENABLE (0x1u << 0)
190#define ISI_SR_DIS_DONE (0x1u << 1)
191#define ISI_SR_SRST (0x1u << 2)
192#define ISI_SR_CDC_PND (0x1u << 8)
193#define ISI_SR_VSYNC (0x1u << 10)
194#define ISI_SR_PXFR_DONE (0x1u << 16)
195#define ISI_SR_CXFR_DONE (0x1u << 17)
196#define ISI_SR_SIP (0x1u << 19)
197#define ISI_SR_P_OVR (0x1u << 24)
198#define ISI_SR_C_OVR (0x1u << 25)
199#define ISI_SR_CRC_ERR (0x1u << 26)
200#define ISI_SR_FR_OVR (0x1u << 27)
201/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */
202#define ISI_IER_DIS_DONE (0x1u << 1)
203#define ISI_IER_SRST (0x1u << 2)
204#define ISI_IER_VSYNC (0x1u << 10)
205#define ISI_IER_PXFR_DONE (0x1u << 16)
206#define ISI_IER_CXFR_DONE (0x1u << 17)
207#define ISI_IER_P_OVR (0x1u << 24)
208#define ISI_IER_C_OVR (0x1u << 25)
209#define ISI_IER_CRC_ERR (0x1u << 26)
210#define ISI_IER_FR_OVR (0x1u << 27)
211/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */
212#define ISI_IDR_DIS_DONE (0x1u << 1)
213#define ISI_IDR_SRST (0x1u << 2)
214#define ISI_IDR_VSYNC (0x1u << 10)
215#define ISI_IDR_PXFR_DONE (0x1u << 16)
216#define ISI_IDR_CXFR_DONE (0x1u << 17)
217#define ISI_IDR_P_OVR (0x1u << 24)
218#define ISI_IDR_C_OVR (0x1u << 25)
219#define ISI_IDR_CRC_ERR (0x1u << 26)
220#define ISI_IDR_FR_OVR (0x1u << 27)
221/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */
222#define ISI_IMR_DIS_DONE (0x1u << 1)
223#define ISI_IMR_SRST (0x1u << 2)
224#define ISI_IMR_VSYNC (0x1u << 10)
225#define ISI_IMR_PXFR_DONE (0x1u << 16)
226#define ISI_IMR_CXFR_DONE (0x1u << 17)
227#define ISI_IMR_P_OVR (0x1u << 24)
228#define ISI_IMR_C_OVR (0x1u << 25)
229#define ISI_IMR_CRC_ERR (0x1u << 26)
230#define ISI_IMR_FR_OVR (0x1u << 27)
231/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */
232#define ISI_DMA_CHER_P_CH_EN (0x1u << 0)
233#define ISI_DMA_CHER_C_CH_EN (0x1u << 1)
234/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */
235#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0)
236#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1)
237/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */
238#define ISI_DMA_CHSR_P_CH_S (0x1u << 0)
239#define ISI_DMA_CHSR_C_CH_S (0x1u << 1)
240/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */
241#define ISI_DMA_P_ADDR_P_ADDR_Pos 2
242#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos)
243#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos)))
244/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */
245#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0)
246#define ISI_DMA_P_CTRL_P_WB (0x1u << 1)
247#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2)
248#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3)
249/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */
250#define ISI_DMA_P_DSCR_P_DSCR_Pos 2
251#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos)
252#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos)))
253/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */
254#define ISI_DMA_C_ADDR_C_ADDR_Pos 2
255#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos)
256#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos)))
257/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */
258#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0)
259#define ISI_DMA_C_CTRL_C_WB (0x1u << 1)
260#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2)
261#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3)
262/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */
263#define ISI_DMA_C_DSCR_C_DSCR_Pos 2
264#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos)
265#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos)))
266/* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */
267#define ISI_WPMR_WPEN (0x1u << 0)
268#define ISI_WPMR_WPKEY_Pos 8
269#define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos)
270#define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos)))
271#define ISI_WPMR_WPKEY_PASSWD (0x495349u << 8)
272/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */
273#define ISI_WPSR_WPVS (0x1u << 0)
274#define ISI_WPSR_WPVSRC_Pos 8
275#define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos)
278
279
280#endif /* _SAMS70_ISI_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Isi
Isi hardware registers.
Definition: component_isi.h:41