RTEMS: L2CC Struct Reference

| RTEMS 5.4-rc2

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Data Fields
L2CC Struct Reference
Board Support Packages » ARM » Shared » Cache Support

L2CC Register Offsets. More...

## Data Fields
uint32_t | cache_id
| Cache ID.
uint32_t | cache_type
| Cache type.
uint8_t | reserved_8 [0x100 - 8]
uint32_t | ctrl
uint32_t | aux_ctrl
| Auxiliary control.
uint32_t | tag_ram_ctrl
| Latency for tag RAM.
uint32_t | data_ram_ctrl
| Latency for data RAM.
uint8_t | reserved_110 [0x200 - 0x110]
uint32_t | ev_ctrl
| Event counter control.
uint32_t | ev_cnt1_cfg
| Event counter 1 configuration.
uint32_t | ev_cnt0_cfg
| Event counter 0 configuration.
uint32_t | ev_cnt1
| Event counter 1 value.
uint32_t | ev_cnt0
| Event counter 0 value.
uint32_t | int_mask
| Interrupt enable mask.
uint32_t | int_mask_status
| Masked interrupt status (read-only)
uint32_t | int_raw_status
| Unmasked interrupt status.
uint32_t | int_clr
| Interrupt clear.
uint8_t | reserved_224 [0x730 - 0x224]
uint32_t | cache_sync
| Drain the STB.
uint8_t | reserved_734 [0x740 - 0x734]
uint32_t | dummy_cache_sync_reg
| ARM Errata 753970 for pl310-r3p0.
uint8_t | reserved_744 [0x770 - 0x744]
uint32_t | inv_pa
| Invalidate line by PA.
uint8_t | reserved_774 [0x77c - 0x774]
uint32_t | inv_way
| Invalidate by Way.
uint8_t | reserved_780 [0x7b0 - 0x780]
uint32_t | clean_pa
| Clean Line by PA.
uint8_t | reserved_7b4 [0x7b8 - 0x7b4]
uint32_t | clean_index
| Clean Line by Set/Way.
uint32_t | clean_way
| Clean by Way.
uint8_t | reserved_7c0 [0x7f0 - 0x7c0]
uint32_t | clean_inv_pa
| Clean and Invalidate Line by PA.
uint8_t | reserved_7f4 [0x7f8 - 0x7f4]
uint32_t | clean_inv_indx
| Clean and Invalidate Line by Set/Way.
uint32_t | clean_inv_way
| Clean and Invalidate by Way.
uint32_t | d_lockdown_0
| Data lock down 0.
uint32_t | i_lockdown_0
| Instruction lock down 0.
uint32_t | d_lockdown_1
| Data lock down 1.
uint32_t | i_lockdown_1
| Instruction lock down 1.
uint32_t | d_lockdown_2
| Data lock down 2.
uint32_t | i_lockdown_2
| Instruction lock down 2.
uint32_t | d_lockdown_3
| Data lock down 3.
uint32_t | i_lockdown_3
| Instruction lock down 3.
uint32_t | d_lockdown_4
| Data lock down 4.
uint32_t | i_lockdown_4
| Instruction lock down 4.
uint32_t | d_lockdown_5
| Data lock down 5.
uint32_t | i_lockdown_5
| Instruction lock down 5.
uint32_t | d_lockdown_6
| Data lock down 6.
uint32_t | i_lockdown_6
| Instruction lock down 6.
uint32_t | d_lockdown_7
| Data lock down 7.
uint32_t | i_lockdown_7
| Instruction lock down 7.
uint8_t | reserved_940 [0x950 - 0x940]
uint32_t | lock_line_en
| Lockdown by Line Enable.
uint32_t | unlock_way
| Cache lockdown by way.
uint8_t | reserved_958 [0xc00 - 0x958]
uint32_t | addr_filtering_start
| Address range redirect, part 1.
uint32_t | addr_filtering_end
| Address range redirect, part 2.
uint8_t | reserved_c08 [0xf40 - 0xc08]
uint32_t | debug_ctrl
| Debug control.
uint8_t | reserved_f44 [0xf60 - 0xf44]
uint32_t | prefetch_ctrl
| Purpose prefetch enables.
uint8_t | reserved_f64 [0xf80 - 0xf64]
uint32_t | power_ctrl
| Purpose power controls.

## Detailed Description

L2CC Register Offsets.

The documentation for this struct was generated from the following file:

- bsps/arm/shared/cache/cache-l2c-310.c