RTEMS: bsps/arm/include/bsp/arm-gic-regs.h Source File

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arm-gic-regs.h
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1
9/*
10 * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved.
11 *
12 * embedded brains GmbH
13 * Dornierstr. 4
14 * 82178 Puchheim
15 * Germany
16 * <info@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_SHARED_ARM_GIC_REGS_H
24#define LIBBSP_ARM_SHARED_ARM_GIC_REGS_H
25
26#include <bsp/utility.h>
27
28 typedef struct {
29 uint32_t iccicr;
30#define GIC_CPUIF_ICCICR_CBPR BSP_BIT32(4)
31#define GIC_CPUIF_ICCICR_FIQ_EN BSP_BIT32(3)
32#define GIC_CPUIF_ICCICR_ACK_CTL BSP_BIT32(2)
33#define GIC_CPUIF_ICCICR_ENABLE_GRP_1 BSP_BIT32(1)
34#define GIC_CPUIF_ICCICR_ENABLE BSP_BIT32(0)
35 uint32_t iccpmr;
36#define GIC_CPUIF_ICCPMR_PRIORITY(val) BSP_FLD32(val, 0, 7)
37#define GIC_CPUIF_ICCPMR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7)
38#define GIC_CPUIF_ICCPMR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
39 uint32_t iccbpr;
40#define GIC_CPUIF_ICCBPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2)
41#define GIC_CPUIF_ICCBPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2)
42#define GIC_CPUIF_ICCBPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
43 uint32_t icciar;
44#define GIC_CPUIF_ICCIAR_CPUID(val) BSP_FLD32(val, 10, 12)
45#define GIC_CPUIF_ICCIAR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
46#define GIC_CPUIF_ICCIAR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
47#define GIC_CPUIF_ICCIAR_ACKINTID(val) BSP_FLD32(val, 0, 9)
48#define GIC_CPUIF_ICCIAR_ACKINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
49#define GIC_CPUIF_ICCIAR_ACKINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
50 uint32_t icceoir;
51#define GIC_CPUIF_ICCEOIR_CPUID(val) BSP_FLD32(val, 10, 12)
52#define GIC_CPUIF_ICCEOIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
53#define GIC_CPUIF_ICCEOIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
54#define GIC_CPUIF_ICCEOIR_EOIINTID(val) BSP_FLD32(val, 0, 9)
55#define GIC_CPUIF_ICCEOIR_EOIINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
56#define GIC_CPUIF_ICCEOIR_EOIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
57 uint32_t iccrpr;
58#define GIC_CPUIF_ICCRPR_PRIORITY(val) BSP_FLD32(val, 0, 7)
59#define GIC_CPUIF_ICCRPR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7)
60#define GIC_CPUIF_ICCRPR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
61 uint32_t icchpir;
62#define GIC_CPUIF_ICCHPIR_CPUID(val) BSP_FLD32(val, 10, 12)
63#define GIC_CPUIF_ICCHPIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
64#define GIC_CPUIF_ICCHPIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
65#define GIC_CPUIF_ICCHPIR_PENDINTID(val) BSP_FLD32(val, 0, 9)
66#define GIC_CPUIF_ICCHPIR_PENDINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
67#define GIC_CPUIF_ICCHPIR_PENDINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
68 uint32_t iccabpr;
69#define GIC_CPUIF_ICCABPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2)
70#define GIC_CPUIF_ICCABPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2)
71#define GIC_CPUIF_ICCABPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
72 uint32_t reserved_20[55];
73 uint32_t icciidr;
74#define GIC_CPUIF_ICCIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31)
75#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31)
76#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
77#define GIC_CPUIF_ICCIIDR_ARCH_VERSION(val) BSP_FLD32(val, 16, 19)
78#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_GET(reg) BSP_FLD32GET(reg, 16, 19)
79#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
80#define GIC_CPUIF_ICCIIDR_REVISION(val) BSP_FLD32(val, 12, 15)
81#define GIC_CPUIF_ICCIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15)
82#define GIC_CPUIF_ICCIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
83#define GIC_CPUIF_ICCIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11)
84#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11)
85#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
86} gic_cpuif;
87
88 typedef struct {
89 /* GICD_CTLR */
90 uint32_t icddcr;
91/* GICv3 only */
92#define GIC_DIST_ICDDCR_RWP BSP_BIT32(31)
93#define GIC_DIST_ICDDCR_E1NWF BSP_BIT32(7)
94#define GIC_DIST_ICDDCR_DS BSP_BIT32(6)
95#define GIC_DIST_ICDDCR_ARE_NS BSP_BIT32(5)
96#define GIC_DIST_ICDDCR_ARE_S BSP_BIT32(4)
97#define GIC_DIST_ICDDCR_ENABLE_GRP1S BSP_BIT32(2)
98#define GIC_DIST_ICDDCR_ENABLE_GRP1NS BSP_BIT32(1)
99#define GIC_DIST_ICDDCR_ENABLE_GRP0 BSP_BIT32(0)
100/* GICv1/GICv2 */
101#define GIC_DIST_ICDDCR_ENABLE_GRP_1 BSP_BIT32(1)
102#define GIC_DIST_ICDDCR_ENABLE BSP_BIT32(0)
103 uint32_t icdictr;
104#define GIC_DIST_ICDICTR_LSPI(val) BSP_FLD32(val, 11, 15)
105#define GIC_DIST_ICDICTR_LSPI_GET(reg) BSP_FLD32GET(reg, 11, 15)
106#define GIC_DIST_ICDICTR_LSPI_SET(reg, val) BSP_FLD32SET(reg, val, 11, 15)
107#define GIC_DIST_ICDICTR_SECURITY_EXTN BSP_BIT32(10)
108#define GIC_DIST_ICDICTR_CPU_NUMBER(val) BSP_FLD32(val, 5, 7)
109#define GIC_DIST_ICDICTR_CPU_NUMBER_GET(reg) BSP_FLD32GET(reg, 5, 7)
110#define GIC_DIST_ICDICTR_CPU_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7)
111#define GIC_DIST_ICDICTR_IT_LINES_NUMBER(val) BSP_FLD32(val, 0, 4)
112#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(reg) BSP_FLD32GET(reg, 0, 4)
113#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
114 uint32_t icdiidr;
115#define GIC_DIST_ICDIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31)
116#define GIC_DIST_ICDIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31)
117#define GIC_DIST_ICDIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
118#define GIC_DIST_ICDIIDR_VARIANT(val) BSP_FLD32(val, 16, 19)
119#define GIC_DIST_ICDIIDR_VARIANT_GET(reg) BSP_FLD32GET(reg, 16, 19)
120#define GIC_DIST_ICDIIDR_VARIANT_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
121#define GIC_DIST_ICDIIDR_REVISION(val) BSP_FLD32(val, 12, 15)
122#define GIC_DIST_ICDIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15)
123#define GIC_DIST_ICDIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
124#define GIC_DIST_ICDIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11)
125#define GIC_DIST_ICDIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11)
126#define GIC_DIST_ICDIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
127 uint32_t reserved_0c[29];
128 uint32_t icdigr[32];
129 uint32_t icdiser[32];
130 uint32_t icdicer[32];
131 uint32_t icdispr[32];
132 uint32_t icdicpr[32];
133 uint32_t icdabr[32];
134 uint32_t reserved_380[32];
135 uint8_t icdipr[256];
136 uint32_t reserved_500[192];
137 uint8_t icdiptr[256];
138 uint32_t reserved_900[192];
139 uint32_t icdicfr[64];
140 /* GICD_IGRPMODR GICv3 only, reserved in GICv1/GICv2 */
141 uint32_t icdigmr[32];
142 uint32_t reserved_d80[96];
143 uint32_t icdsgir;
144#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(val) BSP_FLD32(val, 24, 25)
145#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_GET(reg) BSP_FLD32GET(reg, 24, 25)
146#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25)
147#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST(val) BSP_FLD32(val, 16, 23)
148#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD32GET(reg, 16, 23)
149#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
150#define GIC_DIST_ICDSGIR_NSATT BSP_BIT32(15)
151#define GIC_DIST_ICDSGIR_SGIINTID(val) BSP_FLD32(val, 0, 3)
152#define GIC_DIST_ICDSGIR_SGIINTID_GET(reg) BSP_FLD32GET(reg, 0, 3)
153#define GIC_DIST_ICDSGIR_SGIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
154} gic_dist;
155
156/* GICv3 only */
157 typedef struct {
158 /* GICR_CTLR */
159 uint32_t icrrcr;
160#define GIC_REDIST_ICRRCR_UWP BSP_BIT32(31)
161#define GIC_REDIST_ICRRCR_DPG1S BSP_BIT32(26)
162#define GIC_REDIST_ICRRCR_DPG1NS BSP_BIT32(25)
163#define GIC_REDIST_ICRRCR_DPG0 BSP_BIT32(24)
164#define GIC_REDIST_ICRRCR_RWP BSP_BIT32(4)
165#define GIC_REDIST_ICRRCR_ENABLE_LPI BSP_BIT32(0)
166 uint32_t icriidr;
167 uint64_t icrtyper;
168#define GIC_REDIST_ICRTYPER_AFFINITY_VALUE(val) BSP_FLD64(val, 32, 63)
169#define GIC_REDIST_ICRTYPER_AFFINITY_VALUE_GET(reg) BSP_FLD64GET(reg, 32, 63)
170#define GIC_REDIST_ICRTYPER_AFFINITY_VALUE_SET(reg, val) BSP_FLD64SET(reg, val, 32, 63)
171#define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY(val) BSP_FLD64(val, 24, 25)
172#define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_GET(reg) BSP_FLD64GET(reg, 24, 25)
173#define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_SET(reg, val) BSP_FLD64SET(reg, val, 24, 25)
174#define GIC_REDIST_ICRTYPER_CPU_NUMBER(val) BSP_FLD64(val, 8, 23)
175#define GIC_REDIST_ICRTYPER_CPU_NUMBER_GET(reg) BSP_FLD64GET(reg, 8, 23)
176#define GIC_REDIST_ICRTYPER_CPU_NUMBER_SET(reg, val) BSP_FLD64SET(reg, val, 8, 23)
177#define GIC_REDIST_ICRTYPER_DPGS BSP_BIT64(5)
178#define GIC_REDIST_ICRTYPER_LAST BSP_BIT64(4)
179#define GIC_REDIST_ICRTYPER_DIRECT_LPI BSP_BIT64(3)
180#define GIC_REDIST_ICRTYPER_VLPIS BSP_BIT64(1)
181#define GIC_REDIST_ICRTYPER_PLPIS BSP_BIT64(0)
182 uint32_t unused_10;
183 uint32_t icrwaker;
184#define GIC_REDIST_ICRWAKER_CHILDREN_ASLEEP BSP_BIT32(2)
185#define GIC_REDIST_ICRWAKER_PROCESSOR_SLEEP BSP_BIT32(1)
186} gic_redist;
187
188/* GICv3 only */
189 typedef struct {
190 uint32_t reserved_0_80[32];
191 /* GICR_IGROUPR0 */
192 uint32_t icspigrpr[32];
193 /* GICR_ISENABLER0 */
194 uint32_t icspiser[32];
195 /* GICR_ICENABLER0 */
196 uint32_t icspicer[32];
197 /* GICR_ISPENDR0 */
198 uint32_t icspispendr[32];
199 /* GICR_ICPENDR0 */
200 uint32_t icspicpendr[32];
201 /* GICR_ISACTIVER0 */
202 uint32_t icspisar[32];
203 /* GICR_ICACTIVER0 */
204 uint32_t icspicar[32];
205 /* GICR_IPRIORITYR */
206 uint8_t icspiprior[32];
207 uint32_t reserved_420_bfc[504];
208 /* GICR_ICFGR0 */
209 uint32_t icspicfgr0;
210 /* GICR_ICFGR1 */
211 uint32_t icspicfgr1;
212 uint32_t reserved_c08_cfc[62];
213 /* GICR_IGRPMODR0 */
214 uint32_t icspigrpmodr[64];
215} gic_sgi_ppi;
216
217#endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */
utility.h
Utility macros.
gic_cpuif
Definition: arm-gic-regs.h:28
gic_dist
Definition: arm-gic-regs.h:88
gic_redist
Definition: arm-gic-regs.h:157
gic_sgi_ppi
Definition: arm-gic-regs.h:189