RTEMS: Core Debug Registers (CoreDebug)

| RTEMS 5.4-rc2

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Modules | Data Structures
Core Debug Registers (CoreDebug)
Board Support Packages » ARM » Shared » CMSIS » Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI)

Type definitions for the Core Debug Registers. More...

## Modules
| Core register bit field macros
| Macros for use with bit field definitions (xxx_Pos, xxx_Msk).

## Data Structures
struct | CoreDebug_Type
| Structure type to access the Core Debug Register (CoreDebug). More...
#define | CoreDebug_DHCSR_DBGKEY_Pos 16U
#define | CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
#define | CoreDebug_DHCSR_S_RESET_ST_Pos 25U
#define | CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
#define | CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
#define | CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
#define | CoreDebug_DHCSR_S_LOCKUP_Pos 19U
#define | CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
#define | CoreDebug_DHCSR_S_SLEEP_Pos 18U
#define | CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
#define | CoreDebug_DHCSR_S_HALT_Pos 17U
#define | CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
#define | CoreDebug_DHCSR_S_REGRDY_Pos 16U
#define | CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
#define | CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
#define | CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
#define | CoreDebug_DHCSR_C_MASKINTS_Pos 3U
#define | CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
#define | CoreDebug_DHCSR_C_STEP_Pos 2U
#define | CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
#define | CoreDebug_DHCSR_C_HALT_Pos 1U
#define | CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
#define | CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
#define | CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
#define | CoreDebug_DCRSR_REGWnR_Pos 16U
#define | CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
#define | CoreDebug_DCRSR_REGSEL_Pos 0U
#define | CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
#define | CoreDebug_DEMCR_TRCENA_Pos 24U
#define | CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
#define | CoreDebug_DEMCR_MON_REQ_Pos 19U
#define | CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
#define | CoreDebug_DEMCR_MON_STEP_Pos 18U
#define | CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
#define | CoreDebug_DEMCR_MON_PEND_Pos 17U
#define | CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
#define | CoreDebug_DEMCR_MON_EN_Pos 16U
#define | CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
#define | CoreDebug_DEMCR_VC_HARDERR_Pos 10U
#define | CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
#define | CoreDebug_DEMCR_VC_INTERR_Pos 9U
#define | CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
#define | CoreDebug_DEMCR_VC_BUSERR_Pos 8U
#define | CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
#define | CoreDebug_DEMCR_VC_STATERR_Pos 7U
#define | CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
#define | CoreDebug_DEMCR_VC_CHKERR_Pos 6U
#define | CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
#define | CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
#define | CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
#define | CoreDebug_DEMCR_VC_MMERR_Pos 4U
#define | CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
#define | CoreDebug_DEMCR_VC_CORERESET_Pos 0U
#define | CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

## Detailed Description

Type definitions for the Core Debug Registers.

## Macro Definition Documentation

## ◆ CoreDebug_DCRSR_REGSEL_Msk

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

## ◆ CoreDebug_DCRSR_REGSEL_Pos

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

## ◆ CoreDebug_DCRSR_REGWnR_Msk

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

## ◆ CoreDebug_DCRSR_REGWnR_Pos

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

## ◆ CoreDebug_DEMCR_MON_EN_Msk

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

## ◆ CoreDebug_DEMCR_MON_EN_Pos

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

## ◆ CoreDebug_DEMCR_MON_PEND_Msk

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

## ◆ CoreDebug_DEMCR_MON_PEND_Pos

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

## ◆ CoreDebug_DEMCR_MON_REQ_Msk

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

## ◆ CoreDebug_DEMCR_MON_REQ_Pos

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

## ◆ CoreDebug_DEMCR_MON_STEP_Msk

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

## ◆ CoreDebug_DEMCR_MON_STEP_Pos

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

## ◆ CoreDebug_DEMCR_TRCENA_Msk

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

## ◆ CoreDebug_DEMCR_TRCENA_Pos

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

## ◆ CoreDebug_DEMCR_VC_BUSERR_Msk

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

## ◆ CoreDebug_DEMCR_VC_BUSERR_Pos

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

## ◆ CoreDebug_DEMCR_VC_CHKERR_Msk

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

## ◆ CoreDebug_DEMCR_VC_CHKERR_Pos

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

## ◆ CoreDebug_DEMCR_VC_CORERESET_Msk

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

## ◆ CoreDebug_DEMCR_VC_CORERESET_Pos

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

## ◆ CoreDebug_DEMCR_VC_HARDERR_Msk

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

## ◆ CoreDebug_DEMCR_VC_HARDERR_Pos

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

## ◆ CoreDebug_DEMCR_VC_INTERR_Msk

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

## ◆ CoreDebug_DEMCR_VC_INTERR_Pos

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

## ◆ CoreDebug_DEMCR_VC_MMERR_Msk

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

## ◆ CoreDebug_DEMCR_VC_MMERR_Pos

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

## ◆ CoreDebug_DEMCR_VC_NOCPERR_Msk

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

## ◆ CoreDebug_DEMCR_VC_NOCPERR_Pos

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

## ◆ CoreDebug_DEMCR_VC_STATERR_Msk

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

## ◆ CoreDebug_DEMCR_VC_STATERR_Pos

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

## ◆ CoreDebug_DHCSR_C_DEBUGEN_Msk

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

## ◆ CoreDebug_DHCSR_C_DEBUGEN_Pos

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

## ◆ CoreDebug_DHCSR_C_HALT_Msk

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

## ◆ CoreDebug_DHCSR_C_HALT_Pos

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

## ◆ CoreDebug_DHCSR_C_MASKINTS_Msk

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

## ◆ CoreDebug_DHCSR_C_MASKINTS_Pos

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

## ◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

## ◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

## ◆ CoreDebug_DHCSR_C_STEP_Msk

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

## ◆ CoreDebug_DHCSR_C_STEP_Pos

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

## ◆ CoreDebug_DHCSR_DBGKEY_Msk

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

## ◆ CoreDebug_DHCSR_DBGKEY_Pos

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

## ◆ CoreDebug_DHCSR_S_HALT_Msk

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

## ◆ CoreDebug_DHCSR_S_HALT_Pos

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

## ◆ CoreDebug_DHCSR_S_LOCKUP_Msk

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

## ◆ CoreDebug_DHCSR_S_LOCKUP_Pos

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

## ◆ CoreDebug_DHCSR_S_REGRDY_Msk

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

## ◆ CoreDebug_DHCSR_S_REGRDY_Pos

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

## ◆ CoreDebug_DHCSR_S_RESET_ST_Msk

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

## ◆ CoreDebug_DHCSR_S_RESET_ST_Pos

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

## ◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

## ◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

CoreDebug DHCSR: S_RETIRE_ST Position

## ◆ CoreDebug_DHCSR_S_SLEEP_Msk

#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

## ◆ CoreDebug_DHCSR_S_SLEEP_Pos

#define CoreDebug_DHCSR_S_SLEEP_Pos 18U

CoreDebug DHCSR: S_SLEEP Position