RTEMS: bsps/arm/atsam/include/libchip/include/samv71/component/component_usbhs.h Source File

| RTEMS 5.4-rc2

Loading...
Searching...
No Matches
component_usbhs.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMV71_USBHS_COMPONENT_
31#define _SAMV71_USBHS_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __IO uint32_t USBHS_DEVDMANXTDSC;
43 __IO uint32_t USBHS_DEVDMAADDRESS;
44 __IO uint32_t USBHS_DEVDMACONTROL;
45 __IO uint32_t USBHS_DEVDMASTATUS;
46} UsbhsDevdma;
48typedef struct {
49 __IO uint32_t USBHS_HSTDMANXTDSC;
50 __IO uint32_t USBHS_HSTDMAADDRESS;
51 __IO uint32_t USBHS_HSTDMACONTROL;
52 __IO uint32_t USBHS_HSTDMASTATUS;
53} UsbhsHstdma;
55#define USBHSDEVDMA_NUMBER 7
56#define USBHSHSTDMA_NUMBER 7
57typedef struct {
58 __IO uint32_t USBHS_DEVCTRL;
59 __I uint32_t USBHS_DEVISR;
60 __O uint32_t USBHS_DEVICR;
61 __O uint32_t USBHS_DEVIFR;
62 __I uint32_t USBHS_DEVIMR;
63 __O uint32_t USBHS_DEVIDR;
64 __O uint32_t USBHS_DEVIER;
65 __IO uint32_t USBHS_DEVEPT;
66 __I uint32_t USBHS_DEVFNUM;
67 __I uint32_t Reserved1[55];
68 __IO uint32_t USBHS_DEVEPTCFG[10];
69 __I uint32_t Reserved2[2];
70 __I uint32_t USBHS_DEVEPTISR[10];
71 __I uint32_t Reserved3[2];
72 __O uint32_t USBHS_DEVEPTICR[10];
73 __I uint32_t Reserved4[2];
74 __O uint32_t USBHS_DEVEPTIFR[10];
75 __I uint32_t Reserved5[2];
76 __I uint32_t USBHS_DEVEPTIMR[10];
77 __I uint32_t Reserved6[2];
78 __O uint32_t USBHS_DEVEPTIER[10];
79 __I uint32_t Reserved7[2];
80 __O uint32_t USBHS_DEVEPTIDR[10];
81 __I uint32_t Reserved8[50];
82 UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER];
83 __I uint32_t Reserved9[32];
84 __IO uint32_t USBHS_HSTCTRL;
85 __I uint32_t USBHS_HSTISR;
86 __O uint32_t USBHS_HSTICR;
87 __O uint32_t USBHS_HSTIFR;
88 __I uint32_t USBHS_HSTIMR;
89 __O uint32_t USBHS_HSTIDR;
90 __O uint32_t USBHS_HSTIER;
91 __IO uint32_t USBHS_HSTPIP;
92 __IO uint32_t USBHS_HSTFNUM;
93 __IO uint32_t USBHS_HSTADDR1;
94 __IO uint32_t USBHS_HSTADDR2;
95 __IO uint32_t USBHS_HSTADDR3;
96 __I uint32_t Reserved10[52];
97 __IO uint32_t USBHS_HSTPIPCFG[10];
98 __I uint32_t Reserved11[2];
99 __I uint32_t USBHS_HSTPIPISR[10];
100 __I uint32_t Reserved12[2];
101 __O uint32_t USBHS_HSTPIPICR[10];
102 __I uint32_t Reserved13[2];
103 __O uint32_t USBHS_HSTPIPIFR[10];
104 __I uint32_t Reserved14[2];
105 __I uint32_t USBHS_HSTPIPIMR[10];
106 __I uint32_t Reserved15[2];
107 __O uint32_t USBHS_HSTPIPIER[10];
108 __I uint32_t Reserved16[2];
109 __O uint32_t USBHS_HSTPIPIDR[10];
110 __I uint32_t Reserved17[2];
111 __IO uint32_t USBHS_HSTPIPINRQ[10];
112 __I uint32_t Reserved18[2];
113 __IO uint32_t USBHS_HSTPIPERR[10];
114 __I uint32_t Reserved19[26];
115 UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER];
116 __I uint32_t Reserved20[32];
117 __IO uint32_t USBHS_CTRL;
118 __I uint32_t USBHS_SR;
119 __O uint32_t USBHS_SCR;
120 __O uint32_t USBHS_SFR;
121 __IO uint32_t USBHS_TSTA1;
122 __IO uint32_t USBHS_TSTA2;
123 __I uint32_t USBHS_VERSION;
124 __I uint32_t Reserved21[4];
125 __I uint32_t USBHS_FSM;
126} Usbhs;
127#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
128/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */
129#define USBHS_DEVCTRL_UADD_Pos 0
130#define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos)
131#define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos)))
132#define USBHS_DEVCTRL_ADDEN (0x1u << 7)
133#define USBHS_DEVCTRL_DETACH (0x1u << 8)
134#define USBHS_DEVCTRL_RMWKUP (0x1u << 9)
135#define USBHS_DEVCTRL_SPDCONF_Pos 10
136#define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos)
137#define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos)))
138#define USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10)
139#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10)
140#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10)
141#define USBHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10)
142#define USBHS_DEVCTRL_LS (0x1u << 12)
143#define USBHS_DEVCTRL_TSTJ (0x1u << 13)
144#define USBHS_DEVCTRL_TSTK (0x1u << 14)
145#define USBHS_DEVCTRL_TSTPCKT (0x1u << 15)
146#define USBHS_DEVCTRL_OPMODE2 (0x1u << 16)
147/* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */
148#define USBHS_DEVISR_SUSP (0x1u << 0)
149#define USBHS_DEVISR_MSOF (0x1u << 1)
150#define USBHS_DEVISR_SOF (0x1u << 2)
151#define USBHS_DEVISR_EORST (0x1u << 3)
152#define USBHS_DEVISR_WAKEUP (0x1u << 4)
153#define USBHS_DEVISR_EORSM (0x1u << 5)
154#define USBHS_DEVISR_UPRSM (0x1u << 6)
155#define USBHS_DEVISR_PEP_0 (0x1u << 12)
156#define USBHS_DEVISR_PEP_1 (0x1u << 13)
157#define USBHS_DEVISR_PEP_2 (0x1u << 14)
158#define USBHS_DEVISR_PEP_3 (0x1u << 15)
159#define USBHS_DEVISR_PEP_4 (0x1u << 16)
160#define USBHS_DEVISR_PEP_5 (0x1u << 17)
161#define USBHS_DEVISR_PEP_6 (0x1u << 18)
162#define USBHS_DEVISR_PEP_7 (0x1u << 19)
163#define USBHS_DEVISR_PEP_8 (0x1u << 20)
164#define USBHS_DEVISR_PEP_9 (0x1u << 21)
165#define USBHS_DEVISR_PEP_10 (0x1u << 22)
166#define USBHS_DEVISR_PEP_11 (0x1u << 23)
167#define USBHS_DEVISR_DMA_1 (0x1u << 25)
168#define USBHS_DEVISR_DMA_2 (0x1u << 26)
169#define USBHS_DEVISR_DMA_3 (0x1u << 27)
170#define USBHS_DEVISR_DMA_4 (0x1u << 28)
171#define USBHS_DEVISR_DMA_5 (0x1u << 29)
172#define USBHS_DEVISR_DMA_6 (0x1u << 30)
173#define USBHS_DEVISR_DMA_7 (0x1u << 31)
174/* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */
175#define USBHS_DEVICR_SUSPC (0x1u << 0)
176#define USBHS_DEVICR_MSOFC (0x1u << 1)
177#define USBHS_DEVICR_SOFC (0x1u << 2)
178#define USBHS_DEVICR_EORSTC (0x1u << 3)
179#define USBHS_DEVICR_WAKEUPC (0x1u << 4)
180#define USBHS_DEVICR_EORSMC (0x1u << 5)
181#define USBHS_DEVICR_UPRSMC (0x1u << 6)
182/* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */
183#define USBHS_DEVIFR_SUSPS (0x1u << 0)
184#define USBHS_DEVIFR_MSOFS (0x1u << 1)
185#define USBHS_DEVIFR_SOFS (0x1u << 2)
186#define USBHS_DEVIFR_EORSTS (0x1u << 3)
187#define USBHS_DEVIFR_WAKEUPS (0x1u << 4)
188#define USBHS_DEVIFR_EORSMS (0x1u << 5)
189#define USBHS_DEVIFR_UPRSMS (0x1u << 6)
190#define USBHS_DEVIFR_DMA_1 (0x1u << 25)
191#define USBHS_DEVIFR_DMA_2 (0x1u << 26)
192#define USBHS_DEVIFR_DMA_3 (0x1u << 27)
193#define USBHS_DEVIFR_DMA_4 (0x1u << 28)
194#define USBHS_DEVIFR_DMA_5 (0x1u << 29)
195#define USBHS_DEVIFR_DMA_6 (0x1u << 30)
196#define USBHS_DEVIFR_DMA_7 (0x1u << 31)
197/* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */
198#define USBHS_DEVIMR_SUSPE (0x1u << 0)
199#define USBHS_DEVIMR_MSOFE (0x1u << 1)
200#define USBHS_DEVIMR_SOFE (0x1u << 2)
201#define USBHS_DEVIMR_EORSTE (0x1u << 3)
202#define USBHS_DEVIMR_WAKEUPE (0x1u << 4)
203#define USBHS_DEVIMR_EORSME (0x1u << 5)
204#define USBHS_DEVIMR_UPRSME (0x1u << 6)
205#define USBHS_DEVIMR_PEP_0 (0x1u << 12)
206#define USBHS_DEVIMR_PEP_1 (0x1u << 13)
207#define USBHS_DEVIMR_PEP_2 (0x1u << 14)
208#define USBHS_DEVIMR_PEP_3 (0x1u << 15)
209#define USBHS_DEVIMR_PEP_4 (0x1u << 16)
210#define USBHS_DEVIMR_PEP_5 (0x1u << 17)
211#define USBHS_DEVIMR_PEP_6 (0x1u << 18)
212#define USBHS_DEVIMR_PEP_7 (0x1u << 19)
213#define USBHS_DEVIMR_PEP_8 (0x1u << 20)
214#define USBHS_DEVIMR_PEP_9 (0x1u << 21)
215#define USBHS_DEVIMR_PEP_10 (0x1u << 22)
216#define USBHS_DEVIMR_PEP_11 (0x1u << 23)
217#define USBHS_DEVIMR_DMA_1 (0x1u << 25)
218#define USBHS_DEVIMR_DMA_2 (0x1u << 26)
219#define USBHS_DEVIMR_DMA_3 (0x1u << 27)
220#define USBHS_DEVIMR_DMA_4 (0x1u << 28)
221#define USBHS_DEVIMR_DMA_5 (0x1u << 29)
222#define USBHS_DEVIMR_DMA_6 (0x1u << 30)
223#define USBHS_DEVIMR_DMA_7 (0x1u << 31)
224/* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */
225#define USBHS_DEVIDR_SUSPEC (0x1u << 0)
226#define USBHS_DEVIDR_MSOFEC (0x1u << 1)
227#define USBHS_DEVIDR_SOFEC (0x1u << 2)
228#define USBHS_DEVIDR_EORSTEC (0x1u << 3)
229#define USBHS_DEVIDR_WAKEUPEC (0x1u << 4)
230#define USBHS_DEVIDR_EORSMEC (0x1u << 5)
231#define USBHS_DEVIDR_UPRSMEC (0x1u << 6)
232#define USBHS_DEVIDR_PEP_0 (0x1u << 12)
233#define USBHS_DEVIDR_PEP_1 (0x1u << 13)
234#define USBHS_DEVIDR_PEP_2 (0x1u << 14)
235#define USBHS_DEVIDR_PEP_3 (0x1u << 15)
236#define USBHS_DEVIDR_PEP_4 (0x1u << 16)
237#define USBHS_DEVIDR_PEP_5 (0x1u << 17)
238#define USBHS_DEVIDR_PEP_6 (0x1u << 18)
239#define USBHS_DEVIDR_PEP_7 (0x1u << 19)
240#define USBHS_DEVIDR_PEP_8 (0x1u << 20)
241#define USBHS_DEVIDR_PEP_9 (0x1u << 21)
242#define USBHS_DEVIDR_PEP_10 (0x1u << 22)
243#define USBHS_DEVIDR_PEP_11 (0x1u << 23)
244#define USBHS_DEVIDR_DMA_1 (0x1u << 25)
245#define USBHS_DEVIDR_DMA_2 (0x1u << 26)
246#define USBHS_DEVIDR_DMA_3 (0x1u << 27)
247#define USBHS_DEVIDR_DMA_4 (0x1u << 28)
248#define USBHS_DEVIDR_DMA_5 (0x1u << 29)
249#define USBHS_DEVIDR_DMA_6 (0x1u << 30)
250#define USBHS_DEVIDR_DMA_7 (0x1u << 31)
251/* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */
252#define USBHS_DEVIER_SUSPES (0x1u << 0)
253#define USBHS_DEVIER_MSOFES (0x1u << 1)
254#define USBHS_DEVIER_SOFES (0x1u << 2)
255#define USBHS_DEVIER_EORSTES (0x1u << 3)
256#define USBHS_DEVIER_WAKEUPES (0x1u << 4)
257#define USBHS_DEVIER_EORSMES (0x1u << 5)
258#define USBHS_DEVIER_UPRSMES (0x1u << 6)
259#define USBHS_DEVIER_PEP_0 (0x1u << 12)
260#define USBHS_DEVIER_PEP_1 (0x1u << 13)
261#define USBHS_DEVIER_PEP_2 (0x1u << 14)
262#define USBHS_DEVIER_PEP_3 (0x1u << 15)
263#define USBHS_DEVIER_PEP_4 (0x1u << 16)
264#define USBHS_DEVIER_PEP_5 (0x1u << 17)
265#define USBHS_DEVIER_PEP_6 (0x1u << 18)
266#define USBHS_DEVIER_PEP_7 (0x1u << 19)
267#define USBHS_DEVIER_PEP_8 (0x1u << 20)
268#define USBHS_DEVIER_PEP_9 (0x1u << 21)
269#define USBHS_DEVIER_PEP_10 (0x1u << 22)
270#define USBHS_DEVIER_PEP_11 (0x1u << 23)
271#define USBHS_DEVIER_DMA_1 (0x1u << 25)
272#define USBHS_DEVIER_DMA_2 (0x1u << 26)
273#define USBHS_DEVIER_DMA_3 (0x1u << 27)
274#define USBHS_DEVIER_DMA_4 (0x1u << 28)
275#define USBHS_DEVIER_DMA_5 (0x1u << 29)
276#define USBHS_DEVIER_DMA_6 (0x1u << 30)
277#define USBHS_DEVIER_DMA_7 (0x1u << 31)
278/* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */
279#define USBHS_DEVEPT_EPEN0 (0x1u << 0)
280#define USBHS_DEVEPT_EPEN1 (0x1u << 1)
281#define USBHS_DEVEPT_EPEN2 (0x1u << 2)
282#define USBHS_DEVEPT_EPEN3 (0x1u << 3)
283#define USBHS_DEVEPT_EPEN4 (0x1u << 4)
284#define USBHS_DEVEPT_EPEN5 (0x1u << 5)
285#define USBHS_DEVEPT_EPEN6 (0x1u << 6)
286#define USBHS_DEVEPT_EPEN7 (0x1u << 7)
287#define USBHS_DEVEPT_EPEN8 (0x1u << 8)
288#define USBHS_DEVEPT_EPRST0 (0x1u << 16)
289#define USBHS_DEVEPT_EPRST1 (0x1u << 17)
290#define USBHS_DEVEPT_EPRST2 (0x1u << 18)
291#define USBHS_DEVEPT_EPRST3 (0x1u << 19)
292#define USBHS_DEVEPT_EPRST4 (0x1u << 20)
293#define USBHS_DEVEPT_EPRST5 (0x1u << 21)
294#define USBHS_DEVEPT_EPRST6 (0x1u << 22)
295#define USBHS_DEVEPT_EPRST7 (0x1u << 23)
296#define USBHS_DEVEPT_EPRST8 (0x1u << 24)
297/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */
298#define USBHS_DEVFNUM_MFNUM_Pos 0
299#define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos)
300#define USBHS_DEVFNUM_FNUM_Pos 3
301#define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos)
302#define USBHS_DEVFNUM_FNCERR (0x1u << 15)
303/* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */
304#define USBHS_DEVEPTCFG_ALLOC (0x1u << 1)
305#define USBHS_DEVEPTCFG_EPBK_Pos 2
306#define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos)
307#define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos)))
308#define USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2)
309#define USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2)
310#define USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2)
311#define USBHS_DEVEPTCFG_EPSIZE_Pos 4
312#define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos)
313#define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos)))
314#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4)
315#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4)
316#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4)
317#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4)
318#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4)
319#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4)
320#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4)
321#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4)
322#define USBHS_DEVEPTCFG_EPDIR (0x1u << 8)
323#define USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8)
324#define USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8)
325#define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9)
326#define USBHS_DEVEPTCFG_EPTYPE_Pos 11
327#define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos)
328#define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos)))
329#define USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11)
330#define USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11)
331#define USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11)
332#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11)
333#define USBHS_DEVEPTCFG_NBTRANS_Pos 13
334#define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos)
335#define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos)))
336#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13)
337#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13)
338#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13)
339#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13)
340/* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */
341#define USBHS_DEVEPTISR_TXINI (0x1u << 0)
342#define USBHS_DEVEPTISR_RXOUTI (0x1u << 1)
343#define USBHS_DEVEPTISR_RXSTPI (0x1u << 2)
344#define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3)
345#define USBHS_DEVEPTISR_NAKINI (0x1u << 4)
346#define USBHS_DEVEPTISR_OVERFI (0x1u << 5)
347#define USBHS_DEVEPTISR_STALLEDI (0x1u << 6)
348#define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7)
349#define USBHS_DEVEPTISR_DTSEQ_Pos 8
350#define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos)
351#define USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8)
352#define USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8)
353#define USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8)
354#define USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8)
355#define USBHS_DEVEPTISR_NBUSYBK_Pos 12
356#define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos)
357#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12)
358#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12)
359#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12)
360#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12)
361#define USBHS_DEVEPTISR_CURRBK_Pos 14
362#define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos)
363#define USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14)
364#define USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14)
365#define USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14)
366#define USBHS_DEVEPTISR_RWALL (0x1u << 16)
367#define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17)
368#define USBHS_DEVEPTISR_CFGOK (0x1u << 18)
369#define USBHS_DEVEPTISR_BYCT_Pos 20
370#define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos)
371#define USBHS_DEVEPTISR_UNDERFI (0x1u << 2)
372#define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3)
373#define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4)
374#define USBHS_DEVEPTISR_CRCERRI (0x1u << 6)
375#define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10)
376/* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */
377#define USBHS_DEVEPTICR_TXINIC (0x1u << 0)
378#define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1)
379#define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2)
380#define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3)
381#define USBHS_DEVEPTICR_NAKINIC (0x1u << 4)
382#define USBHS_DEVEPTICR_OVERFIC (0x1u << 5)
383#define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6)
384#define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7)
385#define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2)
386#define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3)
387#define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4)
388#define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6)
389/* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */
390#define USBHS_DEVEPTIFR_TXINIS (0x1u << 0)
391#define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1)
392#define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2)
393#define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3)
394#define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4)
395#define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5)
396#define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6)
397#define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7)
398#define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12)
399#define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2)
400#define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3)
401#define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4)
402#define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6)
403/* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */
404#define USBHS_DEVEPTIMR_TXINE (0x1u << 0)
405#define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1)
406#define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2)
407#define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3)
408#define USBHS_DEVEPTIMR_NAKINE (0x1u << 4)
409#define USBHS_DEVEPTIMR_OVERFE (0x1u << 5)
410#define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6)
411#define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7)
412#define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12)
413#define USBHS_DEVEPTIMR_KILLBK (0x1u << 13)
414#define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14)
415#define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16)
416#define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17)
417#define USBHS_DEVEPTIMR_RSTDT (0x1u << 18)
418#define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19)
419#define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2)
420#define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3)
421#define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4)
422#define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6)
423#define USBHS_DEVEPTIMR_MDATAE (0x1u << 8)
424#define USBHS_DEVEPTIMR_DATAXE (0x1u << 9)
425#define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10)
426/* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */
427#define USBHS_DEVEPTIER_TXINES (0x1u << 0)
428#define USBHS_DEVEPTIER_RXOUTES (0x1u << 1)
429#define USBHS_DEVEPTIER_RXSTPES (0x1u << 2)
430#define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3)
431#define USBHS_DEVEPTIER_NAKINES (0x1u << 4)
432#define USBHS_DEVEPTIER_OVERFES (0x1u << 5)
433#define USBHS_DEVEPTIER_STALLEDES (0x1u << 6)
434#define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7)
435#define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12)
436#define USBHS_DEVEPTIER_KILLBKS (0x1u << 13)
437#define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14)
438#define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16)
439#define USBHS_DEVEPTIER_NYETDISS (0x1u << 17)
440#define USBHS_DEVEPTIER_RSTDTS (0x1u << 18)
441#define USBHS_DEVEPTIER_STALLRQS (0x1u << 19)
442#define USBHS_DEVEPTIER_UNDERFES (0x1u << 2)
443#define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3)
444#define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4)
445#define USBHS_DEVEPTIER_CRCERRES (0x1u << 6)
446#define USBHS_DEVEPTIER_MDATAES (0x1u << 8)
447#define USBHS_DEVEPTIER_DATAXES (0x1u << 9)
448#define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10)
449/* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */
450#define USBHS_DEVEPTIDR_TXINEC (0x1u << 0)
451#define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1)
452#define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2)
453#define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3)
454#define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4)
455#define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5)
456#define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6)
457#define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7)
458#define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12)
459#define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14)
460#define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16)
461#define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17)
462#define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19)
463#define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2)
464#define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3)
465#define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4)
466#define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6)
467#define USBHS_DEVEPTIDR_MDATEC (0x1u << 8)
468#define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9)
469#define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10)
470/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */
471#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0
472#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)
473#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)))
474/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */
475#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0
476#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)
477#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)))
478/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */
479#define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0)
480#define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1)
481#define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2)
482#define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3)
483#define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4)
484#define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5)
485#define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6)
486#define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7)
487#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16
488#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)
489#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)))
490/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */
491#define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0)
492#define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1)
493#define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4)
494#define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5)
495#define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6)
496#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16
497#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)
498#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)))
499/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */
500#define USBHS_HSTCTRL_SOFE (0x1u << 8)
501#define USBHS_HSTCTRL_RESET (0x1u << 9)
502#define USBHS_HSTCTRL_RESUME (0x1u << 10)
503#define USBHS_HSTCTRL_SPDCONF_Pos 12
504#define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos)
505#define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos)))
506#define USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12)
507#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12)
508#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12)
509#define USBHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12)
510/* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */
511#define USBHS_HSTISR_DCONNI (0x1u << 0)
512#define USBHS_HSTISR_DDISCI (0x1u << 1)
513#define USBHS_HSTISR_RSTI (0x1u << 2)
514#define USBHS_HSTISR_RSMEDI (0x1u << 3)
515#define USBHS_HSTISR_RXRSMI (0x1u << 4)
516#define USBHS_HSTISR_HSOFI (0x1u << 5)
517#define USBHS_HSTISR_HWUPI (0x1u << 6)
518#define USBHS_HSTISR_PEP_0 (0x1u << 8)
519#define USBHS_HSTISR_PEP_1 (0x1u << 9)
520#define USBHS_HSTISR_PEP_2 (0x1u << 10)
521#define USBHS_HSTISR_PEP_3 (0x1u << 11)
522#define USBHS_HSTISR_PEP_4 (0x1u << 12)
523#define USBHS_HSTISR_PEP_5 (0x1u << 13)
524#define USBHS_HSTISR_PEP_6 (0x1u << 14)
525#define USBHS_HSTISR_PEP_7 (0x1u << 15)
526#define USBHS_HSTISR_PEP_8 (0x1u << 16)
527#define USBHS_HSTISR_PEP_9 (0x1u << 17)
528#define USBHS_HSTISR_PEP_10 (0x1u << 18)
529#define USBHS_HSTISR_PEP_11 (0x1u << 19)
530#define USBHS_HSTISR_DMA_1 (0x1u << 25)
531#define USBHS_HSTISR_DMA_2 (0x1u << 26)
532#define USBHS_HSTISR_DMA_3 (0x1u << 27)
533#define USBHS_HSTISR_DMA_4 (0x1u << 28)
534#define USBHS_HSTISR_DMA_5 (0x1u << 29)
535#define USBHS_HSTISR_DMA_6 (0x1u << 30)
536#define USBHS_HSTISR_DMA_7 (0x1u << 31)
537/* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */
538#define USBHS_HSTICR_DCONNIC (0x1u << 0)
539#define USBHS_HSTICR_DDISCIC (0x1u << 1)
540#define USBHS_HSTICR_RSTIC (0x1u << 2)
541#define USBHS_HSTICR_RSMEDIC (0x1u << 3)
542#define USBHS_HSTICR_RXRSMIC (0x1u << 4)
543#define USBHS_HSTICR_HSOFIC (0x1u << 5)
544#define USBHS_HSTICR_HWUPIC (0x1u << 6)
545/* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */
546#define USBHS_HSTIFR_DCONNIS (0x1u << 0)
547#define USBHS_HSTIFR_DDISCIS (0x1u << 1)
548#define USBHS_HSTIFR_RSTIS (0x1u << 2)
549#define USBHS_HSTIFR_RSMEDIS (0x1u << 3)
550#define USBHS_HSTIFR_RXRSMIS (0x1u << 4)
551#define USBHS_HSTIFR_HSOFIS (0x1u << 5)
552#define USBHS_HSTIFR_HWUPIS (0x1u << 6)
553#define USBHS_HSTIFR_DMA_1 (0x1u << 25)
554#define USBHS_HSTIFR_DMA_2 (0x1u << 26)
555#define USBHS_HSTIFR_DMA_3 (0x1u << 27)
556#define USBHS_HSTIFR_DMA_4 (0x1u << 28)
557#define USBHS_HSTIFR_DMA_5 (0x1u << 29)
558#define USBHS_HSTIFR_DMA_6 (0x1u << 30)
559#define USBHS_HSTIFR_DMA_7 (0x1u << 31)
560/* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */
561#define USBHS_HSTIMR_DCONNIE (0x1u << 0)
562#define USBHS_HSTIMR_DDISCIE (0x1u << 1)
563#define USBHS_HSTIMR_RSTIE (0x1u << 2)
564#define USBHS_HSTIMR_RSMEDIE (0x1u << 3)
565#define USBHS_HSTIMR_RXRSMIE (0x1u << 4)
566#define USBHS_HSTIMR_HSOFIE (0x1u << 5)
567#define USBHS_HSTIMR_HWUPIE (0x1u << 6)
568#define USBHS_HSTIMR_PEP_0 (0x1u << 8)
569#define USBHS_HSTIMR_PEP_1 (0x1u << 9)
570#define USBHS_HSTIMR_PEP_2 (0x1u << 10)
571#define USBHS_HSTIMR_PEP_3 (0x1u << 11)
572#define USBHS_HSTIMR_PEP_4 (0x1u << 12)
573#define USBHS_HSTIMR_PEP_5 (0x1u << 13)
574#define USBHS_HSTIMR_PEP_6 (0x1u << 14)
575#define USBHS_HSTIMR_PEP_7 (0x1u << 15)
576#define USBHS_HSTIMR_PEP_8 (0x1u << 16)
577#define USBHS_HSTIMR_PEP_9 (0x1u << 17)
578#define USBHS_HSTIMR_PEP_10 (0x1u << 18)
579#define USBHS_HSTIMR_PEP_11 (0x1u << 19)
580#define USBHS_HSTIMR_DMA_1 (0x1u << 25)
581#define USBHS_HSTIMR_DMA_2 (0x1u << 26)
582#define USBHS_HSTIMR_DMA_3 (0x1u << 27)
583#define USBHS_HSTIMR_DMA_4 (0x1u << 28)
584#define USBHS_HSTIMR_DMA_5 (0x1u << 29)
585#define USBHS_HSTIMR_DMA_6 (0x1u << 30)
586#define USBHS_HSTIMR_DMA_7 (0x1u << 31)
587/* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */
588#define USBHS_HSTIDR_DCONNIEC (0x1u << 0)
589#define USBHS_HSTIDR_DDISCIEC (0x1u << 1)
590#define USBHS_HSTIDR_RSTIEC (0x1u << 2)
591#define USBHS_HSTIDR_RSMEDIEC (0x1u << 3)
592#define USBHS_HSTIDR_RXRSMIEC (0x1u << 4)
593#define USBHS_HSTIDR_HSOFIEC (0x1u << 5)
594#define USBHS_HSTIDR_HWUPIEC (0x1u << 6)
595#define USBHS_HSTIDR_PEP_0 (0x1u << 8)
596#define USBHS_HSTIDR_PEP_1 (0x1u << 9)
597#define USBHS_HSTIDR_PEP_2 (0x1u << 10)
598#define USBHS_HSTIDR_PEP_3 (0x1u << 11)
599#define USBHS_HSTIDR_PEP_4 (0x1u << 12)
600#define USBHS_HSTIDR_PEP_5 (0x1u << 13)
601#define USBHS_HSTIDR_PEP_6 (0x1u << 14)
602#define USBHS_HSTIDR_PEP_7 (0x1u << 15)
603#define USBHS_HSTIDR_PEP_8 (0x1u << 16)
604#define USBHS_HSTIDR_PEP_9 (0x1u << 17)
605#define USBHS_HSTIDR_PEP_10 (0x1u << 18)
606#define USBHS_HSTIDR_PEP_11 (0x1u << 19)
607#define USBHS_HSTIDR_DMA_1 (0x1u << 25)
608#define USBHS_HSTIDR_DMA_2 (0x1u << 26)
609#define USBHS_HSTIDR_DMA_3 (0x1u << 27)
610#define USBHS_HSTIDR_DMA_4 (0x1u << 28)
611#define USBHS_HSTIDR_DMA_5 (0x1u << 29)
612#define USBHS_HSTIDR_DMA_6 (0x1u << 30)
613#define USBHS_HSTIDR_DMA_7 (0x1u << 31)
614/* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */
615#define USBHS_HSTIER_DCONNIES (0x1u << 0)
616#define USBHS_HSTIER_DDISCIES (0x1u << 1)
617#define USBHS_HSTIER_RSTIES (0x1u << 2)
618#define USBHS_HSTIER_RSMEDIES (0x1u << 3)
619#define USBHS_HSTIER_RXRSMIES (0x1u << 4)
620#define USBHS_HSTIER_HSOFIES (0x1u << 5)
621#define USBHS_HSTIER_HWUPIES (0x1u << 6)
622#define USBHS_HSTIER_PEP_0 (0x1u << 8)
623#define USBHS_HSTIER_PEP_1 (0x1u << 9)
624#define USBHS_HSTIER_PEP_2 (0x1u << 10)
625#define USBHS_HSTIER_PEP_3 (0x1u << 11)
626#define USBHS_HSTIER_PEP_4 (0x1u << 12)
627#define USBHS_HSTIER_PEP_5 (0x1u << 13)
628#define USBHS_HSTIER_PEP_6 (0x1u << 14)
629#define USBHS_HSTIER_PEP_7 (0x1u << 15)
630#define USBHS_HSTIER_PEP_8 (0x1u << 16)
631#define USBHS_HSTIER_PEP_9 (0x1u << 17)
632#define USBHS_HSTIER_PEP_10 (0x1u << 18)
633#define USBHS_HSTIER_PEP_11 (0x1u << 19)
634#define USBHS_HSTIER_DMA_1 (0x1u << 25)
635#define USBHS_HSTIER_DMA_2 (0x1u << 26)
636#define USBHS_HSTIER_DMA_3 (0x1u << 27)
637#define USBHS_HSTIER_DMA_4 (0x1u << 28)
638#define USBHS_HSTIER_DMA_5 (0x1u << 29)
639#define USBHS_HSTIER_DMA_6 (0x1u << 30)
640#define USBHS_HSTIER_DMA_7 (0x1u << 31)
641/* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */
642#define USBHS_HSTPIP_PEN0 (0x1u << 0)
643#define USBHS_HSTPIP_PEN1 (0x1u << 1)
644#define USBHS_HSTPIP_PEN2 (0x1u << 2)
645#define USBHS_HSTPIP_PEN3 (0x1u << 3)
646#define USBHS_HSTPIP_PEN4 (0x1u << 4)
647#define USBHS_HSTPIP_PEN5 (0x1u << 5)
648#define USBHS_HSTPIP_PEN6 (0x1u << 6)
649#define USBHS_HSTPIP_PEN7 (0x1u << 7)
650#define USBHS_HSTPIP_PEN8 (0x1u << 8)
651#define USBHS_HSTPIP_PRST0 (0x1u << 16)
652#define USBHS_HSTPIP_PRST1 (0x1u << 17)
653#define USBHS_HSTPIP_PRST2 (0x1u << 18)
654#define USBHS_HSTPIP_PRST3 (0x1u << 19)
655#define USBHS_HSTPIP_PRST4 (0x1u << 20)
656#define USBHS_HSTPIP_PRST5 (0x1u << 21)
657#define USBHS_HSTPIP_PRST6 (0x1u << 22)
658#define USBHS_HSTPIP_PRST7 (0x1u << 23)
659#define USBHS_HSTPIP_PRST8 (0x1u << 24)
660/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */
661#define USBHS_HSTFNUM_MFNUM_Pos 0
662#define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos)
663#define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos)))
664#define USBHS_HSTFNUM_FNUM_Pos 3
665#define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos)
666#define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos)))
667#define USBHS_HSTFNUM_FLENHIGH_Pos 16
668#define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos)
669#define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos)))
670/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */
671#define USBHS_HSTADDR1_HSTADDRP0_Pos 0
672#define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos)
673#define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos)))
674#define USBHS_HSTADDR1_HSTADDRP1_Pos 8
675#define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos)
676#define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos)))
677#define USBHS_HSTADDR1_HSTADDRP2_Pos 16
678#define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos)
679#define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos)))
680#define USBHS_HSTADDR1_HSTADDRP3_Pos 24
681#define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos)
682#define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos)))
683/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */
684#define USBHS_HSTADDR2_HSTADDRP4_Pos 0
685#define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos)
686#define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos)))
687#define USBHS_HSTADDR2_HSTADDRP5_Pos 8
688#define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos)
689#define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos)))
690#define USBHS_HSTADDR2_HSTADDRP6_Pos 16
691#define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos)
692#define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos)))
693#define USBHS_HSTADDR2_HSTADDRP7_Pos 24
694#define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos)
695#define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos)))
696/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */
697#define USBHS_HSTADDR3_HSTADDRP8_Pos 0
698#define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos)
699#define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos)))
700#define USBHS_HSTADDR3_HSTADDRP9_Pos 8
701#define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos)
702#define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos)))
703/* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */
704#define USBHS_HSTPIPCFG_ALLOC (0x1u << 1)
705#define USBHS_HSTPIPCFG_PBK_Pos 2
706#define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos)
707#define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos)))
708#define USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2)
709#define USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2)
710#define USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2)
711#define USBHS_HSTPIPCFG_PSIZE_Pos 4
712#define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos)
713#define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos)))
714#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4)
715#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4)
716#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4)
717#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4)
718#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4)
719#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4)
720#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4)
721#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4)
722#define USBHS_HSTPIPCFG_PTOKEN_Pos 8
723#define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos)
724#define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos)))
725#define USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8)
726#define USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8)
727#define USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8)
728#define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10)
729#define USBHS_HSTPIPCFG_PTYPE_Pos 12
730#define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos)
731#define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos)))
732#define USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12)
733#define USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12)
734#define USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12)
735#define USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12)
736#define USBHS_HSTPIPCFG_PEPNUM_Pos 16
737#define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos)
738#define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos)))
739#define USBHS_HSTPIPCFG_INTFRQ_Pos 24
740#define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos)
741#define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos)))
742#define USBHS_HSTPIPCFG_PINGEN (0x1u << 20)
743#define USBHS_HSTPIPCFG_BINTERVAL_Pos 24
744#define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos)
745#define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos)))
746/* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */
747#define USBHS_HSTPIPISR_RXINI (0x1u << 0)
748#define USBHS_HSTPIPISR_TXOUTI (0x1u << 1)
749#define USBHS_HSTPIPISR_TXSTPI (0x1u << 2)
750#define USBHS_HSTPIPISR_PERRI (0x1u << 3)
751#define USBHS_HSTPIPISR_NAKEDI (0x1u << 4)
752#define USBHS_HSTPIPISR_OVERFI (0x1u << 5)
753#define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6)
754#define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7)
755#define USBHS_HSTPIPISR_DTSEQ_Pos 8
756#define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos)
757#define USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8)
758#define USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8)
759#define USBHS_HSTPIPISR_NBUSYBK_Pos 12
760#define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos)
761#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12)
762#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12)
763#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12)
764#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12)
765#define USBHS_HSTPIPISR_CURRBK_Pos 14
766#define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos)
767#define USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14)
768#define USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14)
769#define USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14)
770#define USBHS_HSTPIPISR_RWALL (0x1u << 16)
771#define USBHS_HSTPIPISR_CFGOK (0x1u << 18)
772#define USBHS_HSTPIPISR_PBYCT_Pos 20
773#define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos)
774#define USBHS_HSTPIPISR_UNDERFI (0x1u << 2)
775#define USBHS_HSTPIPISR_CRCERRI (0x1u << 6)
776/* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */
777#define USBHS_HSTPIPICR_RXINIC (0x1u << 0)
778#define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1)
779#define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2)
780#define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4)
781#define USBHS_HSTPIPICR_OVERFIC (0x1u << 5)
782#define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6)
783#define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7)
784#define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2)
785#define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6)
786/* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */
787#define USBHS_HSTPIPIFR_RXINIS (0x1u << 0)
788#define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1)
789#define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2)
790#define USBHS_HSTPIPIFR_PERRIS (0x1u << 3)
791#define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4)
792#define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5)
793#define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6)
794#define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7)
795#define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12)
796#define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2)
797#define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6)
798/* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */
799#define USBHS_HSTPIPIMR_RXINE (0x1u << 0)
800#define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1)
801#define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2)
802#define USBHS_HSTPIPIMR_PERRE (0x1u << 3)
803#define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4)
804#define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5)
805#define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6)
806#define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7)
807#define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12)
808#define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14)
809#define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16)
810#define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17)
811#define USBHS_HSTPIPIMR_RSTDT (0x1u << 18)
812#define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2)
813#define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6)
814/* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */
815#define USBHS_HSTPIPIER_RXINES (0x1u << 0)
816#define USBHS_HSTPIPIER_TXOUTES (0x1u << 1)
817#define USBHS_HSTPIPIER_TXSTPES (0x1u << 2)
818#define USBHS_HSTPIPIER_PERRES (0x1u << 3)
819#define USBHS_HSTPIPIER_NAKEDES (0x1u << 4)
820#define USBHS_HSTPIPIER_OVERFIES (0x1u << 5)
821#define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6)
822#define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7)
823#define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12)
824#define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16)
825#define USBHS_HSTPIPIER_PFREEZES (0x1u << 17)
826#define USBHS_HSTPIPIER_RSTDTS (0x1u << 18)
827#define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2)
828#define USBHS_HSTPIPIER_CRCERRES (0x1u << 6)
829/* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */
830#define USBHS_HSTPIPIDR_RXINEC (0x1u << 0)
831#define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1)
832#define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2)
833#define USBHS_HSTPIPIDR_PERREC (0x1u << 3)
834#define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4)
835#define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5)
836#define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6)
837#define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7)
838#define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12)
839#define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14)
840#define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16)
841#define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17)
842#define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2)
843#define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6)
844/* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */
845#define USBHS_HSTPIPINRQ_INRQ_Pos 0
846#define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos)
847#define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos)))
848#define USBHS_HSTPIPINRQ_INMODE (0x1u << 8)
849/* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */
850#define USBHS_HSTPIPERR_DATATGL (0x1u << 0)
851#define USBHS_HSTPIPERR_DATAPID (0x1u << 1)
852#define USBHS_HSTPIPERR_PID (0x1u << 2)
853#define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3)
854#define USBHS_HSTPIPERR_CRC16 (0x1u << 4)
855#define USBHS_HSTPIPERR_COUNTER_Pos 5
856#define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos)
857#define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos)))
858/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */
859#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0
860#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)
861#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)))
862/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */
863#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0
864#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)
865#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)))
866/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */
867#define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0)
868#define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1)
869#define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2)
870#define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3)
871#define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4)
872#define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5)
873#define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6)
874#define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7)
875#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16
876#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)
877#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)))
878/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */
879#define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0)
880#define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1)
881#define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4)
882#define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5)
883#define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6)
884#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16
885#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)
886#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)))
887/* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */
888#define USBHS_CTRL_RDERRE (0x1u << 4)
889#define USBHS_CTRL_VBUSHWC (0x1u << 8)
890#define USBHS_CTRL_FRZCLK (0x1u << 14)
891#define USBHS_CTRL_USBE (0x1u << 15)
892#define USBHS_CTRL_UIMOD (0x1u << 25)
893#define USBHS_CTRL_UIMOD_HOST (0x0u << 25)
894#define USBHS_CTRL_UIMOD_DEVICE (0x1u << 25)
895/* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */
896#define USBHS_SR_RDERRI (0x1u << 4)
897#define USBHS_SR_VBUSRQ (0x1u << 9)
898#define USBHS_SR_SPEED_Pos 12
899#define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos)
900#define USBHS_SR_SPEED_FULL_SPEED (0x0u << 12)
901#define USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12)
902#define USBHS_SR_SPEED_LOW_SPEED (0x2u << 12)
903#define USBHS_SR_CLKUSABLE (0x1u << 14)
904/* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */
905#define USBHS_SCR_RDERRIC (0x1u << 4)
906#define USBHS_SCR_VBUSRQC (0x1u << 9)
907/* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */
908#define USBHS_SFR_RDERRIS (0x1u << 4)
909#define USBHS_SFR_VBUSRQS (0x1u << 9)
910/* -------- USBHS_TSTA1 : (USBHS Offset: 0x0810) General Test A1 Register -------- */
911#define USBHS_TSTA1_CounterA_Pos 0
912#define USBHS_TSTA1_CounterA_Msk (0x7fffu << USBHS_TSTA1_CounterA_Pos)
913#define USBHS_TSTA1_CounterA(value) ((USBHS_TSTA1_CounterA_Msk & ((value) << USBHS_TSTA1_CounterA_Pos)))
914#define USBHS_TSTA1_LoadCntA (0x1u << 15)
915#define USBHS_TSTA1_CounterB_Pos 16
916#define USBHS_TSTA1_CounterB_Msk (0x3fu << USBHS_TSTA1_CounterB_Pos)
917#define USBHS_TSTA1_CounterB(value) ((USBHS_TSTA1_CounterB_Msk & ((value) << USBHS_TSTA1_CounterB_Pos)))
918#define USBHS_TSTA1_LoadCntB (0x1u << 23)
919#define USBHS_TSTA1_SOFCntMa1_Pos 24
920#define USBHS_TSTA1_SOFCntMa1_Msk (0x7fu << USBHS_TSTA1_SOFCntMa1_Pos)
921#define USBHS_TSTA1_SOFCntMa1(value) ((USBHS_TSTA1_SOFCntMa1_Msk & ((value) << USBHS_TSTA1_SOFCntMa1_Pos)))
922#define USBHS_TSTA1_LoadSOFCnt (0x1u << 31)
923/* -------- USBHS_TSTA2 : (USBHS Offset: 0x0814) General Test A2 Register -------- */
924#define USBHS_TSTA2_FullDetachEn (0x1u << 0)
925#define USBHS_TSTA2_HSSerialMode (0x1u << 1)
926#define USBHS_TSTA2_LoopBackMode (0x1u << 2)
927#define USBHS_TSTA2_DisableGatedClock (0x1u << 3)
928#define USBHS_TSTA2_ForceSuspendMTo1 (0x1u << 4)
929#define USBHS_TSTA2_ByPassDpll (0x1u << 5)
930#define USBHS_TSTA2_HostHSDisconnectDisable (0x1u << 6)
931#define USBHS_TSTA2_ForceHSRst_50ms (0x1u << 7)
932#define USBHS_TSTA2_RemovePUWhenTX (0x1u << 9)
933/* -------- USBHS_VERSION : (USBHS Offset: 0x0818) General Version Register -------- */
934#define USBHS_VERSION_VERSION_Pos 0
935#define USBHS_VERSION_VERSION_Msk (0xfffu << USBHS_VERSION_VERSION_Pos)
936#define USBHS_VERSION_MFN_Pos 16
937#define USBHS_VERSION_MFN_Msk (0xfu << USBHS_VERSION_MFN_Pos)
938/* -------- USBHS_FSM : (USBHS Offset: 0x082C) General Finite State Machine Register -------- */
939#define USBHS_FSM_DRDSTATE_Pos 0
940#define USBHS_FSM_DRDSTATE_Msk (0xfu << USBHS_FSM_DRDSTATE_Pos)
941#define USBHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0)
942#define USBHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0)
943#define USBHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0)
944#define USBHS_FSM_DRDSTATE_A_HOST (0x3u << 0)
945#define USBHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0)
946#define USBHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0)
947#define USBHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0)
948#define USBHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0)
949#define USBHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0)
950#define USBHS_FSM_DRDSTATE_B_IDLE (0x9u << 0)
951#define USBHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0)
952#define USBHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0)
953#define USBHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0)
954#define USBHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0)
955#define USBHS_FSM_DRDSTATE_B_HOST (0xEu << 0)
956#define USBHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0)
959
960
961#endif /* _SAMV71_USBHS_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
UsbhsDevdma
UsbhsDevdma hardware registers.
Definition: component_usbhs.h:41
UsbhsHstdma
UsbhsHstdma hardware registers.
Definition: component_usbhs.h:48
Usbhs
Definition: component_usbhs.h:57
Usbhs::USBHS_TSTA2
__IO uint32_t USBHS_TSTA2
(Usbhs Offset: 0x0814) General Test A2 Register
Definition: component_usbhs.h:122
Usbhs::USBHS_TSTA1
__IO uint32_t USBHS_TSTA1
(Usbhs Offset: 0x0810) General Test A1 Register
Definition: component_usbhs.h:121
Usbhs::USBHS_FSM
__I uint32_t USBHS_FSM
(Usbhs Offset: 0x082C) General Finite State Machine Register
Definition: component_usbhs.h:125
Usbhs::USBHS_VERSION
__I uint32_t USBHS_VERSION
(Usbhs Offset: 0x0818) General Version Register
Definition: component_usbhs.h:123