RTEMS: bsps/arm/altera-cyclone-v/include/bsp/socal/alt_i2c.h Source File

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alt_i2c.h
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1
7/*******************************************************************************
8* *
9* Copyright 2013 Altera Corporation. All Rights Reserved. *
10* *
11* Redistribution and use in source and binary forms, with or without *
12* modification, are permitted provided that the following conditions are met: *
13* *
14* 1. Redistributions of source code must retain the above copyright notice, *
15* this list of conditions and the following disclaimer. *
16* *
17* 2. Redistributions in binary form must reproduce the above copyright notice, *
18* this list of conditions and the following disclaimer in the documentation *
19* and/or other materials provided with the distribution. *
20* *
21* 3. The name of the author may not be used to endorse or promote products *
22* derived from this software without specific prior written permission. *
23* *
24* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
25* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
26* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
27* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
28* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
29* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
30* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
31* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
32* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
33* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
34* *
35*******************************************************************************/
36
37/* Altera - ALT_I2C */
38
39#ifndef __ALTERA_ALT_I2C_H__
40#define __ALTERA_ALT_I2C_H__
41
42#ifdef __cplusplus
43extern "C"
44{
45#endif /* __cplusplus */
46
47/*
48 * Component : I2C Module - ALT_I2C
49 * I2C Module
50 *
51 * Registers in the I2C module
52 *
53 */
54/*
55 * Register : Control Register - ic_con
56 *
57 * This register can be written only when the I2C is disabled, which corresponds to
58 * the Bit [0] of the Enable Register being set to 0. Writes at other times have no
59 * effect.
60 *
61 * Register Layout
62 *
63 * Bits | Access | Reset | Description
64 * :-------|:-------|:------|:---------------------
65 * [0] | RW | 0x1 | Master Enable
66 * [2:1] | RW | 0x2 | Master Speed Control
67 * [3] | RW | 0x1 | Slave Address Size
68 * [4] | RW | 0x1 | Master Address Size
69 * [5] | RW | 0x1 | Restart Enable
70 * [6] | RW | 0x1 | Slave Disable
71 * [31:7] | ??? | 0x0 | *UNDEFINED*
72 *
73 */
74/*
75 * Field : Master Enable - master_mode
76 *
77 * This bit controls whether the i2c master is enabled.
78 *
79 * NOTE: Software should ensure that if this bit is written with '1', then bit 6
80 * should also be written with a '1'.
81 *
82 * Field Enumeration Values:
83 *
84 * Enum | Value | Description
85 * :--------------------------|:------|:----------------
86 * ALT_I2C_CON_MST_MOD_E_DIS | 0x0 | master disabled
87 * ALT_I2C_CON_MST_MOD_E_EN | 0x1 | master enabled
88 *
89 * Field Access Macros:
90 *
91 */
92/*
93 * Enumerated value for register field ALT_I2C_CON_MST_MOD
94 *
95 * master disabled
96 */
97#define ALT_I2C_CON_MST_MOD_E_DIS 0x0
98/*
99 * Enumerated value for register field ALT_I2C_CON_MST_MOD
100 *
101 * master enabled
102 */
103#define ALT_I2C_CON_MST_MOD_E_EN 0x1
104
105/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_MST_MOD register field. */
106#define ALT_I2C_CON_MST_MOD_LSB 0
107/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_MST_MOD register field. */
108#define ALT_I2C_CON_MST_MOD_MSB 0
109/* The width in bits of the ALT_I2C_CON_MST_MOD register field. */
110#define ALT_I2C_CON_MST_MOD_WIDTH 1
111/* The mask used to set the ALT_I2C_CON_MST_MOD register field value. */
112#define ALT_I2C_CON_MST_MOD_SET_MSK 0x00000001
113/* The mask used to clear the ALT_I2C_CON_MST_MOD register field value. */
114#define ALT_I2C_CON_MST_MOD_CLR_MSK 0xfffffffe
115/* The reset value of the ALT_I2C_CON_MST_MOD register field. */
116#define ALT_I2C_CON_MST_MOD_RESET 0x1
117/* Extracts the ALT_I2C_CON_MST_MOD field value from a register. */
118#define ALT_I2C_CON_MST_MOD_GET(value) (((value) & 0x00000001) >> 0)
119/* Produces a ALT_I2C_CON_MST_MOD register field value suitable for setting the register. */
120#define ALT_I2C_CON_MST_MOD_SET(value) (((value) << 0) & 0x00000001)
121
122/*
123 * Field : Master Speed Control - speed
124 *
125 * These bits control at which speed the I2C operates, its setting is relevant only
126 * if one is operating the I2C in master mode. Hardware protects against illegal
127 * values being programmed by software. This field should be programmed only with
128 * standard or fast speed.
129 *
130 * Field Enumeration Values:
131 *
132 * Enum | Value | Description
133 * :-----------------------------|:------|:---------------------------
134 * ALT_I2C_CON_SPEED_E_STANDARD | 0x1 | standard mode (100 kbit/s)
135 * ALT_I2C_CON_SPEED_E_FAST | 0x2 | fast mode (400 kbit/s)
136 *
137 * Field Access Macros:
138 *
139 */
140/*
141 * Enumerated value for register field ALT_I2C_CON_SPEED
142 *
143 * standard mode (100 kbit/s)
144 */
145#define ALT_I2C_CON_SPEED_E_STANDARD 0x1
146/*
147 * Enumerated value for register field ALT_I2C_CON_SPEED
148 *
149 * fast mode (400 kbit/s)
150 */
151#define ALT_I2C_CON_SPEED_E_FAST 0x2
152
153/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_SPEED register field. */
154#define ALT_I2C_CON_SPEED_LSB 1
155/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_SPEED register field. */
156#define ALT_I2C_CON_SPEED_MSB 2
157/* The width in bits of the ALT_I2C_CON_SPEED register field. */
158#define ALT_I2C_CON_SPEED_WIDTH 2
159/* The mask used to set the ALT_I2C_CON_SPEED register field value. */
160#define ALT_I2C_CON_SPEED_SET_MSK 0x00000006
161/* The mask used to clear the ALT_I2C_CON_SPEED register field value. */
162#define ALT_I2C_CON_SPEED_CLR_MSK 0xfffffff9
163/* The reset value of the ALT_I2C_CON_SPEED register field. */
164#define ALT_I2C_CON_SPEED_RESET 0x2
165/* Extracts the ALT_I2C_CON_SPEED field value from a register. */
166#define ALT_I2C_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1)
167/* Produces a ALT_I2C_CON_SPEED register field value suitable for setting the register. */
168#define ALT_I2C_CON_SPEED_SET(value) (((value) << 1) & 0x00000006)
169
170/*
171 * Field : Slave Address Size - ic_10bitaddr_slave
172 *
173 * When acting as a slave, this bit controls whether the I2C responds to 7- or
174 * 10-bit addresses. In 7-bit addressing, only the lower 7 bits of the Slave
175 * Address Register are compared. The I2C responds will only respond to 10-bit
176 * addressing transfers that match the full 10 bits of the Slave Address register.
177 *
178 * Field Enumeration Values:
179 *
180 * Enum | Value | Description
181 * :--------------------------------------------|:------|:------------------
182 * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT | 0x0 | 7-bit addressing
183 * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT | 0x1 | 10-bit addressing
184 *
185 * Field Access Macros:
186 *
187 */
188/*
189 * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV
190 *
191 * 7-bit addressing
192 */
193#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0
194/*
195 * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV
196 *
197 * 10-bit addressing
198 */
199#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1
200
201/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */
202#define ALT_I2C_CON_IC_10BITADDR_SLV_LSB 3
203/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */
204#define ALT_I2C_CON_IC_10BITADDR_SLV_MSB 3
205/* The width in bits of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */
206#define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH 1
207/* The mask used to set the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */
208#define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK 0x00000008
209/* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */
210#define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK 0xfffffff7
211/* The reset value of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */
212#define ALT_I2C_CON_IC_10BITADDR_SLV_RESET 0x1
213/* Extracts the ALT_I2C_CON_IC_10BITADDR_SLV field value from a register. */
214#define ALT_I2C_CON_IC_10BITADDR_SLV_GET(value) (((value) & 0x00000008) >> 3)
215/* Produces a ALT_I2C_CON_IC_10BITADDR_SLV register field value suitable for setting the register. */
216#define ALT_I2C_CON_IC_10BITADDR_SLV_SET(value) (((value) << 3) & 0x00000008)
217
218/*
219 * Field : Master Address Size - ic_10bitaddr_master
220 *
221 * This bit controls whether the I2C starts its transfers in 7-or 10-bit addressing
222 * mode when acting as a master.
223 *
224 * Field Enumeration Values:
225 *
226 * Enum | Value | Description
227 * :--------------------------------------------|:------|:------------------
228 * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT | 0x0 | 7-bit addressing
229 * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT | 0x1 | 10-bit addressing
230 *
231 * Field Access Macros:
232 *
233 */
234/*
235 * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST
236 *
237 * 7-bit addressing
238 */
239#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0
240/*
241 * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST
242 *
243 * 10-bit addressing
244 */
245#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1
246
247/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */
248#define ALT_I2C_CON_IC_10BITADDR_MST_LSB 4
249/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */
250#define ALT_I2C_CON_IC_10BITADDR_MST_MSB 4
251/* The width in bits of the ALT_I2C_CON_IC_10BITADDR_MST register field. */
252#define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH 1
253/* The mask used to set the ALT_I2C_CON_IC_10BITADDR_MST register field value. */
254#define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK 0x00000010
255/* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_MST register field value. */
256#define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK 0xffffffef
257/* The reset value of the ALT_I2C_CON_IC_10BITADDR_MST register field. */
258#define ALT_I2C_CON_IC_10BITADDR_MST_RESET 0x1
259/* Extracts the ALT_I2C_CON_IC_10BITADDR_MST field value from a register. */
260#define ALT_I2C_CON_IC_10BITADDR_MST_GET(value) (((value) & 0x00000010) >> 4)
261/* Produces a ALT_I2C_CON_IC_10BITADDR_MST register field value suitable for setting the register. */
262#define ALT_I2C_CON_IC_10BITADDR_MST_SET(value) (((value) << 4) & 0x00000010)
263
264/*
265 * Field : Restart Enable - ic_restart_en
266 *
267 * Determines whether RESTART conditions may be sent when acting as a master. Some
268 * older slaves do not support handling RESTART conditions; however, RESTART
269 * conditions are used in several I2C operations. When RESTART is disabled, the
270 * master is prohibited from performing the following functions
271 *
272 * * Changing direction within a transfer (split),
273 *
274 * * Sending a START BYTE,
275 *
276 * * High-speed mode operation,
277 *
278 * * Combined format transfers in 7-bit addressing modes,
279 *
280 * * Read operation with a 10-bit address,
281 *
282 * * Sending multiple bytes per transfer,
283 *
284 * By replacing RESTART condition followed by a STOP and a subsequent START
285 * condition, split operations are broken down into multiple I2C transfers. If the
286 * above operations are performed, it will result in setting bit [6](tx_abort) of
287 * the Raw Interrupt Status Register.
288 *
289 * Field Enumeration Values:
290 *
291 * Enum | Value | Description
292 * :--------------------------------|:------|:-----------------------
293 * ALT_I2C_CON_IC_RESTART_EN_E_DIS | 0x0 | restart master disable
294 * ALT_I2C_CON_IC_RESTART_EN_E_EN | 0x1 | restart master enable
295 *
296 * Field Access Macros:
297 *
298 */
299/*
300 * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN
301 *
302 * restart master disable
303 */
304#define ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0
305/*
306 * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN
307 *
308 * restart master enable
309 */
310#define ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1
311
312/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */
313#define ALT_I2C_CON_IC_RESTART_EN_LSB 5
314/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */
315#define ALT_I2C_CON_IC_RESTART_EN_MSB 5
316/* The width in bits of the ALT_I2C_CON_IC_RESTART_EN register field. */
317#define ALT_I2C_CON_IC_RESTART_EN_WIDTH 1
318/* The mask used to set the ALT_I2C_CON_IC_RESTART_EN register field value. */
319#define ALT_I2C_CON_IC_RESTART_EN_SET_MSK 0x00000020
320/* The mask used to clear the ALT_I2C_CON_IC_RESTART_EN register field value. */
321#define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf
322/* The reset value of the ALT_I2C_CON_IC_RESTART_EN register field. */
323#define ALT_I2C_CON_IC_RESTART_EN_RESET 0x1
324/* Extracts the ALT_I2C_CON_IC_RESTART_EN field value from a register. */
325#define ALT_I2C_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5)
326/* Produces a ALT_I2C_CON_IC_RESTART_EN register field value suitable for setting the register. */
327#define ALT_I2C_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020)
328
329/*
330 * Field : Slave Disable - ic_slave_disable
331 *
332 * This bit controls whether I2C has its slave disabled. The slave will be
333 * disabled, after reset.
334 *
335 * NOTE: Software should ensure that if this bit is written with 0, then bit [0] of
336 * this register should also be written with a 0.
337 *
338 * Field Enumeration Values:
339 *
340 * Enum | Value | Description
341 * :-----------------------------|:------|:--------------
342 * ALT_I2C_CON_IC_SLV_DIS_E_DIS | 0x1 | slave disable
343 * ALT_I2C_CON_IC_SLV_DIS_E_EN | 0x0 | slave enable
344 *
345 * Field Access Macros:
346 *
347 */
348/*
349 * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS
350 *
351 * slave disable
352 */
353#define ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1
354/*
355 * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS
356 *
357 * slave enable
358 */
359#define ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0
360
361/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */
362#define ALT_I2C_CON_IC_SLV_DIS_LSB 6
363/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */
364#define ALT_I2C_CON_IC_SLV_DIS_MSB 6
365/* The width in bits of the ALT_I2C_CON_IC_SLV_DIS register field. */
366#define ALT_I2C_CON_IC_SLV_DIS_WIDTH 1
367/* The mask used to set the ALT_I2C_CON_IC_SLV_DIS register field value. */
368#define ALT_I2C_CON_IC_SLV_DIS_SET_MSK 0x00000040
369/* The mask used to clear the ALT_I2C_CON_IC_SLV_DIS register field value. */
370#define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK 0xffffffbf
371/* The reset value of the ALT_I2C_CON_IC_SLV_DIS register field. */
372#define ALT_I2C_CON_IC_SLV_DIS_RESET 0x1
373/* Extracts the ALT_I2C_CON_IC_SLV_DIS field value from a register. */
374#define ALT_I2C_CON_IC_SLV_DIS_GET(value) (((value) & 0x00000040) >> 6)
375/* Produces a ALT_I2C_CON_IC_SLV_DIS register field value suitable for setting the register. */
376#define ALT_I2C_CON_IC_SLV_DIS_SET(value) (((value) << 6) & 0x00000040)
377
378#ifndef __ASSEMBLY__
379/*
380 * WARNING: The C register and register group struct declarations are provided for
381 * convenience and illustrative purposes. They should, however, be used with
382 * caution as the C language standard provides no guarantees about the alignment or
383 * atomicity of device memory accesses. The recommended practice for writing
384 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
385 * alt_write_word() functions.
386 *
387 * The struct declaration for register ALT_I2C_CON.
388 */
389 struct ALT_I2C_CON_s
390{
391 uint32_t master_mode : 1; /* Master Enable */
392 uint32_t speed : 2; /* Master Speed Control */
393 uint32_t ic_10bitaddr_slave : 1; /* Slave Address Size */
394 uint32_t ic_10bitaddr_master : 1; /* Master Address Size */
395 uint32_t ic_restart_en : 1; /* Restart Enable */
396 uint32_t ic_slave_disable : 1; /* Slave Disable */
397 uint32_t : 25; /* *UNDEFINED* */
398};
399
400/* The typedef declaration for register ALT_I2C_CON. */
401typedef volatile struct ALT_I2C_CON_s ALT_I2C_CON_t;
402#endif /* __ASSEMBLY__ */
403
404/* The byte offset of the ALT_I2C_CON register from the beginning of the component. */
405#define ALT_I2C_CON_OFST 0x0
406/* The address of the ALT_I2C_CON register. */
407#define ALT_I2C_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST))
408
409/*
410 * Register : Target Address Register - ic_tar
411 *
412 * This register can be written to only when the ic_enable register is set to 0.
413 * This register is 13 bits wide. All bits can be dynamically updated as long as
414 * any set of the following conditions are true,
415 *
416 * (Enable Register bit 0 is set to 0) or (Enable Register bit 0 is set to 1 AND
417 * (I2C is NOT engaged in any Master [tx, rx] operation [ic_status register
418 * mst_activity bit 5 is set to 0]) AND (I2C is enabled to operate in Master
419 * mode[ic_con bit[0] is set to one]) AND (there are NO entries in the TX FIFO
420 * Register [IC_STATUS bit [2] is set to 1])
421 *
422 * Register Layout
423 *
424 * Bits | Access | Reset | Description
425 * :--------|:-------|:------|:------------------------------
426 * [9:0] | RW | 0x55 | Master Target Address
427 * [10] | RW | 0x0 | General Call OR Start
428 * [11] | RW | 0x0 | Special
429 * [12] | RW | 0x1 | Master Addressing Bit Control
430 * [31:13] | ??? | 0x0 | *UNDEFINED*
431 *
432 */
433/*
434 * Field : Master Target Address - ic_tar
435 *
436 * This is the target address for any master transaction. When transmitting a
437 * General Call, these bits are ignored. To generate a START BYTE, the CPU needs to
438 * write only once into these bits. If the ic_tar and ic_sar are the same, loopback
439 * exists but the FIFOs are shared between master and slave, so full loopback is
440 * not feasible. Only one direction loopback mode is supported (simplex), not
441 * duplex. A master cannot transmit to itself; it can transmit to only a slave.
442 *
443 * Field Access Macros:
444 *
445 */
446/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_TAR register field. */
447#define ALT_I2C_TAR_IC_TAR_LSB 0
448/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_TAR register field. */
449#define ALT_I2C_TAR_IC_TAR_MSB 9
450/* The width in bits of the ALT_I2C_TAR_IC_TAR register field. */
451#define ALT_I2C_TAR_IC_TAR_WIDTH 10
452/* The mask used to set the ALT_I2C_TAR_IC_TAR register field value. */
453#define ALT_I2C_TAR_IC_TAR_SET_MSK 0x000003ff
454/* The mask used to clear the ALT_I2C_TAR_IC_TAR register field value. */
455#define ALT_I2C_TAR_IC_TAR_CLR_MSK 0xfffffc00
456/* The reset value of the ALT_I2C_TAR_IC_TAR register field. */
457#define ALT_I2C_TAR_IC_TAR_RESET 0x55
458/* Extracts the ALT_I2C_TAR_IC_TAR field value from a register. */
459#define ALT_I2C_TAR_IC_TAR_GET(value) (((value) & 0x000003ff) >> 0)
460/* Produces a ALT_I2C_TAR_IC_TAR register field value suitable for setting the register. */
461#define ALT_I2C_TAR_IC_TAR_SET(value) (((value) << 0) & 0x000003ff)
462
463/*
464 * Field : General Call OR Start - gc_or_start
465 *
466 * If bit 11 (SPECIAL) of this Register is set to 1, then this bit indicates
467 * whether a General Call or START byte command is to be performed by the I2C or
468 * General Call Address after issuing a General Call, only writes may be performed.
469 * Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the Raw
470 * Interrupt_Status register. The I2C remains in General Call mode until the
471 * special bit value (bit 11) is cleared.
472 *
473 * Field Enumeration Values:
474 *
475 * Enum | Value | Description
476 * :------------------------------------|:------|:-------------
477 * ALT_I2C_TAR_GC_OR_START_E_GENCALL | 0x0 | General Call
478 * ALT_I2C_TAR_GC_OR_START_E_STARTBYTE | 0x1 | START Byte
479 *
480 * Field Access Macros:
481 *
482 */
483/*
484 * Enumerated value for register field ALT_I2C_TAR_GC_OR_START
485 *
486 * General Call
487 */
488#define ALT_I2C_TAR_GC_OR_START_E_GENCALL 0x0
489/*
490 * Enumerated value for register field ALT_I2C_TAR_GC_OR_START
491 *
492 * START Byte
493 */
494#define ALT_I2C_TAR_GC_OR_START_E_STARTBYTE 0x1
495
496/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_GC_OR_START register field. */
497#define ALT_I2C_TAR_GC_OR_START_LSB 10
498/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_GC_OR_START register field. */
499#define ALT_I2C_TAR_GC_OR_START_MSB 10
500/* The width in bits of the ALT_I2C_TAR_GC_OR_START register field. */
501#define ALT_I2C_TAR_GC_OR_START_WIDTH 1
502/* The mask used to set the ALT_I2C_TAR_GC_OR_START register field value. */
503#define ALT_I2C_TAR_GC_OR_START_SET_MSK 0x00000400
504/* The mask used to clear the ALT_I2C_TAR_GC_OR_START register field value. */
505#define ALT_I2C_TAR_GC_OR_START_CLR_MSK 0xfffffbff
506/* The reset value of the ALT_I2C_TAR_GC_OR_START register field. */
507#define ALT_I2C_TAR_GC_OR_START_RESET 0x0
508/* Extracts the ALT_I2C_TAR_GC_OR_START field value from a register. */
509#define ALT_I2C_TAR_GC_OR_START_GET(value) (((value) & 0x00000400) >> 10)
510/* Produces a ALT_I2C_TAR_GC_OR_START register field value suitable for setting the register. */
511#define ALT_I2C_TAR_GC_OR_START_SET(value) (((value) << 10) & 0x00000400)
512
513/*
514 * Field : Special - special
515 *
516 * This bit indicates whether software performs a General Call or START BYTE
517 * command.
518 *
519 * Field Enumeration Values:
520 *
521 * Enum | Value | Description
522 * :--------------------------------|:------|:--------------------------------------------
523 * ALT_I2C_TAR_SPECIAL_E_GENCALL | 0x0 | Ignore bit 10 gc_or_start and use ic_tar
524 * : | | normally
525 * ALT_I2C_TAR_SPECIAL_E_STARTBYTE | 0x1 | Perform special I2C command as specified in
526 * : | | gc_or_start
527 *
528 * Field Access Macros:
529 *
530 */
531/*
532 * Enumerated value for register field ALT_I2C_TAR_SPECIAL
533 *
534 * Ignore bit 10 gc_or_start and use ic_tar normally
535 */
536#define ALT_I2C_TAR_SPECIAL_E_GENCALL 0x0
537/*
538 * Enumerated value for register field ALT_I2C_TAR_SPECIAL
539 *
540 * Perform special I2C command as specified in gc_or_start
541 */
542#define ALT_I2C_TAR_SPECIAL_E_STARTBYTE 0x1
543
544/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_SPECIAL register field. */
545#define ALT_I2C_TAR_SPECIAL_LSB 11
546/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_SPECIAL register field. */
547#define ALT_I2C_TAR_SPECIAL_MSB 11
548/* The width in bits of the ALT_I2C_TAR_SPECIAL register field. */
549#define ALT_I2C_TAR_SPECIAL_WIDTH 1
550/* The mask used to set the ALT_I2C_TAR_SPECIAL register field value. */
551#define ALT_I2C_TAR_SPECIAL_SET_MSK 0x00000800
552/* The mask used to clear the ALT_I2C_TAR_SPECIAL register field value. */
553#define ALT_I2C_TAR_SPECIAL_CLR_MSK 0xfffff7ff
554/* The reset value of the ALT_I2C_TAR_SPECIAL register field. */
555#define ALT_I2C_TAR_SPECIAL_RESET 0x0
556/* Extracts the ALT_I2C_TAR_SPECIAL field value from a register. */
557#define ALT_I2C_TAR_SPECIAL_GET(value) (((value) & 0x00000800) >> 11)
558/* Produces a ALT_I2C_TAR_SPECIAL register field value suitable for setting the register. */
559#define ALT_I2C_TAR_SPECIAL_SET(value) (((value) << 11) & 0x00000800)
560
561/*
562 * Field : Master Addressing Bit Control - ic_10bitaddr_master
563 *
564 * This bit controls whether the i2c starts its transfers in 7-bit or 10-bit
565 * addressing mode when acting as a master.
566 *
567 * Field Enumeration Values:
568 *
569 * Enum | Value | Description
570 * :---------------------------------------|:------|:----------------------
571 * ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 | 0x0 | Master Address, 7bit
572 * ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 | 0x1 | Master Address, 10bit
573 *
574 * Field Access Macros:
575 *
576 */
577/*
578 * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST
579 *
580 * Master Address, 7bit
581 */
582#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 0x0
583/*
584 * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST
585 *
586 * Master Address, 10bit
587 */
588#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 0x1
589
590/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */
591#define ALT_I2C_TAR_IC_10BITADDR_MST_LSB 12
592/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */
593#define ALT_I2C_TAR_IC_10BITADDR_MST_MSB 12
594/* The width in bits of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */
595#define ALT_I2C_TAR_IC_10BITADDR_MST_WIDTH 1
596/* The mask used to set the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */
597#define ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK 0x00001000
598/* The mask used to clear the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */
599#define ALT_I2C_TAR_IC_10BITADDR_MST_CLR_MSK 0xffffefff
600/* The reset value of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */
601#define ALT_I2C_TAR_IC_10BITADDR_MST_RESET 0x1
602/* Extracts the ALT_I2C_TAR_IC_10BITADDR_MST field value from a register. */
603#define ALT_I2C_TAR_IC_10BITADDR_MST_GET(value) (((value) & 0x00001000) >> 12)
604/* Produces a ALT_I2C_TAR_IC_10BITADDR_MST register field value suitable for setting the register. */
605#define ALT_I2C_TAR_IC_10BITADDR_MST_SET(value) (((value) << 12) & 0x00001000)
606
607#ifndef __ASSEMBLY__
608/*
609 * WARNING: The C register and register group struct declarations are provided for
610 * convenience and illustrative purposes. They should, however, be used with
611 * caution as the C language standard provides no guarantees about the alignment or
612 * atomicity of device memory accesses. The recommended practice for writing
613 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
614 * alt_write_word() functions.
615 *
616 * The struct declaration for register ALT_I2C_TAR.
617 */
618 struct ALT_I2C_TAR_s
619{
620 uint32_t ic_tar : 10; /* Master Target Address */
621 uint32_t gc_or_start : 1; /* General Call OR Start */
622 uint32_t special : 1; /* Special */
623 uint32_t ic_10bitaddr_master : 1; /* Master Addressing Bit Control */
624 uint32_t : 19; /* *UNDEFINED* */
625};
626
627/* The typedef declaration for register ALT_I2C_TAR. */
628typedef volatile struct ALT_I2C_TAR_s ALT_I2C_TAR_t;
629#endif /* __ASSEMBLY__ */
630
631/* The byte offset of the ALT_I2C_TAR register from the beginning of the component. */
632#define ALT_I2C_TAR_OFST 0x4
633/* The address of the ALT_I2C_TAR register. */
634#define ALT_I2C_TAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TAR_OFST))
635
636/*
637 * Register : Slave Address Register - ic_sar
638 *
639 * Holds Address of Slave
640 *
641 * Register Layout
642 *
643 * Bits | Access | Reset | Description
644 * :--------|:-------|:------|:--------------
645 * [9:0] | RW | 0x55 | Slave Address
646 * [31:10] | ??? | 0x0 | *UNDEFINED*
647 *
648 */
649/*
650 * Field : Slave Address - ic_sar
651 *
652 * The Slave Address register holds the slave address when the I2C is operating as
653 * a slave. For 7-bit addressing, only Field Bits [6:0] of the Slave Address
654 * Register are used. This register can be written only when the I2C interface is
655 * disabled, which corresponds to field bit 0 of the Enable Register being set to
656 * 0. Writes at other times have no effect.
657 *
658 * Note, the default values cannot be any of the reserved address locations: that
659 * is,
660 *
661 * 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not
662 * guaranteed if you program the Slave Address Register or Target Address Register
663 * to a reserved value.
664 *
665 * Field Access Macros:
666 *
667 */
668/* The Least Significant Bit (LSB) position of the ALT_I2C_SAR_IC_SAR register field. */
669#define ALT_I2C_SAR_IC_SAR_LSB 0
670/* The Most Significant Bit (MSB) position of the ALT_I2C_SAR_IC_SAR register field. */
671#define ALT_I2C_SAR_IC_SAR_MSB 9
672/* The width in bits of the ALT_I2C_SAR_IC_SAR register field. */
673#define ALT_I2C_SAR_IC_SAR_WIDTH 10
674/* The mask used to set the ALT_I2C_SAR_IC_SAR register field value. */
675#define ALT_I2C_SAR_IC_SAR_SET_MSK 0x000003ff
676/* The mask used to clear the ALT_I2C_SAR_IC_SAR register field value. */
677#define ALT_I2C_SAR_IC_SAR_CLR_MSK 0xfffffc00
678/* The reset value of the ALT_I2C_SAR_IC_SAR register field. */
679#define ALT_I2C_SAR_IC_SAR_RESET 0x55
680/* Extracts the ALT_I2C_SAR_IC_SAR field value from a register. */
681#define ALT_I2C_SAR_IC_SAR_GET(value) (((value) & 0x000003ff) >> 0)
682/* Produces a ALT_I2C_SAR_IC_SAR register field value suitable for setting the register. */
683#define ALT_I2C_SAR_IC_SAR_SET(value) (((value) << 0) & 0x000003ff)
684
685#ifndef __ASSEMBLY__
686/*
687 * WARNING: The C register and register group struct declarations are provided for
688 * convenience and illustrative purposes. They should, however, be used with
689 * caution as the C language standard provides no guarantees about the alignment or
690 * atomicity of device memory accesses. The recommended practice for writing
691 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
692 * alt_write_word() functions.
693 *
694 * The struct declaration for register ALT_I2C_SAR.
695 */
696 struct ALT_I2C_SAR_s
697{
698 uint32_t ic_sar : 10; /* Slave Address */
699 uint32_t : 22; /* *UNDEFINED* */
700};
701
702/* The typedef declaration for register ALT_I2C_SAR. */
703typedef volatile struct ALT_I2C_SAR_s ALT_I2C_SAR_t;
704#endif /* __ASSEMBLY__ */
705
706/* The byte offset of the ALT_I2C_SAR register from the beginning of the component. */
707#define ALT_I2C_SAR_OFST 0x8
708/* The address of the ALT_I2C_SAR register. */
709#define ALT_I2C_SAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SAR_OFST))
710
711/*
712 * Register : Tx Rx Data and Command Register - ic_data_cmd
713 *
714 * This is the register the CPU writes to when filling the TX FIFO. Reading from
715 * this register returns bytes from RX FIFO.
716 *
717 * Register Layout
718 *
719 * Bits | Access | Reset | Description
720 * :--------|:-------|:------|:--------------------------
721 * [7:0] | RW | 0x0 | Tx Rx Data
722 * [8] | W | 0x0 | Master Read Write Control
723 * [9] | W | 0x0 | Generate Stop
724 * [10] | W | 0x0 | Generate Restart
725 * [31:11] | ??? | 0x0 | *UNDEFINED*
726 *
727 */
728/*
729 * Field : Tx Rx Data - dat
730 *
731 * This Field contains the data to be transmitted or received on the I2C bus. If
732 * you are writing to these bits and want to perform a read, bits 7:0 (dat) are
733 * ignored by the I2C. However, when you read from this register, these bits return
734 * the value of data received on the I2C interface.
735 *
736 * Field Access Macros:
737 *
738 */
739/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_DAT register field. */
740#define ALT_I2C_DATA_CMD_DAT_LSB 0
741/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_DAT register field. */
742#define ALT_I2C_DATA_CMD_DAT_MSB 7
743/* The width in bits of the ALT_I2C_DATA_CMD_DAT register field. */
744#define ALT_I2C_DATA_CMD_DAT_WIDTH 8
745/* The mask used to set the ALT_I2C_DATA_CMD_DAT register field value. */
746#define ALT_I2C_DATA_CMD_DAT_SET_MSK 0x000000ff
747/* The mask used to clear the ALT_I2C_DATA_CMD_DAT register field value. */
748#define ALT_I2C_DATA_CMD_DAT_CLR_MSK 0xffffff00
749/* The reset value of the ALT_I2C_DATA_CMD_DAT register field. */
750#define ALT_I2C_DATA_CMD_DAT_RESET 0x0
751/* Extracts the ALT_I2C_DATA_CMD_DAT field value from a register. */
752#define ALT_I2C_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0)
753/* Produces a ALT_I2C_DATA_CMD_DAT register field value suitable for setting the register. */
754#define ALT_I2C_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff)
755
756/*
757 * Field : Master Read Write Control - cmd
758 *
759 * This bit controls whether a read or a write is performed. This bit does not
760 * control the direction when the I2C acts as a slave. It controls only the
761 * direction when it acts as a master. When a command is entered in the TX FIFO,
762 * this bit distinguishes the write and read commands. In slave-receiver mode, this
763 * bit is a 'don't care' because writes to this register are not required. In
764 * slave-transmitter mode, a '0' indicates that the CPU data is to be transmitted.
765 * When programming this bit, you should remember the following: attempting to
766 * perform a read operation after a General Call command has been sent results in a
767 * tx_abrt interrupt (bit 6 of the Raw Intr Status Register), unless bit 11 special
768 * in the Target Address Register has been cleared. If a '1' is written to this bit
769 * after receiving a RD_REQ interrupt, then a tx_abrt interrupt occurs.
770 *
771 * NOTE: It is possible that while attempting a master I2C read transfer on I2C, a
772 * RD_REQ interrupt may have occurred simultaneously due to a remote I2C master
773 * addressing I2C. In this type of scenario, I2C ignores the Data Cmd write,
774 * generates a tx_abrt interrupt, and waits to service the RD_REQ interrupt.
775 *
776 * Field Enumeration Values:
777 *
778 * Enum | Value | Description
779 * :--------------------------|:------|:-------------
780 * ALT_I2C_DATA_CMD_CMD_E_RD | 0x1 | Master Read
781 * ALT_I2C_DATA_CMD_CMD_E_WR | 0x0 | Master Write
782 *
783 * Field Access Macros:
784 *
785 */
786/*
787 * Enumerated value for register field ALT_I2C_DATA_CMD_CMD
788 *
789 * Master Read
790 */
791#define ALT_I2C_DATA_CMD_CMD_E_RD 0x1
792/*
793 * Enumerated value for register field ALT_I2C_DATA_CMD_CMD
794 *
795 * Master Write
796 */
797#define ALT_I2C_DATA_CMD_CMD_E_WR 0x0
798
799/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_CMD register field. */
800#define ALT_I2C_DATA_CMD_CMD_LSB 8
801/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_CMD register field. */
802#define ALT_I2C_DATA_CMD_CMD_MSB 8
803/* The width in bits of the ALT_I2C_DATA_CMD_CMD register field. */
804#define ALT_I2C_DATA_CMD_CMD_WIDTH 1
805/* The mask used to set the ALT_I2C_DATA_CMD_CMD register field value. */
806#define ALT_I2C_DATA_CMD_CMD_SET_MSK 0x00000100
807/* The mask used to clear the ALT_I2C_DATA_CMD_CMD register field value. */
808#define ALT_I2C_DATA_CMD_CMD_CLR_MSK 0xfffffeff
809/* The reset value of the ALT_I2C_DATA_CMD_CMD register field. */
810#define ALT_I2C_DATA_CMD_CMD_RESET 0x0
811/* Extracts the ALT_I2C_DATA_CMD_CMD field value from a register. */
812#define ALT_I2C_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8)
813/* Produces a ALT_I2C_DATA_CMD_CMD register field value suitable for setting the register. */
814#define ALT_I2C_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100)
815
816/*
817 * Field : Generate Stop - stop
818 *
819 * This bit controls whether a STOP is issued after the byte is sent or received.
820 *
821 * 1 = STOP is issued after this byte, regardless of whether or not the Tx FIFO is
822 * empty. If the Tx FIFO is not empty, the master immediately tries to start a new
823 * transfer by issuing a START and arbitrating for the bus.
824 *
825 * 0 = STOP is not issued after this byte, regardless of whether or not the Tx FIFO
826 * is empty. If the Tx FIFO is not empty, the master continues the current transfer
827 * by sending/receiving data bytes according to the value of the CMD bit. If the Tx
828 * FIFO is empty, the master holds the SCL line low and stalls the bus until a new
829 * command is available in the Tx FIFO.
830 *
831 * Field Enumeration Values:
832 *
833 * Enum | Value | Description
834 * :--------------------------------|:------|:------------------
835 * ALT_I2C_DATA_CMD_STOP_E_STOP | 0x1 | Issue Stop
836 * ALT_I2C_DATA_CMD_STOP_E_NO_STOP | 0x0 | Do Not Issue Stop
837 *
838 * Field Access Macros:
839 *
840 */
841/*
842 * Enumerated value for register field ALT_I2C_DATA_CMD_STOP
843 *
844 * Issue Stop
845 */
846#define ALT_I2C_DATA_CMD_STOP_E_STOP 0x1
847/*
848 * Enumerated value for register field ALT_I2C_DATA_CMD_STOP
849 *
850 * Do Not Issue Stop
851 */
852#define ALT_I2C_DATA_CMD_STOP_E_NO_STOP 0x0
853
854/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_STOP register field. */
855#define ALT_I2C_DATA_CMD_STOP_LSB 9
856/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_STOP register field. */
857#define ALT_I2C_DATA_CMD_STOP_MSB 9
858/* The width in bits of the ALT_I2C_DATA_CMD_STOP register field. */
859#define ALT_I2C_DATA_CMD_STOP_WIDTH 1
860/* The mask used to set the ALT_I2C_DATA_CMD_STOP register field value. */
861#define ALT_I2C_DATA_CMD_STOP_SET_MSK 0x00000200
862/* The mask used to clear the ALT_I2C_DATA_CMD_STOP register field value. */
863#define ALT_I2C_DATA_CMD_STOP_CLR_MSK 0xfffffdff
864/* The reset value of the ALT_I2C_DATA_CMD_STOP register field. */
865#define ALT_I2C_DATA_CMD_STOP_RESET 0x0
866/* Extracts the ALT_I2C_DATA_CMD_STOP field value from a register. */
867#define ALT_I2C_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9)
868/* Produces a ALT_I2C_DATA_CMD_STOP register field value suitable for setting the register. */
869#define ALT_I2C_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200)
870
871/*
872 * Field : Generate Restart - restart
873 *
874 * This bit controls whether a RESTART is issued before the byte is sent or
875 * received.
876 *
877 * 1 = A RESTART is issued before the data is sent/received (according to the value
878 * of CMD), regardless of whether or not the transfer direction is changing from
879 * the previous command.
880 *
881 * 0 = A RESTART is issued only if the transfer direction is changing from the
882 * previous command.
883 *
884 * Field Enumeration Values:
885 *
886 * Enum | Value | Description
887 * :-------------------------------------------------|:------|:----------------------------------
888 * ALT_I2C_DATA_CMD_RESTART_E_RESTART | 0x1 | Issue Restart
889 * ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE | 0x0 | Issue Restart On Direction Change
890 *
891 * Field Access Macros:
892 *
893 */
894/*
895 * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART
896 *
897 * Issue Restart
898 */
899#define ALT_I2C_DATA_CMD_RESTART_E_RESTART 0x1
900/*
901 * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART
902 *
903 * Issue Restart On Direction Change
904 */
905#define ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE 0x0
906
907/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */
908#define ALT_I2C_DATA_CMD_RESTART_LSB 10
909/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */
910#define ALT_I2C_DATA_CMD_RESTART_MSB 10
911/* The width in bits of the ALT_I2C_DATA_CMD_RESTART register field. */
912#define ALT_I2C_DATA_CMD_RESTART_WIDTH 1
913/* The mask used to set the ALT_I2C_DATA_CMD_RESTART register field value. */
914#define ALT_I2C_DATA_CMD_RESTART_SET_MSK 0x00000400
915/* The mask used to clear the ALT_I2C_DATA_CMD_RESTART register field value. */
916#define ALT_I2C_DATA_CMD_RESTART_CLR_MSK 0xfffffbff
917/* The reset value of the ALT_I2C_DATA_CMD_RESTART register field. */
918#define ALT_I2C_DATA_CMD_RESTART_RESET 0x0
919/* Extracts the ALT_I2C_DATA_CMD_RESTART field value from a register. */
920#define ALT_I2C_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10)
921/* Produces a ALT_I2C_DATA_CMD_RESTART register field value suitable for setting the register. */
922#define ALT_I2C_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400)
923
924#ifndef __ASSEMBLY__
925/*
926 * WARNING: The C register and register group struct declarations are provided for
927 * convenience and illustrative purposes. They should, however, be used with
928 * caution as the C language standard provides no guarantees about the alignment or
929 * atomicity of device memory accesses. The recommended practice for writing
930 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
931 * alt_write_word() functions.
932 *
933 * The struct declaration for register ALT_I2C_DATA_CMD.
934 */
935 struct ALT_I2C_DATA_CMD_s
936{
937 uint32_t dat : 8; /* Tx Rx Data */
938 uint32_t cmd : 1; /* Master Read Write Control */
939 uint32_t stop : 1; /* Generate Stop */
940 uint32_t restart : 1; /* Generate Restart */
941 uint32_t : 21; /* *UNDEFINED* */
942};
943
944/* The typedef declaration for register ALT_I2C_DATA_CMD. */
945typedef volatile struct ALT_I2C_DATA_CMD_s ALT_I2C_DATA_CMD_t;
946#endif /* __ASSEMBLY__ */
947
948/* The byte offset of the ALT_I2C_DATA_CMD register from the beginning of the component. */
949#define ALT_I2C_DATA_CMD_OFST 0x10
950/* The address of the ALT_I2C_DATA_CMD register. */
951#define ALT_I2C_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DATA_CMD_OFST))
952
953/*
954 * Register : Std Spd Clock SCL HCNT Register - ic_ss_scl_hcnt
955 *
956 * This register sets the SCL clock high-period count for standard speed.
957 *
958 * Register Layout
959 *
960 * Bits | Access | Reset | Description
961 * :--------|:-------|:------|:------------------------
962 * [15:0] | RW | 0x190 | Std Spd SCL High Period
963 * [31:16] | ??? | 0x0 | *UNDEFINED*
964 *
965 */
966/*
967 * Field : Std Spd SCL High Period - ic_ss_scl_hcnt
968 *
969 * This register must be set before any I2C bus transaction can take place to
970 * ensure proper I/O timing. This field sets the SCL clock high-period count for
971 * standard speed. This register can be written only when the I2C interface is
972 * disabled which corresponds to the Enable Register being set to 0. Writes at
973 * other times have no effect. The minimum valid value is 6; hardware prevents
974 * values less than this being written, and if attempted results in 6 being set. It
975 * is readable and writeable.
976 *
977 * NOTE: This register must not be programmed to a value higher than 65525, because
978 * I2C uses a 16-bit counter to flag an I2C bus idle condition when this counter
979 * reaches a value of IC_SS_SCL_HCNT + 10.
980 *
981 * Field Access Macros:
982 *
983 */
984/* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
985#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0
986/* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
987#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15
988/* The width in bits of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
989#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_WIDTH 16
990/* The mask used to set the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */
991#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK 0x0000ffff
992/* The mask used to clear the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */
993#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_CLR_MSK 0xffff0000
994/* The reset value of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
995#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x190
996/* Extracts the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT field value from a register. */
997#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
998/* Produces a ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value suitable for setting the register. */
999#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
1000
1001#ifndef __ASSEMBLY__
1002/*
1003 * WARNING: The C register and register group struct declarations are provided for
1004 * convenience and illustrative purposes. They should, however, be used with
1005 * caution as the C language standard provides no guarantees about the alignment or
1006 * atomicity of device memory accesses. The recommended practice for writing
1007 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1008 * alt_write_word() functions.
1009 *
1010 * The struct declaration for register ALT_I2C_SS_SCL_HCNT.
1011 */
1012 struct ALT_I2C_SS_SCL_HCNT_s
1013{
1014 uint32_t ic_ss_scl_hcnt : 16; /* Std Spd SCL High Period */
1015 uint32_t : 16; /* *UNDEFINED* */
1016};
1017
1018/* The typedef declaration for register ALT_I2C_SS_SCL_HCNT. */
1019typedef volatile struct ALT_I2C_SS_SCL_HCNT_s ALT_I2C_SS_SCL_HCNT_t;
1020#endif /* __ASSEMBLY__ */
1021
1022/* The byte offset of the ALT_I2C_SS_SCL_HCNT register from the beginning of the component. */
1023#define ALT_I2C_SS_SCL_HCNT_OFST 0x14
1024/* The address of the ALT_I2C_SS_SCL_HCNT register. */
1025#define ALT_I2C_SS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_HCNT_OFST))
1026
1027/*
1028 * Register : Std Spd Clock SCL LCNT Register - ic_ss_scl_lcnt
1029 *
1030 * This register sets the SCL clock low-period count for standard speed
1031 *
1032 * Register Layout
1033 *
1034 * Bits | Access | Reset | Description
1035 * :--------|:-------|:------|:-----------------------
1036 * [15:0] | RW | 0x1d6 | Std Spd SCL Low Period
1037 * [31:16] | ??? | 0x0 | *UNDEFINED*
1038 *
1039 */
1040/*
1041 * Field : Std Spd SCL Low Period - ic_ss_scl_lcnt
1042 *
1043 * This register must be set before any I2C bus transaction can take place to
1044 * ensure proper I/O timing. This field sets the SCL clock low period count for
1045 * standard speed. This register can be written only when the I2C interface is
1046 * disabled which corresponds to the Enable Register register being set to 0.
1047 * Writes at other times have no effect. The minimum valid value is 8; hardware
1048 * prevents values less than this from being written, and if attempted, results in
1049 * 8 being set.
1050 *
1051 * Field Access Macros:
1052 *
1053 */
1054/* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
1055#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0
1056/* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
1057#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15
1058/* The width in bits of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
1059#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_WIDTH 16
1060/* The mask used to set the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */
1061#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK 0x0000ffff
1062/* The mask used to clear the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */
1063#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_CLR_MSK 0xffff0000
1064/* The reset value of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
1065#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x1d6
1066/* Extracts the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT field value from a register. */
1067#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1068/* Produces a ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value suitable for setting the register. */
1069#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
1070
1071#ifndef __ASSEMBLY__
1072/*
1073 * WARNING: The C register and register group struct declarations are provided for
1074 * convenience and illustrative purposes. They should, however, be used with
1075 * caution as the C language standard provides no guarantees about the alignment or
1076 * atomicity of device memory accesses. The recommended practice for writing
1077 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1078 * alt_write_word() functions.
1079 *
1080 * The struct declaration for register ALT_I2C_SS_SCL_LCNT.
1081 */
1082 struct ALT_I2C_SS_SCL_LCNT_s
1083{
1084 uint32_t ic_ss_scl_lcnt : 16; /* Std Spd SCL Low Period */
1085 uint32_t : 16; /* *UNDEFINED* */
1086};
1087
1088/* The typedef declaration for register ALT_I2C_SS_SCL_LCNT. */
1089typedef volatile struct ALT_I2C_SS_SCL_LCNT_s ALT_I2C_SS_SCL_LCNT_t;
1090#endif /* __ASSEMBLY__ */
1091
1092/* The byte offset of the ALT_I2C_SS_SCL_LCNT register from the beginning of the component. */
1093#define ALT_I2C_SS_SCL_LCNT_OFST 0x18
1094/* The address of the ALT_I2C_SS_SCL_LCNT register. */
1095#define ALT_I2C_SS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_LCNT_OFST))
1096
1097/*
1098 * Register : Fast Spd Clock SCL HCNT Register - ic_fs_scl_hcnt
1099 *
1100 * This register sets the SCL clock high-period count for fast speed
1101 *
1102 * Register Layout
1103 *
1104 * Bits | Access | Reset | Description
1105 * :--------|:-------|:------|:-------------------------
1106 * [15:0] | RW | 0x3c | Fast Spd SCL High Period
1107 * [31:16] | ??? | 0x0 | *UNDEFINED*
1108 *
1109 */
1110/*
1111 * Field : Fast Spd SCL High Period - ic_fs_scl_hcnt
1112 *
1113 * This register must be set before any I2C bus transaction can take place to
1114 * ensure proper I/O timing. This register sets the SCL clock high-period count for
1115 * fast speed. It is used in high-speed mode to send the Master Code and START BYTE
1116 * or General CALL. This register goes away and becomes read-only returning 0s if
1117 * in Standard Speed Mode. This register can be written only when the I2C interface
1118 * is disabled, which corresponds to the Enable Register being set to 0. Writes at
1119 * other times have no effect. The minimum valid value is 6; hardware prevents
1120 * values less than this from being written, and if attempted results in 6 being
1121 * set.
1122 *
1123 * Field Access Macros:
1124 *
1125 */
1126/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
1127#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0
1128/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
1129#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15
1130/* The width in bits of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
1131#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_WIDTH 16
1132/* The mask used to set the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */
1133#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK 0x0000ffff
1134/* The mask used to clear the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */
1135#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_CLR_MSK 0xffff0000
1136/* The reset value of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
1137#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x3c
1138/* Extracts the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT field value from a register. */
1139#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1140/* Produces a ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value suitable for setting the register. */
1141#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
1142
1143#ifndef __ASSEMBLY__
1144/*
1145 * WARNING: The C register and register group struct declarations are provided for
1146 * convenience and illustrative purposes. They should, however, be used with
1147 * caution as the C language standard provides no guarantees about the alignment or
1148 * atomicity of device memory accesses. The recommended practice for writing
1149 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1150 * alt_write_word() functions.
1151 *
1152 * The struct declaration for register ALT_I2C_FS_SCL_HCNT.
1153 */
1154 struct ALT_I2C_FS_SCL_HCNT_s
1155{
1156 uint32_t ic_fs_scl_hcnt : 16; /* Fast Spd SCL High Period */
1157 uint32_t : 16; /* *UNDEFINED* */
1158};
1159
1160/* The typedef declaration for register ALT_I2C_FS_SCL_HCNT. */
1161typedef volatile struct ALT_I2C_FS_SCL_HCNT_s ALT_I2C_FS_SCL_HCNT_t;
1162#endif /* __ASSEMBLY__ */
1163
1164/* The byte offset of the ALT_I2C_FS_SCL_HCNT register from the beginning of the component. */
1165#define ALT_I2C_FS_SCL_HCNT_OFST 0x1c
1166/* The address of the ALT_I2C_FS_SCL_HCNT register. */
1167#define ALT_I2C_FS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_HCNT_OFST))
1168
1169/*
1170 * Register : Fast Spd Clock SCL LCNT Register - ic_fs_scl_lcnt
1171 *
1172 * This register sets the SCL clock low period count
1173 *
1174 * Register Layout
1175 *
1176 * Bits | Access | Reset | Description
1177 * :--------|:-------|:------|:------------------------
1178 * [15:0] | RW | 0x82 | Fast Spd SCL Low Period
1179 * [31:16] | ??? | 0x0 | *UNDEFINED*
1180 *
1181 */
1182/*
1183 * Field : Fast Spd SCL Low Period - ic_fs_scl_lcnt
1184 *
1185 * This register must be set before any I2C bus transaction can take place to
1186 * ensure proper I/O timing. This field sets the SCL clock low period count for
1187 * fast speed. It is used in high-speed mode to send the Master Code and START BYTE
1188 * or General CALL. This register can be written only when the I2C interface is
1189 * disabled, which corresponds to the Enable Register being set to 0. Writes at
1190 * other times have no effect.The minimum valid value is 8; hardware prevents
1191 * values less than this being written, and if attempted results in 8 being set.
1192 *
1193 * Field Access Macros:
1194 *
1195 */
1196/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
1197#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0
1198/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
1199#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15
1200/* The width in bits of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
1201#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_WIDTH 16
1202/* The mask used to set the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */
1203#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK 0x0000ffff
1204/* The mask used to clear the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */
1205#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_CLR_MSK 0xffff0000
1206/* The reset value of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
1207#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x82
1208/* Extracts the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT field value from a register. */
1209#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1210/* Produces a ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value suitable for setting the register. */
1211#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
1212
1213#ifndef __ASSEMBLY__
1214/*
1215 * WARNING: The C register and register group struct declarations are provided for
1216 * convenience and illustrative purposes. They should, however, be used with
1217 * caution as the C language standard provides no guarantees about the alignment or
1218 * atomicity of device memory accesses. The recommended practice for writing
1219 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1220 * alt_write_word() functions.
1221 *
1222 * The struct declaration for register ALT_I2C_FS_SCL_LCNT.
1223 */
1224 struct ALT_I2C_FS_SCL_LCNT_s
1225{
1226 uint32_t ic_fs_scl_lcnt : 16; /* Fast Spd SCL Low Period */
1227 uint32_t : 16; /* *UNDEFINED* */
1228};
1229
1230/* The typedef declaration for register ALT_I2C_FS_SCL_LCNT. */
1231typedef volatile struct ALT_I2C_FS_SCL_LCNT_s ALT_I2C_FS_SCL_LCNT_t;
1232#endif /* __ASSEMBLY__ */
1233
1234/* The byte offset of the ALT_I2C_FS_SCL_LCNT register from the beginning of the component. */
1235#define ALT_I2C_FS_SCL_LCNT_OFST 0x20
1236/* The address of the ALT_I2C_FS_SCL_LCNT register. */
1237#define ALT_I2C_FS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_LCNT_OFST))
1238
1239/*
1240 * Register : Interrupt Status Register - ic_intr_stat
1241 *
1242 * Each bit in this register has a corresponding mask bit in the Interrupt Mask
1243 * Register. These bits are cleared by reading the matching Interrupt Clear
1244 * Register. The unmasked raw versions of these bits are available in the Raw
1245 * Interrupt Status Register.
1246 *
1247 * Register Layout
1248 *
1249 * Bits | Access | Reset | Description
1250 * :--------|:-------|:------|:-------------------------
1251 * [0] | R | 0x0 | Receiver Under
1252 * [1] | R | 0x0 | Receiver Over
1253 * [2] | R | 0x0 | Receive Full
1254 * [3] | R | 0x0 | Interrupt Transmit Over
1255 * [4] | R | 0x0 | Interrupt Transmit Empty
1256 * [5] | R | 0x0 | Interrupt Read Request
1257 * [6] | R | 0x0 | Interrupt TX Abort
1258 * [7] | R | 0x0 | Interrupt RX Done
1259 * [8] | R | 0x0 | Interrupt R_activity
1260 * [9] | R | 0x0 | Interrupt Stop Detect
1261 * [10] | R | 0x0 | Interrupt Start Detect
1262 * [11] | R | 0x0 | Interrupt General Call
1263 * [31:12] | ??? | 0x0 | *UNDEFINED*
1264 *
1265 */
1266/*
1267 * Field : Receiver Under - r_rx_under
1268 *
1269 * Set if the processor attempts to read the receive buffer when it is empty by
1270 * reading from the Tx Rx Data and Command Register. If the module is disabled,
1271 * Enable Register is set to 0, this bit keeps its level until the master or slave
1272 * state machines go into idle, then this interrupt is cleared.
1273 *
1274 * Field Access Macros:
1275 *
1276 */
1277/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */
1278#define ALT_I2C_INTR_STAT_R_RX_UNDER_LSB 0
1279/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */
1280#define ALT_I2C_INTR_STAT_R_RX_UNDER_MSB 0
1281/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */
1282#define ALT_I2C_INTR_STAT_R_RX_UNDER_WIDTH 1
1283/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */
1284#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001
1285/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */
1286#define ALT_I2C_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe
1287/* The reset value of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */
1288#define ALT_I2C_INTR_STAT_R_RX_UNDER_RESET 0x0
1289/* Extracts the ALT_I2C_INTR_STAT_R_RX_UNDER field value from a register. */
1290#define ALT_I2C_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
1291/* Produces a ALT_I2C_INTR_STAT_R_RX_UNDER register field value suitable for setting the register. */
1292#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
1293
1294/*
1295 * Field : Receiver Over - r_rx_over
1296 *
1297 * Set if the receive buffer is completely filled to 64 and an additional byte is
1298 * received from an external I2C device. The I2C acknowledges this, but any data
1299 * bytes received after the FIFO is full are lost. If the module is disabled,
1300 * Enable Register bit[0] is set to 0 this bit keeps its level until the master or
1301 * slave state machines go into idle, then this interrupt is cleared.
1302 *
1303 * Field Access Macros:
1304 *
1305 */
1306/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */
1307#define ALT_I2C_INTR_STAT_R_RX_OVER_LSB 1
1308/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */
1309#define ALT_I2C_INTR_STAT_R_RX_OVER_MSB 1
1310/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */
1311#define ALT_I2C_INTR_STAT_R_RX_OVER_WIDTH 1
1312/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */
1313#define ALT_I2C_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002
1314/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */
1315#define ALT_I2C_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd
1316/* The reset value of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */
1317#define ALT_I2C_INTR_STAT_R_RX_OVER_RESET 0x0
1318/* Extracts the ALT_I2C_INTR_STAT_R_RX_OVER field value from a register. */
1319#define ALT_I2C_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
1320/* Produces a ALT_I2C_INTR_STAT_R_RX_OVER register field value suitable for setting the register. */
1321#define ALT_I2C_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
1322
1323/*
1324 * Field : Receive Full - r_rx_full
1325 *
1326 * Set when the receive buffer reaches or goes above the Receive FIFO Threshold
1327 * Value(rx_tl). It is automatically cleared by hardware when buffer level goes
1328 * below the threshold. If the module is disabled, Bit [0] of the Enable Register
1329 * set to 0, the RX FIFO is flushed and held in reset; therefore the RX FIFO is not
1330 * full. So this bit is cleared once the Enable Register Bit 0 is programmed with a
1331 * 0, regardless of the activity that continues.
1332 *
1333 * Field Access Macros:
1334 *
1335 */
1336/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */
1337#define ALT_I2C_INTR_STAT_R_RX_FULL_LSB 2
1338/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */
1339#define ALT_I2C_INTR_STAT_R_RX_FULL_MSB 2
1340/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */
1341#define ALT_I2C_INTR_STAT_R_RX_FULL_WIDTH 1
1342/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */
1343#define ALT_I2C_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004
1344/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */
1345#define ALT_I2C_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb
1346/* The reset value of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */
1347#define ALT_I2C_INTR_STAT_R_RX_FULL_RESET 0x0
1348/* Extracts the ALT_I2C_INTR_STAT_R_RX_FULL field value from a register. */
1349#define ALT_I2C_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
1350/* Produces a ALT_I2C_INTR_STAT_R_RX_FULL register field value suitable for setting the register. */
1351#define ALT_I2C_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
1352
1353/*
1354 * Field : Interrupt Transmit Over - r_tx_over
1355 *
1356 * Set during transmit if the transmit buffer is filled to 64 and the processor
1357 * attempts to issue another I2C command by writing to the Data and Command
1358 * Register. When the module is disabled, this bit keeps its level until the master
1359 * or slave state machines goes into idle, then interrupt is cleared.
1360 *
1361 * Field Access Macros:
1362 *
1363 */
1364/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */
1365#define ALT_I2C_INTR_STAT_R_TX_OVER_LSB 3
1366/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */
1367#define ALT_I2C_INTR_STAT_R_TX_OVER_MSB 3
1368/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */
1369#define ALT_I2C_INTR_STAT_R_TX_OVER_WIDTH 1
1370/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */
1371#define ALT_I2C_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008
1372/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */
1373#define ALT_I2C_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7
1374/* The reset value of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */
1375#define ALT_I2C_INTR_STAT_R_TX_OVER_RESET 0x0
1376/* Extracts the ALT_I2C_INTR_STAT_R_TX_OVER field value from a register. */
1377#define ALT_I2C_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
1378/* Produces a ALT_I2C_INTR_STAT_R_TX_OVER register field value suitable for setting the register. */
1379#define ALT_I2C_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
1380
1381/*
1382 * Field : Interrupt Transmit Empty - r_tx_empty
1383 *
1384 * This bit is set to 1 when the transmit buffer is at or below the threshold value
1385 * set in the ic_tx_tl register. It is automatically cleared by hardware when the
1386 * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX
1387 * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data
1388 * within it, so this bit is set to 1, provided there is activity in the master or
1389 * slave state machines. When there is no longer activity, this bit is set to 0.
1390 *
1391 * Field Access Macros:
1392 *
1393 */
1394/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */
1395#define ALT_I2C_INTR_STAT_R_TX_EMPTY_LSB 4
1396/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */
1397#define ALT_I2C_INTR_STAT_R_TX_EMPTY_MSB 4
1398/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */
1399#define ALT_I2C_INTR_STAT_R_TX_EMPTY_WIDTH 1
1400/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */
1401#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010
1402/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */
1403#define ALT_I2C_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef
1404/* The reset value of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */
1405#define ALT_I2C_INTR_STAT_R_TX_EMPTY_RESET 0x0
1406/* Extracts the ALT_I2C_INTR_STAT_R_TX_EMPTY field value from a register. */
1407#define ALT_I2C_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
1408/* Produces a ALT_I2C_INTR_STAT_R_TX_EMPTY register field value suitable for setting the register. */
1409#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
1410
1411/*
1412 * Field : Interrupt Read Request - r_rd_req
1413 *
1414 * This bit is set to 1 when i2c is acting as a slave and another I2C master is
1415 * attempting to read data from I2C. The I2C holds the I2C bus in a wait state
1416 * (SCL=0) until this interrupt is serviced, which means that the slave has been
1417 * addressed by a remote master that is asking for data to be transferred. The
1418 * processor must respond to this interrupt and then write the requested data to
1419 * the IC_DATA_CMD register. This bit is set to 0 just after the processor reads
1420 * the ic_clr_rd_req register.
1421 *
1422 * Field Access Macros:
1423 *
1424 */
1425/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */
1426#define ALT_I2C_INTR_STAT_R_RD_REQ_LSB 5
1427/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */
1428#define ALT_I2C_INTR_STAT_R_RD_REQ_MSB 5
1429/* The width in bits of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */
1430#define ALT_I2C_INTR_STAT_R_RD_REQ_WIDTH 1
1431/* The mask used to set the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */
1432#define ALT_I2C_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020
1433/* The mask used to clear the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */
1434#define ALT_I2C_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf
1435/* The reset value of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */
1436#define ALT_I2C_INTR_STAT_R_RD_REQ_RESET 0x0
1437/* Extracts the ALT_I2C_INTR_STAT_R_RD_REQ field value from a register. */
1438#define ALT_I2C_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
1439/* Produces a ALT_I2C_INTR_STAT_R_RD_REQ register field value suitable for setting the register. */
1440#define ALT_I2C_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
1441
1442/*
1443 * Field : Interrupt TX Abort - r_tx_abrt
1444 *
1445 * This bit indicates if I2C, as an I2C transmitter, is unable to complete the
1446 * intended actions on the contents of the transmit FIFO. This situation can occur
1447 * both as an I2C master or an I2C slave, and is referred to as a 'transmit
1448 * abort'.When this bit is set to 1, the ic_tx_abrt_source register indicates the
1449 * reason why the transmit abort takes places.
1450 *
1451 * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The
1452 * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read.
1453 * Once this read is performed, the TX FIFO is then ready to accept more data bytes
1454 * from the APB interface.
1455 *
1456 * Field Access Macros:
1457 *
1458 */
1459/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */
1460#define ALT_I2C_INTR_STAT_R_TX_ABRT_LSB 6
1461/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */
1462#define ALT_I2C_INTR_STAT_R_TX_ABRT_MSB 6
1463/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */
1464#define ALT_I2C_INTR_STAT_R_TX_ABRT_WIDTH 1
1465/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */
1466#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040
1467/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */
1468#define ALT_I2C_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf
1469/* The reset value of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */
1470#define ALT_I2C_INTR_STAT_R_TX_ABRT_RESET 0x0
1471/* Extracts the ALT_I2C_INTR_STAT_R_TX_ABRT field value from a register. */
1472#define ALT_I2C_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
1473/* Produces a ALT_I2C_INTR_STAT_R_TX_ABRT register field value suitable for setting the register. */
1474#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
1475
1476/*
1477 * Field : Interrupt RX Done - r_rx_done
1478 *
1479 * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the
1480 * master does not acknowledge a transmitted byte. This occurs on the last byte of
1481 * the transmission, indicating that the transmission is done.
1482 *
1483 * Field Access Macros:
1484 *
1485 */
1486/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */
1487#define ALT_I2C_INTR_STAT_R_RX_DONE_LSB 7
1488/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */
1489#define ALT_I2C_INTR_STAT_R_RX_DONE_MSB 7
1490/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */
1491#define ALT_I2C_INTR_STAT_R_RX_DONE_WIDTH 1
1492/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */
1493#define ALT_I2C_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080
1494/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */
1495#define ALT_I2C_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f
1496/* The reset value of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */
1497#define ALT_I2C_INTR_STAT_R_RX_DONE_RESET 0x0
1498/* Extracts the ALT_I2C_INTR_STAT_R_RX_DONE field value from a register. */
1499#define ALT_I2C_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
1500/* Produces a ALT_I2C_INTR_STAT_R_RX_DONE register field value suitable for setting the register. */
1501#define ALT_I2C_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
1502
1503/*
1504 * Field : Interrupt R_activity - r_activity
1505 *
1506 * This bit captures I2C activity and stays set until it is cleared. There are four
1507 * ways to clear it:
1508 *
1509 * * Disabling the I2C
1510 *
1511 * * Reading the ic_clr_activity register
1512 *
1513 * * Reading the ic_clr_intr register
1514 *
1515 * * I2C reset
1516 *
1517 * Once this bit is set, it stays set unless one of the four methods is used to
1518 * clear it. Even if the I2C module is idle, this bit remains set until cleared,
1519 * indicating that there was activity on the bus.
1520 *
1521 * Field Access Macros:
1522 *
1523 */
1524/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */
1525#define ALT_I2C_INTR_STAT_R_ACTIVITY_LSB 8
1526/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */
1527#define ALT_I2C_INTR_STAT_R_ACTIVITY_MSB 8
1528/* The width in bits of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */
1529#define ALT_I2C_INTR_STAT_R_ACTIVITY_WIDTH 1
1530/* The mask used to set the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */
1531#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100
1532/* The mask used to clear the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */
1533#define ALT_I2C_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff
1534/* The reset value of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */
1535#define ALT_I2C_INTR_STAT_R_ACTIVITY_RESET 0x0
1536/* Extracts the ALT_I2C_INTR_STAT_R_ACTIVITY field value from a register. */
1537#define ALT_I2C_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
1538/* Produces a ALT_I2C_INTR_STAT_R_ACTIVITY register field value suitable for setting the register. */
1539#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
1540
1541/*
1542 * Field : Interrupt Stop Detect - r_stop_det
1543 *
1544 * Indicates whether a STOP condition has occurred on the I2C interface regardless
1545 * of whether I2C is operating in slave or master mode.
1546 *
1547 * Field Access Macros:
1548 *
1549 */
1550/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */
1551#define ALT_I2C_INTR_STAT_R_STOP_DET_LSB 9
1552/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */
1553#define ALT_I2C_INTR_STAT_R_STOP_DET_MSB 9
1554/* The width in bits of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */
1555#define ALT_I2C_INTR_STAT_R_STOP_DET_WIDTH 1
1556/* The mask used to set the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */
1557#define ALT_I2C_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200
1558/* The mask used to clear the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */
1559#define ALT_I2C_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff
1560/* The reset value of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */
1561#define ALT_I2C_INTR_STAT_R_STOP_DET_RESET 0x0
1562/* Extracts the ALT_I2C_INTR_STAT_R_STOP_DET field value from a register. */
1563#define ALT_I2C_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
1564/* Produces a ALT_I2C_INTR_STAT_R_STOP_DET register field value suitable for setting the register. */
1565#define ALT_I2C_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
1566
1567/*
1568 * Field : Interrupt Start Detect - r_start_det
1569 *
1570 * Indicates whether a START or RESTART condition has occurred on the I2C interface
1571 * regardless of whether I2C is operating in slave or master mode.
1572 *
1573 * Field Access Macros:
1574 *
1575 */
1576/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */
1577#define ALT_I2C_INTR_STAT_R_START_DET_LSB 10
1578/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */
1579#define ALT_I2C_INTR_STAT_R_START_DET_MSB 10
1580/* The width in bits of the ALT_I2C_INTR_STAT_R_START_DET register field. */
1581#define ALT_I2C_INTR_STAT_R_START_DET_WIDTH 1
1582/* The mask used to set the ALT_I2C_INTR_STAT_R_START_DET register field value. */
1583#define ALT_I2C_INTR_STAT_R_START_DET_SET_MSK 0x00000400
1584/* The mask used to clear the ALT_I2C_INTR_STAT_R_START_DET register field value. */
1585#define ALT_I2C_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff
1586/* The reset value of the ALT_I2C_INTR_STAT_R_START_DET register field. */
1587#define ALT_I2C_INTR_STAT_R_START_DET_RESET 0x0
1588/* Extracts the ALT_I2C_INTR_STAT_R_START_DET field value from a register. */
1589#define ALT_I2C_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10)
1590/* Produces a ALT_I2C_INTR_STAT_R_START_DET register field value suitable for setting the register. */
1591#define ALT_I2C_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400)
1592
1593/*
1594 * Field : Interrupt General Call - r_gen_call
1595 *
1596 * Set only when a General Call address is received and it is acknowledged. It
1597 * stays set until it is cleared either by disabling I2C or when the CPU reads bit
1598 * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx
1599 * buffer.
1600 *
1601 * Field Access Macros:
1602 *
1603 */
1604/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */
1605#define ALT_I2C_INTR_STAT_R_GEN_CALL_LSB 11
1606/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */
1607#define ALT_I2C_INTR_STAT_R_GEN_CALL_MSB 11
1608/* The width in bits of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */
1609#define ALT_I2C_INTR_STAT_R_GEN_CALL_WIDTH 1
1610/* The mask used to set the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */
1611#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800
1612/* The mask used to clear the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */
1613#define ALT_I2C_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff
1614/* The reset value of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */
1615#define ALT_I2C_INTR_STAT_R_GEN_CALL_RESET 0x0
1616/* Extracts the ALT_I2C_INTR_STAT_R_GEN_CALL field value from a register. */
1617#define ALT_I2C_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
1618/* Produces a ALT_I2C_INTR_STAT_R_GEN_CALL register field value suitable for setting the register. */
1619#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
1620
1621#ifndef __ASSEMBLY__
1622/*
1623 * WARNING: The C register and register group struct declarations are provided for
1624 * convenience and illustrative purposes. They should, however, be used with
1625 * caution as the C language standard provides no guarantees about the alignment or
1626 * atomicity of device memory accesses. The recommended practice for writing
1627 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1628 * alt_write_word() functions.
1629 *
1630 * The struct declaration for register ALT_I2C_INTR_STAT.
1631 */
1632 struct ALT_I2C_INTR_STAT_s
1633{
1634 const uint32_t r_rx_under : 1; /* Receiver Under */
1635 const uint32_t r_rx_over : 1; /* Receiver Over */
1636 const uint32_t r_rx_full : 1; /* Receive Full */
1637 const uint32_t r_tx_over : 1; /* Interrupt Transmit Over */
1638 const uint32_t r_tx_empty : 1; /* Interrupt Transmit Empty */
1639 const uint32_t r_rd_req : 1; /* Interrupt Read Request */
1640 const uint32_t r_tx_abrt : 1; /* Interrupt TX Abort */
1641 const uint32_t r_rx_done : 1; /* Interrupt RX Done */
1642 const uint32_t r_activity : 1; /* Interrupt R_activity */
1643 const uint32_t r_stop_det : 1; /* Interrupt Stop Detect */
1644 const uint32_t r_start_det : 1; /* Interrupt Start Detect */
1645 const uint32_t r_gen_call : 1; /* Interrupt General Call */
1646 uint32_t : 20; /* *UNDEFINED* */
1647};
1648
1649/* The typedef declaration for register ALT_I2C_INTR_STAT. */
1650typedef volatile struct ALT_I2C_INTR_STAT_s ALT_I2C_INTR_STAT_t;
1651#endif /* __ASSEMBLY__ */
1652
1653/* The byte offset of the ALT_I2C_INTR_STAT register from the beginning of the component. */
1654#define ALT_I2C_INTR_STAT_OFST 0x2c
1655/* The address of the ALT_I2C_INTR_STAT register. */
1656#define ALT_I2C_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_STAT_OFST))
1657
1658/*
1659 * Register : Interrupt Mask Register - ic_intr_mask
1660 *
1661 * These bits mask their corresponding interrupt status bits.
1662 *
1663 * Register Layout
1664 *
1665 * Bits | Access | Reset | Description
1666 * :--------|:-------|:------|:----------------
1667 * [0] | RW | 0x1 | Mask RX Under
1668 * [1] | RW | 0x1 | RX Buffer Over
1669 * [2] | RW | 0x1 | RX Buffer Full
1670 * [3] | RW | 0x1 | TX Buffer Over
1671 * [4] | RW | 0x1 | TX Buffer Empty
1672 * [5] | RW | 0x1 | Read Request
1673 * [6] | RW | 0x1 | TX Abort
1674 * [7] | RW | 0x1 | RX Done
1675 * [8] | RW | 0x0 | Activity Bit
1676 * [9] | RW | 0x0 | Stop Detect
1677 * [10] | RW | 0x0 | Start Detect
1678 * [11] | RW | 0x1 | General Call
1679 * [31:12] | ??? | 0x0 | *UNDEFINED*
1680 *
1681 */
1682/*
1683 * Field : Mask RX Under - m_rx_under
1684 *
1685 * Set if the processor attempts to read the receive buffer when it is empty by
1686 * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0,
1687 * this bit keeps its level until the master or slave state machines go into idle,
1688 * and then this interrupt is cleared.
1689 *
1690 * Field Access Macros:
1691 *
1692 */
1693/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */
1694#define ALT_I2C_INTR_MSK_M_RX_UNDER_LSB 0
1695/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */
1696#define ALT_I2C_INTR_MSK_M_RX_UNDER_MSB 0
1697/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */
1698#define ALT_I2C_INTR_MSK_M_RX_UNDER_WIDTH 1
1699/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */
1700#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET_MSK 0x00000001
1701/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */
1702#define ALT_I2C_INTR_MSK_M_RX_UNDER_CLR_MSK 0xfffffffe
1703/* The reset value of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */
1704#define ALT_I2C_INTR_MSK_M_RX_UNDER_RESET 0x1
1705/* Extracts the ALT_I2C_INTR_MSK_M_RX_UNDER field value from a register. */
1706#define ALT_I2C_INTR_MSK_M_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
1707/* Produces a ALT_I2C_INTR_MSK_M_RX_UNDER register field value suitable for setting the register. */
1708#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
1709
1710/*
1711 * Field : RX Buffer Over - m_rx_over
1712 *
1713 * Set if the receive buffer is completely filled to 64 and an additional byte is
1714 * received from an external I2C device. The I2C acknowledges this, but any data
1715 * bytes received after the FIFO is full are lost. If the module is disabled
1716 * ic_enable[0]=0, this bit keeps its level until the master or slave state
1717 * machines go into idle, then this interrupt is cleared.
1718 *
1719 * Field Access Macros:
1720 *
1721 */
1722/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */
1723#define ALT_I2C_INTR_MSK_M_RX_OVER_LSB 1
1724/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */
1725#define ALT_I2C_INTR_MSK_M_RX_OVER_MSB 1
1726/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */
1727#define ALT_I2C_INTR_MSK_M_RX_OVER_WIDTH 1
1728/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */
1729#define ALT_I2C_INTR_MSK_M_RX_OVER_SET_MSK 0x00000002
1730/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */
1731#define ALT_I2C_INTR_MSK_M_RX_OVER_CLR_MSK 0xfffffffd
1732/* The reset value of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */
1733#define ALT_I2C_INTR_MSK_M_RX_OVER_RESET 0x1
1734/* Extracts the ALT_I2C_INTR_MSK_M_RX_OVER field value from a register. */
1735#define ALT_I2C_INTR_MSK_M_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
1736/* Produces a ALT_I2C_INTR_MSK_M_RX_OVER register field value suitable for setting the register. */
1737#define ALT_I2C_INTR_MSK_M_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
1738
1739/*
1740 * Field : RX Buffer Full - m_rx_full
1741 *
1742 * Set when the receive buffer reaches or goes above the RX_TL threshold in the
1743 * ic_rx_tl register. It is automatically cleared by hardware when buffer level
1744 * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO
1745 * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is
1746 * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the
1747 * activity that continues.
1748 *
1749 * Field Access Macros:
1750 *
1751 */
1752/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */
1753#define ALT_I2C_INTR_MSK_M_RX_FULL_LSB 2
1754/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */
1755#define ALT_I2C_INTR_MSK_M_RX_FULL_MSB 2
1756/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */
1757#define ALT_I2C_INTR_MSK_M_RX_FULL_WIDTH 1
1758/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */
1759#define ALT_I2C_INTR_MSK_M_RX_FULL_SET_MSK 0x00000004
1760/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */
1761#define ALT_I2C_INTR_MSK_M_RX_FULL_CLR_MSK 0xfffffffb
1762/* The reset value of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */
1763#define ALT_I2C_INTR_MSK_M_RX_FULL_RESET 0x1
1764/* Extracts the ALT_I2C_INTR_MSK_M_RX_FULL field value from a register. */
1765#define ALT_I2C_INTR_MSK_M_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
1766/* Produces a ALT_I2C_INTR_MSK_M_RX_FULL register field value suitable for setting the register. */
1767#define ALT_I2C_INTR_MSK_M_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
1768
1769/*
1770 * Field : TX Buffer Over - m_tx_over
1771 *
1772 * Set during transmit if the transmit buffer is filled to 64 and the processor
1773 * attempts to issue another I2C command by writing to the ic_data_cmd register.
1774 * When the module is disabled, this bit keeps its level until the master or slave
1775 * state machines go into idle, then this interrupt is cleared.
1776 *
1777 * Field Access Macros:
1778 *
1779 */
1780/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */
1781#define ALT_I2C_INTR_MSK_M_TX_OVER_LSB 3
1782/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */
1783#define ALT_I2C_INTR_MSK_M_TX_OVER_MSB 3
1784/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */
1785#define ALT_I2C_INTR_MSK_M_TX_OVER_WIDTH 1
1786/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */
1787#define ALT_I2C_INTR_MSK_M_TX_OVER_SET_MSK 0x00000008
1788/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */
1789#define ALT_I2C_INTR_MSK_M_TX_OVER_CLR_MSK 0xfffffff7
1790/* The reset value of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */
1791#define ALT_I2C_INTR_MSK_M_TX_OVER_RESET 0x1
1792/* Extracts the ALT_I2C_INTR_MSK_M_TX_OVER field value from a register. */
1793#define ALT_I2C_INTR_MSK_M_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
1794/* Produces a ALT_I2C_INTR_MSK_M_TX_OVER register field value suitable for setting the register. */
1795#define ALT_I2C_INTR_MSK_M_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
1796
1797/*
1798 * Field : TX Buffer Empty - m_tx_empty
1799 *
1800 * This bit is set to 1 when the transmit buffer is at or below the threshold value
1801 * set in the ic_tx_tl register. It is automatically cleared by hardware when the
1802 * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX
1803 * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data
1804 * within it, so this bit is set to 1, provided there is activity in the master or
1805 * slave state machines. When there is no longer activity, then this bit is set to
1806 * 0.
1807 *
1808 * Field Access Macros:
1809 *
1810 */
1811/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */
1812#define ALT_I2C_INTR_MSK_M_TX_EMPTY_LSB 4
1813/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */
1814#define ALT_I2C_INTR_MSK_M_TX_EMPTY_MSB 4
1815/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */
1816#define ALT_I2C_INTR_MSK_M_TX_EMPTY_WIDTH 1
1817/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */
1818#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET_MSK 0x00000010
1819/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */
1820#define ALT_I2C_INTR_MSK_M_TX_EMPTY_CLR_MSK 0xffffffef
1821/* The reset value of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */
1822#define ALT_I2C_INTR_MSK_M_TX_EMPTY_RESET 0x1
1823/* Extracts the ALT_I2C_INTR_MSK_M_TX_EMPTY field value from a register. */
1824#define ALT_I2C_INTR_MSK_M_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
1825/* Produces a ALT_I2C_INTR_MSK_M_TX_EMPTY register field value suitable for setting the register. */
1826#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
1827
1828/*
1829 * Field : Read Request - m_rd_req
1830 *
1831 * This bit is set to 1 when I2C is acting as a slave and another I2C master is
1832 * attempting to read data from I2C. The I2C holds the I2C bus in a wait state
1833 * (SCL=0) until this interrupt is serviced, which means that the slave has been
1834 * addressed by a remote master that is asking for data to be transferred. The
1835 * processor must respond to this interrupt and then write the requested data to
1836 * the ic_data_cmd register. This bit is set to 0 just after the processor reads
1837 * the ic_clr_rd_req register.
1838 *
1839 * Field Access Macros:
1840 *
1841 */
1842/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */
1843#define ALT_I2C_INTR_MSK_M_RD_REQ_LSB 5
1844/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */
1845#define ALT_I2C_INTR_MSK_M_RD_REQ_MSB 5
1846/* The width in bits of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */
1847#define ALT_I2C_INTR_MSK_M_RD_REQ_WIDTH 1
1848/* The mask used to set the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */
1849#define ALT_I2C_INTR_MSK_M_RD_REQ_SET_MSK 0x00000020
1850/* The mask used to clear the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */
1851#define ALT_I2C_INTR_MSK_M_RD_REQ_CLR_MSK 0xffffffdf
1852/* The reset value of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */
1853#define ALT_I2C_INTR_MSK_M_RD_REQ_RESET 0x1
1854/* Extracts the ALT_I2C_INTR_MSK_M_RD_REQ field value from a register. */
1855#define ALT_I2C_INTR_MSK_M_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
1856/* Produces a ALT_I2C_INTR_MSK_M_RD_REQ register field value suitable for setting the register. */
1857#define ALT_I2C_INTR_MSK_M_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
1858
1859/*
1860 * Field : TX Abort - m_tx_abrt
1861 *
1862 * This bit indicates if I2C, as an I2C transmitter, is unable to complete the
1863 * intended actions on the contents of the transmit FIFO. This situation can occur
1864 * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'.
1865 * When this bit is set to 1, the ic_tx_abrt_source register indicates the reason
1866 * why the transmit abort takes places.
1867 *
1868 * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The
1869 * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read.
1870 * Once this read is performed, the TX FIFO is then ready to accept more data bytes
1871 * from the APB interface.
1872 *
1873 * Field Access Macros:
1874 *
1875 */
1876/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */
1877#define ALT_I2C_INTR_MSK_M_TX_ABRT_LSB 6
1878/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */
1879#define ALT_I2C_INTR_MSK_M_TX_ABRT_MSB 6
1880/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */
1881#define ALT_I2C_INTR_MSK_M_TX_ABRT_WIDTH 1
1882/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */
1883#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET_MSK 0x00000040
1884/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */
1885#define ALT_I2C_INTR_MSK_M_TX_ABRT_CLR_MSK 0xffffffbf
1886/* The reset value of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */
1887#define ALT_I2C_INTR_MSK_M_TX_ABRT_RESET 0x1
1888/* Extracts the ALT_I2C_INTR_MSK_M_TX_ABRT field value from a register. */
1889#define ALT_I2C_INTR_MSK_M_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
1890/* Produces a ALT_I2C_INTR_MSK_M_TX_ABRT register field value suitable for setting the register. */
1891#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
1892
1893/*
1894 * Field : RX Done - m_rx_done
1895 *
1896 * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the
1897 * master does not acknowledge a transmitted byte. This occurs on the last byte of
1898 * the transmission, indicating that the transmission is done.
1899 *
1900 * Field Access Macros:
1901 *
1902 */
1903/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */
1904#define ALT_I2C_INTR_MSK_M_RX_DONE_LSB 7
1905/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */
1906#define ALT_I2C_INTR_MSK_M_RX_DONE_MSB 7
1907/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */
1908#define ALT_I2C_INTR_MSK_M_RX_DONE_WIDTH 1
1909/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */
1910#define ALT_I2C_INTR_MSK_M_RX_DONE_SET_MSK 0x00000080
1911/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */
1912#define ALT_I2C_INTR_MSK_M_RX_DONE_CLR_MSK 0xffffff7f
1913/* The reset value of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */
1914#define ALT_I2C_INTR_MSK_M_RX_DONE_RESET 0x1
1915/* Extracts the ALT_I2C_INTR_MSK_M_RX_DONE field value from a register. */
1916#define ALT_I2C_INTR_MSK_M_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
1917/* Produces a ALT_I2C_INTR_MSK_M_RX_DONE register field value suitable for setting the register. */
1918#define ALT_I2C_INTR_MSK_M_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
1919
1920/*
1921 * Field : Activity Bit - m_activity
1922 *
1923 * This bit captures i2c activity and stays set until it is cleared. There are four
1924 * ways to clear it:
1925 *
1926 * * Disabling the i2c
1927 *
1928 * * Reading the ic_clr_activity register
1929 *
1930 * * Reading the ic_clr_intr register
1931 *
1932 * * System reset
1933 *
1934 * Once this bit is set, it stays set unless one of the four methods is used to
1935 * clear it. Even if the I2C module is idle, this bit remains set until cleared,
1936 * indicating that there was activity on the bus.
1937 *
1938 * Field Access Macros:
1939 *
1940 */
1941/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */
1942#define ALT_I2C_INTR_MSK_M_ACTIVITY_LSB 8
1943/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */
1944#define ALT_I2C_INTR_MSK_M_ACTIVITY_MSB 8
1945/* The width in bits of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */
1946#define ALT_I2C_INTR_MSK_M_ACTIVITY_WIDTH 1
1947/* The mask used to set the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */
1948#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET_MSK 0x00000100
1949/* The mask used to clear the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */
1950#define ALT_I2C_INTR_MSK_M_ACTIVITY_CLR_MSK 0xfffffeff
1951/* The reset value of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */
1952#define ALT_I2C_INTR_MSK_M_ACTIVITY_RESET 0x0
1953/* Extracts the ALT_I2C_INTR_MSK_M_ACTIVITY field value from a register. */
1954#define ALT_I2C_INTR_MSK_M_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
1955/* Produces a ALT_I2C_INTR_MSK_M_ACTIVITY register field value suitable for setting the register. */
1956#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
1957
1958/*
1959 * Field : Stop Detect - m_stop_det
1960 *
1961 * Indicates whether a STOP condition has occurred on the I2C interface regardless
1962 * of whether i2c is operating in slave or master mode.
1963 *
1964 * Field Access Macros:
1965 *
1966 */
1967/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */
1968#define ALT_I2C_INTR_MSK_M_STOP_DET_LSB 9
1969/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */
1970#define ALT_I2C_INTR_MSK_M_STOP_DET_MSB 9
1971/* The width in bits of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */
1972#define ALT_I2C_INTR_MSK_M_STOP_DET_WIDTH 1
1973/* The mask used to set the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */
1974#define ALT_I2C_INTR_MSK_M_STOP_DET_SET_MSK 0x00000200
1975/* The mask used to clear the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */
1976#define ALT_I2C_INTR_MSK_M_STOP_DET_CLR_MSK 0xfffffdff
1977/* The reset value of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */
1978#define ALT_I2C_INTR_MSK_M_STOP_DET_RESET 0x0
1979/* Extracts the ALT_I2C_INTR_MSK_M_STOP_DET field value from a register. */
1980#define ALT_I2C_INTR_MSK_M_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
1981/* Produces a ALT_I2C_INTR_MSK_M_STOP_DET register field value suitable for setting the register. */
1982#define ALT_I2C_INTR_MSK_M_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
1983
1984/*
1985 * Field : Start Detect - m_start_det
1986 *
1987 * Indicates whether a START or RESTART condition has occurred on the I2C interface
1988 * regardless of whether I2C is operating in slave or master mode.
1989 *
1990 * Field Access Macros:
1991 *
1992 */
1993/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */
1994#define ALT_I2C_INTR_MSK_M_START_DET_LSB 10
1995/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */
1996#define ALT_I2C_INTR_MSK_M_START_DET_MSB 10
1997/* The width in bits of the ALT_I2C_INTR_MSK_M_START_DET register field. */
1998#define ALT_I2C_INTR_MSK_M_START_DET_WIDTH 1
1999/* The mask used to set the ALT_I2C_INTR_MSK_M_START_DET register field value. */
2000#define ALT_I2C_INTR_MSK_M_START_DET_SET_MSK 0x00000400
2001/* The mask used to clear the ALT_I2C_INTR_MSK_M_START_DET register field value. */
2002#define ALT_I2C_INTR_MSK_M_START_DET_CLR_MSK 0xfffffbff
2003/* The reset value of the ALT_I2C_INTR_MSK_M_START_DET register field. */
2004#define ALT_I2C_INTR_MSK_M_START_DET_RESET 0x0
2005/* Extracts the ALT_I2C_INTR_MSK_M_START_DET field value from a register. */
2006#define ALT_I2C_INTR_MSK_M_START_DET_GET(value) (((value) & 0x00000400) >> 10)
2007/* Produces a ALT_I2C_INTR_MSK_M_START_DET register field value suitable for setting the register. */
2008#define ALT_I2C_INTR_MSK_M_START_DET_SET(value) (((value) << 10) & 0x00000400)
2009
2010/*
2011 * Field : General Call - m_gen_call
2012 *
2013 * Set only when a General Call address is received and it is acknowledged. It
2014 * stays set until it is cleared either by disabling I2C or when the CPU reads bit
2015 * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx
2016 * buffer.
2017 *
2018 * Field Access Macros:
2019 *
2020 */
2021/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */
2022#define ALT_I2C_INTR_MSK_M_GEN_CALL_LSB 11
2023/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */
2024#define ALT_I2C_INTR_MSK_M_GEN_CALL_MSB 11
2025/* The width in bits of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */
2026#define ALT_I2C_INTR_MSK_M_GEN_CALL_WIDTH 1
2027/* The mask used to set the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */
2028#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET_MSK 0x00000800
2029/* The mask used to clear the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */
2030#define ALT_I2C_INTR_MSK_M_GEN_CALL_CLR_MSK 0xfffff7ff
2031/* The reset value of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */
2032#define ALT_I2C_INTR_MSK_M_GEN_CALL_RESET 0x1
2033/* Extracts the ALT_I2C_INTR_MSK_M_GEN_CALL field value from a register. */
2034#define ALT_I2C_INTR_MSK_M_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
2035/* Produces a ALT_I2C_INTR_MSK_M_GEN_CALL register field value suitable for setting the register. */
2036#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
2037
2038#ifndef __ASSEMBLY__
2039/*
2040 * WARNING: The C register and register group struct declarations are provided for
2041 * convenience and illustrative purposes. They should, however, be used with
2042 * caution as the C language standard provides no guarantees about the alignment or
2043 * atomicity of device memory accesses. The recommended practice for writing
2044 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2045 * alt_write_word() functions.
2046 *
2047 * The struct declaration for register ALT_I2C_INTR_MSK.
2048 */
2049 struct ALT_I2C_INTR_MSK_s
2050{
2051 uint32_t m_rx_under : 1; /* Mask RX Under */
2052 uint32_t m_rx_over : 1; /* RX Buffer Over */
2053 uint32_t m_rx_full : 1; /* RX Buffer Full */
2054 uint32_t m_tx_over : 1; /* TX Buffer Over */
2055 uint32_t m_tx_empty : 1; /* TX Buffer Empty */
2056 uint32_t m_rd_req : 1; /* Read Request */
2057 uint32_t m_tx_abrt : 1; /* TX Abort */
2058 uint32_t m_rx_done : 1; /* RX Done */
2059 uint32_t m_activity : 1; /* Activity Bit */
2060 uint32_t m_stop_det : 1; /* Stop Detect */
2061 uint32_t m_start_det : 1; /* Start Detect */
2062 uint32_t m_gen_call : 1; /* General Call */
2063 uint32_t : 20; /* *UNDEFINED* */
2064};
2065
2066/* The typedef declaration for register ALT_I2C_INTR_MSK. */
2067typedef volatile struct ALT_I2C_INTR_MSK_s ALT_I2C_INTR_MSK_t;
2068#endif /* __ASSEMBLY__ */
2069
2070/* The byte offset of the ALT_I2C_INTR_MSK register from the beginning of the component. */
2071#define ALT_I2C_INTR_MSK_OFST 0x30
2072/* The address of the ALT_I2C_INTR_MSK register. */
2073#define ALT_I2C_INTR_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_MSK_OFST))
2074
2075/*
2076 * Register : Raw Interrupt Status Register - ic_raw_intr_stat
2077 *
2078 * Unlike the ic_intr_stat register, these bits are not masked so they always show
2079 * the true status of the I2C.
2080 *
2081 * Register Layout
2082 *
2083 * Bits | Access | Reset | Description
2084 * :--------|:-------|:------|:---------------------------
2085 * [0] | R | 0x0 | I2C Raw Interrupt RX Under
2086 * [1] | R | 0x0 | Raw Interrupt RX Over
2087 * [2] | R | 0x0 | Raw Interrupt RX Full
2088 * [3] | R | 0x0 | Raw Interrupt TX Over
2089 * [4] | R | 0x0 | Raw Interrupt TX Empty
2090 * [5] | R | 0x0 | Raw Interrupt Read Request
2091 * [6] | R | 0x0 | Raw Interrupt TX Abort
2092 * [7] | R | 0x0 | Raw Interrupt RX Done
2093 * [8] | R | 0x0 | Raw Interrupt Activity
2094 * [9] | R | 0x0 | Raw Interrupt Stop Detect
2095 * [10] | R | 0x0 | Raw Interrupt Start Detect
2096 * [11] | R | 0x0 | Raw Interrupt General Call
2097 * [31:12] | ??? | 0x0 | *UNDEFINED*
2098 *
2099 */
2100/*
2101 * Field : I2C Raw Interrupt RX Under - rx_under
2102 *
2103 * Set if the processor attempts to read the receive buffer when it is empty by
2104 * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0,
2105 * this bit keeps its level until the master or slave state machines go into idle,
2106 * then this interrupt is cleared.
2107 *
2108 * Field Access Macros:
2109 *
2110 */
2111/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */
2112#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_LSB 0
2113/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */
2114#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_MSB 0
2115/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */
2116#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_WIDTH 1
2117/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */
2118#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET_MSK 0x00000001
2119/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */
2120#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_CLR_MSK 0xfffffffe
2121/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */
2122#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_RESET 0x0
2123/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_UNDER field value from a register. */
2124#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
2125/* Produces a ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value suitable for setting the register. */
2126#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
2127
2128/*
2129 * Field : Raw Interrupt RX Over - rx_over
2130 *
2131 * Set if the receive buffer is completely filled to 64 and an additional byte is
2132 * received from an external I2C device. The I2C acknowledges this, but any data
2133 * bytes received after the FIFO is full are lost. If the module is disabled
2134 * ic_enable[0]=0), this bit keeps its level until the master or slave state
2135 * machines go into then, this interrupt is cleared.
2136 *
2137 * Field Access Macros:
2138 *
2139 */
2140/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */
2141#define ALT_I2C_RAW_INTR_STAT_RX_OVER_LSB 1
2142/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */
2143#define ALT_I2C_RAW_INTR_STAT_RX_OVER_MSB 1
2144/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */
2145#define ALT_I2C_RAW_INTR_STAT_RX_OVER_WIDTH 1
2146/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */
2147#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET_MSK 0x00000002
2148/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */
2149#define ALT_I2C_RAW_INTR_STAT_RX_OVER_CLR_MSK 0xfffffffd
2150/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */
2151#define ALT_I2C_RAW_INTR_STAT_RX_OVER_RESET 0x0
2152/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_OVER field value from a register. */
2153#define ALT_I2C_RAW_INTR_STAT_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
2154/* Produces a ALT_I2C_RAW_INTR_STAT_RX_OVER register field value suitable for setting the register. */
2155#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
2156
2157/*
2158 * Field : Raw Interrupt RX Full - rx_full
2159 *
2160 * Set when the receive buffer reaches or goes above the RX_TL threshold in the
2161 * ic_rx_tl register. It is automatically cleared by hardware when buffer level
2162 * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO
2163 * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is
2164 * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the
2165 * activity that continues.
2166 *
2167 * Field Access Macros:
2168 *
2169 */
2170/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */
2171#define ALT_I2C_RAW_INTR_STAT_RX_FULL_LSB 2
2172/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */
2173#define ALT_I2C_RAW_INTR_STAT_RX_FULL_MSB 2
2174/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */
2175#define ALT_I2C_RAW_INTR_STAT_RX_FULL_WIDTH 1
2176/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */
2177#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET_MSK 0x00000004
2178/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */
2179#define ALT_I2C_RAW_INTR_STAT_RX_FULL_CLR_MSK 0xfffffffb
2180/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */
2181#define ALT_I2C_RAW_INTR_STAT_RX_FULL_RESET 0x0
2182/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_FULL field value from a register. */
2183#define ALT_I2C_RAW_INTR_STAT_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
2184/* Produces a ALT_I2C_RAW_INTR_STAT_RX_FULL register field value suitable for setting the register. */
2185#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
2186
2187/*
2188 * Field : Raw Interrupt TX Over - tx_over
2189 *
2190 * Set during transmit if the transmit buffer is filled to 64 and the processor
2191 * attempts to issue another I2C command by writing to the ic_data_cmd register.
2192 * When the module is disabled, this bit keeps its level until the master or slave
2193 * state machines go into idle, then this interrupt is cleared.
2194 *
2195 * Field Access Macros:
2196 *
2197 */
2198/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */
2199#define ALT_I2C_RAW_INTR_STAT_TX_OVER_LSB 3
2200/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */
2201#define ALT_I2C_RAW_INTR_STAT_TX_OVER_MSB 3
2202/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */
2203#define ALT_I2C_RAW_INTR_STAT_TX_OVER_WIDTH 1
2204/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */
2205#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET_MSK 0x00000008
2206/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */
2207#define ALT_I2C_RAW_INTR_STAT_TX_OVER_CLR_MSK 0xfffffff7
2208/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */
2209#define ALT_I2C_RAW_INTR_STAT_TX_OVER_RESET 0x0
2210/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_OVER field value from a register. */
2211#define ALT_I2C_RAW_INTR_STAT_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
2212/* Produces a ALT_I2C_RAW_INTR_STAT_TX_OVER register field value suitable for setting the register. */
2213#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
2214
2215/*
2216 * Field : Raw Interrupt TX Empty - tx_empty
2217 *
2218 * This bit is set to 1 when the transmit buffer is at or below the threshold value
2219 * set in the ic_tx_tl register. It is automatically cleared by hardware when the
2220 * buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX
2221 * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data
2222 * within it, so this bit is set to 1, provided there is activity in the master or
2223 * slave state machines. When there is no longer activity, then this bit is set to
2224 * 0.
2225 *
2226 * Field Access Macros:
2227 *
2228 */
2229/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */
2230#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_LSB 4
2231/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */
2232#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_MSB 4
2233/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */
2234#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_WIDTH 1
2235/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */
2236#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET_MSK 0x00000010
2237/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */
2238#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_CLR_MSK 0xffffffef
2239/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */
2240#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_RESET 0x0
2241/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_EMPTY field value from a register. */
2242#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
2243/* Produces a ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value suitable for setting the register. */
2244#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
2245
2246/*
2247 * Field : Raw Interrupt Read Request - rd_req
2248 *
2249 * This bit is set to 1 when I2C is acting as a slave and another I2C master is
2250 * attempting to read data from I2C. The i2c holds the I2C bus in a wait state
2251 * (SCL=0) until this interrupt is serviced, which means that the slave has been
2252 * addressed by a remote master that is asking for data to be transferred. The
2253 * processor must respond to this interrupt and then write the requested data to
2254 * the ic_data_cmd register. This bit is set to 0 just after the processor reads
2255 * the ic_clr_rd_req register.
2256 *
2257 * Field Access Macros:
2258 *
2259 */
2260/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */
2261#define ALT_I2C_RAW_INTR_STAT_RD_REQ_LSB 5
2262/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */
2263#define ALT_I2C_RAW_INTR_STAT_RD_REQ_MSB 5
2264/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */
2265#define ALT_I2C_RAW_INTR_STAT_RD_REQ_WIDTH 1
2266/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */
2267#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET_MSK 0x00000020
2268/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */
2269#define ALT_I2C_RAW_INTR_STAT_RD_REQ_CLR_MSK 0xffffffdf
2270/* The reset value of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */
2271#define ALT_I2C_RAW_INTR_STAT_RD_REQ_RESET 0x0
2272/* Extracts the ALT_I2C_RAW_INTR_STAT_RD_REQ field value from a register. */
2273#define ALT_I2C_RAW_INTR_STAT_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
2274/* Produces a ALT_I2C_RAW_INTR_STAT_RD_REQ register field value suitable for setting the register. */
2275#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
2276
2277/*
2278 * Field : Raw Interrupt TX Abort - tx_abrt
2279 *
2280 * This bit indicates if I2C, as an I2C transmitter, is unable to complete the
2281 * intended actions on the contents of the transmit FIFO. This situation can occur
2282 * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'.
2283 * When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason
2284 * why the transmit abort takes places.
2285 *
2286 * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The
2287 * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read.
2288 * Once this read is performed, the TX FIFO is then ready to accept more data bytes
2289 * from the APB interface.
2290 *
2291 * Field Access Macros:
2292 *
2293 */
2294/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */
2295#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_LSB 6
2296/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */
2297#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_MSB 6
2298/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */
2299#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_WIDTH 1
2300/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */
2301#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET_MSK 0x00000040
2302/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */
2303#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_CLR_MSK 0xffffffbf
2304/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */
2305#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_RESET 0x0
2306/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_ABRT field value from a register. */
2307#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
2308/* Produces a ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value suitable for setting the register. */
2309#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
2310
2311/*
2312 * Field : Raw Interrupt RX Done - rx_done
2313 *
2314 * When the I2C is acting as a slave-transmitter, this bit is set to 1 if the
2315 * master does not acknowledge a transmitted byte. This occurs on the last byte of
2316 * the transmission, indicating that the transmission is done.
2317 *
2318 * Field Access Macros:
2319 *
2320 */
2321/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */
2322#define ALT_I2C_RAW_INTR_STAT_RX_DONE_LSB 7
2323/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */
2324#define ALT_I2C_RAW_INTR_STAT_RX_DONE_MSB 7
2325/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */
2326#define ALT_I2C_RAW_INTR_STAT_RX_DONE_WIDTH 1
2327/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */
2328#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET_MSK 0x00000080
2329/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */
2330#define ALT_I2C_RAW_INTR_STAT_RX_DONE_CLR_MSK 0xffffff7f
2331/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */
2332#define ALT_I2C_RAW_INTR_STAT_RX_DONE_RESET 0x0
2333/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_DONE field value from a register. */
2334#define ALT_I2C_RAW_INTR_STAT_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
2335/* Produces a ALT_I2C_RAW_INTR_STAT_RX_DONE register field value suitable for setting the register. */
2336#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
2337
2338/*
2339 * Field : Raw Interrupt Activity - activity
2340 *
2341 * This bit captures i2c activity and stays set until it is cleared. There are four
2342 * ways to clear it:
2343 *
2344 * * Disabling the I2C
2345 *
2346 * * Reading the ic_clr_activity register
2347 *
2348 * * Reading the ic_clr_intr register
2349 *
2350 * * System reset
2351 *
2352 * Once this bit is set, it stays set unless one of the four methods is used to
2353 * clear it. Even if the i2c module is idle, this bit remains set until cleared,
2354 * indicating that there was activity on the bus.
2355 *
2356 * Field Access Macros:
2357 *
2358 */
2359/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */
2360#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_LSB 8
2361/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */
2362#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_MSB 8
2363/* The width in bits of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */
2364#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_WIDTH 1
2365/* The mask used to set the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */
2366#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET_MSK 0x00000100
2367/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */
2368#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_CLR_MSK 0xfffffeff
2369/* The reset value of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */
2370#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_RESET 0x0
2371/* Extracts the ALT_I2C_RAW_INTR_STAT_ACTIVITY field value from a register. */
2372#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
2373/* Produces a ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value suitable for setting the register. */
2374#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
2375
2376/*
2377 * Field : Raw Interrupt Stop Detect - stop_det
2378 *
2379 * Indicates whether a STOP condition has occurred on the I2C interface regardless
2380 * of whether I2C is operating in slave or master mode.
2381 *
2382 * Field Access Macros:
2383 *
2384 */
2385/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */
2386#define ALT_I2C_RAW_INTR_STAT_STOP_DET_LSB 9
2387/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */
2388#define ALT_I2C_RAW_INTR_STAT_STOP_DET_MSB 9
2389/* The width in bits of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */
2390#define ALT_I2C_RAW_INTR_STAT_STOP_DET_WIDTH 1
2391/* The mask used to set the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */
2392#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET_MSK 0x00000200
2393/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */
2394#define ALT_I2C_RAW_INTR_STAT_STOP_DET_CLR_MSK 0xfffffdff
2395/* The reset value of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */
2396#define ALT_I2C_RAW_INTR_STAT_STOP_DET_RESET 0x0
2397/* Extracts the ALT_I2C_RAW_INTR_STAT_STOP_DET field value from a register. */
2398#define ALT_I2C_RAW_INTR_STAT_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
2399/* Produces a ALT_I2C_RAW_INTR_STAT_STOP_DET register field value suitable for setting the register. */
2400#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
2401
2402/*
2403 * Field : Raw Interrupt Start Detect - start_det
2404 *
2405 * Indicates whether a START or RESTART condition has occurred on the I2C interface
2406 * regardless of whether I2C is operating in slave or master mode.
2407 *
2408 * Field Access Macros:
2409 *
2410 */
2411/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */
2412#define ALT_I2C_RAW_INTR_STAT_START_DET_LSB 10
2413/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */
2414#define ALT_I2C_RAW_INTR_STAT_START_DET_MSB 10
2415/* The width in bits of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */
2416#define ALT_I2C_RAW_INTR_STAT_START_DET_WIDTH 1
2417/* The mask used to set the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */
2418#define ALT_I2C_RAW_INTR_STAT_START_DET_SET_MSK 0x00000400
2419/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */
2420#define ALT_I2C_RAW_INTR_STAT_START_DET_CLR_MSK 0xfffffbff
2421/* The reset value of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */
2422#define ALT_I2C_RAW_INTR_STAT_START_DET_RESET 0x0
2423/* Extracts the ALT_I2C_RAW_INTR_STAT_START_DET field value from a register. */
2424#define ALT_I2C_RAW_INTR_STAT_START_DET_GET(value) (((value) & 0x00000400) >> 10)
2425/* Produces a ALT_I2C_RAW_INTR_STAT_START_DET register field value suitable for setting the register. */
2426#define ALT_I2C_RAW_INTR_STAT_START_DET_SET(value) (((value) << 10) & 0x00000400)
2427
2428/*
2429 * Field : Raw Interrupt General Call - gen_call
2430 *
2431 * Set only when a General Call address is received and it is acknowledged. It
2432 * stays set until it is cleared either by disabling I2C or when the CPU reads bit
2433 * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx
2434 * buffer.
2435 *
2436 * Field Access Macros:
2437 *
2438 */
2439/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */
2440#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_LSB 11
2441/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */
2442#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_MSB 11
2443/* The width in bits of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */
2444#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_WIDTH 1
2445/* The mask used to set the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */
2446#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET_MSK 0x00000800
2447/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */
2448#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_CLR_MSK 0xfffff7ff
2449/* The reset value of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */
2450#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_RESET 0x0
2451/* Extracts the ALT_I2C_RAW_INTR_STAT_GEN_CALL field value from a register. */
2452#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
2453/* Produces a ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value suitable for setting the register. */
2454#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
2455
2456#ifndef __ASSEMBLY__
2457/*
2458 * WARNING: The C register and register group struct declarations are provided for
2459 * convenience and illustrative purposes. They should, however, be used with
2460 * caution as the C language standard provides no guarantees about the alignment or
2461 * atomicity of device memory accesses. The recommended practice for writing
2462 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2463 * alt_write_word() functions.
2464 *
2465 * The struct declaration for register ALT_I2C_RAW_INTR_STAT.
2466 */
2467 struct ALT_I2C_RAW_INTR_STAT_s
2468{
2469 const uint32_t rx_under : 1; /* I2C Raw Interrupt RX Under */
2470 const uint32_t rx_over : 1; /* Raw Interrupt RX Over */
2471 const uint32_t rx_full : 1; /* Raw Interrupt RX Full */
2472 const uint32_t tx_over : 1; /* Raw Interrupt TX Over */
2473 const uint32_t tx_empty : 1; /* Raw Interrupt TX Empty */
2474 const uint32_t rd_req : 1; /* Raw Interrupt Read Request */
2475 const uint32_t tx_abrt : 1; /* Raw Interrupt TX Abort */
2476 const uint32_t rx_done : 1; /* Raw Interrupt RX Done */
2477 const uint32_t activity : 1; /* Raw Interrupt Activity */
2478 const uint32_t stop_det : 1; /* Raw Interrupt Stop Detect */
2479 const uint32_t start_det : 1; /* Raw Interrupt Start Detect */
2480 const uint32_t gen_call : 1; /* Raw Interrupt General Call */
2481 uint32_t : 20; /* *UNDEFINED* */
2482};
2483
2484/* The typedef declaration for register ALT_I2C_RAW_INTR_STAT. */
2485typedef volatile struct ALT_I2C_RAW_INTR_STAT_s ALT_I2C_RAW_INTR_STAT_t;
2486#endif /* __ASSEMBLY__ */
2487
2488/* The byte offset of the ALT_I2C_RAW_INTR_STAT register from the beginning of the component. */
2489#define ALT_I2C_RAW_INTR_STAT_OFST 0x34
2490/* The address of the ALT_I2C_RAW_INTR_STAT register. */
2491#define ALT_I2C_RAW_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RAW_INTR_STAT_OFST))
2492
2493/*
2494 * Register : Receive FIFO Threshold Register - ic_rx_tl
2495 *
2496 * I2C Receive FIFO Threshold Register.
2497 *
2498 * Register Layout
2499 *
2500 * Bits | Access | Reset | Description
2501 * :-------|:-------|:------|:-----------------------------
2502 * [7:0] | RW | 0x0 | Receive FIFO Threshold Level
2503 * [31:8] | ??? | 0x0 | *UNDEFINED*
2504 *
2505 */
2506/*
2507 * Field : Receive FIFO Threshold Level - rx_tl
2508 *
2509 * Controls the level of entries (or above) that triggers the RX_FULL interrupt
2510 * (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the
2511 * additional restriction that hardware does not allow this value to be set to a
2512 * value larger than the depth of the buffer. If an attempt is made to do that, the
2513 * actual value set will be the maximum depth of the buffer. A value of 0 sets the
2514 * threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.
2515 *
2516 * Field Access Macros:
2517 *
2518 */
2519/* The Least Significant Bit (LSB) position of the ALT_I2C_RX_TL_RX_TL register field. */
2520#define ALT_I2C_RX_TL_RX_TL_LSB 0
2521/* The Most Significant Bit (MSB) position of the ALT_I2C_RX_TL_RX_TL register field. */
2522#define ALT_I2C_RX_TL_RX_TL_MSB 7
2523/* The width in bits of the ALT_I2C_RX_TL_RX_TL register field. */
2524#define ALT_I2C_RX_TL_RX_TL_WIDTH 8
2525/* The mask used to set the ALT_I2C_RX_TL_RX_TL register field value. */
2526#define ALT_I2C_RX_TL_RX_TL_SET_MSK 0x000000ff
2527/* The mask used to clear the ALT_I2C_RX_TL_RX_TL register field value. */
2528#define ALT_I2C_RX_TL_RX_TL_CLR_MSK 0xffffff00
2529/* The reset value of the ALT_I2C_RX_TL_RX_TL register field. */
2530#define ALT_I2C_RX_TL_RX_TL_RESET 0x0
2531/* Extracts the ALT_I2C_RX_TL_RX_TL field value from a register. */
2532#define ALT_I2C_RX_TL_RX_TL_GET(value) (((value) & 0x000000ff) >> 0)
2533/* Produces a ALT_I2C_RX_TL_RX_TL register field value suitable for setting the register. */
2534#define ALT_I2C_RX_TL_RX_TL_SET(value) (((value) << 0) & 0x000000ff)
2535
2536#ifndef __ASSEMBLY__
2537/*
2538 * WARNING: The C register and register group struct declarations are provided for
2539 * convenience and illustrative purposes. They should, however, be used with
2540 * caution as the C language standard provides no guarantees about the alignment or
2541 * atomicity of device memory accesses. The recommended practice for writing
2542 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2543 * alt_write_word() functions.
2544 *
2545 * The struct declaration for register ALT_I2C_RX_TL.
2546 */
2547 struct ALT_I2C_RX_TL_s
2548{
2549 uint32_t rx_tl : 8; /* Receive FIFO Threshold Level */
2550 uint32_t : 24; /* *UNDEFINED* */
2551};
2552
2553/* The typedef declaration for register ALT_I2C_RX_TL. */
2554typedef volatile struct ALT_I2C_RX_TL_s ALT_I2C_RX_TL_t;
2555#endif /* __ASSEMBLY__ */
2556
2557/* The byte offset of the ALT_I2C_RX_TL register from the beginning of the component. */
2558#define ALT_I2C_RX_TL_OFST 0x38
2559/* The address of the ALT_I2C_RX_TL register. */
2560#define ALT_I2C_RX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RX_TL_OFST))
2561
2562/*
2563 * Register : Transmit FIFO Threshold Level Register - ic_tx_tl
2564 *
2565 * Sets FIFO depth for Interrupt.
2566 *
2567 * Register Layout
2568 *
2569 * Bits | Access | Reset | Description
2570 * :-------|:-------|:------|:------------------------------
2571 * [7:0] | RW | 0x0 | Transmit FIFO Threshold Level
2572 * [31:8] | ??? | 0x0 | *UNDEFINED*
2573 *
2574 */
2575/*
2576 * Field : Transmit FIFO Threshold Level - tx_tl
2577 *
2578 * Controls the level of entries (or below) that trigger the TX_EMPTY interrupt
2579 * (bit 4 in ic_raw_intr_stat register). The valid range is 0-255, with the
2580 * additional restriction that it may not be set to value larger than the depth of
2581 * the buffer. If an attempt is made to do that, the actual value set will be the
2582 * maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and
2583 * a value of 255 sets the threshold for 255 entries.
2584 *
2585 * Field Access Macros:
2586 *
2587 */
2588/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_TL_TX_TL register field. */
2589#define ALT_I2C_TX_TL_TX_TL_LSB 0
2590/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_TL_TX_TL register field. */
2591#define ALT_I2C_TX_TL_TX_TL_MSB 7
2592/* The width in bits of the ALT_I2C_TX_TL_TX_TL register field. */
2593#define ALT_I2C_TX_TL_TX_TL_WIDTH 8
2594/* The mask used to set the ALT_I2C_TX_TL_TX_TL register field value. */
2595#define ALT_I2C_TX_TL_TX_TL_SET_MSK 0x000000ff
2596/* The mask used to clear the ALT_I2C_TX_TL_TX_TL register field value. */
2597#define ALT_I2C_TX_TL_TX_TL_CLR_MSK 0xffffff00
2598/* The reset value of the ALT_I2C_TX_TL_TX_TL register field. */
2599#define ALT_I2C_TX_TL_TX_TL_RESET 0x0
2600/* Extracts the ALT_I2C_TX_TL_TX_TL field value from a register. */
2601#define ALT_I2C_TX_TL_TX_TL_GET(value) (((value) & 0x000000ff) >> 0)
2602/* Produces a ALT_I2C_TX_TL_TX_TL register field value suitable for setting the register. */
2603#define ALT_I2C_TX_TL_TX_TL_SET(value) (((value) << 0) & 0x000000ff)
2604
2605#ifndef __ASSEMBLY__
2606/*
2607 * WARNING: The C register and register group struct declarations are provided for
2608 * convenience and illustrative purposes. They should, however, be used with
2609 * caution as the C language standard provides no guarantees about the alignment or
2610 * atomicity of device memory accesses. The recommended practice for writing
2611 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2612 * alt_write_word() functions.
2613 *
2614 * The struct declaration for register ALT_I2C_TX_TL.
2615 */
2616 struct ALT_I2C_TX_TL_s
2617{
2618 uint32_t tx_tl : 8; /* Transmit FIFO Threshold Level */
2619 uint32_t : 24; /* *UNDEFINED* */
2620};
2621
2622/* The typedef declaration for register ALT_I2C_TX_TL. */
2623typedef volatile struct ALT_I2C_TX_TL_s ALT_I2C_TX_TL_t;
2624#endif /* __ASSEMBLY__ */
2625
2626/* The byte offset of the ALT_I2C_TX_TL register from the beginning of the component. */
2627#define ALT_I2C_TX_TL_OFST 0x3c
2628/* The address of the ALT_I2C_TX_TL register. */
2629#define ALT_I2C_TX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_TL_OFST))
2630
2631/*
2632 * Register : Combined and Individual Interrupt Register - ic_clr_intr
2633 *
2634 * Controls Interrupts
2635 *
2636 * Register Layout
2637 *
2638 * Bits | Access | Reset | Description
2639 * :-------|:-------|:------|:---------------------------------------
2640 * [0] | R | 0x0 | Combined and Individual Interrupt Bits
2641 * [31:1] | ??? | 0x0 | *UNDEFINED*
2642 *
2643 */
2644/*
2645 * Field : Combined and Individual Interrupt Bits - clr_intr
2646 *
2647 * Read this register to clear the combined interrupt, all individual interrupts,
2648 * and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable
2649 * interrupts but software clearable interrupts. Refer to Bit 9 of the
2650 * ic_tx_abrt_source register for an exception to clearing ic_tx_abrt_source.
2651 *
2652 * Field Access Macros:
2653 *
2654 */
2655/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */
2656#define ALT_I2C_CLR_INTR_CLR_INTR_LSB 0
2657/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */
2658#define ALT_I2C_CLR_INTR_CLR_INTR_MSB 0
2659/* The width in bits of the ALT_I2C_CLR_INTR_CLR_INTR register field. */
2660#define ALT_I2C_CLR_INTR_CLR_INTR_WIDTH 1
2661/* The mask used to set the ALT_I2C_CLR_INTR_CLR_INTR register field value. */
2662#define ALT_I2C_CLR_INTR_CLR_INTR_SET_MSK 0x00000001
2663/* The mask used to clear the ALT_I2C_CLR_INTR_CLR_INTR register field value. */
2664#define ALT_I2C_CLR_INTR_CLR_INTR_CLR_MSK 0xfffffffe
2665/* The reset value of the ALT_I2C_CLR_INTR_CLR_INTR register field. */
2666#define ALT_I2C_CLR_INTR_CLR_INTR_RESET 0x0
2667/* Extracts the ALT_I2C_CLR_INTR_CLR_INTR field value from a register. */
2668#define ALT_I2C_CLR_INTR_CLR_INTR_GET(value) (((value) & 0x00000001) >> 0)
2669/* Produces a ALT_I2C_CLR_INTR_CLR_INTR register field value suitable for setting the register. */
2670#define ALT_I2C_CLR_INTR_CLR_INTR_SET(value) (((value) << 0) & 0x00000001)
2671
2672#ifndef __ASSEMBLY__
2673/*
2674 * WARNING: The C register and register group struct declarations are provided for
2675 * convenience and illustrative purposes. They should, however, be used with
2676 * caution as the C language standard provides no guarantees about the alignment or
2677 * atomicity of device memory accesses. The recommended practice for writing
2678 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2679 * alt_write_word() functions.
2680 *
2681 * The struct declaration for register ALT_I2C_CLR_INTR.
2682 */
2683 struct ALT_I2C_CLR_INTR_s
2684{
2685 const uint32_t clr_intr : 1; /* Combined and Individual Interrupt Bits */
2686 uint32_t : 31; /* *UNDEFINED* */
2687};
2688
2689/* The typedef declaration for register ALT_I2C_CLR_INTR. */
2690typedef volatile struct ALT_I2C_CLR_INTR_s ALT_I2C_CLR_INTR_t;
2691#endif /* __ASSEMBLY__ */
2692
2693/* The byte offset of the ALT_I2C_CLR_INTR register from the beginning of the component. */
2694#define ALT_I2C_CLR_INTR_OFST 0x40
2695/* The address of the ALT_I2C_CLR_INTR register. */
2696#define ALT_I2C_CLR_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_INTR_OFST))
2697
2698/*
2699 * Register : Rx Under Interrupt Register - ic_clr_rx_under
2700 *
2701 * Rx Under Interrupt Bits.
2702 *
2703 * Register Layout
2704 *
2705 * Bits | Access | Reset | Description
2706 * :-------|:-------|:------|:-----------------------------
2707 * [0] | R | 0x0 | Clear Rx Under Interrupt Bit
2708 * [31:1] | ??? | 0x0 | *UNDEFINED*
2709 *
2710 */
2711/*
2712 * Field : Clear Rx Under Interrupt Bit - clr_rx_under
2713 *
2714 * Read this register to clear the RX_UNDER interrupt bit 0 of the ic_raw_intr_stat
2715 * register.
2716 *
2717 * Field Access Macros:
2718 *
2719 */
2720/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */
2721#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0
2722/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */
2723#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0
2724/* The width in bits of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */
2725#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_WIDTH 1
2726/* The mask used to set the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */
2727#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET_MSK 0x00000001
2728/* The mask used to clear the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */
2729#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_CLR_MSK 0xfffffffe
2730/* The reset value of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */
2731#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0
2732/* Extracts the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER field value from a register. */
2733#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
2734/* Produces a ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value suitable for setting the register. */
2735#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
2736
2737#ifndef __ASSEMBLY__
2738/*
2739 * WARNING: The C register and register group struct declarations are provided for
2740 * convenience and illustrative purposes. They should, however, be used with
2741 * caution as the C language standard provides no guarantees about the alignment or
2742 * atomicity of device memory accesses. The recommended practice for writing
2743 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2744 * alt_write_word() functions.
2745 *
2746 * The struct declaration for register ALT_I2C_CLR_RX_UNDER.
2747 */
2748 struct ALT_I2C_CLR_RX_UNDER_s
2749{
2750 const uint32_t clr_rx_under : 1; /* Clear Rx Under Interrupt Bit */
2751 uint32_t : 31; /* *UNDEFINED* */
2752};
2753
2754/* The typedef declaration for register ALT_I2C_CLR_RX_UNDER. */
2755typedef volatile struct ALT_I2C_CLR_RX_UNDER_s ALT_I2C_CLR_RX_UNDER_t;
2756#endif /* __ASSEMBLY__ */
2757
2758/* The byte offset of the ALT_I2C_CLR_RX_UNDER register from the beginning of the component. */
2759#define ALT_I2C_CLR_RX_UNDER_OFST 0x44
2760/* The address of the ALT_I2C_CLR_RX_UNDER register. */
2761#define ALT_I2C_CLR_RX_UNDER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_UNDER_OFST))
2762
2763/*
2764 * Register : RX Over Interrupt Register - ic_clr_rx_over
2765 *
2766 * Clears Rx over Interrupt Bit
2767 *
2768 * Register Layout
2769 *
2770 * Bits | Access | Reset | Description
2771 * :-------|:-------|:------|:----------------------
2772 * [0] | R | 0x0 | RX Over Interrupt Bit
2773 * [31:1] | ??? | 0x0 | *UNDEFINED*
2774 *
2775 */
2776/*
2777 * Field : RX Over Interrupt Bit - clr_rx_over
2778 *
2779 * Read this register to clear the RX_OVER interrupt bit 1 of the ic_raw_intr_stat
2780 * register.
2781 *
2782 * Field Access Macros:
2783 *
2784 */
2785/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */
2786#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_LSB 0
2787/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */
2788#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_MSB 0
2789/* The width in bits of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */
2790#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_WIDTH 1
2791/* The mask used to set the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */
2792#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET_MSK 0x00000001
2793/* The mask used to clear the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */
2794#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_CLR_MSK 0xfffffffe
2795/* The reset value of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */
2796#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0
2797/* Extracts the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER field value from a register. */
2798#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_GET(value) (((value) & 0x00000001) >> 0)
2799/* Produces a ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value suitable for setting the register. */
2800#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET(value) (((value) << 0) & 0x00000001)
2801
2802#ifndef __ASSEMBLY__
2803/*
2804 * WARNING: The C register and register group struct declarations are provided for
2805 * convenience and illustrative purposes. They should, however, be used with
2806 * caution as the C language standard provides no guarantees about the alignment or
2807 * atomicity of device memory accesses. The recommended practice for writing
2808 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2809 * alt_write_word() functions.
2810 *
2811 * The struct declaration for register ALT_I2C_CLR_RX_OVER.
2812 */
2813 struct ALT_I2C_CLR_RX_OVER_s
2814{
2815 const uint32_t clr_rx_over : 1; /* RX Over Interrupt Bit */
2816 uint32_t : 31; /* *UNDEFINED* */
2817};
2818
2819/* The typedef declaration for register ALT_I2C_CLR_RX_OVER. */
2820typedef volatile struct ALT_I2C_CLR_RX_OVER_s ALT_I2C_CLR_RX_OVER_t;
2821#endif /* __ASSEMBLY__ */
2822
2823/* The byte offset of the ALT_I2C_CLR_RX_OVER register from the beginning of the component. */
2824#define ALT_I2C_CLR_RX_OVER_OFST 0x48
2825/* The address of the ALT_I2C_CLR_RX_OVER register. */
2826#define ALT_I2C_CLR_RX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_OVER_OFST))
2827
2828/*
2829 * Register : TX Over Interrupt Register - ic_clr_tx_over
2830 *
2831 * Clears Over Interrupts
2832 *
2833 * Register Layout
2834 *
2835 * Bits | Access | Reset | Description
2836 * :-------|:-------|:------|:----------------------
2837 * [0] | R | 0x0 | TX Over Interrupt Bit
2838 * [31:1] | ??? | 0x0 | *UNDEFINED*
2839 *
2840 */
2841/*
2842 * Field : TX Over Interrupt Bit - clr_tx_over
2843 *
2844 * Read this register to clear the TX_OVER interrupt (bit 3) of the
2845 * ic_raw_intr_stat register.
2846 *
2847 * Field Access Macros:
2848 *
2849 */
2850/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */
2851#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_LSB 0
2852/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */
2853#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_MSB 0
2854/* The width in bits of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */
2855#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_WIDTH 1
2856/* The mask used to set the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */
2857#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET_MSK 0x00000001
2858/* The mask used to clear the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */
2859#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_CLR_MSK 0xfffffffe
2860/* The reset value of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */
2861#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0
2862/* Extracts the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER field value from a register. */
2863#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_GET(value) (((value) & 0x00000001) >> 0)
2864/* Produces a ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value suitable for setting the register. */
2865#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET(value) (((value) << 0) & 0x00000001)
2866
2867#ifndef __ASSEMBLY__
2868/*
2869 * WARNING: The C register and register group struct declarations are provided for
2870 * convenience and illustrative purposes. They should, however, be used with
2871 * caution as the C language standard provides no guarantees about the alignment or
2872 * atomicity of device memory accesses. The recommended practice for writing
2873 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2874 * alt_write_word() functions.
2875 *
2876 * The struct declaration for register ALT_I2C_CLR_TX_OVER.
2877 */
2878 struct ALT_I2C_CLR_TX_OVER_s
2879{
2880 const uint32_t clr_tx_over : 1; /* TX Over Interrupt Bit */
2881 uint32_t : 31; /* *UNDEFINED* */
2882};
2883
2884/* The typedef declaration for register ALT_I2C_CLR_TX_OVER. */
2885typedef volatile struct ALT_I2C_CLR_TX_OVER_s ALT_I2C_CLR_TX_OVER_t;
2886#endif /* __ASSEMBLY__ */
2887
2888/* The byte offset of the ALT_I2C_CLR_TX_OVER register from the beginning of the component. */
2889#define ALT_I2C_CLR_TX_OVER_OFST 0x4c
2890/* The address of the ALT_I2C_CLR_TX_OVER register. */
2891#define ALT_I2C_CLR_TX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_OVER_OFST))
2892
2893/*
2894 * Register : Interrupt Read Request Register - ic_clr_rd_req
2895 *
2896 * Clear RD_REQ Interrupt Register
2897 *
2898 * Register Layout
2899 *
2900 * Bits | Access | Reset | Description
2901 * :-------|:-------|:------|:------------------------------------
2902 * [0] | R | 0x0 | Interrupt Register Read Request Bit
2903 * [31:1] | ??? | 0x0 | *UNDEFINED*
2904 *
2905 */
2906/*
2907 * Field : Interrupt Register Read Request Bit - clr_rd_req
2908 *
2909 * Read this register to clear the RD_REQ interrupt (bit 5) of the ic_raw_intr_stat
2910 * register.
2911 *
2912 * Field Access Macros:
2913 *
2914 */
2915/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */
2916#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_LSB 0
2917/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */
2918#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_MSB 0
2919/* The width in bits of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */
2920#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_WIDTH 1
2921/* The mask used to set the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */
2922#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET_MSK 0x00000001
2923/* The mask used to clear the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */
2924#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_CLR_MSK 0xfffffffe
2925/* The reset value of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */
2926#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0
2927/* Extracts the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ field value from a register. */
2928#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_GET(value) (((value) & 0x00000001) >> 0)
2929/* Produces a ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value suitable for setting the register. */
2930#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET(value) (((value) << 0) & 0x00000001)
2931
2932#ifndef __ASSEMBLY__
2933/*
2934 * WARNING: The C register and register group struct declarations are provided for
2935 * convenience and illustrative purposes. They should, however, be used with
2936 * caution as the C language standard provides no guarantees about the alignment or
2937 * atomicity of device memory accesses. The recommended practice for writing
2938 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2939 * alt_write_word() functions.
2940 *
2941 * The struct declaration for register ALT_I2C_CLR_RD_REQ.
2942 */
2943 struct ALT_I2C_CLR_RD_REQ_s
2944{
2945 const uint32_t clr_rd_req : 1; /* Interrupt Register Read Request Bit */
2946 uint32_t : 31; /* *UNDEFINED* */
2947};
2948
2949/* The typedef declaration for register ALT_I2C_CLR_RD_REQ. */
2950typedef volatile struct ALT_I2C_CLR_RD_REQ_s ALT_I2C_CLR_RD_REQ_t;
2951#endif /* __ASSEMBLY__ */
2952
2953/* The byte offset of the ALT_I2C_CLR_RD_REQ register from the beginning of the component. */
2954#define ALT_I2C_CLR_RD_REQ_OFST 0x50
2955/* The address of the ALT_I2C_CLR_RD_REQ register. */
2956#define ALT_I2C_CLR_RD_REQ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RD_REQ_OFST))
2957
2958/*
2959 * Register : Tx Abort Interrupt Register - ic_clr_tx_abrt
2960 *
2961 * Clear TX_ABRT Interrupt
2962 *
2963 * Register Layout
2964 *
2965 * Bits | Access | Reset | Description
2966 * :-------|:-------|:------|:-----------------------
2967 * [0] | R | 0x0 | Tx Abort Interrupt Bit
2968 * [31:1] | ??? | 0x0 | *UNDEFINED*
2969 *
2970 */
2971/*
2972 * Field : Tx Abort Interrupt Bit - clr_tx_abort
2973 *
2974 * Read this register to clear the TX_ABRT interrupt (bit 6) of the
2975 * ic_raw_intr_stat register, and the ic_tx_abrt_source register. This also
2976 * releases the TX FIFO from the flushed/reset state, allowing more writes to the
2977 * TX FIFO. Refer to Bit 9 of the ic_tx_abrt_source register for an exception to
2978 * clearing ic_tx_abrt_source.
2979 *
2980 * Field Access Macros:
2981 *
2982 */
2983/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */
2984#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_LSB 0
2985/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */
2986#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_MSB 0
2987/* The width in bits of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */
2988#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_WIDTH 1
2989/* The mask used to set the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */
2990#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET_MSK 0x00000001
2991/* The mask used to clear the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */
2992#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_CLR_MSK 0xfffffffe
2993/* The reset value of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */
2994#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_RESET 0x0
2995/* Extracts the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT field value from a register. */
2996#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_GET(value) (((value) & 0x00000001) >> 0)
2997/* Produces a ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value suitable for setting the register. */
2998#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET(value) (((value) << 0) & 0x00000001)
2999
3000#ifndef __ASSEMBLY__
3001/*
3002 * WARNING: The C register and register group struct declarations are provided for
3003 * convenience and illustrative purposes. They should, however, be used with
3004 * caution as the C language standard provides no guarantees about the alignment or
3005 * atomicity of device memory accesses. The recommended practice for writing
3006 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3007 * alt_write_word() functions.
3008 *
3009 * The struct declaration for register ALT_I2C_CLR_TX_ABRT.
3010 */
3011 struct ALT_I2C_CLR_TX_ABRT_s
3012{
3013 const uint32_t clr_tx_abort : 1; /* Tx Abort Interrupt Bit */
3014 uint32_t : 31; /* *UNDEFINED* */
3015};
3016
3017/* The typedef declaration for register ALT_I2C_CLR_TX_ABRT. */
3018typedef volatile struct ALT_I2C_CLR_TX_ABRT_s ALT_I2C_CLR_TX_ABRT_t;
3019#endif /* __ASSEMBLY__ */
3020
3021/* The byte offset of the ALT_I2C_CLR_TX_ABRT register from the beginning of the component. */
3022#define ALT_I2C_CLR_TX_ABRT_OFST 0x54
3023/* The address of the ALT_I2C_CLR_TX_ABRT register. */
3024#define ALT_I2C_CLR_TX_ABRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_ABRT_OFST))
3025
3026/*
3027 * Register : Rx Done Interrupt Register - ic_clr_rx_done
3028 *
3029 * Clear RX_DONE Interrupt Register
3030 *
3031 * Register Layout
3032 *
3033 * Bits | Access | Reset | Description
3034 * :-------|:-------|:------|:----------------------
3035 * [0] | R | 0x0 | RX_DONE Interrupt Bit
3036 * [31:1] | ??? | 0x0 | *UNDEFINED*
3037 *
3038 */
3039/*
3040 * Field : RX_DONE Interrupt Bit - clr_rx_done
3041 *
3042 * Read this register to clear the RX_DONE interrupt (bit 7) of the
3043 * ic_raw_intr_stat register.
3044 *
3045 * Field Access Macros:
3046 *
3047 */
3048/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */
3049#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_LSB 0
3050/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */
3051#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_MSB 0
3052/* The width in bits of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */
3053#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_WIDTH 1
3054/* The mask used to set the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */
3055#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET_MSK 0x00000001
3056/* The mask used to clear the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */
3057#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_CLR_MSK 0xfffffffe
3058/* The reset value of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */
3059#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0
3060/* Extracts the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE field value from a register. */
3061#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_GET(value) (((value) & 0x00000001) >> 0)
3062/* Produces a ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value suitable for setting the register. */
3063#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET(value) (((value) << 0) & 0x00000001)
3064
3065#ifndef __ASSEMBLY__
3066/*
3067 * WARNING: The C register and register group struct declarations are provided for
3068 * convenience and illustrative purposes. They should, however, be used with
3069 * caution as the C language standard provides no guarantees about the alignment or
3070 * atomicity of device memory accesses. The recommended practice for writing
3071 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3072 * alt_write_word() functions.
3073 *
3074 * The struct declaration for register ALT_I2C_CLR_RX_DONE.
3075 */
3076 struct ALT_I2C_CLR_RX_DONE_s
3077{
3078 const uint32_t clr_rx_done : 1; /* RX_DONE Interrupt Bit */
3079 uint32_t : 31; /* *UNDEFINED* */
3080};
3081
3082/* The typedef declaration for register ALT_I2C_CLR_RX_DONE. */
3083typedef volatile struct ALT_I2C_CLR_RX_DONE_s ALT_I2C_CLR_RX_DONE_t;
3084#endif /* __ASSEMBLY__ */
3085
3086/* The byte offset of the ALT_I2C_CLR_RX_DONE register from the beginning of the component. */
3087#define ALT_I2C_CLR_RX_DONE_OFST 0x58
3088/* The address of the ALT_I2C_CLR_RX_DONE register. */
3089#define ALT_I2C_CLR_RX_DONE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_DONE_OFST))
3090
3091/*
3092 * Register : Activity Interrupt Register - ic_clr_activity
3093 *
3094 * Clears ACTIVITY Interrupt
3095 *
3096 * Register Layout
3097 *
3098 * Bits | Access | Reset | Description
3099 * :-------|:-------|:------|:-----------------------
3100 * [0] | R | 0x0 | Activity Interrupt Bit
3101 * [31:1] | ??? | 0x0 | *UNDEFINED*
3102 *
3103 */
3104/*
3105 * Field : Activity Interrupt Bit - clr_activity
3106 *
3107 * Reading this register clears the ACTIVITY interrupt if the I2C is not active
3108 * anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt
3109 * bit continues to be set. It is automatically cleared by hardware if the module
3110 * is disabled and if there is no further activity on the bus. The value read from
3111 * this register to get status of the ACTIVITY interrupt (bit 8) of the
3112 * ic_raw_intr_stat register.
3113 *
3114 * Field Access Macros:
3115 *
3116 */
3117/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */
3118#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0
3119/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */
3120#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0
3121/* The width in bits of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */
3122#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_WIDTH 1
3123/* The mask used to set the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */
3124#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET_MSK 0x00000001
3125/* The mask used to clear the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */
3126#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_CLR_MSK 0xfffffffe
3127/* The reset value of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */
3128#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0
3129/* Extracts the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY field value from a register. */
3130#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
3131/* Produces a ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value suitable for setting the register. */
3132#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
3133
3134#ifndef __ASSEMBLY__
3135/*
3136 * WARNING: The C register and register group struct declarations are provided for
3137 * convenience and illustrative purposes. They should, however, be used with
3138 * caution as the C language standard provides no guarantees about the alignment or
3139 * atomicity of device memory accesses. The recommended practice for writing
3140 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3141 * alt_write_word() functions.
3142 *
3143 * The struct declaration for register ALT_I2C_CLR_ACTIVITY.
3144 */
3145 struct ALT_I2C_CLR_ACTIVITY_s
3146{
3147 const uint32_t clr_activity : 1; /* Activity Interrupt Bit */
3148 uint32_t : 31; /* *UNDEFINED* */
3149};
3150
3151/* The typedef declaration for register ALT_I2C_CLR_ACTIVITY. */
3152typedef volatile struct ALT_I2C_CLR_ACTIVITY_s ALT_I2C_CLR_ACTIVITY_t;
3153#endif /* __ASSEMBLY__ */
3154
3155/* The byte offset of the ALT_I2C_CLR_ACTIVITY register from the beginning of the component. */
3156#define ALT_I2C_CLR_ACTIVITY_OFST 0x5c
3157/* The address of the ALT_I2C_CLR_ACTIVITY register. */
3158#define ALT_I2C_CLR_ACTIVITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_ACTIVITY_OFST))
3159
3160/*
3161 * Register : Stop Detect Interrupt Register - ic_clr_stop_det
3162 *
3163 * Clear Interrupts.
3164 *
3165 * Register Layout
3166 *
3167 * Bits | Access | Reset | Description
3168 * :-------|:-------|:------|:--------------------------
3169 * [0] | R | 0x0 | Stop Detect Interrupt Bit
3170 * [31:1] | ??? | 0x0 | *UNDEFINED*
3171 *
3172 */
3173/*
3174 * Field : Stop Detect Interrupt Bit - clr_stop_det
3175 *
3176 * Read this register to clear the clr_stop_det interrupt (bit 9) of the
3177 * ic_raw_intr_stat register.
3178 *
3179 * Field Access Macros:
3180 *
3181 */
3182/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */
3183#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_LSB 0
3184/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */
3185#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_MSB 0
3186/* The width in bits of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */
3187#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_WIDTH 1
3188/* The mask used to set the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */
3189#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET_MSK 0x00000001
3190/* The mask used to clear the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */
3191#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_CLR_MSK 0xfffffffe
3192/* The reset value of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */
3193#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0
3194/* Extracts the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET field value from a register. */
3195#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_GET(value) (((value) & 0x00000001) >> 0)
3196/* Produces a ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value suitable for setting the register. */
3197#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET(value) (((value) << 0) & 0x00000001)
3198
3199#ifndef __ASSEMBLY__
3200/*
3201 * WARNING: The C register and register group struct declarations are provided for
3202 * convenience and illustrative purposes. They should, however, be used with
3203 * caution as the C language standard provides no guarantees about the alignment or
3204 * atomicity of device memory accesses. The recommended practice for writing
3205 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3206 * alt_write_word() functions.
3207 *
3208 * The struct declaration for register ALT_I2C_CLR_STOP_DET.
3209 */
3210 struct ALT_I2C_CLR_STOP_DET_s
3211{
3212 const uint32_t clr_stop_det : 1; /* Stop Detect Interrupt Bit */
3213 uint32_t : 31; /* *UNDEFINED* */
3214};
3215
3216/* The typedef declaration for register ALT_I2C_CLR_STOP_DET. */
3217typedef volatile struct ALT_I2C_CLR_STOP_DET_s ALT_I2C_CLR_STOP_DET_t;
3218#endif /* __ASSEMBLY__ */
3219
3220/* The byte offset of the ALT_I2C_CLR_STOP_DET register from the beginning of the component. */
3221#define ALT_I2C_CLR_STOP_DET_OFST 0x60
3222/* The address of the ALT_I2C_CLR_STOP_DET register. */
3223#define ALT_I2C_CLR_STOP_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_STOP_DET_OFST))
3224
3225/*
3226 * Register : Start Detect Interrupt Register - ic_clr_start_det
3227 *
3228 * Clears START_DET Interrupt
3229 *
3230 * Register Layout
3231 *
3232 * Bits | Access | Reset | Description
3233 * :-------|:-------|:------|:---------------------------
3234 * [0] | R | 0x0 | Start Detect Interrupt Bit
3235 * [31:1] | ??? | 0x0 | *UNDEFINED*
3236 *
3237 */
3238/*
3239 * Field : Start Detect Interrupt Bit - clr_start_det
3240 *
3241 * Read this register to clear the start_det interrupt (bit 10) of the
3242 * ic_raw_intr_stat register.
3243 *
3244 * Field Access Macros:
3245 *
3246 */
3247/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */
3248#define ALT_I2C_CLR_START_DET_CLR_START_DET_LSB 0
3249/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */
3250#define ALT_I2C_CLR_START_DET_CLR_START_DET_MSB 0
3251/* The width in bits of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */
3252#define ALT_I2C_CLR_START_DET_CLR_START_DET_WIDTH 1
3253/* The mask used to set the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */
3254#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET_MSK 0x00000001
3255/* The mask used to clear the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */
3256#define ALT_I2C_CLR_START_DET_CLR_START_DET_CLR_MSK 0xfffffffe
3257/* The reset value of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */
3258#define ALT_I2C_CLR_START_DET_CLR_START_DET_RESET 0x0
3259/* Extracts the ALT_I2C_CLR_START_DET_CLR_START_DET field value from a register. */
3260#define ALT_I2C_CLR_START_DET_CLR_START_DET_GET(value) (((value) & 0x00000001) >> 0)
3261/* Produces a ALT_I2C_CLR_START_DET_CLR_START_DET register field value suitable for setting the register. */
3262#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET(value) (((value) << 0) & 0x00000001)
3263
3264#ifndef __ASSEMBLY__
3265/*
3266 * WARNING: The C register and register group struct declarations are provided for
3267 * convenience and illustrative purposes. They should, however, be used with
3268 * caution as the C language standard provides no guarantees about the alignment or
3269 * atomicity of device memory accesses. The recommended practice for writing
3270 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3271 * alt_write_word() functions.
3272 *
3273 * The struct declaration for register ALT_I2C_CLR_START_DET.
3274 */
3275 struct ALT_I2C_CLR_START_DET_s
3276{
3277 const uint32_t clr_start_det : 1; /* Start Detect Interrupt Bit */
3278 uint32_t : 31; /* *UNDEFINED* */
3279};
3280
3281/* The typedef declaration for register ALT_I2C_CLR_START_DET. */
3282typedef volatile struct ALT_I2C_CLR_START_DET_s ALT_I2C_CLR_START_DET_t;
3283#endif /* __ASSEMBLY__ */
3284
3285/* The byte offset of the ALT_I2C_CLR_START_DET register from the beginning of the component. */
3286#define ALT_I2C_CLR_START_DET_OFST 0x64
3287/* The address of the ALT_I2C_CLR_START_DET register. */
3288#define ALT_I2C_CLR_START_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_START_DET_OFST))
3289
3290/*
3291 * Register : GEN CALL Interrupt Register - ic_clr_gen_call
3292 *
3293 * Clear GEN_CALL Interrupt Register
3294 *
3295 * Register Layout
3296 *
3297 * Bits | Access | Reset | Description
3298 * :-------|:-------|:------|:-----------------------
3299 * [0] | R | 0x0 | GEN CALL Interrupt Bit
3300 * [31:1] | ??? | 0x0 | *UNDEFINED*
3301 *
3302 */
3303/*
3304 * Field : GEN CALL Interrupt Bit - clr_gen_call
3305 *
3306 * Read this register to clear the GEN_CALL interrupt (bit 11) of ic_raw_intr_stat
3307 * register.
3308 *
3309 * Field Access Macros:
3310 *
3311 */
3312/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */
3313#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0
3314/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */
3315#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0
3316/* The width in bits of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */
3317#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_WIDTH 1
3318/* The mask used to set the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */
3319#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET_MSK 0x00000001
3320/* The mask used to clear the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */
3321#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_CLR_MSK 0xfffffffe
3322/* The reset value of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */
3323#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0
3324/* Extracts the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL field value from a register. */
3325#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
3326/* Produces a ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value suitable for setting the register. */
3327#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
3328
3329#ifndef __ASSEMBLY__
3330/*
3331 * WARNING: The C register and register group struct declarations are provided for
3332 * convenience and illustrative purposes. They should, however, be used with
3333 * caution as the C language standard provides no guarantees about the alignment or
3334 * atomicity of device memory accesses. The recommended practice for writing
3335 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3336 * alt_write_word() functions.
3337 *
3338 * The struct declaration for register ALT_I2C_CLR_GEN_CALL.
3339 */
3340 struct ALT_I2C_CLR_GEN_CALL_s
3341{
3342 const uint32_t clr_gen_call : 1; /* GEN CALL Interrupt Bit */
3343 uint32_t : 31; /* *UNDEFINED* */
3344};
3345
3346/* The typedef declaration for register ALT_I2C_CLR_GEN_CALL. */
3347typedef volatile struct ALT_I2C_CLR_GEN_CALL_s ALT_I2C_CLR_GEN_CALL_t;
3348#endif /* __ASSEMBLY__ */
3349
3350/* The byte offset of the ALT_I2C_CLR_GEN_CALL register from the beginning of the component. */
3351#define ALT_I2C_CLR_GEN_CALL_OFST 0x68
3352/* The address of the ALT_I2C_CLR_GEN_CALL register. */
3353#define ALT_I2C_CLR_GEN_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_GEN_CALL_OFST))
3354
3355/*
3356 * Register : Enable Register - ic_enable
3357 *
3358 * Enable and disable i2c operation
3359 *
3360 * Register Layout
3361 *
3362 * Bits | Access | Reset | Description
3363 * :-------|:-------|:------|:-------------
3364 * [0] | RW | 0x0 | Enable Bit
3365 * [1] | RW | 0x0 | TX abort Bit
3366 * [31:2] | ??? | 0x0 | *UNDEFINED*
3367 *
3368 */
3369/*
3370 * Field : Enable Bit - enable
3371 *
3372 * Controls whether the I2C is enabled. Software can disable I2C while it is
3373 * active. However, it is important that care be taken to ensure that I2C is
3374 * disabled properly. When the I2C is disabled, the following occurs:
3375 *
3376 * The TX FIFO and RX FIFO get flushed. Status bits in the IC_INTR_STAT register
3377 * are still active until I2C goes into IDLE state. If the module is transmitting,
3378 * it stops as well as deletes the contents of the transmit buffer after the
3379 * current transfer is complete. If the module is receiving, the I2C stops the
3380 * current transfer at the end of the current byte and does not acknowledge the
3381 * transfer. The l4_sp_clk synchronizes pclk and ic_clk. The register
3382 * ic_enable_status is added to allow software to determine when the hardware has
3383 * completely shutdown in response to the IC_ENABLE register being set from 1 to 0.
3384 * Only one register is required to be monitored. Procedure for Disabling I2C
3385 *
3386 * 1. Define a timer interval (ti2c_poll) equal to the 10 times the signaling
3387 * period for the highest I2C transfer speed used in the system and supported by
3388 * I2C. For example, if the highest I2C transfer mode is 400 kb/s, then this
3389 * ti2c_poll is 25us.
3390 *
3391 * 2. Define a maximum time-out parameter, MAX_T_POLL_COUNT, such that if any
3392 * repeated polling operation exceeds this maximum value, an error is reported. 3.
3393 * Execute a blocking thread/process/function that prevents any further I2C master
3394 * transactions to be started by software, but allows any pending transfers to be
3395 * completed.
3396 *
3397 * 4. The variable POLL_COUNT is initialized to zero. 5. Set IC_ENABLE to 0.
3398 *
3399 * 6. Read the IC_ENABLE_STATUS register and test the IC_EN bit (bit 0). Increment
3400 * POLL_COUNT by one. If POLL_COUNT >= MAX_T_POLL_COUNT, exit with the relevant
3401 * error code.
3402 *
3403 * 7. If IC_ENABLE_STATUS[0] is 1, then sleep for ti2c_poll and proceed to the
3404 * previous step. Otherwise, exit with a relevant success code.
3405 *
3406 * Field Enumeration Values:
3407 *
3408 * Enum | Value | Description
3409 * :--------------------|:------|:-----------------------------------------------
3410 * ALT_I2C_EN_EN_E_DIS | 0x0 | Disables i2c. TX and RX FIFOs are held in an
3411 * : | | erased state
3412 * ALT_I2C_EN_EN_E_EN | 0x1 | Enables i2c. Software can disable i2c while it
3413 * : | | is active
3414 *
3415 * Field Access Macros:
3416 *
3417 */
3418/*
3419 * Enumerated value for register field ALT_I2C_EN_EN
3420 *
3421 * Disables i2c. TX and RX FIFOs are held in an erased state
3422 */
3423#define ALT_I2C_EN_EN_E_DIS 0x0
3424/*
3425 * Enumerated value for register field ALT_I2C_EN_EN
3426 *
3427 * Enables i2c. Software can disable i2c while it is active
3428 */
3429#define ALT_I2C_EN_EN_E_EN 0x1
3430
3431/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_EN register field. */
3432#define ALT_I2C_EN_EN_LSB 0
3433/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_EN register field. */
3434#define ALT_I2C_EN_EN_MSB 0
3435/* The width in bits of the ALT_I2C_EN_EN register field. */
3436#define ALT_I2C_EN_EN_WIDTH 1
3437/* The mask used to set the ALT_I2C_EN_EN register field value. */
3438#define ALT_I2C_EN_EN_SET_MSK 0x00000001
3439/* The mask used to clear the ALT_I2C_EN_EN register field value. */
3440#define ALT_I2C_EN_EN_CLR_MSK 0xfffffffe
3441/* The reset value of the ALT_I2C_EN_EN register field. */
3442#define ALT_I2C_EN_EN_RESET 0x0
3443/* Extracts the ALT_I2C_EN_EN field value from a register. */
3444#define ALT_I2C_EN_EN_GET(value) (((value) & 0x00000001) >> 0)
3445/* Produces a ALT_I2C_EN_EN register field value suitable for setting the register. */
3446#define ALT_I2C_EN_EN_SET(value) (((value) << 0) & 0x00000001)
3447
3448/*
3449 * Field : TX abort Bit - txabort
3450 *
3451 * Write 1 does a TX abort. Self cleared on abort completion
3452 *
3453 * Field Access Macros:
3454 *
3455 */
3456/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_TXABT register field. */
3457#define ALT_I2C_EN_TXABT_LSB 1
3458/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_TXABT register field. */
3459#define ALT_I2C_EN_TXABT_MSB 1
3460/* The width in bits of the ALT_I2C_EN_TXABT register field. */
3461#define ALT_I2C_EN_TXABT_WIDTH 1
3462/* The mask used to set the ALT_I2C_EN_TXABT register field value. */
3463#define ALT_I2C_EN_TXABT_SET_MSK 0x00000002
3464/* The mask used to clear the ALT_I2C_EN_TXABT register field value. */
3465#define ALT_I2C_EN_TXABT_CLR_MSK 0xfffffffd
3466/* The reset value of the ALT_I2C_EN_TXABT register field. */
3467#define ALT_I2C_EN_TXABT_RESET 0x0
3468/* Extracts the ALT_I2C_EN_TXABT field value from a register. */
3469#define ALT_I2C_EN_TXABT_GET(value) (((value) & 0x00000002) >> 1)
3470/* Produces a ALT_I2C_EN_TXABT register field value suitable for setting the register. */
3471#define ALT_I2C_EN_TXABT_SET(value) (((value) << 1) & 0x00000002)
3472
3473#ifndef __ASSEMBLY__
3474/*
3475 * WARNING: The C register and register group struct declarations are provided for
3476 * convenience and illustrative purposes. They should, however, be used with
3477 * caution as the C language standard provides no guarantees about the alignment or
3478 * atomicity of device memory accesses. The recommended practice for writing
3479 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3480 * alt_write_word() functions.
3481 *
3482 * The struct declaration for register ALT_I2C_EN.
3483 */
3484 struct ALT_I2C_EN_s
3485{
3486 uint32_t enable : 1; /* Enable Bit */
3487 uint32_t txabort : 1; /* TX abort Bit */
3488 uint32_t : 30; /* *UNDEFINED* */
3489};
3490
3491/* The typedef declaration for register ALT_I2C_EN. */
3492typedef volatile struct ALT_I2C_EN_s ALT_I2C_EN_t;
3493#endif /* __ASSEMBLY__ */
3494
3495/* The byte offset of the ALT_I2C_EN register from the beginning of the component. */
3496#define ALT_I2C_EN_OFST 0x6c
3497/* The address of the ALT_I2C_EN register. */
3498#define ALT_I2C_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_OFST))
3499
3500/*
3501 * Register : Status Register - ic_status
3502 *
3503 * This is a read-only register used to indicate the current transfer status and
3504 * FIFO status. The status register may be read at any time. None of the bits in
3505 * this register request an interrupt.When the I2C is disabled by writing 0 in bit
3506 * 0 of the ic_enable register:
3507 *
3508 * * Bits 1 and 2 are set to 1
3509 *
3510 * * Bits 3 and 4 are set to 0
3511 *
3512 * When the master or slave state machines goes to idle
3513 *
3514 * * Bits 5 and 6 are set to 0
3515 *
3516 * Register Layout
3517 *
3518 * Bits | Access | Reset | Description
3519 * :-------|:-------|:------|:-------------------------------
3520 * [0] | R | 0x0 | Activity Status Bit
3521 * [1] | R | 0x1 | TX FIFO Not Full Bit
3522 * [2] | R | 0x1 | TX FIFO Empty Bit
3523 * [3] | R | 0x0 | RX FIFO Empty Bit
3524 * [4] | R | 0x0 | RX FIFO Full Bit
3525 * [5] | R | 0x0 | Master FSM Activity Status Bit
3526 * [6] | R | 0x0 | Slave FSM Activity Status Bit
3527 * [31:7] | ??? | 0x0 | *UNDEFINED*
3528 *
3529 */
3530/*
3531 * Field : Activity Status Bit - activity
3532 *
3533 * I2C Activity.
3534 *
3535 * Field Access Macros:
3536 *
3537 */
3538/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_ACTIVITY register field. */
3539#define ALT_I2C_STAT_ACTIVITY_LSB 0
3540/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_ACTIVITY register field. */
3541#define ALT_I2C_STAT_ACTIVITY_MSB 0
3542/* The width in bits of the ALT_I2C_STAT_ACTIVITY register field. */
3543#define ALT_I2C_STAT_ACTIVITY_WIDTH 1
3544/* The mask used to set the ALT_I2C_STAT_ACTIVITY register field value. */
3545#define ALT_I2C_STAT_ACTIVITY_SET_MSK 0x00000001
3546/* The mask used to clear the ALT_I2C_STAT_ACTIVITY register field value. */
3547#define ALT_I2C_STAT_ACTIVITY_CLR_MSK 0xfffffffe
3548/* The reset value of the ALT_I2C_STAT_ACTIVITY register field. */
3549#define ALT_I2C_STAT_ACTIVITY_RESET 0x0
3550/* Extracts the ALT_I2C_STAT_ACTIVITY field value from a register. */
3551#define ALT_I2C_STAT_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
3552/* Produces a ALT_I2C_STAT_ACTIVITY register field value suitable for setting the register. */
3553#define ALT_I2C_STAT_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
3554
3555/*
3556 * Field : TX FIFO Not Full Bit - tfnf
3557 *
3558 * Transmit Fifo Full
3559 *
3560 * Field Enumeration Values:
3561 *
3562 * Enum | Value | Description
3563 * :----------------------------|:------|:--------------------------
3564 * ALT_I2C_STAT_TFNF_E_FULL | 0x0 | Transmit FIFO is full
3565 * ALT_I2C_STAT_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full
3566 *
3567 * Field Access Macros:
3568 *
3569 */
3570/*
3571 * Enumerated value for register field ALT_I2C_STAT_TFNF
3572 *
3573 * Transmit FIFO is full
3574 */
3575#define ALT_I2C_STAT_TFNF_E_FULL 0x0
3576/*
3577 * Enumerated value for register field ALT_I2C_STAT_TFNF
3578 *
3579 * Transmit FIFO is not full
3580 */
3581#define ALT_I2C_STAT_TFNF_E_NOTFULL 0x1
3582
3583/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFNF register field. */
3584#define ALT_I2C_STAT_TFNF_LSB 1
3585/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFNF register field. */
3586#define ALT_I2C_STAT_TFNF_MSB 1
3587/* The width in bits of the ALT_I2C_STAT_TFNF register field. */
3588#define ALT_I2C_STAT_TFNF_WIDTH 1
3589/* The mask used to set the ALT_I2C_STAT_TFNF register field value. */
3590#define ALT_I2C_STAT_TFNF_SET_MSK 0x00000002
3591/* The mask used to clear the ALT_I2C_STAT_TFNF register field value. */
3592#define ALT_I2C_STAT_TFNF_CLR_MSK 0xfffffffd
3593/* The reset value of the ALT_I2C_STAT_TFNF register field. */
3594#define ALT_I2C_STAT_TFNF_RESET 0x1
3595/* Extracts the ALT_I2C_STAT_TFNF field value from a register. */
3596#define ALT_I2C_STAT_TFNF_GET(value) (((value) & 0x00000002) >> 1)
3597/* Produces a ALT_I2C_STAT_TFNF register field value suitable for setting the register. */
3598#define ALT_I2C_STAT_TFNF_SET(value) (((value) << 1) & 0x00000002)
3599
3600/*
3601 * Field : TX FIFO Empty Bit - tfe
3602 *
3603 * Transmit FIFO Empty.
3604 *
3605 * Field Enumeration Values:
3606 *
3607 * Enum | Value | Description
3608 * :----------------------------|:------|:---------------------------
3609 * ALT_I2C_STAT_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty
3610 * ALT_I2C_STAT_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty
3611 *
3612 * Field Access Macros:
3613 *
3614 */
3615/*
3616 * Enumerated value for register field ALT_I2C_STAT_TFE
3617 *
3618 * Transmit FIFO is not empty
3619 */
3620#define ALT_I2C_STAT_TFE_E_NOTEMPTY 0x0
3621/*
3622 * Enumerated value for register field ALT_I2C_STAT_TFE
3623 *
3624 * Transmit FIFO is empty
3625 */
3626#define ALT_I2C_STAT_TFE_E_EMPTY 0x1
3627
3628/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFE register field. */
3629#define ALT_I2C_STAT_TFE_LSB 2
3630/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFE register field. */
3631#define ALT_I2C_STAT_TFE_MSB 2
3632/* The width in bits of the ALT_I2C_STAT_TFE register field. */
3633#define ALT_I2C_STAT_TFE_WIDTH 1
3634/* The mask used to set the ALT_I2C_STAT_TFE register field value. */
3635#define ALT_I2C_STAT_TFE_SET_MSK 0x00000004
3636/* The mask used to clear the ALT_I2C_STAT_TFE register field value. */
3637#define ALT_I2C_STAT_TFE_CLR_MSK 0xfffffffb
3638/* The reset value of the ALT_I2C_STAT_TFE register field. */
3639#define ALT_I2C_STAT_TFE_RESET 0x1
3640/* Extracts the ALT_I2C_STAT_TFE field value from a register. */
3641#define ALT_I2C_STAT_TFE_GET(value) (((value) & 0x00000004) >> 2)
3642/* Produces a ALT_I2C_STAT_TFE register field value suitable for setting the register. */
3643#define ALT_I2C_STAT_TFE_SET(value) (((value) << 2) & 0x00000004)
3644
3645/*
3646 * Field : RX FIFO Empty Bit - rfne
3647 *
3648 * Receive FIFO Not Empty.
3649 *
3650 * Field Enumeration Values:
3651 *
3652 * Enum | Value | Description
3653 * :-----------------------------|:------|:--------------------------
3654 * ALT_I2C_STAT_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty
3655 * ALT_I2C_STAT_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty
3656 *
3657 * Field Access Macros:
3658 *
3659 */
3660/*
3661 * Enumerated value for register field ALT_I2C_STAT_RFNE
3662 *
3663 * Receive FIFO is empty
3664 */
3665#define ALT_I2C_STAT_RFNE_E_EMPTY 0x0
3666/*
3667 * Enumerated value for register field ALT_I2C_STAT_RFNE
3668 *
3669 * Receive FIFO is not empty
3670 */
3671#define ALT_I2C_STAT_RFNE_E_NOTEMPTY 0x1
3672
3673/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFNE register field. */
3674#define ALT_I2C_STAT_RFNE_LSB 3
3675/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFNE register field. */
3676#define ALT_I2C_STAT_RFNE_MSB 3
3677/* The width in bits of the ALT_I2C_STAT_RFNE register field. */
3678#define ALT_I2C_STAT_RFNE_WIDTH 1
3679/* The mask used to set the ALT_I2C_STAT_RFNE register field value. */
3680#define ALT_I2C_STAT_RFNE_SET_MSK 0x00000008
3681/* The mask used to clear the ALT_I2C_STAT_RFNE register field value. */
3682#define ALT_I2C_STAT_RFNE_CLR_MSK 0xfffffff7
3683/* The reset value of the ALT_I2C_STAT_RFNE register field. */
3684#define ALT_I2C_STAT_RFNE_RESET 0x0
3685/* Extracts the ALT_I2C_STAT_RFNE field value from a register. */
3686#define ALT_I2C_STAT_RFNE_GET(value) (((value) & 0x00000008) >> 3)
3687/* Produces a ALT_I2C_STAT_RFNE register field value suitable for setting the register. */
3688#define ALT_I2C_STAT_RFNE_SET(value) (((value) << 3) & 0x00000008)
3689
3690/*
3691 * Field : RX FIFO Full Bit - rff
3692 *
3693 * Receive FIFO Completely Full.
3694 *
3695 * Field Enumeration Values:
3696 *
3697 * Enum | Value | Description
3698 * :---------------------------|:------|:-------------------------
3699 * ALT_I2C_STAT_RFF_E_NOTFULL | 0x0 | Receive FIFO is not full
3700 * ALT_I2C_STAT_RFF_E_FULL | 0x1 | Receive FIFO is full
3701 *
3702 * Field Access Macros:
3703 *
3704 */
3705/*
3706 * Enumerated value for register field ALT_I2C_STAT_RFF
3707 *
3708 * Receive FIFO is not full
3709 */
3710#define ALT_I2C_STAT_RFF_E_NOTFULL 0x0
3711/*
3712 * Enumerated value for register field ALT_I2C_STAT_RFF
3713 *
3714 * Receive FIFO is full
3715 */
3716#define ALT_I2C_STAT_RFF_E_FULL 0x1
3717
3718/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFF register field. */
3719#define ALT_I2C_STAT_RFF_LSB 4
3720/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFF register field. */
3721#define ALT_I2C_STAT_RFF_MSB 4
3722/* The width in bits of the ALT_I2C_STAT_RFF register field. */
3723#define ALT_I2C_STAT_RFF_WIDTH 1
3724/* The mask used to set the ALT_I2C_STAT_RFF register field value. */
3725#define ALT_I2C_STAT_RFF_SET_MSK 0x00000010
3726/* The mask used to clear the ALT_I2C_STAT_RFF register field value. */
3727#define ALT_I2C_STAT_RFF_CLR_MSK 0xffffffef
3728/* The reset value of the ALT_I2C_STAT_RFF register field. */
3729#define ALT_I2C_STAT_RFF_RESET 0x0
3730/* Extracts the ALT_I2C_STAT_RFF field value from a register. */
3731#define ALT_I2C_STAT_RFF_GET(value) (((value) & 0x00000010) >> 4)
3732/* Produces a ALT_I2C_STAT_RFF register field value suitable for setting the register. */
3733#define ALT_I2C_STAT_RFF_SET(value) (((value) << 4) & 0x00000010)
3734
3735/*
3736 * Field : Master FSM Activity Status Bit - mst_activity
3737 *
3738 * When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is
3739 * set. Note:IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and
3740 * MST_ACTIVITY bits.
3741 *
3742 * Field Enumeration Values:
3743 *
3744 * Enum | Value | Description
3745 * :------------------------------------|:------|:------------------------------------------------
3746 * ALT_I2C_STAT_MST_ACTIVITY_E_IDLE | 0x0 | Master FSM is in IDLE state. Master part of i2c
3747 * : | | is not Active
3748 * ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE | 0x1 | Master FSM is not in IDLE state. Master part of
3749 * : | | i2c is Active
3750 *
3751 * Field Access Macros:
3752 *
3753 */
3754/*
3755 * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY
3756 *
3757 * Master FSM is in IDLE state. Master part of i2c is not Active
3758 */
3759#define ALT_I2C_STAT_MST_ACTIVITY_E_IDLE 0x0
3760/*
3761 * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY
3762 *
3763 * Master FSM is not in IDLE state. Master part of i2c is Active
3764 */
3765#define ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE 0x1
3766
3767/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */
3768#define ALT_I2C_STAT_MST_ACTIVITY_LSB 5
3769/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */
3770#define ALT_I2C_STAT_MST_ACTIVITY_MSB 5
3771/* The width in bits of the ALT_I2C_STAT_MST_ACTIVITY register field. */
3772#define ALT_I2C_STAT_MST_ACTIVITY_WIDTH 1
3773/* The mask used to set the ALT_I2C_STAT_MST_ACTIVITY register field value. */
3774#define ALT_I2C_STAT_MST_ACTIVITY_SET_MSK 0x00000020
3775/* The mask used to clear the ALT_I2C_STAT_MST_ACTIVITY register field value. */
3776#define ALT_I2C_STAT_MST_ACTIVITY_CLR_MSK 0xffffffdf
3777/* The reset value of the ALT_I2C_STAT_MST_ACTIVITY register field. */
3778#define ALT_I2C_STAT_MST_ACTIVITY_RESET 0x0
3779/* Extracts the ALT_I2C_STAT_MST_ACTIVITY field value from a register. */
3780#define ALT_I2C_STAT_MST_ACTIVITY_GET(value) (((value) & 0x00000020) >> 5)
3781/* Produces a ALT_I2C_STAT_MST_ACTIVITY register field value suitable for setting the register. */
3782#define ALT_I2C_STAT_MST_ACTIVITY_SET(value) (((value) << 5) & 0x00000020)
3783
3784/*
3785 * Field : Slave FSM Activity Status Bit - slv_activity
3786 *
3787 * Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in
3788 * the IDLE state, this bit is set.
3789 *
3790 * Field Enumeration Values:
3791 *
3792 * Enum | Value | Description
3793 * :------------------------------------|:------|:-------------------------------------------------
3794 * ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE | 0x0 | Slave FSM is in IDLE state so the Slave part of
3795 * : | | i2c is not Active
3796 * ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE | 0x1 | Slave FSM is not in IDLE state so the Slave part
3797 * : | | of i2c is Active
3798 *
3799 * Field Access Macros:
3800 *
3801 */
3802/*
3803 * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY
3804 *
3805 * Slave FSM is in IDLE state so the Slave part of i2c is not Active
3806 */
3807#define ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE 0x0
3808/*
3809 * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY
3810 *
3811 * Slave FSM is not in IDLE state so the Slave part of i2c is Active
3812 */
3813#define ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE 0x1
3814
3815/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */
3816#define ALT_I2C_STAT_SLV_ACTIVITY_LSB 6
3817/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */
3818#define ALT_I2C_STAT_SLV_ACTIVITY_MSB 6
3819/* The width in bits of the ALT_I2C_STAT_SLV_ACTIVITY register field. */
3820#define ALT_I2C_STAT_SLV_ACTIVITY_WIDTH 1
3821/* The mask used to set the ALT_I2C_STAT_SLV_ACTIVITY register field value. */
3822#define ALT_I2C_STAT_SLV_ACTIVITY_SET_MSK 0x00000040
3823/* The mask used to clear the ALT_I2C_STAT_SLV_ACTIVITY register field value. */
3824#define ALT_I2C_STAT_SLV_ACTIVITY_CLR_MSK 0xffffffbf
3825/* The reset value of the ALT_I2C_STAT_SLV_ACTIVITY register field. */
3826#define ALT_I2C_STAT_SLV_ACTIVITY_RESET 0x0
3827/* Extracts the ALT_I2C_STAT_SLV_ACTIVITY field value from a register. */
3828#define ALT_I2C_STAT_SLV_ACTIVITY_GET(value) (((value) & 0x00000040) >> 6)
3829/* Produces a ALT_I2C_STAT_SLV_ACTIVITY register field value suitable for setting the register. */
3830#define ALT_I2C_STAT_SLV_ACTIVITY_SET(value) (((value) << 6) & 0x00000040)
3831
3832#ifndef __ASSEMBLY__
3833/*
3834 * WARNING: The C register and register group struct declarations are provided for
3835 * convenience and illustrative purposes. They should, however, be used with
3836 * caution as the C language standard provides no guarantees about the alignment or
3837 * atomicity of device memory accesses. The recommended practice for writing
3838 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3839 * alt_write_word() functions.
3840 *
3841 * The struct declaration for register ALT_I2C_STAT.
3842 */
3843 struct ALT_I2C_STAT_s
3844{
3845 const uint32_t activity : 1; /* Activity Status Bit */
3846 const uint32_t tfnf : 1; /* TX FIFO Not Full Bit */
3847 const uint32_t tfe : 1; /* TX FIFO Empty Bit */
3848 const uint32_t rfne : 1; /* RX FIFO Empty Bit */
3849 const uint32_t rff : 1; /* RX FIFO Full Bit */
3850 const uint32_t mst_activity : 1; /* Master FSM Activity Status Bit */
3851 const uint32_t slv_activity : 1; /* Slave FSM Activity Status Bit */
3852 uint32_t : 25; /* *UNDEFINED* */
3853};
3854
3855/* The typedef declaration for register ALT_I2C_STAT. */
3856typedef volatile struct ALT_I2C_STAT_s ALT_I2C_STAT_t;
3857#endif /* __ASSEMBLY__ */
3858
3859/* The byte offset of the ALT_I2C_STAT register from the beginning of the component. */
3860#define ALT_I2C_STAT_OFST 0x70
3861/* The address of the ALT_I2C_STAT register. */
3862#define ALT_I2C_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_STAT_OFST))
3863
3864/*
3865 * Register : Transmit FIFO Level Register - ic_txflr
3866 *
3867 * This register contains the number of valid data entries in the transmit FIFO
3868 * buffer. It is cleared whenever:
3869 *
3870 * * The I2C is disabled
3871 *
3872 * * There is a transmit abort that is, TX_ABRT bit is set in the ic_raw_intr_stat
3873 * register. The slave bulk transmit mode is aborted The register increments
3874 * whenever data is placed into the transmit FIFO and decrements when data is
3875 * taken from the transmit FIFO.
3876 *
3877 * Register Layout
3878 *
3879 * Bits | Access | Reset | Description
3880 * :-------|:-------|:------|:------------------------
3881 * [6:0] | R | 0x0 | Transmit FIFO Level Bit
3882 * [31:7] | ??? | 0x0 | *UNDEFINED*
3883 *
3884 */
3885/*
3886 * Field : Transmit FIFO Level Bit - txflr
3887 *
3888 * Transmit FIFO Level.Contains the number of valid data entries in the transmit
3889 * FIFO.
3890 *
3891 * Field Access Macros:
3892 *
3893 */
3894/* The Least Significant Bit (LSB) position of the ALT_I2C_TXFLR_TXFLR register field. */
3895#define ALT_I2C_TXFLR_TXFLR_LSB 0
3896/* The Most Significant Bit (MSB) position of the ALT_I2C_TXFLR_TXFLR register field. */
3897#define ALT_I2C_TXFLR_TXFLR_MSB 6
3898/* The width in bits of the ALT_I2C_TXFLR_TXFLR register field. */
3899#define ALT_I2C_TXFLR_TXFLR_WIDTH 7
3900/* The mask used to set the ALT_I2C_TXFLR_TXFLR register field value. */
3901#define ALT_I2C_TXFLR_TXFLR_SET_MSK 0x0000007f
3902/* The mask used to clear the ALT_I2C_TXFLR_TXFLR register field value. */
3903#define ALT_I2C_TXFLR_TXFLR_CLR_MSK 0xffffff80
3904/* The reset value of the ALT_I2C_TXFLR_TXFLR register field. */
3905#define ALT_I2C_TXFLR_TXFLR_RESET 0x0
3906/* Extracts the ALT_I2C_TXFLR_TXFLR field value from a register. */
3907#define ALT_I2C_TXFLR_TXFLR_GET(value) (((value) & 0x0000007f) >> 0)
3908/* Produces a ALT_I2C_TXFLR_TXFLR register field value suitable for setting the register. */
3909#define ALT_I2C_TXFLR_TXFLR_SET(value) (((value) << 0) & 0x0000007f)
3910
3911#ifndef __ASSEMBLY__
3912/*
3913 * WARNING: The C register and register group struct declarations are provided for
3914 * convenience and illustrative purposes. They should, however, be used with
3915 * caution as the C language standard provides no guarantees about the alignment or
3916 * atomicity of device memory accesses. The recommended practice for writing
3917 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3918 * alt_write_word() functions.
3919 *
3920 * The struct declaration for register ALT_I2C_TXFLR.
3921 */
3922 struct ALT_I2C_TXFLR_s
3923{
3924 const uint32_t txflr : 7; /* Transmit FIFO Level Bit */
3925 uint32_t : 25; /* *UNDEFINED* */
3926};
3927
3928/* The typedef declaration for register ALT_I2C_TXFLR. */
3929typedef volatile struct ALT_I2C_TXFLR_s ALT_I2C_TXFLR_t;
3930#endif /* __ASSEMBLY__ */
3931
3932/* The byte offset of the ALT_I2C_TXFLR register from the beginning of the component. */
3933#define ALT_I2C_TXFLR_OFST 0x74
3934/* The address of the ALT_I2C_TXFLR register. */
3935#define ALT_I2C_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TXFLR_OFST))
3936
3937/*
3938 * Register : Receive FIFO Level Register - ic_rxflr
3939 *
3940 * This register contains the number of valid data entries in the receive FIFO
3941 * buffer. It is cleared whenever:
3942 *
3943 * * The I2C is disabled
3944 *
3945 * * Whenever there is a transmit abort caused by any of the events tracked in
3946 * ic_tx_abrt_source The register increments whenever data is placed into the
3947 * receive FIFO and decrements when data is taken from the receive FIFO.
3948 *
3949 * Register Layout
3950 *
3951 * Bits | Access | Reset | Description
3952 * :-------|:-------|:------|:-----------------------
3953 * [6:0] | R | 0x0 | Receive FIFO Level Bit
3954 * [31:7] | ??? | 0x0 | *UNDEFINED*
3955 *
3956 */
3957/*
3958 * Field : Receive FIFO Level Bit - rxflr
3959 *
3960 * Receive FIFO Level. Contains the number of valid data entries in the receive
3961 * FIFO.
3962 *
3963 * Field Access Macros:
3964 *
3965 */
3966/* The Least Significant Bit (LSB) position of the ALT_I2C_RXFLR_RXFLR register field. */
3967#define ALT_I2C_RXFLR_RXFLR_LSB 0
3968/* The Most Significant Bit (MSB) position of the ALT_I2C_RXFLR_RXFLR register field. */
3969#define ALT_I2C_RXFLR_RXFLR_MSB 6
3970/* The width in bits of the ALT_I2C_RXFLR_RXFLR register field. */
3971#define ALT_I2C_RXFLR_RXFLR_WIDTH 7
3972/* The mask used to set the ALT_I2C_RXFLR_RXFLR register field value. */
3973#define ALT_I2C_RXFLR_RXFLR_SET_MSK 0x0000007f
3974/* The mask used to clear the ALT_I2C_RXFLR_RXFLR register field value. */
3975#define ALT_I2C_RXFLR_RXFLR_CLR_MSK 0xffffff80
3976/* The reset value of the ALT_I2C_RXFLR_RXFLR register field. */
3977#define ALT_I2C_RXFLR_RXFLR_RESET 0x0
3978/* Extracts the ALT_I2C_RXFLR_RXFLR field value from a register. */
3979#define ALT_I2C_RXFLR_RXFLR_GET(value) (((value) & 0x0000007f) >> 0)
3980/* Produces a ALT_I2C_RXFLR_RXFLR register field value suitable for setting the register. */
3981#define ALT_I2C_RXFLR_RXFLR_SET(value) (((value) << 0) & 0x0000007f)
3982
3983#ifndef __ASSEMBLY__
3984/*
3985 * WARNING: The C register and register group struct declarations are provided for
3986 * convenience and illustrative purposes. They should, however, be used with
3987 * caution as the C language standard provides no guarantees about the alignment or
3988 * atomicity of device memory accesses. The recommended practice for writing
3989 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3990 * alt_write_word() functions.
3991 *
3992 * The struct declaration for register ALT_I2C_RXFLR.
3993 */
3994 struct ALT_I2C_RXFLR_s
3995{
3996 const uint32_t rxflr : 7; /* Receive FIFO Level Bit */
3997 uint32_t : 25; /* *UNDEFINED* */
3998};
3999
4000/* The typedef declaration for register ALT_I2C_RXFLR. */
4001typedef volatile struct ALT_I2C_RXFLR_s ALT_I2C_RXFLR_t;
4002#endif /* __ASSEMBLY__ */
4003
4004/* The byte offset of the ALT_I2C_RXFLR register from the beginning of the component. */
4005#define ALT_I2C_RXFLR_OFST 0x78
4006/* The address of the ALT_I2C_RXFLR register. */
4007#define ALT_I2C_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RXFLR_OFST))
4008
4009/*
4010 * Register : SDA Hold Register - ic_sda_hold
4011 *
4012 * This register controls the amount of time delay (in terms of number of l4_sp_clk
4013 * clock periods) introduced in the falling edge of SCL, relative to SDA changing,
4014 * when I2C services a read request in a slave-transmitter operation. The relevant
4015 * I2C requirement is thd:DAT as detailed in the I2C Bus Specification.
4016 *
4017 * Register Layout
4018 *
4019 * Bits | Access | Reset | Description
4020 * :--------|:-------|:------|:-------------
4021 * [15:0] | RW | 0x1 | SDA Hold Bit
4022 * [31:16] | ??? | 0x0 | *UNDEFINED*
4023 *
4024 */
4025/*
4026 * Field : SDA Hold Bit - ic_sda_hold
4027 *
4028 * Program to a minimum 0f 300ns.
4029 *
4030 * Field Access Macros:
4031 *
4032 */
4033/* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */
4034#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_LSB 0
4035/* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */
4036#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_MSB 15
4037/* The width in bits of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */
4038#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_WIDTH 16
4039/* The mask used to set the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */
4040#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET_MSK 0x0000ffff
4041/* The mask used to clear the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */
4042#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_CLR_MSK 0xffff0000
4043/* The reset value of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */
4044#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_RESET 0x1
4045/* Extracts the ALT_I2C_SDA_HOLD_IC_SDA_HOLD field value from a register. */
4046#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_GET(value) (((value) & 0x0000ffff) >> 0)
4047/* Produces a ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value suitable for setting the register. */
4048#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET(value) (((value) << 0) & 0x0000ffff)
4049
4050#ifndef __ASSEMBLY__
4051/*
4052 * WARNING: The C register and register group struct declarations are provided for
4053 * convenience and illustrative purposes. They should, however, be used with
4054 * caution as the C language standard provides no guarantees about the alignment or
4055 * atomicity of device memory accesses. The recommended practice for writing
4056 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4057 * alt_write_word() functions.
4058 *
4059 * The struct declaration for register ALT_I2C_SDA_HOLD.
4060 */
4061 struct ALT_I2C_SDA_HOLD_s
4062{
4063 uint32_t ic_sda_hold : 16; /* SDA Hold Bit */
4064 uint32_t : 16; /* *UNDEFINED* */
4065};
4066
4067/* The typedef declaration for register ALT_I2C_SDA_HOLD. */
4068typedef volatile struct ALT_I2C_SDA_HOLD_s ALT_I2C_SDA_HOLD_t;
4069#endif /* __ASSEMBLY__ */
4070
4071/* The byte offset of the ALT_I2C_SDA_HOLD register from the beginning of the component. */
4072#define ALT_I2C_SDA_HOLD_OFST 0x7c
4073/* The address of the ALT_I2C_SDA_HOLD register. */
4074#define ALT_I2C_SDA_HOLD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_HOLD_OFST))
4075
4076/*
4077 * Register : Transmit Abort Source Register - ic_tx_abrt_source
4078 *
4079 * This register has 16 bits that indicate the source of the TX_ABRT bit. Except
4080 * for Bit 9, this register is cleared whenever the ic_clr_tx_abrt register or the
4081 * ic_clr_intr register is read. To clear Bit 9, the source of the
4082 * abrt_sbyte_norstrt must be fixed first; RESTART must be enabled (ic_con[5]=1),
4083 * the special bit must be cleared (ic_tar[11]), or the gc_or_start bit must be
4084 * cleared (ic_tar[10]). Once the source of the abrt_sbyte_norstrt is fixed, then
4085 * this bit can be cleared in the same manner as other bits in this register. If
4086 * the source of the abrt_sbyte_norstrt is not fixed before attempting to clear
4087 * this bit, Bit 9 clears for one cycle and is then re-asserted.
4088 *
4089 * Register Layout
4090 *
4091 * Bits | Access | Reset | Description
4092 * :--------|:-------|:------|:-----------------------------------
4093 * [0] | RW | 0x0 | Master Abort 7 Bit Address
4094 * [1] | RW | 0x0 | Master Abort 10 Bit Address Byte 1
4095 * [2] | RW | 0x0 | Master Abort 10 Bit Address Byte 2
4096 * [3] | RW | 0x0 | Master Abort TX Noack Bit
4097 * [4] | RW | 0x0 | Master Abort GC Noack Bit
4098 * [5] | RW | 0x0 | Master Abort GC Read Bit
4099 * [6] | RW | 0x0 | Master HS MC Ack
4100 * [7] | RW | 0x0 | Master Abort START Byte
4101 * [8] | RW | 0x0 | Master HS Restart Disabled
4102 * [9] | RW | 0x0 | Master Abort START No Restart
4103 * [10] | RW | 0x0 | Master Abort 10 Bit No Restart
4104 * [11] | RW | 0x0 | Master Oper Master Dis
4105 * [12] | RW | 0x0 | Master Abort Arbitration Lost
4106 * [13] | RW | 0x0 | Slave Abort Flush TXFIFO
4107 * [14] | RW | 0x0 | Slave Abort Arbitration Lost
4108 * [15] | RW | 0x0 | Slave Abort Read TX
4109 * [31:16] | ??? | 0x0 | *UNDEFINED*
4110 *
4111 */
4112/*
4113 * Field : Master Abort 7 Bit Address - abrt_7b_addr_noack
4114 *
4115 * Master is in 7-bit addressing mode and the address sent was not acknowledged by
4116 * any slave. Role of i2c: Master-Transmitter or Master-Receiver
4117 *
4118 * Field Access Macros:
4119 *
4120 */
4121/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */
4122#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_LSB 0
4123/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */
4124#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_MSB 0
4125/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */
4126#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_WIDTH 1
4127/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */
4128#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET_MSK 0x00000001
4129/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */
4130#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_CLR_MSK 0xfffffffe
4131/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */
4132#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_RESET 0x0
4133/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK field value from a register. */
4134#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_GET(value) (((value) & 0x00000001) >> 0)
4135/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value suitable for setting the register. */
4136#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET(value) (((value) << 0) & 0x00000001)
4137
4138/*
4139 * Field : Master Abort 10 Bit Address Byte 1 - abrt_10addr1_noack
4140 *
4141 * Master is in 10-bit address mode and the first 10-bit address byte was not
4142 * acknowledged by any slave. Role of i2c: Master-Transmitter or Master-Receiver
4143 *
4144 * Field Access Macros:
4145 *
4146 */
4147/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */
4148#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_LSB 1
4149/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */
4150#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_MSB 1
4151/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */
4152#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_WIDTH 1
4153/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */
4154#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET_MSK 0x00000002
4155/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */
4156#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_CLR_MSK 0xfffffffd
4157/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */
4158#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_RESET 0x0
4159/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK field value from a register. */
4160#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_GET(value) (((value) & 0x00000002) >> 1)
4161/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value suitable for setting the register. */
4162#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET(value) (((value) << 1) & 0x00000002)
4163
4164/*
4165 * Field : Master Abort 10 Bit Address Byte 2 - abrt_10addr2_noack
4166 *
4167 * Master is in 10-bit address mode and the second address byte of the 10-bit
4168 * address was not acknowledged by any slave. Role of i2c: Master-Transmitter or
4169 * Master-Receiver
4170 *
4171 * Field Access Macros:
4172 *
4173 */
4174/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */
4175#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_LSB 2
4176/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */
4177#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_MSB 2
4178/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */
4179#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_WIDTH 1
4180/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */
4181#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET_MSK 0x00000004
4182/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */
4183#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_CLR_MSK 0xfffffffb
4184/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */
4185#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_RESET 0x0
4186/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK field value from a register. */
4187#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_GET(value) (((value) & 0x00000004) >> 2)
4188/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value suitable for setting the register. */
4189#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET(value) (((value) << 2) & 0x00000004)
4190
4191/*
4192 * Field : Master Abort TX Noack Bit - abrt_txdata_noack
4193 *
4194 * This is a master-mode only bit. Master has received an acknowledgement for the
4195 * address, but when it sent data byte(s) following the address, it did not receive
4196 * an acknowledge from the remote slave(s). Role of i2c: Master-Transmitter
4197 *
4198 * Field Access Macros:
4199 *
4200 */
4201/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */
4202#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_LSB 3
4203/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */
4204#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_MSB 3
4205/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */
4206#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_WIDTH 1
4207/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */
4208#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET_MSK 0x00000008
4209/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */
4210#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_CLR_MSK 0xfffffff7
4211/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */
4212#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_RESET 0x0
4213/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK field value from a register. */
4214#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_GET(value) (((value) & 0x00000008) >> 3)
4215/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value suitable for setting the register. */
4216#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET(value) (((value) << 3) & 0x00000008)
4217
4218/*
4219 * Field : Master Abort GC Noack Bit - abrt_gcall_noack
4220 *
4221 * i2c in master mode sent a General Call and no slave on the bus acknowledged the
4222 * General Call. Role of i2c: Master-Transmitter
4223 *
4224 * Field Access Macros:
4225 *
4226 */
4227/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */
4228#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_LSB 4
4229/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */
4230#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_MSB 4
4231/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */
4232#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_WIDTH 1
4233/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */
4234#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET_MSK 0x00000010
4235/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */
4236#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_CLR_MSK 0xffffffef
4237/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */
4238#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_RESET 0x0
4239/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK field value from a register. */
4240#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_GET(value) (((value) & 0x00000010) >> 4)
4241/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value suitable for setting the register. */
4242#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET(value) (((value) << 4) & 0x00000010)
4243
4244/*
4245 * Field : Master Abort GC Read Bit - abrt_gcall_read
4246 *
4247 * i2c in master mode sent a General Call but the user programmed the byte
4248 * following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to
4249 * 1). Role of i2c: Master-Transmitter
4250 *
4251 * Field Access Macros:
4252 *
4253 */
4254/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */
4255#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_LSB 5
4256/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */
4257#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_MSB 5
4258/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */
4259#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_WIDTH 1
4260/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */
4261#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET_MSK 0x00000020
4262/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */
4263#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_CLR_MSK 0xffffffdf
4264/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */
4265#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_RESET 0x0
4266/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD field value from a register. */
4267#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_GET(value) (((value) & 0x00000020) >> 5)
4268/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value suitable for setting the register. */
4269#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET(value) (((value) << 5) & 0x00000020)
4270
4271/*
4272 * Field : Master HS MC Ack - abrt_hs_ackdet
4273 *
4274 * Master is in High Speed mode and the High Speed Master code was acknowledged
4275 * (wrong behavior). Role of i2c: Master
4276 *
4277 * Field Access Macros:
4278 *
4279 */
4280/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */
4281#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_LSB 6
4282/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */
4283#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_MSB 6
4284/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */
4285#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_WIDTH 1
4286/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */
4287#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET_MSK 0x00000040
4288/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */
4289#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_CLR_MSK 0xffffffbf
4290/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */
4291#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_RESET 0x0
4292/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET field value from a register. */
4293#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_GET(value) (((value) & 0x00000040) >> 6)
4294/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value suitable for setting the register. */
4295#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET(value) (((value) << 6) & 0x00000040)
4296
4297/*
4298 * Field : Master Abort START Byte - abrt_sbyte_ackdet
4299 *
4300 * Master has sent a START Byte and the START Byte was acknowledged (wrong
4301 * behavior). Role of i2c: Master
4302 *
4303 * Field Access Macros:
4304 *
4305 */
4306/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */
4307#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_LSB 7
4308/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */
4309#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_MSB 7
4310/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */
4311#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_WIDTH 1
4312/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */
4313#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET_MSK 0x00000080
4314/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */
4315#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_CLR_MSK 0xffffff7f
4316/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */
4317#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_RESET 0x0
4318/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET field value from a register. */
4319#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_GET(value) (((value) & 0x00000080) >> 7)
4320/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value suitable for setting the register. */
4321#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET(value) (((value) << 7) & 0x00000080)
4322
4323/*
4324 * Field : Master HS Restart Disabled - abrt_hs_norstrt
4325 *
4326 * The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is
4327 * trying to use the master to transfer data in High Speed mode. Role of i2c:
4328 * Master-Transmitter or Master-Receiver
4329 *
4330 * Field Access Macros:
4331 *
4332 */
4333/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */
4334#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_LSB 8
4335/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */
4336#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_MSB 8
4337/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */
4338#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_WIDTH 1
4339/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */
4340#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET_MSK 0x00000100
4341/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */
4342#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_CLR_MSK 0xfffffeff
4343/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */
4344#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_RESET 0x0
4345/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT field value from a register. */
4346#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_GET(value) (((value) & 0x00000100) >> 8)
4347/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value suitable for setting the register. */
4348#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET(value) (((value) << 8) & 0x00000100)
4349
4350/*
4351 * Field : Master Abort START No Restart - abrt_sbyte_norstrt
4352 *
4353 * To clear Bit 9, the source of then abrt_sbyte_norstrt must be fixed first;
4354 * restart must be enabled (ic_con[5]=1), the SPECIAL bit must be cleared
4355 * (ic_tar[11]), or the GC_OR_START bit must be cleared (ic_tar[10]). Once the
4356 * source of the abrt_sbyte_norstrt is fixed, then this bit can be cleared in the
4357 * same manner as other bits in this register. If the source of the
4358 * abrt_sbyte_norstrt is not fixed before attempting to clear this bit, bit 9
4359 * clears for one cycle and then gets reasserted. 1: The restart is disabled
4360 * (IC_RESTART_EN bit (ic_con[5]) =0) and the user is trying to send a START Byte.
4361 * Role of I2C: Master
4362 *
4363 * Field Access Macros:
4364 *
4365 */
4366/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */
4367#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_LSB 9
4368/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */
4369#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_MSB 9
4370/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */
4371#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_WIDTH 1
4372/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */
4373#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET_MSK 0x00000200
4374/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */
4375#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_CLR_MSK 0xfffffdff
4376/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */
4377#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_RESET 0x0
4378/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT field value from a register. */
4379#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_GET(value) (((value) & 0x00000200) >> 9)
4380/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value suitable for setting the register. */
4381#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET(value) (((value) << 9) & 0x00000200)
4382
4383/*
4384 * Field : Master Abort 10 Bit No Restart - abrt_10b_rd_norstrt
4385 *
4386 * The restart is disabled (ic_restart_en bit (ic_con[5]) =0) and the master sends
4387 * a read command in 10-bit addressing mode. Role of I2C: Master-Receiver
4388 *
4389 * Field Access Macros:
4390 *
4391 */
4392/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */
4393#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_LSB 10
4394/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */
4395#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_MSB 10
4396/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */
4397#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_WIDTH 1
4398/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */
4399#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET_MSK 0x00000400
4400/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */
4401#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_CLR_MSK 0xfffffbff
4402/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */
4403#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_RESET 0x0
4404/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT field value from a register. */
4405#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_GET(value) (((value) & 0x00000400) >> 10)
4406/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value suitable for setting the register. */
4407#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET(value) (((value) << 10) & 0x00000400)
4408
4409/*
4410 * Field : Master Oper Master Dis - abrt_master_dis
4411 *
4412 * User tries to initiate a Master operation with the Master mode disabled. Role of
4413 * I2C: Master-Transmitter or Master-Receiver
4414 *
4415 * Field Access Macros:
4416 *
4417 */
4418/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */
4419#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_LSB 11
4420/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */
4421#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_MSB 11
4422/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */
4423#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_WIDTH 1
4424/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */
4425#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET_MSK 0x00000800
4426/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */
4427#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_CLR_MSK 0xfffff7ff
4428/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */
4429#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_RESET 0x0
4430/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS field value from a register. */
4431#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_GET(value) (((value) & 0x00000800) >> 11)
4432/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value suitable for setting the register. */
4433#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET(value) (((value) << 11) & 0x00000800)
4434
4435/*
4436 * Field : Master Abort Arbitration Lost - arb_lost
4437 *
4438 * Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the
4439 * slave transmitter has lost arbitration. Note: I2C can be both master and slave
4440 * at the same time. Role of i2c: Master-Transmitter or Slave-Transmitter
4441 *
4442 * Field Access Macros:
4443 *
4444 */
4445/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */
4446#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_LSB 12
4447/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */
4448#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_MSB 12
4449/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */
4450#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_WIDTH 1
4451/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */
4452#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET_MSK 0x00001000
4453/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */
4454#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_CLR_MSK 0xffffefff
4455/* The reset value of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */
4456#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_RESET 0x0
4457/* Extracts the ALT_I2C_TX_ABRT_SRC_ARB_LOST field value from a register. */
4458#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_GET(value) (((value) & 0x00001000) >> 12)
4459/* Produces a ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value suitable for setting the register. */
4460#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET(value) (((value) << 12) & 0x00001000)
4461
4462/*
4463 * Field : Slave Abort Flush TXFIFO - abrt_slvflush_txfifo
4464 *
4465 * Slave has received a read command and some data exists in the TX FIFO so the
4466 * slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Role of I2C:
4467 * Slave-Transmitter
4468 *
4469 * Field Access Macros:
4470 *
4471 */
4472/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */
4473#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_LSB 13
4474/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */
4475#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_MSB 13
4476/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */
4477#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_WIDTH 1
4478/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */
4479#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET_MSK 0x00002000
4480/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */
4481#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_CLR_MSK 0xffffdfff
4482/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */
4483#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_RESET 0x0
4484/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO field value from a register. */
4485#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_GET(value) (((value) & 0x00002000) >> 13)
4486/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value suitable for setting the register. */
4487#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET(value) (((value) << 13) & 0x00002000)
4488
4489/*
4490 * Field : Slave Abort Arbitration Lost - abrt_slv_arblost
4491 *
4492 * Slave lost the bus while transmitting data to a remote master.
4493 * IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never
4494 * 'owns' the bus, something could go wrong on the bus. This is a fail safe check.
4495 * For instance, during a data transmission at the low-to-high transition of SCL,
4496 * if what is on the data bus is not what is supposed to be transmitted, then i2c
4497 * no longer own the bus. Role of I2C: Slave-Transmitter
4498 *
4499 * Field Access Macros:
4500 *
4501 */
4502/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */
4503#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_LSB 14
4504/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */
4505#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_MSB 14
4506/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */
4507#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_WIDTH 1
4508/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */
4509#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET_MSK 0x00004000
4510/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */
4511#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_CLR_MSK 0xffffbfff
4512/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */
4513#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_RESET 0x0
4514/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST field value from a register. */
4515#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_GET(value) (((value) & 0x00004000) >> 14)
4516/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value suitable for setting the register. */
4517#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET(value) (((value) << 14) & 0x00004000)
4518
4519/*
4520 * Field : Slave Abort Read TX - abrt_slvrd_intx
4521 *
4522 * When the processor side responds to a slave mode request for data to be
4523 * transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD
4524 * register. Role of I2C: Slave-Transmitter
4525 *
4526 * Field Access Macros:
4527 *
4528 */
4529/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */
4530#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_LSB 15
4531/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */
4532#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_MSB 15
4533/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */
4534#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_WIDTH 1
4535/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */
4536#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET_MSK 0x00008000
4537/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */
4538#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_CLR_MSK 0xffff7fff
4539/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */
4540#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_RESET 0x0
4541/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX field value from a register. */
4542#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_GET(value) (((value) & 0x00008000) >> 15)
4543/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value suitable for setting the register. */
4544#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET(value) (((value) << 15) & 0x00008000)
4545
4546#ifndef __ASSEMBLY__
4547/*
4548 * WARNING: The C register and register group struct declarations are provided for
4549 * convenience and illustrative purposes. They should, however, be used with
4550 * caution as the C language standard provides no guarantees about the alignment or
4551 * atomicity of device memory accesses. The recommended practice for writing
4552 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4553 * alt_write_word() functions.
4554 *
4555 * The struct declaration for register ALT_I2C_TX_ABRT_SRC.
4556 */
4557 struct ALT_I2C_TX_ABRT_SRC_s
4558{
4559 uint32_t abrt_7b_addr_noack : 1; /* Master Abort 7 Bit Address */
4560 uint32_t abrt_10addr1_noack : 1; /* Master Abort 10 Bit Address Byte 1 */
4561 uint32_t abrt_10addr2_noack : 1; /* Master Abort 10 Bit Address Byte 2 */
4562 uint32_t abrt_txdata_noack : 1; /* Master Abort TX Noack Bit */
4563 uint32_t abrt_gcall_noack : 1; /* Master Abort GC Noack Bit */
4564 uint32_t abrt_gcall_read : 1; /* Master Abort GC Read Bit */
4565 uint32_t abrt_hs_ackdet : 1; /* Master HS MC Ack */
4566 uint32_t abrt_sbyte_ackdet : 1; /* Master Abort START Byte */
4567 uint32_t abrt_hs_norstrt : 1; /* Master HS Restart Disabled */
4568 uint32_t abrt_sbyte_norstrt : 1; /* Master Abort START No Restart */
4569 uint32_t abrt_10b_rd_norstrt : 1; /* Master Abort 10 Bit No Restart */
4570 uint32_t abrt_master_dis : 1; /* Master Oper Master Dis */
4571 uint32_t arb_lost : 1; /* Master Abort Arbitration Lost */
4572 uint32_t abrt_slvflush_txfifo : 1; /* Slave Abort Flush TXFIFO */
4573 uint32_t abrt_slv_arblost : 1; /* Slave Abort Arbitration Lost */
4574 uint32_t abrt_slvrd_intx : 1; /* Slave Abort Read TX */
4575 uint32_t : 16; /* *UNDEFINED* */
4576};
4577
4578/* The typedef declaration for register ALT_I2C_TX_ABRT_SRC. */
4579typedef volatile struct ALT_I2C_TX_ABRT_SRC_s ALT_I2C_TX_ABRT_SRC_t;
4580#endif /* __ASSEMBLY__ */
4581
4582/* The byte offset of the ALT_I2C_TX_ABRT_SRC register from the beginning of the component. */
4583#define ALT_I2C_TX_ABRT_SRC_OFST 0x80
4584/* The address of the ALT_I2C_TX_ABRT_SRC register. */
4585#define ALT_I2C_TX_ABRT_SRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_ABRT_SRC_OFST))
4586
4587/*
4588 * Register : Generate Slave Data NACK - ic_slv_data_nack_only
4589 *
4590 * The register is used to generate a NACK for the data part of a transfer when i2c
4591 * is acting as a slave-receiver.
4592 *
4593 * Register Layout
4594 *
4595 * Bits | Access | Reset | Description
4596 * :-------|:-------|:------|:------------------
4597 * [0] | RW | 0x0 | Generate Nack Bit
4598 * [31:1] | ??? | 0x0 | *UNDEFINED*
4599 *
4600 */
4601/*
4602 * Field : Generate Nack Bit - nack
4603 *
4604 * This Bit control Nack generation
4605 *
4606 * Field Enumeration Values:
4607 *
4608 * Enum | Value | Description
4609 * :---------------------------------------------|:------|:--------------------------------------
4610 * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE | 0x1 | Generate NACK after data byte receive
4611 * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM | 0x0 | Generate NACK/ACK normally
4612 *
4613 * Field Access Macros:
4614 *
4615 */
4616/*
4617 * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK
4618 *
4619 * Generate NACK after data byte receive
4620 */
4621#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE 0x1
4622/*
4623 * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK
4624 *
4625 * Generate NACK/ACK normally
4626 */
4627#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM 0x0
4628
4629/* The Least Significant Bit (LSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */
4630#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_LSB 0
4631/* The Most Significant Bit (MSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */
4632#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_MSB 0
4633/* The width in bits of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */
4634#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_WIDTH 1
4635/* The mask used to set the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */
4636#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK 0x00000001
4637/* The mask used to clear the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */
4638#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_CLR_MSK 0xfffffffe
4639/* The reset value of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */
4640#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_RESET 0x0
4641/* Extracts the ALT_I2C_SLV_DATA_NACK_ONLY_NACK field value from a register. */
4642#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(value) (((value) & 0x00000001) >> 0)
4643/* Produces a ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value suitable for setting the register. */
4644#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(value) (((value) << 0) & 0x00000001)
4645
4646#ifndef __ASSEMBLY__
4647/*
4648 * WARNING: The C register and register group struct declarations are provided for
4649 * convenience and illustrative purposes. They should, however, be used with
4650 * caution as the C language standard provides no guarantees about the alignment or
4651 * atomicity of device memory accesses. The recommended practice for writing
4652 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4653 * alt_write_word() functions.
4654 *
4655 * The struct declaration for register ALT_I2C_SLV_DATA_NACK_ONLY.
4656 */
4657 struct ALT_I2C_SLV_DATA_NACK_ONLY_s
4658{
4659 uint32_t nack : 1; /* Generate Nack Bit */
4660 uint32_t : 31; /* *UNDEFINED* */
4661};
4662
4663/* The typedef declaration for register ALT_I2C_SLV_DATA_NACK_ONLY. */
4664typedef volatile struct ALT_I2C_SLV_DATA_NACK_ONLY_s ALT_I2C_SLV_DATA_NACK_ONLY_t;
4665#endif /* __ASSEMBLY__ */
4666
4667/* The byte offset of the ALT_I2C_SLV_DATA_NACK_ONLY register from the beginning of the component. */
4668#define ALT_I2C_SLV_DATA_NACK_ONLY_OFST 0x84
4669/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register. */
4670#define ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SLV_DATA_NACK_ONLY_OFST))
4671
4672/*
4673 * Register : DMA Control - ic_dma_cr
4674 *
4675 * The register is used to enable the DMA Controller interface operation. There is
4676 * a separate bit for transmit and receive. This can be programmed regardless of
4677 * the state of IC_ENABLE.
4678 *
4679 * Register Layout
4680 *
4681 * Bits | Access | Reset | Description
4682 * :-------|:-------|:------|:------------------------
4683 * [0] | RW | 0x0 | Receive DMA Enable Bit
4684 * [1] | RW | 0x0 | Transmit DMA Enable Bit
4685 * [31:2] | ??? | 0x0 | *UNDEFINED*
4686 *
4687 */
4688/*
4689 * Field : Receive DMA Enable Bit - rdmae
4690 *
4691 * This bit enables/disables the receive FIFO DMA channel.
4692 *
4693 * Field Enumeration Values:
4694 *
4695 * Enum | Value | Description
4696 * :---------------------------|:------|:--------------------
4697 * ALT_I2C_DMA_CR_RDMAE_E_DIS | 0x0 | Receive DMA disable
4698 * ALT_I2C_DMA_CR_RDMAE_E_EN | 0x1 | Receive DMA enabled
4699 *
4700 * Field Access Macros:
4701 *
4702 */
4703/*
4704 * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE
4705 *
4706 * Receive DMA disable
4707 */
4708#define ALT_I2C_DMA_CR_RDMAE_E_DIS 0x0
4709/*
4710 * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE
4711 *
4712 * Receive DMA enabled
4713 */
4714#define ALT_I2C_DMA_CR_RDMAE_E_EN 0x1
4715
4716/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */
4717#define ALT_I2C_DMA_CR_RDMAE_LSB 0
4718/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */
4719#define ALT_I2C_DMA_CR_RDMAE_MSB 0
4720/* The width in bits of the ALT_I2C_DMA_CR_RDMAE register field. */
4721#define ALT_I2C_DMA_CR_RDMAE_WIDTH 1
4722/* The mask used to set the ALT_I2C_DMA_CR_RDMAE register field value. */
4723#define ALT_I2C_DMA_CR_RDMAE_SET_MSK 0x00000001
4724/* The mask used to clear the ALT_I2C_DMA_CR_RDMAE register field value. */
4725#define ALT_I2C_DMA_CR_RDMAE_CLR_MSK 0xfffffffe
4726/* The reset value of the ALT_I2C_DMA_CR_RDMAE register field. */
4727#define ALT_I2C_DMA_CR_RDMAE_RESET 0x0
4728/* Extracts the ALT_I2C_DMA_CR_RDMAE field value from a register. */
4729#define ALT_I2C_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
4730/* Produces a ALT_I2C_DMA_CR_RDMAE register field value suitable for setting the register. */
4731#define ALT_I2C_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
4732
4733/*
4734 * Field : Transmit DMA Enable Bit - tdmae
4735 *
4736 * This bit enables/disables the transmit FIFO DMA channel.
4737 *
4738 * Field Enumeration Values:
4739 *
4740 * Enum | Value | Description
4741 * :---------------------------|:------|:---------------------
4742 * ALT_I2C_DMA_CR_TDMAE_E_DIS | 0x0 | Transmit DMA disable
4743 * ALT_I2C_DMA_CR_TDMAE_E_EN | 0x1 | Transmit DMA enabled
4744 *
4745 * Field Access Macros:
4746 *
4747 */
4748/*
4749 * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE
4750 *
4751 * Transmit DMA disable
4752 */
4753#define ALT_I2C_DMA_CR_TDMAE_E_DIS 0x0
4754/*
4755 * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE
4756 *
4757 * Transmit DMA enabled
4758 */
4759#define ALT_I2C_DMA_CR_TDMAE_E_EN 0x1
4760
4761/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */
4762#define ALT_I2C_DMA_CR_TDMAE_LSB 1
4763/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */
4764#define ALT_I2C_DMA_CR_TDMAE_MSB 1
4765/* The width in bits of the ALT_I2C_DMA_CR_TDMAE register field. */
4766#define ALT_I2C_DMA_CR_TDMAE_WIDTH 1
4767/* The mask used to set the ALT_I2C_DMA_CR_TDMAE register field value. */
4768#define ALT_I2C_DMA_CR_TDMAE_SET_MSK 0x00000002
4769/* The mask used to clear the ALT_I2C_DMA_CR_TDMAE register field value. */
4770#define ALT_I2C_DMA_CR_TDMAE_CLR_MSK 0xfffffffd
4771/* The reset value of the ALT_I2C_DMA_CR_TDMAE register field. */
4772#define ALT_I2C_DMA_CR_TDMAE_RESET 0x0
4773/* Extracts the ALT_I2C_DMA_CR_TDMAE field value from a register. */
4774#define ALT_I2C_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
4775/* Produces a ALT_I2C_DMA_CR_TDMAE register field value suitable for setting the register. */
4776#define ALT_I2C_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
4777
4778#ifndef __ASSEMBLY__
4779/*
4780 * WARNING: The C register and register group struct declarations are provided for
4781 * convenience and illustrative purposes. They should, however, be used with
4782 * caution as the C language standard provides no guarantees about the alignment or
4783 * atomicity of device memory accesses. The recommended practice for writing
4784 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4785 * alt_write_word() functions.
4786 *
4787 * The struct declaration for register ALT_I2C_DMA_CR.
4788 */
4789 struct ALT_I2C_DMA_CR_s
4790{
4791 uint32_t rdmae : 1; /* Receive DMA Enable Bit */
4792 uint32_t tdmae : 1; /* Transmit DMA Enable Bit */
4793 uint32_t : 30; /* *UNDEFINED* */
4794};
4795
4796/* The typedef declaration for register ALT_I2C_DMA_CR. */
4797typedef volatile struct ALT_I2C_DMA_CR_s ALT_I2C_DMA_CR_t;
4798#endif /* __ASSEMBLY__ */
4799
4800/* The byte offset of the ALT_I2C_DMA_CR register from the beginning of the component. */
4801#define ALT_I2C_DMA_CR_OFST 0x88
4802/* The address of the ALT_I2C_DMA_CR register. */
4803#define ALT_I2C_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_CR_OFST))
4804
4805/*
4806 * Register : DMA Transmit Data Level - ic_dma_tdlr
4807 *
4808 * This register supports DMA Transmit Operation.
4809 *
4810 * Register Layout
4811 *
4812 * Bits | Access | Reset | Description
4813 * :-------|:-------|:------|:----------------------------
4814 * [5:0] | RW | 0x0 | DMA Transmit Data Level Bit
4815 * [31:6] | ??? | 0x0 | *UNDEFINED*
4816 *
4817 */
4818/*
4819 * Field : DMA Transmit Data Level Bit - dmatdl
4820 *
4821 * This bit field controls the level at which a DMA request is made by the transmit
4822 * logic. It is equal to the watermark level; that is, the i2c_dma_tx_req signal is
4823 * generated when the number of valid data entries in the transmit FIFO is equal to
4824 * or below this field value, and TDMAE = 1.
4825 *
4826 * Field Access Macros:
4827 *
4828 */
4829/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */
4830#define ALT_I2C_DMA_TDLR_DMATDL_LSB 0
4831/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */
4832#define ALT_I2C_DMA_TDLR_DMATDL_MSB 5
4833/* The width in bits of the ALT_I2C_DMA_TDLR_DMATDL register field. */
4834#define ALT_I2C_DMA_TDLR_DMATDL_WIDTH 6
4835/* The mask used to set the ALT_I2C_DMA_TDLR_DMATDL register field value. */
4836#define ALT_I2C_DMA_TDLR_DMATDL_SET_MSK 0x0000003f
4837/* The mask used to clear the ALT_I2C_DMA_TDLR_DMATDL register field value. */
4838#define ALT_I2C_DMA_TDLR_DMATDL_CLR_MSK 0xffffffc0
4839/* The reset value of the ALT_I2C_DMA_TDLR_DMATDL register field. */
4840#define ALT_I2C_DMA_TDLR_DMATDL_RESET 0x0
4841/* Extracts the ALT_I2C_DMA_TDLR_DMATDL field value from a register. */
4842#define ALT_I2C_DMA_TDLR_DMATDL_GET(value) (((value) & 0x0000003f) >> 0)
4843/* Produces a ALT_I2C_DMA_TDLR_DMATDL register field value suitable for setting the register. */
4844#define ALT_I2C_DMA_TDLR_DMATDL_SET(value) (((value) << 0) & 0x0000003f)
4845
4846#ifndef __ASSEMBLY__
4847/*
4848 * WARNING: The C register and register group struct declarations are provided for
4849 * convenience and illustrative purposes. They should, however, be used with
4850 * caution as the C language standard provides no guarantees about the alignment or
4851 * atomicity of device memory accesses. The recommended practice for writing
4852 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4853 * alt_write_word() functions.
4854 *
4855 * The struct declaration for register ALT_I2C_DMA_TDLR.
4856 */
4857 struct ALT_I2C_DMA_TDLR_s
4858{
4859 uint32_t dmatdl : 6; /* DMA Transmit Data Level Bit */
4860 uint32_t : 26; /* *UNDEFINED* */
4861};
4862
4863/* The typedef declaration for register ALT_I2C_DMA_TDLR. */
4864typedef volatile struct ALT_I2C_DMA_TDLR_s ALT_I2C_DMA_TDLR_t;
4865#endif /* __ASSEMBLY__ */
4866
4867/* The byte offset of the ALT_I2C_DMA_TDLR register from the beginning of the component. */
4868#define ALT_I2C_DMA_TDLR_OFST 0x8c
4869/* The address of the ALT_I2C_DMA_TDLR register. */
4870#define ALT_I2C_DMA_TDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_TDLR_OFST))
4871
4872/*
4873 * Register : Receive Data Level - ic_dma_rdlr
4874 *
4875 * DMA Control Signals Interface.
4876 *
4877 * Register Layout
4878 *
4879 * Bits | Access | Reset | Description
4880 * :-------|:-------|:------|:------------------------
4881 * [5:0] | RW | 0x0 | Receive Data Level Bits
4882 * [31:6] | ??? | 0x0 | *UNDEFINED*
4883 *
4884 */
4885/*
4886 * Field : Receive Data Level Bits - dmardl
4887 *
4888 * This bit field controls the level at which a DMA request is made by the receive
4889 * logic. The watermark level \= DMARDL+1; that is, dma_rx_req is generated when
4890 * the number of valid data entries in the receive FIFO is equal to or more than
4891 * this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then
4892 * dma_rx_req is asserted when or more data entries are present in the receive
4893 * FIFO.
4894 *
4895 * Field Access Macros:
4896 *
4897 */
4898/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */
4899#define ALT_I2C_DMA_RDLR_DMARDL_LSB 0
4900/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */
4901#define ALT_I2C_DMA_RDLR_DMARDL_MSB 5
4902/* The width in bits of the ALT_I2C_DMA_RDLR_DMARDL register field. */
4903#define ALT_I2C_DMA_RDLR_DMARDL_WIDTH 6
4904/* The mask used to set the ALT_I2C_DMA_RDLR_DMARDL register field value. */
4905#define ALT_I2C_DMA_RDLR_DMARDL_SET_MSK 0x0000003f
4906/* The mask used to clear the ALT_I2C_DMA_RDLR_DMARDL register field value. */
4907#define ALT_I2C_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0
4908/* The reset value of the ALT_I2C_DMA_RDLR_DMARDL register field. */
4909#define ALT_I2C_DMA_RDLR_DMARDL_RESET 0x0
4910/* Extracts the ALT_I2C_DMA_RDLR_DMARDL field value from a register. */
4911#define ALT_I2C_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0)
4912/* Produces a ALT_I2C_DMA_RDLR_DMARDL register field value suitable for setting the register. */
4913#define ALT_I2C_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f)
4914
4915#ifndef __ASSEMBLY__
4916/*
4917 * WARNING: The C register and register group struct declarations are provided for
4918 * convenience and illustrative purposes. They should, however, be used with
4919 * caution as the C language standard provides no guarantees about the alignment or
4920 * atomicity of device memory accesses. The recommended practice for writing
4921 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4922 * alt_write_word() functions.
4923 *
4924 * The struct declaration for register ALT_I2C_DMA_RDLR.
4925 */
4926 struct ALT_I2C_DMA_RDLR_s
4927{
4928 uint32_t dmardl : 6; /* Receive Data Level Bits */
4929 uint32_t : 26; /* *UNDEFINED* */
4930};
4931
4932/* The typedef declaration for register ALT_I2C_DMA_RDLR. */
4933typedef volatile struct ALT_I2C_DMA_RDLR_s ALT_I2C_DMA_RDLR_t;
4934#endif /* __ASSEMBLY__ */
4935
4936/* The byte offset of the ALT_I2C_DMA_RDLR register from the beginning of the component. */
4937#define ALT_I2C_DMA_RDLR_OFST 0x90
4938/* The address of the ALT_I2C_DMA_RDLR register. */
4939#define ALT_I2C_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_RDLR_OFST))
4940
4941/*
4942 * Register : SDA Setup Register - ic_sda_setup
4943 *
4944 * This register controls the amount of time delay (in terms of number of l4_sp_clk
4945 * clock periods) introduced in the rising edge of SCL relative to SDA changing by
4946 * holding SCL low when I2C services a read request while operating as a slave-
4947 * transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the
4948 * I2C Bus Specification. This register must be programmed with a value equal to or
4949 * greater than 2.
4950 *
4951 * Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) *
4952 * (l4_sp_clk)], so if the user requires 10 l4_sp_clk periods of setup time, they
4953 * should program a value of 11. The IC_SDA_SETUP register is only used by the I2C
4954 * when operating as a slave transmitter.
4955 *
4956 * Register Layout
4957 *
4958 * Bits | Access | Reset | Description
4959 * :-------|:-------|:------|:----------------
4960 * [7:0] | RW | 0x64 | SDA Setup Value
4961 * [31:8] | ??? | 0x0 | *UNDEFINED*
4962 *
4963 */
4964/*
4965 * Field : SDA Setup Value - sda_setup
4966 *
4967 * It is recommended that if the required delay is 1000ns, then for an l4_sp_clk
4968 * frequency of 10 MHz, ic_sda_setup should be programmed to a value of 11.
4969 *
4970 * Field Access Macros:
4971 *
4972 */
4973/* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */
4974#define ALT_I2C_SDA_SETUP_SDA_SETUP_LSB 0
4975/* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */
4976#define ALT_I2C_SDA_SETUP_SDA_SETUP_MSB 7
4977/* The width in bits of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */
4978#define ALT_I2C_SDA_SETUP_SDA_SETUP_WIDTH 8
4979/* The mask used to set the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */
4980#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET_MSK 0x000000ff
4981/* The mask used to clear the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */
4982#define ALT_I2C_SDA_SETUP_SDA_SETUP_CLR_MSK 0xffffff00
4983/* The reset value of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */
4984#define ALT_I2C_SDA_SETUP_SDA_SETUP_RESET 0x64
4985/* Extracts the ALT_I2C_SDA_SETUP_SDA_SETUP field value from a register. */
4986#define ALT_I2C_SDA_SETUP_SDA_SETUP_GET(value) (((value) & 0x000000ff) >> 0)
4987/* Produces a ALT_I2C_SDA_SETUP_SDA_SETUP register field value suitable for setting the register. */
4988#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET(value) (((value) << 0) & 0x000000ff)
4989
4990#ifndef __ASSEMBLY__
4991/*
4992 * WARNING: The C register and register group struct declarations are provided for
4993 * convenience and illustrative purposes. They should, however, be used with
4994 * caution as the C language standard provides no guarantees about the alignment or
4995 * atomicity of device memory accesses. The recommended practice for writing
4996 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4997 * alt_write_word() functions.
4998 *
4999 * The struct declaration for register ALT_I2C_SDA_SETUP.
5000 */
5001 struct ALT_I2C_SDA_SETUP_s
5002{
5003 uint32_t sda_setup : 8; /* SDA Setup Value */
5004 uint32_t : 24; /* *UNDEFINED* */
5005};
5006
5007/* The typedef declaration for register ALT_I2C_SDA_SETUP. */
5008typedef volatile struct ALT_I2C_SDA_SETUP_s ALT_I2C_SDA_SETUP_t;
5009#endif /* __ASSEMBLY__ */
5010
5011/* The byte offset of the ALT_I2C_SDA_SETUP register from the beginning of the component. */
5012#define ALT_I2C_SDA_SETUP_OFST 0x94
5013/* The address of the ALT_I2C_SDA_SETUP register. */
5014#define ALT_I2C_SDA_SETUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_SETUP_OFST))
5015
5016/*
5017 * Register : ACK General Call - ic_ack_general_call
5018 *
5019 * The register controls whether i2c responds with a ACK or NACK when it receives
5020 * an I2C General Call address.
5021 *
5022 * Register Layout
5023 *
5024 * Bits | Access | Reset | Description
5025 * :-------|:-------|:------|:---------------------
5026 * [0] | RW | 0x1 | ACK General Call Bit
5027 * [31:1] | ??? | 0x0 | *UNDEFINED*
5028 *
5029 */
5030/*
5031 * Field : ACK General Call Bit - ack_gen_call
5032 *
5033 * When an ACK is asserted, (by asserting i2c_out_data) when it receives a General
5034 * call. Otherwise, i2c responds with a NACK (by negating i2c_out_data).
5035 *
5036 * Field Enumeration Values:
5037 *
5038 * Enum | Value | Description
5039 * :---------------------------------------------|:------|:-------------------------
5040 * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK | 0x0 | I2C responds with a NACK
5041 * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK | 0x1 | I2C responds with an ACK
5042 *
5043 * Field Access Macros:
5044 *
5045 */
5046/*
5047 * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL
5048 *
5049 * I2C responds with a NACK
5050 */
5051#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK 0x0
5052/*
5053 * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL
5054 *
5055 * I2C responds with an ACK
5056 */
5057#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK 0x1
5058
5059/* The Least Significant Bit (LSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
5060#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0
5061/* The Most Significant Bit (MSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
5062#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0
5063/* The width in bits of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
5064#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_WIDTH 1
5065/* The mask used to set the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */
5066#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET_MSK 0x00000001
5067/* The mask used to clear the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */
5068#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_CLR_MSK 0xfffffffe
5069/* The reset value of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
5070#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1
5071/* Extracts the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL field value from a register. */
5072#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
5073/* Produces a ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value suitable for setting the register. */
5074#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
5075
5076#ifndef __ASSEMBLY__
5077/*
5078 * WARNING: The C register and register group struct declarations are provided for
5079 * convenience and illustrative purposes. They should, however, be used with
5080 * caution as the C language standard provides no guarantees about the alignment or
5081 * atomicity of device memory accesses. The recommended practice for writing
5082 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5083 * alt_write_word() functions.
5084 *
5085 * The struct declaration for register ALT_I2C_ACK_GENERAL_CALL.
5086 */
5087 struct ALT_I2C_ACK_GENERAL_CALL_s
5088{
5089 uint32_t ack_gen_call : 1; /* ACK General Call Bit */
5090 uint32_t : 31; /* *UNDEFINED* */
5091};
5092
5093/* The typedef declaration for register ALT_I2C_ACK_GENERAL_CALL. */
5094typedef volatile struct ALT_I2C_ACK_GENERAL_CALL_s ALT_I2C_ACK_GENERAL_CALL_t;
5095#endif /* __ASSEMBLY__ */
5096
5097/* The byte offset of the ALT_I2C_ACK_GENERAL_CALL register from the beginning of the component. */
5098#define ALT_I2C_ACK_GENERAL_CALL_OFST 0x98
5099/* The address of the ALT_I2C_ACK_GENERAL_CALL register. */
5100#define ALT_I2C_ACK_GENERAL_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_ACK_GENERAL_CALL_OFST))
5101
5102/*
5103 * Register : Enable Status Register - ic_enable_status
5104 *
5105 * This register is used to report the i2c hardware status when the IC_ENABLE
5106 * register is set from 1 to 0; that is, when i2c is disabled. If IC_ENABLE has
5107 * been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE
5108 * has been set to 0, bits 2:1 are only valid as soon as bit 0 is read as '0'.
5109 *
5110 * Note: When ic_enable has been written with '0' a delay occurs for bit 0 to be
5111 * read as '0' because disabling the i2c depends on I2C bus activities.
5112 *
5113 * Register Layout
5114 *
5115 * Bits | Access | Reset | Description
5116 * :-------|:-------|:------|:------------------------------
5117 * [0] | R | 0x0 | Enable Status Bit
5118 * [1] | R | 0x0 | Slave Disabled While Busy Bit
5119 * [2] | R | 0x0 | Slave Received Data Lost Bit
5120 * [31:3] | ??? | 0x0 | *UNDEFINED*
5121 *
5122 */
5123/*
5124 * Field : Enable Status Bit - ic_en
5125 *
5126 * This bit always reflects the value driven on the output port ic_en. Not used in
5127 * current application. When read as 1, i2c is deemed to be in an enabled state.
5128 * When read as 0, i2c is deemed completely inactive. NOTE: The CPU can safely read
5129 * this bit anytime. When this bit is read as 0, the CPU can safely read
5130 * slv_rx_data_lost (bit 2) and slv_disabled_while_busy (bit 1).
5131 *
5132 * Field Access Macros:
5133 *
5134 */
5135/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */
5136#define ALT_I2C_EN_STAT_IC_EN_LSB 0
5137/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */
5138#define ALT_I2C_EN_STAT_IC_EN_MSB 0
5139/* The width in bits of the ALT_I2C_EN_STAT_IC_EN register field. */
5140#define ALT_I2C_EN_STAT_IC_EN_WIDTH 1
5141/* The mask used to set the ALT_I2C_EN_STAT_IC_EN register field value. */
5142#define ALT_I2C_EN_STAT_IC_EN_SET_MSK 0x00000001
5143/* The mask used to clear the ALT_I2C_EN_STAT_IC_EN register field value. */
5144#define ALT_I2C_EN_STAT_IC_EN_CLR_MSK 0xfffffffe
5145/* The reset value of the ALT_I2C_EN_STAT_IC_EN register field. */
5146#define ALT_I2C_EN_STAT_IC_EN_RESET 0x0
5147/* Extracts the ALT_I2C_EN_STAT_IC_EN field value from a register. */
5148#define ALT_I2C_EN_STAT_IC_EN_GET(value) (((value) & 0x00000001) >> 0)
5149/* Produces a ALT_I2C_EN_STAT_IC_EN register field value suitable for setting the register. */
5150#define ALT_I2C_EN_STAT_IC_EN_SET(value) (((value) << 0) & 0x00000001)
5151
5152/*
5153 * Field : Slave Disabled While Busy Bit - slv_disabled_while_busy
5154 *
5155 * This bit indicates if a potential or active Slave operation has been aborted due
5156 * to the setting of the ic_enable register from 1 to 0. This bit is set when the
5157 * CPU writes a 0 to the ic_enable register while: (a) I2C is receiving the address
5158 * byte of the Slave-Transmitter operation from a remote master; OR, (b) address
5159 * and data bytes of the Slave-Receiver operation from a remote master. When read
5160 * as 1, I2C is deemed to have forced a NACK during any part of an I2C transfer,
5161 * irrespective of whether the I2C address matches the slave address set in i2c
5162 * (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0
5163 * but has not taken effect. NOTE: If the remote I2C master terminates the transfer
5164 * with a STOP condition before the i2c has a chance to NACK a transfer, and
5165 * IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as
5166 * 0, i2c is deemed to have been disabled when there is master activity, or when
5167 * the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0)
5168 * is read as 0.
5169 *
5170 * Field Access Macros:
5171 *
5172 */
5173/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */
5174#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_LSB 1
5175/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */
5176#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_MSB 1
5177/* The width in bits of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */
5178#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_WIDTH 1
5179/* The mask used to set the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */
5180#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET_MSK 0x00000002
5181/* The mask used to clear the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */
5182#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_CLR_MSK 0xfffffffd
5183/* The reset value of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */
5184#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_RESET 0x0
5185/* Extracts the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY field value from a register. */
5186#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1)
5187/* Produces a ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value suitable for setting the register. */
5188#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002)
5189
5190/*
5191 * Field : Slave Received Data Lost Bit - slv_rx_data_lost
5192 *
5193 * This bit indicates if a Slave-Receiver operation has been aborted with at least
5194 * one data byte received from an I2C transfer due to the setting of IC ENABLE from
5195 * 1 to 0. When read as 1, i2c is deemed to have been actively engaged in an
5196 * aborted I2C transfer (with matching address) and the data phase of the I2C
5197 * transfer has been entered, even though a data byte has been responded with a
5198 * NACK. NOTE: If the remote I2C master terminates the transfer with a STOP
5199 * condition before the i2c has a chance to NACK a transfer, and ic_enable has been
5200 * set to 0, then this bit is also set to 1. When read as 0, i2c is deemed to have
5201 * been disabled without being actively involved in the data phase of a Slave-
5202 * Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is
5203 * read as 0.
5204 *
5205 * Field Access Macros:
5206 *
5207 */
5208/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */
5209#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_LSB 2
5210/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */
5211#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_MSB 2
5212/* The width in bits of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */
5213#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_WIDTH 1
5214/* The mask used to set the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */
5215#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET_MSK 0x00000004
5216/* The mask used to clear the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */
5217#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb
5218/* The reset value of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */
5219#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_RESET 0x0
5220/* Extracts the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST field value from a register. */
5221#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2)
5222/* Produces a ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value suitable for setting the register. */
5223#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004)
5224
5225#ifndef __ASSEMBLY__
5226/*
5227 * WARNING: The C register and register group struct declarations are provided for
5228 * convenience and illustrative purposes. They should, however, be used with
5229 * caution as the C language standard provides no guarantees about the alignment or
5230 * atomicity of device memory accesses. The recommended practice for writing
5231 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5232 * alt_write_word() functions.
5233 *
5234 * The struct declaration for register ALT_I2C_EN_STAT.
5235 */
5236 struct ALT_I2C_EN_STAT_s
5237{
5238 const uint32_t ic_en : 1; /* Enable Status Bit */
5239 const uint32_t slv_disabled_while_busy : 1; /* Slave Disabled While Busy Bit */
5240 const uint32_t slv_rx_data_lost : 1; /* Slave Received Data Lost Bit */
5241 uint32_t : 29; /* *UNDEFINED* */
5242};
5243
5244/* The typedef declaration for register ALT_I2C_EN_STAT. */
5245typedef volatile struct ALT_I2C_EN_STAT_s ALT_I2C_EN_STAT_t;
5246#endif /* __ASSEMBLY__ */
5247
5248/* The byte offset of the ALT_I2C_EN_STAT register from the beginning of the component. */
5249#define ALT_I2C_EN_STAT_OFST 0x9c
5250/* The address of the ALT_I2C_EN_STAT register. */
5251#define ALT_I2C_EN_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_STAT_OFST))
5252
5253/*
5254 * Register : SS and FS Spike Suppression Limit Register - ic_fs_spklen
5255 *
5256 * This register is used to store the duration, measured in ic_clk cycles, of the
5257 * longest spike that is filtered out by the spike suppression logic when the
5258 * component is operating in SS or FS modes.
5259 *
5260 * Register Layout
5261 *
5262 * Bits | Access | Reset | Description
5263 * :-------|:-------|:------|:---------------------------------
5264 * [7:0] | RW | 0x2 | Spike Suppression Limit Register
5265 * [31:8] | ??? | 0x0 | *UNDEFINED*
5266 *
5267 */
5268/*
5269 * Field : Spike Suppression Limit Register - spklen
5270 *
5271 * This register must be set before any I2C bus transaction can take place to
5272 * ensure stable operation. This register sets the duration, measured in ic_clk
5273 * cycles, of the longest spike in the SCL or SDA lines that are filtered out by
5274 * the spike suppression logic. This register can be written only when the I2C
5275 * interface is disabled, which corresponds to the IC_ENABLE register being set to
5276 * 0. Writes at other times have no effect. The minimum valid value is 1; hardware
5277 * prevents values less than this being written, and if attempted results in 2
5278 * being set.
5279 *
5280 * Field Access Macros:
5281 *
5282 */
5283/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */
5284#define ALT_I2C_FS_SPKLEN_SPKLEN_LSB 0
5285/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */
5286#define ALT_I2C_FS_SPKLEN_SPKLEN_MSB 7
5287/* The width in bits of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */
5288#define ALT_I2C_FS_SPKLEN_SPKLEN_WIDTH 8
5289/* The mask used to set the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */
5290#define ALT_I2C_FS_SPKLEN_SPKLEN_SET_MSK 0x000000ff
5291/* The mask used to clear the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */
5292#define ALT_I2C_FS_SPKLEN_SPKLEN_CLR_MSK 0xffffff00
5293/* The reset value of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */
5294#define ALT_I2C_FS_SPKLEN_SPKLEN_RESET 0x2
5295/* Extracts the ALT_I2C_FS_SPKLEN_SPKLEN field value from a register. */
5296#define ALT_I2C_FS_SPKLEN_SPKLEN_GET(value) (((value) & 0x000000ff) >> 0)
5297/* Produces a ALT_I2C_FS_SPKLEN_SPKLEN register field value suitable for setting the register. */
5298#define ALT_I2C_FS_SPKLEN_SPKLEN_SET(value) (((value) << 0) & 0x000000ff)
5299
5300#ifndef __ASSEMBLY__
5301/*
5302 * WARNING: The C register and register group struct declarations are provided for
5303 * convenience and illustrative purposes. They should, however, be used with
5304 * caution as the C language standard provides no guarantees about the alignment or
5305 * atomicity of device memory accesses. The recommended practice for writing
5306 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5307 * alt_write_word() functions.
5308 *
5309 * The struct declaration for register ALT_I2C_FS_SPKLEN.
5310 */
5311 struct ALT_I2C_FS_SPKLEN_s
5312{
5313 uint32_t spklen : 8; /* Spike Suppression Limit Register */
5314 uint32_t : 24; /* *UNDEFINED* */
5315};
5316
5317/* The typedef declaration for register ALT_I2C_FS_SPKLEN. */
5318typedef volatile struct ALT_I2C_FS_SPKLEN_s ALT_I2C_FS_SPKLEN_t;
5319#endif /* __ASSEMBLY__ */
5320
5321/* The byte offset of the ALT_I2C_FS_SPKLEN register from the beginning of the component. */
5322#define ALT_I2C_FS_SPKLEN_OFST 0xa0
5323/* The address of the ALT_I2C_FS_SPKLEN register. */
5324#define ALT_I2C_FS_SPKLEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SPKLEN_OFST))
5325
5326/*
5327 * Register : Component Parameter Register 1 - ic_comp_param_1
5328 *
5329 * This is a constant read-only register that contains encoded information about
5330 * the component's parameter settings.
5331 *
5332 * Register Layout
5333 *
5334 * Bits | Access | Reset | Description
5335 * :--------|:-------|:------|:------------------------
5336 * [1:0] | R | 0x2 | APB Data Width Register
5337 * [3:2] | R | 0x2 | Max Speed Mode
5338 * [4] | R | 0x0 | CNT Registers Access
5339 * [5] | R | 0x1 | Intr IO
5340 * [6] | R | 0x1 | Has DMA
5341 * [7] | R | 0x1 | Add Encoded Params
5342 * [15:8] | R | 0x3f | Rx Buffer Depth
5343 * [23:16] | R | 0x3f | Tx Buffer Depth
5344 * [31:24] | ??? | 0x0 | *UNDEFINED*
5345 *
5346 */
5347/*
5348 * Field : APB Data Width Register - apb_data_width
5349 *
5350 * Sets the APB Data Width.
5351 *
5352 * Field Enumeration Values:
5353 *
5354 * Enum | Value | Description
5355 * :--------------------------------------------------|:------|:--------------------------
5356 * ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width is 32 Bits
5357 *
5358 * Field Access Macros:
5359 *
5360 */
5361/*
5362 * Enumerated value for register field ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH
5363 *
5364 * APB Data Width is 32 Bits
5365 */
5366#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2
5367
5368/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */
5369#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0
5370/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */
5371#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1
5372/* The width in bits of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */
5373#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2
5374/* The mask used to set the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */
5375#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000003
5376/* The mask used to clear the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */
5377#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc
5378/* The reset value of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */
5379#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2
5380/* Extracts the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH field value from a register. */
5381#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
5382/* Produces a ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value suitable for setting the register. */
5383#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
5384
5385/*
5386 * Field : Max Speed Mode - max_speed_mode
5387 *
5388 * The value of this field determines the maximum i2c bus interface speed.
5389 *
5390 * Field Enumeration Values:
5391 *
5392 * Enum | Value | Description
5393 * :------------------------------------------|:------|:-----------------------
5394 * ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST | 0x2 | Fast Mode (400 kbit/s)
5395 *
5396 * Field Access Macros:
5397 *
5398 */
5399/*
5400 * Enumerated value for register field ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD
5401 *
5402 * Fast Mode (400 kbit/s)
5403 */
5404#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST 0x2
5405
5406/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */
5407#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_LSB 2
5408/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */
5409#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_MSB 3
5410/* The width in bits of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */
5411#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_WIDTH 2
5412/* The mask used to set the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */
5413#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET_MSK 0x0000000c
5414/* The mask used to clear the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */
5415#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_CLR_MSK 0xfffffff3
5416/* The reset value of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */
5417#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_RESET 0x2
5418/* Extracts the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD field value from a register. */
5419#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_GET(value) (((value) & 0x0000000c) >> 2)
5420/* Produces a ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value suitable for setting the register. */
5421#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET(value) (((value) << 2) & 0x0000000c)
5422
5423/*
5424 * Field : CNT Registers Access - hc_count_values
5425 *
5426 * This makes the *CNT registers readable and writable.
5427 *
5428 * Field Enumeration Values:
5429 *
5430 * Enum | Value | Description
5431 * :--------------------------------------------|:------|:--------------------------
5432 * ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR | 0x0 | *CNT registers read/write
5433 *
5434 * Field Access Macros:
5435 *
5436 */
5437/*
5438 * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES
5439 *
5440 * * CNT registers read/write
5441 */
5442#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR 0x0
5443
5444/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */
5445#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4
5446/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */
5447#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4
5448/* The width in bits of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */
5449#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH 1
5450/* The mask used to set the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */
5451#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK 0x00000010
5452/* The mask used to clear the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */
5453#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK 0xffffffef
5454/* The reset value of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */
5455#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0
5456/* Extracts the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES field value from a register. */
5457#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_GET(value) (((value) & 0x00000010) >> 4)
5458/* Produces a ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value suitable for setting the register. */
5459#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET(value) (((value) << 4) & 0x00000010)
5460
5461/*
5462 * Field : Intr IO - intr_io
5463 *
5464 * All interrupt sources are combined in to a single output.
5465 *
5466 * Field Enumeration Values:
5467 *
5468 * Enum | Value | Description
5469 * :----------------------------------------|:------|:--------------------------
5470 * ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED | 0x1 | Combined Interrupt Output
5471 *
5472 * Field Access Macros:
5473 *
5474 */
5475/*
5476 * Enumerated value for register field ALT_I2C_COMP_PARAM_1_INTR_IO
5477 *
5478 * Combined Interrupt Output
5479 */
5480#define ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1
5481
5482/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */
5483#define ALT_I2C_COMP_PARAM_1_INTR_IO_LSB 5
5484/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */
5485#define ALT_I2C_COMP_PARAM_1_INTR_IO_MSB 5
5486/* The width in bits of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */
5487#define ALT_I2C_COMP_PARAM_1_INTR_IO_WIDTH 1
5488/* The mask used to set the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */
5489#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET_MSK 0x00000020
5490/* The mask used to clear the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */
5491#define ALT_I2C_COMP_PARAM_1_INTR_IO_CLR_MSK 0xffffffdf
5492/* The reset value of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */
5493#define ALT_I2C_COMP_PARAM_1_INTR_IO_RESET 0x1
5494/* Extracts the ALT_I2C_COMP_PARAM_1_INTR_IO field value from a register. */
5495#define ALT_I2C_COMP_PARAM_1_INTR_IO_GET(value) (((value) & 0x00000020) >> 5)
5496/* Produces a ALT_I2C_COMP_PARAM_1_INTR_IO register field value suitable for setting the register. */
5497#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET(value) (((value) << 5) & 0x00000020)
5498
5499/*
5500 * Field : Has DMA - has_dma
5501 *
5502 * This configures the inclusion of DMA handshaking interface signals.
5503 *
5504 * Field Enumeration Values:
5505 *
5506 * Enum | Value | Description
5507 * :---------------------------------------|:------|:------------
5508 * ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT | 0x1 | Has DMA
5509 *
5510 * Field Access Macros:
5511 *
5512 */
5513/*
5514 * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HAS_DMA
5515 *
5516 * Has DMA
5517 */
5518#define ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT 0x1
5519
5520/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */
5521#define ALT_I2C_COMP_PARAM_1_HAS_DMA_LSB 6
5522/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */
5523#define ALT_I2C_COMP_PARAM_1_HAS_DMA_MSB 6
5524/* The width in bits of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */
5525#define ALT_I2C_COMP_PARAM_1_HAS_DMA_WIDTH 1
5526/* The mask used to set the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */
5527#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET_MSK 0x00000040
5528/* The mask used to clear the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */
5529#define ALT_I2C_COMP_PARAM_1_HAS_DMA_CLR_MSK 0xffffffbf
5530/* The reset value of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */
5531#define ALT_I2C_COMP_PARAM_1_HAS_DMA_RESET 0x1
5532/* Extracts the ALT_I2C_COMP_PARAM_1_HAS_DMA field value from a register. */
5533#define ALT_I2C_COMP_PARAM_1_HAS_DMA_GET(value) (((value) & 0x00000040) >> 6)
5534/* Produces a ALT_I2C_COMP_PARAM_1_HAS_DMA register field value suitable for setting the register. */
5535#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET(value) (((value) << 6) & 0x00000040)
5536
5537/*
5538 * Field : Add Encoded Params - add_encoded_params
5539 *
5540 * By adding in the encoded parameters, this gives firmware an easy and quick way
5541 * of identifying the DesignWare component within an I/O memory map. Some critical
5542 * design-time options determine how a driver should interact with the peripheral.
5543 * There is a minimal area overhead by including these parameters. Allows a single
5544 * driver to be developed for each component which will be self-configurable.
5545 *
5546 * Field Enumeration Values:
5547 *
5548 * Enum | Value | Description
5549 * :---------------------------------------------------|:------|:-------------------
5550 * ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Add Encoded Params
5551 *
5552 * Field Access Macros:
5553 *
5554 */
5555/*
5556 * Enumerated value for register field ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS
5557 *
5558 * Add Encoded Params
5559 */
5560#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1
5561
5562/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */
5563#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_LSB 7
5564/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */
5565#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_MSB 7
5566/* The width in bits of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */
5567#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_WIDTH 1
5568/* The mask used to set the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */
5569#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET_MSK 0x00000080
5570/* The mask used to clear the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */
5571#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_CLR_MSK 0xffffff7f
5572/* The reset value of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */
5573#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_RESET 0x1
5574/* Extracts the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS field value from a register. */
5575#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00000080) >> 7)
5576/* Produces a ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value suitable for setting the register. */
5577#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET(value) (((value) << 7) & 0x00000080)
5578
5579/*
5580 * Field : Rx Buffer Depth - rx_buffer_depth
5581 *
5582 * Sets Rx FIFO Depth.
5583 *
5584 * Field Enumeration Values:
5585 *
5586 * Enum | Value | Description
5587 * :------------------------------------------------|:------|:-------------------------
5588 * ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Rx Fifo Depth 64 Entries
5589 *
5590 * Field Access Macros:
5591 *
5592 */
5593/*
5594 * Enumerated value for register field ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH
5595 *
5596 * Rx Fifo Depth 64 Entries
5597 */
5598#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES 0x40
5599
5600/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */
5601#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_LSB 8
5602/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */
5603#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_MSB 15
5604/* The width in bits of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */
5605#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_WIDTH 8
5606/* The mask used to set the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */
5607#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET_MSK 0x0000ff00
5608/* The mask used to clear the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */
5609#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_CLR_MSK 0xffff00ff
5610/* The reset value of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */
5611#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_RESET 0x3f
5612/* Extracts the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH field value from a register. */
5613#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_GET(value) (((value) & 0x0000ff00) >> 8)
5614/* Produces a ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value suitable for setting the register. */
5615#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET(value) (((value) << 8) & 0x0000ff00)
5616
5617/*
5618 * Field : Tx Buffer Depth - tx_buffer_depth
5619 *
5620 * Sets Tx FIFO Depth.
5621 *
5622 * Field Enumeration Values:
5623 *
5624 * Enum | Value | Description
5625 * :------------------------------------------------|:------|:---------------------------
5626 * ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Tx Buffer Depth 64 Entries
5627 *
5628 * Field Access Macros:
5629 *
5630 */
5631/*
5632 * Enumerated value for register field ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH
5633 *
5634 * Tx Buffer Depth 64 Entries
5635 */
5636#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES 0x40
5637
5638/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */
5639#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_LSB 16
5640/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */
5641#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_MSB 23
5642/* The width in bits of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */
5643#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_WIDTH 8
5644/* The mask used to set the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */
5645#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET_MSK 0x00ff0000
5646/* The mask used to clear the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */
5647#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_CLR_MSK 0xff00ffff
5648/* The reset value of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */
5649#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_RESET 0x3f
5650/* Extracts the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH field value from a register. */
5651#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_GET(value) (((value) & 0x00ff0000) >> 16)
5652/* Produces a ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value suitable for setting the register. */
5653#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET(value) (((value) << 16) & 0x00ff0000)
5654
5655#ifndef __ASSEMBLY__
5656/*
5657 * WARNING: The C register and register group struct declarations are provided for
5658 * convenience and illustrative purposes. They should, however, be used with
5659 * caution as the C language standard provides no guarantees about the alignment or
5660 * atomicity of device memory accesses. The recommended practice for writing
5661 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5662 * alt_write_word() functions.
5663 *
5664 * The struct declaration for register ALT_I2C_COMP_PARAM_1.
5665 */
5666 struct ALT_I2C_COMP_PARAM_1_s
5667{
5668 const uint32_t apb_data_width : 2; /* APB Data Width Register */
5669 const uint32_t max_speed_mode : 2; /* Max Speed Mode */
5670 const uint32_t hc_count_values : 1; /* CNT Registers Access */
5671 const uint32_t intr_io : 1; /* Intr IO */
5672 const uint32_t has_dma : 1; /* Has DMA */
5673 const uint32_t add_encoded_params : 1; /* Add Encoded Params */
5674 const uint32_t rx_buffer_depth : 8; /* Rx Buffer Depth */
5675 const uint32_t tx_buffer_depth : 8; /* Tx Buffer Depth */
5676 uint32_t : 8; /* *UNDEFINED* */
5677};
5678
5679/* The typedef declaration for register ALT_I2C_COMP_PARAM_1. */
5680typedef volatile struct ALT_I2C_COMP_PARAM_1_s ALT_I2C_COMP_PARAM_1_t;
5681#endif /* __ASSEMBLY__ */
5682
5683/* The byte offset of the ALT_I2C_COMP_PARAM_1 register from the beginning of the component. */
5684#define ALT_I2C_COMP_PARAM_1_OFST 0xf4
5685/* The address of the ALT_I2C_COMP_PARAM_1 register. */
5686#define ALT_I2C_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_PARAM_1_OFST))
5687
5688/*
5689 * Register : Component Version Register - ic_comp_version
5690 *
5691 * Describes the version of the I2C
5692 *
5693 * Register Layout
5694 *
5695 * Bits | Access | Reset | Description
5696 * :-------|:-------|:-----------|:--------------------------
5697 * [31:0] | R | 0x3132302a | Component Parameter Value
5698 *
5699 */
5700/*
5701 * Field : Component Parameter Value - ic_comp_version
5702 *
5703 * Specifies I2C release number (encoded as 4 ASCII characters)
5704 *
5705 * Field Enumeration Values:
5706 *
5707 * Enum | Value | Description
5708 * :-----------------------------------------|:-----------|:--------------
5709 * ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A | 0x3132302a | Version 1.20a
5710 *
5711 * Field Access Macros:
5712 *
5713 */
5714/*
5715 * Enumerated value for register field ALT_I2C_COMP_VER_IC_COMP_VER
5716 *
5717 * Version 1.20a
5718 */
5719#define ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A 0x3132302a
5720
5721/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */
5722#define ALT_I2C_COMP_VER_IC_COMP_VER_LSB 0
5723/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */
5724#define ALT_I2C_COMP_VER_IC_COMP_VER_MSB 31
5725/* The width in bits of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */
5726#define ALT_I2C_COMP_VER_IC_COMP_VER_WIDTH 32
5727/* The mask used to set the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */
5728#define ALT_I2C_COMP_VER_IC_COMP_VER_SET_MSK 0xffffffff
5729/* The mask used to clear the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */
5730#define ALT_I2C_COMP_VER_IC_COMP_VER_CLR_MSK 0x00000000
5731/* The reset value of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */
5732#define ALT_I2C_COMP_VER_IC_COMP_VER_RESET 0x3132302a
5733/* Extracts the ALT_I2C_COMP_VER_IC_COMP_VER field value from a register. */
5734#define ALT_I2C_COMP_VER_IC_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0)
5735/* Produces a ALT_I2C_COMP_VER_IC_COMP_VER register field value suitable for setting the register. */
5736#define ALT_I2C_COMP_VER_IC_COMP_VER_SET(value) (((value) << 0) & 0xffffffff)
5737
5738#ifndef __ASSEMBLY__
5739/*
5740 * WARNING: The C register and register group struct declarations are provided for
5741 * convenience and illustrative purposes. They should, however, be used with
5742 * caution as the C language standard provides no guarantees about the alignment or
5743 * atomicity of device memory accesses. The recommended practice for writing
5744 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5745 * alt_write_word() functions.
5746 *
5747 * The struct declaration for register ALT_I2C_COMP_VER.
5748 */
5749 struct ALT_I2C_COMP_VER_s
5750{
5751 const uint32_t ic_comp_version : 32; /* Component Parameter Value */
5752};
5753
5754/* The typedef declaration for register ALT_I2C_COMP_VER. */
5755typedef volatile struct ALT_I2C_COMP_VER_s ALT_I2C_COMP_VER_t;
5756#endif /* __ASSEMBLY__ */
5757
5758/* The byte offset of the ALT_I2C_COMP_VER register from the beginning of the component. */
5759#define ALT_I2C_COMP_VER_OFST 0xf8
5760/* The address of the ALT_I2C_COMP_VER register. */
5761#define ALT_I2C_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_VER_OFST))
5762
5763/*
5764 * Register : Component Type Register - ic_comp_type
5765 *
5766 * Describes a unique ASCII value
5767 *
5768 * Register Layout
5769 *
5770 * Bits | Access | Reset | Description
5771 * :-------|:-------|:-----------|:----------------------
5772 * [31:0] | R | 0x44570140 | Component Type Number
5773 *
5774 */
5775/*
5776 * Field : Component Type Number - ic_comp_type
5777 *
5778 * Designware Component Type number = 0x44_57_01_40. This assigned unique hex value
5779 * is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit
5780 * unsigned number.
5781 *
5782 * Field Access Macros:
5783 *
5784 */
5785/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */
5786#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_LSB 0
5787/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */
5788#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_MSB 31
5789/* The width in bits of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */
5790#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_WIDTH 32
5791/* The mask used to set the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */
5792#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET_MSK 0xffffffff
5793/* The mask used to clear the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */
5794#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_CLR_MSK 0x00000000
5795/* The reset value of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */
5796#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140
5797/* Extracts the ALT_I2C_COMP_TYPE_IC_COMP_TYPE field value from a register. */
5798#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0)
5799/* Produces a ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value suitable for setting the register. */
5800#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff)
5801
5802#ifndef __ASSEMBLY__
5803/*
5804 * WARNING: The C register and register group struct declarations are provided for
5805 * convenience and illustrative purposes. They should, however, be used with
5806 * caution as the C language standard provides no guarantees about the alignment or
5807 * atomicity of device memory accesses. The recommended practice for writing
5808 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5809 * alt_write_word() functions.
5810 *
5811 * The struct declaration for register ALT_I2C_COMP_TYPE.
5812 */
5813 struct ALT_I2C_COMP_TYPE_s
5814{
5815 const uint32_t ic_comp_type : 32; /* Component Type Number */
5816};
5817
5818/* The typedef declaration for register ALT_I2C_COMP_TYPE. */
5819typedef volatile struct ALT_I2C_COMP_TYPE_s ALT_I2C_COMP_TYPE_t;
5820#endif /* __ASSEMBLY__ */
5821
5822/* The byte offset of the ALT_I2C_COMP_TYPE register from the beginning of the component. */
5823#define ALT_I2C_COMP_TYPE_OFST 0xfc
5824/* The address of the ALT_I2C_COMP_TYPE register. */
5825#define ALT_I2C_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_TYPE_OFST))
5826
5827#ifndef __ASSEMBLY__
5828/*
5829 * WARNING: The C register and register group struct declarations are provided for
5830 * convenience and illustrative purposes. They should, however, be used with
5831 * caution as the C language standard provides no guarantees about the alignment or
5832 * atomicity of device memory accesses. The recommended practice for writing
5833 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5834 * alt_write_word() functions.
5835 *
5836 * The struct declaration for register group ALT_I2C.
5837 */
5838 struct ALT_I2C_s
5839{
5840 volatile ALT_I2C_CON_t ic_con; /* ALT_I2C_CON */
5841 volatile ALT_I2C_TAR_t ic_tar; /* ALT_I2C_TAR */
5842 volatile ALT_I2C_SAR_t ic_sar; /* ALT_I2C_SAR */
5843 volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
5844 volatile ALT_I2C_DATA_CMD_t ic_data_cmd; /* ALT_I2C_DATA_CMD */
5845 volatile ALT_I2C_SS_SCL_HCNT_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */
5846 volatile ALT_I2C_SS_SCL_LCNT_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */
5847 volatile ALT_I2C_FS_SCL_HCNT_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */
5848 volatile ALT_I2C_FS_SCL_LCNT_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */
5849 volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */
5850 volatile ALT_I2C_INTR_STAT_t ic_intr_stat; /* ALT_I2C_INTR_STAT */
5851 volatile ALT_I2C_INTR_MSK_t ic_intr_mask; /* ALT_I2C_INTR_MSK */
5852 volatile ALT_I2C_RAW_INTR_STAT_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */
5853 volatile ALT_I2C_RX_TL_t ic_rx_tl; /* ALT_I2C_RX_TL */
5854 volatile ALT_I2C_TX_TL_t ic_tx_tl; /* ALT_I2C_TX_TL */
5855 volatile ALT_I2C_CLR_INTR_t ic_clr_intr; /* ALT_I2C_CLR_INTR */
5856 volatile ALT_I2C_CLR_RX_UNDER_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */
5857 volatile ALT_I2C_CLR_RX_OVER_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */
5858 volatile ALT_I2C_CLR_TX_OVER_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */
5859 volatile ALT_I2C_CLR_RD_REQ_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */
5860 volatile ALT_I2C_CLR_TX_ABRT_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */
5861 volatile ALT_I2C_CLR_RX_DONE_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */
5862 volatile ALT_I2C_CLR_ACTIVITY_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */
5863 volatile ALT_I2C_CLR_STOP_DET_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */
5864 volatile ALT_I2C_CLR_START_DET_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */
5865 volatile ALT_I2C_CLR_GEN_CALL_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */
5866 volatile ALT_I2C_EN_t ic_enable; /* ALT_I2C_EN */
5867 volatile ALT_I2C_STAT_t ic_status; /* ALT_I2C_STAT */
5868 volatile ALT_I2C_TXFLR_t ic_txflr; /* ALT_I2C_TXFLR */
5869 volatile ALT_I2C_RXFLR_t ic_rxflr; /* ALT_I2C_RXFLR */
5870 volatile ALT_I2C_SDA_HOLD_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */
5871 volatile ALT_I2C_TX_ABRT_SRC_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */
5872 volatile ALT_I2C_SLV_DATA_NACK_ONLY_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */
5873 volatile ALT_I2C_DMA_CR_t ic_dma_cr; /* ALT_I2C_DMA_CR */
5874 volatile ALT_I2C_DMA_TDLR_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */
5875 volatile ALT_I2C_DMA_RDLR_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */
5876 volatile ALT_I2C_SDA_SETUP_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */
5877 volatile ALT_I2C_ACK_GENERAL_CALL_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */
5878 volatile ALT_I2C_EN_STAT_t ic_enable_status; /* ALT_I2C_EN_STAT */
5879 volatile ALT_I2C_FS_SPKLEN_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */
5880 volatile uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */
5881 volatile ALT_I2C_COMP_PARAM_1_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */
5882 volatile ALT_I2C_COMP_VER_t ic_comp_version; /* ALT_I2C_COMP_VER */
5883 volatile ALT_I2C_COMP_TYPE_t ic_comp_type; /* ALT_I2C_COMP_TYPE */
5884};
5885
5886/* The typedef declaration for register group ALT_I2C. */
5887typedef volatile struct ALT_I2C_s ALT_I2C_t;
5888/* The struct declaration for the raw register contents of register group ALT_I2C. */
5889 struct ALT_I2C_raw_s
5890{
5891 volatile uint32_t ic_con; /* ALT_I2C_CON */
5892 volatile uint32_t ic_tar; /* ALT_I2C_TAR */
5893 volatile uint32_t ic_sar; /* ALT_I2C_SAR */
5894 volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
5895 volatile uint32_t ic_data_cmd; /* ALT_I2C_DATA_CMD */
5896 volatile uint32_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */
5897 volatile uint32_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */
5898 volatile uint32_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */
5899 volatile uint32_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */
5900 volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */
5901 volatile uint32_t ic_intr_stat; /* ALT_I2C_INTR_STAT */
5902 volatile uint32_t ic_intr_mask; /* ALT_I2C_INTR_MSK */
5903 volatile uint32_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */
5904 volatile uint32_t ic_rx_tl; /* ALT_I2C_RX_TL */
5905 volatile uint32_t ic_tx_tl; /* ALT_I2C_TX_TL */
5906 volatile uint32_t ic_clr_intr; /* ALT_I2C_CLR_INTR */
5907 volatile uint32_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */
5908 volatile uint32_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */
5909 volatile uint32_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */
5910 volatile uint32_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */
5911 volatile uint32_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */
5912 volatile uint32_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */
5913 volatile uint32_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */
5914 volatile uint32_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */
5915 volatile uint32_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */
5916 volatile uint32_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */
5917 volatile uint32_t ic_enable; /* ALT_I2C_EN */
5918 volatile uint32_t ic_status; /* ALT_I2C_STAT */
5919 volatile uint32_t ic_txflr; /* ALT_I2C_TXFLR */
5920 volatile uint32_t ic_rxflr; /* ALT_I2C_RXFLR */
5921 volatile uint32_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */
5922 volatile uint32_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */
5923 volatile uint32_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */
5924 volatile uint32_t ic_dma_cr; /* ALT_I2C_DMA_CR */
5925 volatile uint32_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */
5926 volatile uint32_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */
5927 volatile uint32_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */
5928 volatile uint32_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */
5929 volatile uint32_t ic_enable_status; /* ALT_I2C_EN_STAT */
5930 volatile uint32_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */
5931 volatile uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */
5932 volatile uint32_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */
5933 volatile uint32_t ic_comp_version; /* ALT_I2C_COMP_VER */
5934 volatile uint32_t ic_comp_type; /* ALT_I2C_COMP_TYPE */
5935};
5936
5937/* The typedef declaration for the raw register contents of register group ALT_I2C. */
5938typedef volatile struct ALT_I2C_raw_s ALT_I2C_raw_t;
5939#endif /* __ASSEMBLY__ */
5940
5941
5942#ifdef __cplusplus
5943}
5944#endif /* __cplusplus */
5945#endif /* __ALTERA_ALT_I2C_H__ */
5946
ALT_I2C_ACK_GENERAL_CALL_s
Definition: alt_i2c.h:5088
ALT_I2C_CLR_ACTIVITY_s
Definition: alt_i2c.h:3146
ALT_I2C_CLR_GEN_CALL_s
Definition: alt_i2c.h:3341
ALT_I2C_CLR_INTR_s
Definition: alt_i2c.h:2684
ALT_I2C_CLR_RD_REQ_s
Definition: alt_i2c.h:2944
ALT_I2C_CLR_RX_DONE_s
Definition: alt_i2c.h:3077
ALT_I2C_CLR_RX_OVER_s
Definition: alt_i2c.h:2814
ALT_I2C_CLR_RX_UNDER_s
Definition: alt_i2c.h:2749
ALT_I2C_CLR_START_DET_s
Definition: alt_i2c.h:3276
ALT_I2C_CLR_STOP_DET_s
Definition: alt_i2c.h:3211
ALT_I2C_CLR_TX_ABRT_s
Definition: alt_i2c.h:3012
ALT_I2C_CLR_TX_OVER_s
Definition: alt_i2c.h:2879
ALT_I2C_COMP_PARAM_1_s
Definition: alt_i2c.h:5667
ALT_I2C_COMP_TYPE_s
Definition: alt_i2c.h:5814
ALT_I2C_COMP_VER_s
Definition: alt_i2c.h:5750
ALT_I2C_CON_s
Definition: alt_i2c.h:390
ALT_I2C_DATA_CMD_s
Definition: alt_i2c.h:936
ALT_I2C_DMA_CR_s
Definition: alt_i2c.h:4790
ALT_I2C_DMA_RDLR_s
Definition: alt_i2c.h:4927
ALT_I2C_DMA_TDLR_s
Definition: alt_i2c.h:4858
ALT_I2C_EN_STAT_s
Definition: alt_i2c.h:5237
ALT_I2C_EN_s
Definition: alt_i2c.h:3485
ALT_I2C_FS_SCL_HCNT_s
Definition: alt_i2c.h:1155
ALT_I2C_FS_SCL_LCNT_s
Definition: alt_i2c.h:1225
ALT_I2C_FS_SPKLEN_s
Definition: alt_i2c.h:5312
ALT_I2C_INTR_MSK_s
Definition: alt_i2c.h:2050
ALT_I2C_INTR_STAT_s
Definition: alt_i2c.h:1633
ALT_I2C_RAW_INTR_STAT_s
Definition: alt_i2c.h:2468
ALT_I2C_RXFLR_s
Definition: alt_i2c.h:3995
ALT_I2C_RX_TL_s
Definition: alt_i2c.h:2548
ALT_I2C_SAR_s
Definition: alt_i2c.h:697
ALT_I2C_SDA_HOLD_s
Definition: alt_i2c.h:4062
ALT_I2C_SDA_SETUP_s
Definition: alt_i2c.h:5002
ALT_I2C_SLV_DATA_NACK_ONLY_s
Definition: alt_i2c.h:4658
ALT_I2C_SS_SCL_HCNT_s
Definition: alt_i2c.h:1013
ALT_I2C_SS_SCL_LCNT_s
Definition: alt_i2c.h:1083
ALT_I2C_STAT_s
Definition: alt_i2c.h:3844
ALT_I2C_TAR_s
Definition: alt_i2c.h:619
ALT_I2C_TXFLR_s
Definition: alt_i2c.h:3923
ALT_I2C_TX_ABRT_SRC_s
Definition: alt_i2c.h:4558
ALT_I2C_TX_TL_s
Definition: alt_i2c.h:2617
ALT_I2C_raw_s
Definition: alt_i2c.h:5890
ALT_I2C_s
Definition: alt_i2c.h:5839