RTEMS: bsps/sh/gensh1/include/sh/sh7_sci.h Source File

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sh7_sci.h
1/*
2 * Bit values for the serial control registers of the Hitachi SH703X
3 *
4 * From Hitachi tutorials
5 *
6 * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
7 * Bernd Becker (becker@faw.uni-ulm.de)
8 *
9 * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 *
15 *
16 * COPYRIGHT (c) 1998.
17 * On-Line Applications Research Corporation (OAR).
18 *
19 * The license and distribution terms for this file may be
20 * found in the file LICENSE in this distribution or at
21 * http://www.rtems.org/license/LICENSE.
22 */
23
24#ifndef _sh7_sci_h
25#define _sh7_sci_h
26
27#include <rtems/score/iosh7032.h>
28
29/*
30 * Serial mode register bits
31 */
32
33#define SCI_SYNC_MODE 0x80
34#define SCI_SEVEN_BIT_DATA 0x40
35#define SCI_PARITY_ON 0x20
36#define SCI_ODD_PARITY 0x10
37#define SCI_STOP_BITS_2 0x08
38#define SCI_ENABLE_MULTIP 0x04
39#define SCI_PHI_64 0x03
40#define SCI_PHI_16 0x02
41#define SCI_PHI_4 0x01
42#define SCI_PHI_0 0x00
43
44/*
45 * Serial register offsets, relative to SCI0_SMR or SCI1_SMR
46 */
47
48#define SCI_SMR 0x00
49#define SCI_BRR 0x01
50#define SCI_SCR 0x02
51#define SCI_TDR 0x03
52#define SCI_SSR 0x04
53#define SCI_RDR 0x05
54
55/*
56 * Serial control register bits
57 */
58#define SCI_TIE 0x80 /* Transmit interrupt enable */
59#define SCI_RIE 0x40 /* Receive interrupt enable */
60#define SCI_TE 0x20 /* Transmit enable */
61#define SCI_RE 0x10 /* Receive enable */
62#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */
63#define SCI_TEIE 0x04 /* Transmit end interrupt enable */
64#define SCI_CKE1 0x02 /* Clock enable 1 */
65#define SCI_CKE0 0x01 /* Clock enable 0 */
66
67/*
68 * Serial status register bits
69 */
70#define SCI_TDRE 0x80 /* Transmit data register empty */
71#define SCI_RDRF 0x40 /* Receive data register full */
72#define SCI_ORER 0x20 /* Overrun error */
73#define SCI_FER 0x10 /* Framing error */
74#define SCI_PER 0x08 /* Parity error */
75#define SCI_TEND 0x04 /* Transmit end */
76#define SCI_MPB 0x02 /* Multiprocessor bit */
77#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */
78
79#endif /* _sh7_sci_h */