RTEMS: bsps/bfin/include/libcpu/ethernetRegs.h Source File

| RTEMS 5.4-rc2

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ethernetRegs.h
1/* Blackfin Ethernet Registers
2 *
3 * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
4 * written by Allan Hessenflow <allanh@kallisti.com>
5 *
6 * The license and distribution terms for this file may be
7 * found in the file LICENSE in this distribution or at
8 * http://www.rtems.org/license/LICENSE.
9 */
10
11#ifndef _ethernetRegs_h_
12#define _ethernetRegs_h_
13
14/* register addresses */
15
16#define EMAC_OPMODE_OFFSET 0x0000
17#define EMAC_ADDRLO_OFFSET 0x0004
18#define EMAC_ADDRHI_OFFSET 0x0008
19#define EMAC_HASHLO_OFFSET 0x000c
20#define EMAC_HASHHI_OFFSET 0x0010
21#define EMAC_STAADD_OFFSET 0x0014
22#define EMAC_STADAT_OFFSET 0x0018
23#define EMAC_FLC_OFFSET 0x001c
24#define EMAC_VLAN1_OFFSET 0x0020
25#define EMAC_VLAN2_OFFSET 0x0024
26#define EMAC_WKUP_CTL_OFFSET 0x002c
27#define EMAC_WKUP_FFMSK0_OFFSET 0x0030
28#define EMAC_WKUP_FFMSK1_OFFSET 0x0034
29#define EMAC_WKUP_FFMSK2_OFFSET 0x0038
30#define EMAC_WKUP_FFMSK3_OFFSET 0x003c
31#define EMAC_WKUP_FFCMD_OFFSET 0x0040
32#define EMAC_WKUP_FFOFF_OFFSET 0x0044
33#define EMAC_WKUP_FFCRC01_OFFSET 0x0048
34#define EMAC_WKUP_FFCRC23_OFFSET 0x004c
35#define EMAC_SYSCTL_OFFSET 0x0060
36#define EMAC_SYSTAT_OFFSET 0x0064
37#define EMAC_RX_STAT_OFFSET 0x0068
38#define EMAC_RX_STKY_OFFSET 0x006c
39#define EMAC_RX_IRQE_OFFSET 0x0070
40#define EMAC_TX_STAT_OFFSET 0x0074
41#define EMAC_TX_STKY_OFFSET 0x0078
42#define EMAC_TX_IRQE_OFFSET 0x007c
43#define EMAC_MMC_CTL_OFFSET 0x0080
44#define EMAC_MMC_RIRQS_OFFSET 0x0084
45#define EMAC_MMC_RIRQE_OFFSET 0x0088
46#define EMAC_MMC_TIRQS_OFFSET 0x008c
47#define EMAC_MMC_TIRQE_OFFSET 0x0090
48
49#define EMAC_RXC_OK_OFFSET 0x0100
50#define EMAC_RXC_FCS_OFFSET 0x0104
51#define EMAC_RXC_ALIGN_OFFSET 0x0108
52#define EMAC_RXC_OCTET_OFFSET 0x010c
53#define EMAC_RXC_DMAOVF_OFFSET 0x0110
54#define EMAC_RXC_UNICST_OFFSET 0x0114
55#define EMAC_RXC_MULTI_OFFSET 0x0118
56#define EMAC_RXC_BROAD_OFFSET 0x011c
57#define EMAC_RXC_LNERRI_OFFSET 0x0120
58#define EMAC_RXC_LNERRO_OFFSET 0x0124
59#define EMAC_RXC_LONG_OFFSET 0x0128
60#define EMAC_RXC_MACCTL_OFFSET 0x012c
61#define EMAC_RXC_OPCODE_OFFSET 0x0130
62#define EMAC_RXC_PAUSE_OFFSET 0x0134
63#define EMAC_RXC_ALLFRM_OFFSET 0x0138
64#define EMAC_RXC_ALLOCT_OFFSET 0x013c
65#define EMAC_RXC_TYPED_OFFSET 0x0140
66#define EMAC_RXC_SHORT_OFFSET 0x0144
67#define EMAC_RXC_EQ64_OFFSET 0x0148
68#define EMAC_RXC_LT128_OFFSET 0x014c
69#define EMAC_RXC_LT256_OFFSET 0x0150
70#define EMAC_RXC_LT512_OFFSET 0x0154
71#define EMAC_RXC_LT1024_OFFSET 0x0158
72#define EMAC_RXC_GE1024_OFFSET 0x015c
73
74#define EMAC_TXC_OK_OFFSET 0x0180
75#define EMAC_TXC_1COL_OFFSET 0x0184
76#define EMAC_TXC_GT1COL_OFFSET 0x0188
77#define EMAC_TXC_OCTET_OFFSET 0x018c
78#define EMAC_TXC_DEFER_OFFSET 0x0190
79#define EMAC_TXC_LATECL_OFFSET 0x0194
80#define EMAC_TXC_XS_COL_OFFSET 0x0198
81#define EMAC_TXC_DMAUND_OFFSET 0x019c
82#define EMAC_TXC_CRSERR_OFFSET 0x01a0
83#define EMAC_TXC_UNICST_OFFSET 0x01a4
84#define EMAC_TXC_MULTI_OFFSET 0x01a8
85#define EMAC_TXC_BROAD_OFFSET 0x01ac
86#define EMAC_TXC_ES_DFR_OFFSET 0x01b0
87#define EMAC_TXC_MACCTL_OFFSET 0x01b4
88#define EMAC_TXC_ALLFRM_OFFSET 0x01b8
89#define EMAC_TXC_ALLOCT_OFFSET 0x01bc
90#define EMAC_TXC_EQ64_OFFSET 0x01c0
91#define EMAC_TXC_LT128_OFFSET 0x01c4
92#define EMAC_TXC_LT256_OFFSET 0x01c8
93#define EMAC_TXC_LT512_OFFSET 0x01cc
94#define EMAC_TXC_LT1024_OFFSET 0x01d0
95#define EMAC_TXC_GE1024_OFFSET 0x01d4
96#define EMAC_TXC_ABORT_OFFSET 0x01d8
97
98
99/* register fields */
100
101#define EMAC_OPMODE_DRO 0x10000000
102#define EMAC_OPMODE_LB 0x08000000
103#define EMAC_OPMODE_FDMODE 0x04000000
104#define EMAC_OPMODE_RMII_10 0x02000000
105#define EMAC_OPMODE_RMII 0x01000000
106#define EMAC_OPMODE_LCTRE 0x00800000
107#define EMAC_OPMODE_DRTY 0x00400000
108#define EMAC_OPMODE_BOLMT_MASK 0x00300000
109#define EMAC_OPMODE_BOLMT_1023 0x00000000
110#define EMAC_OPMODE_BOLMT_255 0x00100000
111#define EMAC_OPMODE_BOLMT_15 0x00200000
112#define EMAC_OPMODE_BOLMT_1 0x00300000
113#define EMAC_OPMODE_DC 0x00080000
114#define EMAC_OPMODE_DTXCRC 0x00040000
115#define EMAC_OPMODE_DTXPAD 0x00020000
116#define EMAC_OPMODE_TE 0x00010000
117#define EMAC_OPMODE_RAF 0x00001000
118#define EMAC_OPMODE_PSF 0x00000800
119#define EMAC_OPMODE_PBF 0x00000400
120#define EMAC_OPMODE_DBF 0x00000200
121#define EMAC_OPMODE_IFE 0x00000100
122#define EMAC_OPMODE_PR 0x00000080
123#define EMAC_OPMODE_PAM 0x00000040
124#define EMAC_OPMODE_HM 0x00000020
125#define EMAC_OPMODE_HU 0x00000010
126#define EMAC_OPMODE_ASTP 0x00000002
127#define EMAC_OPMODE_RE 0x00000001
128
129#define EMAC_STAADD_PHYAD_MASK 0x0000f800
130#define EMAC_STAADD_PHYAD_SHIFT 11
131#define EMAC_STAADD_REGAD_MASK 0x000007c0
132#define EMAC_STAADD_REGAD_SHIFT 6
133#define EMAC_STAADD_STAIE 0x00000008
134#define EMAC_STAADD_STADISPRE 0x00000004
135#define EMAC_STAADD_STAOP 0x00000002
136#define EMAC_STAADD_STABUSY 0x00000001
137
138#define EMAC_FLC_FLCPAUSE_MASK 0xffff0000
139#define EMAC_FLC_FLCPAUSE_SHIFT 16
140#define EMAC_FLC_BKPRSEN 0x00000008
141#define EMAC_FLC_PCF 0x00000004
142#define EMAC_FLC_FLCE 0x00000002
143#define EMAC_FLC_FLCBUSY 0x00000001
144
145#define EMAC_WKUP_CTL_RWKS_MASK 0x00000f00
146#define EMAC_WKUP_CTL_RWKS_SHIFT 8
147#define EMAC_WKUP_CTL_MPKS 0x00000020
148#define EMAC_WKUP_CTL_GUWKE 0x00000008
149#define EMAC_WKUP_CTL_RWKE 0x00000004
150#define EMAC_WKUP_CTL_MPKE 0x00000002
151#define EMAC_WKUP_CTL_CAPWKFRM 0x00000001
152
153#define EMAC_WKUP_FFCMD_3_TYPE 0x08000000
154#define EMAC_WKUP_FFCMD_3_EN 0x01000000
155#define EMAC_WKUP_FFCMD_2_TYPE 0x00080000
156#define EMAC_WKUP_FFCMD_2_EN 0x00010000
157#define EMAC_WKUP_FFCMD_1_TYPE 0x00000800
158#define EMAC_WKUP_FFCMD_1_EN 0x00000100
159#define EMAC_WKUP_FFCMD_0_TYPE 0x00000008
160#define EMAC_WKUP_FFCMD_0_EN 0x00000001
161
162#define EMAC_WKUP_FFOFF_3_MASK 0xff000000
163#define EMAC_WKUP_FFOFF_3_SHIFT 24
164#define EMAC_WKUP_FFOFF_2_MASK 0x00ff0000
165#define EMAC_WKUP_FFOFF_2_SHIFT 16
166#define EMAC_WKUP_FFOFF_1_MASK 0x0000ff00
167#define EMAC_WKUP_FFOFF_1_SHIFT 8
168#define EMAC_WKUP_FFOFF_0_MASK 0x000000ff
169#define EMAC_WKUP_FFOFF_0_SHIFT 0
170
171#define EMAC_WKUP_FFCRC01_1_MASK 0xffff0000
172#define EMAC_WKUP_FFCRC01_1_SHIFT 16
173#define EMAC_WKUP_FFCRC01_0_MASK 0x0000ffff
174#define EMAC_WKUP_FFCRC01_0_SHIFT 0
175
176#define EMAC_WKUP_FFCRC23_3_MASK 0xffff0000
177#define EMAC_WKUP_FFCRC23_3_SHIFT 16
178#define EMAC_WKUP_FFCRC23_2_MASK 0x0000ffff
179#define EMAC_WKUP_FFCRC23_2_SHIFT 0
180
181#define EMAC_SYSCTL_MDCDIV_MASK 0x00003f00
182#define EMAC_SYSCTL_MDCDIV_SHIFT 8
183#define EMAC_SYSCTL_TXDWA 0x00000010
184#define EMAC_SYSCTL_RXCKS 0x00000004
185#define EMAC_SYSCTL_RXDWA 0x00000002
186#define EMAC_SYSCTL_PHYIE 0x00000001
187
188#define EMAC_SYSTAT_STMDONE 0x00000080
189#define EMAC_SYSTAT_TXDMAERR 0x00000040
190#define EMAC_SYSTAT_RXDMAERR 0x00000020
191#define EMAC_SYSTAT_WAKEDET 0x00000010
192#define EMAC_SYSTAT_TXFSINT 0x00000008
193#define EMAC_SYSTAT_RXFSINT 0x00000004
194#define EMAC_SYSTAT_MMCINT 0x00000002
195#define EMAC_SYSTAT_PHYINT 0x00000001
196
197#define EMAC_RX_STAT_RX_ACCEPT 0x80000000
198#define EMAC_RX_STAT_RX_VLAN2 0x40000000
199#define EMAC_RX_STAT_RX_VLAN1 0x20000000
200#define EMAC_RX_STAT_RX_TYPE 0x10000000
201#define EMAC_RX_STAT_RX_UCTL 0x08000000
202#define EMAC_RX_STAT_RX_CTL 0x04000000
203#define EMAC_RX_STAT_RX_BROAD_MULTI_MASK 0x03000000
204#define EMAC_RX_STAT_RX_BROAD_MULTI_ILLEGAL 0x03000000
205#define EMAC_RX_STAT_RX_BROAD_MULTI_BROADCAST 0x02000000
206#define EMAC_RX_STAT_RX_BROAD_MULTI_GROUP 0x01000000
207#define EMAC_RX_STAT_RX_BROAD_MULTI_UNICAST 0x00000000
208#define EMAC_RX_STAT_RX_RANGE 0x00800000
209#define EMAC_RX_STAT_RX_LATE 0x00400000
210#define EMAC_RX_STAT_RX_PHY 0x00200000
211#define EMAC_RX_STAT_RX_DMAO 0x00100000
212#define EMAC_RX_STAT_RX_ADDR 0x00080000
213#define EMAC_RX_STAT_RX_FRAG 0x00040000
214#define EMAC_RX_STAT_RX_LEN 0x00020000
215#define EMAC_RX_STAT_RX_CRC 0x00010000
216#define EMAC_RX_STAT_RX_ALIGN 0x00008000
217#define EMAC_RX_STAT_RX_LONG 0x00004000
218#define EMAC_RX_STAT_RX_OK 0x00002000
219#define EMAC_RX_STAT_RX_COMP 0x00001000
220#define EMAC_RX_STAT_RX_FRLEN_MASK 0x000007ff
221#define EMAC_RX_STAT_RX_FRLEN_SHIFT 0
222
223#define EMAC_RX_STKY_RX_ACCEPT 0x80000000
224#define EMAC_RX_STKY_RX_VLAN2 0x40000000
225#define EMAC_RX_STKY_RX_VLAN1 0x20000000
226#define EMAC_RX_STKY_RX_TYPE 0x10000000
227#define EMAC_RX_STKY_RX_UCTL 0x08000000
228#define EMAC_RX_STKY_RX_CTL 0x04000000
229#define EMAC_RX_STKY_RX_BROAD 0x02000000
230#define EMAC_RX_STKY_RX_MULTI 0x01000000
231#define EMAC_RX_STKY_RX_RANGE 0x00800000
232#define EMAC_RX_STKY_RX_LATE 0x00400000
233#define EMAC_RX_STKY_RX_PHY 0x00200000
234#define EMAC_RX_STKY_RX_DMAO 0x00100000
235#define EMAC_RX_STKY_RX_ADDR 0x00080000
236#define EMAC_RX_STKY_RX_FRAG 0x00040000
237#define EMAC_RX_STKY_RX_LEN 0x00020000
238#define EMAC_RX_STKY_RX_CRC 0x00010000
239#define EMAC_RX_STKY_RX_ALIGN 0x00008000
240#define EMAC_RX_STKY_RX_LONG 0x00004000
241#define EMAC_RX_STKY_RX_OK 0x00002000
242#define EMAC_RX_STKY_RX_COMP 0x00001000
243
244#define EMAC_RX_IRQE_RX_ACCEPT 0x80000000
245#define EMAC_RX_IRQE_RX_VLAN2 0x40000000
246#define EMAC_RX_IRQE_RX_VLAN1 0x20000000
247#define EMAC_RX_IRQE_RX_TYPE 0x10000000
248#define EMAC_RX_IRQE_RX_UCTL 0x08000000
249#define EMAC_RX_IRQE_RX_CTL 0x04000000
250#define EMAC_RX_IRQE_RX_BROAD 0x02000000
251#define EMAC_RX_IRQE_RX_MULTI 0x01000000
252#define EMAC_RX_IRQE_RX_RANGE 0x00800000
253#define EMAC_RX_IRQE_RX_LATE 0x00400000
254#define EMAC_RX_IRQE_RX_PHY 0x00200000
255#define EMAC_RX_IRQE_RX_DMAO 0x00100000
256#define EMAC_RX_IRQE_RX_ADDR 0x00080000
257#define EMAC_RX_IRQE_RX_FRAG 0x00040000
258#define EMAC_RX_IRQE_RX_LEN 0x00020000
259#define EMAC_RX_IRQE_RX_CRC 0x00010000
260#define EMAC_RX_IRQE_RX_ALIGN 0x00008000
261#define EMAC_RX_IRQE_RX_LONG 0x00004000
262#define EMAC_RX_IRQE_RX_OK 0x00002000
263#define EMAC_RX_IRQE_RX_COMP 0x00001000
264
265#define EMAC_TX_STAT_TX_FRLEN_MASK 0x07ff0000
266#define EMAC_TX_STAT_TX_FRLEN_SHIFT 16
267#define EMAC_TX_STAT_TX_RETRY 0x00008000
268#define EMAC_TX_STAT_TX_LOSS 0x00004000
269#define EMAC_TX_STAT_TX_CRS 0x00002000
270#define EMAC_TX_STAT_TX_DEFER 0x00001000
271#define EMAC_TX_STAT_TX_CCNT_MASK 0x00000f00
272#define EMAC_TX_STAT_TX_CCNT_SHIFT 8
273#define EMAC_TX_STAT_TX_MULTI_BROAD_MASK 0x000000c0
274#define EMAC_TX_STAT_TX_MULTI_BROAD_ILLEGAL 0x000000c0
275#define EMAC_TX_STAT_TX_MULTI_BROAD_GROUP 0x00000080
276#define EMAC_TX_STAT_TX_MULTI_BROAD_BROADCAST 0x00000040
277#define EMAC_TX_STAT_TX_MULTI_BROAD_UNICAST 0x00000000
278#define EMAC_TX_STAT_TX_EDEFER 0x00000020
279#define EMAC_TX_STAT_TX_DMAU 0x00000010
280#define EMAC_TX_STAT_TX_LATE 0x00000008
281#define EMAC_TX_STAT_TX_ECOLL 0x00000004
282#define EMAC_TX_STAT_TX_OK 0x00000002
283#define EMAC_TX_STAT_TX_COMP 0x00000001
284
285#define EMAC_TX_STKY_TX_RETRY 0x00008000
286#define EMAC_TX_STKY_TX_LOSS 0x00004000
287#define EMAC_TX_STKY_TX_CRS 0x00002000
288#define EMAC_TX_STKY_TX_DEFER 0x00001000
289#define EMAC_TX_STKY_TX_CCNT_MASK 0x00000f00
290#define EMAC_TX_STKY_TX_CCNT_SHIFT 8
291#define EMAC_TX_STKY_TX_MULTI 0x00000080
292#define EMAC_TX_STKY_TX_BROAD 0x00000040
293#define EMAC_TX_STKY_TX_EDEFER 0x00000020
294#define EMAC_TX_STKY_TX_DMAU 0x00000010
295#define EMAC_TX_STKY_TX_LATE 0x00000008
296#define EMAC_TX_STAT_TX_ECOLL 0x00000004
297#define EMAC_TX_STAT_TX_OK 0x00000002
298#define EMAC_TX_STAT_TX_COMP 0x00000001
299
300#define EMAC_TX_IRQE_TX_RETRY 0x00008000
301#define EMAC_TX_IRQE_TX_LOSS 0x00004000
302#define EMAC_TX_IRQE_TX_CRS 0x00002000
303#define EMAC_TX_IRQE_TX_DEFER 0x00001000
304#define EMAC_TX_IRQE_TX_CCNT_MASK 0x00000f00
305#define EMAC_TX_IRQE_TX_CCNT_SHIFT 8
306#define EMAC_TX_IRQE_TX_MULTI 0x00000080
307#define EMAC_TX_IRQE_TX_BROAD 0x00000040
308#define EMAC_TX_IRQE_TX_EDEFER 0x00000020
309#define EMAC_TX_IRQE_TX_DMAU 0x00000010
310#define EMAC_TX_IRQE_TX_LATE 0x00000008
311#define EMAC_TX_IRQE_TX_ECOLL 0x00000004
312#define EMAC_TX_IRQE_TX_OK 0x00000002
313#define EMAC_TX_IRQE_TX_COMP 0x00000001
314
315#define EMAC_MMC_RIRQS_RX_GE1024_CNT 0x00800000
316#define EMAC_MMC_RIRQS_RX_LT1024_CNT 0x00400000
317#define EMAC_MMC_RIRQS_RX_LT512_CNT 0x00200000
318#define EMAC_MMC_RIRQS_RX_LT256_CNT 0x00100000
319#define EMAC_MMC_RIRQS_RX_LT128_CNT 0x00080000
320#define EMAC_MMC_RIRQS_RX_EQ64_CNT 0x00040000
321#define EMAC_MMC_RIRQS_RX_SHORT_CNT 0x00020000
322#define EMAC_MMC_RIRQS_RX_TYPED_CNT 0x00010000
323#define EMAC_MMC_RIRQS_RX_ALLO_CNT 0x00008000
324#define EMAC_MMC_RIRQS_RX_ALLF_CNT 0x00004000
325#define EMAC_MMC_RIRQS_RX_PAUSE_CNT 0x00002000
326#define EMAC_MMC_RIRQS_RX_OPCODE_CNT 0x00001000
327#define EMAC_MMC_RIRQS_RX_MACCTL_CNT 0x00000800
328#define EMAC_MMC_RIRQS_RX_LONG_CNT 0x00000400
329#define EMAC_MMC_RIRQS_RX_ORL_CNT 0x00000200
330#define EMAC_MMC_RIRQS_RX_IRL_CNT 0x00000100
331#define EMAC_MMC_RIRQS_RX_BROAD_CNT 0x00000080
332#define EMAC_MMC_RIRQS_RX_MULTI_CNT 0x00000040
333#define EMAC_MMC_RIRQS_RX_UNI_CNT 0x00000020
334#define EMAC_MMC_RIRQS_RX_LOST_CNT 0x00000010
335#define EMAC_MMC_RIRQS_RX_OCTET_CNT 0x00000008
336#define EMAC_MMC_RIRQS_RX_ALIGN_CNT 0x00000004
337#define EMAC_MMC_RIRQS_RX_FCS_CNT 0x00000002
338#define EMAC_MMC_RIRQS_RX_OK_CNT 0x00000001
339
340#define EMAC_MMC_RIRQE_RX_GE1024_CNT 0x00800000
341#define EMAC_MMC_RIRQE_RX_LT1024_CNT 0x00400000
342#define EMAC_MMC_RIRQE_RX_LT512_CNT 0x00200000
343#define EMAC_MMC_RIRQE_RX_LT256_CNT 0x00100000
344#define EMAC_MMC_RIRQE_RX_LT128_CNT 0x00080000
345#define EMAC_MMC_RIRQE_RX_EQ64_CNT 0x00040000
346#define EMAC_MMC_RIRQE_RX_SHORT_CNT 0x00020000
347#define EMAC_MMC_RIRQE_RX_TYPED_CNT 0x00010000
348#define EMAC_MMC_RIRQE_RX_ALLO_CNT 0x00008000
349#define EMAC_MMC_RIRQE_RX_ALLF_CNT 0x00004000
350#define EMAC_MMC_RIRQE_RX_PAUSE_CNT 0x00002000
351#define EMAC_MMC_RIRQE_RX_OPCODE_CNT 0x00001000
352#define EMAC_MMC_RIRQE_RX_MACCTL_CNT 0x00000800
353#define EMAC_MMC_RIRQE_RX_LONG_CNT 0x00000400
354#define EMAC_MMC_RIRQE_RX_ORL_CNT 0x00000200
355#define EMAC_MMC_RIRQE_RX_IRL_CNT 0x00000100
356#define EMAC_MMC_RIRQE_RX_BROAD_CNT 0x00000080
357#define EMAC_MMC_RIRQE_RX_MULTI_CNT 0x00000040
358#define EMAC_MMC_RIRQE_RX_UNI_CNT 0x00000020
359#define EMAC_MMC_RIRQE_RX_LOST_CNT 0x00000010
360#define EMAC_MMC_RIRQE_RX_OCTET_CNT 0x00000008
361#define EMAC_MMC_RIRQE_RX_ALIGN_CNT 0x00000004
362#define EMAC_MMC_RIRQE_RX_FCS_CNT 0x00000002
363#define EMAC_MMC_RIRQE_RX_OK_CNT 0x00000001
364
365#define EMAC_MMC_TIRQS_TX_ABORT_CNT 0x00400000
366#define EMAC_MMC_TIRQS_TX_GE1024_CNT 0x00200000
367#define EMAC_MMC_TIRQS_TX_LT1024_CNT 0x00100000
368#define EMAC_MMC_TIRQS_TX_LT512_CNT 0x00080000
369#define EMAC_MMC_TIRQS_TX_LT256_CNT 0x00040000
370#define EMAC_MMC_TIRQS_TX_LT128_CNT 0x00020000
371#define EMAC_MMC_TIRQS_TX_EQ64_CNT 0x00010000
372#define EMAC_MMC_TIRQS_TX_ALLO_CNT 0x00008000
373#define EMAC_MMC_TIRQS_TX_ALLF_CNT 0x00004000
374#define EMAC_MMC_TIRQS_TX_MACCTL_CNT 0x00002000
375#define EMAC_MMC_TIRQS_TX_EXDEF_CNT 0x00001000
376#define EMAC_MMC_TIRQS_TX_BROAD_CNT 0x00000800
377#define EMAC_MMC_TIRQS_TX_MULTI_CNT 0x00000400
378#define EMAC_MMC_TIRQS_TX_UNI_CNT 0x00000200
379#define EMAC_MMC_TIRQS_TX_CRS_CNT 0x00000100
380#define EMAC_MMC_TIRQS_TX_LOST_CNT 0x00000080
381#define EMAC_MMC_TIRQS_TX_ABORTC_CNT 0x00000040
382#define EMAC_MMC_TIRQS_TX_LATE_CNT 0x00000020
383#define EMAC_MMC_TIRQS_TX_DEFER_CNT 0x00000010
384#define EMAC_MMC_TIRQS_TX_OCTET_CNT 0x00000008
385#define EMAC_MMC_TIRQS_TX_MCOLL_CNT 0x00000004
386#define EMAC_MMC_TIRQS_TX_SCOLL_CNT 0x00000002
387#define EMAC_MMC_TIRQS_TX_OK_CNT 0x00000001
388
389#define EMAC_MMC_TIRQE_TX_ABORT_CNT 0x00400000
390#define EMAC_MMC_TIRQE_TX_GE1024_CNT 0x00200000
391#define EMAC_MMC_TIRQE_TX_LT1024_CNT 0x00100000
392#define EMAC_MMC_TIRQE_TX_LT512_CNT 0x00080000
393#define EMAC_MMC_TIRQE_TX_LT256_CNT 0x00040000
394#define EMAC_MMC_TIRQE_TX_LT128_CNT 0x00020000
395#define EMAC_MMC_TIRQE_TX_EQ64_CNT 0x00010000
396#define EMAC_MMC_TIRQE_TX_ALLO_CNT 0x00008000
397#define EMAC_MMC_TIRQE_TX_ALLF_CNT 0x00004000
398#define EMAC_MMC_TIRQE_TX_MACCTL_CNT 0x00002000
399#define EMAC_MMC_TIRQE_TX_EXDEF_CNT 0x00001000
400#define EMAC_MMC_TIRQE_TX_BROAD_CNT 0x00000800
401#define EMAC_MMC_TIRQE_TX_MULTI_CNT 0x00000400
402#define EMAC_MMC_TIRQE_TX_UNI_CNT 0x00000200
403#define EMAC_MMC_TIRQE_TX_CRS_CNT 0x00000100
404#define EMAC_MMC_TIRQE_TX_LOST_CNT 0x00000080
405#define EMAC_MMC_TIRQE_TX_ABORTC_CNT 0x00000040
406#define EMAC_MMC_TIRQE_TX_LATE_CNT 0x00000020
407#define EMAC_MMC_TIRQE_TX_DEFER_CNT 0x00000010
408#define EMAC_MMC_TIRQE_TX_OCTET_CNT 0x00000008
409#define EMAC_MMC_TIRQE_TX_MCOLL_CNT 0x00000004
410#define EMAC_MMC_TIRQE_TX_SCOLL_CNT 0x00000002
411#define EMAC_MMC_TIRQE_TX_OK_CNT 0x00000001
412
413#define EMAC_MMC_CTL_MMCE 0x00000008
414#define EMAC_MMC_CTL_CCOR 0x00000004
415#define EMAC_MMC_CTL_CROLL 0x00000002
416#define EMAC_MMC_CTL_RSTC 0x00000001
417
418
419#endif /* _ethernetRegs_h_ */