RTEMS: bsps/arm/atsam/include/libchip/include/sams70/component/component_pwm.h Source File

| RTEMS 5.4-rc2

Loading...
Searching...
No Matches
component_pwm.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70_PWM_COMPONENT_
31#define _SAMS70_PWM_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __IO uint32_t PWM_CMR;
43 __IO uint32_t PWM_CDTY;
44 __O uint32_t PWM_CDTYUPD;
45 __IO uint32_t PWM_CPRD;
46 __O uint32_t PWM_CPRDUPD;
47 __I uint32_t PWM_CCNT;
48 __IO uint32_t PWM_DT;
49 __O uint32_t PWM_DTUPD;
50} PwmCh_num;
52#define PWMCH_NUM_NUMBER 4
53typedef struct {
54 __IO uint32_t PWM_CLK;
55 __O uint32_t PWM_ENA;
56 __O uint32_t PWM_DIS;
57 __I uint32_t PWM_SR;
58 __O uint32_t PWM_IER1;
59 __O uint32_t PWM_IDR1;
60 __I uint32_t PWM_IMR1;
61 __I uint32_t PWM_ISR1;
62 __IO uint32_t PWM_SCM;
63 __O uint32_t PWM_DMAR;
64 __IO uint32_t PWM_SCUC;
65 __IO uint32_t PWM_SCUP;
66 __O uint32_t PWM_SCUPUPD;
67 __O uint32_t PWM_IER2;
68 __O uint32_t PWM_IDR2;
69 __I uint32_t PWM_IMR2;
70 __I uint32_t PWM_ISR2;
71 __IO uint32_t PWM_OOV;
72 __IO uint32_t PWM_OS;
73 __O uint32_t PWM_OSS;
74 __O uint32_t PWM_OSC;
75 __O uint32_t PWM_OSSUPD;
76 __O uint32_t PWM_OSCUPD;
77 __IO uint32_t PWM_FMR;
78 __I uint32_t PWM_FSR;
79 __O uint32_t PWM_FCR;
80 __IO uint32_t PWM_FPV1;
81 __IO uint32_t PWM_FPE;
82 __I uint32_t Reserved1[3];
83 __IO uint32_t PWM_ELMR[2];
84 __I uint32_t Reserved2[7];
85 __IO uint32_t PWM_SSPR;
86 __O uint32_t PWM_SSPUP;
87 __I uint32_t Reserved3[2];
88 __IO uint32_t PWM_SMMR;
89 __I uint32_t Reserved4[3];
90 __IO uint32_t PWM_FPV2;
91 __I uint32_t Reserved5[8];
92 __O uint32_t PWM_WPCR;
93 __I uint32_t PWM_WPSR;
94 __I uint32_t Reserved6[17];
95 __IO uint32_t PWM_CMPV0;
96 __O uint32_t PWM_CMPVUPD0;
97 __IO uint32_t PWM_CMPM0;
98 __O uint32_t PWM_CMPMUPD0;
99 __IO uint32_t PWM_CMPV1;
100 __O uint32_t PWM_CMPVUPD1;
101 __IO uint32_t PWM_CMPM1;
102 __O uint32_t PWM_CMPMUPD1;
103 __IO uint32_t PWM_CMPV2;
104 __O uint32_t PWM_CMPVUPD2;
105 __IO uint32_t PWM_CMPM2;
106 __O uint32_t PWM_CMPMUPD2;
107 __IO uint32_t PWM_CMPV3;
108 __O uint32_t PWM_CMPVUPD3;
109 __IO uint32_t PWM_CMPM3;
110 __O uint32_t PWM_CMPMUPD3;
111 __IO uint32_t PWM_CMPV4;
112 __O uint32_t PWM_CMPVUPD4;
113 __IO uint32_t PWM_CMPM4;
114 __O uint32_t PWM_CMPMUPD4;
115 __IO uint32_t PWM_CMPV5;
116 __O uint32_t PWM_CMPVUPD5;
117 __IO uint32_t PWM_CMPM5;
118 __O uint32_t PWM_CMPMUPD5;
119 __IO uint32_t PWM_CMPV6;
120 __O uint32_t PWM_CMPVUPD6;
121 __IO uint32_t PWM_CMPM6;
122 __O uint32_t PWM_CMPMUPD6;
123 __IO uint32_t PWM_CMPV7;
124 __O uint32_t PWM_CMPVUPD7;
125 __IO uint32_t PWM_CMPM7;
126 __O uint32_t PWM_CMPMUPD7;
127 __I uint32_t Reserved7[20];
128 PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER];
129 __I uint32_t Reserved8[96];
130 __O uint32_t PWM_CMUPD0;
131 __I uint32_t Reserved9[7];
132 __O uint32_t PWM_CMUPD1;
133 __I uint32_t Reserved10[2];
134 __IO uint32_t PWM_ETRG1;
135 __IO uint32_t PWM_LEBR1;
136 __I uint32_t Reserved11[3];
137 __O uint32_t PWM_CMUPD2;
138 __I uint32_t Reserved12[2];
139 __IO uint32_t PWM_ETRG2;
140 __IO uint32_t PWM_LEBR2;
141 __I uint32_t Reserved13[3];
142 __O uint32_t PWM_CMUPD3;
143} Pwm;
144#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
145/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
146#define PWM_CLK_DIVA_Pos 0
147#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos)
148#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
149#define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0)
150#define PWM_CLK_DIVA_PREA (0x1u << 0)
151#define PWM_CLK_PREA_Pos 8
152#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos)
153#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
154#define PWM_CLK_PREA_CLK (0x0u << 8)
155#define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8)
156#define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8)
157#define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8)
158#define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8)
159#define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8)
160#define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8)
161#define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8)
162#define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8)
163#define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8)
164#define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8)
165#define PWM_CLK_DIVB_Pos 16
166#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos)
167#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
168#define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16)
169#define PWM_CLK_DIVB_PREB (0x1u << 16)
170#define PWM_CLK_PREB_Pos 24
171#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos)
172#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
173#define PWM_CLK_PREB_CLK (0x0u << 24)
174#define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24)
175#define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24)
176#define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24)
177#define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24)
178#define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24)
179#define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24)
180#define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24)
181#define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24)
182#define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24)
183#define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24)
184/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
185#define PWM_ENA_CHID0 (0x1u << 0)
186#define PWM_ENA_CHID1 (0x1u << 1)
187#define PWM_ENA_CHID2 (0x1u << 2)
188#define PWM_ENA_CHID3 (0x1u << 3)
189/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
190#define PWM_DIS_CHID0 (0x1u << 0)
191#define PWM_DIS_CHID1 (0x1u << 1)
192#define PWM_DIS_CHID2 (0x1u << 2)
193#define PWM_DIS_CHID3 (0x1u << 3)
194/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
195#define PWM_SR_CHID0 (0x1u << 0)
196#define PWM_SR_CHID1 (0x1u << 1)
197#define PWM_SR_CHID2 (0x1u << 2)
198#define PWM_SR_CHID3 (0x1u << 3)
199/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
200#define PWM_IER1_CHID0 (0x1u << 0)
201#define PWM_IER1_CHID1 (0x1u << 1)
202#define PWM_IER1_CHID2 (0x1u << 2)
203#define PWM_IER1_CHID3 (0x1u << 3)
204#define PWM_IER1_FCHID0 (0x1u << 16)
205#define PWM_IER1_FCHID1 (0x1u << 17)
206#define PWM_IER1_FCHID2 (0x1u << 18)
207#define PWM_IER1_FCHID3 (0x1u << 19)
208/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
209#define PWM_IDR1_CHID0 (0x1u << 0)
210#define PWM_IDR1_CHID1 (0x1u << 1)
211#define PWM_IDR1_CHID2 (0x1u << 2)
212#define PWM_IDR1_CHID3 (0x1u << 3)
213#define PWM_IDR1_FCHID0 (0x1u << 16)
214#define PWM_IDR1_FCHID1 (0x1u << 17)
215#define PWM_IDR1_FCHID2 (0x1u << 18)
216#define PWM_IDR1_FCHID3 (0x1u << 19)
217/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
218#define PWM_IMR1_CHID0 (0x1u << 0)
219#define PWM_IMR1_CHID1 (0x1u << 1)
220#define PWM_IMR1_CHID2 (0x1u << 2)
221#define PWM_IMR1_CHID3 (0x1u << 3)
222#define PWM_IMR1_FCHID0 (0x1u << 16)
223#define PWM_IMR1_FCHID1 (0x1u << 17)
224#define PWM_IMR1_FCHID2 (0x1u << 18)
225#define PWM_IMR1_FCHID3 (0x1u << 19)
226/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
227#define PWM_ISR1_CHID0 (0x1u << 0)
228#define PWM_ISR1_CHID1 (0x1u << 1)
229#define PWM_ISR1_CHID2 (0x1u << 2)
230#define PWM_ISR1_CHID3 (0x1u << 3)
231#define PWM_ISR1_FCHID0 (0x1u << 16)
232#define PWM_ISR1_FCHID1 (0x1u << 17)
233#define PWM_ISR1_FCHID2 (0x1u << 18)
234#define PWM_ISR1_FCHID3 (0x1u << 19)
235/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
236#define PWM_SCM_SYNC0 (0x1u << 0)
237#define PWM_SCM_SYNC1 (0x1u << 1)
238#define PWM_SCM_SYNC2 (0x1u << 2)
239#define PWM_SCM_SYNC3 (0x1u << 3)
240#define PWM_SCM_UPDM_Pos 16
241#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos)
242#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos)))
243#define PWM_SCM_UPDM_MODE0 (0x0u << 16)
244#define PWM_SCM_UPDM_MODE1 (0x1u << 16)
245#define PWM_SCM_UPDM_MODE2 (0x2u << 16)
246#define PWM_SCM_PTRM (0x1u << 20)
247#define PWM_SCM_PTRCS_Pos 21
248#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos)
249#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
250/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */
251#define PWM_DMAR_DMADUTY_Pos 0
252#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos)
253#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos)))
254/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
255#define PWM_SCUC_UPDULOCK (0x1u << 0)
256/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
257#define PWM_SCUP_UPR_Pos 0
258#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos)
259#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
260#define PWM_SCUP_UPRCNT_Pos 4
261#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos)
262#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
263/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
264#define PWM_SCUPUPD_UPRUPD_Pos 0
265#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos)
266#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
267/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
268#define PWM_IER2_WRDY (0x1u << 0)
269#define PWM_IER2_UNRE (0x1u << 3)
270#define PWM_IER2_CMPM0 (0x1u << 8)
271#define PWM_IER2_CMPM1 (0x1u << 9)
272#define PWM_IER2_CMPM2 (0x1u << 10)
273#define PWM_IER2_CMPM3 (0x1u << 11)
274#define PWM_IER2_CMPM4 (0x1u << 12)
275#define PWM_IER2_CMPM5 (0x1u << 13)
276#define PWM_IER2_CMPM6 (0x1u << 14)
277#define PWM_IER2_CMPM7 (0x1u << 15)
278#define PWM_IER2_CMPU0 (0x1u << 16)
279#define PWM_IER2_CMPU1 (0x1u << 17)
280#define PWM_IER2_CMPU2 (0x1u << 18)
281#define PWM_IER2_CMPU3 (0x1u << 19)
282#define PWM_IER2_CMPU4 (0x1u << 20)
283#define PWM_IER2_CMPU5 (0x1u << 21)
284#define PWM_IER2_CMPU6 (0x1u << 22)
285#define PWM_IER2_CMPU7 (0x1u << 23)
286/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
287#define PWM_IDR2_WRDY (0x1u << 0)
288#define PWM_IDR2_UNRE (0x1u << 3)
289#define PWM_IDR2_CMPM0 (0x1u << 8)
290#define PWM_IDR2_CMPM1 (0x1u << 9)
291#define PWM_IDR2_CMPM2 (0x1u << 10)
292#define PWM_IDR2_CMPM3 (0x1u << 11)
293#define PWM_IDR2_CMPM4 (0x1u << 12)
294#define PWM_IDR2_CMPM5 (0x1u << 13)
295#define PWM_IDR2_CMPM6 (0x1u << 14)
296#define PWM_IDR2_CMPM7 (0x1u << 15)
297#define PWM_IDR2_CMPU0 (0x1u << 16)
298#define PWM_IDR2_CMPU1 (0x1u << 17)
299#define PWM_IDR2_CMPU2 (0x1u << 18)
300#define PWM_IDR2_CMPU3 (0x1u << 19)
301#define PWM_IDR2_CMPU4 (0x1u << 20)
302#define PWM_IDR2_CMPU5 (0x1u << 21)
303#define PWM_IDR2_CMPU6 (0x1u << 22)
304#define PWM_IDR2_CMPU7 (0x1u << 23)
305/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
306#define PWM_IMR2_WRDY (0x1u << 0)
307#define PWM_IMR2_UNRE (0x1u << 3)
308#define PWM_IMR2_CMPM0 (0x1u << 8)
309#define PWM_IMR2_CMPM1 (0x1u << 9)
310#define PWM_IMR2_CMPM2 (0x1u << 10)
311#define PWM_IMR2_CMPM3 (0x1u << 11)
312#define PWM_IMR2_CMPM4 (0x1u << 12)
313#define PWM_IMR2_CMPM5 (0x1u << 13)
314#define PWM_IMR2_CMPM6 (0x1u << 14)
315#define PWM_IMR2_CMPM7 (0x1u << 15)
316#define PWM_IMR2_CMPU0 (0x1u << 16)
317#define PWM_IMR2_CMPU1 (0x1u << 17)
318#define PWM_IMR2_CMPU2 (0x1u << 18)
319#define PWM_IMR2_CMPU3 (0x1u << 19)
320#define PWM_IMR2_CMPU4 (0x1u << 20)
321#define PWM_IMR2_CMPU5 (0x1u << 21)
322#define PWM_IMR2_CMPU6 (0x1u << 22)
323#define PWM_IMR2_CMPU7 (0x1u << 23)
324/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
325#define PWM_ISR2_WRDY (0x1u << 0)
326#define PWM_ISR2_UNRE (0x1u << 3)
327#define PWM_ISR2_CMPM0 (0x1u << 8)
328#define PWM_ISR2_CMPM1 (0x1u << 9)
329#define PWM_ISR2_CMPM2 (0x1u << 10)
330#define PWM_ISR2_CMPM3 (0x1u << 11)
331#define PWM_ISR2_CMPM4 (0x1u << 12)
332#define PWM_ISR2_CMPM5 (0x1u << 13)
333#define PWM_ISR2_CMPM6 (0x1u << 14)
334#define PWM_ISR2_CMPM7 (0x1u << 15)
335#define PWM_ISR2_CMPU0 (0x1u << 16)
336#define PWM_ISR2_CMPU1 (0x1u << 17)
337#define PWM_ISR2_CMPU2 (0x1u << 18)
338#define PWM_ISR2_CMPU3 (0x1u << 19)
339#define PWM_ISR2_CMPU4 (0x1u << 20)
340#define PWM_ISR2_CMPU5 (0x1u << 21)
341#define PWM_ISR2_CMPU6 (0x1u << 22)
342#define PWM_ISR2_CMPU7 (0x1u << 23)
343/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
344#define PWM_OOV_OOVH0 (0x1u << 0)
345#define PWM_OOV_OOVH1 (0x1u << 1)
346#define PWM_OOV_OOVH2 (0x1u << 2)
347#define PWM_OOV_OOVH3 (0x1u << 3)
348#define PWM_OOV_OOVL0 (0x1u << 16)
349#define PWM_OOV_OOVL1 (0x1u << 17)
350#define PWM_OOV_OOVL2 (0x1u << 18)
351#define PWM_OOV_OOVL3 (0x1u << 19)
352/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
353#define PWM_OS_OSH0 (0x1u << 0)
354#define PWM_OS_OSH1 (0x1u << 1)
355#define PWM_OS_OSH2 (0x1u << 2)
356#define PWM_OS_OSH3 (0x1u << 3)
357#define PWM_OS_OSL0 (0x1u << 16)
358#define PWM_OS_OSL1 (0x1u << 17)
359#define PWM_OS_OSL2 (0x1u << 18)
360#define PWM_OS_OSL3 (0x1u << 19)
361/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
362#define PWM_OSS_OSSH0 (0x1u << 0)
363#define PWM_OSS_OSSH1 (0x1u << 1)
364#define PWM_OSS_OSSH2 (0x1u << 2)
365#define PWM_OSS_OSSH3 (0x1u << 3)
366#define PWM_OSS_OSSL0 (0x1u << 16)
367#define PWM_OSS_OSSL1 (0x1u << 17)
368#define PWM_OSS_OSSL2 (0x1u << 18)
369#define PWM_OSS_OSSL3 (0x1u << 19)
370/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
371#define PWM_OSC_OSCH0 (0x1u << 0)
372#define PWM_OSC_OSCH1 (0x1u << 1)
373#define PWM_OSC_OSCH2 (0x1u << 2)
374#define PWM_OSC_OSCH3 (0x1u << 3)
375#define PWM_OSC_OSCL0 (0x1u << 16)
376#define PWM_OSC_OSCL1 (0x1u << 17)
377#define PWM_OSC_OSCL2 (0x1u << 18)
378#define PWM_OSC_OSCL3 (0x1u << 19)
379/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
380#define PWM_OSSUPD_OSSUPH0 (0x1u << 0)
381#define PWM_OSSUPD_OSSUPH1 (0x1u << 1)
382#define PWM_OSSUPD_OSSUPH2 (0x1u << 2)
383#define PWM_OSSUPD_OSSUPH3 (0x1u << 3)
384#define PWM_OSSUPD_OSSUPL0 (0x1u << 16)
385#define PWM_OSSUPD_OSSUPL1 (0x1u << 17)
386#define PWM_OSSUPD_OSSUPL2 (0x1u << 18)
387#define PWM_OSSUPD_OSSUPL3 (0x1u << 19)
388/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
389#define PWM_OSCUPD_OSCUPH0 (0x1u << 0)
390#define PWM_OSCUPD_OSCUPH1 (0x1u << 1)
391#define PWM_OSCUPD_OSCUPH2 (0x1u << 2)
392#define PWM_OSCUPD_OSCUPH3 (0x1u << 3)
393#define PWM_OSCUPD_OSCUPL0 (0x1u << 16)
394#define PWM_OSCUPD_OSCUPL1 (0x1u << 17)
395#define PWM_OSCUPD_OSCUPL2 (0x1u << 18)
396#define PWM_OSCUPD_OSCUPL3 (0x1u << 19)
397/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
398#define PWM_FMR_FPOL_Pos 0
399#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos)
400#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
401#define PWM_FMR_FMOD_Pos 8
402#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos)
403#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
404#define PWM_FMR_FFIL_Pos 16
405#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos)
406#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
407/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
408#define PWM_FSR_FIV_Pos 0
409#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos)
410#define PWM_FSR_FS_Pos 8
411#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos)
412/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
413#define PWM_FCR_FCLR_Pos 0
414#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos)
415#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
416/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */
417#define PWM_FPV1_FPVH0 (0x1u << 0)
418#define PWM_FPV1_FPVH1 (0x1u << 1)
419#define PWM_FPV1_FPVH2 (0x1u << 2)
420#define PWM_FPV1_FPVH3 (0x1u << 3)
421#define PWM_FPV1_FPVL0 (0x1u << 16)
422#define PWM_FPV1_FPVL1 (0x1u << 17)
423#define PWM_FPV1_FPVL2 (0x1u << 18)
424#define PWM_FPV1_FPVL3 (0x1u << 19)
425/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
426#define PWM_FPE_FPE0_Pos 0
427#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos)
428#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
429#define PWM_FPE_FPE1_Pos 8
430#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos)
431#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
432#define PWM_FPE_FPE2_Pos 16
433#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos)
434#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
435#define PWM_FPE_FPE3_Pos 24
436#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos)
437#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
438/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
439#define PWM_ELMR_CSEL0 (0x1u << 0)
440#define PWM_ELMR_CSEL1 (0x1u << 1)
441#define PWM_ELMR_CSEL2 (0x1u << 2)
442#define PWM_ELMR_CSEL3 (0x1u << 3)
443#define PWM_ELMR_CSEL4 (0x1u << 4)
444#define PWM_ELMR_CSEL5 (0x1u << 5)
445#define PWM_ELMR_CSEL6 (0x1u << 6)
446#define PWM_ELMR_CSEL7 (0x1u << 7)
447/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */
448#define PWM_SSPR_SPRD_Pos 0
449#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos)
450#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos)))
451#define PWM_SSPR_SPRDM (0x1u << 24)
452/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */
453#define PWM_SSPUP_SPRDUP_Pos 0
454#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos)
455#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos)))
456/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
457#define PWM_SMMR_GCEN0 (0x1u << 0)
458#define PWM_SMMR_GCEN1 (0x1u << 1)
459#define PWM_SMMR_DOWN0 (0x1u << 16)
460#define PWM_SMMR_DOWN1 (0x1u << 17)
461/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */
462#define PWM_FPV2_FPZH0 (0x1u << 0)
463#define PWM_FPV2_FPZH1 (0x1u << 1)
464#define PWM_FPV2_FPZH2 (0x1u << 2)
465#define PWM_FPV2_FPZH3 (0x1u << 3)
466#define PWM_FPV2_FPZL0 (0x1u << 16)
467#define PWM_FPV2_FPZL1 (0x1u << 17)
468#define PWM_FPV2_FPZL2 (0x1u << 18)
469#define PWM_FPV2_FPZL3 (0x1u << 19)
470/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */
471#define PWM_WPCR_WPCMD_Pos 0
472#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos)
473#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
474#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0)
475#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0)
476#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0)
477#define PWM_WPCR_WPRG0 (0x1u << 2)
478#define PWM_WPCR_WPRG1 (0x1u << 3)
479#define PWM_WPCR_WPRG2 (0x1u << 4)
480#define PWM_WPCR_WPRG3 (0x1u << 5)
481#define PWM_WPCR_WPRG4 (0x1u << 6)
482#define PWM_WPCR_WPRG5 (0x1u << 7)
483#define PWM_WPCR_WPKEY_Pos 8
484#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos)
485#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
486#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8)
487/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */
488#define PWM_WPSR_WPSWS0 (0x1u << 0)
489#define PWM_WPSR_WPSWS1 (0x1u << 1)
490#define PWM_WPSR_WPSWS2 (0x1u << 2)
491#define PWM_WPSR_WPSWS3 (0x1u << 3)
492#define PWM_WPSR_WPSWS4 (0x1u << 4)
493#define PWM_WPSR_WPSWS5 (0x1u << 5)
494#define PWM_WPSR_WPVS (0x1u << 7)
495#define PWM_WPSR_WPHWS0 (0x1u << 8)
496#define PWM_WPSR_WPHWS1 (0x1u << 9)
497#define PWM_WPSR_WPHWS2 (0x1u << 10)
498#define PWM_WPSR_WPHWS3 (0x1u << 11)
499#define PWM_WPSR_WPHWS4 (0x1u << 12)
500#define PWM_WPSR_WPHWS5 (0x1u << 13)
501#define PWM_WPSR_WPVSRC_Pos 16
502#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos)
503/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
504#define PWM_CMPV_CV_Pos 0
505#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos)
506#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
507#define PWM_CMPV_CVM (0x1u << 24)
508/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
509#define PWM_CMPVUPD_CVUPD_Pos 0
510#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos)
511#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
512#define PWM_CMPVUPD_CVMUPD (0x1u << 24)
513/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
514#define PWM_CMPM_CEN (0x1u << 0)
515#define PWM_CMPM_CTR_Pos 4
516#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos)
517#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
518#define PWM_CMPM_CPR_Pos 8
519#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos)
520#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
521#define PWM_CMPM_CPRCNT_Pos 12
522#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos)
523#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
524#define PWM_CMPM_CUPR_Pos 16
525#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos)
526#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
527#define PWM_CMPM_CUPRCNT_Pos 20
528#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos)
529#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
530/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
531#define PWM_CMPMUPD_CENUPD (0x1u << 0)
532#define PWM_CMPMUPD_CTRUPD_Pos 4
533#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos)
534#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
535#define PWM_CMPMUPD_CPRUPD_Pos 8
536#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos)
537#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
538#define PWM_CMPMUPD_CUPRUPD_Pos 16
539#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos)
540#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
541/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
542#define PWM_CMR_CPRE_Pos 0
543#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos)
544#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos)))
545#define PWM_CMR_CPRE_MCK (0x0u << 0)
546#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0)
547#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0)
548#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0)
549#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0)
550#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0)
551#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0)
552#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0)
553#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0)
554#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0)
555#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0)
556#define PWM_CMR_CPRE_CLKA (0xBu << 0)
557#define PWM_CMR_CPRE_CLKB (0xCu << 0)
558#define PWM_CMR_CALG (0x1u << 8)
559#define PWM_CMR_CPOL (0x1u << 9)
560#define PWM_CMR_CES (0x1u << 10)
561#define PWM_CMR_UPDS (0x1u << 11)
562#define PWM_CMR_DPOLI (0x1u << 12)
563#define PWM_CMR_TCTS (0x1u << 13)
564#define PWM_CMR_DTE (0x1u << 16)
565#define PWM_CMR_DTHI (0x1u << 17)
566#define PWM_CMR_DTLI (0x1u << 18)
567#define PWM_CMR_PPM (0x1u << 19)
568/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
569#define PWM_CDTY_CDTY_Pos 0
570#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos)
571#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
572/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
573#define PWM_CDTYUPD_CDTYUPD_Pos 0
574#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos)
575#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
576/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
577#define PWM_CPRD_CPRD_Pos 0
578#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos)
579#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
580/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
581#define PWM_CPRDUPD_CPRDUPD_Pos 0
582#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos)
583#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
584/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
585#define PWM_CCNT_CNT_Pos 0
586#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos)
587/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
588#define PWM_DT_DTH_Pos 0
589#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos)
590#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
591#define PWM_DT_DTL_Pos 16
592#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos)
593#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
594/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
595#define PWM_DTUPD_DTHUPD_Pos 0
596#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos)
597#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
598#define PWM_DTUPD_DTLUPD_Pos 16
599#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos)
600#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
601/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */
602#define PWM_CMUPD0_CPOLUP (0x1u << 9)
603#define PWM_CMUPD0_CPOLINVUP (0x1u << 13)
604/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */
605#define PWM_CMUPD1_CPOLUP (0x1u << 9)
606#define PWM_CMUPD1_CPOLINVUP (0x1u << 13)
607/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */
608#define PWM_ETRG1_MAXCNT_Pos 0
609#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos)
610#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos)))
611#define PWM_ETRG1_TRGMODE_Pos 24
612#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos)
613#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos)))
614#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24)
615#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24)
616#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24)
617#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24)
618#define PWM_ETRG1_TRGEDGE (0x1u << 28)
619#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28)
620#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28)
621#define PWM_ETRG1_TRGFILT (0x1u << 29)
622#define PWM_ETRG1_TRGSRC (0x1u << 30)
623#define PWM_ETRG1_RFEN (0x1u << 31)
624/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */
625#define PWM_LEBR1_LEBDELAY_Pos 0
626#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos)
627#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos)))
628#define PWM_LEBR1_PWMLFEN (0x1u << 16)
629#define PWM_LEBR1_PWMLREN (0x1u << 17)
630#define PWM_LEBR1_PWMHFEN (0x1u << 18)
631#define PWM_LEBR1_PWMHREN (0x1u << 19)
632/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */
633#define PWM_CMUPD2_CPOLUP (0x1u << 9)
634#define PWM_CMUPD2_CPOLINVUP (0x1u << 13)
635/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */
636#define PWM_ETRG2_MAXCNT_Pos 0
637#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos)
638#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos)))
639#define PWM_ETRG2_TRGMODE_Pos 24
640#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos)
641#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos)))
642#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24)
643#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24)
644#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24)
645#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24)
646#define PWM_ETRG2_TRGEDGE (0x1u << 28)
647#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28)
648#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28)
649#define PWM_ETRG2_TRGFILT (0x1u << 29)
650#define PWM_ETRG2_TRGSRC (0x1u << 30)
651#define PWM_ETRG2_RFEN (0x1u << 31)
652/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */
653#define PWM_LEBR2_LEBDELAY_Pos 0
654#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos)
655#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos)))
656#define PWM_LEBR2_PWMLFEN (0x1u << 16)
657#define PWM_LEBR2_PWMLREN (0x1u << 17)
658#define PWM_LEBR2_PWMHFEN (0x1u << 18)
659#define PWM_LEBR2_PWMHREN (0x1u << 19)
660/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */
661#define PWM_CMUPD3_CPOLUP (0x1u << 9)
662#define PWM_CMUPD3_CPOLINVUP (0x1u << 13)
665
666
667#endif /* _SAMS70_PWM_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
PwmCh_num
PwmCh_num hardware registers.
Definition: component_pwm.h:41
Pwm
Definition: component_pwm.h:61
Pwm::PWM_CMPM6
__IO uint32_t PWM_CMPM6
(Pwm Offset: 0x198) PWM Comparison 6 Mode Register
Definition: component_pwm.h:121
Pwm::PWM_CMPMUPD1
__O uint32_t PWM_CMPMUPD1
(Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register
Definition: component_pwm.h:102
Pwm::PWM_CMPV0
__IO uint32_t PWM_CMPV0
(Pwm Offset: 0x130) PWM Comparison 0 Value Register
Definition: component_pwm.h:95
Pwm::PWM_CMPM7
__IO uint32_t PWM_CMPM7
(Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register
Definition: component_pwm.h:125
Pwm::PWM_CMPV1
__IO uint32_t PWM_CMPV1
(Pwm Offset: 0x140) PWM Comparison 1 Value Register
Definition: component_pwm.h:99
Pwm::PWM_CMPMUPD0
__O uint32_t PWM_CMPMUPD0
(Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register
Definition: component_pwm.h:98
Pwm::PWM_CMPMUPD7
__O uint32_t PWM_CMPMUPD7
(Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register
Definition: component_pwm.h:126
Pwm::PWM_CMPV4
__IO uint32_t PWM_CMPV4
(Pwm Offset: 0x170) PWM Comparison 4 Value Register
Definition: component_pwm.h:111
Pwm::PWM_CMPM1
__IO uint32_t PWM_CMPM1
(Pwm Offset: 0x148) PWM Comparison 1 Mode Register
Definition: component_pwm.h:101
Pwm::PWM_CMPV7
__IO uint32_t PWM_CMPV7
(Pwm Offset: 0x1A0) PWM Comparison 7 Value Register
Definition: component_pwm.h:123
Pwm::PWM_CMPMUPD3
__O uint32_t PWM_CMPMUPD3
(Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register
Definition: component_pwm.h:110
Pwm::PWM_CMPV2
__IO uint32_t PWM_CMPV2
(Pwm Offset: 0x150) PWM Comparison 2 Value Register
Definition: component_pwm.h:103
Pwm::PWM_CMPVUPD6
__O uint32_t PWM_CMPVUPD6
(Pwm Offset: 0x194) PWM Comparison 6 Value Update Register
Definition: component_pwm.h:120
Pwm::PWM_CMPMUPD6
__O uint32_t PWM_CMPMUPD6
(Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register
Definition: component_pwm.h:122
Pwm::PWM_CMPM0
__IO uint32_t PWM_CMPM0
(Pwm Offset: 0x138) PWM Comparison 0 Mode Register
Definition: component_pwm.h:97
Pwm::PWM_CMPM3
__IO uint32_t PWM_CMPM3
(Pwm Offset: 0x168) PWM Comparison 3 Mode Register
Definition: component_pwm.h:109
Pwm::PWM_CMPVUPD1
__O uint32_t PWM_CMPVUPD1
(Pwm Offset: 0x144) PWM Comparison 1 Value Update Register
Definition: component_pwm.h:100
Pwm::PWM_CMPVUPD3
__O uint32_t PWM_CMPVUPD3
(Pwm Offset: 0x164) PWM Comparison 3 Value Update Register
Definition: component_pwm.h:108
Pwm::PWM_CMPMUPD4
__O uint32_t PWM_CMPMUPD4
(Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register
Definition: component_pwm.h:114
Pwm::PWM_CMPV5
__IO uint32_t PWM_CMPV5
(Pwm Offset: 0x180) PWM Comparison 5 Value Register
Definition: component_pwm.h:115
Pwm::PWM_CMPVUPD4
__O uint32_t PWM_CMPVUPD4
(Pwm Offset: 0x174) PWM Comparison 4 Value Update Register
Definition: component_pwm.h:112
Pwm::PWM_CMPVUPD0
__O uint32_t PWM_CMPVUPD0
(Pwm Offset: 0x134) PWM Comparison 0 Value Update Register
Definition: component_pwm.h:96
Pwm::PWM_CMPMUPD2
__O uint32_t PWM_CMPMUPD2
(Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register
Definition: component_pwm.h:106
Pwm::PWM_CMPVUPD7
__O uint32_t PWM_CMPVUPD7
(Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register
Definition: component_pwm.h:124
Pwm::PWM_CMPM5
__IO uint32_t PWM_CMPM5
(Pwm Offset: 0x188) PWM Comparison 5 Mode Register
Definition: component_pwm.h:117
Pwm::PWM_CMPV6
__IO uint32_t PWM_CMPV6
(Pwm Offset: 0x190) PWM Comparison 6 Value Register
Definition: component_pwm.h:119
Pwm::PWM_CMPM4
__IO uint32_t PWM_CMPM4
(Pwm Offset: 0x178) PWM Comparison 4 Mode Register
Definition: component_pwm.h:113
Pwm::PWM_CMPVUPD2
__O uint32_t PWM_CMPVUPD2
(Pwm Offset: 0x154) PWM Comparison 2 Value Update Register
Definition: component_pwm.h:104
Pwm::PWM_CMPV3
__IO uint32_t PWM_CMPV3
(Pwm Offset: 0x160) PWM Comparison 3 Value Register
Definition: component_pwm.h:107
Pwm::PWM_CMPMUPD5
__O uint32_t PWM_CMPMUPD5
(Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register
Definition: component_pwm.h:118
Pwm::PWM_CMPVUPD5
__O uint32_t PWM_CMPVUPD5
(Pwm Offset: 0x184) PWM Comparison 5 Value Update Register
Definition: component_pwm.h:116
Pwm::PWM_CMPM2
__IO uint32_t PWM_CMPM2
(Pwm Offset: 0x158) PWM Comparison 2 Mode Register
Definition: component_pwm.h:105