RTEMS: bsps/arm/atsam/include/libchip/include/same70/component/component_rtc.h Source File

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component_rtc.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAME70_RTC_COMPONENT_
31#define _SAME70_RTC_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41 typedef struct {
42 __IO uint32_t RTC_CR;
43 __IO uint32_t RTC_MR;
44 __IO uint32_t RTC_TIMR;
45 __IO uint32_t RTC_CALR;
46 __IO uint32_t RTC_TIMALR;
47 __IO uint32_t RTC_CALALR;
48 __I uint32_t RTC_SR;
49 __O uint32_t RTC_SCCR;
50 __O uint32_t RTC_IER;
51 __O uint32_t RTC_IDR;
52 __I uint32_t RTC_IMR;
53 __I uint32_t RTC_VER;
54 __I uint32_t Reserved1[45];
55 __IO uint32_t RTC_WPMR;
56} Rtc;
57#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
58/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
59#define RTC_CR_UPDTIM (0x1u << 0)
60#define RTC_CR_UPDCAL (0x1u << 1)
61#define RTC_CR_TIMEVSEL_Pos 8
62#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos)
63#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos)))
64#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8)
65#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8)
66#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8)
67#define RTC_CR_TIMEVSEL_NOON (0x3u << 8)
68#define RTC_CR_CALEVSEL_Pos 16
69#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos)
70#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos)))
71#define RTC_CR_CALEVSEL_WEEK (0x0u << 16)
72#define RTC_CR_CALEVSEL_MONTH (0x1u << 16)
73#define RTC_CR_CALEVSEL_YEAR (0x2u << 16)
74/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
75#define RTC_MR_HRMOD (0x1u << 0)
76#define RTC_MR_PERSIAN (0x1u << 1)
77#define RTC_MR_NEGPPM (0x1u << 4)
78#define RTC_MR_CORRECTION_Pos 8
79#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos)
80#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))
81#define RTC_MR_HIGHPPM (0x1u << 15)
82#define RTC_MR_OUT0_Pos 16
83#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos)
84#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos)))
85#define RTC_MR_OUT0_NO_WAVE (0x0u << 16)
86#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16)
87#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16)
88#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16)
89#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16)
90#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16)
91#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16)
92#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16)
93#define RTC_MR_OUT1_Pos 20
94#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos)
95#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos)))
96#define RTC_MR_OUT1_NO_WAVE (0x0u << 20)
97#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20)
98#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20)
99#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20)
100#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20)
101#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20)
102#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20)
103#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20)
104#define RTC_MR_THIGH_Pos 24
105#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos)
106#define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos)))
107#define RTC_MR_THIGH_H_31MS (0x0u << 24)
108#define RTC_MR_THIGH_H_16MS (0x1u << 24)
109#define RTC_MR_THIGH_H_4MS (0x2u << 24)
110#define RTC_MR_THIGH_H_976US (0x3u << 24)
111#define RTC_MR_THIGH_H_488US (0x4u << 24)
112#define RTC_MR_THIGH_H_122US (0x5u << 24)
113#define RTC_MR_THIGH_H_30US (0x6u << 24)
114#define RTC_MR_THIGH_H_15US (0x7u << 24)
115#define RTC_MR_TPERIOD_Pos 28
116#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos)
117#define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos)))
118#define RTC_MR_TPERIOD_P_1S (0x0u << 28)
119#define RTC_MR_TPERIOD_P_500MS (0x1u << 28)
120#define RTC_MR_TPERIOD_P_250MS (0x2u << 28)
121#define RTC_MR_TPERIOD_P_125MS (0x3u << 28)
122/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
123#define RTC_TIMR_SEC_Pos 0
124#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos)
125#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
126#define RTC_TIMR_MIN_Pos 8
127#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos)
128#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
129#define RTC_TIMR_HOUR_Pos 16
130#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos)
131#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
132#define RTC_TIMR_AMPM (0x1u << 22)
133/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
134#define RTC_CALR_CENT_Pos 0
135#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos)
136#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
137#define RTC_CALR_YEAR_Pos 8
138#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos)
139#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
140#define RTC_CALR_MONTH_Pos 16
141#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos)
142#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
143#define RTC_CALR_DAY_Pos 21
144#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos)
145#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
146#define RTC_CALR_DATE_Pos 24
147#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos)
148#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
149/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
150#define RTC_TIMALR_SEC_Pos 0
151#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos)
152#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
153#define RTC_TIMALR_SECEN (0x1u << 7)
154#define RTC_TIMALR_MIN_Pos 8
155#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos)
156#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
157#define RTC_TIMALR_MINEN (0x1u << 15)
158#define RTC_TIMALR_HOUR_Pos 16
159#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos)
160#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
161#define RTC_TIMALR_AMPM (0x1u << 22)
162#define RTC_TIMALR_HOUREN (0x1u << 23)
163/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
164#define RTC_CALALR_MONTH_Pos 16
165#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos)
166#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
167#define RTC_CALALR_MTHEN (0x1u << 23)
168#define RTC_CALALR_DATE_Pos 24
169#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos)
170#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
171#define RTC_CALALR_DATEEN (0x1u << 31)
172/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
173#define RTC_SR_ACKUPD (0x1u << 0)
174#define RTC_SR_ACKUPD_FREERUN (0x0u << 0)
175#define RTC_SR_ACKUPD_UPDATE (0x1u << 0)
176#define RTC_SR_ALARM (0x1u << 1)
177#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1)
178#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1)
179#define RTC_SR_SEC (0x1u << 2)
180#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2)
181#define RTC_SR_SEC_SECEVENT (0x1u << 2)
182#define RTC_SR_TIMEV (0x1u << 3)
183#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3)
184#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3)
185#define RTC_SR_CALEV (0x1u << 4)
186#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4)
187#define RTC_SR_CALEV_CALEVENT (0x1u << 4)
188#define RTC_SR_TDERR (0x1u << 5)
189#define RTC_SR_TDERR_CORRECT (0x0u << 5)
190#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5)
191/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
192#define RTC_SCCR_ACKCLR (0x1u << 0)
193#define RTC_SCCR_ALRCLR (0x1u << 1)
194#define RTC_SCCR_SECCLR (0x1u << 2)
195#define RTC_SCCR_TIMCLR (0x1u << 3)
196#define RTC_SCCR_CALCLR (0x1u << 4)
197#define RTC_SCCR_TDERRCLR (0x1u << 5)
198/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
199#define RTC_IER_ACKEN (0x1u << 0)
200#define RTC_IER_ALREN (0x1u << 1)
201#define RTC_IER_SECEN (0x1u << 2)
202#define RTC_IER_TIMEN (0x1u << 3)
203#define RTC_IER_CALEN (0x1u << 4)
204#define RTC_IER_TDERREN (0x1u << 5)
205/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
206#define RTC_IDR_ACKDIS (0x1u << 0)
207#define RTC_IDR_ALRDIS (0x1u << 1)
208#define RTC_IDR_SECDIS (0x1u << 2)
209#define RTC_IDR_TIMDIS (0x1u << 3)
210#define RTC_IDR_CALDIS (0x1u << 4)
211#define RTC_IDR_TDERRDIS (0x1u << 5)
212/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
213#define RTC_IMR_ACK (0x1u << 0)
214#define RTC_IMR_ALR (0x1u << 1)
215#define RTC_IMR_SEC (0x1u << 2)
216#define RTC_IMR_TIM (0x1u << 3)
217#define RTC_IMR_CAL (0x1u << 4)
218#define RTC_IMR_TDERR (0x1u << 5)
219/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
220#define RTC_VER_NVTIM (0x1u << 0)
221#define RTC_VER_NVCAL (0x1u << 1)
222#define RTC_VER_NVTIMALR (0x1u << 2)
223#define RTC_VER_NVCALALR (0x1u << 3)
224/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */
225#define RTC_WPMR_WPEN (0x1u << 0)
226#define RTC_WPMR_WPKEY_Pos 8
227#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos)
228#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
229#define RTC_WPMR_WPKEY_PASSWD (0x525443u << 8)
232
233
234#endif /* _SAME70_RTC_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Rtc
Rtc hardware registers.
Definition: component_rtc.h:41
Rtc::RTC_VER
__I uint32_t RTC_VER
(Rtc Offset: 0x2C) Valid Entry Register
Definition: component_rtc.h:53
Rtc::RTC_SCCR
__O uint32_t RTC_SCCR
(Rtc Offset: 0x1C) Status Clear Command Register
Definition: component_rtc.h:49
Rtc::RTC_MR
__IO uint32_t RTC_MR
(Rtc Offset: 0x04) Mode Register
Definition: component_rtc.h:43
Rtc::RTC_WPMR
__IO uint32_t RTC_WPMR
(Rtc Offset: 0xE4) Write Protection Mode Register
Definition: component_rtc.h:55
Rtc::RTC_SR
__I uint32_t RTC_SR
(Rtc Offset: 0x18) Status Register
Definition: component_rtc.h:48
Rtc::RTC_TIMR
__IO uint32_t RTC_TIMR
(Rtc Offset: 0x08) Time Register
Definition: component_rtc.h:44
Rtc::RTC_TIMALR
__IO uint32_t RTC_TIMALR
(Rtc Offset: 0x10) Time Alarm Register
Definition: component_rtc.h:46
Rtc::RTC_IDR
__O uint32_t RTC_IDR
(Rtc Offset: 0x24) Interrupt Disable Register
Definition: component_rtc.h:51
Rtc::RTC_CALR
__IO uint32_t RTC_CALR
(Rtc Offset: 0x0C) Calendar Register
Definition: component_rtc.h:45
Rtc::RTC_IMR
__I uint32_t RTC_IMR
(Rtc Offset: 0x28) Interrupt Mask Register
Definition: component_rtc.h:52
Rtc::RTC_IER
__O uint32_t RTC_IER
(Rtc Offset: 0x20) Interrupt Enable Register
Definition: component_rtc.h:50
Rtc::RTC_CALALR
__IO uint32_t RTC_CALALR
(Rtc Offset: 0x14) Calendar Alarm Register
Definition: component_rtc.h:47
Rtc::RTC_CR
__IO uint32_t RTC_CR
(Rtc Offset: 0x00) Control Register
Definition: component_rtc.h:42