RTEMS: Pio Struct Reference

| RTEMS 5.4-rc2

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Data Fields
Pio Struct Reference

Pio hardware registers. More...

`#include <component_pio.h>`

## Data Fields
__O uint32_t | PIO_PER
| (Pio Offset: 0x0000) PIO Enable Register
__O uint32_t | PIO_PDR
| (Pio Offset: 0x0004) PIO Disable Register
__I uint32_t | PIO_PSR
| (Pio Offset: 0x0008) PIO Status Register
__I uint32_t | Reserved1 [1]
__O uint32_t | PIO_OER
| (Pio Offset: 0x0010) Output Enable Register
__O uint32_t | PIO_ODR
| (Pio Offset: 0x0014) Output Disable Register
__I uint32_t | PIO_OSR
| (Pio Offset: 0x0018) Output Status Register
__I uint32_t | Reserved2 [1]
__O uint32_t | PIO_IFER
| (Pio Offset: 0x0020) Glitch Input Filter Enable Register
__O uint32_t | PIO_IFDR
| (Pio Offset: 0x0024) Glitch Input Filter Disable Register
__I uint32_t | PIO_IFSR
| (Pio Offset: 0x0028) Glitch Input Filter Status Register
__I uint32_t | Reserved3 [1]
__O uint32_t | PIO_SODR
| (Pio Offset: 0x0030) Set Output Data Register
__O uint32_t | PIO_CODR
| (Pio Offset: 0x0034) Clear Output Data Register
__IO uint32_t | PIO_ODSR
| (Pio Offset: 0x0038) Output Data Status Register
__I uint32_t | PIO_PDSR
| (Pio Offset: 0x003C) Pin Data Status Register
__O uint32_t | PIO_IER
| (Pio Offset: 0x0040) Interrupt Enable Register
__O uint32_t | PIO_IDR
| (Pio Offset: 0x0044) Interrupt Disable Register
__I uint32_t | PIO_IMR
| (Pio Offset: 0x0048) Interrupt Mask Register
__I uint32_t | PIO_ISR
| (Pio Offset: 0x004C) Interrupt Status Register
__O uint32_t | PIO_MDER
| (Pio Offset: 0x0050) Multi-driver Enable Register
__O uint32_t | PIO_MDDR
| (Pio Offset: 0x0054) Multi-driver Disable Register
__I uint32_t | PIO_MDSR
| (Pio Offset: 0x0058) Multi-driver Status Register
__I uint32_t | Reserved4 [1]
__O uint32_t | PIO_PUDR
| (Pio Offset: 0x0060) Pull-up Disable Register
__O uint32_t | PIO_PUER
| (Pio Offset: 0x0064) Pull-up Enable Register
__I uint32_t | PIO_PUSR
| (Pio Offset: 0x0068) Pad Pull-up Status Register
__I uint32_t | Reserved5 [1]
__IO uint32_t | PIO_ABCDSR [2]
| (Pio Offset: 0x0070) Peripheral Select Register
__I uint32_t | Reserved6 [2]
__O uint32_t | PIO_IFSCDR
| (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register
__O uint32_t | PIO_IFSCER
| (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register
__I uint32_t | PIO_IFSCSR
| (Pio Offset: 0x0088) Input Filter Slow Clock Status Register
__IO uint32_t | PIO_SCDR
| (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register
__O uint32_t | PIO_PPDDR
| (Pio Offset: 0x0090) Pad Pull-down Disable Register
__O uint32_t | PIO_PPDER
| (Pio Offset: 0x0094) Pad Pull-down Enable Register
__I uint32_t | PIO_PPDSR
| (Pio Offset: 0x0098) Pad Pull-down Status Register
__I uint32_t | Reserved7 [1]
__O uint32_t | PIO_OWER
| (Pio Offset: 0x00A0) Output Write Enable
__O uint32_t | PIO_OWDR
| (Pio Offset: 0x00A4) Output Write Disable
__I uint32_t | PIO_OWSR
| (Pio Offset: 0x00A8) Output Write Status Register
__I uint32_t | Reserved8 [1]
__O uint32_t | PIO_AIMER
| (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register
__O uint32_t | PIO_AIMDR
| (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register
__I uint32_t | PIO_AIMMR
| (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register
__I uint32_t | Reserved9 [1]
__O uint32_t | PIO_ESR
| (Pio Offset: 0x00C0) Edge Select Register
__O uint32_t | PIO_LSR
| (Pio Offset: 0x00C4) Level Select Register
__I uint32_t | PIO_ELSR
| (Pio Offset: 0x00C8) Edge/Level Status Register
__I uint32_t | Reserved10 [1]
__O uint32_t | PIO_FELLSR
| (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register
__O uint32_t | PIO_REHLSR
| (Pio Offset: 0x00D4) Rising Edge/High-Level Select Register
__I uint32_t | PIO_FRLHSR
| (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register
__I uint32_t | Reserved11 [1]
__I uint32_t | PIO_LOCKSR
| (Pio Offset: 0x00E0) Lock Status
__IO uint32_t | PIO_WPMR
| (Pio Offset: 0x00E4) Write Protection Mode Register
__I uint32_t | PIO_WPSR
| (Pio Offset: 0x00E8) Write Protection Status Register
__I uint32_t | Reserved12 [5]
__IO uint32_t | PIO_SCHMITT
| (Pio Offset: 0x0100) Schmitt Trigger Register
__I uint32_t | Reserved13 [5]
__IO uint32_t | PIO_DRIVER
| (Pio Offset: 0x0118) I/O Drive Register
__I uint32_t | Reserved14 [13]
__IO uint32_t | PIO_PCMR
| (Pio Offset: 0x0150) Parallel Capture Mode Register
__O uint32_t | PIO_PCIER
| (Pio Offset: 0x0154) Parallel Capture Interrupt Enable Register
__O uint32_t | PIO_PCIDR
| (Pio Offset: 0x0158) Parallel Capture Interrupt Disable Register
__I uint32_t | PIO_PCIMR
| (Pio Offset: 0x015C) Parallel Capture Interrupt Mask Register
__I uint32_t | PIO_PCISR
| (Pio Offset: 0x0160) Parallel Capture Interrupt Status Register
__I uint32_t | PIO_PCRHR
| (Pio Offset: 0x0164) Parallel Capture Reception Holding Register
__I uint32_t | PIO_VERSION
| (Pio Offset: 0x00FC) Version Register

## Detailed Description

Pio hardware registers.

The documentation for this struct was generated from the following files:

- bsps/arm/atsam/include/libchip/include/same70/component/component_pio.h
- bsps/arm/atsam/include/libchip/include/sams70/component/component_pio.h
- bsps/arm/atsam/include/libchip/include/samv71/component/component_pio.h