RTEMS: bsps/powerpc/mpc55xxevb/include/mpc55xx/fsl-mpc564xL.h Source File

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fsl-mpc564xL.h
1/*
2 * Modifications of the original file provided by Freescale Semiconductor and
3 * ST Microelectronics are:
4 *
5 * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
6 *
7 * embedded brains GmbH
8 * Obere Lagerstr. 30
9 * 82178 Puchheim
10 * Germany
11 * <info@embedded-brains.de>
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/****************************************************************************\
36 * PROJECT : MPC5643L
37 * FILE : mpc5643l.h
38 *
39 * DESCRIPTION : This is the header file describing the register
40 * set for the named projects.
41 *
42 * COPYRIGHT : (c) 2009, Freescale Semiconductor & ST Microelectronics
43 *
44 * VERSION : 1.04
45 * RELEASE DATE : Tue Dec 1 2009
46 * CREATION DATE : Thu Oct 8 13:53:51 CEST 2009
47 * AUTHOR : generated from IP-XACT database
48 * HISTORY : Preliminary release.
49\****************************************************************************/
50
51/* >>>> NOTE! this file is auto-generated please do not edit it! <<<< */
52
53/****************************************************************************\
54 * Example instantiation and use:
55 *
56 * <MODULE>.<REGISTER>.B.<BIT> = 1;
57 * <MODULE>.<REGISTER>.R = 0x10000000;
58 *
59\****************************************************************************/
60
61/*
62 * LICENSE:
63 * Copyright (c) 2006 Freescale Semiconductor
64 *
65 * Permission is hereby granted, free of charge, to any person
66 * obtaining a copy of this software and associated documentation
67 * files (the "Software"), to deal in the Software without
68 * restriction, including without limitation the rights to use,
69 * copy, modify, merge, publish, distribute, sublicense, and/or
70 * sell copies of the Software, and to permit persons to whom the
71 * Software is furnished to do so, subject to the following
72 * conditions:
73 *
74 * The above copyright notice and this permission notice
75 * shall be included in all copies or substantial portions
76 * of the Software.
77 *
78 * THIS SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
79 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
80 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
81 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
82 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
83 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
84 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
85 * DEALINGS IN THE SOFTWARE.
86 *
87 */
88
89#ifndef _leopard_H_ /* prevents multiple inclusions of this file */
90#define _leopard_H_
91
92#ifndef ASM
93
94#include <stdint.h>
95
96#include <mpc55xx/regs-edma.h>
97
98#ifdef __cplusplus
99extern "C" {
100#endif
101
102#ifdef __MWERKS__
103#pragma push
104#pragma ANSI_strict off
105#endif
106
107//#define USE_FIELD_ALIASES_CFLASH
108//#define USE_FIELD_ALIASES_SIUL
109//#define USE_FIELD_ALIASES_SSCM
110//#define USE_FIELD_ALIASES_ME
111//#define USE_FIELD_ALIASES_RGM
112//#define USE_FIELD_ALIASES_ADC
113//#define USE_FIELD_ALIASES_CTU
114//#define USE_FIELD_ALIASES_mcTIMER
115//#define USE_FIELD_ALIASES_mcPWM
116//#define USE_FIELD_ALIASES_LINFLEX
117//#define USE_FIELD_ALIASES_SPP_MCM
118#define USE_FIELD_ALIASES_INTC
119#define USE_FIELD_ALIASES_DSPI
120//#define USE_FIELD_ALIASES_FLEXCAN
121//#define USE_FIELD_ALIASES_FR
122//#define USE_FIELD_ALIASES_CMU
123//#define USE_FIELD_ALIASES_PLLD
124//#define USE_FIELD_ALIASES_SPP_DMA2
125
126/* Define memories */
127
128#define SRAM_START 0x40000000
129#define SRAM_SIZE 0x20000
130#define SRAM_END 0x4001FFFF
131
132#define FLASH_START 0x0
133#define FLASH_SIZE 0xC0000
134#define FLASH_END 0xBFFFF
135
136/****************************************************************/
137/* */
138/* Global definitions and aliases */
139/* */
140/****************************************************************/
141
142/*
143 Platform blocks that are only accessible by the second core (core 1) when
144 the device is in DPM mode. The block definition is equivalent to the one
145 for the first core (core 0) and reuses the related block structure.
146
147 NOTE: the <block_name>_1 defines are the preferred method for programming
148 */
149#define PBRIDGE_1 (*(volatile PBRIDGE_tag*) 0x8FF00000UL)
150#define MAX_1 (*(volatile MAX_tag*) 0x8FF04000UL)
151#define MPU_1 (*(volatile MPU_tag*) 0x8FF10000UL)
152#define SEMA4_1 (*(volatile SEMA4_tag*) 0x8FF24000UL)
153#define SWT_1 (*(volatile SWT_tag*) 0x8FF38000UL)
154#define STM_1 (*(volatile STM_tag*) 0x8FF3C000UL)
155#define SPP_MCM_1 (*(volatile SPP_MCM_tag*) 0x8FF40000UL)
156#define SPP_DMA2_1 (*(volatile SPP_DMA2_tag*) 0x8FF44000UL)
157#define INTC_1 (*(volatile INTC_tag*) 0x8FF48000UL)
158
159/*
160 Platform blocks that are only accessible by the second core (core 1) when
161 the device is in DPM mode. The block definition is equivalent to the one
162 for the first core (core 0) and reuses the related block structure.
163
164 NOTE: the <block_name>_DPM defines are deprecated, use <block_name>_1 for
165 programming the corresponding blocks for new code instead.
166 */
167#define PBRIDGE_DPM PBRIDGE_1
168#define MAX_DPM MAX_1
169#define MPU_DPM MPU_1
170#define SEMA4_DPM SEMA4_1
171#define SWT_DPM SWT_1
172#define STM_DPM STM_1
173#define SPP_MCM_DPM SPP_MCM_1
174#define SPP_DMA2_DPM SPP_DMA2_1
175#define INTC_DPM INTC_1
176
177/* Aliases for Pictus Module names */
178#define CAN_0 FLEXCAN_A
179#define CAN_1 FLEXCAN_B
180#define CTU_0 CTU
181#define DFLASH CRC
182#define DMAMUX DMA_CH_MUX
183#define DSPI_0 DSPI_A
184#define DSPI_1 DSPI_B
185#define DSPI_2 DSPI_C
186#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL)
187#define ETIMER_0 mcTIMER0
188#define ETIMER_1 mcTIMER1
189#define FLEXPWM_0 mcPWM_A
190#define FLEXPWM_1 mcPWM_B
191#define LINFLEX_0 LINFLEX0
192#define LINFLEX_1 LINFLEX1
193#define MCM_ SPP_MCM
194#define PIT PIT_RTI
195#define SIU SIUL
196#define WKUP WKPU
197#define ADC_0 ADC0
198#define ADC_1 ADC1
199
200/* Other Aliases */
201#define AIPS_DPM PBRIDGE_1
202#define AIPS_1 PBRIDGE_1
203#define AIPS PBRIDGE
204
205/****************************************************************/
206/* */
207/* Module: CFLASH_SHADOW */
208/* */
209/****************************************************************/
210
211
212 /* Register layout for all registers NVPWD... */
213
214 typedef union { /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
215 uint32_t R;
216 struct {
217 uint32_t PWD:32; /* PassWorD */
218 } B;
219 } CFLASH_SHADOW_NVPWD_32B_tag;
220
221
222 /* Register layout for all registers NVSCI... */
223
224 typedef union { /* NVSCI - Non Volatile System Censoring Information Register */
225 uint32_t R;
226 struct {
227 uint32_t SC:16; /* Serial Censorship Control Word */
228 uint32_t CW:16; /* Censorship Control Word */
229 } B;
230 } CFLASH_SHADOW_NVSCI_32B_tag;
231
232 typedef union { /* Non Volatile LML Default Value */
233 uint32_t R;
234 } CFLASH_SHADOW_NVLML_32B_tag;
235
236 typedef union { /* Non Volatile HBL Default Value */
237 uint32_t R;
238 } CFLASH_SHADOW_NVHBL_32B_tag;
239
240 typedef union { /* Non Volatile SLL Default Value */
241 uint32_t R;
242 } CFLASH_SHADOW_NVSLL_32B_tag;
243
244
245 /* Register layout for all registers NVBIU... */
246
247 typedef union { /* Non Volatile Bus Interface Unit Register */
248 uint32_t R;
249 struct {
250 uint32_t BI:32; /* Bus interface Unit */
251 } B;
252 } CFLASH_SHADOW_NVBIU_32B_tag;
253
254 typedef union { /* NVUSRO - Non Volatile USeR Options Register */
255 uint32_t R;
256 struct {
257 uint32_t UO:32; /* User Options */
258 } B;
259 } CFLASH_SHADOW_NVUSRO_32B_tag;
260
261
262 typedef struct CFLASH_SHADOW_BIU_DEFAULTS_struct_tag {
263
264 /* Non Volatile Bus Interface Unit Register */
265 CFLASH_SHADOW_NVBIU_32B_tag NVBIU; /* relative offset: 0x0000 */
266 int8_t CFLASH_SHADOW_BIU_DEFAULTS_reserved_0004[4];
267
268 } CFLASH_SHADOW_BIU_DEFAULTS_tag;
269
270
271 typedef struct CFLASH_SHADOW_struct_tag { /* start of CFLASH_SHADOW_tag */
272 int8_t CFLASH_SHADOW_reserved_0000_C[15832];
273 union {
274 /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
275 CFLASH_SHADOW_NVPWD_32B_tag NVPWD[2]; /* offset: 0x3DD8 (0x0004 x 2) */
276
277 struct {
278 /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
279 CFLASH_SHADOW_NVPWD_32B_tag NVPWD0; /* offset: 0x3DD8 size: 32 bit */
280 CFLASH_SHADOW_NVPWD_32B_tag NVPWD1; /* offset: 0x3DDC size: 32 bit */
281 };
282
283 };
284 union {
285 /* NVSCI - Non Volatile System Censoring Information Register */
286 CFLASH_SHADOW_NVSCI_32B_tag NVSCI[2]; /* offset: 0x3DE0 (0x0004 x 2) */
287
288 struct {
289 /* NVSCI - Non Volatile System Censoring Information Register */
290 CFLASH_SHADOW_NVSCI_32B_tag NVSCI0; /* offset: 0x3DE0 size: 32 bit */
291 CFLASH_SHADOW_NVSCI_32B_tag NVSCI1; /* offset: 0x3DE4 size: 32 bit */
292 };
293
294 };
295 /* Non Volatile LML Default Value */
296 CFLASH_SHADOW_NVLML_32B_tag NVLML; /* offset: 0x3DE8 size: 32 bit */
297 int8_t CFLASH_SHADOW_reserved_3DEC[4];
298 /* Non Volatile HBL Default Value */
299 CFLASH_SHADOW_NVHBL_32B_tag NVHBL; /* offset: 0x3DF0 size: 32 bit */
300 int8_t CFLASH_SHADOW_reserved_3DF4[4];
301 /* Non Volatile SLL Default Value */
302 CFLASH_SHADOW_NVSLL_32B_tag NVSLL; /* offset: 0x3DF8 size: 32 bit */
303 int8_t CFLASH_SHADOW_reserved_3DFC_C[4];
304 union {
305 /* Register set BIU_DEFAULTS */
306 CFLASH_SHADOW_BIU_DEFAULTS_tag BIU_DEFAULTS[3]; /* offset: 0x3E00 (0x0008 x 3) */
307
308 struct {
309 /* Non Volatile Bus Interface Unit Register */
310 CFLASH_SHADOW_NVBIU_32B_tag NVBIU2; /* offset: 0x3E00 size: 32 bit */
311 int8_t CFLASH_SHADOW_reserved_3E04_I1[4];
312 CFLASH_SHADOW_NVBIU_32B_tag NVBIU3; /* offset: 0x3E08 size: 32 bit */
313 int8_t CFLASH_SHADOW_reserved_3E0C_I1[4];
314 CFLASH_SHADOW_NVBIU_32B_tag NVBIU4; /* offset: 0x3E10 size: 32 bit */
315 int8_t CFLASH_SHADOW_reserved_3E14_E1[4];
316 };
317
318 };
319 /* NVUSRO - Non Volatile USeR Options Register */
320 CFLASH_SHADOW_NVUSRO_32B_tag NVUSRO; /* offset: 0x3E18 size: 32 bit */
321 } CFLASH_SHADOW_tag;
322
323
324#define CFLASH_SHADOW (*(volatile CFLASH_SHADOW_tag *) 0x00F00000UL)
325
326
327
328/****************************************************************/
329/* */
330/* Module: CFLASH */
331/* */
332/****************************************************************/
333
334 typedef union { /* MCR - Module Configuration Register */
335 uint32_t R;
336 struct {
337 uint32_t:5;
338 uint32_t SIZE:3; /* Array Space Size */
339 uint32_t:1;
340 uint32_t LAS:3; /* Low Address Space */
341 uint32_t:3;
342 uint32_t MAS:1; /* Mid Address Space Configuration */
343 uint32_t EER:1; /* ECC Event Error */
344 uint32_t RWE:1; /* Read-while-Write Event Error */
345 uint32_t SBC:1; /* Single Bit Correction */
346 uint32_t:1;
347 uint32_t PEAS:1; /* Program/Erase Access Space */
348 uint32_t DONE:1; /* modify operation DONE */
349 uint32_t PEG:1; /* Program/Erase Good */
350 uint32_t:4;
351 uint32_t PGM:1; /* Program Bit */
352 uint32_t PSUS:1; /* Program Suspend */
353 uint32_t ERS:1; /* Erase Bit */
354 uint32_t ESUS:1; /* Erase Suspend */
355 uint32_t EHV:1; /* Enable High Voltage */
356 } B;
357 } CFLASH_MCR_32B_tag;
358
359 typedef union { /* LML - Low/Mid Address Space Block Locking Register */
360 uint32_t R;
361 struct {
362 uint32_t LME:1; /* Low/Mid Address Space Block Enable */
363 uint32_t:10;
364#ifndef USE_FIELD_ALIASES_CFLASH
365 uint32_t SLOCK:1; /* Shadow Address Space Block Lock */
366#else
367 uint32_t TSLK:1; /* deprecated name - please avoid */
368#endif
369 uint32_t:2;
370#ifndef USE_FIELD_ALIASES_CFLASH
371 uint32_t MLOCK:2; /* Mid Address Space Block Lock */
372#else
373 uint32_t MLK:2; /* deprecated name - please avoid */
374#endif
375 uint32_t:6;
376 uint32_t LLOCK:10; /* Low Address Space Block Lock */
377 } B;
378 } CFLASH_LML_32B_tag;
379
380 typedef union { /* HBL - High Address Space Block Locking Register */
381 uint32_t R;
382 struct {
383 uint32_t HBE:1; /* High Address Space Block Enable */
384 uint32_t:25;
385 uint32_t HLOCK:6; /* High Address Space Block Lock */
386 } B;
387 } CFLASH_HBL_32B_tag;
388
389 typedef union { /* SLL - Secondary Low/Mid Address Space Block Locking Register */
390 uint32_t R;
391 struct {
392 uint32_t SLE:1; /* Secondary Low/Mid Address Space Block Enable */
393 uint32_t:10;
394#ifndef USE_FIELD_ALIASES_CFLASH
395 uint32_t SSLOCK:1; /* Secondary Shadow Address Space Block Lock */
396#else
397 uint32_t STSLK:1; /* deprecated name - please avoid */
398#endif
399 uint32_t:2;
400#ifndef USE_FIELD_ALIASES_CFLASH
401 uint32_t SMLOCK:2; /* Secondary Mid Address Space Block Lock */
402#else
403 uint32_t SMK:2; /* deprecated name - please avoid */
404#endif
405 uint32_t:6;
406 uint32_t SLLOCK:10; /* Secondary Low Address Space Block Lock */
407 } B;
408 } CFLASH_SLL_32B_tag;
409
410 typedef union { /* LMS - Low/Mid Address Space Block Select Register */
411 uint32_t R;
412 struct {
413 uint32_t:14;
414 uint32_t MSL:2; /* Mid Address Space Block Select */
415 uint32_t:6;
416 uint32_t LSL:10; /* Low Address Space Block Select */
417 } B;
418 } CFLASH_LMS_32B_tag;
419
420 typedef union { /* HBS - High Address Space Block Select Register */
421 uint32_t R;
422 struct {
423 uint32_t:26;
424 uint32_t HSL:6; /* High Address Space Block Select */
425 } B;
426 } CFLASH_HBS_32B_tag;
427
428 typedef union { /* ADR - Address Register */
429 uint32_t R;
430 struct {
431 uint32_t SAD:1; /* Shadow Address */
432 uint32_t:10;
433 uint32_t ADDR:18; /* Address */
434 uint32_t:3;
435 } B;
436 } CFLASH_ADR_32B_tag;
437
438 typedef union { /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */
439 uint32_t R;
440 struct {
441#ifndef USE_FIELD_ALIASES_CFLASH
442 uint32_t B02_APC:5; /* Bank0+2 Address Pipelining Control */
443#else
444 uint32_t BK0_APC:5; /* deprecated name - please avoid */
445#endif
446#ifndef USE_FIELD_ALIASES_CFLASH
447 uint32_t B02_WWSC:5; /* Bank0+2 Write Wait State Control */
448#else
449 uint32_t BK0_WWSC:5; /* deprecated name - please avoid */
450#endif
451#ifndef USE_FIELD_ALIASES_CFLASH
452 uint32_t B02_RWSC:5; /* Bank0+2 Read Wait State Control */
453#else
454 uint32_t BK0_RWSC:5; /* deprecated name - please avoid */
455#endif
456#ifndef USE_FIELD_ALIASES_CFLASH
457 uint32_t B02_RWWC2:1; /* Bank 0+2 Read While Write Control, bit 2 */
458#else
459 uint32_t BK0_RWWC2:1; /* deprecated name - please avoid */
460#endif
461#ifndef USE_FIELD_ALIASES_CFLASH
462 uint32_t B02_RWWC1:1; /* Bank 0+2 Read While Write Control, bit 1 */
463#else
464 uint32_t BK0_RWWC1:1; /* deprecated name - please avoid */
465#endif
466#ifndef USE_FIELD_ALIASES_CFLASH
467 uint32_t B02_P1_BCFG:2; /* Bank0+2 Port 1 Page Buffer Configuration */
468#else
469 uint32_t B0_P1_BCFG:2; /* deprecated name - please avoid */
470#endif
471#ifndef USE_FIELD_ALIASES_CFLASH
472 uint32_t B02_P1_DPFE:1; /* Bank0+2 Port 1 Data Prefetch Enable */
473#else
474 uint32_t B0_P1_DPFE:1; /* deprecated name - please avoid */
475#endif
476#ifndef USE_FIELD_ALIASES_CFLASH
477 uint32_t B02_P1_IPFE:1; /* Bank0+2 Port 1 Inst Prefetch Enable */
478#else
479 uint32_t B0_P1_IPFE:1; /* deprecated name - please avoid */
480#endif
481#ifndef USE_FIELD_ALIASES_CFLASH
482 uint32_t B02_P1_PFLM:2; /* Bank0+2 Port 1 Prefetch Limit */
483#else
484 uint32_t B0_P1_PFLM:2; /* deprecated name - please avoid */
485#endif
486#ifndef USE_FIELD_ALIASES_CFLASH
487 uint32_t B02_P1_BFE:1; /* Bank0+2 Port 1 Buffer Enable */
488#else
489 uint32_t B0_P1_BFE:1; /* deprecated name - please avoid */
490#endif
491#ifndef USE_FIELD_ALIASES_CFLASH
492 uint32_t B02_RWWC0:1; /* Bank 0+2 Read While Write Control, bit 0 */
493#else
494 uint32_t BK0_RWWC0:1; /* deprecated name - please avoid */
495#endif
496#ifndef USE_FIELD_ALIASES_CFLASH
497 uint32_t B02_P0_BCFG:2; /* Bank0+2 Port 0 Page Buffer Configuration */
498#else
499 uint32_t B0_P0_BCFG:2; /* deprecated name - please avoid */
500#endif
501#ifndef USE_FIELD_ALIASES_CFLASH
502 uint32_t B02_P0_DPFE:1; /* Bank0+2 Port 0 Data Prefetch Enable */
503#else
504 uint32_t B0_P0_DPFE:1; /* deprecated name - please avoid */
505#endif
506#ifndef USE_FIELD_ALIASES_CFLASH
507 uint32_t B02_P0_IPFE:1; /* Bank0+2 Port 0 Inst Prefetch Enable */
508#else
509 uint32_t B0_P0_IPFE:1; /* deprecated name - please avoid */
510#endif
511#ifndef USE_FIELD_ALIASES_CFLASH
512 uint32_t B02_P0_PFLM:2; /* Bank0+2 Port 0 Prefetch Limit */
513#else
514 uint32_t B0_P0_PFLM:2; /* deprecated name - please avoid */
515#endif
516#ifndef USE_FIELD_ALIASES_CFLASH
517 uint32_t B02_P0_BFE:1; /* Bank0+2 Port 0 Buffer Enable */
518#else
519 uint32_t B0_P0_BFE:1; /* deprecated name - please avoid */
520#endif
521 } B;
522 } CFLASH_PFCR0_32B_tag;
523
524
525 /* Register layout for all registers BIU... */
526
527 typedef union { /* Bus Interface Unit Register */
528 uint32_t R;
529 } CFLASH_BIU_32B_tag;
530
531 typedef union { /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */
532 uint32_t R;
533 struct {
534#ifndef USE_FIELD_ALIASES_CFLASH
535 uint32_t B1_APC:5; /* Bank 1 Address Pipelining Control */
536 uint32_t B1_WWSC:5; /* Bank 1 Write Wait State Control */
537 uint32_t B1_RWSC:5; /* Bank 1 Read Wait State Control */
538 uint32_t B1_RWWC2:1; /* Bank1 Read While Write Control, bit 2 */
539 uint32_t B1_RWWC1:1; /* Bank1 Read While Write Control, bit 1 */
540 uint32_t:6;
541 uint32_t B1_P1_BFE:1; /* Bank 1 Port 1 Buffer Enable */
542 uint32_t B1_RWWC0:1; /* Bank1 Read While Write Control, bit 0 */
543 uint32_t:6;
544 uint32_t B1_P0_BFE:1; /* Bank 1 Port 0 Buffer Enable */
545#else
546 uint32_t BK1_APC:5;
547 uint32_t BK1_WWSC:5;
548 uint32_t BK1_RWSC:5;
549 uint32_t BK1_RWWC2:1;
550 uint32_t BK1_RWWC1:1;
551 uint32_t:6;
552 uint32_t B0_P1_BFE:1;
553 uint32_t BK1_RWWC0:1;
554 uint32_t:6;
555 uint32_t B1_P0_BFE:1;
556#endif
557 } B;
558 } CFLASH_PFCR1_32B_tag;
559
560 typedef union { /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */
561 uint32_t R;
562 struct {
563 uint32_t:6;
564 uint32_t ARBM:2; /* Arbitration Mode */
565 uint32_t M7PFD:1; /* Master x Prefetch Disable */
566 uint32_t M6PFD:1; /* Master x Prefetch Disable */
567 uint32_t M5PFD:1; /* Master x Prefetch Disable */
568 uint32_t M4PFD:1; /* Master x Prefetch Disable */
569 uint32_t M3PFD:1; /* Master x Prefetch Disable */
570 uint32_t M2PFD:1; /* Master x Prefetch Disable */
571 uint32_t M1PFD:1; /* Master x Prefetch Disable */
572 uint32_t M0PFD:1; /* Master x Prefetch Disable */
573 uint32_t M7AP:2; /* Master 7 Access Protection */
574 uint32_t M6AP:2; /* Master 6 Access Protection */
575 uint32_t M5AP:2; /* Master 5 Access Protection */
576 uint32_t M4AP:2; /* Master 4 Access Protection */
577 uint32_t M3AP:2; /* Master 3 Access Protection */
578 uint32_t M2AP:2; /* Master 2 Access Protection */
579 uint32_t M1AP:2; /* Master 1 Access Protection */
580 uint32_t M0AP:2; /* Master 0 Access Protection */
581 } B;
582 } CFLASH_PFAPR_32B_tag;
583
584 typedef union { /* UT0 - User Test Register */
585 uint32_t R;
586 struct {
587 uint32_t UTE:1; /* User Test Enable */
588 uint32_t SBCE:1; /* Single Bit Correction Enable */
589 uint32_t:6;
590 uint32_t DSI:8; /* Data Syndrome Input */
591 uint32_t:10;
592 uint32_t MRE:1; /* Margin Read Enable */
593 uint32_t MRV:1; /* Margin Read Value */
594 uint32_t EIE:1; /* ECC Data Input Enable */
595 uint32_t AIS:1; /* Array Integrity Sequence */
596 uint32_t AIE:1; /* Array Integrity Enable */
597 uint32_t AID:1; /* Array Integrity Done */
598 } B;
599 } CFLASH_UT0_32B_tag;
600
601 typedef union { /* UT1 - User Test Register */
602 uint32_t R;
603 } CFLASH_UT1_32B_tag;
604
605 typedef union { /* UT2 - User Test Register */
606 uint32_t R;
607 } CFLASH_UT2_32B_tag;
608
609
610 /* Register layout for all registers UM... */
611
612 typedef union { /* UM - User Multiple Input Signature Register */
613 uint32_t R;
614 struct {
615#ifndef USE_FIELD_ALIASES_CFLASH
616 uint32_t MISR:32; /* Multiple Input Signature */
617#else
618 uint32_t MS:32; /* deprecated - please avoid */
619#endif
620 } B;
621 } CFLASH_UM_32B_tag;
622
623
624 /* Register layout for generated register(s) UT... */
625
626 typedef union { /* */
627 uint32_t R;
628 } CFLASH_UT_32B_tag;
629
630
631 /* Register layout for generated register(s) PFCR... */
632
633 typedef union { /* */
634 uint32_t R;
635 } CFLASH_PFCR_32B_tag;
636
637
638
639 typedef struct CFLASH_struct_tag { /* start of CFLASH_tag */
640 /* MCR - Module Configuration Register */
641 CFLASH_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */
642 /* LML - Low/Mid Address Space Block Locking Register */
643 CFLASH_LML_32B_tag LML; /* offset: 0x0004 size: 32 bit */
644 /* HBL - High Address Space Block Locking Register */
645 CFLASH_HBL_32B_tag HBL; /* offset: 0x0008 size: 32 bit */
646 /* SLL - Secondary Low/Mid Address Space Block Locking Register */
647 CFLASH_SLL_32B_tag SLL; /* offset: 0x000C size: 32 bit */
648 /* LMS - Low/Mid Address Space Block Select Register */
649 CFLASH_LMS_32B_tag LMS; /* offset: 0x0010 size: 32 bit */
650 /* HBS - High Address Space Block Select Register */
651 CFLASH_HBS_32B_tag HBS; /* offset: 0x0014 size: 32 bit */
652 /* ADR - Address Register */
653 CFLASH_ADR_32B_tag ADR; /* offset: 0x0018 size: 32 bit */
654 union {
655 struct {
656 /* */
657 CFLASH_PFCR_32B_tag PFCR[2]; /* offset: 0x001C (0x0004 x 2) */
658 int8_t CFLASH_reserved_0024_E0[12];
659 };
660
661 /* Bus Interface Unit Register */
662 CFLASH_BIU_32B_tag BIU[5]; /* offset: 0x001C (0x0004 x 5) */
663
664 struct {
665 /* Bus Interface Unit Register */
666 CFLASH_BIU_32B_tag BIU0; /* offset: 0x001C size: 32 bit */
667 CFLASH_BIU_32B_tag BIU1; /* offset: 0x0020 size: 32 bit */
668 CFLASH_BIU_32B_tag BIU2; /* offset: 0x0024 size: 32 bit */
669 CFLASH_BIU_32B_tag BIU3; /* offset: 0x0028 size: 32 bit */
670 CFLASH_BIU_32B_tag BIU4; /* offset: 0x002C size: 32 bit */
671 };
672
673 struct {
674 int8_t CFLASH_reserved_001C_I3[8];
675 CFLASH_PFAPR_32B_tag FAPR; /* deprecated - please avoid */
676 int8_t CFLASH_reserved_0028_E3[8];
677 };
678
679 struct {
680 /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */
681 CFLASH_PFCR0_32B_tag PFCR0; /* offset: 0x001C size: 32 bit */
682 /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */
683 CFLASH_PFCR1_32B_tag PFCR1; /* offset: 0x0020 size: 32 bit */
684 /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */
685 CFLASH_PFAPR_32B_tag PFAPR; /* offset: 0x0024 size: 32 bit */
686 int8_t CFLASH_reserved_0028_E4[8];
687 };
688
689 };
690 int8_t CFLASH_reserved_0030_C[12];
691 union {
692 CFLASH_UT_32B_tag UT[3]; /* offset: 0x003C (0x0004 x 3) */
693
694 struct {
695 /* UT0 - User Test Register */
696 CFLASH_UT0_32B_tag UT0; /* offset: 0x003C size: 32 bit */
697 /* UT1 - User Test Register */
698 CFLASH_UT1_32B_tag UT1; /* offset: 0x0040 size: 32 bit */
699 /* UT2 - User Test Register */
700 CFLASH_UT2_32B_tag UT2; /* offset: 0x0044 size: 32 bit */
701 };
702
703 };
704 union {
705 CFLASH_UM_32B_tag UMISR[5]; /* offset: 0x0048 (0x0004 x 5) */
706
707 /* UM - User Multiple Input Signature Register */
708 CFLASH_UM_32B_tag UM[5]; /* offset: 0x0048 (0x0004 x 5) */
709
710 struct {
711 /* UM - User Multiple Input Signature Register */
712 CFLASH_UM_32B_tag UM0; /* offset: 0x0048 size: 32 bit */
713 CFLASH_UM_32B_tag UM1; /* offset: 0x004C size: 32 bit */
714 CFLASH_UM_32B_tag UM2; /* offset: 0x0050 size: 32 bit */
715 CFLASH_UM_32B_tag UM3; /* offset: 0x0054 size: 32 bit */
716 CFLASH_UM_32B_tag UM4; /* offset: 0x0058 size: 32 bit */
717 };
718
719 };
720 } CFLASH_tag;
721
722
723#define CFLASH (*(volatile CFLASH_tag *) 0xC3F88000UL)
724
725
726
727/****************************************************************/
728/* */
729/* Module: SIUL */
730/* */
731/****************************************************************/
732
733 typedef union { /* MIDR1 - MCU ID Register #1 */
734 uint32_t R;
735 struct {
736 uint32_t PARTNUM:16; /* MCU Part Number */
737 uint32_t CSP:1; /* CSP Package */
738 uint32_t PKG:5; /* Package Settings */
739 uint32_t:2;
740#ifndef USE_FIELD_ALIASES_SIUL
741 uint32_t MAJOR_MASK:4; /* Major Mask Revision */
742#else
743 uint32_t MAJORMASK:4; /* deprecated name - please avoid */
744#endif
745#ifndef USE_FIELD_ALIASES_SIUL
746 uint32_t MINOR_MASK:4; /* Minor Mask Revision */
747#else
748 uint32_t MINORMASK:4; /* deprecated name - please avoid */
749#endif
750 } B;
751 } SIUL_MIDR1_32B_tag;
752
753 typedef union { /* MIDR2 - MCU ID Register #2 */
754 uint32_t R;
755 struct {
756 uint32_t SF:1; /* Manufacturer */
757 uint32_t FLASH_SIZE_1:4; /* Coarse Flash Memory Size */
758 uint32_t FLASH_SIZE_2:4; /* Fine Flash Memory Size */
759 uint32_t:7;
760#ifndef USE_FIELD_ALIASES_SIUL
761 uint32_t PARTNUM2:8; /* MCU Part Number */
762#else
763 uint32_t PARTNUM:8; /* deprecated name - please avoid */
764#endif
765 uint32_t TBD:1; /* Optional Bit */
766 uint32_t:2;
767 uint32_t EE:1; /* Data Flash Present */
768 uint32_t:3;
769 uint32_t FR:1; /* Flexray Present */
770 } B;
771 } SIUL_MIDR2_32B_tag;
772
773 typedef union { /* ISR - Interrupt Status Flag Register */
774 uint32_t R;
775 struct {
776 uint32_t EIF31:1; /* External Interrupt Status Flag */
777 uint32_t EIF30:1; /* External Interrupt Status Flag */
778 uint32_t EIF29:1; /* External Interrupt Status Flag */
779 uint32_t EIF28:1; /* External Interrupt Status Flag */
780 uint32_t EIF27:1; /* External Interrupt Status Flag */
781 uint32_t EIF26:1; /* External Interrupt Status Flag */
782 uint32_t EIF25:1; /* External Interrupt Status Flag */
783 uint32_t EIF24:1; /* External Interrupt Status Flag */
784 uint32_t EIF23:1; /* External Interrupt Status Flag */
785 uint32_t EIF22:1; /* External Interrupt Status Flag */
786 uint32_t EIF21:1; /* External Interrupt Status Flag */
787 uint32_t EIF20:1; /* External Interrupt Status Flag */
788 uint32_t EIF19:1; /* External Interrupt Status Flag */
789 uint32_t EIF18:1; /* External Interrupt Status Flag */
790 uint32_t EIF17:1; /* External Interrupt Status Flag */
791 uint32_t EIF16:1; /* External Interrupt Status Flag */
792 uint32_t EIF15:1; /* External Interrupt Status Flag */
793 uint32_t EIF14:1; /* External Interrupt Status Flag */
794 uint32_t EIF13:1; /* External Interrupt Status Flag */
795 uint32_t EIF12:1; /* External Interrupt Status Flag */
796 uint32_t EIF11:1; /* External Interrupt Status Flag */
797 uint32_t EIF10:1; /* External Interrupt Status Flag */
798 uint32_t EIF9:1; /* External Interrupt Status Flag */
799 uint32_t EIF8:1; /* External Interrupt Status Flag */
800 uint32_t EIF7:1; /* External Interrupt Status Flag */
801 uint32_t EIF6:1; /* External Interrupt Status Flag */
802 uint32_t EIF5:1; /* External Interrupt Status Flag */
803 uint32_t EIF4:1; /* External Interrupt Status Flag */
804 uint32_t EIF3:1; /* External Interrupt Status Flag */
805 uint32_t EIF2:1; /* External Interrupt Status Flag */
806 uint32_t EIF1:1; /* External Interrupt Status Flag */
807 uint32_t EIF0:1; /* External Interrupt Status Flag */
808 } B;
809 } SIUL_ISR_32B_tag;
810
811 typedef union { /* IRER - Interrupt Request Enable Register */
812 uint32_t R;
813 struct {
814 uint32_t EIRE31:1; /* Enable External Interrupt Requests */
815 uint32_t EIRE30:1; /* Enable External Interrupt Requests */
816 uint32_t EIRE29:1; /* Enable External Interrupt Requests */
817 uint32_t EIRE28:1; /* Enable External Interrupt Requests */
818 uint32_t EIRE27:1; /* Enable External Interrupt Requests */
819 uint32_t EIRE26:1; /* Enable External Interrupt Requests */
820 uint32_t EIRE25:1; /* Enable External Interrupt Requests */
821 uint32_t EIRE24:1; /* Enable External Interrupt Requests */
822 uint32_t EIRE23:1; /* Enable External Interrupt Requests */
823 uint32_t EIRE22:1; /* Enable External Interrupt Requests */
824 uint32_t EIRE21:1; /* Enable External Interrupt Requests */
825 uint32_t EIRE20:1; /* Enable External Interrupt Requests */
826 uint32_t EIRE19:1; /* Enable External Interrupt Requests */
827 uint32_t EIRE18:1; /* Enable External Interrupt Requests */
828 uint32_t EIRE17:1; /* Enable External Interrupt Requests */
829 uint32_t EIRE16:1; /* Enable External Interrupt Requests */
830 uint32_t EIRE15:1; /* Enable External Interrupt Requests */
831 uint32_t EIRE14:1; /* Enable External Interrupt Requests */
832 uint32_t EIRE13:1; /* Enable External Interrupt Requests */
833 uint32_t EIRE12:1; /* Enable External Interrupt Requests */
834 uint32_t EIRE11:1; /* Enable External Interrupt Requests */
835 uint32_t EIRE10:1; /* Enable External Interrupt Requests */
836 uint32_t EIRE9:1; /* Enable External Interrupt Requests */
837 uint32_t EIRE8:1; /* Enable External Interrupt Requests */
838 uint32_t EIRE7:1; /* Enable External Interrupt Requests */
839 uint32_t EIRE6:1; /* Enable External Interrupt Requests */
840 uint32_t EIRE5:1; /* Enable External Interrupt Requests */
841 uint32_t EIRE4:1; /* Enable External Interrupt Requests */
842 uint32_t EIRE3:1; /* Enable External Interrupt Requests */
843 uint32_t EIRE2:1; /* Enable External Interrupt Requests */
844 uint32_t EIRE1:1; /* Enable External Interrupt Requests */
845 uint32_t EIRE0:1; /* Enable External Interrupt Requests */
846 } B;
847 } SIUL_IRER_32B_tag;
848
849 typedef union { /* IREER - Interrupt Rising Edge Event Enable */
850 uint32_t R;
851 struct {
852 uint32_t IREE31:1; /* Enable rising-edge events */
853 uint32_t IREE30:1; /* Enable rising-edge events */
854 uint32_t IREE29:1; /* Enable rising-edge events */
855 uint32_t IREE28:1; /* Enable rising-edge events */
856 uint32_t IREE27:1; /* Enable rising-edge events */
857 uint32_t IREE26:1; /* Enable rising-edge events */
858 uint32_t IREE25:1; /* Enable rising-edge events */
859 uint32_t IREE24:1; /* Enable rising-edge events */
860 uint32_t IREE23:1; /* Enable rising-edge events */
861 uint32_t IREE22:1; /* Enable rising-edge events */
862 uint32_t IREE21:1; /* Enable rising-edge events */
863 uint32_t IREE20:1; /* Enable rising-edge events */
864 uint32_t IREE19:1; /* Enable rising-edge events */
865 uint32_t IREE18:1; /* Enable rising-edge events */
866 uint32_t IREE17:1; /* Enable rising-edge events */
867 uint32_t IREE16:1; /* Enable rising-edge events */
868 uint32_t IREE15:1; /* Enable rising-edge events */
869 uint32_t IREE14:1; /* Enable rising-edge events */
870 uint32_t IREE13:1; /* Enable rising-edge events */
871 uint32_t IREE12:1; /* Enable rising-edge events */
872 uint32_t IREE11:1; /* Enable rising-edge events */
873 uint32_t IREE10:1; /* Enable rising-edge events */
874 uint32_t IREE9:1; /* Enable rising-edge events */
875 uint32_t IREE8:1; /* Enable rising-edge events */
876 uint32_t IREE7:1; /* Enable rising-edge events */
877 uint32_t IREE6:1; /* Enable rising-edge events */
878 uint32_t IREE5:1; /* Enable rising-edge events */
879 uint32_t IREE4:1; /* Enable rising-edge events */
880 uint32_t IREE3:1; /* Enable rising-edge events */
881 uint32_t IREE2:1; /* Enable rising-edge events */
882 uint32_t IREE1:1; /* Enable rising-edge events */
883 uint32_t IREE0:1; /* Enable rising-edge events */
884 } B;
885 } SIUL_IREER_32B_tag;
886
887 typedef union { /* IFEER - Interrupt Falling-Edge Event Enable */
888 uint32_t R;
889 struct {
890 uint32_t IFEE31:1; /* Enable Falling Edge Events */
891 uint32_t IFEE30:1; /* Enable Falling Edge Events */
892 uint32_t IFEE29:1; /* Enable Falling Edge Events */
893 uint32_t IFEE28:1; /* Enable Falling Edge Events */
894 uint32_t IFEE27:1; /* Enable Falling Edge Events */
895 uint32_t IFEE26:1; /* Enable Falling Edge Events */
896 uint32_t IFEE25:1; /* Enable Falling Edge Events */
897 uint32_t IFEE24:1; /* Enable Falling Edge Events */
898 uint32_t IFEE23:1; /* Enable Falling Edge Events */
899 uint32_t IFEE22:1; /* Enable Falling Edge Events */
900 uint32_t IFEE21:1; /* Enable Falling Edge Events */
901 uint32_t IFEE20:1; /* Enable Falling Edge Events */
902 uint32_t IFEE19:1; /* Enable Falling Edge Events */
903 uint32_t IFEE18:1; /* Enable Falling Edge Events */
904 uint32_t IFEE17:1; /* Enable Falling Edge Events */
905 uint32_t IFEE16:1; /* Enable Falling Edge Events */
906 uint32_t IFEE15:1; /* Enable Falling Edge Events */
907 uint32_t IFEE14:1; /* Enable Falling Edge Events */
908 uint32_t IFEE13:1; /* Enable Falling Edge Events */
909 uint32_t IFEE12:1; /* Enable Falling Edge Events */
910 uint32_t IFEE11:1; /* Enable Falling Edge Events */
911 uint32_t IFEE10:1; /* Enable Falling Edge Events */
912 uint32_t IFEE9:1; /* Enable Falling Edge Events */
913 uint32_t IFEE8:1; /* Enable Falling Edge Events */
914 uint32_t IFEE7:1; /* Enable Falling Edge Events */
915 uint32_t IFEE6:1; /* Enable Falling Edge Events */
916 uint32_t IFEE5:1; /* Enable Falling Edge Events */
917 uint32_t IFEE4:1; /* Enable Falling Edge Events */
918 uint32_t IFEE3:1; /* Enable Falling Edge Events */
919 uint32_t IFEE2:1; /* Enable Falling Edge Events */
920 uint32_t IFEE1:1; /* Enable Falling Edge Events */
921 uint32_t IFEE0:1; /* Enable Falling Edge Events */
922 } B;
923 } SIUL_IFEER_32B_tag;
924
925 typedef union { /* IFER Interrupt Filter Enable Register */
926 uint32_t R;
927 struct {
928 uint32_t IFE31:1; /* Enable Digital Glitch Filter */
929 uint32_t IFE30:1; /* Enable Digital Glitch Filter */
930 uint32_t IFE29:1; /* Enable Digital Glitch Filter */
931 uint32_t IFE28:1; /* Enable Digital Glitch Filter */
932 uint32_t IFE27:1; /* Enable Digital Glitch Filter */
933 uint32_t IFE26:1; /* Enable Digital Glitch Filter */
934 uint32_t IFE25:1; /* Enable Digital Glitch Filter */
935 uint32_t IFE24:1; /* Enable Digital Glitch Filter */
936 uint32_t IFE23:1; /* Enable Digital Glitch Filter */
937 uint32_t IFE22:1; /* Enable Digital Glitch Filter */
938 uint32_t IFE21:1; /* Enable Digital Glitch Filter */
939 uint32_t IFE20:1; /* Enable Digital Glitch Filter */
940 uint32_t IFE19:1; /* Enable Digital Glitch Filter */
941 uint32_t IFE18:1; /* Enable Digital Glitch Filter */
942 uint32_t IFE17:1; /* Enable Digital Glitch Filter */
943 uint32_t IFE16:1; /* Enable Digital Glitch Filter */
944 uint32_t IFE15:1; /* Enable Digital Glitch Filter */
945 uint32_t IFE14:1; /* Enable Digital Glitch Filter */
946 uint32_t IFE13:1; /* Enable Digital Glitch Filter */
947 uint32_t IFE12:1; /* Enable Digital Glitch Filter */
948 uint32_t IFE11:1; /* Enable Digital Glitch Filter */
949 uint32_t IFE10:1; /* Enable Digital Glitch Filter */
950 uint32_t IFE9:1; /* Enable Digital Glitch Filter */
951 uint32_t IFE8:1; /* Enable Digital Glitch Filter */
952 uint32_t IFE7:1; /* Enable Digital Glitch Filter */
953 uint32_t IFE6:1; /* Enable Digital Glitch Filter */
954 uint32_t IFE5:1; /* Enable Digital Glitch Filter */
955 uint32_t IFE4:1; /* Enable Digital Glitch Filter */
956 uint32_t IFE3:1; /* Enable Digital Glitch Filter */
957 uint32_t IFE2:1; /* Enable Digital Glitch Filter */
958 uint32_t IFE1:1; /* Enable Digital Glitch Filter */
959 uint32_t IFE0:1; /* Enable Digital Glitch Filter */
960 } B;
961 } SIUL_IFER_32B_tag;
962
963
964 /* Register layout for all registers PCR... */
965
966 typedef union SIU_PCR_tag { /* PCR - Pad Configuration Register */
967 uint16_t R;
968 struct {
969 uint16_t:1;
970#ifndef USE_FIELD_ALIASES_SIUL
971 uint16_t SMC:1; /* Safe Mode Control */
972#else
973 uint16_t SME:1; /* deprecated name - please avoid */
974#endif
975 uint16_t APC:1; /* Analog Pad Control */
976 uint16_t:1;
977 uint16_t PA:2; /* Pad Output Assignment */
978 uint16_t OBE:1; /* Output Buffer Enable */
979 uint16_t IBE:1; /* Input Buffer Enable */
980#ifndef USE_FIELD_ALIASES_SIUL
981 uint16_t DSC:2; /* Drive Strength Control */
982#else
983 uint16_t DCS:2; /* deprecated name - please avoid */
984#endif
985 uint16_t ODE:1; /* Open Drain Output Enable */
986 uint16_t HYS:1; /* Input Hysteresis */
987 uint16_t SRC:2; /* Slew Rate Control */
988 uint16_t WPE:1; /* Weak Pull Up/Down Enable */
989 uint16_t WPS:1; /* Weak Pull Up/Down Select */
990 } B;
991 } SIU_PCR_tag;
992
993
994 /* Register layout for all registers PSMI... */
995
996 typedef union SIUL_PSMI_8B_tag { /* PSMI - Pad Selection for Multiplexed Inputs */
997 uint8_t R;
998 struct {
999 uint8_t:4;
1000 uint8_t PADSEL:4; /* Pad selection for pin */
1001 } B;
1002 } SIUL_PSMI_8B_tag;
1003
1004
1005 /* Register layout for all registers PSMI... */
1006
1007 typedef union { /* PSMI - Pad Selection for Multiplexed Inputs */
1008 uint32_t R;
1009 struct {
1010 uint32_t:4;
1011 uint32_t PADSEL0:4; /* Pad selection for pin */
1012 uint32_t:4;
1013 uint32_t PADSEL1:4; /* Pad selection for pin */
1014 uint32_t:4;
1015 uint32_t PADSEL2:4; /* Pad selection for pin */
1016 uint32_t:4;
1017 uint32_t PADSEL3:4; /* Pad selection for pin */
1018 } B;
1019 } SIUL_PSMI_32B_tag;
1020
1021
1022 /* Register layout for all registers GPDO... */
1023
1024 typedef union { /* GPDO - GPIO Pad Data Output Register */
1025 uint8_t R;
1026 struct {
1027 uint8_t:7;
1028 uint8_t PDO:1; /* Pad Data Out */
1029 } B;
1030 } SIUL_GPDO_8B_tag;
1031
1032
1033 /* Register layout for all registers GPDO... */
1034
1035 typedef union { /* GPDO - GPIO Pad Data Output Register */
1036 uint32_t R;
1037 struct {
1038 uint32_t:7;
1039 uint32_t PDO0:1; /* Pad Data Out */
1040 uint32_t:7;
1041 uint32_t PDO1:1; /* Pad Data Out */
1042 uint32_t:7;
1043 uint32_t PDO2:1; /* Pad Data Out */
1044 uint32_t:7;
1045 uint32_t PDO3:1; /* Pad Data Out */
1046 } B;
1047 } SIUL_GPDO_32B_tag;
1048
1049
1050 /* Register layout for all registers GPDI... */
1051
1052 typedef union { /* GPDI - GPIO Pad Data Input Register */
1053 uint8_t R;
1054 struct {
1055 uint8_t:7;
1056 uint8_t PDI:1; /* Pad Data In */
1057 } B;
1058 } SIUL_GPDI_8B_tag;
1059
1060
1061 /* Register layout for all registers GPDI... */
1062
1063 typedef union { /* GPDI - GPIO Pad Data Input Register */
1064 uint32_t R;
1065 struct {
1066 uint32_t:7;
1067 uint32_t PDI0:1; /* Pad Data In */
1068 uint32_t:7;
1069 uint32_t PDI1:1; /* Pad Data In */
1070 uint32_t:7;
1071 uint32_t PDI2:1; /* Pad Data In */
1072 uint32_t:7;
1073 uint32_t PDI3:1; /* Pad Data In */
1074 } B;
1075 } SIUL_GPDI_32B_tag;
1076
1077
1078 /* Register layout for all registers PGPDO... */
1079
1080 typedef union { /* PGPDO - Parallel GPIO Pad Data Out Register */
1081 uint16_t R;
1082 } SIUL_PGPDO_16B_tag;
1083
1084
1085 /* Register layout for all registers PGPDI... */
1086
1087 typedef union { /* PGPDI - Parallel GPIO Pad Data In Register */
1088 uint16_t R;
1089 } SIUL_PGPDI_16B_tag;
1090
1091
1092 /* Register layout for all registers MPGPDO... */
1093
1094 typedef union { /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
1095 uint32_t R;
1096 struct {
1097 uint32_t MASK:16; /* Mask Field */
1098 uint32_t MPPDO:16; /* Masked Parallel Pad Data Out */
1099 } B;
1100 } SIUL_MPGPDO_32B_tag;
1101
1102
1103 /* Register layout for all registers IFMC... */
1104
1105 typedef union { /* IFMC - Interrupt Filter Maximum Counter Register */
1106 uint32_t R;
1107 struct {
1108 uint32_t:28;
1109 uint32_t MAXCNT:4; /* Maximum Interrupt Filter Counter Setting */
1110 } B;
1111 } SIUL_IFMC_32B_tag;
1112
1113 typedef union { /* IFCPR - Inerrupt Filter Clock Prescaler Register */
1114 uint32_t R;
1115 struct {
1116 uint32_t:28;
1117 uint32_t IFCP:4; /* Interrupt Filter Clock Prescaler Setting */
1118 } B;
1119 } SIUL_IFCPR_32B_tag;
1120
1121
1122
1123 typedef struct SIU_tag { /* start of SIUL_tag */
1124 int8_t SIUL_reserved_0000_C[4];
1125 union {
1126 SIUL_MIDR1_32B_tag MIDR; /* deprecated - please avoid */
1127
1128 /* MIDR1 - MCU ID Register #1 */
1129 SIUL_MIDR1_32B_tag MIDR1; /* offset: 0x0004 size: 32 bit */
1130
1131 };
1132 /* MIDR2 - MCU ID Register #2 */
1133 SIUL_MIDR2_32B_tag MIDR2; /* offset: 0x0008 size: 32 bit */
1134 int8_t SIUL_reserved_000C[8];
1135 /* ISR - Interrupt Status Flag Register */
1136 SIUL_ISR_32B_tag ISR; /* offset: 0x0014 size: 32 bit */
1137 /* IRER - Interrupt Request Enable Register */
1138 SIUL_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */
1139 int8_t SIUL_reserved_001C[12];
1140 /* IREER - Interrupt Rising Edge Event Enable */
1141 SIUL_IREER_32B_tag IREER; /* offset: 0x0028 size: 32 bit */
1142 /* IFEER - Interrupt Falling-Edge Event Enable */
1143 SIUL_IFEER_32B_tag IFEER; /* offset: 0x002C size: 32 bit */
1144 /* IFER Interrupt Filter Enable Register */
1145 SIUL_IFER_32B_tag IFER; /* offset: 0x0030 size: 32 bit */
1146 int8_t SIUL_reserved_0034_C[12];
1147 union {
1148 /* PCR - Pad Configuration Register */
1149 SIU_PCR_tag PCR[512]; /* offset: 0x0040 (0x0002 x 512) */
1150
1151 struct {
1152 /* PCR - Pad Configuration Register */
1153 SIU_PCR_tag PCR0; /* offset: 0x0040 size: 16 bit */
1154 SIU_PCR_tag PCR1; /* offset: 0x0042 size: 16 bit */
1155 SIU_PCR_tag PCR2; /* offset: 0x0044 size: 16 bit */
1156 SIU_PCR_tag PCR3; /* offset: 0x0046 size: 16 bit */
1157 SIU_PCR_tag PCR4; /* offset: 0x0048 size: 16 bit */
1158 SIU_PCR_tag PCR5; /* offset: 0x004A size: 16 bit */
1159 SIU_PCR_tag PCR6; /* offset: 0x004C size: 16 bit */
1160 SIU_PCR_tag PCR7; /* offset: 0x004E size: 16 bit */
1161 SIU_PCR_tag PCR8; /* offset: 0x0050 size: 16 bit */
1162 SIU_PCR_tag PCR9; /* offset: 0x0052 size: 16 bit */
1163 SIU_PCR_tag PCR10; /* offset: 0x0054 size: 16 bit */
1164 SIU_PCR_tag PCR11; /* offset: 0x0056 size: 16 bit */
1165 SIU_PCR_tag PCR12; /* offset: 0x0058 size: 16 bit */
1166 SIU_PCR_tag PCR13; /* offset: 0x005A size: 16 bit */
1167 SIU_PCR_tag PCR14; /* offset: 0x005C size: 16 bit */
1168 SIU_PCR_tag PCR15; /* offset: 0x005E size: 16 bit */
1169 SIU_PCR_tag PCR16; /* offset: 0x0060 size: 16 bit */
1170 SIU_PCR_tag PCR17; /* offset: 0x0062 size: 16 bit */
1171 SIU_PCR_tag PCR18; /* offset: 0x0064 size: 16 bit */
1172 SIU_PCR_tag PCR19; /* offset: 0x0066 size: 16 bit */
1173 SIU_PCR_tag PCR20; /* offset: 0x0068 size: 16 bit */
1174 SIU_PCR_tag PCR21; /* offset: 0x006A size: 16 bit */
1175 SIU_PCR_tag PCR22; /* offset: 0x006C size: 16 bit */
1176 SIU_PCR_tag PCR23; /* offset: 0x006E size: 16 bit */
1177 SIU_PCR_tag PCR24; /* offset: 0x0070 size: 16 bit */
1178 SIU_PCR_tag PCR25; /* offset: 0x0072 size: 16 bit */
1179 SIU_PCR_tag PCR26; /* offset: 0x0074 size: 16 bit */
1180 SIU_PCR_tag PCR27; /* offset: 0x0076 size: 16 bit */
1181 SIU_PCR_tag PCR28; /* offset: 0x0078 size: 16 bit */
1182 SIU_PCR_tag PCR29; /* offset: 0x007A size: 16 bit */
1183 SIU_PCR_tag PCR30; /* offset: 0x007C size: 16 bit */
1184 SIU_PCR_tag PCR31; /* offset: 0x007E size: 16 bit */
1185 SIU_PCR_tag PCR32; /* offset: 0x0080 size: 16 bit */
1186 SIU_PCR_tag PCR33; /* offset: 0x0082 size: 16 bit */
1187 SIU_PCR_tag PCR34; /* offset: 0x0084 size: 16 bit */
1188 SIU_PCR_tag PCR35; /* offset: 0x0086 size: 16 bit */
1189 SIU_PCR_tag PCR36; /* offset: 0x0088 size: 16 bit */
1190 SIU_PCR_tag PCR37; /* offset: 0x008A size: 16 bit */
1191 SIU_PCR_tag PCR38; /* offset: 0x008C size: 16 bit */
1192 SIU_PCR_tag PCR39; /* offset: 0x008E size: 16 bit */
1193 SIU_PCR_tag PCR40; /* offset: 0x0090 size: 16 bit */
1194 SIU_PCR_tag PCR41; /* offset: 0x0092 size: 16 bit */
1195 SIU_PCR_tag PCR42; /* offset: 0x0094 size: 16 bit */
1196 SIU_PCR_tag PCR43; /* offset: 0x0096 size: 16 bit */
1197 SIU_PCR_tag PCR44; /* offset: 0x0098 size: 16 bit */
1198 SIU_PCR_tag PCR45; /* offset: 0x009A size: 16 bit */
1199 SIU_PCR_tag PCR46; /* offset: 0x009C size: 16 bit */
1200 SIU_PCR_tag PCR47; /* offset: 0x009E size: 16 bit */
1201 SIU_PCR_tag PCR48; /* offset: 0x00A0 size: 16 bit */
1202 SIU_PCR_tag PCR49; /* offset: 0x00A2 size: 16 bit */
1203 SIU_PCR_tag PCR50; /* offset: 0x00A4 size: 16 bit */
1204 SIU_PCR_tag PCR51; /* offset: 0x00A6 size: 16 bit */
1205 SIU_PCR_tag PCR52; /* offset: 0x00A8 size: 16 bit */
1206 SIU_PCR_tag PCR53; /* offset: 0x00AA size: 16 bit */
1207 SIU_PCR_tag PCR54; /* offset: 0x00AC size: 16 bit */
1208 SIU_PCR_tag PCR55; /* offset: 0x00AE size: 16 bit */
1209 SIU_PCR_tag PCR56; /* offset: 0x00B0 size: 16 bit */
1210 SIU_PCR_tag PCR57; /* offset: 0x00B2 size: 16 bit */
1211 SIU_PCR_tag PCR58; /* offset: 0x00B4 size: 16 bit */
1212 SIU_PCR_tag PCR59; /* offset: 0x00B6 size: 16 bit */
1213 SIU_PCR_tag PCR60; /* offset: 0x00B8 size: 16 bit */
1214 SIU_PCR_tag PCR61; /* offset: 0x00BA size: 16 bit */
1215 SIU_PCR_tag PCR62; /* offset: 0x00BC size: 16 bit */
1216 SIU_PCR_tag PCR63; /* offset: 0x00BE size: 16 bit */
1217 SIU_PCR_tag PCR64; /* offset: 0x00C0 size: 16 bit */
1218 SIU_PCR_tag PCR65; /* offset: 0x00C2 size: 16 bit */
1219 SIU_PCR_tag PCR66; /* offset: 0x00C4 size: 16 bit */
1220 SIU_PCR_tag PCR67; /* offset: 0x00C6 size: 16 bit */
1221 SIU_PCR_tag PCR68; /* offset: 0x00C8 size: 16 bit */
1222 SIU_PCR_tag PCR69; /* offset: 0x00CA size: 16 bit */
1223 SIU_PCR_tag PCR70; /* offset: 0x00CC size: 16 bit */
1224 SIU_PCR_tag PCR71; /* offset: 0x00CE size: 16 bit */
1225 SIU_PCR_tag PCR72; /* offset: 0x00D0 size: 16 bit */
1226 SIU_PCR_tag PCR73; /* offset: 0x00D2 size: 16 bit */
1227 SIU_PCR_tag PCR74; /* offset: 0x00D4 size: 16 bit */
1228 SIU_PCR_tag PCR75; /* offset: 0x00D6 size: 16 bit */
1229 SIU_PCR_tag PCR76; /* offset: 0x00D8 size: 16 bit */
1230 SIU_PCR_tag PCR77; /* offset: 0x00DA size: 16 bit */
1231 SIU_PCR_tag PCR78; /* offset: 0x00DC size: 16 bit */
1232 SIU_PCR_tag PCR79; /* offset: 0x00DE size: 16 bit */
1233 SIU_PCR_tag PCR80; /* offset: 0x00E0 size: 16 bit */
1234 SIU_PCR_tag PCR81; /* offset: 0x00E2 size: 16 bit */
1235 SIU_PCR_tag PCR82; /* offset: 0x00E4 size: 16 bit */
1236 SIU_PCR_tag PCR83; /* offset: 0x00E6 size: 16 bit */
1237 SIU_PCR_tag PCR84; /* offset: 0x00E8 size: 16 bit */
1238 SIU_PCR_tag PCR85; /* offset: 0x00EA size: 16 bit */
1239 SIU_PCR_tag PCR86; /* offset: 0x00EC size: 16 bit */
1240 SIU_PCR_tag PCR87; /* offset: 0x00EE size: 16 bit */
1241 SIU_PCR_tag PCR88; /* offset: 0x00F0 size: 16 bit */
1242 SIU_PCR_tag PCR89; /* offset: 0x00F2 size: 16 bit */
1243 SIU_PCR_tag PCR90; /* offset: 0x00F4 size: 16 bit */
1244 SIU_PCR_tag PCR91; /* offset: 0x00F6 size: 16 bit */
1245 SIU_PCR_tag PCR92; /* offset: 0x00F8 size: 16 bit */
1246 SIU_PCR_tag PCR93; /* offset: 0x00FA size: 16 bit */
1247 SIU_PCR_tag PCR94; /* offset: 0x00FC size: 16 bit */
1248 SIU_PCR_tag PCR95; /* offset: 0x00FE size: 16 bit */
1249 SIU_PCR_tag PCR96; /* offset: 0x0100 size: 16 bit */
1250 SIU_PCR_tag PCR97; /* offset: 0x0102 size: 16 bit */
1251 SIU_PCR_tag PCR98; /* offset: 0x0104 size: 16 bit */
1252 SIU_PCR_tag PCR99; /* offset: 0x0106 size: 16 bit */
1253 SIU_PCR_tag PCR100; /* offset: 0x0108 size: 16 bit */
1254 SIU_PCR_tag PCR101; /* offset: 0x010A size: 16 bit */
1255 SIU_PCR_tag PCR102; /* offset: 0x010C size: 16 bit */
1256 SIU_PCR_tag PCR103; /* offset: 0x010E size: 16 bit */
1257 SIU_PCR_tag PCR104; /* offset: 0x0110 size: 16 bit */
1258 SIU_PCR_tag PCR105; /* offset: 0x0112 size: 16 bit */
1259 SIU_PCR_tag PCR106; /* offset: 0x0114 size: 16 bit */
1260 SIU_PCR_tag PCR107; /* offset: 0x0116 size: 16 bit */
1261 SIU_PCR_tag PCR108; /* offset: 0x0118 size: 16 bit */
1262 SIU_PCR_tag PCR109; /* offset: 0x011A size: 16 bit */
1263 SIU_PCR_tag PCR110; /* offset: 0x011C size: 16 bit */
1264 SIU_PCR_tag PCR111; /* offset: 0x011E size: 16 bit */
1265 SIU_PCR_tag PCR112; /* offset: 0x0120 size: 16 bit */
1266 SIU_PCR_tag PCR113; /* offset: 0x0122 size: 16 bit */
1267 SIU_PCR_tag PCR114; /* offset: 0x0124 size: 16 bit */
1268 SIU_PCR_tag PCR115; /* offset: 0x0126 size: 16 bit */
1269 SIU_PCR_tag PCR116; /* offset: 0x0128 size: 16 bit */
1270 SIU_PCR_tag PCR117; /* offset: 0x012A size: 16 bit */
1271 SIU_PCR_tag PCR118; /* offset: 0x012C size: 16 bit */
1272 SIU_PCR_tag PCR119; /* offset: 0x012E size: 16 bit */
1273 SIU_PCR_tag PCR120; /* offset: 0x0130 size: 16 bit */
1274 SIU_PCR_tag PCR121; /* offset: 0x0132 size: 16 bit */
1275 SIU_PCR_tag PCR122; /* offset: 0x0134 size: 16 bit */
1276 SIU_PCR_tag PCR123; /* offset: 0x0136 size: 16 bit */
1277 SIU_PCR_tag PCR124; /* offset: 0x0138 size: 16 bit */
1278 SIU_PCR_tag PCR125; /* offset: 0x013A size: 16 bit */
1279 SIU_PCR_tag PCR126; /* offset: 0x013C size: 16 bit */
1280 SIU_PCR_tag PCR127; /* offset: 0x013E size: 16 bit */
1281 SIU_PCR_tag PCR128; /* offset: 0x0140 size: 16 bit */
1282 SIU_PCR_tag PCR129; /* offset: 0x0142 size: 16 bit */
1283 SIU_PCR_tag PCR130; /* offset: 0x0144 size: 16 bit */
1284 SIU_PCR_tag PCR131; /* offset: 0x0146 size: 16 bit */
1285 SIU_PCR_tag PCR132; /* offset: 0x0148 size: 16 bit */
1286 SIU_PCR_tag PCR133; /* offset: 0x014A size: 16 bit */
1287 SIU_PCR_tag PCR134; /* offset: 0x014C size: 16 bit */
1288 SIU_PCR_tag PCR135; /* offset: 0x014E size: 16 bit */
1289 SIU_PCR_tag PCR136; /* offset: 0x0150 size: 16 bit */
1290 SIU_PCR_tag PCR137; /* offset: 0x0152 size: 16 bit */
1291 SIU_PCR_tag PCR138; /* offset: 0x0154 size: 16 bit */
1292 SIU_PCR_tag PCR139; /* offset: 0x0156 size: 16 bit */
1293 SIU_PCR_tag PCR140; /* offset: 0x0158 size: 16 bit */
1294 SIU_PCR_tag PCR141; /* offset: 0x015A size: 16 bit */
1295 SIU_PCR_tag PCR142; /* offset: 0x015C size: 16 bit */
1296 SIU_PCR_tag PCR143; /* offset: 0x015E size: 16 bit */
1297 SIU_PCR_tag PCR144; /* offset: 0x0160 size: 16 bit */
1298 SIU_PCR_tag PCR145; /* offset: 0x0162 size: 16 bit */
1299 SIU_PCR_tag PCR146; /* offset: 0x0164 size: 16 bit */
1300 SIU_PCR_tag PCR147; /* offset: 0x0166 size: 16 bit */
1301 SIU_PCR_tag PCR148; /* offset: 0x0168 size: 16 bit */
1302 SIU_PCR_tag PCR149; /* offset: 0x016A size: 16 bit */
1303 SIU_PCR_tag PCR150; /* offset: 0x016C size: 16 bit */
1304 SIU_PCR_tag PCR151; /* offset: 0x016E size: 16 bit */
1305 SIU_PCR_tag PCR152; /* offset: 0x0170 size: 16 bit */
1306 SIU_PCR_tag PCR153; /* offset: 0x0172 size: 16 bit */
1307 SIU_PCR_tag PCR154; /* offset: 0x0174 size: 16 bit */
1308 SIU_PCR_tag PCR155; /* offset: 0x0176 size: 16 bit */
1309 SIU_PCR_tag PCR156; /* offset: 0x0178 size: 16 bit */
1310 SIU_PCR_tag PCR157; /* offset: 0x017A size: 16 bit */
1311 SIU_PCR_tag PCR158; /* offset: 0x017C size: 16 bit */
1312 SIU_PCR_tag PCR159; /* offset: 0x017E size: 16 bit */
1313 SIU_PCR_tag PCR160; /* offset: 0x0180 size: 16 bit */
1314 SIU_PCR_tag PCR161; /* offset: 0x0182 size: 16 bit */
1315 SIU_PCR_tag PCR162; /* offset: 0x0184 size: 16 bit */
1316 SIU_PCR_tag PCR163; /* offset: 0x0186 size: 16 bit */
1317 SIU_PCR_tag PCR164; /* offset: 0x0188 size: 16 bit */
1318 SIU_PCR_tag PCR165; /* offset: 0x018A size: 16 bit */
1319 SIU_PCR_tag PCR166; /* offset: 0x018C size: 16 bit */
1320 SIU_PCR_tag PCR167; /* offset: 0x018E size: 16 bit */
1321 SIU_PCR_tag PCR168; /* offset: 0x0190 size: 16 bit */
1322 SIU_PCR_tag PCR169; /* offset: 0x0192 size: 16 bit */
1323 SIU_PCR_tag PCR170; /* offset: 0x0194 size: 16 bit */
1324 SIU_PCR_tag PCR171; /* offset: 0x0196 size: 16 bit */
1325 SIU_PCR_tag PCR172; /* offset: 0x0198 size: 16 bit */
1326 SIU_PCR_tag PCR173; /* offset: 0x019A size: 16 bit */
1327 SIU_PCR_tag PCR174; /* offset: 0x019C size: 16 bit */
1328 SIU_PCR_tag PCR175; /* offset: 0x019E size: 16 bit */
1329 SIU_PCR_tag PCR176; /* offset: 0x01A0 size: 16 bit */
1330 SIU_PCR_tag PCR177; /* offset: 0x01A2 size: 16 bit */
1331 SIU_PCR_tag PCR178; /* offset: 0x01A4 size: 16 bit */
1332 SIU_PCR_tag PCR179; /* offset: 0x01A6 size: 16 bit */
1333 SIU_PCR_tag PCR180; /* offset: 0x01A8 size: 16 bit */
1334 SIU_PCR_tag PCR181; /* offset: 0x01AA size: 16 bit */
1335 SIU_PCR_tag PCR182; /* offset: 0x01AC size: 16 bit */
1336 SIU_PCR_tag PCR183; /* offset: 0x01AE size: 16 bit */
1337 SIU_PCR_tag PCR184; /* offset: 0x01B0 size: 16 bit */
1338 SIU_PCR_tag PCR185; /* offset: 0x01B2 size: 16 bit */
1339 SIU_PCR_tag PCR186; /* offset: 0x01B4 size: 16 bit */
1340 SIU_PCR_tag PCR187; /* offset: 0x01B6 size: 16 bit */
1341 SIU_PCR_tag PCR188; /* offset: 0x01B8 size: 16 bit */
1342 SIU_PCR_tag PCR189; /* offset: 0x01BA size: 16 bit */
1343 SIU_PCR_tag PCR190; /* offset: 0x01BC size: 16 bit */
1344 SIU_PCR_tag PCR191; /* offset: 0x01BE size: 16 bit */
1345 SIU_PCR_tag PCR192; /* offset: 0x01C0 size: 16 bit */
1346 SIU_PCR_tag PCR193; /* offset: 0x01C2 size: 16 bit */
1347 SIU_PCR_tag PCR194; /* offset: 0x01C4 size: 16 bit */
1348 SIU_PCR_tag PCR195; /* offset: 0x01C6 size: 16 bit */
1349 SIU_PCR_tag PCR196; /* offset: 0x01C8 size: 16 bit */
1350 SIU_PCR_tag PCR197; /* offset: 0x01CA size: 16 bit */
1351 SIU_PCR_tag PCR198; /* offset: 0x01CC size: 16 bit */
1352 SIU_PCR_tag PCR199; /* offset: 0x01CE size: 16 bit */
1353 SIU_PCR_tag PCR200; /* offset: 0x01D0 size: 16 bit */
1354 SIU_PCR_tag PCR201; /* offset: 0x01D2 size: 16 bit */
1355 SIU_PCR_tag PCR202; /* offset: 0x01D4 size: 16 bit */
1356 SIU_PCR_tag PCR203; /* offset: 0x01D6 size: 16 bit */
1357 SIU_PCR_tag PCR204; /* offset: 0x01D8 size: 16 bit */
1358 SIU_PCR_tag PCR205; /* offset: 0x01DA size: 16 bit */
1359 SIU_PCR_tag PCR206; /* offset: 0x01DC size: 16 bit */
1360 SIU_PCR_tag PCR207; /* offset: 0x01DE size: 16 bit */
1361 SIU_PCR_tag PCR208; /* offset: 0x01E0 size: 16 bit */
1362 SIU_PCR_tag PCR209; /* offset: 0x01E2 size: 16 bit */
1363 SIU_PCR_tag PCR210; /* offset: 0x01E4 size: 16 bit */
1364 SIU_PCR_tag PCR211; /* offset: 0x01E6 size: 16 bit */
1365 SIU_PCR_tag PCR212; /* offset: 0x01E8 size: 16 bit */
1366 SIU_PCR_tag PCR213; /* offset: 0x01EA size: 16 bit */
1367 SIU_PCR_tag PCR214; /* offset: 0x01EC size: 16 bit */
1368 SIU_PCR_tag PCR215; /* offset: 0x01EE size: 16 bit */
1369 SIU_PCR_tag PCR216; /* offset: 0x01F0 size: 16 bit */
1370 SIU_PCR_tag PCR217; /* offset: 0x01F2 size: 16 bit */
1371 SIU_PCR_tag PCR218; /* offset: 0x01F4 size: 16 bit */
1372 SIU_PCR_tag PCR219; /* offset: 0x01F6 size: 16 bit */
1373 SIU_PCR_tag PCR220; /* offset: 0x01F8 size: 16 bit */
1374 SIU_PCR_tag PCR221; /* offset: 0x01FA size: 16 bit */
1375 SIU_PCR_tag PCR222; /* offset: 0x01FC size: 16 bit */
1376 SIU_PCR_tag PCR223; /* offset: 0x01FE size: 16 bit */
1377 SIU_PCR_tag PCR224; /* offset: 0x0200 size: 16 bit */
1378 SIU_PCR_tag PCR225; /* offset: 0x0202 size: 16 bit */
1379 SIU_PCR_tag PCR226; /* offset: 0x0204 size: 16 bit */
1380 SIU_PCR_tag PCR227; /* offset: 0x0206 size: 16 bit */
1381 SIU_PCR_tag PCR228; /* offset: 0x0208 size: 16 bit */
1382 SIU_PCR_tag PCR229; /* offset: 0x020A size: 16 bit */
1383 SIU_PCR_tag PCR230; /* offset: 0x020C size: 16 bit */
1384 SIU_PCR_tag PCR231; /* offset: 0x020E size: 16 bit */
1385 SIU_PCR_tag PCR232; /* offset: 0x0210 size: 16 bit */
1386 SIU_PCR_tag PCR233; /* offset: 0x0212 size: 16 bit */
1387 SIU_PCR_tag PCR234; /* offset: 0x0214 size: 16 bit */
1388 SIU_PCR_tag PCR235; /* offset: 0x0216 size: 16 bit */
1389 SIU_PCR_tag PCR236; /* offset: 0x0218 size: 16 bit */
1390 SIU_PCR_tag PCR237; /* offset: 0x021A size: 16 bit */
1391 SIU_PCR_tag PCR238; /* offset: 0x021C size: 16 bit */
1392 SIU_PCR_tag PCR239; /* offset: 0x021E size: 16 bit */
1393 SIU_PCR_tag PCR240; /* offset: 0x0220 size: 16 bit */
1394 SIU_PCR_tag PCR241; /* offset: 0x0222 size: 16 bit */
1395 SIU_PCR_tag PCR242; /* offset: 0x0224 size: 16 bit */
1396 SIU_PCR_tag PCR243; /* offset: 0x0226 size: 16 bit */
1397 SIU_PCR_tag PCR244; /* offset: 0x0228 size: 16 bit */
1398 SIU_PCR_tag PCR245; /* offset: 0x022A size: 16 bit */
1399 SIU_PCR_tag PCR246; /* offset: 0x022C size: 16 bit */
1400 SIU_PCR_tag PCR247; /* offset: 0x022E size: 16 bit */
1401 SIU_PCR_tag PCR248; /* offset: 0x0230 size: 16 bit */
1402 SIU_PCR_tag PCR249; /* offset: 0x0232 size: 16 bit */
1403 SIU_PCR_tag PCR250; /* offset: 0x0234 size: 16 bit */
1404 SIU_PCR_tag PCR251; /* offset: 0x0236 size: 16 bit */
1405 SIU_PCR_tag PCR252; /* offset: 0x0238 size: 16 bit */
1406 SIU_PCR_tag PCR253; /* offset: 0x023A size: 16 bit */
1407 SIU_PCR_tag PCR254; /* offset: 0x023C size: 16 bit */
1408 SIU_PCR_tag PCR255; /* offset: 0x023E size: 16 bit */
1409 SIU_PCR_tag PCR256; /* offset: 0x0240 size: 16 bit */
1410 SIU_PCR_tag PCR257; /* offset: 0x0242 size: 16 bit */
1411 SIU_PCR_tag PCR258; /* offset: 0x0244 size: 16 bit */
1412 SIU_PCR_tag PCR259; /* offset: 0x0246 size: 16 bit */
1413 SIU_PCR_tag PCR260; /* offset: 0x0248 size: 16 bit */
1414 SIU_PCR_tag PCR261; /* offset: 0x024A size: 16 bit */
1415 SIU_PCR_tag PCR262; /* offset: 0x024C size: 16 bit */
1416 SIU_PCR_tag PCR263; /* offset: 0x024E size: 16 bit */
1417 SIU_PCR_tag PCR264; /* offset: 0x0250 size: 16 bit */
1418 SIU_PCR_tag PCR265; /* offset: 0x0252 size: 16 bit */
1419 SIU_PCR_tag PCR266; /* offset: 0x0254 size: 16 bit */
1420 SIU_PCR_tag PCR267; /* offset: 0x0256 size: 16 bit */
1421 SIU_PCR_tag PCR268; /* offset: 0x0258 size: 16 bit */
1422 SIU_PCR_tag PCR269; /* offset: 0x025A size: 16 bit */
1423 SIU_PCR_tag PCR270; /* offset: 0x025C size: 16 bit */
1424 SIU_PCR_tag PCR271; /* offset: 0x025E size: 16 bit */
1425 SIU_PCR_tag PCR272; /* offset: 0x0260 size: 16 bit */
1426 SIU_PCR_tag PCR273; /* offset: 0x0262 size: 16 bit */
1427 SIU_PCR_tag PCR274; /* offset: 0x0264 size: 16 bit */
1428 SIU_PCR_tag PCR275; /* offset: 0x0266 size: 16 bit */
1429 SIU_PCR_tag PCR276; /* offset: 0x0268 size: 16 bit */
1430 SIU_PCR_tag PCR277; /* offset: 0x026A size: 16 bit */
1431 SIU_PCR_tag PCR278; /* offset: 0x026C size: 16 bit */
1432 SIU_PCR_tag PCR279; /* offset: 0x026E size: 16 bit */
1433 SIU_PCR_tag PCR280; /* offset: 0x0270 size: 16 bit */
1434 SIU_PCR_tag PCR281; /* offset: 0x0272 size: 16 bit */
1435 SIU_PCR_tag PCR282; /* offset: 0x0274 size: 16 bit */
1436 SIU_PCR_tag PCR283; /* offset: 0x0276 size: 16 bit */
1437 SIU_PCR_tag PCR284; /* offset: 0x0278 size: 16 bit */
1438 SIU_PCR_tag PCR285; /* offset: 0x027A size: 16 bit */
1439 SIU_PCR_tag PCR286; /* offset: 0x027C size: 16 bit */
1440 SIU_PCR_tag PCR287; /* offset: 0x027E size: 16 bit */
1441 SIU_PCR_tag PCR288; /* offset: 0x0280 size: 16 bit */
1442 SIU_PCR_tag PCR289; /* offset: 0x0282 size: 16 bit */
1443 SIU_PCR_tag PCR290; /* offset: 0x0284 size: 16 bit */
1444 SIU_PCR_tag PCR291; /* offset: 0x0286 size: 16 bit */
1445 SIU_PCR_tag PCR292; /* offset: 0x0288 size: 16 bit */
1446 SIU_PCR_tag PCR293; /* offset: 0x028A size: 16 bit */
1447 SIU_PCR_tag PCR294; /* offset: 0x028C size: 16 bit */
1448 SIU_PCR_tag PCR295; /* offset: 0x028E size: 16 bit */
1449 SIU_PCR_tag PCR296; /* offset: 0x0290 size: 16 bit */
1450 SIU_PCR_tag PCR297; /* offset: 0x0292 size: 16 bit */
1451 SIU_PCR_tag PCR298; /* offset: 0x0294 size: 16 bit */
1452 SIU_PCR_tag PCR299; /* offset: 0x0296 size: 16 bit */
1453 SIU_PCR_tag PCR300; /* offset: 0x0298 size: 16 bit */
1454 SIU_PCR_tag PCR301; /* offset: 0x029A size: 16 bit */
1455 SIU_PCR_tag PCR302; /* offset: 0x029C size: 16 bit */
1456 SIU_PCR_tag PCR303; /* offset: 0x029E size: 16 bit */
1457 SIU_PCR_tag PCR304; /* offset: 0x02A0 size: 16 bit */
1458 SIU_PCR_tag PCR305; /* offset: 0x02A2 size: 16 bit */
1459 SIU_PCR_tag PCR306; /* offset: 0x02A4 size: 16 bit */
1460 SIU_PCR_tag PCR307; /* offset: 0x02A6 size: 16 bit */
1461 SIU_PCR_tag PCR308; /* offset: 0x02A8 size: 16 bit */
1462 SIU_PCR_tag PCR309; /* offset: 0x02AA size: 16 bit */
1463 SIU_PCR_tag PCR310; /* offset: 0x02AC size: 16 bit */
1464 SIU_PCR_tag PCR311; /* offset: 0x02AE size: 16 bit */
1465 SIU_PCR_tag PCR312; /* offset: 0x02B0 size: 16 bit */
1466 SIU_PCR_tag PCR313; /* offset: 0x02B2 size: 16 bit */
1467 SIU_PCR_tag PCR314; /* offset: 0x02B4 size: 16 bit */
1468 SIU_PCR_tag PCR315; /* offset: 0x02B6 size: 16 bit */
1469 SIU_PCR_tag PCR316; /* offset: 0x02B8 size: 16 bit */
1470 SIU_PCR_tag PCR317; /* offset: 0x02BA size: 16 bit */
1471 SIU_PCR_tag PCR318; /* offset: 0x02BC size: 16 bit */
1472 SIU_PCR_tag PCR319; /* offset: 0x02BE size: 16 bit */
1473 SIU_PCR_tag PCR320; /* offset: 0x02C0 size: 16 bit */
1474 SIU_PCR_tag PCR321; /* offset: 0x02C2 size: 16 bit */
1475 SIU_PCR_tag PCR322; /* offset: 0x02C4 size: 16 bit */
1476 SIU_PCR_tag PCR323; /* offset: 0x02C6 size: 16 bit */
1477 SIU_PCR_tag PCR324; /* offset: 0x02C8 size: 16 bit */
1478 SIU_PCR_tag PCR325; /* offset: 0x02CA size: 16 bit */
1479 SIU_PCR_tag PCR326; /* offset: 0x02CC size: 16 bit */
1480 SIU_PCR_tag PCR327; /* offset: 0x02CE size: 16 bit */
1481 SIU_PCR_tag PCR328; /* offset: 0x02D0 size: 16 bit */
1482 SIU_PCR_tag PCR329; /* offset: 0x02D2 size: 16 bit */
1483 SIU_PCR_tag PCR330; /* offset: 0x02D4 size: 16 bit */
1484 SIU_PCR_tag PCR331; /* offset: 0x02D6 size: 16 bit */
1485 SIU_PCR_tag PCR332; /* offset: 0x02D8 size: 16 bit */
1486 SIU_PCR_tag PCR333; /* offset: 0x02DA size: 16 bit */
1487 SIU_PCR_tag PCR334; /* offset: 0x02DC size: 16 bit */
1488 SIU_PCR_tag PCR335; /* offset: 0x02DE size: 16 bit */
1489 SIU_PCR_tag PCR336; /* offset: 0x02E0 size: 16 bit */
1490 SIU_PCR_tag PCR337; /* offset: 0x02E2 size: 16 bit */
1491 SIU_PCR_tag PCR338; /* offset: 0x02E4 size: 16 bit */
1492 SIU_PCR_tag PCR339; /* offset: 0x02E6 size: 16 bit */
1493 SIU_PCR_tag PCR340; /* offset: 0x02E8 size: 16 bit */
1494 SIU_PCR_tag PCR341; /* offset: 0x02EA size: 16 bit */
1495 SIU_PCR_tag PCR342; /* offset: 0x02EC size: 16 bit */
1496 SIU_PCR_tag PCR343; /* offset: 0x02EE size: 16 bit */
1497 SIU_PCR_tag PCR344; /* offset: 0x02F0 size: 16 bit */
1498 SIU_PCR_tag PCR345; /* offset: 0x02F2 size: 16 bit */
1499 SIU_PCR_tag PCR346; /* offset: 0x02F4 size: 16 bit */
1500 SIU_PCR_tag PCR347; /* offset: 0x02F6 size: 16 bit */
1501 SIU_PCR_tag PCR348; /* offset: 0x02F8 size: 16 bit */
1502 SIU_PCR_tag PCR349; /* offset: 0x02FA size: 16 bit */
1503 SIU_PCR_tag PCR350; /* offset: 0x02FC size: 16 bit */
1504 SIU_PCR_tag PCR351; /* offset: 0x02FE size: 16 bit */
1505 SIU_PCR_tag PCR352; /* offset: 0x0300 size: 16 bit */
1506 SIU_PCR_tag PCR353; /* offset: 0x0302 size: 16 bit */
1507 SIU_PCR_tag PCR354; /* offset: 0x0304 size: 16 bit */
1508 SIU_PCR_tag PCR355; /* offset: 0x0306 size: 16 bit */
1509 SIU_PCR_tag PCR356; /* offset: 0x0308 size: 16 bit */
1510 SIU_PCR_tag PCR357; /* offset: 0x030A size: 16 bit */
1511 SIU_PCR_tag PCR358; /* offset: 0x030C size: 16 bit */
1512 SIU_PCR_tag PCR359; /* offset: 0x030E size: 16 bit */
1513 SIU_PCR_tag PCR360; /* offset: 0x0310 size: 16 bit */
1514 SIU_PCR_tag PCR361; /* offset: 0x0312 size: 16 bit */
1515 SIU_PCR_tag PCR362; /* offset: 0x0314 size: 16 bit */
1516 SIU_PCR_tag PCR363; /* offset: 0x0316 size: 16 bit */
1517 SIU_PCR_tag PCR364; /* offset: 0x0318 size: 16 bit */
1518 SIU_PCR_tag PCR365; /* offset: 0x031A size: 16 bit */
1519 SIU_PCR_tag PCR366; /* offset: 0x031C size: 16 bit */
1520 SIU_PCR_tag PCR367; /* offset: 0x031E size: 16 bit */
1521 SIU_PCR_tag PCR368; /* offset: 0x0320 size: 16 bit */
1522 SIU_PCR_tag PCR369; /* offset: 0x0322 size: 16 bit */
1523 SIU_PCR_tag PCR370; /* offset: 0x0324 size: 16 bit */
1524 SIU_PCR_tag PCR371; /* offset: 0x0326 size: 16 bit */
1525 SIU_PCR_tag PCR372; /* offset: 0x0328 size: 16 bit */
1526 SIU_PCR_tag PCR373; /* offset: 0x032A size: 16 bit */
1527 SIU_PCR_tag PCR374; /* offset: 0x032C size: 16 bit */
1528 SIU_PCR_tag PCR375; /* offset: 0x032E size: 16 bit */
1529 SIU_PCR_tag PCR376; /* offset: 0x0330 size: 16 bit */
1530 SIU_PCR_tag PCR377; /* offset: 0x0332 size: 16 bit */
1531 SIU_PCR_tag PCR378; /* offset: 0x0334 size: 16 bit */
1532 SIU_PCR_tag PCR379; /* offset: 0x0336 size: 16 bit */
1533 SIU_PCR_tag PCR380; /* offset: 0x0338 size: 16 bit */
1534 SIU_PCR_tag PCR381; /* offset: 0x033A size: 16 bit */
1535 SIU_PCR_tag PCR382; /* offset: 0x033C size: 16 bit */
1536 SIU_PCR_tag PCR383; /* offset: 0x033E size: 16 bit */
1537 SIU_PCR_tag PCR384; /* offset: 0x0340 size: 16 bit */
1538 SIU_PCR_tag PCR385; /* offset: 0x0342 size: 16 bit */
1539 SIU_PCR_tag PCR386; /* offset: 0x0344 size: 16 bit */
1540 SIU_PCR_tag PCR387; /* offset: 0x0346 size: 16 bit */
1541 SIU_PCR_tag PCR388; /* offset: 0x0348 size: 16 bit */
1542 SIU_PCR_tag PCR389; /* offset: 0x034A size: 16 bit */
1543 SIU_PCR_tag PCR390; /* offset: 0x034C size: 16 bit */
1544 SIU_PCR_tag PCR391; /* offset: 0x034E size: 16 bit */
1545 SIU_PCR_tag PCR392; /* offset: 0x0350 size: 16 bit */
1546 SIU_PCR_tag PCR393; /* offset: 0x0352 size: 16 bit */
1547 SIU_PCR_tag PCR394; /* offset: 0x0354 size: 16 bit */
1548 SIU_PCR_tag PCR395; /* offset: 0x0356 size: 16 bit */
1549 SIU_PCR_tag PCR396; /* offset: 0x0358 size: 16 bit */
1550 SIU_PCR_tag PCR397; /* offset: 0x035A size: 16 bit */
1551 SIU_PCR_tag PCR398; /* offset: 0x035C size: 16 bit */
1552 SIU_PCR_tag PCR399; /* offset: 0x035E size: 16 bit */
1553 SIU_PCR_tag PCR400; /* offset: 0x0360 size: 16 bit */
1554 SIU_PCR_tag PCR401; /* offset: 0x0362 size: 16 bit */
1555 SIU_PCR_tag PCR402; /* offset: 0x0364 size: 16 bit */
1556 SIU_PCR_tag PCR403; /* offset: 0x0366 size: 16 bit */
1557 SIU_PCR_tag PCR404; /* offset: 0x0368 size: 16 bit */
1558 SIU_PCR_tag PCR405; /* offset: 0x036A size: 16 bit */
1559 SIU_PCR_tag PCR406; /* offset: 0x036C size: 16 bit */
1560 SIU_PCR_tag PCR407; /* offset: 0x036E size: 16 bit */
1561 SIU_PCR_tag PCR408; /* offset: 0x0370 size: 16 bit */
1562 SIU_PCR_tag PCR409; /* offset: 0x0372 size: 16 bit */
1563 SIU_PCR_tag PCR410; /* offset: 0x0374 size: 16 bit */
1564 SIU_PCR_tag PCR411; /* offset: 0x0376 size: 16 bit */
1565 SIU_PCR_tag PCR412; /* offset: 0x0378 size: 16 bit */
1566 SIU_PCR_tag PCR413; /* offset: 0x037A size: 16 bit */
1567 SIU_PCR_tag PCR414; /* offset: 0x037C size: 16 bit */
1568 SIU_PCR_tag PCR415; /* offset: 0x037E size: 16 bit */
1569 SIU_PCR_tag PCR416; /* offset: 0x0380 size: 16 bit */
1570 SIU_PCR_tag PCR417; /* offset: 0x0382 size: 16 bit */
1571 SIU_PCR_tag PCR418; /* offset: 0x0384 size: 16 bit */
1572 SIU_PCR_tag PCR419; /* offset: 0x0386 size: 16 bit */
1573 SIU_PCR_tag PCR420; /* offset: 0x0388 size: 16 bit */
1574 SIU_PCR_tag PCR421; /* offset: 0x038A size: 16 bit */
1575 SIU_PCR_tag PCR422; /* offset: 0x038C size: 16 bit */
1576 SIU_PCR_tag PCR423; /* offset: 0x038E size: 16 bit */
1577 SIU_PCR_tag PCR424; /* offset: 0x0390 size: 16 bit */
1578 SIU_PCR_tag PCR425; /* offset: 0x0392 size: 16 bit */
1579 SIU_PCR_tag PCR426; /* offset: 0x0394 size: 16 bit */
1580 SIU_PCR_tag PCR427; /* offset: 0x0396 size: 16 bit */
1581 SIU_PCR_tag PCR428; /* offset: 0x0398 size: 16 bit */
1582 SIU_PCR_tag PCR429; /* offset: 0x039A size: 16 bit */
1583 SIU_PCR_tag PCR430; /* offset: 0x039C size: 16 bit */
1584 SIU_PCR_tag PCR431; /* offset: 0x039E size: 16 bit */
1585 SIU_PCR_tag PCR432; /* offset: 0x03A0 size: 16 bit */
1586 SIU_PCR_tag PCR433; /* offset: 0x03A2 size: 16 bit */
1587 SIU_PCR_tag PCR434; /* offset: 0x03A4 size: 16 bit */
1588 SIU_PCR_tag PCR435; /* offset: 0x03A6 size: 16 bit */
1589 SIU_PCR_tag PCR436; /* offset: 0x03A8 size: 16 bit */
1590 SIU_PCR_tag PCR437; /* offset: 0x03AA size: 16 bit */
1591 SIU_PCR_tag PCR438; /* offset: 0x03AC size: 16 bit */
1592 SIU_PCR_tag PCR439; /* offset: 0x03AE size: 16 bit */
1593 SIU_PCR_tag PCR440; /* offset: 0x03B0 size: 16 bit */
1594 SIU_PCR_tag PCR441; /* offset: 0x03B2 size: 16 bit */
1595 SIU_PCR_tag PCR442; /* offset: 0x03B4 size: 16 bit */
1596 SIU_PCR_tag PCR443; /* offset: 0x03B6 size: 16 bit */
1597 SIU_PCR_tag PCR444; /* offset: 0x03B8 size: 16 bit */
1598 SIU_PCR_tag PCR445; /* offset: 0x03BA size: 16 bit */
1599 SIU_PCR_tag PCR446; /* offset: 0x03BC size: 16 bit */
1600 SIU_PCR_tag PCR447; /* offset: 0x03BE size: 16 bit */
1601 SIU_PCR_tag PCR448; /* offset: 0x03C0 size: 16 bit */
1602 SIU_PCR_tag PCR449; /* offset: 0x03C2 size: 16 bit */
1603 SIU_PCR_tag PCR450; /* offset: 0x03C4 size: 16 bit */
1604 SIU_PCR_tag PCR451; /* offset: 0x03C6 size: 16 bit */
1605 SIU_PCR_tag PCR452; /* offset: 0x03C8 size: 16 bit */
1606 SIU_PCR_tag PCR453; /* offset: 0x03CA size: 16 bit */
1607 SIU_PCR_tag PCR454; /* offset: 0x03CC size: 16 bit */
1608 SIU_PCR_tag PCR455; /* offset: 0x03CE size: 16 bit */
1609 SIU_PCR_tag PCR456; /* offset: 0x03D0 size: 16 bit */
1610 SIU_PCR_tag PCR457; /* offset: 0x03D2 size: 16 bit */
1611 SIU_PCR_tag PCR458; /* offset: 0x03D4 size: 16 bit */
1612 SIU_PCR_tag PCR459; /* offset: 0x03D6 size: 16 bit */
1613 SIU_PCR_tag PCR460; /* offset: 0x03D8 size: 16 bit */
1614 SIU_PCR_tag PCR461; /* offset: 0x03DA size: 16 bit */
1615 SIU_PCR_tag PCR462; /* offset: 0x03DC size: 16 bit */
1616 SIU_PCR_tag PCR463; /* offset: 0x03DE size: 16 bit */
1617 SIU_PCR_tag PCR464; /* offset: 0x03E0 size: 16 bit */
1618 SIU_PCR_tag PCR465; /* offset: 0x03E2 size: 16 bit */
1619 SIU_PCR_tag PCR466; /* offset: 0x03E4 size: 16 bit */
1620 SIU_PCR_tag PCR467; /* offset: 0x03E6 size: 16 bit */
1621 SIU_PCR_tag PCR468; /* offset: 0x03E8 size: 16 bit */
1622 SIU_PCR_tag PCR469; /* offset: 0x03EA size: 16 bit */
1623 SIU_PCR_tag PCR470; /* offset: 0x03EC size: 16 bit */
1624 SIU_PCR_tag PCR471; /* offset: 0x03EE size: 16 bit */
1625 SIU_PCR_tag PCR472; /* offset: 0x03F0 size: 16 bit */
1626 SIU_PCR_tag PCR473; /* offset: 0x03F2 size: 16 bit */
1627 SIU_PCR_tag PCR474; /* offset: 0x03F4 size: 16 bit */
1628 SIU_PCR_tag PCR475; /* offset: 0x03F6 size: 16 bit */
1629 SIU_PCR_tag PCR476; /* offset: 0x03F8 size: 16 bit */
1630 SIU_PCR_tag PCR477; /* offset: 0x03FA size: 16 bit */
1631 SIU_PCR_tag PCR478; /* offset: 0x03FC size: 16 bit */
1632 SIU_PCR_tag PCR479; /* offset: 0x03FE size: 16 bit */
1633 SIU_PCR_tag PCR480; /* offset: 0x0400 size: 16 bit */
1634 SIU_PCR_tag PCR481; /* offset: 0x0402 size: 16 bit */
1635 SIU_PCR_tag PCR482; /* offset: 0x0404 size: 16 bit */
1636 SIU_PCR_tag PCR483; /* offset: 0x0406 size: 16 bit */
1637 SIU_PCR_tag PCR484; /* offset: 0x0408 size: 16 bit */
1638 SIU_PCR_tag PCR485; /* offset: 0x040A size: 16 bit */
1639 SIU_PCR_tag PCR486; /* offset: 0x040C size: 16 bit */
1640 SIU_PCR_tag PCR487; /* offset: 0x040E size: 16 bit */
1641 SIU_PCR_tag PCR488; /* offset: 0x0410 size: 16 bit */
1642 SIU_PCR_tag PCR489; /* offset: 0x0412 size: 16 bit */
1643 SIU_PCR_tag PCR490; /* offset: 0x0414 size: 16 bit */
1644 SIU_PCR_tag PCR491; /* offset: 0x0416 size: 16 bit */
1645 SIU_PCR_tag PCR492; /* offset: 0x0418 size: 16 bit */
1646 SIU_PCR_tag PCR493; /* offset: 0x041A size: 16 bit */
1647 SIU_PCR_tag PCR494; /* offset: 0x041C size: 16 bit */
1648 SIU_PCR_tag PCR495; /* offset: 0x041E size: 16 bit */
1649 SIU_PCR_tag PCR496; /* offset: 0x0420 size: 16 bit */
1650 SIU_PCR_tag PCR497; /* offset: 0x0422 size: 16 bit */
1651 SIU_PCR_tag PCR498; /* offset: 0x0424 size: 16 bit */
1652 SIU_PCR_tag PCR499; /* offset: 0x0426 size: 16 bit */
1653 SIU_PCR_tag PCR500; /* offset: 0x0428 size: 16 bit */
1654 SIU_PCR_tag PCR501; /* offset: 0x042A size: 16 bit */
1655 SIU_PCR_tag PCR502; /* offset: 0x042C size: 16 bit */
1656 SIU_PCR_tag PCR503; /* offset: 0x042E size: 16 bit */
1657 SIU_PCR_tag PCR504; /* offset: 0x0430 size: 16 bit */
1658 SIU_PCR_tag PCR505; /* offset: 0x0432 size: 16 bit */
1659 SIU_PCR_tag PCR506; /* offset: 0x0434 size: 16 bit */
1660 SIU_PCR_tag PCR507; /* offset: 0x0436 size: 16 bit */
1661 SIU_PCR_tag PCR508; /* offset: 0x0438 size: 16 bit */
1662 SIU_PCR_tag PCR509; /* offset: 0x043A size: 16 bit */
1663 SIU_PCR_tag PCR510; /* offset: 0x043C size: 16 bit */
1664 SIU_PCR_tag PCR511; /* offset: 0x043E size: 16 bit */
1665 };
1666
1667 };
1668 int8_t SIUL_reserved_0440_C[192];
1669 union {
1670 /* PSMI - Pad Selection for Multiplexed Inputs */
1671 SIUL_PSMI_32B_tag PSMI_32B[64]; /* offset: 0x0500 (0x0004 x 64) */
1672
1673 /* PSMI - Pad Selection for Multiplexed Inputs */
1674 SIUL_PSMI_8B_tag PSMI[256]; /* offset: 0x0500 (0x0001 x 256) */
1675
1676 struct {
1677 /* PSMI - Pad Selection for Multiplexed Inputs */
1678 SIUL_PSMI_32B_tag PSMI0_3; /* offset: 0x0500 size: 32 bit */
1679 SIUL_PSMI_32B_tag PSMI4_7; /* offset: 0x0504 size: 32 bit */
1680 SIUL_PSMI_32B_tag PSMI8_11; /* offset: 0x0508 size: 32 bit */
1681 SIUL_PSMI_32B_tag PSMI12_15; /* offset: 0x050C size: 32 bit */
1682 SIUL_PSMI_32B_tag PSMI16_19; /* offset: 0x0510 size: 32 bit */
1683 SIUL_PSMI_32B_tag PSMI20_23; /* offset: 0x0514 size: 32 bit */
1684 SIUL_PSMI_32B_tag PSMI24_27; /* offset: 0x0518 size: 32 bit */
1685 SIUL_PSMI_32B_tag PSMI28_31; /* offset: 0x051C size: 32 bit */
1686 SIUL_PSMI_32B_tag PSMI32_35; /* offset: 0x0520 size: 32 bit */
1687 SIUL_PSMI_32B_tag PSMI36_39; /* offset: 0x0524 size: 32 bit */
1688 SIUL_PSMI_32B_tag PSMI40_43; /* offset: 0x0528 size: 32 bit */
1689 SIUL_PSMI_32B_tag PSMI44_47; /* offset: 0x052C size: 32 bit */
1690 SIUL_PSMI_32B_tag PSMI48_51; /* offset: 0x0530 size: 32 bit */
1691 SIUL_PSMI_32B_tag PSMI52_55; /* offset: 0x0534 size: 32 bit */
1692 SIUL_PSMI_32B_tag PSMI56_59; /* offset: 0x0538 size: 32 bit */
1693 SIUL_PSMI_32B_tag PSMI60_63; /* offset: 0x053C size: 32 bit */
1694 SIUL_PSMI_32B_tag PSMI64_67; /* offset: 0x0540 size: 32 bit */
1695 SIUL_PSMI_32B_tag PSMI68_71; /* offset: 0x0544 size: 32 bit */
1696 SIUL_PSMI_32B_tag PSMI72_75; /* offset: 0x0548 size: 32 bit */
1697 SIUL_PSMI_32B_tag PSMI76_79; /* offset: 0x054C size: 32 bit */
1698 SIUL_PSMI_32B_tag PSMI80_83; /* offset: 0x0550 size: 32 bit */
1699 SIUL_PSMI_32B_tag PSMI84_87; /* offset: 0x0554 size: 32 bit */
1700 SIUL_PSMI_32B_tag PSMI88_91; /* offset: 0x0558 size: 32 bit */
1701 SIUL_PSMI_32B_tag PSMI92_95; /* offset: 0x055C size: 32 bit */
1702 SIUL_PSMI_32B_tag PSMI96_99; /* offset: 0x0560 size: 32 bit */
1703 SIUL_PSMI_32B_tag PSMI100_103; /* offset: 0x0564 size: 32 bit */
1704 SIUL_PSMI_32B_tag PSMI104_107; /* offset: 0x0568 size: 32 bit */
1705 SIUL_PSMI_32B_tag PSMI108_111; /* offset: 0x056C size: 32 bit */
1706 SIUL_PSMI_32B_tag PSMI112_115; /* offset: 0x0570 size: 32 bit */
1707 SIUL_PSMI_32B_tag PSMI116_119; /* offset: 0x0574 size: 32 bit */
1708 SIUL_PSMI_32B_tag PSMI120_123; /* offset: 0x0578 size: 32 bit */
1709 SIUL_PSMI_32B_tag PSMI124_127; /* offset: 0x057C size: 32 bit */
1710 SIUL_PSMI_32B_tag PSMI128_131; /* offset: 0x0580 size: 32 bit */
1711 SIUL_PSMI_32B_tag PSMI132_135; /* offset: 0x0584 size: 32 bit */
1712 SIUL_PSMI_32B_tag PSMI136_139; /* offset: 0x0588 size: 32 bit */
1713 SIUL_PSMI_32B_tag PSMI140_143; /* offset: 0x058C size: 32 bit */
1714 SIUL_PSMI_32B_tag PSMI144_147; /* offset: 0x0590 size: 32 bit */
1715 SIUL_PSMI_32B_tag PSMI148_151; /* offset: 0x0594 size: 32 bit */
1716 SIUL_PSMI_32B_tag PSMI152_155; /* offset: 0x0598 size: 32 bit */
1717 SIUL_PSMI_32B_tag PSMI156_159; /* offset: 0x059C size: 32 bit */
1718 SIUL_PSMI_32B_tag PSMI160_163; /* offset: 0x05A0 size: 32 bit */
1719 SIUL_PSMI_32B_tag PSMI164_167; /* offset: 0x05A4 size: 32 bit */
1720 SIUL_PSMI_32B_tag PSMI168_171; /* offset: 0x05A8 size: 32 bit */
1721 SIUL_PSMI_32B_tag PSMI172_175; /* offset: 0x05AC size: 32 bit */
1722 SIUL_PSMI_32B_tag PSMI176_179; /* offset: 0x05B0 size: 32 bit */
1723 SIUL_PSMI_32B_tag PSMI180_183; /* offset: 0x05B4 size: 32 bit */
1724 SIUL_PSMI_32B_tag PSMI184_187; /* offset: 0x05B8 size: 32 bit */
1725 SIUL_PSMI_32B_tag PSMI188_191; /* offset: 0x05BC size: 32 bit */
1726 SIUL_PSMI_32B_tag PSMI192_195; /* offset: 0x05C0 size: 32 bit */
1727 SIUL_PSMI_32B_tag PSMI196_199; /* offset: 0x05C4 size: 32 bit */
1728 SIUL_PSMI_32B_tag PSMI200_203; /* offset: 0x05C8 size: 32 bit */
1729 SIUL_PSMI_32B_tag PSMI204_207; /* offset: 0x05CC size: 32 bit */
1730 SIUL_PSMI_32B_tag PSMI208_211; /* offset: 0x05D0 size: 32 bit */
1731 SIUL_PSMI_32B_tag PSMI212_215; /* offset: 0x05D4 size: 32 bit */
1732 SIUL_PSMI_32B_tag PSMI216_219; /* offset: 0x05D8 size: 32 bit */
1733 SIUL_PSMI_32B_tag PSMI220_223; /* offset: 0x05DC size: 32 bit */
1734 SIUL_PSMI_32B_tag PSMI224_227; /* offset: 0x05E0 size: 32 bit */
1735 SIUL_PSMI_32B_tag PSMI228_231; /* offset: 0x05E4 size: 32 bit */
1736 SIUL_PSMI_32B_tag PSMI232_235; /* offset: 0x05E8 size: 32 bit */
1737 SIUL_PSMI_32B_tag PSMI236_239; /* offset: 0x05EC size: 32 bit */
1738 SIUL_PSMI_32B_tag PSMI240_243; /* offset: 0x05F0 size: 32 bit */
1739 SIUL_PSMI_32B_tag PSMI244_247; /* offset: 0x05F4 size: 32 bit */
1740 SIUL_PSMI_32B_tag PSMI248_251; /* offset: 0x05F8 size: 32 bit */
1741 SIUL_PSMI_32B_tag PSMI252_255; /* offset: 0x05FC size: 32 bit */
1742 };
1743
1744 struct {
1745 /* PSMI - Pad Selection for Multiplexed Inputs */
1746 SIUL_PSMI_8B_tag PSMI0; /* offset: 0x0500 size: 8 bit */
1747 SIUL_PSMI_8B_tag PSMI1; /* offset: 0x0501 size: 8 bit */
1748 SIUL_PSMI_8B_tag PSMI2; /* offset: 0x0502 size: 8 bit */
1749 SIUL_PSMI_8B_tag PSMI3; /* offset: 0x0503 size: 8 bit */
1750 SIUL_PSMI_8B_tag PSMI4; /* offset: 0x0504 size: 8 bit */
1751 SIUL_PSMI_8B_tag PSMI5; /* offset: 0x0505 size: 8 bit */
1752 SIUL_PSMI_8B_tag PSMI6; /* offset: 0x0506 size: 8 bit */
1753 SIUL_PSMI_8B_tag PSMI7; /* offset: 0x0507 size: 8 bit */
1754 SIUL_PSMI_8B_tag PSMI8; /* offset: 0x0508 size: 8 bit */
1755 SIUL_PSMI_8B_tag PSMI9; /* offset: 0x0509 size: 8 bit */
1756 SIUL_PSMI_8B_tag PSMI10; /* offset: 0x050A size: 8 bit */
1757 SIUL_PSMI_8B_tag PSMI11; /* offset: 0x050B size: 8 bit */
1758 SIUL_PSMI_8B_tag PSMI12; /* offset: 0x050C size: 8 bit */
1759 SIUL_PSMI_8B_tag PSMI13; /* offset: 0x050D size: 8 bit */
1760 SIUL_PSMI_8B_tag PSMI14; /* offset: 0x050E size: 8 bit */
1761 SIUL_PSMI_8B_tag PSMI15; /* offset: 0x050F size: 8 bit */
1762 SIUL_PSMI_8B_tag PSMI16; /* offset: 0x0510 size: 8 bit */
1763 SIUL_PSMI_8B_tag PSMI17; /* offset: 0x0511 size: 8 bit */
1764 SIUL_PSMI_8B_tag PSMI18; /* offset: 0x0512 size: 8 bit */
1765 SIUL_PSMI_8B_tag PSMI19; /* offset: 0x0513 size: 8 bit */
1766 SIUL_PSMI_8B_tag PSMI20; /* offset: 0x0514 size: 8 bit */
1767 SIUL_PSMI_8B_tag PSMI21; /* offset: 0x0515 size: 8 bit */
1768 SIUL_PSMI_8B_tag PSMI22; /* offset: 0x0516 size: 8 bit */
1769 SIUL_PSMI_8B_tag PSMI23; /* offset: 0x0517 size: 8 bit */
1770 SIUL_PSMI_8B_tag PSMI24; /* offset: 0x0518 size: 8 bit */
1771 SIUL_PSMI_8B_tag PSMI25; /* offset: 0x0519 size: 8 bit */
1772 SIUL_PSMI_8B_tag PSMI26; /* offset: 0x051A size: 8 bit */
1773 SIUL_PSMI_8B_tag PSMI27; /* offset: 0x051B size: 8 bit */
1774 SIUL_PSMI_8B_tag PSMI28; /* offset: 0x051C size: 8 bit */
1775 SIUL_PSMI_8B_tag PSMI29; /* offset: 0x051D size: 8 bit */
1776 SIUL_PSMI_8B_tag PSMI30; /* offset: 0x051E size: 8 bit */
1777 SIUL_PSMI_8B_tag PSMI31; /* offset: 0x051F size: 8 bit */
1778 SIUL_PSMI_8B_tag PSMI32; /* offset: 0x0520 size: 8 bit */
1779 SIUL_PSMI_8B_tag PSMI33; /* offset: 0x0521 size: 8 bit */
1780 SIUL_PSMI_8B_tag PSMI34; /* offset: 0x0522 size: 8 bit */
1781 SIUL_PSMI_8B_tag PSMI35; /* offset: 0x0523 size: 8 bit */
1782 SIUL_PSMI_8B_tag PSMI36; /* offset: 0x0524 size: 8 bit */
1783 SIUL_PSMI_8B_tag PSMI37; /* offset: 0x0525 size: 8 bit */
1784 SIUL_PSMI_8B_tag PSMI38; /* offset: 0x0526 size: 8 bit */
1785 SIUL_PSMI_8B_tag PSMI39; /* offset: 0x0527 size: 8 bit */
1786 SIUL_PSMI_8B_tag PSMI40; /* offset: 0x0528 size: 8 bit */
1787 SIUL_PSMI_8B_tag PSMI41; /* offset: 0x0529 size: 8 bit */
1788 SIUL_PSMI_8B_tag PSMI42; /* offset: 0x052A size: 8 bit */
1789 SIUL_PSMI_8B_tag PSMI43; /* offset: 0x052B size: 8 bit */
1790 SIUL_PSMI_8B_tag PSMI44; /* offset: 0x052C size: 8 bit */
1791 SIUL_PSMI_8B_tag PSMI45; /* offset: 0x052D size: 8 bit */
1792 SIUL_PSMI_8B_tag PSMI46; /* offset: 0x052E size: 8 bit */
1793 SIUL_PSMI_8B_tag PSMI47; /* offset: 0x052F size: 8 bit */
1794 SIUL_PSMI_8B_tag PSMI48; /* offset: 0x0530 size: 8 bit */
1795 SIUL_PSMI_8B_tag PSMI49; /* offset: 0x0531 size: 8 bit */
1796 SIUL_PSMI_8B_tag PSMI50; /* offset: 0x0532 size: 8 bit */
1797 SIUL_PSMI_8B_tag PSMI51; /* offset: 0x0533 size: 8 bit */
1798 SIUL_PSMI_8B_tag PSMI52; /* offset: 0x0534 size: 8 bit */
1799 SIUL_PSMI_8B_tag PSMI53; /* offset: 0x0535 size: 8 bit */
1800 SIUL_PSMI_8B_tag PSMI54; /* offset: 0x0536 size: 8 bit */
1801 SIUL_PSMI_8B_tag PSMI55; /* offset: 0x0537 size: 8 bit */
1802 SIUL_PSMI_8B_tag PSMI56; /* offset: 0x0538 size: 8 bit */
1803 SIUL_PSMI_8B_tag PSMI57; /* offset: 0x0539 size: 8 bit */
1804 SIUL_PSMI_8B_tag PSMI58; /* offset: 0x053A size: 8 bit */
1805 SIUL_PSMI_8B_tag PSMI59; /* offset: 0x053B size: 8 bit */
1806 SIUL_PSMI_8B_tag PSMI60; /* offset: 0x053C size: 8 bit */
1807 SIUL_PSMI_8B_tag PSMI61; /* offset: 0x053D size: 8 bit */
1808 SIUL_PSMI_8B_tag PSMI62; /* offset: 0x053E size: 8 bit */
1809 SIUL_PSMI_8B_tag PSMI63; /* offset: 0x053F size: 8 bit */
1810 SIUL_PSMI_8B_tag PSMI64; /* offset: 0x0540 size: 8 bit */
1811 SIUL_PSMI_8B_tag PSMI65; /* offset: 0x0541 size: 8 bit */
1812 SIUL_PSMI_8B_tag PSMI66; /* offset: 0x0542 size: 8 bit */
1813 SIUL_PSMI_8B_tag PSMI67; /* offset: 0x0543 size: 8 bit */
1814 SIUL_PSMI_8B_tag PSMI68; /* offset: 0x0544 size: 8 bit */
1815 SIUL_PSMI_8B_tag PSMI69; /* offset: 0x0545 size: 8 bit */
1816 SIUL_PSMI_8B_tag PSMI70; /* offset: 0x0546 size: 8 bit */
1817 SIUL_PSMI_8B_tag PSMI71; /* offset: 0x0547 size: 8 bit */
1818 SIUL_PSMI_8B_tag PSMI72; /* offset: 0x0548 size: 8 bit */
1819 SIUL_PSMI_8B_tag PSMI73; /* offset: 0x0549 size: 8 bit */
1820 SIUL_PSMI_8B_tag PSMI74; /* offset: 0x054A size: 8 bit */
1821 SIUL_PSMI_8B_tag PSMI75; /* offset: 0x054B size: 8 bit */
1822 SIUL_PSMI_8B_tag PSMI76; /* offset: 0x054C size: 8 bit */
1823 SIUL_PSMI_8B_tag PSMI77; /* offset: 0x054D size: 8 bit */
1824 SIUL_PSMI_8B_tag PSMI78; /* offset: 0x054E size: 8 bit */
1825 SIUL_PSMI_8B_tag PSMI79; /* offset: 0x054F size: 8 bit */
1826 SIUL_PSMI_8B_tag PSMI80; /* offset: 0x0550 size: 8 bit */
1827 SIUL_PSMI_8B_tag PSMI81; /* offset: 0x0551 size: 8 bit */
1828 SIUL_PSMI_8B_tag PSMI82; /* offset: 0x0552 size: 8 bit */
1829 SIUL_PSMI_8B_tag PSMI83; /* offset: 0x0553 size: 8 bit */
1830 SIUL_PSMI_8B_tag PSMI84; /* offset: 0x0554 size: 8 bit */
1831 SIUL_PSMI_8B_tag PSMI85; /* offset: 0x0555 size: 8 bit */
1832 SIUL_PSMI_8B_tag PSMI86; /* offset: 0x0556 size: 8 bit */
1833 SIUL_PSMI_8B_tag PSMI87; /* offset: 0x0557 size: 8 bit */
1834 SIUL_PSMI_8B_tag PSMI88; /* offset: 0x0558 size: 8 bit */
1835 SIUL_PSMI_8B_tag PSMI89; /* offset: 0x0559 size: 8 bit */
1836 SIUL_PSMI_8B_tag PSMI90; /* offset: 0x055A size: 8 bit */
1837 SIUL_PSMI_8B_tag PSMI91; /* offset: 0x055B size: 8 bit */
1838 SIUL_PSMI_8B_tag PSMI92; /* offset: 0x055C size: 8 bit */
1839 SIUL_PSMI_8B_tag PSMI93; /* offset: 0x055D size: 8 bit */
1840 SIUL_PSMI_8B_tag PSMI94; /* offset: 0x055E size: 8 bit */
1841 SIUL_PSMI_8B_tag PSMI95; /* offset: 0x055F size: 8 bit */
1842 SIUL_PSMI_8B_tag PSMI96; /* offset: 0x0560 size: 8 bit */
1843 SIUL_PSMI_8B_tag PSMI97; /* offset: 0x0561 size: 8 bit */
1844 SIUL_PSMI_8B_tag PSMI98; /* offset: 0x0562 size: 8 bit */
1845 SIUL_PSMI_8B_tag PSMI99; /* offset: 0x0563 size: 8 bit */
1846 SIUL_PSMI_8B_tag PSMI100; /* offset: 0x0564 size: 8 bit */
1847 SIUL_PSMI_8B_tag PSMI101; /* offset: 0x0565 size: 8 bit */
1848 SIUL_PSMI_8B_tag PSMI102; /* offset: 0x0566 size: 8 bit */
1849 SIUL_PSMI_8B_tag PSMI103; /* offset: 0x0567 size: 8 bit */
1850 SIUL_PSMI_8B_tag PSMI104; /* offset: 0x0568 size: 8 bit */
1851 SIUL_PSMI_8B_tag PSMI105; /* offset: 0x0569 size: 8 bit */
1852 SIUL_PSMI_8B_tag PSMI106; /* offset: 0x056A size: 8 bit */
1853 SIUL_PSMI_8B_tag PSMI107; /* offset: 0x056B size: 8 bit */
1854 SIUL_PSMI_8B_tag PSMI108; /* offset: 0x056C size: 8 bit */
1855 SIUL_PSMI_8B_tag PSMI109; /* offset: 0x056D size: 8 bit */
1856 SIUL_PSMI_8B_tag PSMI110; /* offset: 0x056E size: 8 bit */
1857 SIUL_PSMI_8B_tag PSMI111; /* offset: 0x056F size: 8 bit */
1858 SIUL_PSMI_8B_tag PSMI112; /* offset: 0x0570 size: 8 bit */
1859 SIUL_PSMI_8B_tag PSMI113; /* offset: 0x0571 size: 8 bit */
1860 SIUL_PSMI_8B_tag PSMI114; /* offset: 0x0572 size: 8 bit */
1861 SIUL_PSMI_8B_tag PSMI115; /* offset: 0x0573 size: 8 bit */
1862 SIUL_PSMI_8B_tag PSMI116; /* offset: 0x0574 size: 8 bit */
1863 SIUL_PSMI_8B_tag PSMI117; /* offset: 0x0575 size: 8 bit */
1864 SIUL_PSMI_8B_tag PSMI118; /* offset: 0x0576 size: 8 bit */
1865 SIUL_PSMI_8B_tag PSMI119; /* offset: 0x0577 size: 8 bit */
1866 SIUL_PSMI_8B_tag PSMI120; /* offset: 0x0578 size: 8 bit */
1867 SIUL_PSMI_8B_tag PSMI121; /* offset: 0x0579 size: 8 bit */
1868 SIUL_PSMI_8B_tag PSMI122; /* offset: 0x057A size: 8 bit */
1869 SIUL_PSMI_8B_tag PSMI123; /* offset: 0x057B size: 8 bit */
1870 SIUL_PSMI_8B_tag PSMI124; /* offset: 0x057C size: 8 bit */
1871 SIUL_PSMI_8B_tag PSMI125; /* offset: 0x057D size: 8 bit */
1872 SIUL_PSMI_8B_tag PSMI126; /* offset: 0x057E size: 8 bit */
1873 SIUL_PSMI_8B_tag PSMI127; /* offset: 0x057F size: 8 bit */
1874 SIUL_PSMI_8B_tag PSMI128; /* offset: 0x0580 size: 8 bit */
1875 SIUL_PSMI_8B_tag PSMI129; /* offset: 0x0581 size: 8 bit */
1876 SIUL_PSMI_8B_tag PSMI130; /* offset: 0x0582 size: 8 bit */
1877 SIUL_PSMI_8B_tag PSMI131; /* offset: 0x0583 size: 8 bit */
1878 SIUL_PSMI_8B_tag PSMI132; /* offset: 0x0584 size: 8 bit */
1879 SIUL_PSMI_8B_tag PSMI133; /* offset: 0x0585 size: 8 bit */
1880 SIUL_PSMI_8B_tag PSMI134; /* offset: 0x0586 size: 8 bit */
1881 SIUL_PSMI_8B_tag PSMI135; /* offset: 0x0587 size: 8 bit */
1882 SIUL_PSMI_8B_tag PSMI136; /* offset: 0x0588 size: 8 bit */
1883 SIUL_PSMI_8B_tag PSMI137; /* offset: 0x0589 size: 8 bit */
1884 SIUL_PSMI_8B_tag PSMI138; /* offset: 0x058A size: 8 bit */
1885 SIUL_PSMI_8B_tag PSMI139; /* offset: 0x058B size: 8 bit */
1886 SIUL_PSMI_8B_tag PSMI140; /* offset: 0x058C size: 8 bit */
1887 SIUL_PSMI_8B_tag PSMI141; /* offset: 0x058D size: 8 bit */
1888 SIUL_PSMI_8B_tag PSMI142; /* offset: 0x058E size: 8 bit */
1889 SIUL_PSMI_8B_tag PSMI143; /* offset: 0x058F size: 8 bit */
1890 SIUL_PSMI_8B_tag PSMI144; /* offset: 0x0590 size: 8 bit */
1891 SIUL_PSMI_8B_tag PSMI145; /* offset: 0x0591 size: 8 bit */
1892 SIUL_PSMI_8B_tag PSMI146; /* offset: 0x0592 size: 8 bit */
1893 SIUL_PSMI_8B_tag PSMI147; /* offset: 0x0593 size: 8 bit */
1894 SIUL_PSMI_8B_tag PSMI148; /* offset: 0x0594 size: 8 bit */
1895 SIUL_PSMI_8B_tag PSMI149; /* offset: 0x0595 size: 8 bit */
1896 SIUL_PSMI_8B_tag PSMI150; /* offset: 0x0596 size: 8 bit */
1897 SIUL_PSMI_8B_tag PSMI151; /* offset: 0x0597 size: 8 bit */
1898 SIUL_PSMI_8B_tag PSMI152; /* offset: 0x0598 size: 8 bit */
1899 SIUL_PSMI_8B_tag PSMI153; /* offset: 0x0599 size: 8 bit */
1900 SIUL_PSMI_8B_tag PSMI154; /* offset: 0x059A size: 8 bit */
1901 SIUL_PSMI_8B_tag PSMI155; /* offset: 0x059B size: 8 bit */
1902 SIUL_PSMI_8B_tag PSMI156; /* offset: 0x059C size: 8 bit */
1903 SIUL_PSMI_8B_tag PSMI157; /* offset: 0x059D size: 8 bit */
1904 SIUL_PSMI_8B_tag PSMI158; /* offset: 0x059E size: 8 bit */
1905 SIUL_PSMI_8B_tag PSMI159; /* offset: 0x059F size: 8 bit */
1906 SIUL_PSMI_8B_tag PSMI160; /* offset: 0x05A0 size: 8 bit */
1907 SIUL_PSMI_8B_tag PSMI161; /* offset: 0x05A1 size: 8 bit */
1908 SIUL_PSMI_8B_tag PSMI162; /* offset: 0x05A2 size: 8 bit */
1909 SIUL_PSMI_8B_tag PSMI163; /* offset: 0x05A3 size: 8 bit */
1910 SIUL_PSMI_8B_tag PSMI164; /* offset: 0x05A4 size: 8 bit */
1911 SIUL_PSMI_8B_tag PSMI165; /* offset: 0x05A5 size: 8 bit */
1912 SIUL_PSMI_8B_tag PSMI166; /* offset: 0x05A6 size: 8 bit */
1913 SIUL_PSMI_8B_tag PSMI167; /* offset: 0x05A7 size: 8 bit */
1914 SIUL_PSMI_8B_tag PSMI168; /* offset: 0x05A8 size: 8 bit */
1915 SIUL_PSMI_8B_tag PSMI169; /* offset: 0x05A9 size: 8 bit */
1916 SIUL_PSMI_8B_tag PSMI170; /* offset: 0x05AA size: 8 bit */
1917 SIUL_PSMI_8B_tag PSMI171; /* offset: 0x05AB size: 8 bit */
1918 SIUL_PSMI_8B_tag PSMI172; /* offset: 0x05AC size: 8 bit */
1919 SIUL_PSMI_8B_tag PSMI173; /* offset: 0x05AD size: 8 bit */
1920 SIUL_PSMI_8B_tag PSMI174; /* offset: 0x05AE size: 8 bit */
1921 SIUL_PSMI_8B_tag PSMI175; /* offset: 0x05AF size: 8 bit */
1922 SIUL_PSMI_8B_tag PSMI176; /* offset: 0x05B0 size: 8 bit */
1923 SIUL_PSMI_8B_tag PSMI177; /* offset: 0x05B1 size: 8 bit */
1924 SIUL_PSMI_8B_tag PSMI178; /* offset: 0x05B2 size: 8 bit */
1925 SIUL_PSMI_8B_tag PSMI179; /* offset: 0x05B3 size: 8 bit */
1926 SIUL_PSMI_8B_tag PSMI180; /* offset: 0x05B4 size: 8 bit */
1927 SIUL_PSMI_8B_tag PSMI181; /* offset: 0x05B5 size: 8 bit */
1928 SIUL_PSMI_8B_tag PSMI182; /* offset: 0x05B6 size: 8 bit */
1929 SIUL_PSMI_8B_tag PSMI183; /* offset: 0x05B7 size: 8 bit */
1930 SIUL_PSMI_8B_tag PSMI184; /* offset: 0x05B8 size: 8 bit */
1931 SIUL_PSMI_8B_tag PSMI185; /* offset: 0x05B9 size: 8 bit */
1932 SIUL_PSMI_8B_tag PSMI186; /* offset: 0x05BA size: 8 bit */
1933 SIUL_PSMI_8B_tag PSMI187; /* offset: 0x05BB size: 8 bit */
1934 SIUL_PSMI_8B_tag PSMI188; /* offset: 0x05BC size: 8 bit */
1935 SIUL_PSMI_8B_tag PSMI189; /* offset: 0x05BD size: 8 bit */
1936 SIUL_PSMI_8B_tag PSMI190; /* offset: 0x05BE size: 8 bit */
1937 SIUL_PSMI_8B_tag PSMI191; /* offset: 0x05BF size: 8 bit */
1938 SIUL_PSMI_8B_tag PSMI192; /* offset: 0x05C0 size: 8 bit */
1939 SIUL_PSMI_8B_tag PSMI193; /* offset: 0x05C1 size: 8 bit */
1940 SIUL_PSMI_8B_tag PSMI194; /* offset: 0x05C2 size: 8 bit */
1941 SIUL_PSMI_8B_tag PSMI195; /* offset: 0x05C3 size: 8 bit */
1942 SIUL_PSMI_8B_tag PSMI196; /* offset: 0x05C4 size: 8 bit */
1943 SIUL_PSMI_8B_tag PSMI197; /* offset: 0x05C5 size: 8 bit */
1944 SIUL_PSMI_8B_tag PSMI198; /* offset: 0x05C6 size: 8 bit */
1945 SIUL_PSMI_8B_tag PSMI199; /* offset: 0x05C7 size: 8 bit */
1946 SIUL_PSMI_8B_tag PSMI200; /* offset: 0x05C8 size: 8 bit */
1947 SIUL_PSMI_8B_tag PSMI201; /* offset: 0x05C9 size: 8 bit */
1948 SIUL_PSMI_8B_tag PSMI202; /* offset: 0x05CA size: 8 bit */
1949 SIUL_PSMI_8B_tag PSMI203; /* offset: 0x05CB size: 8 bit */
1950 SIUL_PSMI_8B_tag PSMI204; /* offset: 0x05CC size: 8 bit */
1951 SIUL_PSMI_8B_tag PSMI205; /* offset: 0x05CD size: 8 bit */
1952 SIUL_PSMI_8B_tag PSMI206; /* offset: 0x05CE size: 8 bit */
1953 SIUL_PSMI_8B_tag PSMI207; /* offset: 0x05CF size: 8 bit */
1954 SIUL_PSMI_8B_tag PSMI208; /* offset: 0x05D0 size: 8 bit */
1955 SIUL_PSMI_8B_tag PSMI209; /* offset: 0x05D1 size: 8 bit */
1956 SIUL_PSMI_8B_tag PSMI210; /* offset: 0x05D2 size: 8 bit */
1957 SIUL_PSMI_8B_tag PSMI211; /* offset: 0x05D3 size: 8 bit */
1958 SIUL_PSMI_8B_tag PSMI212; /* offset: 0x05D4 size: 8 bit */
1959 SIUL_PSMI_8B_tag PSMI213; /* offset: 0x05D5 size: 8 bit */
1960 SIUL_PSMI_8B_tag PSMI214; /* offset: 0x05D6 size: 8 bit */
1961 SIUL_PSMI_8B_tag PSMI215; /* offset: 0x05D7 size: 8 bit */
1962 SIUL_PSMI_8B_tag PSMI216; /* offset: 0x05D8 size: 8 bit */
1963 SIUL_PSMI_8B_tag PSMI217; /* offset: 0x05D9 size: 8 bit */
1964 SIUL_PSMI_8B_tag PSMI218; /* offset: 0x05DA size: 8 bit */
1965 SIUL_PSMI_8B_tag PSMI219; /* offset: 0x05DB size: 8 bit */
1966 SIUL_PSMI_8B_tag PSMI220; /* offset: 0x05DC size: 8 bit */
1967 SIUL_PSMI_8B_tag PSMI221; /* offset: 0x05DD size: 8 bit */
1968 SIUL_PSMI_8B_tag PSMI222; /* offset: 0x05DE size: 8 bit */
1969 SIUL_PSMI_8B_tag PSMI223; /* offset: 0x05DF size: 8 bit */
1970 SIUL_PSMI_8B_tag PSMI224; /* offset: 0x05E0 size: 8 bit */
1971 SIUL_PSMI_8B_tag PSMI225; /* offset: 0x05E1 size: 8 bit */
1972 SIUL_PSMI_8B_tag PSMI226; /* offset: 0x05E2 size: 8 bit */
1973 SIUL_PSMI_8B_tag PSMI227; /* offset: 0x05E3 size: 8 bit */
1974 SIUL_PSMI_8B_tag PSMI228; /* offset: 0x05E4 size: 8 bit */
1975 SIUL_PSMI_8B_tag PSMI229; /* offset: 0x05E5 size: 8 bit */
1976 SIUL_PSMI_8B_tag PSMI230; /* offset: 0x05E6 size: 8 bit */
1977 SIUL_PSMI_8B_tag PSMI231; /* offset: 0x05E7 size: 8 bit */
1978 SIUL_PSMI_8B_tag PSMI232; /* offset: 0x05E8 size: 8 bit */
1979 SIUL_PSMI_8B_tag PSMI233; /* offset: 0x05E9 size: 8 bit */
1980 SIUL_PSMI_8B_tag PSMI234; /* offset: 0x05EA size: 8 bit */
1981 SIUL_PSMI_8B_tag PSMI235; /* offset: 0x05EB size: 8 bit */
1982 SIUL_PSMI_8B_tag PSMI236; /* offset: 0x05EC size: 8 bit */
1983 SIUL_PSMI_8B_tag PSMI237; /* offset: 0x05ED size: 8 bit */
1984 SIUL_PSMI_8B_tag PSMI238; /* offset: 0x05EE size: 8 bit */
1985 SIUL_PSMI_8B_tag PSMI239; /* offset: 0x05EF size: 8 bit */
1986 SIUL_PSMI_8B_tag PSMI240; /* offset: 0x05F0 size: 8 bit */
1987 SIUL_PSMI_8B_tag PSMI241; /* offset: 0x05F1 size: 8 bit */
1988 SIUL_PSMI_8B_tag PSMI242; /* offset: 0x05F2 size: 8 bit */
1989 SIUL_PSMI_8B_tag PSMI243; /* offset: 0x05F3 size: 8 bit */
1990 SIUL_PSMI_8B_tag PSMI244; /* offset: 0x05F4 size: 8 bit */
1991 SIUL_PSMI_8B_tag PSMI245; /* offset: 0x05F5 size: 8 bit */
1992 SIUL_PSMI_8B_tag PSMI246; /* offset: 0x05F6 size: 8 bit */
1993 SIUL_PSMI_8B_tag PSMI247; /* offset: 0x05F7 size: 8 bit */
1994 SIUL_PSMI_8B_tag PSMI248; /* offset: 0x05F8 size: 8 bit */
1995 SIUL_PSMI_8B_tag PSMI249; /* offset: 0x05F9 size: 8 bit */
1996 SIUL_PSMI_8B_tag PSMI250; /* offset: 0x05FA size: 8 bit */
1997 SIUL_PSMI_8B_tag PSMI251; /* offset: 0x05FB size: 8 bit */
1998 SIUL_PSMI_8B_tag PSMI252; /* offset: 0x05FC size: 8 bit */
1999 SIUL_PSMI_8B_tag PSMI253; /* offset: 0x05FD size: 8 bit */
2000 SIUL_PSMI_8B_tag PSMI254; /* offset: 0x05FE size: 8 bit */
2001 SIUL_PSMI_8B_tag PSMI255; /* offset: 0x05FF size: 8 bit */
2002 };
2003
2004 };
2005 union {
2006 /* GPDO - GPIO Pad Data Output Register */
2007 SIUL_GPDO_32B_tag GPDO_32B[128]; /* offset: 0x0600 (0x0004 x 128) */
2008
2009 /* GPDO - GPIO Pad Data Output Register */
2010 SIUL_GPDO_8B_tag GPDO[512]; /* offset: 0x0600 (0x0001 x 512) */
2011
2012 struct {
2013 /* GPDO - GPIO Pad Data Output Register */
2014 SIUL_GPDO_32B_tag GPDO0_3; /* offset: 0x0600 size: 32 bit */
2015 SIUL_GPDO_32B_tag GPDO4_7; /* offset: 0x0604 size: 32 bit */
2016 SIUL_GPDO_32B_tag GPDO8_11; /* offset: 0x0608 size: 32 bit */
2017 SIUL_GPDO_32B_tag GPDO12_15; /* offset: 0x060C size: 32 bit */
2018 SIUL_GPDO_32B_tag GPDO16_19; /* offset: 0x0610 size: 32 bit */
2019 SIUL_GPDO_32B_tag GPDO20_23; /* offset: 0x0614 size: 32 bit */
2020 SIUL_GPDO_32B_tag GPDO24_27; /* offset: 0x0618 size: 32 bit */
2021 SIUL_GPDO_32B_tag GPDO28_31; /* offset: 0x061C size: 32 bit */
2022 SIUL_GPDO_32B_tag GPDO32_35; /* offset: 0x0620 size: 32 bit */
2023 SIUL_GPDO_32B_tag GPDO36_39; /* offset: 0x0624 size: 32 bit */
2024 SIUL_GPDO_32B_tag GPDO40_43; /* offset: 0x0628 size: 32 bit */
2025 SIUL_GPDO_32B_tag GPDO44_47; /* offset: 0x062C size: 32 bit */
2026 SIUL_GPDO_32B_tag GPDO48_51; /* offset: 0x0630 size: 32 bit */
2027 SIUL_GPDO_32B_tag GPDO52_55; /* offset: 0x0634 size: 32 bit */
2028 SIUL_GPDO_32B_tag GPDO56_59; /* offset: 0x0638 size: 32 bit */
2029 SIUL_GPDO_32B_tag GPDO60_63; /* offset: 0x063C size: 32 bit */
2030 SIUL_GPDO_32B_tag GPDO64_67; /* offset: 0x0640 size: 32 bit */
2031 SIUL_GPDO_32B_tag GPDO68_71; /* offset: 0x0644 size: 32 bit */
2032 SIUL_GPDO_32B_tag GPDO72_75; /* offset: 0x0648 size: 32 bit */
2033 SIUL_GPDO_32B_tag GPDO76_79; /* offset: 0x064C size: 32 bit */
2034 SIUL_GPDO_32B_tag GPDO80_83; /* offset: 0x0650 size: 32 bit */
2035 SIUL_GPDO_32B_tag GPDO84_87; /* offset: 0x0654 size: 32 bit */
2036 SIUL_GPDO_32B_tag GPDO88_91; /* offset: 0x0658 size: 32 bit */
2037 SIUL_GPDO_32B_tag GPDO92_95; /* offset: 0x065C size: 32 bit */
2038 SIUL_GPDO_32B_tag GPDO96_99; /* offset: 0x0660 size: 32 bit */
2039 SIUL_GPDO_32B_tag GPDO100_103; /* offset: 0x0664 size: 32 bit */
2040 SIUL_GPDO_32B_tag GPDO104_107; /* offset: 0x0668 size: 32 bit */
2041 SIUL_GPDO_32B_tag GPDO108_111; /* offset: 0x066C size: 32 bit */
2042 SIUL_GPDO_32B_tag GPDO112_115; /* offset: 0x0670 size: 32 bit */
2043 SIUL_GPDO_32B_tag GPDO116_119; /* offset: 0x0674 size: 32 bit */
2044 SIUL_GPDO_32B_tag GPDO120_123; /* offset: 0x0678 size: 32 bit */
2045 SIUL_GPDO_32B_tag GPDO124_127; /* offset: 0x067C size: 32 bit */
2046 SIUL_GPDO_32B_tag GPDO128_131; /* offset: 0x0680 size: 32 bit */
2047 SIUL_GPDO_32B_tag GPDO132_135; /* offset: 0x0684 size: 32 bit */
2048 SIUL_GPDO_32B_tag GPDO136_139; /* offset: 0x0688 size: 32 bit */
2049 SIUL_GPDO_32B_tag GPDO140_143; /* offset: 0x068C size: 32 bit */
2050 SIUL_GPDO_32B_tag GPDO144_147; /* offset: 0x0690 size: 32 bit */
2051 SIUL_GPDO_32B_tag GPDO148_151; /* offset: 0x0694 size: 32 bit */
2052 SIUL_GPDO_32B_tag GPDO152_155; /* offset: 0x0698 size: 32 bit */
2053 SIUL_GPDO_32B_tag GPDO156_159; /* offset: 0x069C size: 32 bit */
2054 SIUL_GPDO_32B_tag GPDO160_163; /* offset: 0x06A0 size: 32 bit */
2055 SIUL_GPDO_32B_tag GPDO164_167; /* offset: 0x06A4 size: 32 bit */
2056 SIUL_GPDO_32B_tag GPDO168_171; /* offset: 0x06A8 size: 32 bit */
2057 SIUL_GPDO_32B_tag GPDO172_175; /* offset: 0x06AC size: 32 bit */
2058 SIUL_GPDO_32B_tag GPDO176_179; /* offset: 0x06B0 size: 32 bit */
2059 SIUL_GPDO_32B_tag GPDO180_183; /* offset: 0x06B4 size: 32 bit */
2060 SIUL_GPDO_32B_tag GPDO184_187; /* offset: 0x06B8 size: 32 bit */
2061 SIUL_GPDO_32B_tag GPDO188_191; /* offset: 0x06BC size: 32 bit */
2062 SIUL_GPDO_32B_tag GPDO192_195; /* offset: 0x06C0 size: 32 bit */
2063 SIUL_GPDO_32B_tag GPDO196_199; /* offset: 0x06C4 size: 32 bit */
2064 SIUL_GPDO_32B_tag GPDO200_203; /* offset: 0x06C8 size: 32 bit */
2065 SIUL_GPDO_32B_tag GPDO204_207; /* offset: 0x06CC size: 32 bit */
2066 SIUL_GPDO_32B_tag GPDO208_211; /* offset: 0x06D0 size: 32 bit */
2067 SIUL_GPDO_32B_tag GPDO212_215; /* offset: 0x06D4 size: 32 bit */
2068 SIUL_GPDO_32B_tag GPDO216_219; /* offset: 0x06D8 size: 32 bit */
2069 SIUL_GPDO_32B_tag GPDO220_223; /* offset: 0x06DC size: 32 bit */
2070 SIUL_GPDO_32B_tag GPDO224_227; /* offset: 0x06E0 size: 32 bit */
2071 SIUL_GPDO_32B_tag GPDO228_231; /* offset: 0x06E4 size: 32 bit */
2072 SIUL_GPDO_32B_tag GPDO232_235; /* offset: 0x06E8 size: 32 bit */
2073 SIUL_GPDO_32B_tag GPDO236_239; /* offset: 0x06EC size: 32 bit */
2074 SIUL_GPDO_32B_tag GPDO240_243; /* offset: 0x06F0 size: 32 bit */
2075 SIUL_GPDO_32B_tag GPDO244_247; /* offset: 0x06F4 size: 32 bit */
2076 SIUL_GPDO_32B_tag GPDO248_251; /* offset: 0x06F8 size: 32 bit */
2077 SIUL_GPDO_32B_tag GPDO252_255; /* offset: 0x06FC size: 32 bit */
2078 SIUL_GPDO_32B_tag GPDO256_259; /* offset: 0x0700 size: 32 bit */
2079 SIUL_GPDO_32B_tag GPDO260_263; /* offset: 0x0704 size: 32 bit */
2080 SIUL_GPDO_32B_tag GPDO264_267; /* offset: 0x0708 size: 32 bit */
2081 SIUL_GPDO_32B_tag GPDO268_271; /* offset: 0x070C size: 32 bit */
2082 SIUL_GPDO_32B_tag GPDO272_275; /* offset: 0x0710 size: 32 bit */
2083 SIUL_GPDO_32B_tag GPDO276_279; /* offset: 0x0714 size: 32 bit */
2084 SIUL_GPDO_32B_tag GPDO280_283; /* offset: 0x0718 size: 32 bit */
2085 SIUL_GPDO_32B_tag GPDO284_287; /* offset: 0x071C size: 32 bit */
2086 SIUL_GPDO_32B_tag GPDO288_291; /* offset: 0x0720 size: 32 bit */
2087 SIUL_GPDO_32B_tag GPDO292_295; /* offset: 0x0724 size: 32 bit */
2088 SIUL_GPDO_32B_tag GPDO296_299; /* offset: 0x0728 size: 32 bit */
2089 SIUL_GPDO_32B_tag GPDO300_303; /* offset: 0x072C size: 32 bit */
2090 SIUL_GPDO_32B_tag GPDO304_307; /* offset: 0x0730 size: 32 bit */
2091 SIUL_GPDO_32B_tag GPDO308_311; /* offset: 0x0734 size: 32 bit */
2092 SIUL_GPDO_32B_tag GPDO312_315; /* offset: 0x0738 size: 32 bit */
2093 SIUL_GPDO_32B_tag GPDO316_319; /* offset: 0x073C size: 32 bit */
2094 SIUL_GPDO_32B_tag GPDO320_323; /* offset: 0x0740 size: 32 bit */
2095 SIUL_GPDO_32B_tag GPDO324_327; /* offset: 0x0744 size: 32 bit */
2096 SIUL_GPDO_32B_tag GPDO328_331; /* offset: 0x0748 size: 32 bit */
2097 SIUL_GPDO_32B_tag GPDO332_335; /* offset: 0x074C size: 32 bit */
2098 SIUL_GPDO_32B_tag GPDO336_339; /* offset: 0x0750 size: 32 bit */
2099 SIUL_GPDO_32B_tag GPDO340_343; /* offset: 0x0754 size: 32 bit */
2100 SIUL_GPDO_32B_tag GPDO344_347; /* offset: 0x0758 size: 32 bit */
2101 SIUL_GPDO_32B_tag GPDO348_351; /* offset: 0x075C size: 32 bit */
2102 SIUL_GPDO_32B_tag GPDO352_355; /* offset: 0x0760 size: 32 bit */
2103 SIUL_GPDO_32B_tag GPDO356_359; /* offset: 0x0764 size: 32 bit */
2104 SIUL_GPDO_32B_tag GPDO360_363; /* offset: 0x0768 size: 32 bit */
2105 SIUL_GPDO_32B_tag GPDO364_367; /* offset: 0x076C size: 32 bit */
2106 SIUL_GPDO_32B_tag GPDO368_371; /* offset: 0x0770 size: 32 bit */
2107 SIUL_GPDO_32B_tag GPDO372_375; /* offset: 0x0774 size: 32 bit */
2108 SIUL_GPDO_32B_tag GPDO376_379; /* offset: 0x0778 size: 32 bit */
2109 SIUL_GPDO_32B_tag GPDO380_383; /* offset: 0x077C size: 32 bit */
2110 SIUL_GPDO_32B_tag GPDO384_387; /* offset: 0x0780 size: 32 bit */
2111 SIUL_GPDO_32B_tag GPDO388_391; /* offset: 0x0784 size: 32 bit */
2112 SIUL_GPDO_32B_tag GPDO392_395; /* offset: 0x0788 size: 32 bit */
2113 SIUL_GPDO_32B_tag GPDO396_399; /* offset: 0x078C size: 32 bit */
2114 SIUL_GPDO_32B_tag GPDO400_403; /* offset: 0x0790 size: 32 bit */
2115 SIUL_GPDO_32B_tag GPDO404_407; /* offset: 0x0794 size: 32 bit */
2116 SIUL_GPDO_32B_tag GPDO408_411; /* offset: 0x0798 size: 32 bit */
2117 SIUL_GPDO_32B_tag GPDO412_415; /* offset: 0x079C size: 32 bit */
2118 SIUL_GPDO_32B_tag GPDO416_419; /* offset: 0x07A0 size: 32 bit */
2119 SIUL_GPDO_32B_tag GPDO420_423; /* offset: 0x07A4 size: 32 bit */
2120 SIUL_GPDO_32B_tag GPDO424_427; /* offset: 0x07A8 size: 32 bit */
2121 SIUL_GPDO_32B_tag GPDO428_431; /* offset: 0x07AC size: 32 bit */
2122 SIUL_GPDO_32B_tag GPDO432_435; /* offset: 0x07B0 size: 32 bit */
2123 SIUL_GPDO_32B_tag GPDO436_439; /* offset: 0x07B4 size: 32 bit */
2124 SIUL_GPDO_32B_tag GPDO440_443; /* offset: 0x07B8 size: 32 bit */
2125 SIUL_GPDO_32B_tag GPDO444_447; /* offset: 0x07BC size: 32 bit */
2126 SIUL_GPDO_32B_tag GPDO448_451; /* offset: 0x07C0 size: 32 bit */
2127 SIUL_GPDO_32B_tag GPDO452_455; /* offset: 0x07C4 size: 32 bit */
2128 SIUL_GPDO_32B_tag GPDO456_459; /* offset: 0x07C8 size: 32 bit */
2129 SIUL_GPDO_32B_tag GPDO460_463; /* offset: 0x07CC size: 32 bit */
2130 SIUL_GPDO_32B_tag GPDO464_467; /* offset: 0x07D0 size: 32 bit */
2131 SIUL_GPDO_32B_tag GPDO468_471; /* offset: 0x07D4 size: 32 bit */
2132 SIUL_GPDO_32B_tag GPDO472_475; /* offset: 0x07D8 size: 32 bit */
2133 SIUL_GPDO_32B_tag GPDO476_479; /* offset: 0x07DC size: 32 bit */
2134 SIUL_GPDO_32B_tag GPDO480_483; /* offset: 0x07E0 size: 32 bit */
2135 SIUL_GPDO_32B_tag GPDO484_487; /* offset: 0x07E4 size: 32 bit */
2136 SIUL_GPDO_32B_tag GPDO488_491; /* offset: 0x07E8 size: 32 bit */
2137 SIUL_GPDO_32B_tag GPDO492_495; /* offset: 0x07EC size: 32 bit */
2138 SIUL_GPDO_32B_tag GPDO496_499; /* offset: 0x07F0 size: 32 bit */
2139 SIUL_GPDO_32B_tag GPDO500_503; /* offset: 0x07F4 size: 32 bit */
2140 SIUL_GPDO_32B_tag GPDO504_507; /* offset: 0x07F8 size: 32 bit */
2141 SIUL_GPDO_32B_tag GPDO508_511; /* offset: 0x07FC size: 32 bit */
2142 };
2143
2144 struct {
2145 /* GPDO - GPIO Pad Data Output Register */
2146 SIUL_GPDO_8B_tag GPDO0; /* offset: 0x0600 size: 8 bit */
2147 SIUL_GPDO_8B_tag GPDO1; /* offset: 0x0601 size: 8 bit */
2148 SIUL_GPDO_8B_tag GPDO2; /* offset: 0x0602 size: 8 bit */
2149 SIUL_GPDO_8B_tag GPDO3; /* offset: 0x0603 size: 8 bit */
2150 SIUL_GPDO_8B_tag GPDO4; /* offset: 0x0604 size: 8 bit */
2151 SIUL_GPDO_8B_tag GPDO5; /* offset: 0x0605 size: 8 bit */
2152 SIUL_GPDO_8B_tag GPDO6; /* offset: 0x0606 size: 8 bit */
2153 SIUL_GPDO_8B_tag GPDO7; /* offset: 0x0607 size: 8 bit */
2154 SIUL_GPDO_8B_tag GPDO8; /* offset: 0x0608 size: 8 bit */
2155 SIUL_GPDO_8B_tag GPDO9; /* offset: 0x0609 size: 8 bit */
2156 SIUL_GPDO_8B_tag GPDO10; /* offset: 0x060A size: 8 bit */
2157 SIUL_GPDO_8B_tag GPDO11; /* offset: 0x060B size: 8 bit */
2158 SIUL_GPDO_8B_tag GPDO12; /* offset: 0x060C size: 8 bit */
2159 SIUL_GPDO_8B_tag GPDO13; /* offset: 0x060D size: 8 bit */
2160 SIUL_GPDO_8B_tag GPDO14; /* offset: 0x060E size: 8 bit */
2161 SIUL_GPDO_8B_tag GPDO15; /* offset: 0x060F size: 8 bit */
2162 SIUL_GPDO_8B_tag GPDO16; /* offset: 0x0610 size: 8 bit */
2163 SIUL_GPDO_8B_tag GPDO17; /* offset: 0x0611 size: 8 bit */
2164 SIUL_GPDO_8B_tag GPDO18; /* offset: 0x0612 size: 8 bit */
2165 SIUL_GPDO_8B_tag GPDO19; /* offset: 0x0613 size: 8 bit */
2166 SIUL_GPDO_8B_tag GPDO20; /* offset: 0x0614 size: 8 bit */
2167 SIUL_GPDO_8B_tag GPDO21; /* offset: 0x0615 size: 8 bit */
2168 SIUL_GPDO_8B_tag GPDO22; /* offset: 0x0616 size: 8 bit */
2169 SIUL_GPDO_8B_tag GPDO23; /* offset: 0x0617 size: 8 bit */
2170 SIUL_GPDO_8B_tag GPDO24; /* offset: 0x0618 size: 8 bit */
2171 SIUL_GPDO_8B_tag GPDO25; /* offset: 0x0619 size: 8 bit */
2172 SIUL_GPDO_8B_tag GPDO26; /* offset: 0x061A size: 8 bit */
2173 SIUL_GPDO_8B_tag GPDO27; /* offset: 0x061B size: 8 bit */
2174 SIUL_GPDO_8B_tag GPDO28; /* offset: 0x061C size: 8 bit */
2175 SIUL_GPDO_8B_tag GPDO29; /* offset: 0x061D size: 8 bit */
2176 SIUL_GPDO_8B_tag GPDO30; /* offset: 0x061E size: 8 bit */
2177 SIUL_GPDO_8B_tag GPDO31; /* offset: 0x061F size: 8 bit */
2178 SIUL_GPDO_8B_tag GPDO32; /* offset: 0x0620 size: 8 bit */
2179 SIUL_GPDO_8B_tag GPDO33; /* offset: 0x0621 size: 8 bit */
2180 SIUL_GPDO_8B_tag GPDO34; /* offset: 0x0622 size: 8 bit */
2181 SIUL_GPDO_8B_tag GPDO35; /* offset: 0x0623 size: 8 bit */
2182 SIUL_GPDO_8B_tag GPDO36; /* offset: 0x0624 size: 8 bit */
2183 SIUL_GPDO_8B_tag GPDO37; /* offset: 0x0625 size: 8 bit */
2184 SIUL_GPDO_8B_tag GPDO38; /* offset: 0x0626 size: 8 bit */
2185 SIUL_GPDO_8B_tag GPDO39; /* offset: 0x0627 size: 8 bit */
2186 SIUL_GPDO_8B_tag GPDO40; /* offset: 0x0628 size: 8 bit */
2187 SIUL_GPDO_8B_tag GPDO41; /* offset: 0x0629 size: 8 bit */
2188 SIUL_GPDO_8B_tag GPDO42; /* offset: 0x062A size: 8 bit */
2189 SIUL_GPDO_8B_tag GPDO43; /* offset: 0x062B size: 8 bit */
2190 SIUL_GPDO_8B_tag GPDO44; /* offset: 0x062C size: 8 bit */
2191 SIUL_GPDO_8B_tag GPDO45; /* offset: 0x062D size: 8 bit */
2192 SIUL_GPDO_8B_tag GPDO46; /* offset: 0x062E size: 8 bit */
2193 SIUL_GPDO_8B_tag GPDO47; /* offset: 0x062F size: 8 bit */
2194 SIUL_GPDO_8B_tag GPDO48; /* offset: 0x0630 size: 8 bit */
2195 SIUL_GPDO_8B_tag GPDO49; /* offset: 0x0631 size: 8 bit */
2196 SIUL_GPDO_8B_tag GPDO50; /* offset: 0x0632 size: 8 bit */
2197 SIUL_GPDO_8B_tag GPDO51; /* offset: 0x0633 size: 8 bit */
2198 SIUL_GPDO_8B_tag GPDO52; /* offset: 0x0634 size: 8 bit */
2199 SIUL_GPDO_8B_tag GPDO53; /* offset: 0x0635 size: 8 bit */
2200 SIUL_GPDO_8B_tag GPDO54; /* offset: 0x0636 size: 8 bit */
2201 SIUL_GPDO_8B_tag GPDO55; /* offset: 0x0637 size: 8 bit */
2202 SIUL_GPDO_8B_tag GPDO56; /* offset: 0x0638 size: 8 bit */
2203 SIUL_GPDO_8B_tag GPDO57; /* offset: 0x0639 size: 8 bit */
2204 SIUL_GPDO_8B_tag GPDO58; /* offset: 0x063A size: 8 bit */
2205 SIUL_GPDO_8B_tag GPDO59; /* offset: 0x063B size: 8 bit */
2206 SIUL_GPDO_8B_tag GPDO60; /* offset: 0x063C size: 8 bit */
2207 SIUL_GPDO_8B_tag GPDO61; /* offset: 0x063D size: 8 bit */
2208 SIUL_GPDO_8B_tag GPDO62; /* offset: 0x063E size: 8 bit */
2209 SIUL_GPDO_8B_tag GPDO63; /* offset: 0x063F size: 8 bit */
2210 SIUL_GPDO_8B_tag GPDO64; /* offset: 0x0640 size: 8 bit */
2211 SIUL_GPDO_8B_tag GPDO65; /* offset: 0x0641 size: 8 bit */
2212 SIUL_GPDO_8B_tag GPDO66; /* offset: 0x0642 size: 8 bit */
2213 SIUL_GPDO_8B_tag GPDO67; /* offset: 0x0643 size: 8 bit */
2214 SIUL_GPDO_8B_tag GPDO68; /* offset: 0x0644 size: 8 bit */
2215 SIUL_GPDO_8B_tag GPDO69; /* offset: 0x0645 size: 8 bit */
2216 SIUL_GPDO_8B_tag GPDO70; /* offset: 0x0646 size: 8 bit */
2217 SIUL_GPDO_8B_tag GPDO71; /* offset: 0x0647 size: 8 bit */
2218 SIUL_GPDO_8B_tag GPDO72; /* offset: 0x0648 size: 8 bit */
2219 SIUL_GPDO_8B_tag GPDO73; /* offset: 0x0649 size: 8 bit */
2220 SIUL_GPDO_8B_tag GPDO74; /* offset: 0x064A size: 8 bit */
2221 SIUL_GPDO_8B_tag GPDO75; /* offset: 0x064B size: 8 bit */
2222 SIUL_GPDO_8B_tag GPDO76; /* offset: 0x064C size: 8 bit */
2223 SIUL_GPDO_8B_tag GPDO77; /* offset: 0x064D size: 8 bit */
2224 SIUL_GPDO_8B_tag GPDO78; /* offset: 0x064E size: 8 bit */
2225 SIUL_GPDO_8B_tag GPDO79; /* offset: 0x064F size: 8 bit */
2226 SIUL_GPDO_8B_tag GPDO80; /* offset: 0x0650 size: 8 bit */
2227 SIUL_GPDO_8B_tag GPDO81; /* offset: 0x0651 size: 8 bit */
2228 SIUL_GPDO_8B_tag GPDO82; /* offset: 0x0652 size: 8 bit */
2229 SIUL_GPDO_8B_tag GPDO83; /* offset: 0x0653 size: 8 bit */
2230 SIUL_GPDO_8B_tag GPDO84; /* offset: 0x0654 size: 8 bit */
2231 SIUL_GPDO_8B_tag GPDO85; /* offset: 0x0655 size: 8 bit */
2232 SIUL_GPDO_8B_tag GPDO86; /* offset: 0x0656 size: 8 bit */
2233 SIUL_GPDO_8B_tag GPDO87; /* offset: 0x0657 size: 8 bit */
2234 SIUL_GPDO_8B_tag GPDO88; /* offset: 0x0658 size: 8 bit */
2235 SIUL_GPDO_8B_tag GPDO89; /* offset: 0x0659 size: 8 bit */
2236 SIUL_GPDO_8B_tag GPDO90; /* offset: 0x065A size: 8 bit */
2237 SIUL_GPDO_8B_tag GPDO91; /* offset: 0x065B size: 8 bit */
2238 SIUL_GPDO_8B_tag GPDO92; /* offset: 0x065C size: 8 bit */
2239 SIUL_GPDO_8B_tag GPDO93; /* offset: 0x065D size: 8 bit */
2240 SIUL_GPDO_8B_tag GPDO94; /* offset: 0x065E size: 8 bit */
2241 SIUL_GPDO_8B_tag GPDO95; /* offset: 0x065F size: 8 bit */
2242 SIUL_GPDO_8B_tag GPDO96; /* offset: 0x0660 size: 8 bit */
2243 SIUL_GPDO_8B_tag GPDO97; /* offset: 0x0661 size: 8 bit */
2244 SIUL_GPDO_8B_tag GPDO98; /* offset: 0x0662 size: 8 bit */
2245 SIUL_GPDO_8B_tag GPDO99; /* offset: 0x0663 size: 8 bit */
2246 SIUL_GPDO_8B_tag GPDO100; /* offset: 0x0664 size: 8 bit */
2247 SIUL_GPDO_8B_tag GPDO101; /* offset: 0x0665 size: 8 bit */
2248 SIUL_GPDO_8B_tag GPDO102; /* offset: 0x0666 size: 8 bit */
2249 SIUL_GPDO_8B_tag GPDO103; /* offset: 0x0667 size: 8 bit */
2250 SIUL_GPDO_8B_tag GPDO104; /* offset: 0x0668 size: 8 bit */
2251 SIUL_GPDO_8B_tag GPDO105; /* offset: 0x0669 size: 8 bit */
2252 SIUL_GPDO_8B_tag GPDO106; /* offset: 0x066A size: 8 bit */
2253 SIUL_GPDO_8B_tag GPDO107; /* offset: 0x066B size: 8 bit */
2254 SIUL_GPDO_8B_tag GPDO108; /* offset: 0x066C size: 8 bit */
2255 SIUL_GPDO_8B_tag GPDO109; /* offset: 0x066D size: 8 bit */
2256 SIUL_GPDO_8B_tag GPDO110; /* offset: 0x066E size: 8 bit */
2257 SIUL_GPDO_8B_tag GPDO111; /* offset: 0x066F size: 8 bit */
2258 SIUL_GPDO_8B_tag GPDO112; /* offset: 0x0670 size: 8 bit */
2259 SIUL_GPDO_8B_tag GPDO113; /* offset: 0x0671 size: 8 bit */
2260 SIUL_GPDO_8B_tag GPDO114; /* offset: 0x0672 size: 8 bit */
2261 SIUL_GPDO_8B_tag GPDO115; /* offset: 0x0673 size: 8 bit */
2262 SIUL_GPDO_8B_tag GPDO116; /* offset: 0x0674 size: 8 bit */
2263 SIUL_GPDO_8B_tag GPDO117; /* offset: 0x0675 size: 8 bit */
2264 SIUL_GPDO_8B_tag GPDO118; /* offset: 0x0676 size: 8 bit */
2265 SIUL_GPDO_8B_tag GPDO119; /* offset: 0x0677 size: 8 bit */
2266 SIUL_GPDO_8B_tag GPDO120; /* offset: 0x0678 size: 8 bit */
2267 SIUL_GPDO_8B_tag GPDO121; /* offset: 0x0679 size: 8 bit */
2268 SIUL_GPDO_8B_tag GPDO122; /* offset: 0x067A size: 8 bit */
2269 SIUL_GPDO_8B_tag GPDO123; /* offset: 0x067B size: 8 bit */
2270 SIUL_GPDO_8B_tag GPDO124; /* offset: 0x067C size: 8 bit */
2271 SIUL_GPDO_8B_tag GPDO125; /* offset: 0x067D size: 8 bit */
2272 SIUL_GPDO_8B_tag GPDO126; /* offset: 0x067E size: 8 bit */
2273 SIUL_GPDO_8B_tag GPDO127; /* offset: 0x067F size: 8 bit */
2274 SIUL_GPDO_8B_tag GPDO128; /* offset: 0x0680 size: 8 bit */
2275 SIUL_GPDO_8B_tag GPDO129; /* offset: 0x0681 size: 8 bit */
2276 SIUL_GPDO_8B_tag GPDO130; /* offset: 0x0682 size: 8 bit */
2277 SIUL_GPDO_8B_tag GPDO131; /* offset: 0x0683 size: 8 bit */
2278 SIUL_GPDO_8B_tag GPDO132; /* offset: 0x0684 size: 8 bit */
2279 SIUL_GPDO_8B_tag GPDO133; /* offset: 0x0685 size: 8 bit */
2280 SIUL_GPDO_8B_tag GPDO134; /* offset: 0x0686 size: 8 bit */
2281 SIUL_GPDO_8B_tag GPDO135; /* offset: 0x0687 size: 8 bit */
2282 SIUL_GPDO_8B_tag GPDO136; /* offset: 0x0688 size: 8 bit */
2283 SIUL_GPDO_8B_tag GPDO137; /* offset: 0x0689 size: 8 bit */
2284 SIUL_GPDO_8B_tag GPDO138; /* offset: 0x068A size: 8 bit */
2285 SIUL_GPDO_8B_tag GPDO139; /* offset: 0x068B size: 8 bit */
2286 SIUL_GPDO_8B_tag GPDO140; /* offset: 0x068C size: 8 bit */
2287 SIUL_GPDO_8B_tag GPDO141; /* offset: 0x068D size: 8 bit */
2288 SIUL_GPDO_8B_tag GPDO142; /* offset: 0x068E size: 8 bit */
2289 SIUL_GPDO_8B_tag GPDO143; /* offset: 0x068F size: 8 bit */
2290 SIUL_GPDO_8B_tag GPDO144; /* offset: 0x0690 size: 8 bit */
2291 SIUL_GPDO_8B_tag GPDO145; /* offset: 0x0691 size: 8 bit */
2292 SIUL_GPDO_8B_tag GPDO146; /* offset: 0x0692 size: 8 bit */
2293 SIUL_GPDO_8B_tag GPDO147; /* offset: 0x0693 size: 8 bit */
2294 SIUL_GPDO_8B_tag GPDO148; /* offset: 0x0694 size: 8 bit */
2295 SIUL_GPDO_8B_tag GPDO149; /* offset: 0x0695 size: 8 bit */
2296 SIUL_GPDO_8B_tag GPDO150; /* offset: 0x0696 size: 8 bit */
2297 SIUL_GPDO_8B_tag GPDO151; /* offset: 0x0697 size: 8 bit */
2298 SIUL_GPDO_8B_tag GPDO152; /* offset: 0x0698 size: 8 bit */
2299 SIUL_GPDO_8B_tag GPDO153; /* offset: 0x0699 size: 8 bit */
2300 SIUL_GPDO_8B_tag GPDO154; /* offset: 0x069A size: 8 bit */
2301 SIUL_GPDO_8B_tag GPDO155; /* offset: 0x069B size: 8 bit */
2302 SIUL_GPDO_8B_tag GPDO156; /* offset: 0x069C size: 8 bit */
2303 SIUL_GPDO_8B_tag GPDO157; /* offset: 0x069D size: 8 bit */
2304 SIUL_GPDO_8B_tag GPDO158; /* offset: 0x069E size: 8 bit */
2305 SIUL_GPDO_8B_tag GPDO159; /* offset: 0x069F size: 8 bit */
2306 SIUL_GPDO_8B_tag GPDO160; /* offset: 0x06A0 size: 8 bit */
2307 SIUL_GPDO_8B_tag GPDO161; /* offset: 0x06A1 size: 8 bit */
2308 SIUL_GPDO_8B_tag GPDO162; /* offset: 0x06A2 size: 8 bit */
2309 SIUL_GPDO_8B_tag GPDO163; /* offset: 0x06A3 size: 8 bit */
2310 SIUL_GPDO_8B_tag GPDO164; /* offset: 0x06A4 size: 8 bit */
2311 SIUL_GPDO_8B_tag GPDO165; /* offset: 0x06A5 size: 8 bit */
2312 SIUL_GPDO_8B_tag GPDO166; /* offset: 0x06A6 size: 8 bit */
2313 SIUL_GPDO_8B_tag GPDO167; /* offset: 0x06A7 size: 8 bit */
2314 SIUL_GPDO_8B_tag GPDO168; /* offset: 0x06A8 size: 8 bit */
2315 SIUL_GPDO_8B_tag GPDO169; /* offset: 0x06A9 size: 8 bit */
2316 SIUL_GPDO_8B_tag GPDO170; /* offset: 0x06AA size: 8 bit */
2317 SIUL_GPDO_8B_tag GPDO171; /* offset: 0x06AB size: 8 bit */
2318 SIUL_GPDO_8B_tag GPDO172; /* offset: 0x06AC size: 8 bit */
2319 SIUL_GPDO_8B_tag GPDO173; /* offset: 0x06AD size: 8 bit */
2320 SIUL_GPDO_8B_tag GPDO174; /* offset: 0x06AE size: 8 bit */
2321 SIUL_GPDO_8B_tag GPDO175; /* offset: 0x06AF size: 8 bit */
2322 SIUL_GPDO_8B_tag GPDO176; /* offset: 0x06B0 size: 8 bit */
2323 SIUL_GPDO_8B_tag GPDO177; /* offset: 0x06B1 size: 8 bit */
2324 SIUL_GPDO_8B_tag GPDO178; /* offset: 0x06B2 size: 8 bit */
2325 SIUL_GPDO_8B_tag GPDO179; /* offset: 0x06B3 size: 8 bit */
2326 SIUL_GPDO_8B_tag GPDO180; /* offset: 0x06B4 size: 8 bit */
2327 SIUL_GPDO_8B_tag GPDO181; /* offset: 0x06B5 size: 8 bit */
2328 SIUL_GPDO_8B_tag GPDO182; /* offset: 0x06B6 size: 8 bit */
2329 SIUL_GPDO_8B_tag GPDO183; /* offset: 0x06B7 size: 8 bit */
2330 SIUL_GPDO_8B_tag GPDO184; /* offset: 0x06B8 size: 8 bit */
2331 SIUL_GPDO_8B_tag GPDO185; /* offset: 0x06B9 size: 8 bit */
2332 SIUL_GPDO_8B_tag GPDO186; /* offset: 0x06BA size: 8 bit */
2333 SIUL_GPDO_8B_tag GPDO187; /* offset: 0x06BB size: 8 bit */
2334 SIUL_GPDO_8B_tag GPDO188; /* offset: 0x06BC size: 8 bit */
2335 SIUL_GPDO_8B_tag GPDO189; /* offset: 0x06BD size: 8 bit */
2336 SIUL_GPDO_8B_tag GPDO190; /* offset: 0x06BE size: 8 bit */
2337 SIUL_GPDO_8B_tag GPDO191; /* offset: 0x06BF size: 8 bit */
2338 SIUL_GPDO_8B_tag GPDO192; /* offset: 0x06C0 size: 8 bit */
2339 SIUL_GPDO_8B_tag GPDO193; /* offset: 0x06C1 size: 8 bit */
2340 SIUL_GPDO_8B_tag GPDO194; /* offset: 0x06C2 size: 8 bit */
2341 SIUL_GPDO_8B_tag GPDO195; /* offset: 0x06C3 size: 8 bit */
2342 SIUL_GPDO_8B_tag GPDO196; /* offset: 0x06C4 size: 8 bit */
2343 SIUL_GPDO_8B_tag GPDO197; /* offset: 0x06C5 size: 8 bit */
2344 SIUL_GPDO_8B_tag GPDO198; /* offset: 0x06C6 size: 8 bit */
2345 SIUL_GPDO_8B_tag GPDO199; /* offset: 0x06C7 size: 8 bit */
2346 SIUL_GPDO_8B_tag GPDO200; /* offset: 0x06C8 size: 8 bit */
2347 SIUL_GPDO_8B_tag GPDO201; /* offset: 0x06C9 size: 8 bit */
2348 SIUL_GPDO_8B_tag GPDO202; /* offset: 0x06CA size: 8 bit */
2349 SIUL_GPDO_8B_tag GPDO203; /* offset: 0x06CB size: 8 bit */
2350 SIUL_GPDO_8B_tag GPDO204; /* offset: 0x06CC size: 8 bit */
2351 SIUL_GPDO_8B_tag GPDO205; /* offset: 0x06CD size: 8 bit */
2352 SIUL_GPDO_8B_tag GPDO206; /* offset: 0x06CE size: 8 bit */
2353 SIUL_GPDO_8B_tag GPDO207; /* offset: 0x06CF size: 8 bit */
2354 SIUL_GPDO_8B_tag GPDO208; /* offset: 0x06D0 size: 8 bit */
2355 SIUL_GPDO_8B_tag GPDO209; /* offset: 0x06D1 size: 8 bit */
2356 SIUL_GPDO_8B_tag GPDO210; /* offset: 0x06D2 size: 8 bit */
2357 SIUL_GPDO_8B_tag GPDO211; /* offset: 0x06D3 size: 8 bit */
2358 SIUL_GPDO_8B_tag GPDO212; /* offset: 0x06D4 size: 8 bit */
2359 SIUL_GPDO_8B_tag GPDO213; /* offset: 0x06D5 size: 8 bit */
2360 SIUL_GPDO_8B_tag GPDO214; /* offset: 0x06D6 size: 8 bit */
2361 SIUL_GPDO_8B_tag GPDO215; /* offset: 0x06D7 size: 8 bit */
2362 SIUL_GPDO_8B_tag GPDO216; /* offset: 0x06D8 size: 8 bit */
2363 SIUL_GPDO_8B_tag GPDO217; /* offset: 0x06D9 size: 8 bit */
2364 SIUL_GPDO_8B_tag GPDO218; /* offset: 0x06DA size: 8 bit */
2365 SIUL_GPDO_8B_tag GPDO219; /* offset: 0x06DB size: 8 bit */
2366 SIUL_GPDO_8B_tag GPDO220; /* offset: 0x06DC size: 8 bit */
2367 SIUL_GPDO_8B_tag GPDO221; /* offset: 0x06DD size: 8 bit */
2368 SIUL_GPDO_8B_tag GPDO222; /* offset: 0x06DE size: 8 bit */
2369 SIUL_GPDO_8B_tag GPDO223; /* offset: 0x06DF size: 8 bit */
2370 SIUL_GPDO_8B_tag GPDO224; /* offset: 0x06E0 size: 8 bit */
2371 SIUL_GPDO_8B_tag GPDO225; /* offset: 0x06E1 size: 8 bit */
2372 SIUL_GPDO_8B_tag GPDO226; /* offset: 0x06E2 size: 8 bit */
2373 SIUL_GPDO_8B_tag GPDO227; /* offset: 0x06E3 size: 8 bit */
2374 SIUL_GPDO_8B_tag GPDO228; /* offset: 0x06E4 size: 8 bit */
2375 SIUL_GPDO_8B_tag GPDO229; /* offset: 0x06E5 size: 8 bit */
2376 SIUL_GPDO_8B_tag GPDO230; /* offset: 0x06E6 size: 8 bit */
2377 SIUL_GPDO_8B_tag GPDO231; /* offset: 0x06E7 size: 8 bit */
2378 SIUL_GPDO_8B_tag GPDO232; /* offset: 0x06E8 size: 8 bit */
2379 SIUL_GPDO_8B_tag GPDO233; /* offset: 0x06E9 size: 8 bit */
2380 SIUL_GPDO_8B_tag GPDO234; /* offset: 0x06EA size: 8 bit */
2381 SIUL_GPDO_8B_tag GPDO235; /* offset: 0x06EB size: 8 bit */
2382 SIUL_GPDO_8B_tag GPDO236; /* offset: 0x06EC size: 8 bit */
2383 SIUL_GPDO_8B_tag GPDO237; /* offset: 0x06ED size: 8 bit */
2384 SIUL_GPDO_8B_tag GPDO238; /* offset: 0x06EE size: 8 bit */
2385 SIUL_GPDO_8B_tag GPDO239; /* offset: 0x06EF size: 8 bit */
2386 SIUL_GPDO_8B_tag GPDO240; /* offset: 0x06F0 size: 8 bit */
2387 SIUL_GPDO_8B_tag GPDO241; /* offset: 0x06F1 size: 8 bit */
2388 SIUL_GPDO_8B_tag GPDO242; /* offset: 0x06F2 size: 8 bit */
2389 SIUL_GPDO_8B_tag GPDO243; /* offset: 0x06F3 size: 8 bit */
2390 SIUL_GPDO_8B_tag GPDO244; /* offset: 0x06F4 size: 8 bit */
2391 SIUL_GPDO_8B_tag GPDO245; /* offset: 0x06F5 size: 8 bit */
2392 SIUL_GPDO_8B_tag GPDO246; /* offset: 0x06F6 size: 8 bit */
2393 SIUL_GPDO_8B_tag GPDO247; /* offset: 0x06F7 size: 8 bit */
2394 SIUL_GPDO_8B_tag GPDO248; /* offset: 0x06F8 size: 8 bit */
2395 SIUL_GPDO_8B_tag GPDO249; /* offset: 0x06F9 size: 8 bit */
2396 SIUL_GPDO_8B_tag GPDO250; /* offset: 0x06FA size: 8 bit */
2397 SIUL_GPDO_8B_tag GPDO251; /* offset: 0x06FB size: 8 bit */
2398 SIUL_GPDO_8B_tag GPDO252; /* offset: 0x06FC size: 8 bit */
2399 SIUL_GPDO_8B_tag GPDO253; /* offset: 0x06FD size: 8 bit */
2400 SIUL_GPDO_8B_tag GPDO254; /* offset: 0x06FE size: 8 bit */
2401 SIUL_GPDO_8B_tag GPDO255; /* offset: 0x06FF size: 8 bit */
2402 SIUL_GPDO_8B_tag GPDO256; /* offset: 0x0700 size: 8 bit */
2403 SIUL_GPDO_8B_tag GPDO257; /* offset: 0x0701 size: 8 bit */
2404 SIUL_GPDO_8B_tag GPDO258; /* offset: 0x0702 size: 8 bit */
2405 SIUL_GPDO_8B_tag GPDO259; /* offset: 0x0703 size: 8 bit */
2406 SIUL_GPDO_8B_tag GPDO260; /* offset: 0x0704 size: 8 bit */
2407 SIUL_GPDO_8B_tag GPDO261; /* offset: 0x0705 size: 8 bit */
2408 SIUL_GPDO_8B_tag GPDO262; /* offset: 0x0706 size: 8 bit */
2409 SIUL_GPDO_8B_tag GPDO263; /* offset: 0x0707 size: 8 bit */
2410 SIUL_GPDO_8B_tag GPDO264; /* offset: 0x0708 size: 8 bit */
2411 SIUL_GPDO_8B_tag GPDO265; /* offset: 0x0709 size: 8 bit */
2412 SIUL_GPDO_8B_tag GPDO266; /* offset: 0x070A size: 8 bit */
2413 SIUL_GPDO_8B_tag GPDO267; /* offset: 0x070B size: 8 bit */
2414 SIUL_GPDO_8B_tag GPDO268; /* offset: 0x070C size: 8 bit */
2415 SIUL_GPDO_8B_tag GPDO269; /* offset: 0x070D size: 8 bit */
2416 SIUL_GPDO_8B_tag GPDO270; /* offset: 0x070E size: 8 bit */
2417 SIUL_GPDO_8B_tag GPDO271; /* offset: 0x070F size: 8 bit */
2418 SIUL_GPDO_8B_tag GPDO272; /* offset: 0x0710 size: 8 bit */
2419 SIUL_GPDO_8B_tag GPDO273; /* offset: 0x0711 size: 8 bit */
2420 SIUL_GPDO_8B_tag GPDO274; /* offset: 0x0712 size: 8 bit */
2421 SIUL_GPDO_8B_tag GPDO275; /* offset: 0x0713 size: 8 bit */
2422 SIUL_GPDO_8B_tag GPDO276; /* offset: 0x0714 size: 8 bit */
2423 SIUL_GPDO_8B_tag GPDO277; /* offset: 0x0715 size: 8 bit */
2424 SIUL_GPDO_8B_tag GPDO278; /* offset: 0x0716 size: 8 bit */
2425 SIUL_GPDO_8B_tag GPDO279; /* offset: 0x0717 size: 8 bit */
2426 SIUL_GPDO_8B_tag GPDO280; /* offset: 0x0718 size: 8 bit */
2427 SIUL_GPDO_8B_tag GPDO281; /* offset: 0x0719 size: 8 bit */
2428 SIUL_GPDO_8B_tag GPDO282; /* offset: 0x071A size: 8 bit */
2429 SIUL_GPDO_8B_tag GPDO283; /* offset: 0x071B size: 8 bit */
2430 SIUL_GPDO_8B_tag GPDO284; /* offset: 0x071C size: 8 bit */
2431 SIUL_GPDO_8B_tag GPDO285; /* offset: 0x071D size: 8 bit */
2432 SIUL_GPDO_8B_tag GPDO286; /* offset: 0x071E size: 8 bit */
2433 SIUL_GPDO_8B_tag GPDO287; /* offset: 0x071F size: 8 bit */
2434 SIUL_GPDO_8B_tag GPDO288; /* offset: 0x0720 size: 8 bit */
2435 SIUL_GPDO_8B_tag GPDO289; /* offset: 0x0721 size: 8 bit */
2436 SIUL_GPDO_8B_tag GPDO290; /* offset: 0x0722 size: 8 bit */
2437 SIUL_GPDO_8B_tag GPDO291; /* offset: 0x0723 size: 8 bit */
2438 SIUL_GPDO_8B_tag GPDO292; /* offset: 0x0724 size: 8 bit */
2439 SIUL_GPDO_8B_tag GPDO293; /* offset: 0x0725 size: 8 bit */
2440 SIUL_GPDO_8B_tag GPDO294; /* offset: 0x0726 size: 8 bit */
2441 SIUL_GPDO_8B_tag GPDO295; /* offset: 0x0727 size: 8 bit */
2442 SIUL_GPDO_8B_tag GPDO296; /* offset: 0x0728 size: 8 bit */
2443 SIUL_GPDO_8B_tag GPDO297; /* offset: 0x0729 size: 8 bit */
2444 SIUL_GPDO_8B_tag GPDO298; /* offset: 0x072A size: 8 bit */
2445 SIUL_GPDO_8B_tag GPDO299; /* offset: 0x072B size: 8 bit */
2446 SIUL_GPDO_8B_tag GPDO300; /* offset: 0x072C size: 8 bit */
2447 SIUL_GPDO_8B_tag GPDO301; /* offset: 0x072D size: 8 bit */
2448 SIUL_GPDO_8B_tag GPDO302; /* offset: 0x072E size: 8 bit */
2449 SIUL_GPDO_8B_tag GPDO303; /* offset: 0x072F size: 8 bit */
2450 SIUL_GPDO_8B_tag GPDO304; /* offset: 0x0730 size: 8 bit */
2451 SIUL_GPDO_8B_tag GPDO305; /* offset: 0x0731 size: 8 bit */
2452 SIUL_GPDO_8B_tag GPDO306; /* offset: 0x0732 size: 8 bit */
2453 SIUL_GPDO_8B_tag GPDO307; /* offset: 0x0733 size: 8 bit */
2454 SIUL_GPDO_8B_tag GPDO308; /* offset: 0x0734 size: 8 bit */
2455 SIUL_GPDO_8B_tag GPDO309; /* offset: 0x0735 size: 8 bit */
2456 SIUL_GPDO_8B_tag GPDO310; /* offset: 0x0736 size: 8 bit */
2457 SIUL_GPDO_8B_tag GPDO311; /* offset: 0x0737 size: 8 bit */
2458 SIUL_GPDO_8B_tag GPDO312; /* offset: 0x0738 size: 8 bit */
2459 SIUL_GPDO_8B_tag GPDO313; /* offset: 0x0739 size: 8 bit */
2460 SIUL_GPDO_8B_tag GPDO314; /* offset: 0x073A size: 8 bit */
2461 SIUL_GPDO_8B_tag GPDO315; /* offset: 0x073B size: 8 bit */
2462 SIUL_GPDO_8B_tag GPDO316; /* offset: 0x073C size: 8 bit */
2463 SIUL_GPDO_8B_tag GPDO317; /* offset: 0x073D size: 8 bit */
2464 SIUL_GPDO_8B_tag GPDO318; /* offset: 0x073E size: 8 bit */
2465 SIUL_GPDO_8B_tag GPDO319; /* offset: 0x073F size: 8 bit */
2466 SIUL_GPDO_8B_tag GPDO320; /* offset: 0x0740 size: 8 bit */
2467 SIUL_GPDO_8B_tag GPDO321; /* offset: 0x0741 size: 8 bit */
2468 SIUL_GPDO_8B_tag GPDO322; /* offset: 0x0742 size: 8 bit */
2469 SIUL_GPDO_8B_tag GPDO323; /* offset: 0x0743 size: 8 bit */
2470 SIUL_GPDO_8B_tag GPDO324; /* offset: 0x0744 size: 8 bit */
2471 SIUL_GPDO_8B_tag GPDO325; /* offset: 0x0745 size: 8 bit */
2472 SIUL_GPDO_8B_tag GPDO326; /* offset: 0x0746 size: 8 bit */
2473 SIUL_GPDO_8B_tag GPDO327; /* offset: 0x0747 size: 8 bit */
2474 SIUL_GPDO_8B_tag GPDO328; /* offset: 0x0748 size: 8 bit */
2475 SIUL_GPDO_8B_tag GPDO329; /* offset: 0x0749 size: 8 bit */
2476 SIUL_GPDO_8B_tag GPDO330; /* offset: 0x074A size: 8 bit */
2477 SIUL_GPDO_8B_tag GPDO331; /* offset: 0x074B size: 8 bit */
2478 SIUL_GPDO_8B_tag GPDO332; /* offset: 0x074C size: 8 bit */
2479 SIUL_GPDO_8B_tag GPDO333; /* offset: 0x074D size: 8 bit */
2480 SIUL_GPDO_8B_tag GPDO334; /* offset: 0x074E size: 8 bit */
2481 SIUL_GPDO_8B_tag GPDO335; /* offset: 0x074F size: 8 bit */
2482 SIUL_GPDO_8B_tag GPDO336; /* offset: 0x0750 size: 8 bit */
2483 SIUL_GPDO_8B_tag GPDO337; /* offset: 0x0751 size: 8 bit */
2484 SIUL_GPDO_8B_tag GPDO338; /* offset: 0x0752 size: 8 bit */
2485 SIUL_GPDO_8B_tag GPDO339; /* offset: 0x0753 size: 8 bit */
2486 SIUL_GPDO_8B_tag GPDO340; /* offset: 0x0754 size: 8 bit */
2487 SIUL_GPDO_8B_tag GPDO341; /* offset: 0x0755 size: 8 bit */
2488 SIUL_GPDO_8B_tag GPDO342; /* offset: 0x0756 size: 8 bit */
2489 SIUL_GPDO_8B_tag GPDO343; /* offset: 0x0757 size: 8 bit */
2490 SIUL_GPDO_8B_tag GPDO344; /* offset: 0x0758 size: 8 bit */
2491 SIUL_GPDO_8B_tag GPDO345; /* offset: 0x0759 size: 8 bit */
2492 SIUL_GPDO_8B_tag GPDO346; /* offset: 0x075A size: 8 bit */
2493 SIUL_GPDO_8B_tag GPDO347; /* offset: 0x075B size: 8 bit */
2494 SIUL_GPDO_8B_tag GPDO348; /* offset: 0x075C size: 8 bit */
2495 SIUL_GPDO_8B_tag GPDO349; /* offset: 0x075D size: 8 bit */
2496 SIUL_GPDO_8B_tag GPDO350; /* offset: 0x075E size: 8 bit */
2497 SIUL_GPDO_8B_tag GPDO351; /* offset: 0x075F size: 8 bit */
2498 SIUL_GPDO_8B_tag GPDO352; /* offset: 0x0760 size: 8 bit */
2499 SIUL_GPDO_8B_tag GPDO353; /* offset: 0x0761 size: 8 bit */
2500 SIUL_GPDO_8B_tag GPDO354; /* offset: 0x0762 size: 8 bit */
2501 SIUL_GPDO_8B_tag GPDO355; /* offset: 0x0763 size: 8 bit */
2502 SIUL_GPDO_8B_tag GPDO356; /* offset: 0x0764 size: 8 bit */
2503 SIUL_GPDO_8B_tag GPDO357; /* offset: 0x0765 size: 8 bit */
2504 SIUL_GPDO_8B_tag GPDO358; /* offset: 0x0766 size: 8 bit */
2505 SIUL_GPDO_8B_tag GPDO359; /* offset: 0x0767 size: 8 bit */
2506 SIUL_GPDO_8B_tag GPDO360; /* offset: 0x0768 size: 8 bit */
2507 SIUL_GPDO_8B_tag GPDO361; /* offset: 0x0769 size: 8 bit */
2508 SIUL_GPDO_8B_tag GPDO362; /* offset: 0x076A size: 8 bit */
2509 SIUL_GPDO_8B_tag GPDO363; /* offset: 0x076B size: 8 bit */
2510 SIUL_GPDO_8B_tag GPDO364; /* offset: 0x076C size: 8 bit */
2511 SIUL_GPDO_8B_tag GPDO365; /* offset: 0x076D size: 8 bit */
2512 SIUL_GPDO_8B_tag GPDO366; /* offset: 0x076E size: 8 bit */
2513 SIUL_GPDO_8B_tag GPDO367; /* offset: 0x076F size: 8 bit */
2514 SIUL_GPDO_8B_tag GPDO368; /* offset: 0x0770 size: 8 bit */
2515 SIUL_GPDO_8B_tag GPDO369; /* offset: 0x0771 size: 8 bit */
2516 SIUL_GPDO_8B_tag GPDO370; /* offset: 0x0772 size: 8 bit */
2517 SIUL_GPDO_8B_tag GPDO371; /* offset: 0x0773 size: 8 bit */
2518 SIUL_GPDO_8B_tag GPDO372; /* offset: 0x0774 size: 8 bit */
2519 SIUL_GPDO_8B_tag GPDO373; /* offset: 0x0775 size: 8 bit */
2520 SIUL_GPDO_8B_tag GPDO374; /* offset: 0x0776 size: 8 bit */
2521 SIUL_GPDO_8B_tag GPDO375; /* offset: 0x0777 size: 8 bit */
2522 SIUL_GPDO_8B_tag GPDO376; /* offset: 0x0778 size: 8 bit */
2523 SIUL_GPDO_8B_tag GPDO377; /* offset: 0x0779 size: 8 bit */
2524 SIUL_GPDO_8B_tag GPDO378; /* offset: 0x077A size: 8 bit */
2525 SIUL_GPDO_8B_tag GPDO379; /* offset: 0x077B size: 8 bit */
2526 SIUL_GPDO_8B_tag GPDO380; /* offset: 0x077C size: 8 bit */
2527 SIUL_GPDO_8B_tag GPDO381; /* offset: 0x077D size: 8 bit */
2528 SIUL_GPDO_8B_tag GPDO382; /* offset: 0x077E size: 8 bit */
2529 SIUL_GPDO_8B_tag GPDO383; /* offset: 0x077F size: 8 bit */
2530 SIUL_GPDO_8B_tag GPDO384; /* offset: 0x0780 size: 8 bit */
2531 SIUL_GPDO_8B_tag GPDO385; /* offset: 0x0781 size: 8 bit */
2532 SIUL_GPDO_8B_tag GPDO386; /* offset: 0x0782 size: 8 bit */
2533 SIUL_GPDO_8B_tag GPDO387; /* offset: 0x0783 size: 8 bit */
2534 SIUL_GPDO_8B_tag GPDO388; /* offset: 0x0784 size: 8 bit */
2535 SIUL_GPDO_8B_tag GPDO389; /* offset: 0x0785 size: 8 bit */
2536 SIUL_GPDO_8B_tag GPDO390; /* offset: 0x0786 size: 8 bit */
2537 SIUL_GPDO_8B_tag GPDO391; /* offset: 0x0787 size: 8 bit */
2538 SIUL_GPDO_8B_tag GPDO392; /* offset: 0x0788 size: 8 bit */
2539 SIUL_GPDO_8B_tag GPDO393; /* offset: 0x0789 size: 8 bit */
2540 SIUL_GPDO_8B_tag GPDO394; /* offset: 0x078A size: 8 bit */
2541 SIUL_GPDO_8B_tag GPDO395; /* offset: 0x078B size: 8 bit */
2542 SIUL_GPDO_8B_tag GPDO396; /* offset: 0x078C size: 8 bit */
2543 SIUL_GPDO_8B_tag GPDO397; /* offset: 0x078D size: 8 bit */
2544 SIUL_GPDO_8B_tag GPDO398; /* offset: 0x078E size: 8 bit */
2545 SIUL_GPDO_8B_tag GPDO399; /* offset: 0x078F size: 8 bit */
2546 SIUL_GPDO_8B_tag GPDO400; /* offset: 0x0790 size: 8 bit */
2547 SIUL_GPDO_8B_tag GPDO401; /* offset: 0x0791 size: 8 bit */
2548 SIUL_GPDO_8B_tag GPDO402; /* offset: 0x0792 size: 8 bit */
2549 SIUL_GPDO_8B_tag GPDO403; /* offset: 0x0793 size: 8 bit */
2550 SIUL_GPDO_8B_tag GPDO404; /* offset: 0x0794 size: 8 bit */
2551 SIUL_GPDO_8B_tag GPDO405; /* offset: 0x0795 size: 8 bit */
2552 SIUL_GPDO_8B_tag GPDO406; /* offset: 0x0796 size: 8 bit */
2553 SIUL_GPDO_8B_tag GPDO407; /* offset: 0x0797 size: 8 bit */
2554 SIUL_GPDO_8B_tag GPDO408; /* offset: 0x0798 size: 8 bit */
2555 SIUL_GPDO_8B_tag GPDO409; /* offset: 0x0799 size: 8 bit */
2556 SIUL_GPDO_8B_tag GPDO410; /* offset: 0x079A size: 8 bit */
2557 SIUL_GPDO_8B_tag GPDO411; /* offset: 0x079B size: 8 bit */
2558 SIUL_GPDO_8B_tag GPDO412; /* offset: 0x079C size: 8 bit */
2559 SIUL_GPDO_8B_tag GPDO413; /* offset: 0x079D size: 8 bit */
2560 SIUL_GPDO_8B_tag GPDO414; /* offset: 0x079E size: 8 bit */
2561 SIUL_GPDO_8B_tag GPDO415; /* offset: 0x079F size: 8 bit */
2562 SIUL_GPDO_8B_tag GPDO416; /* offset: 0x07A0 size: 8 bit */
2563 SIUL_GPDO_8B_tag GPDO417; /* offset: 0x07A1 size: 8 bit */
2564 SIUL_GPDO_8B_tag GPDO418; /* offset: 0x07A2 size: 8 bit */
2565 SIUL_GPDO_8B_tag GPDO419; /* offset: 0x07A3 size: 8 bit */
2566 SIUL_GPDO_8B_tag GPDO420; /* offset: 0x07A4 size: 8 bit */
2567 SIUL_GPDO_8B_tag GPDO421; /* offset: 0x07A5 size: 8 bit */
2568 SIUL_GPDO_8B_tag GPDO422; /* offset: 0x07A6 size: 8 bit */
2569 SIUL_GPDO_8B_tag GPDO423; /* offset: 0x07A7 size: 8 bit */
2570 SIUL_GPDO_8B_tag GPDO424; /* offset: 0x07A8 size: 8 bit */
2571 SIUL_GPDO_8B_tag GPDO425; /* offset: 0x07A9 size: 8 bit */
2572 SIUL_GPDO_8B_tag GPDO426; /* offset: 0x07AA size: 8 bit */
2573 SIUL_GPDO_8B_tag GPDO427; /* offset: 0x07AB size: 8 bit */
2574 SIUL_GPDO_8B_tag GPDO428; /* offset: 0x07AC size: 8 bit */
2575 SIUL_GPDO_8B_tag GPDO429; /* offset: 0x07AD size: 8 bit */
2576 SIUL_GPDO_8B_tag GPDO430; /* offset: 0x07AE size: 8 bit */
2577 SIUL_GPDO_8B_tag GPDO431; /* offset: 0x07AF size: 8 bit */
2578 SIUL_GPDO_8B_tag GPDO432; /* offset: 0x07B0 size: 8 bit */
2579 SIUL_GPDO_8B_tag GPDO433; /* offset: 0x07B1 size: 8 bit */
2580 SIUL_GPDO_8B_tag GPDO434; /* offset: 0x07B2 size: 8 bit */
2581 SIUL_GPDO_8B_tag GPDO435; /* offset: 0x07B3 size: 8 bit */
2582 SIUL_GPDO_8B_tag GPDO436; /* offset: 0x07B4 size: 8 bit */
2583 SIUL_GPDO_8B_tag GPDO437; /* offset: 0x07B5 size: 8 bit */
2584 SIUL_GPDO_8B_tag GPDO438; /* offset: 0x07B6 size: 8 bit */
2585 SIUL_GPDO_8B_tag GPDO439; /* offset: 0x07B7 size: 8 bit */
2586 SIUL_GPDO_8B_tag GPDO440; /* offset: 0x07B8 size: 8 bit */
2587 SIUL_GPDO_8B_tag GPDO441; /* offset: 0x07B9 size: 8 bit */
2588 SIUL_GPDO_8B_tag GPDO442; /* offset: 0x07BA size: 8 bit */
2589 SIUL_GPDO_8B_tag GPDO443; /* offset: 0x07BB size: 8 bit */
2590 SIUL_GPDO_8B_tag GPDO444; /* offset: 0x07BC size: 8 bit */
2591 SIUL_GPDO_8B_tag GPDO445; /* offset: 0x07BD size: 8 bit */
2592 SIUL_GPDO_8B_tag GPDO446; /* offset: 0x07BE size: 8 bit */
2593 SIUL_GPDO_8B_tag GPDO447; /* offset: 0x07BF size: 8 bit */
2594 SIUL_GPDO_8B_tag GPDO448; /* offset: 0x07C0 size: 8 bit */
2595 SIUL_GPDO_8B_tag GPDO449; /* offset: 0x07C1 size: 8 bit */
2596 SIUL_GPDO_8B_tag GPDO450; /* offset: 0x07C2 size: 8 bit */
2597 SIUL_GPDO_8B_tag GPDO451; /* offset: 0x07C3 size: 8 bit */
2598 SIUL_GPDO_8B_tag GPDO452; /* offset: 0x07C4 size: 8 bit */
2599 SIUL_GPDO_8B_tag GPDO453; /* offset: 0x07C5 size: 8 bit */
2600 SIUL_GPDO_8B_tag GPDO454; /* offset: 0x07C6 size: 8 bit */
2601 SIUL_GPDO_8B_tag GPDO455; /* offset: 0x07C7 size: 8 bit */
2602 SIUL_GPDO_8B_tag GPDO456; /* offset: 0x07C8 size: 8 bit */
2603 SIUL_GPDO_8B_tag GPDO457; /* offset: 0x07C9 size: 8 bit */
2604 SIUL_GPDO_8B_tag GPDO458; /* offset: 0x07CA size: 8 bit */
2605 SIUL_GPDO_8B_tag GPDO459; /* offset: 0x07CB size: 8 bit */
2606 SIUL_GPDO_8B_tag GPDO460; /* offset: 0x07CC size: 8 bit */
2607 SIUL_GPDO_8B_tag GPDO461; /* offset: 0x07CD size: 8 bit */
2608 SIUL_GPDO_8B_tag GPDO462; /* offset: 0x07CE size: 8 bit */
2609 SIUL_GPDO_8B_tag GPDO463; /* offset: 0x07CF size: 8 bit */
2610 SIUL_GPDO_8B_tag GPDO464; /* offset: 0x07D0 size: 8 bit */
2611 SIUL_GPDO_8B_tag GPDO465; /* offset: 0x07D1 size: 8 bit */
2612 SIUL_GPDO_8B_tag GPDO466; /* offset: 0x07D2 size: 8 bit */
2613 SIUL_GPDO_8B_tag GPDO467; /* offset: 0x07D3 size: 8 bit */
2614 SIUL_GPDO_8B_tag GPDO468; /* offset: 0x07D4 size: 8 bit */
2615 SIUL_GPDO_8B_tag GPDO469; /* offset: 0x07D5 size: 8 bit */
2616 SIUL_GPDO_8B_tag GPDO470; /* offset: 0x07D6 size: 8 bit */
2617 SIUL_GPDO_8B_tag GPDO471; /* offset: 0x07D7 size: 8 bit */
2618 SIUL_GPDO_8B_tag GPDO472; /* offset: 0x07D8 size: 8 bit */
2619 SIUL_GPDO_8B_tag GPDO473; /* offset: 0x07D9 size: 8 bit */
2620 SIUL_GPDO_8B_tag GPDO474; /* offset: 0x07DA size: 8 bit */
2621 SIUL_GPDO_8B_tag GPDO475; /* offset: 0x07DB size: 8 bit */
2622 SIUL_GPDO_8B_tag GPDO476; /* offset: 0x07DC size: 8 bit */
2623 SIUL_GPDO_8B_tag GPDO477; /* offset: 0x07DD size: 8 bit */
2624 SIUL_GPDO_8B_tag GPDO478; /* offset: 0x07DE size: 8 bit */
2625 SIUL_GPDO_8B_tag GPDO479; /* offset: 0x07DF size: 8 bit */
2626 SIUL_GPDO_8B_tag GPDO480; /* offset: 0x07E0 size: 8 bit */
2627 SIUL_GPDO_8B_tag GPDO481; /* offset: 0x07E1 size: 8 bit */
2628 SIUL_GPDO_8B_tag GPDO482; /* offset: 0x07E2 size: 8 bit */
2629 SIUL_GPDO_8B_tag GPDO483; /* offset: 0x07E3 size: 8 bit */
2630 SIUL_GPDO_8B_tag GPDO484; /* offset: 0x07E4 size: 8 bit */
2631 SIUL_GPDO_8B_tag GPDO485; /* offset: 0x07E5 size: 8 bit */
2632 SIUL_GPDO_8B_tag GPDO486; /* offset: 0x07E6 size: 8 bit */
2633 SIUL_GPDO_8B_tag GPDO487; /* offset: 0x07E7 size: 8 bit */
2634 SIUL_GPDO_8B_tag GPDO488; /* offset: 0x07E8 size: 8 bit */
2635 SIUL_GPDO_8B_tag GPDO489; /* offset: 0x07E9 size: 8 bit */
2636 SIUL_GPDO_8B_tag GPDO490; /* offset: 0x07EA size: 8 bit */
2637 SIUL_GPDO_8B_tag GPDO491; /* offset: 0x07EB size: 8 bit */
2638 SIUL_GPDO_8B_tag GPDO492; /* offset: 0x07EC size: 8 bit */
2639 SIUL_GPDO_8B_tag GPDO493; /* offset: 0x07ED size: 8 bit */
2640 SIUL_GPDO_8B_tag GPDO494; /* offset: 0x07EE size: 8 bit */
2641 SIUL_GPDO_8B_tag GPDO495; /* offset: 0x07EF size: 8 bit */
2642 SIUL_GPDO_8B_tag GPDO496; /* offset: 0x07F0 size: 8 bit */
2643 SIUL_GPDO_8B_tag GPDO497; /* offset: 0x07F1 size: 8 bit */
2644 SIUL_GPDO_8B_tag GPDO498; /* offset: 0x07F2 size: 8 bit */
2645 SIUL_GPDO_8B_tag GPDO499; /* offset: 0x07F3 size: 8 bit */
2646 SIUL_GPDO_8B_tag GPDO500; /* offset: 0x07F4 size: 8 bit */
2647 SIUL_GPDO_8B_tag GPDO501; /* offset: 0x07F5 size: 8 bit */
2648 SIUL_GPDO_8B_tag GPDO502; /* offset: 0x07F6 size: 8 bit */
2649 SIUL_GPDO_8B_tag GPDO503; /* offset: 0x07F7 size: 8 bit */
2650 SIUL_GPDO_8B_tag GPDO504; /* offset: 0x07F8 size: 8 bit */
2651 SIUL_GPDO_8B_tag GPDO505; /* offset: 0x07F9 size: 8 bit */
2652 SIUL_GPDO_8B_tag GPDO506; /* offset: 0x07FA size: 8 bit */
2653 SIUL_GPDO_8B_tag GPDO507; /* offset: 0x07FB size: 8 bit */
2654 SIUL_GPDO_8B_tag GPDO508; /* offset: 0x07FC size: 8 bit */
2655 SIUL_GPDO_8B_tag GPDO509; /* offset: 0x07FD size: 8 bit */
2656 SIUL_GPDO_8B_tag GPDO510; /* offset: 0x07FE size: 8 bit */
2657 SIUL_GPDO_8B_tag GPDO511; /* offset: 0x07FF size: 8 bit */
2658 };
2659
2660 };
2661 union {
2662 /* GPDI - GPIO Pad Data Input Register */
2663 SIUL_GPDI_32B_tag GPDI_32B[128]; /* offset: 0x0800 (0x0004 x 128) */
2664
2665 /* GPDI - GPIO Pad Data Input Register */
2666 SIUL_GPDI_8B_tag GPDI[512]; /* offset: 0x0800 (0x0001 x 512) */
2667
2668 struct {
2669 /* GPDI - GPIO Pad Data Input Register */
2670 SIUL_GPDI_32B_tag GPDI0_3; /* offset: 0x0800 size: 32 bit */
2671 SIUL_GPDI_32B_tag GPDI4_7; /* offset: 0x0804 size: 32 bit */
2672 SIUL_GPDI_32B_tag GPDI8_11; /* offset: 0x0808 size: 32 bit */
2673 SIUL_GPDI_32B_tag GPDI12_15; /* offset: 0x080C size: 32 bit */
2674 SIUL_GPDI_32B_tag GPDI16_19; /* offset: 0x0810 size: 32 bit */
2675 SIUL_GPDI_32B_tag GPDI20_23; /* offset: 0x0814 size: 32 bit */
2676 SIUL_GPDI_32B_tag GPDI24_27; /* offset: 0x0818 size: 32 bit */
2677 SIUL_GPDI_32B_tag GPDI28_31; /* offset: 0x081C size: 32 bit */
2678 SIUL_GPDI_32B_tag GPDI32_35; /* offset: 0x0820 size: 32 bit */
2679 SIUL_GPDI_32B_tag GPDI36_39; /* offset: 0x0824 size: 32 bit */
2680 SIUL_GPDI_32B_tag GPDI40_43; /* offset: 0x0828 size: 32 bit */
2681 SIUL_GPDI_32B_tag GPDI44_47; /* offset: 0x082C size: 32 bit */
2682 SIUL_GPDI_32B_tag GPDI48_51; /* offset: 0x0830 size: 32 bit */
2683 SIUL_GPDI_32B_tag GPDI52_55; /* offset: 0x0834 size: 32 bit */
2684 SIUL_GPDI_32B_tag GPDI56_59; /* offset: 0x0838 size: 32 bit */
2685 SIUL_GPDI_32B_tag GPDI60_63; /* offset: 0x083C size: 32 bit */
2686 SIUL_GPDI_32B_tag GPDI64_67; /* offset: 0x0840 size: 32 bit */
2687 SIUL_GPDI_32B_tag GPDI68_71; /* offset: 0x0844 size: 32 bit */
2688 SIUL_GPDI_32B_tag GPDI72_75; /* offset: 0x0848 size: 32 bit */
2689 SIUL_GPDI_32B_tag GPDI76_79; /* offset: 0x084C size: 32 bit */
2690 SIUL_GPDI_32B_tag GPDI80_83; /* offset: 0x0850 size: 32 bit */
2691 SIUL_GPDI_32B_tag GPDI84_87; /* offset: 0x0854 size: 32 bit */
2692 SIUL_GPDI_32B_tag GPDI88_91; /* offset: 0x0858 size: 32 bit */
2693 SIUL_GPDI_32B_tag GPDI92_95; /* offset: 0x085C size: 32 bit */
2694 SIUL_GPDI_32B_tag GPDI96_99; /* offset: 0x0860 size: 32 bit */
2695 SIUL_GPDI_32B_tag GPDI100_103; /* offset: 0x0864 size: 32 bit */
2696 SIUL_GPDI_32B_tag GPDI104_107; /* offset: 0x0868 size: 32 bit */
2697 SIUL_GPDI_32B_tag GPDI108_111; /* offset: 0x086C size: 32 bit */
2698 SIUL_GPDI_32B_tag GPDI112_115; /* offset: 0x0870 size: 32 bit */
2699 SIUL_GPDI_32B_tag GPDI116_119; /* offset: 0x0874 size: 32 bit */
2700 SIUL_GPDI_32B_tag GPDI120_123; /* offset: 0x0878 size: 32 bit */
2701 SIUL_GPDI_32B_tag GPDI124_127; /* offset: 0x087C size: 32 bit */
2702 SIUL_GPDI_32B_tag GPDI128_131; /* offset: 0x0880 size: 32 bit */
2703 SIUL_GPDI_32B_tag GPDI132_135; /* offset: 0x0884 size: 32 bit */
2704 SIUL_GPDI_32B_tag GPDI136_139; /* offset: 0x0888 size: 32 bit */
2705 SIUL_GPDI_32B_tag GPDI140_143; /* offset: 0x088C size: 32 bit */
2706 SIUL_GPDI_32B_tag GPDI144_147; /* offset: 0x0890 size: 32 bit */
2707 SIUL_GPDI_32B_tag GPDI148_151; /* offset: 0x0894 size: 32 bit */
2708 SIUL_GPDI_32B_tag GPDI152_155; /* offset: 0x0898 size: 32 bit */
2709 SIUL_GPDI_32B_tag GPDI156_159; /* offset: 0x089C size: 32 bit */
2710 SIUL_GPDI_32B_tag GPDI160_163; /* offset: 0x08A0 size: 32 bit */
2711 SIUL_GPDI_32B_tag GPDI164_167; /* offset: 0x08A4 size: 32 bit */
2712 SIUL_GPDI_32B_tag GPDI168_171; /* offset: 0x08A8 size: 32 bit */
2713 SIUL_GPDI_32B_tag GPDI172_175; /* offset: 0x08AC size: 32 bit */
2714 SIUL_GPDI_32B_tag GPDI176_179; /* offset: 0x08B0 size: 32 bit */
2715 SIUL_GPDI_32B_tag GPDI180_183; /* offset: 0x08B4 size: 32 bit */
2716 SIUL_GPDI_32B_tag GPDI184_187; /* offset: 0x08B8 size: 32 bit */
2717 SIUL_GPDI_32B_tag GPDI188_191; /* offset: 0x08BC size: 32 bit */
2718 SIUL_GPDI_32B_tag GPDI192_195; /* offset: 0x08C0 size: 32 bit */
2719 SIUL_GPDI_32B_tag GPDI196_199; /* offset: 0x08C4 size: 32 bit */
2720 SIUL_GPDI_32B_tag GPDI200_203; /* offset: 0x08C8 size: 32 bit */
2721 SIUL_GPDI_32B_tag GPDI204_207; /* offset: 0x08CC size: 32 bit */
2722 SIUL_GPDI_32B_tag GPDI208_211; /* offset: 0x08D0 size: 32 bit */
2723 SIUL_GPDI_32B_tag GPDI212_215; /* offset: 0x08D4 size: 32 bit */
2724 SIUL_GPDI_32B_tag GPDI216_219; /* offset: 0x08D8 size: 32 bit */
2725 SIUL_GPDI_32B_tag GPDI220_223; /* offset: 0x08DC size: 32 bit */
2726 SIUL_GPDI_32B_tag GPDI224_227; /* offset: 0x08E0 size: 32 bit */
2727 SIUL_GPDI_32B_tag GPDI228_231; /* offset: 0x08E4 size: 32 bit */
2728 SIUL_GPDI_32B_tag GPDI232_235; /* offset: 0x08E8 size: 32 bit */
2729 SIUL_GPDI_32B_tag GPDI236_239; /* offset: 0x08EC size: 32 bit */
2730 SIUL_GPDI_32B_tag GPDI240_243; /* offset: 0x08F0 size: 32 bit */
2731 SIUL_GPDI_32B_tag GPDI244_247; /* offset: 0x08F4 size: 32 bit */
2732 SIUL_GPDI_32B_tag GPDI248_251; /* offset: 0x08F8 size: 32 bit */
2733 SIUL_GPDI_32B_tag GPDI252_255; /* offset: 0x08FC size: 32 bit */
2734 SIUL_GPDI_32B_tag GPDI256_259; /* offset: 0x0900 size: 32 bit */
2735 SIUL_GPDI_32B_tag GPDI260_263; /* offset: 0x0904 size: 32 bit */
2736 SIUL_GPDI_32B_tag GPDI264_267; /* offset: 0x0908 size: 32 bit */
2737 SIUL_GPDI_32B_tag GPDI268_271; /* offset: 0x090C size: 32 bit */
2738 SIUL_GPDI_32B_tag GPDI272_275; /* offset: 0x0910 size: 32 bit */
2739 SIUL_GPDI_32B_tag GPDI276_279; /* offset: 0x0914 size: 32 bit */
2740 SIUL_GPDI_32B_tag GPDI280_283; /* offset: 0x0918 size: 32 bit */
2741 SIUL_GPDI_32B_tag GPDI284_287; /* offset: 0x091C size: 32 bit */
2742 SIUL_GPDI_32B_tag GPDI288_291; /* offset: 0x0920 size: 32 bit */
2743 SIUL_GPDI_32B_tag GPDI292_295; /* offset: 0x0924 size: 32 bit */
2744 SIUL_GPDI_32B_tag GPDI296_299; /* offset: 0x0928 size: 32 bit */
2745 SIUL_GPDI_32B_tag GPDI300_303; /* offset: 0x092C size: 32 bit */
2746 SIUL_GPDI_32B_tag GPDI304_307; /* offset: 0x0930 size: 32 bit */
2747 SIUL_GPDI_32B_tag GPDI308_311; /* offset: 0x0934 size: 32 bit */
2748 SIUL_GPDI_32B_tag GPDI312_315; /* offset: 0x0938 size: 32 bit */
2749 SIUL_GPDI_32B_tag GPDI316_319; /* offset: 0x093C size: 32 bit */
2750 SIUL_GPDI_32B_tag GPDI320_323; /* offset: 0x0940 size: 32 bit */
2751 SIUL_GPDI_32B_tag GPDI324_327; /* offset: 0x0944 size: 32 bit */
2752 SIUL_GPDI_32B_tag GPDI328_331; /* offset: 0x0948 size: 32 bit */
2753 SIUL_GPDI_32B_tag GPDI332_335; /* offset: 0x094C size: 32 bit */
2754 SIUL_GPDI_32B_tag GPDI336_339; /* offset: 0x0950 size: 32 bit */
2755 SIUL_GPDI_32B_tag GPDI340_343; /* offset: 0x0954 size: 32 bit */
2756 SIUL_GPDI_32B_tag GPDI344_347; /* offset: 0x0958 size: 32 bit */
2757 SIUL_GPDI_32B_tag GPDI348_351; /* offset: 0x095C size: 32 bit */
2758 SIUL_GPDI_32B_tag GPDI352_355; /* offset: 0x0960 size: 32 bit */
2759 SIUL_GPDI_32B_tag GPDI356_359; /* offset: 0x0964 size: 32 bit */
2760 SIUL_GPDI_32B_tag GPDI360_363; /* offset: 0x0968 size: 32 bit */
2761 SIUL_GPDI_32B_tag GPDI364_367; /* offset: 0x096C size: 32 bit */
2762 SIUL_GPDI_32B_tag GPDI368_371; /* offset: 0x0970 size: 32 bit */
2763 SIUL_GPDI_32B_tag GPDI372_375; /* offset: 0x0974 size: 32 bit */
2764 SIUL_GPDI_32B_tag GPDI376_379; /* offset: 0x0978 size: 32 bit */
2765 SIUL_GPDI_32B_tag GPDI380_383; /* offset: 0x097C size: 32 bit */
2766 SIUL_GPDI_32B_tag GPDI384_387; /* offset: 0x0980 size: 32 bit */
2767 SIUL_GPDI_32B_tag GPDI388_391; /* offset: 0x0984 size: 32 bit */
2768 SIUL_GPDI_32B_tag GPDI392_395; /* offset: 0x0988 size: 32 bit */
2769 SIUL_GPDI_32B_tag GPDI396_399; /* offset: 0x098C size: 32 bit */
2770 SIUL_GPDI_32B_tag GPDI400_403; /* offset: 0x0990 size: 32 bit */
2771 SIUL_GPDI_32B_tag GPDI404_407; /* offset: 0x0994 size: 32 bit */
2772 SIUL_GPDI_32B_tag GPDI408_411; /* offset: 0x0998 size: 32 bit */
2773 SIUL_GPDI_32B_tag GPDI412_415; /* offset: 0x099C size: 32 bit */
2774 SIUL_GPDI_32B_tag GPDI416_419; /* offset: 0x09A0 size: 32 bit */
2775 SIUL_GPDI_32B_tag GPDI420_423; /* offset: 0x09A4 size: 32 bit */
2776 SIUL_GPDI_32B_tag GPDI424_427; /* offset: 0x09A8 size: 32 bit */
2777 SIUL_GPDI_32B_tag GPDI428_431; /* offset: 0x09AC size: 32 bit */
2778 SIUL_GPDI_32B_tag GPDI432_435; /* offset: 0x09B0 size: 32 bit */
2779 SIUL_GPDI_32B_tag GPDI436_439; /* offset: 0x09B4 size: 32 bit */
2780 SIUL_GPDI_32B_tag GPDI440_443; /* offset: 0x09B8 size: 32 bit */
2781 SIUL_GPDI_32B_tag GPDI444_447; /* offset: 0x09BC size: 32 bit */
2782 SIUL_GPDI_32B_tag GPDI448_451; /* offset: 0x09C0 size: 32 bit */
2783 SIUL_GPDI_32B_tag GPDI452_455; /* offset: 0x09C4 size: 32 bit */
2784 SIUL_GPDI_32B_tag GPDI456_459; /* offset: 0x09C8 size: 32 bit */
2785 SIUL_GPDI_32B_tag GPDI460_463; /* offset: 0x09CC size: 32 bit */
2786 SIUL_GPDI_32B_tag GPDI464_467; /* offset: 0x09D0 size: 32 bit */
2787 SIUL_GPDI_32B_tag GPDI468_471; /* offset: 0x09D4 size: 32 bit */
2788 SIUL_GPDI_32B_tag GPDI472_475; /* offset: 0x09D8 size: 32 bit */
2789 SIUL_GPDI_32B_tag GPDI476_479; /* offset: 0x09DC size: 32 bit */
2790 SIUL_GPDI_32B_tag GPDI480_483; /* offset: 0x09E0 size: 32 bit */
2791 SIUL_GPDI_32B_tag GPDI484_487; /* offset: 0x09E4 size: 32 bit */
2792 SIUL_GPDI_32B_tag GPDI488_491; /* offset: 0x09E8 size: 32 bit */
2793 SIUL_GPDI_32B_tag GPDI492_495; /* offset: 0x09EC size: 32 bit */
2794 SIUL_GPDI_32B_tag GPDI496_499; /* offset: 0x09F0 size: 32 bit */
2795 SIUL_GPDI_32B_tag GPDI500_503; /* offset: 0x09F4 size: 32 bit */
2796 SIUL_GPDI_32B_tag GPDI504_507; /* offset: 0x09F8 size: 32 bit */
2797 SIUL_GPDI_32B_tag GPDI508_511; /* offset: 0x09FC size: 32 bit */
2798 };
2799
2800 struct {
2801 /* GPDI - GPIO Pad Data Input Register */
2802 SIUL_GPDI_8B_tag GPDI0; /* offset: 0x0800 size: 8 bit */
2803 SIUL_GPDI_8B_tag GPDI1; /* offset: 0x0801 size: 8 bit */
2804 SIUL_GPDI_8B_tag GPDI2; /* offset: 0x0802 size: 8 bit */
2805 SIUL_GPDI_8B_tag GPDI3; /* offset: 0x0803 size: 8 bit */
2806 SIUL_GPDI_8B_tag GPDI4; /* offset: 0x0804 size: 8 bit */
2807 SIUL_GPDI_8B_tag GPDI5; /* offset: 0x0805 size: 8 bit */
2808 SIUL_GPDI_8B_tag GPDI6; /* offset: 0x0806 size: 8 bit */
2809 SIUL_GPDI_8B_tag GPDI7; /* offset: 0x0807 size: 8 bit */
2810 SIUL_GPDI_8B_tag GPDI8; /* offset: 0x0808 size: 8 bit */
2811 SIUL_GPDI_8B_tag GPDI9; /* offset: 0x0809 size: 8 bit */
2812 SIUL_GPDI_8B_tag GPDI10; /* offset: 0x080A size: 8 bit */
2813 SIUL_GPDI_8B_tag GPDI11; /* offset: 0x080B size: 8 bit */
2814 SIUL_GPDI_8B_tag GPDI12; /* offset: 0x080C size: 8 bit */
2815 SIUL_GPDI_8B_tag GPDI13; /* offset: 0x080D size: 8 bit */
2816 SIUL_GPDI_8B_tag GPDI14; /* offset: 0x080E size: 8 bit */
2817 SIUL_GPDI_8B_tag GPDI15; /* offset: 0x080F size: 8 bit */
2818 SIUL_GPDI_8B_tag GPDI16; /* offset: 0x0810 size: 8 bit */
2819 SIUL_GPDI_8B_tag GPDI17; /* offset: 0x0811 size: 8 bit */
2820 SIUL_GPDI_8B_tag GPDI18; /* offset: 0x0812 size: 8 bit */
2821 SIUL_GPDI_8B_tag GPDI19; /* offset: 0x0813 size: 8 bit */
2822 SIUL_GPDI_8B_tag GPDI20; /* offset: 0x0814 size: 8 bit */
2823 SIUL_GPDI_8B_tag GPDI21; /* offset: 0x0815 size: 8 bit */
2824 SIUL_GPDI_8B_tag GPDI22; /* offset: 0x0816 size: 8 bit */
2825 SIUL_GPDI_8B_tag GPDI23; /* offset: 0x0817 size: 8 bit */
2826 SIUL_GPDI_8B_tag GPDI24; /* offset: 0x0818 size: 8 bit */
2827 SIUL_GPDI_8B_tag GPDI25; /* offset: 0x0819 size: 8 bit */
2828 SIUL_GPDI_8B_tag GPDI26; /* offset: 0x081A size: 8 bit */
2829 SIUL_GPDI_8B_tag GPDI27; /* offset: 0x081B size: 8 bit */
2830 SIUL_GPDI_8B_tag GPDI28; /* offset: 0x081C size: 8 bit */
2831 SIUL_GPDI_8B_tag GPDI29; /* offset: 0x081D size: 8 bit */
2832 SIUL_GPDI_8B_tag GPDI30; /* offset: 0x081E size: 8 bit */
2833 SIUL_GPDI_8B_tag GPDI31; /* offset: 0x081F size: 8 bit */
2834 SIUL_GPDI_8B_tag GPDI32; /* offset: 0x0820 size: 8 bit */
2835 SIUL_GPDI_8B_tag GPDI33; /* offset: 0x0821 size: 8 bit */
2836 SIUL_GPDI_8B_tag GPDI34; /* offset: 0x0822 size: 8 bit */
2837 SIUL_GPDI_8B_tag GPDI35; /* offset: 0x0823 size: 8 bit */
2838 SIUL_GPDI_8B_tag GPDI36; /* offset: 0x0824 size: 8 bit */
2839 SIUL_GPDI_8B_tag GPDI37; /* offset: 0x0825 size: 8 bit */
2840 SIUL_GPDI_8B_tag GPDI38; /* offset: 0x0826 size: 8 bit */
2841 SIUL_GPDI_8B_tag GPDI39; /* offset: 0x0827 size: 8 bit */
2842 SIUL_GPDI_8B_tag GPDI40; /* offset: 0x0828 size: 8 bit */
2843 SIUL_GPDI_8B_tag GPDI41; /* offset: 0x0829 size: 8 bit */
2844 SIUL_GPDI_8B_tag GPDI42; /* offset: 0x082A size: 8 bit */
2845 SIUL_GPDI_8B_tag GPDI43; /* offset: 0x082B size: 8 bit */
2846 SIUL_GPDI_8B_tag GPDI44; /* offset: 0x082C size: 8 bit */
2847 SIUL_GPDI_8B_tag GPDI45; /* offset: 0x082D size: 8 bit */
2848 SIUL_GPDI_8B_tag GPDI46; /* offset: 0x082E size: 8 bit */
2849 SIUL_GPDI_8B_tag GPDI47; /* offset: 0x082F size: 8 bit */
2850 SIUL_GPDI_8B_tag GPDI48; /* offset: 0x0830 size: 8 bit */
2851 SIUL_GPDI_8B_tag GPDI49; /* offset: 0x0831 size: 8 bit */
2852 SIUL_GPDI_8B_tag GPDI50; /* offset: 0x0832 size: 8 bit */
2853 SIUL_GPDI_8B_tag GPDI51; /* offset: 0x0833 size: 8 bit */
2854 SIUL_GPDI_8B_tag GPDI52; /* offset: 0x0834 size: 8 bit */
2855 SIUL_GPDI_8B_tag GPDI53; /* offset: 0x0835 size: 8 bit */
2856 SIUL_GPDI_8B_tag GPDI54; /* offset: 0x0836 size: 8 bit */
2857 SIUL_GPDI_8B_tag GPDI55; /* offset: 0x0837 size: 8 bit */
2858 SIUL_GPDI_8B_tag GPDI56; /* offset: 0x0838 size: 8 bit */
2859 SIUL_GPDI_8B_tag GPDI57; /* offset: 0x0839 size: 8 bit */
2860 SIUL_GPDI_8B_tag GPDI58; /* offset: 0x083A size: 8 bit */
2861 SIUL_GPDI_8B_tag GPDI59; /* offset: 0x083B size: 8 bit */
2862 SIUL_GPDI_8B_tag GPDI60; /* offset: 0x083C size: 8 bit */
2863 SIUL_GPDI_8B_tag GPDI61; /* offset: 0x083D size: 8 bit */
2864 SIUL_GPDI_8B_tag GPDI62; /* offset: 0x083E size: 8 bit */
2865 SIUL_GPDI_8B_tag GPDI63; /* offset: 0x083F size: 8 bit */
2866 SIUL_GPDI_8B_tag GPDI64; /* offset: 0x0840 size: 8 bit */
2867 SIUL_GPDI_8B_tag GPDI65; /* offset: 0x0841 size: 8 bit */
2868 SIUL_GPDI_8B_tag GPDI66; /* offset: 0x0842 size: 8 bit */
2869 SIUL_GPDI_8B_tag GPDI67; /* offset: 0x0843 size: 8 bit */
2870 SIUL_GPDI_8B_tag GPDI68; /* offset: 0x0844 size: 8 bit */
2871 SIUL_GPDI_8B_tag GPDI69; /* offset: 0x0845 size: 8 bit */
2872 SIUL_GPDI_8B_tag GPDI70; /* offset: 0x0846 size: 8 bit */
2873 SIUL_GPDI_8B_tag GPDI71; /* offset: 0x0847 size: 8 bit */
2874 SIUL_GPDI_8B_tag GPDI72; /* offset: 0x0848 size: 8 bit */
2875 SIUL_GPDI_8B_tag GPDI73; /* offset: 0x0849 size: 8 bit */
2876 SIUL_GPDI_8B_tag GPDI74; /* offset: 0x084A size: 8 bit */
2877 SIUL_GPDI_8B_tag GPDI75; /* offset: 0x084B size: 8 bit */
2878 SIUL_GPDI_8B_tag GPDI76; /* offset: 0x084C size: 8 bit */
2879 SIUL_GPDI_8B_tag GPDI77; /* offset: 0x084D size: 8 bit */
2880 SIUL_GPDI_8B_tag GPDI78; /* offset: 0x084E size: 8 bit */
2881 SIUL_GPDI_8B_tag GPDI79; /* offset: 0x084F size: 8 bit */
2882 SIUL_GPDI_8B_tag GPDI80; /* offset: 0x0850 size: 8 bit */
2883 SIUL_GPDI_8B_tag GPDI81; /* offset: 0x0851 size: 8 bit */
2884 SIUL_GPDI_8B_tag GPDI82; /* offset: 0x0852 size: 8 bit */
2885 SIUL_GPDI_8B_tag GPDI83; /* offset: 0x0853 size: 8 bit */
2886 SIUL_GPDI_8B_tag GPDI84; /* offset: 0x0854 size: 8 bit */
2887 SIUL_GPDI_8B_tag GPDI85; /* offset: 0x0855 size: 8 bit */
2888 SIUL_GPDI_8B_tag GPDI86; /* offset: 0x0856 size: 8 bit */
2889 SIUL_GPDI_8B_tag GPDI87; /* offset: 0x0857 size: 8 bit */
2890 SIUL_GPDI_8B_tag GPDI88; /* offset: 0x0858 size: 8 bit */
2891 SIUL_GPDI_8B_tag GPDI89; /* offset: 0x0859 size: 8 bit */
2892 SIUL_GPDI_8B_tag GPDI90; /* offset: 0x085A size: 8 bit */
2893 SIUL_GPDI_8B_tag GPDI91; /* offset: 0x085B size: 8 bit */
2894 SIUL_GPDI_8B_tag GPDI92; /* offset: 0x085C size: 8 bit */
2895 SIUL_GPDI_8B_tag GPDI93; /* offset: 0x085D size: 8 bit */
2896 SIUL_GPDI_8B_tag GPDI94; /* offset: 0x085E size: 8 bit */
2897 SIUL_GPDI_8B_tag GPDI95; /* offset: 0x085F size: 8 bit */
2898 SIUL_GPDI_8B_tag GPDI96; /* offset: 0x0860 size: 8 bit */
2899 SIUL_GPDI_8B_tag GPDI97; /* offset: 0x0861 size: 8 bit */
2900 SIUL_GPDI_8B_tag GPDI98; /* offset: 0x0862 size: 8 bit */
2901 SIUL_GPDI_8B_tag GPDI99; /* offset: 0x0863 size: 8 bit */
2902 SIUL_GPDI_8B_tag GPDI100; /* offset: 0x0864 size: 8 bit */
2903 SIUL_GPDI_8B_tag GPDI101; /* offset: 0x0865 size: 8 bit */
2904 SIUL_GPDI_8B_tag GPDI102; /* offset: 0x0866 size: 8 bit */
2905 SIUL_GPDI_8B_tag GPDI103; /* offset: 0x0867 size: 8 bit */
2906 SIUL_GPDI_8B_tag GPDI104; /* offset: 0x0868 size: 8 bit */
2907 SIUL_GPDI_8B_tag GPDI105; /* offset: 0x0869 size: 8 bit */
2908 SIUL_GPDI_8B_tag GPDI106; /* offset: 0x086A size: 8 bit */
2909 SIUL_GPDI_8B_tag GPDI107; /* offset: 0x086B size: 8 bit */
2910 SIUL_GPDI_8B_tag GPDI108; /* offset: 0x086C size: 8 bit */
2911 SIUL_GPDI_8B_tag GPDI109; /* offset: 0x086D size: 8 bit */
2912 SIUL_GPDI_8B_tag GPDI110; /* offset: 0x086E size: 8 bit */
2913 SIUL_GPDI_8B_tag GPDI111; /* offset: 0x086F size: 8 bit */
2914 SIUL_GPDI_8B_tag GPDI112; /* offset: 0x0870 size: 8 bit */
2915 SIUL_GPDI_8B_tag GPDI113; /* offset: 0x0871 size: 8 bit */
2916 SIUL_GPDI_8B_tag GPDI114; /* offset: 0x0872 size: 8 bit */
2917 SIUL_GPDI_8B_tag GPDI115; /* offset: 0x0873 size: 8 bit */
2918 SIUL_GPDI_8B_tag GPDI116; /* offset: 0x0874 size: 8 bit */
2919 SIUL_GPDI_8B_tag GPDI117; /* offset: 0x0875 size: 8 bit */
2920 SIUL_GPDI_8B_tag GPDI118; /* offset: 0x0876 size: 8 bit */
2921 SIUL_GPDI_8B_tag GPDI119; /* offset: 0x0877 size: 8 bit */
2922 SIUL_GPDI_8B_tag GPDI120; /* offset: 0x0878 size: 8 bit */
2923 SIUL_GPDI_8B_tag GPDI121; /* offset: 0x0879 size: 8 bit */
2924 SIUL_GPDI_8B_tag GPDI122; /* offset: 0x087A size: 8 bit */
2925 SIUL_GPDI_8B_tag GPDI123; /* offset: 0x087B size: 8 bit */
2926 SIUL_GPDI_8B_tag GPDI124; /* offset: 0x087C size: 8 bit */
2927 SIUL_GPDI_8B_tag GPDI125; /* offset: 0x087D size: 8 bit */
2928 SIUL_GPDI_8B_tag GPDI126; /* offset: 0x087E size: 8 bit */
2929 SIUL_GPDI_8B_tag GPDI127; /* offset: 0x087F size: 8 bit */
2930 SIUL_GPDI_8B_tag GPDI128; /* offset: 0x0880 size: 8 bit */
2931 SIUL_GPDI_8B_tag GPDI129; /* offset: 0x0881 size: 8 bit */
2932 SIUL_GPDI_8B_tag GPDI130; /* offset: 0x0882 size: 8 bit */
2933 SIUL_GPDI_8B_tag GPDI131; /* offset: 0x0883 size: 8 bit */
2934 SIUL_GPDI_8B_tag GPDI132; /* offset: 0x0884 size: 8 bit */
2935 SIUL_GPDI_8B_tag GPDI133; /* offset: 0x0885 size: 8 bit */
2936 SIUL_GPDI_8B_tag GPDI134; /* offset: 0x0886 size: 8 bit */
2937 SIUL_GPDI_8B_tag GPDI135; /* offset: 0x0887 size: 8 bit */
2938 SIUL_GPDI_8B_tag GPDI136; /* offset: 0x0888 size: 8 bit */
2939 SIUL_GPDI_8B_tag GPDI137; /* offset: 0x0889 size: 8 bit */
2940 SIUL_GPDI_8B_tag GPDI138; /* offset: 0x088A size: 8 bit */
2941 SIUL_GPDI_8B_tag GPDI139; /* offset: 0x088B size: 8 bit */
2942 SIUL_GPDI_8B_tag GPDI140; /* offset: 0x088C size: 8 bit */
2943 SIUL_GPDI_8B_tag GPDI141; /* offset: 0x088D size: 8 bit */
2944 SIUL_GPDI_8B_tag GPDI142; /* offset: 0x088E size: 8 bit */
2945 SIUL_GPDI_8B_tag GPDI143; /* offset: 0x088F size: 8 bit */
2946 SIUL_GPDI_8B_tag GPDI144; /* offset: 0x0890 size: 8 bit */
2947 SIUL_GPDI_8B_tag GPDI145; /* offset: 0x0891 size: 8 bit */
2948 SIUL_GPDI_8B_tag GPDI146; /* offset: 0x0892 size: 8 bit */
2949 SIUL_GPDI_8B_tag GPDI147; /* offset: 0x0893 size: 8 bit */
2950 SIUL_GPDI_8B_tag GPDI148; /* offset: 0x0894 size: 8 bit */
2951 SIUL_GPDI_8B_tag GPDI149; /* offset: 0x0895 size: 8 bit */
2952 SIUL_GPDI_8B_tag GPDI150; /* offset: 0x0896 size: 8 bit */
2953 SIUL_GPDI_8B_tag GPDI151; /* offset: 0x0897 size: 8 bit */
2954 SIUL_GPDI_8B_tag GPDI152; /* offset: 0x0898 size: 8 bit */
2955 SIUL_GPDI_8B_tag GPDI153; /* offset: 0x0899 size: 8 bit */
2956 SIUL_GPDI_8B_tag GPDI154; /* offset: 0x089A size: 8 bit */
2957 SIUL_GPDI_8B_tag GPDI155; /* offset: 0x089B size: 8 bit */
2958 SIUL_GPDI_8B_tag GPDI156; /* offset: 0x089C size: 8 bit */
2959 SIUL_GPDI_8B_tag GPDI157; /* offset: 0x089D size: 8 bit */
2960 SIUL_GPDI_8B_tag GPDI158; /* offset: 0x089E size: 8 bit */
2961 SIUL_GPDI_8B_tag GPDI159; /* offset: 0x089F size: 8 bit */
2962 SIUL_GPDI_8B_tag GPDI160; /* offset: 0x08A0 size: 8 bit */
2963 SIUL_GPDI_8B_tag GPDI161; /* offset: 0x08A1 size: 8 bit */
2964 SIUL_GPDI_8B_tag GPDI162; /* offset: 0x08A2 size: 8 bit */
2965 SIUL_GPDI_8B_tag GPDI163; /* offset: 0x08A3 size: 8 bit */
2966 SIUL_GPDI_8B_tag GPDI164; /* offset: 0x08A4 size: 8 bit */
2967 SIUL_GPDI_8B_tag GPDI165; /* offset: 0x08A5 size: 8 bit */
2968 SIUL_GPDI_8B_tag GPDI166; /* offset: 0x08A6 size: 8 bit */
2969 SIUL_GPDI_8B_tag GPDI167; /* offset: 0x08A7 size: 8 bit */
2970 SIUL_GPDI_8B_tag GPDI168; /* offset: 0x08A8 size: 8 bit */
2971 SIUL_GPDI_8B_tag GPDI169; /* offset: 0x08A9 size: 8 bit */
2972 SIUL_GPDI_8B_tag GPDI170; /* offset: 0x08AA size: 8 bit */
2973 SIUL_GPDI_8B_tag GPDI171; /* offset: 0x08AB size: 8 bit */
2974 SIUL_GPDI_8B_tag GPDI172; /* offset: 0x08AC size: 8 bit */
2975 SIUL_GPDI_8B_tag GPDI173; /* offset: 0x08AD size: 8 bit */
2976 SIUL_GPDI_8B_tag GPDI174; /* offset: 0x08AE size: 8 bit */
2977 SIUL_GPDI_8B_tag GPDI175; /* offset: 0x08AF size: 8 bit */
2978 SIUL_GPDI_8B_tag GPDI176; /* offset: 0x08B0 size: 8 bit */
2979 SIUL_GPDI_8B_tag GPDI177; /* offset: 0x08B1 size: 8 bit */
2980 SIUL_GPDI_8B_tag GPDI178; /* offset: 0x08B2 size: 8 bit */
2981 SIUL_GPDI_8B_tag GPDI179; /* offset: 0x08B3 size: 8 bit */
2982 SIUL_GPDI_8B_tag GPDI180; /* offset: 0x08B4 size: 8 bit */
2983 SIUL_GPDI_8B_tag GPDI181; /* offset: 0x08B5 size: 8 bit */
2984 SIUL_GPDI_8B_tag GPDI182; /* offset: 0x08B6 size: 8 bit */
2985 SIUL_GPDI_8B_tag GPDI183; /* offset: 0x08B7 size: 8 bit */
2986 SIUL_GPDI_8B_tag GPDI184; /* offset: 0x08B8 size: 8 bit */
2987 SIUL_GPDI_8B_tag GPDI185; /* offset: 0x08B9 size: 8 bit */
2988 SIUL_GPDI_8B_tag GPDI186; /* offset: 0x08BA size: 8 bit */
2989 SIUL_GPDI_8B_tag GPDI187; /* offset: 0x08BB size: 8 bit */
2990 SIUL_GPDI_8B_tag GPDI188; /* offset: 0x08BC size: 8 bit */
2991 SIUL_GPDI_8B_tag GPDI189; /* offset: 0x08BD size: 8 bit */
2992 SIUL_GPDI_8B_tag GPDI190; /* offset: 0x08BE size: 8 bit */
2993 SIUL_GPDI_8B_tag GPDI191; /* offset: 0x08BF size: 8 bit */
2994 SIUL_GPDI_8B_tag GPDI192; /* offset: 0x08C0 size: 8 bit */
2995 SIUL_GPDI_8B_tag GPDI193; /* offset: 0x08C1 size: 8 bit */
2996 SIUL_GPDI_8B_tag GPDI194; /* offset: 0x08C2 size: 8 bit */
2997 SIUL_GPDI_8B_tag GPDI195; /* offset: 0x08C3 size: 8 bit */
2998 SIUL_GPDI_8B_tag GPDI196; /* offset: 0x08C4 size: 8 bit */
2999 SIUL_GPDI_8B_tag GPDI197; /* offset: 0x08C5 size: 8 bit */
3000 SIUL_GPDI_8B_tag GPDI198; /* offset: 0x08C6 size: 8 bit */
3001 SIUL_GPDI_8B_tag GPDI199; /* offset: 0x08C7 size: 8 bit */
3002 SIUL_GPDI_8B_tag GPDI200; /* offset: 0x08C8 size: 8 bit */
3003 SIUL_GPDI_8B_tag GPDI201; /* offset: 0x08C9 size: 8 bit */
3004 SIUL_GPDI_8B_tag GPDI202; /* offset: 0x08CA size: 8 bit */
3005 SIUL_GPDI_8B_tag GPDI203; /* offset: 0x08CB size: 8 bit */
3006 SIUL_GPDI_8B_tag GPDI204; /* offset: 0x08CC size: 8 bit */
3007 SIUL_GPDI_8B_tag GPDI205; /* offset: 0x08CD size: 8 bit */
3008 SIUL_GPDI_8B_tag GPDI206; /* offset: 0x08CE size: 8 bit */
3009 SIUL_GPDI_8B_tag GPDI207; /* offset: 0x08CF size: 8 bit */
3010 SIUL_GPDI_8B_tag GPDI208; /* offset: 0x08D0 size: 8 bit */
3011 SIUL_GPDI_8B_tag GPDI209; /* offset: 0x08D1 size: 8 bit */
3012 SIUL_GPDI_8B_tag GPDI210; /* offset: 0x08D2 size: 8 bit */
3013 SIUL_GPDI_8B_tag GPDI211; /* offset: 0x08D3 size: 8 bit */
3014 SIUL_GPDI_8B_tag GPDI212; /* offset: 0x08D4 size: 8 bit */
3015 SIUL_GPDI_8B_tag GPDI213; /* offset: 0x08D5 size: 8 bit */
3016 SIUL_GPDI_8B_tag GPDI214; /* offset: 0x08D6 size: 8 bit */
3017 SIUL_GPDI_8B_tag GPDI215; /* offset: 0x08D7 size: 8 bit */
3018 SIUL_GPDI_8B_tag GPDI216; /* offset: 0x08D8 size: 8 bit */
3019 SIUL_GPDI_8B_tag GPDI217; /* offset: 0x08D9 size: 8 bit */
3020 SIUL_GPDI_8B_tag GPDI218; /* offset: 0x08DA size: 8 bit */
3021 SIUL_GPDI_8B_tag GPDI219; /* offset: 0x08DB size: 8 bit */
3022 SIUL_GPDI_8B_tag GPDI220; /* offset: 0x08DC size: 8 bit */
3023 SIUL_GPDI_8B_tag GPDI221; /* offset: 0x08DD size: 8 bit */
3024 SIUL_GPDI_8B_tag GPDI222; /* offset: 0x08DE size: 8 bit */
3025 SIUL_GPDI_8B_tag GPDI223; /* offset: 0x08DF size: 8 bit */
3026 SIUL_GPDI_8B_tag GPDI224; /* offset: 0x08E0 size: 8 bit */
3027 SIUL_GPDI_8B_tag GPDI225; /* offset: 0x08E1 size: 8 bit */
3028 SIUL_GPDI_8B_tag GPDI226; /* offset: 0x08E2 size: 8 bit */
3029 SIUL_GPDI_8B_tag GPDI227; /* offset: 0x08E3 size: 8 bit */
3030 SIUL_GPDI_8B_tag GPDI228; /* offset: 0x08E4 size: 8 bit */
3031 SIUL_GPDI_8B_tag GPDI229; /* offset: 0x08E5 size: 8 bit */
3032 SIUL_GPDI_8B_tag GPDI230; /* offset: 0x08E6 size: 8 bit */
3033 SIUL_GPDI_8B_tag GPDI231; /* offset: 0x08E7 size: 8 bit */
3034 SIUL_GPDI_8B_tag GPDI232; /* offset: 0x08E8 size: 8 bit */
3035 SIUL_GPDI_8B_tag GPDI233; /* offset: 0x08E9 size: 8 bit */
3036 SIUL_GPDI_8B_tag GPDI234; /* offset: 0x08EA size: 8 bit */
3037 SIUL_GPDI_8B_tag GPDI235; /* offset: 0x08EB size: 8 bit */
3038 SIUL_GPDI_8B_tag GPDI236; /* offset: 0x08EC size: 8 bit */
3039 SIUL_GPDI_8B_tag GPDI237; /* offset: 0x08ED size: 8 bit */
3040 SIUL_GPDI_8B_tag GPDI238; /* offset: 0x08EE size: 8 bit */
3041 SIUL_GPDI_8B_tag GPDI239; /* offset: 0x08EF size: 8 bit */
3042 SIUL_GPDI_8B_tag GPDI240; /* offset: 0x08F0 size: 8 bit */
3043 SIUL_GPDI_8B_tag GPDI241; /* offset: 0x08F1 size: 8 bit */
3044 SIUL_GPDI_8B_tag GPDI242; /* offset: 0x08F2 size: 8 bit */
3045 SIUL_GPDI_8B_tag GPDI243; /* offset: 0x08F3 size: 8 bit */
3046 SIUL_GPDI_8B_tag GPDI244; /* offset: 0x08F4 size: 8 bit */
3047 SIUL_GPDI_8B_tag GPDI245; /* offset: 0x08F5 size: 8 bit */
3048 SIUL_GPDI_8B_tag GPDI246; /* offset: 0x08F6 size: 8 bit */
3049 SIUL_GPDI_8B_tag GPDI247; /* offset: 0x08F7 size: 8 bit */
3050 SIUL_GPDI_8B_tag GPDI248; /* offset: 0x08F8 size: 8 bit */
3051 SIUL_GPDI_8B_tag GPDI249; /* offset: 0x08F9 size: 8 bit */
3052 SIUL_GPDI_8B_tag GPDI250; /* offset: 0x08FA size: 8 bit */
3053 SIUL_GPDI_8B_tag GPDI251; /* offset: 0x08FB size: 8 bit */
3054 SIUL_GPDI_8B_tag GPDI252; /* offset: 0x08FC size: 8 bit */
3055 SIUL_GPDI_8B_tag GPDI253; /* offset: 0x08FD size: 8 bit */
3056 SIUL_GPDI_8B_tag GPDI254; /* offset: 0x08FE size: 8 bit */
3057 SIUL_GPDI_8B_tag GPDI255; /* offset: 0x08FF size: 8 bit */
3058 SIUL_GPDI_8B_tag GPDI256; /* offset: 0x0900 size: 8 bit */
3059 SIUL_GPDI_8B_tag GPDI257; /* offset: 0x0901 size: 8 bit */
3060 SIUL_GPDI_8B_tag GPDI258; /* offset: 0x0902 size: 8 bit */
3061 SIUL_GPDI_8B_tag GPDI259; /* offset: 0x0903 size: 8 bit */
3062 SIUL_GPDI_8B_tag GPDI260; /* offset: 0x0904 size: 8 bit */
3063 SIUL_GPDI_8B_tag GPDI261; /* offset: 0x0905 size: 8 bit */
3064 SIUL_GPDI_8B_tag GPDI262; /* offset: 0x0906 size: 8 bit */
3065 SIUL_GPDI_8B_tag GPDI263; /* offset: 0x0907 size: 8 bit */
3066 SIUL_GPDI_8B_tag GPDI264; /* offset: 0x0908 size: 8 bit */
3067 SIUL_GPDI_8B_tag GPDI265; /* offset: 0x0909 size: 8 bit */
3068 SIUL_GPDI_8B_tag GPDI266; /* offset: 0x090A size: 8 bit */
3069 SIUL_GPDI_8B_tag GPDI267; /* offset: 0x090B size: 8 bit */
3070 SIUL_GPDI_8B_tag GPDI268; /* offset: 0x090C size: 8 bit */
3071 SIUL_GPDI_8B_tag GPDI269; /* offset: 0x090D size: 8 bit */
3072 SIUL_GPDI_8B_tag GPDI270; /* offset: 0x090E size: 8 bit */
3073 SIUL_GPDI_8B_tag GPDI271; /* offset: 0x090F size: 8 bit */
3074 SIUL_GPDI_8B_tag GPDI272; /* offset: 0x0910 size: 8 bit */
3075 SIUL_GPDI_8B_tag GPDI273; /* offset: 0x0911 size: 8 bit */
3076 SIUL_GPDI_8B_tag GPDI274; /* offset: 0x0912 size: 8 bit */
3077 SIUL_GPDI_8B_tag GPDI275; /* offset: 0x0913 size: 8 bit */
3078 SIUL_GPDI_8B_tag GPDI276; /* offset: 0x0914 size: 8 bit */
3079 SIUL_GPDI_8B_tag GPDI277; /* offset: 0x0915 size: 8 bit */
3080 SIUL_GPDI_8B_tag GPDI278; /* offset: 0x0916 size: 8 bit */
3081 SIUL_GPDI_8B_tag GPDI279; /* offset: 0x0917 size: 8 bit */
3082 SIUL_GPDI_8B_tag GPDI280; /* offset: 0x0918 size: 8 bit */
3083 SIUL_GPDI_8B_tag GPDI281; /* offset: 0x0919 size: 8 bit */
3084 SIUL_GPDI_8B_tag GPDI282; /* offset: 0x091A size: 8 bit */
3085 SIUL_GPDI_8B_tag GPDI283; /* offset: 0x091B size: 8 bit */
3086 SIUL_GPDI_8B_tag GPDI284; /* offset: 0x091C size: 8 bit */
3087 SIUL_GPDI_8B_tag GPDI285; /* offset: 0x091D size: 8 bit */
3088 SIUL_GPDI_8B_tag GPDI286; /* offset: 0x091E size: 8 bit */
3089 SIUL_GPDI_8B_tag GPDI287; /* offset: 0x091F size: 8 bit */
3090 SIUL_GPDI_8B_tag GPDI288; /* offset: 0x0920 size: 8 bit */
3091 SIUL_GPDI_8B_tag GPDI289; /* offset: 0x0921 size: 8 bit */
3092 SIUL_GPDI_8B_tag GPDI290; /* offset: 0x0922 size: 8 bit */
3093 SIUL_GPDI_8B_tag GPDI291; /* offset: 0x0923 size: 8 bit */
3094 SIUL_GPDI_8B_tag GPDI292; /* offset: 0x0924 size: 8 bit */
3095 SIUL_GPDI_8B_tag GPDI293; /* offset: 0x0925 size: 8 bit */
3096 SIUL_GPDI_8B_tag GPDI294; /* offset: 0x0926 size: 8 bit */
3097 SIUL_GPDI_8B_tag GPDI295; /* offset: 0x0927 size: 8 bit */
3098 SIUL_GPDI_8B_tag GPDI296; /* offset: 0x0928 size: 8 bit */
3099 SIUL_GPDI_8B_tag GPDI297; /* offset: 0x0929 size: 8 bit */
3100 SIUL_GPDI_8B_tag GPDI298; /* offset: 0x092A size: 8 bit */
3101 SIUL_GPDI_8B_tag GPDI299; /* offset: 0x092B size: 8 bit */
3102 SIUL_GPDI_8B_tag GPDI300; /* offset: 0x092C size: 8 bit */
3103 SIUL_GPDI_8B_tag GPDI301; /* offset: 0x092D size: 8 bit */
3104 SIUL_GPDI_8B_tag GPDI302; /* offset: 0x092E size: 8 bit */
3105 SIUL_GPDI_8B_tag GPDI303; /* offset: 0x092F size: 8 bit */
3106 SIUL_GPDI_8B_tag GPDI304; /* offset: 0x0930 size: 8 bit */
3107 SIUL_GPDI_8B_tag GPDI305; /* offset: 0x0931 size: 8 bit */
3108 SIUL_GPDI_8B_tag GPDI306; /* offset: 0x0932 size: 8 bit */
3109 SIUL_GPDI_8B_tag GPDI307; /* offset: 0x0933 size: 8 bit */
3110 SIUL_GPDI_8B_tag GPDI308; /* offset: 0x0934 size: 8 bit */
3111 SIUL_GPDI_8B_tag GPDI309; /* offset: 0x0935 size: 8 bit */
3112 SIUL_GPDI_8B_tag GPDI310; /* offset: 0x0936 size: 8 bit */
3113 SIUL_GPDI_8B_tag GPDI311; /* offset: 0x0937 size: 8 bit */
3114 SIUL_GPDI_8B_tag GPDI312; /* offset: 0x0938 size: 8 bit */
3115 SIUL_GPDI_8B_tag GPDI313; /* offset: 0x0939 size: 8 bit */
3116 SIUL_GPDI_8B_tag GPDI314; /* offset: 0x093A size: 8 bit */
3117 SIUL_GPDI_8B_tag GPDI315; /* offset: 0x093B size: 8 bit */
3118 SIUL_GPDI_8B_tag GPDI316; /* offset: 0x093C size: 8 bit */
3119 SIUL_GPDI_8B_tag GPDI317; /* offset: 0x093D size: 8 bit */
3120 SIUL_GPDI_8B_tag GPDI318; /* offset: 0x093E size: 8 bit */
3121 SIUL_GPDI_8B_tag GPDI319; /* offset: 0x093F size: 8 bit */
3122 SIUL_GPDI_8B_tag GPDI320; /* offset: 0x0940 size: 8 bit */
3123 SIUL_GPDI_8B_tag GPDI321; /* offset: 0x0941 size: 8 bit */
3124 SIUL_GPDI_8B_tag GPDI322; /* offset: 0x0942 size: 8 bit */
3125 SIUL_GPDI_8B_tag GPDI323; /* offset: 0x0943 size: 8 bit */
3126 SIUL_GPDI_8B_tag GPDI324; /* offset: 0x0944 size: 8 bit */
3127 SIUL_GPDI_8B_tag GPDI325; /* offset: 0x0945 size: 8 bit */
3128 SIUL_GPDI_8B_tag GPDI326; /* offset: 0x0946 size: 8 bit */
3129 SIUL_GPDI_8B_tag GPDI327; /* offset: 0x0947 size: 8 bit */
3130 SIUL_GPDI_8B_tag GPDI328; /* offset: 0x0948 size: 8 bit */
3131 SIUL_GPDI_8B_tag GPDI329; /* offset: 0x0949 size: 8 bit */
3132 SIUL_GPDI_8B_tag GPDI330; /* offset: 0x094A size: 8 bit */
3133 SIUL_GPDI_8B_tag GPDI331; /* offset: 0x094B size: 8 bit */
3134 SIUL_GPDI_8B_tag GPDI332; /* offset: 0x094C size: 8 bit */
3135 SIUL_GPDI_8B_tag GPDI333; /* offset: 0x094D size: 8 bit */
3136 SIUL_GPDI_8B_tag GPDI334; /* offset: 0x094E size: 8 bit */
3137 SIUL_GPDI_8B_tag GPDI335; /* offset: 0x094F size: 8 bit */
3138 SIUL_GPDI_8B_tag GPDI336; /* offset: 0x0950 size: 8 bit */
3139 SIUL_GPDI_8B_tag GPDI337; /* offset: 0x0951 size: 8 bit */
3140 SIUL_GPDI_8B_tag GPDI338; /* offset: 0x0952 size: 8 bit */
3141 SIUL_GPDI_8B_tag GPDI339; /* offset: 0x0953 size: 8 bit */
3142 SIUL_GPDI_8B_tag GPDI340; /* offset: 0x0954 size: 8 bit */
3143 SIUL_GPDI_8B_tag GPDI341; /* offset: 0x0955 size: 8 bit */
3144 SIUL_GPDI_8B_tag GPDI342; /* offset: 0x0956 size: 8 bit */
3145 SIUL_GPDI_8B_tag GPDI343; /* offset: 0x0957 size: 8 bit */
3146 SIUL_GPDI_8B_tag GPDI344; /* offset: 0x0958 size: 8 bit */
3147 SIUL_GPDI_8B_tag GPDI345; /* offset: 0x0959 size: 8 bit */
3148 SIUL_GPDI_8B_tag GPDI346; /* offset: 0x095A size: 8 bit */
3149 SIUL_GPDI_8B_tag GPDI347; /* offset: 0x095B size: 8 bit */
3150 SIUL_GPDI_8B_tag GPDI348; /* offset: 0x095C size: 8 bit */
3151 SIUL_GPDI_8B_tag GPDI349; /* offset: 0x095D size: 8 bit */
3152 SIUL_GPDI_8B_tag GPDI350; /* offset: 0x095E size: 8 bit */
3153 SIUL_GPDI_8B_tag GPDI351; /* offset: 0x095F size: 8 bit */
3154 SIUL_GPDI_8B_tag GPDI352; /* offset: 0x0960 size: 8 bit */
3155 SIUL_GPDI_8B_tag GPDI353; /* offset: 0x0961 size: 8 bit */
3156 SIUL_GPDI_8B_tag GPDI354; /* offset: 0x0962 size: 8 bit */
3157 SIUL_GPDI_8B_tag GPDI355; /* offset: 0x0963 size: 8 bit */
3158 SIUL_GPDI_8B_tag GPDI356; /* offset: 0x0964 size: 8 bit */
3159 SIUL_GPDI_8B_tag GPDI357; /* offset: 0x0965 size: 8 bit */
3160 SIUL_GPDI_8B_tag GPDI358; /* offset: 0x0966 size: 8 bit */
3161 SIUL_GPDI_8B_tag GPDI359; /* offset: 0x0967 size: 8 bit */
3162 SIUL_GPDI_8B_tag GPDI360; /* offset: 0x0968 size: 8 bit */
3163 SIUL_GPDI_8B_tag GPDI361; /* offset: 0x0969 size: 8 bit */
3164 SIUL_GPDI_8B_tag GPDI362; /* offset: 0x096A size: 8 bit */
3165 SIUL_GPDI_8B_tag GPDI363; /* offset: 0x096B size: 8 bit */
3166 SIUL_GPDI_8B_tag GPDI364; /* offset: 0x096C size: 8 bit */
3167 SIUL_GPDI_8B_tag GPDI365; /* offset: 0x096D size: 8 bit */
3168 SIUL_GPDI_8B_tag GPDI366; /* offset: 0x096E size: 8 bit */
3169 SIUL_GPDI_8B_tag GPDI367; /* offset: 0x096F size: 8 bit */
3170 SIUL_GPDI_8B_tag GPDI368; /* offset: 0x0970 size: 8 bit */
3171 SIUL_GPDI_8B_tag GPDI369; /* offset: 0x0971 size: 8 bit */
3172 SIUL_GPDI_8B_tag GPDI370; /* offset: 0x0972 size: 8 bit */
3173 SIUL_GPDI_8B_tag GPDI371; /* offset: 0x0973 size: 8 bit */
3174 SIUL_GPDI_8B_tag GPDI372; /* offset: 0x0974 size: 8 bit */
3175 SIUL_GPDI_8B_tag GPDI373; /* offset: 0x0975 size: 8 bit */
3176 SIUL_GPDI_8B_tag GPDI374; /* offset: 0x0976 size: 8 bit */
3177 SIUL_GPDI_8B_tag GPDI375; /* offset: 0x0977 size: 8 bit */
3178 SIUL_GPDI_8B_tag GPDI376; /* offset: 0x0978 size: 8 bit */
3179 SIUL_GPDI_8B_tag GPDI377; /* offset: 0x0979 size: 8 bit */
3180 SIUL_GPDI_8B_tag GPDI378; /* offset: 0x097A size: 8 bit */
3181 SIUL_GPDI_8B_tag GPDI379; /* offset: 0x097B size: 8 bit */
3182 SIUL_GPDI_8B_tag GPDI380; /* offset: 0x097C size: 8 bit */
3183 SIUL_GPDI_8B_tag GPDI381; /* offset: 0x097D size: 8 bit */
3184 SIUL_GPDI_8B_tag GPDI382; /* offset: 0x097E size: 8 bit */
3185 SIUL_GPDI_8B_tag GPDI383; /* offset: 0x097F size: 8 bit */
3186 SIUL_GPDI_8B_tag GPDI384; /* offset: 0x0980 size: 8 bit */
3187 SIUL_GPDI_8B_tag GPDI385; /* offset: 0x0981 size: 8 bit */
3188 SIUL_GPDI_8B_tag GPDI386; /* offset: 0x0982 size: 8 bit */
3189 SIUL_GPDI_8B_tag GPDI387; /* offset: 0x0983 size: 8 bit */
3190 SIUL_GPDI_8B_tag GPDI388; /* offset: 0x0984 size: 8 bit */
3191 SIUL_GPDI_8B_tag GPDI389; /* offset: 0x0985 size: 8 bit */
3192 SIUL_GPDI_8B_tag GPDI390; /* offset: 0x0986 size: 8 bit */
3193 SIUL_GPDI_8B_tag GPDI391; /* offset: 0x0987 size: 8 bit */
3194 SIUL_GPDI_8B_tag GPDI392; /* offset: 0x0988 size: 8 bit */
3195 SIUL_GPDI_8B_tag GPDI393; /* offset: 0x0989 size: 8 bit */
3196 SIUL_GPDI_8B_tag GPDI394; /* offset: 0x098A size: 8 bit */
3197 SIUL_GPDI_8B_tag GPDI395; /* offset: 0x098B size: 8 bit */
3198 SIUL_GPDI_8B_tag GPDI396; /* offset: 0x098C size: 8 bit */
3199 SIUL_GPDI_8B_tag GPDI397; /* offset: 0x098D size: 8 bit */
3200 SIUL_GPDI_8B_tag GPDI398; /* offset: 0x098E size: 8 bit */
3201 SIUL_GPDI_8B_tag GPDI399; /* offset: 0x098F size: 8 bit */
3202 SIUL_GPDI_8B_tag GPDI400; /* offset: 0x0990 size: 8 bit */
3203 SIUL_GPDI_8B_tag GPDI401; /* offset: 0x0991 size: 8 bit */
3204 SIUL_GPDI_8B_tag GPDI402; /* offset: 0x0992 size: 8 bit */
3205 SIUL_GPDI_8B_tag GPDI403; /* offset: 0x0993 size: 8 bit */
3206 SIUL_GPDI_8B_tag GPDI404; /* offset: 0x0994 size: 8 bit */
3207 SIUL_GPDI_8B_tag GPDI405; /* offset: 0x0995 size: 8 bit */
3208 SIUL_GPDI_8B_tag GPDI406; /* offset: 0x0996 size: 8 bit */
3209 SIUL_GPDI_8B_tag GPDI407; /* offset: 0x0997 size: 8 bit */
3210 SIUL_GPDI_8B_tag GPDI408; /* offset: 0x0998 size: 8 bit */
3211 SIUL_GPDI_8B_tag GPDI409; /* offset: 0x0999 size: 8 bit */
3212 SIUL_GPDI_8B_tag GPDI410; /* offset: 0x099A size: 8 bit */
3213 SIUL_GPDI_8B_tag GPDI411; /* offset: 0x099B size: 8 bit */
3214 SIUL_GPDI_8B_tag GPDI412; /* offset: 0x099C size: 8 bit */
3215 SIUL_GPDI_8B_tag GPDI413; /* offset: 0x099D size: 8 bit */
3216 SIUL_GPDI_8B_tag GPDI414; /* offset: 0x099E size: 8 bit */
3217 SIUL_GPDI_8B_tag GPDI415; /* offset: 0x099F size: 8 bit */
3218 SIUL_GPDI_8B_tag GPDI416; /* offset: 0x09A0 size: 8 bit */
3219 SIUL_GPDI_8B_tag GPDI417; /* offset: 0x09A1 size: 8 bit */
3220 SIUL_GPDI_8B_tag GPDI418; /* offset: 0x09A2 size: 8 bit */
3221 SIUL_GPDI_8B_tag GPDI419; /* offset: 0x09A3 size: 8 bit */
3222 SIUL_GPDI_8B_tag GPDI420; /* offset: 0x09A4 size: 8 bit */
3223 SIUL_GPDI_8B_tag GPDI421; /* offset: 0x09A5 size: 8 bit */
3224 SIUL_GPDI_8B_tag GPDI422; /* offset: 0x09A6 size: 8 bit */
3225 SIUL_GPDI_8B_tag GPDI423; /* offset: 0x09A7 size: 8 bit */
3226 SIUL_GPDI_8B_tag GPDI424; /* offset: 0x09A8 size: 8 bit */
3227 SIUL_GPDI_8B_tag GPDI425; /* offset: 0x09A9 size: 8 bit */
3228 SIUL_GPDI_8B_tag GPDI426; /* offset: 0x09AA size: 8 bit */
3229 SIUL_GPDI_8B_tag GPDI427; /* offset: 0x09AB size: 8 bit */
3230 SIUL_GPDI_8B_tag GPDI428; /* offset: 0x09AC size: 8 bit */
3231 SIUL_GPDI_8B_tag GPDI429; /* offset: 0x09AD size: 8 bit */
3232 SIUL_GPDI_8B_tag GPDI430; /* offset: 0x09AE size: 8 bit */
3233 SIUL_GPDI_8B_tag GPDI431; /* offset: 0x09AF size: 8 bit */
3234 SIUL_GPDI_8B_tag GPDI432; /* offset: 0x09B0 size: 8 bit */
3235 SIUL_GPDI_8B_tag GPDI433; /* offset: 0x09B1 size: 8 bit */
3236 SIUL_GPDI_8B_tag GPDI434; /* offset: 0x09B2 size: 8 bit */
3237 SIUL_GPDI_8B_tag GPDI435; /* offset: 0x09B3 size: 8 bit */
3238 SIUL_GPDI_8B_tag GPDI436; /* offset: 0x09B4 size: 8 bit */
3239 SIUL_GPDI_8B_tag GPDI437; /* offset: 0x09B5 size: 8 bit */
3240 SIUL_GPDI_8B_tag GPDI438; /* offset: 0x09B6 size: 8 bit */
3241 SIUL_GPDI_8B_tag GPDI439; /* offset: 0x09B7 size: 8 bit */
3242 SIUL_GPDI_8B_tag GPDI440; /* offset: 0x09B8 size: 8 bit */
3243 SIUL_GPDI_8B_tag GPDI441; /* offset: 0x09B9 size: 8 bit */
3244 SIUL_GPDI_8B_tag GPDI442; /* offset: 0x09BA size: 8 bit */
3245 SIUL_GPDI_8B_tag GPDI443; /* offset: 0x09BB size: 8 bit */
3246 SIUL_GPDI_8B_tag GPDI444; /* offset: 0x09BC size: 8 bit */
3247 SIUL_GPDI_8B_tag GPDI445; /* offset: 0x09BD size: 8 bit */
3248 SIUL_GPDI_8B_tag GPDI446; /* offset: 0x09BE size: 8 bit */
3249 SIUL_GPDI_8B_tag GPDI447; /* offset: 0x09BF size: 8 bit */
3250 SIUL_GPDI_8B_tag GPDI448; /* offset: 0x09C0 size: 8 bit */
3251 SIUL_GPDI_8B_tag GPDI449; /* offset: 0x09C1 size: 8 bit */
3252 SIUL_GPDI_8B_tag GPDI450; /* offset: 0x09C2 size: 8 bit */
3253 SIUL_GPDI_8B_tag GPDI451; /* offset: 0x09C3 size: 8 bit */
3254 SIUL_GPDI_8B_tag GPDI452; /* offset: 0x09C4 size: 8 bit */
3255 SIUL_GPDI_8B_tag GPDI453; /* offset: 0x09C5 size: 8 bit */
3256 SIUL_GPDI_8B_tag GPDI454; /* offset: 0x09C6 size: 8 bit */
3257 SIUL_GPDI_8B_tag GPDI455; /* offset: 0x09C7 size: 8 bit */
3258 SIUL_GPDI_8B_tag GPDI456; /* offset: 0x09C8 size: 8 bit */
3259 SIUL_GPDI_8B_tag GPDI457; /* offset: 0x09C9 size: 8 bit */
3260 SIUL_GPDI_8B_tag GPDI458; /* offset: 0x09CA size: 8 bit */
3261 SIUL_GPDI_8B_tag GPDI459; /* offset: 0x09CB size: 8 bit */
3262 SIUL_GPDI_8B_tag GPDI460; /* offset: 0x09CC size: 8 bit */
3263 SIUL_GPDI_8B_tag GPDI461; /* offset: 0x09CD size: 8 bit */
3264 SIUL_GPDI_8B_tag GPDI462; /* offset: 0x09CE size: 8 bit */
3265 SIUL_GPDI_8B_tag GPDI463; /* offset: 0x09CF size: 8 bit */
3266 SIUL_GPDI_8B_tag GPDI464; /* offset: 0x09D0 size: 8 bit */
3267 SIUL_GPDI_8B_tag GPDI465; /* offset: 0x09D1 size: 8 bit */
3268 SIUL_GPDI_8B_tag GPDI466; /* offset: 0x09D2 size: 8 bit */
3269 SIUL_GPDI_8B_tag GPDI467; /* offset: 0x09D3 size: 8 bit */
3270 SIUL_GPDI_8B_tag GPDI468; /* offset: 0x09D4 size: 8 bit */
3271 SIUL_GPDI_8B_tag GPDI469; /* offset: 0x09D5 size: 8 bit */
3272 SIUL_GPDI_8B_tag GPDI470; /* offset: 0x09D6 size: 8 bit */
3273 SIUL_GPDI_8B_tag GPDI471; /* offset: 0x09D7 size: 8 bit */
3274 SIUL_GPDI_8B_tag GPDI472; /* offset: 0x09D8 size: 8 bit */
3275 SIUL_GPDI_8B_tag GPDI473; /* offset: 0x09D9 size: 8 bit */
3276 SIUL_GPDI_8B_tag GPDI474; /* offset: 0x09DA size: 8 bit */
3277 SIUL_GPDI_8B_tag GPDI475; /* offset: 0x09DB size: 8 bit */
3278 SIUL_GPDI_8B_tag GPDI476; /* offset: 0x09DC size: 8 bit */
3279 SIUL_GPDI_8B_tag GPDI477; /* offset: 0x09DD size: 8 bit */
3280 SIUL_GPDI_8B_tag GPDI478; /* offset: 0x09DE size: 8 bit */
3281 SIUL_GPDI_8B_tag GPDI479; /* offset: 0x09DF size: 8 bit */
3282 SIUL_GPDI_8B_tag GPDI480; /* offset: 0x09E0 size: 8 bit */
3283 SIUL_GPDI_8B_tag GPDI481; /* offset: 0x09E1 size: 8 bit */
3284 SIUL_GPDI_8B_tag GPDI482; /* offset: 0x09E2 size: 8 bit */
3285 SIUL_GPDI_8B_tag GPDI483; /* offset: 0x09E3 size: 8 bit */
3286 SIUL_GPDI_8B_tag GPDI484; /* offset: 0x09E4 size: 8 bit */
3287 SIUL_GPDI_8B_tag GPDI485; /* offset: 0x09E5 size: 8 bit */
3288 SIUL_GPDI_8B_tag GPDI486; /* offset: 0x09E6 size: 8 bit */
3289 SIUL_GPDI_8B_tag GPDI487; /* offset: 0x09E7 size: 8 bit */
3290 SIUL_GPDI_8B_tag GPDI488; /* offset: 0x09E8 size: 8 bit */
3291 SIUL_GPDI_8B_tag GPDI489; /* offset: 0x09E9 size: 8 bit */
3292 SIUL_GPDI_8B_tag GPDI490; /* offset: 0x09EA size: 8 bit */
3293 SIUL_GPDI_8B_tag GPDI491; /* offset: 0x09EB size: 8 bit */
3294 SIUL_GPDI_8B_tag GPDI492; /* offset: 0x09EC size: 8 bit */
3295 SIUL_GPDI_8B_tag GPDI493; /* offset: 0x09ED size: 8 bit */
3296 SIUL_GPDI_8B_tag GPDI494; /* offset: 0x09EE size: 8 bit */
3297 SIUL_GPDI_8B_tag GPDI495; /* offset: 0x09EF size: 8 bit */
3298 SIUL_GPDI_8B_tag GPDI496; /* offset: 0x09F0 size: 8 bit */
3299 SIUL_GPDI_8B_tag GPDI497; /* offset: 0x09F1 size: 8 bit */
3300 SIUL_GPDI_8B_tag GPDI498; /* offset: 0x09F2 size: 8 bit */
3301 SIUL_GPDI_8B_tag GPDI499; /* offset: 0x09F3 size: 8 bit */
3302 SIUL_GPDI_8B_tag GPDI500; /* offset: 0x09F4 size: 8 bit */
3303 SIUL_GPDI_8B_tag GPDI501; /* offset: 0x09F5 size: 8 bit */
3304 SIUL_GPDI_8B_tag GPDI502; /* offset: 0x09F6 size: 8 bit */
3305 SIUL_GPDI_8B_tag GPDI503; /* offset: 0x09F7 size: 8 bit */
3306 SIUL_GPDI_8B_tag GPDI504; /* offset: 0x09F8 size: 8 bit */
3307 SIUL_GPDI_8B_tag GPDI505; /* offset: 0x09F9 size: 8 bit */
3308 SIUL_GPDI_8B_tag GPDI506; /* offset: 0x09FA size: 8 bit */
3309 SIUL_GPDI_8B_tag GPDI507; /* offset: 0x09FB size: 8 bit */
3310 SIUL_GPDI_8B_tag GPDI508; /* offset: 0x09FC size: 8 bit */
3311 SIUL_GPDI_8B_tag GPDI509; /* offset: 0x09FD size: 8 bit */
3312 SIUL_GPDI_8B_tag GPDI510; /* offset: 0x09FE size: 8 bit */
3313 SIUL_GPDI_8B_tag GPDI511; /* offset: 0x09FF size: 8 bit */
3314 };
3315
3316 };
3317 int8_t SIUL_reserved_0A00_C[512];
3318 union {
3319 /* PGPDO - Parallel GPIO Pad Data Out Register */
3320 SIUL_PGPDO_16B_tag PGPDO[32]; /* offset: 0x0C00 (0x0002 x 32) */
3321
3322 struct {
3323 /* PGPDO - Parallel GPIO Pad Data Out Register */
3324 SIUL_PGPDO_16B_tag PGPDO0; /* offset: 0x0C00 size: 16 bit */
3325 SIUL_PGPDO_16B_tag PGPDO1; /* offset: 0x0C02 size: 16 bit */
3326 SIUL_PGPDO_16B_tag PGPDO2; /* offset: 0x0C04 size: 16 bit */
3327 SIUL_PGPDO_16B_tag PGPDO3; /* offset: 0x0C06 size: 16 bit */
3328 SIUL_PGPDO_16B_tag PGPDO4; /* offset: 0x0C08 size: 16 bit */
3329 SIUL_PGPDO_16B_tag PGPDO5; /* offset: 0x0C0A size: 16 bit */
3330 SIUL_PGPDO_16B_tag PGPDO6; /* offset: 0x0C0C size: 16 bit */
3331 SIUL_PGPDO_16B_tag PGPDO7; /* offset: 0x0C0E size: 16 bit */
3332 SIUL_PGPDO_16B_tag PGPDO8; /* offset: 0x0C10 size: 16 bit */
3333 SIUL_PGPDO_16B_tag PGPDO9; /* offset: 0x0C12 size: 16 bit */
3334 SIUL_PGPDO_16B_tag PGPDO10; /* offset: 0x0C14 size: 16 bit */
3335 SIUL_PGPDO_16B_tag PGPDO11; /* offset: 0x0C16 size: 16 bit */
3336 SIUL_PGPDO_16B_tag PGPDO12; /* offset: 0x0C18 size: 16 bit */
3337 SIUL_PGPDO_16B_tag PGPDO13; /* offset: 0x0C1A size: 16 bit */
3338 SIUL_PGPDO_16B_tag PGPDO14; /* offset: 0x0C1C size: 16 bit */
3339 SIUL_PGPDO_16B_tag PGPDO15; /* offset: 0x0C1E size: 16 bit */
3340 SIUL_PGPDO_16B_tag PGPDO16; /* offset: 0x0C20 size: 16 bit */
3341 SIUL_PGPDO_16B_tag PGPDO17; /* offset: 0x0C22 size: 16 bit */
3342 SIUL_PGPDO_16B_tag PGPDO18; /* offset: 0x0C24 size: 16 bit */
3343 SIUL_PGPDO_16B_tag PGPDO19; /* offset: 0x0C26 size: 16 bit */
3344 SIUL_PGPDO_16B_tag PGPDO20; /* offset: 0x0C28 size: 16 bit */
3345 SIUL_PGPDO_16B_tag PGPDO21; /* offset: 0x0C2A size: 16 bit */
3346 SIUL_PGPDO_16B_tag PGPDO22; /* offset: 0x0C2C size: 16 bit */
3347 SIUL_PGPDO_16B_tag PGPDO23; /* offset: 0x0C2E size: 16 bit */
3348 SIUL_PGPDO_16B_tag PGPDO24; /* offset: 0x0C30 size: 16 bit */
3349 SIUL_PGPDO_16B_tag PGPDO25; /* offset: 0x0C32 size: 16 bit */
3350 SIUL_PGPDO_16B_tag PGPDO26; /* offset: 0x0C34 size: 16 bit */
3351 SIUL_PGPDO_16B_tag PGPDO27; /* offset: 0x0C36 size: 16 bit */
3352 SIUL_PGPDO_16B_tag PGPDO28; /* offset: 0x0C38 size: 16 bit */
3353 SIUL_PGPDO_16B_tag PGPDO29; /* offset: 0x0C3A size: 16 bit */
3354 SIUL_PGPDO_16B_tag PGPDO30; /* offset: 0x0C3C size: 16 bit */
3355 SIUL_PGPDO_16B_tag PGPDO31; /* offset: 0x0C3E size: 16 bit */
3356 };
3357
3358 };
3359 union {
3360 /* PGPDI - Parallel GPIO Pad Data In Register */
3361 SIUL_PGPDI_16B_tag PGPDI[32]; /* offset: 0x0C40 (0x0002 x 32) */
3362
3363 struct {
3364 /* PGPDI - Parallel GPIO Pad Data In Register */
3365 SIUL_PGPDI_16B_tag PGPDI0; /* offset: 0x0C40 size: 16 bit */
3366 SIUL_PGPDI_16B_tag PGPDI1; /* offset: 0x0C42 size: 16 bit */
3367 SIUL_PGPDI_16B_tag PGPDI2; /* offset: 0x0C44 size: 16 bit */
3368 SIUL_PGPDI_16B_tag PGPDI3; /* offset: 0x0C46 size: 16 bit */
3369 SIUL_PGPDI_16B_tag PGPDI4; /* offset: 0x0C48 size: 16 bit */
3370 SIUL_PGPDI_16B_tag PGPDI5; /* offset: 0x0C4A size: 16 bit */
3371 SIUL_PGPDI_16B_tag PGPDI6; /* offset: 0x0C4C size: 16 bit */
3372 SIUL_PGPDI_16B_tag PGPDI7; /* offset: 0x0C4E size: 16 bit */
3373 SIUL_PGPDI_16B_tag PGPDI8; /* offset: 0x0C50 size: 16 bit */
3374 SIUL_PGPDI_16B_tag PGPDI9; /* offset: 0x0C52 size: 16 bit */
3375 SIUL_PGPDI_16B_tag PGPDI10; /* offset: 0x0C54 size: 16 bit */
3376 SIUL_PGPDI_16B_tag PGPDI11; /* offset: 0x0C56 size: 16 bit */
3377 SIUL_PGPDI_16B_tag PGPDI12; /* offset: 0x0C58 size: 16 bit */
3378 SIUL_PGPDI_16B_tag PGPDI13; /* offset: 0x0C5A size: 16 bit */
3379 SIUL_PGPDI_16B_tag PGPDI14; /* offset: 0x0C5C size: 16 bit */
3380 SIUL_PGPDI_16B_tag PGPDI15; /* offset: 0x0C5E size: 16 bit */
3381 SIUL_PGPDI_16B_tag PGPDI16; /* offset: 0x0C60 size: 16 bit */
3382 SIUL_PGPDI_16B_tag PGPDI17; /* offset: 0x0C62 size: 16 bit */
3383 SIUL_PGPDI_16B_tag PGPDI18; /* offset: 0x0C64 size: 16 bit */
3384 SIUL_PGPDI_16B_tag PGPDI19; /* offset: 0x0C66 size: 16 bit */
3385 SIUL_PGPDI_16B_tag PGPDI20; /* offset: 0x0C68 size: 16 bit */
3386 SIUL_PGPDI_16B_tag PGPDI21; /* offset: 0x0C6A size: 16 bit */
3387 SIUL_PGPDI_16B_tag PGPDI22; /* offset: 0x0C6C size: 16 bit */
3388 SIUL_PGPDI_16B_tag PGPDI23; /* offset: 0x0C6E size: 16 bit */
3389 SIUL_PGPDI_16B_tag PGPDI24; /* offset: 0x0C70 size: 16 bit */
3390 SIUL_PGPDI_16B_tag PGPDI25; /* offset: 0x0C72 size: 16 bit */
3391 SIUL_PGPDI_16B_tag PGPDI26; /* offset: 0x0C74 size: 16 bit */
3392 SIUL_PGPDI_16B_tag PGPDI27; /* offset: 0x0C76 size: 16 bit */
3393 SIUL_PGPDI_16B_tag PGPDI28; /* offset: 0x0C78 size: 16 bit */
3394 SIUL_PGPDI_16B_tag PGPDI29; /* offset: 0x0C7A size: 16 bit */
3395 SIUL_PGPDI_16B_tag PGPDI30; /* offset: 0x0C7C size: 16 bit */
3396 SIUL_PGPDI_16B_tag PGPDI31; /* offset: 0x0C7E size: 16 bit */
3397 };
3398
3399 };
3400 union {
3401 /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
3402 SIUL_MPGPDO_32B_tag MPGPDO[32]; /* offset: 0x0C80 (0x0004 x 32) */
3403
3404 struct {
3405 /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
3406 SIUL_MPGPDO_32B_tag MPGPDO0; /* offset: 0x0C80 size: 32 bit */
3407 SIUL_MPGPDO_32B_tag MPGPDO1; /* offset: 0x0C84 size: 32 bit */
3408 SIUL_MPGPDO_32B_tag MPGPDO2; /* offset: 0x0C88 size: 32 bit */
3409 SIUL_MPGPDO_32B_tag MPGPDO3; /* offset: 0x0C8C size: 32 bit */
3410 SIUL_MPGPDO_32B_tag MPGPDO4; /* offset: 0x0C90 size: 32 bit */
3411 SIUL_MPGPDO_32B_tag MPGPDO5; /* offset: 0x0C94 size: 32 bit */
3412 SIUL_MPGPDO_32B_tag MPGPDO6; /* offset: 0x0C98 size: 32 bit */
3413 SIUL_MPGPDO_32B_tag MPGPDO7; /* offset: 0x0C9C size: 32 bit */
3414 SIUL_MPGPDO_32B_tag MPGPDO8; /* offset: 0x0CA0 size: 32 bit */
3415 SIUL_MPGPDO_32B_tag MPGPDO9; /* offset: 0x0CA4 size: 32 bit */
3416 SIUL_MPGPDO_32B_tag MPGPDO10; /* offset: 0x0CA8 size: 32 bit */
3417 SIUL_MPGPDO_32B_tag MPGPDO11; /* offset: 0x0CAC size: 32 bit */
3418 SIUL_MPGPDO_32B_tag MPGPDO12; /* offset: 0x0CB0 size: 32 bit */
3419 SIUL_MPGPDO_32B_tag MPGPDO13; /* offset: 0x0CB4 size: 32 bit */
3420 SIUL_MPGPDO_32B_tag MPGPDO14; /* offset: 0x0CB8 size: 32 bit */
3421 SIUL_MPGPDO_32B_tag MPGPDO15; /* offset: 0x0CBC size: 32 bit */
3422 SIUL_MPGPDO_32B_tag MPGPDO16; /* offset: 0x0CC0 size: 32 bit */
3423 SIUL_MPGPDO_32B_tag MPGPDO17; /* offset: 0x0CC4 size: 32 bit */
3424 SIUL_MPGPDO_32B_tag MPGPDO18; /* offset: 0x0CC8 size: 32 bit */
3425 SIUL_MPGPDO_32B_tag MPGPDO19; /* offset: 0x0CCC size: 32 bit */
3426 SIUL_MPGPDO_32B_tag MPGPDO20; /* offset: 0x0CD0 size: 32 bit */
3427 SIUL_MPGPDO_32B_tag MPGPDO21; /* offset: 0x0CD4 size: 32 bit */
3428 SIUL_MPGPDO_32B_tag MPGPDO22; /* offset: 0x0CD8 size: 32 bit */
3429 SIUL_MPGPDO_32B_tag MPGPDO23; /* offset: 0x0CDC size: 32 bit */
3430 SIUL_MPGPDO_32B_tag MPGPDO24; /* offset: 0x0CE0 size: 32 bit */
3431 SIUL_MPGPDO_32B_tag MPGPDO25; /* offset: 0x0CE4 size: 32 bit */
3432 SIUL_MPGPDO_32B_tag MPGPDO26; /* offset: 0x0CE8 size: 32 bit */
3433 SIUL_MPGPDO_32B_tag MPGPDO27; /* offset: 0x0CEC size: 32 bit */
3434 SIUL_MPGPDO_32B_tag MPGPDO28; /* offset: 0x0CF0 size: 32 bit */
3435 SIUL_MPGPDO_32B_tag MPGPDO29; /* offset: 0x0CF4 size: 32 bit */
3436 SIUL_MPGPDO_32B_tag MPGPDO30; /* offset: 0x0CF8 size: 32 bit */
3437 SIUL_MPGPDO_32B_tag MPGPDO31; /* offset: 0x0CFC size: 32 bit */
3438 };
3439
3440 };
3441 int8_t SIUL_reserved_0D00_C[768];
3442 union {
3443 /* IFMC - Interrupt Filter Maximum Counter Register */
3444 SIUL_IFMC_32B_tag IFMC[32]; /* offset: 0x1000 (0x0004 x 32) */
3445
3446 struct {
3447 /* IFMC - Interrupt Filter Maximum Counter Register */
3448 SIUL_IFMC_32B_tag IFMC0; /* offset: 0x1000 size: 32 bit */
3449 SIUL_IFMC_32B_tag IFMC1; /* offset: 0x1004 size: 32 bit */
3450 SIUL_IFMC_32B_tag IFMC2; /* offset: 0x1008 size: 32 bit */
3451 SIUL_IFMC_32B_tag IFMC3; /* offset: 0x100C size: 32 bit */
3452 SIUL_IFMC_32B_tag IFMC4; /* offset: 0x1010 size: 32 bit */
3453 SIUL_IFMC_32B_tag IFMC5; /* offset: 0x1014 size: 32 bit */
3454 SIUL_IFMC_32B_tag IFMC6; /* offset: 0x1018 size: 32 bit */
3455 SIUL_IFMC_32B_tag IFMC7; /* offset: 0x101C size: 32 bit */
3456 SIUL_IFMC_32B_tag IFMC8; /* offset: 0x1020 size: 32 bit */
3457 SIUL_IFMC_32B_tag IFMC9; /* offset: 0x1024 size: 32 bit */
3458 SIUL_IFMC_32B_tag IFMC10; /* offset: 0x1028 size: 32 bit */
3459 SIUL_IFMC_32B_tag IFMC11; /* offset: 0x102C size: 32 bit */
3460 SIUL_IFMC_32B_tag IFMC12; /* offset: 0x1030 size: 32 bit */
3461 SIUL_IFMC_32B_tag IFMC13; /* offset: 0x1034 size: 32 bit */
3462 SIUL_IFMC_32B_tag IFMC14; /* offset: 0x1038 size: 32 bit */
3463 SIUL_IFMC_32B_tag IFMC15; /* offset: 0x103C size: 32 bit */
3464 SIUL_IFMC_32B_tag IFMC16; /* offset: 0x1040 size: 32 bit */
3465 SIUL_IFMC_32B_tag IFMC17; /* offset: 0x1044 size: 32 bit */
3466 SIUL_IFMC_32B_tag IFMC18; /* offset: 0x1048 size: 32 bit */
3467 SIUL_IFMC_32B_tag IFMC19; /* offset: 0x104C size: 32 bit */
3468 SIUL_IFMC_32B_tag IFMC20; /* offset: 0x1050 size: 32 bit */
3469 SIUL_IFMC_32B_tag IFMC21; /* offset: 0x1054 size: 32 bit */
3470 SIUL_IFMC_32B_tag IFMC22; /* offset: 0x1058 size: 32 bit */
3471 SIUL_IFMC_32B_tag IFMC23; /* offset: 0x105C size: 32 bit */
3472 SIUL_IFMC_32B_tag IFMC24; /* offset: 0x1060 size: 32 bit */
3473 SIUL_IFMC_32B_tag IFMC25; /* offset: 0x1064 size: 32 bit */
3474 SIUL_IFMC_32B_tag IFMC26; /* offset: 0x1068 size: 32 bit */
3475 SIUL_IFMC_32B_tag IFMC27; /* offset: 0x106C size: 32 bit */
3476 SIUL_IFMC_32B_tag IFMC28; /* offset: 0x1070 size: 32 bit */
3477 SIUL_IFMC_32B_tag IFMC29; /* offset: 0x1074 size: 32 bit */
3478 SIUL_IFMC_32B_tag IFMC30; /* offset: 0x1078 size: 32 bit */
3479 SIUL_IFMC_32B_tag IFMC31; /* offset: 0x107C size: 32 bit */
3480 };
3481
3482 };
3483 /* IFCPR - Inerrupt Filter Clock Prescaler Register */
3484 SIUL_IFCPR_32B_tag IFCPR; /* offset: 0x1080 size: 32 bit */
3485 } SIU_tag;
3486
3487
3488#define SIUL (*(volatile SIU_tag *) 0xC3F90000UL)
3489
3490
3491
3492/****************************************************************/
3493/* */
3494/* Module: WKPU */
3495/* */
3496/****************************************************************/
3497
3498 typedef union { /* WKPU_NSR - NMI Status Flag Register */
3499 uint32_t R;
3500 struct {
3501 uint32_t NIF0:1; /* NMI Status Flag 0 */
3502 uint32_t NOVF0:1; /* NMI Overrun Status Flag 0 */
3503 uint32_t:6;
3504 uint32_t NIF1:1; /* NMI Status Flag 1 */
3505 uint32_t NOVF1:1; /* NMI Overrun Status Flag 1 */
3506 uint32_t:6;
3507 uint32_t NIF2:1; /* NMI Status Flag 2 */
3508 uint32_t NOVF2:1; /* NMI Overrun Status Flag 2 */
3509 uint32_t:6;
3510 uint32_t NIF3:1; /* NMI Status Flag 3 */
3511 uint32_t NOVF3:1; /* NMI Overrun Status Flag 3 */
3512 uint32_t:6;
3513 } B;
3514 } WKPU_NSR_32B_tag;
3515
3516 typedef union { /* WKPU_NCR - NMI Configuration Register */
3517 uint32_t R;
3518 struct {
3519 uint32_t NLOCK0:1; /* NMI Configuration Lock Register 0 */
3520 uint32_t NDSS0:2; /* NMI Desination Source Select 0 */
3521 uint32_t NWRE0:1; /* NMI Wakeup Request Enable 0 */
3522 uint32_t:1;
3523 uint32_t NREE0:1; /* NMI Rising Edge Events Enable 0 */
3524 uint32_t NFEE0:1; /* NMI Falling Edge Events Enable 0 */
3525 uint32_t NFE0:1; /* NMI Filter Enable 0 */
3526 uint32_t NLOCK1:1; /* NMI Configuration Lock Register 1 */
3527 uint32_t NDSS1:2; /* NMI Desination Source Select 1 */
3528 uint32_t NWRE1:1; /* NMI Wakeup Request Enable 1 */
3529 uint32_t:1;
3530 uint32_t NREE1:1; /* NMI Rising Edge Events Enable 1 */
3531 uint32_t NFEE1:1; /* NMI Falling Edge Events Enable 1 */
3532 uint32_t NFE1:1; /* NMI Filter Enable 1 */
3533 uint32_t NLOCK2:1; /* NMI Configuration Lock Register 2 */
3534 uint32_t NDSS2:2; /* NMI Desination Source Select 2 */
3535 uint32_t NWRE2:1; /* NMI Wakeup Request Enable 2 */
3536 uint32_t:1;
3537 uint32_t NREE2:1; /* NMI Rising Edge Events Enable 2 */
3538 uint32_t NFEE2:1; /* NMI Falling Edge Events Enable 2 */
3539 uint32_t NFE2:1; /* NMI Filter Enable 2 */
3540 uint32_t NLOCK3:1; /* NMI Configuration Lock Register 3 */
3541 uint32_t NDSS3:2; /* NMI Desination Source Select 3 */
3542 uint32_t NWRE3:1; /* NMI Wakeup Request Enable 3 */
3543 uint32_t:1;
3544 uint32_t NREE3:1; /* NMI Rising Edge Events Enable 3 */
3545 uint32_t NFEE3:1; /* NMI Falling Edge Events Enable 3 */
3546 uint32_t NFE3:1; /* NMI Filter Enable 3 */
3547 } B;
3548 } WKPU_NCR_32B_tag;
3549
3550 typedef union { /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */
3551 uint32_t R;
3552 struct {
3553 uint32_t EIF:32; /* External Wakeup/Interrupt Status Flag */
3554 } B;
3555 } WKPU_WISR_32B_tag;
3556
3557 typedef union { /* WKPU_IRER - Interrupt Request Enable Register */
3558 uint32_t R;
3559 struct {
3560 uint32_t EIRE:32; /* Enable External Interrupt Requests */
3561 } B;
3562 } WKPU_IRER_32B_tag;
3563
3564 typedef union { /* WKPU_WRER - Wakeup Request Enable Register */
3565 uint32_t R;
3566 struct {
3567 uint32_t WRE:32; /* Enable Wakeup requests to the mode entry module */
3568 } B;
3569 } WKPU_WRER_32B_tag;
3570
3571 typedef union { /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */
3572 uint32_t R;
3573 struct {
3574 uint32_t IREE:32; /* Enable rising-edge events to cause EIF[x] to be set */
3575 } B;
3576 } WKPU_WIREER_32B_tag;
3577
3578 typedef union { /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */
3579 uint32_t R;
3580 struct {
3581 uint32_t IFEE:32; /* Enable Falling-edge events to cause EIF[x] to be set */
3582 } B;
3583 } WKPU_WIFEER_32B_tag;
3584
3585 typedef union { /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */
3586 uint32_t R;
3587 struct {
3588 uint32_t IFE:32; /* Enable Digital glitch filter on the interrupt pad input */
3589 } B;
3590 } WKPU_WIFER_32B_tag;
3591
3592 typedef union { /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */
3593 uint32_t R;
3594 struct {
3595 uint32_t IPUE:32; /* Enable a pullup on the interrupt pad input */
3596 } B;
3597 } WKPU_WIPUER_32B_tag;
3598
3599
3600
3601 typedef struct WKPU_struct_tag { /* start of WKPU_tag */
3602 /* WKPU_NSR - NMI Status Flag Register */
3603 WKPU_NSR_32B_tag NSR; /* offset: 0x0000 size: 32 bit */
3604 int8_t WKPU_reserved_0004[4];
3605 /* WKPU_NCR - NMI Configuration Register */
3606 WKPU_NCR_32B_tag NCR; /* offset: 0x0008 size: 32 bit */
3607 int8_t WKPU_reserved_000C[8];
3608 /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */
3609 WKPU_WISR_32B_tag WISR; /* offset: 0x0014 size: 32 bit */
3610 /* WKPU_IRER - Interrupt Request Enable Register */
3611 WKPU_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */
3612 /* WKPU_WRER - Wakeup Request Enable Register */
3613 WKPU_WRER_32B_tag WRER; /* offset: 0x001C size: 32 bit */
3614 int8_t WKPU_reserved_0020[8];
3615 /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */
3616 WKPU_WIREER_32B_tag WIREER; /* offset: 0x0028 size: 32 bit */
3617 /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */
3618 WKPU_WIFEER_32B_tag WIFEER; /* offset: 0x002C size: 32 bit */
3619 /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */
3620 WKPU_WIFER_32B_tag WIFER; /* offset: 0x0030 size: 32 bit */
3621 /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */
3622 WKPU_WIPUER_32B_tag WIPUER; /* offset: 0x0034 size: 32 bit */
3623 } WKPU_tag;
3624
3625
3626#define WKPU (*(volatile WKPU_tag *) 0xC3F94000UL)
3627
3628
3629
3630/****************************************************************/
3631/* */
3632/* Module: SSCM */
3633/* */
3634/****************************************************************/
3635
3636 typedef union { /* SSCM_STATUS - System Status Register */
3637 uint16_t R;
3638 struct {
3639 uint16_t LSM:1; /* Lock Step Mode */
3640 uint16_t:2;
3641 uint16_t NXEN1:1; /* Processor 1 Nexus enabled */
3642 uint16_t NXEN:1; /* Processor 0 Nexus enabled */
3643 uint16_t PUB:1; /* Public Serial Access Status */
3644 uint16_t SEC:1; /* Security Status */
3645 uint16_t:1;
3646 uint16_t BMODE:3; /* Device Boot Mode */
3647 uint16_t VLE:1; /* Variable Length Instruction Mode */
3648 uint16_t ABD:1; /* Autobaud detection */
3649 uint16_t:3;
3650 } B;
3651 } SSCM_STATUS_16B_tag;
3652
3653 typedef union { /* SSCM_MEMCONFIG - System Memory Configuration Register */
3654 uint16_t R;
3655 struct {
3656 uint16_t JPIN:10; /* JTAG Part ID Number */
3657 uint16_t IVLD:1; /* Instruction Flash Valid */
3658 uint16_t MREV:4; /* Minor Mask Revision */
3659 uint16_t DVLD:1; /* Data Flash Valid */
3660 } B;
3661 } SSCM_MEMCONFIG_16B_tag;
3662
3663 typedef union { /* SSCM_ERROR - Error Configuration */
3664 uint16_t R;
3665 struct {
3666 uint16_t:14;
3667 uint16_t PAE:1; /* Peripheral Bus Abort Enable */
3668 uint16_t RAE:1; /* Register Bus Abort Enable */
3669 } B;
3670 } SSCM_ERROR_16B_tag;
3671
3672 typedef union { /* SSCM_DEBUGPORT - Debug Status Port Register */
3673 uint16_t R;
3674 struct {
3675 uint16_t:13;
3676 uint16_t DEBUG_MODE:3; /* Debug Status Port Mode */
3677 } B;
3678 } SSCM_DEBUGPORT_16B_tag;
3679
3680 typedef union { /* SSCM_PWCMPH - Password Comparison Register High */
3681 uint32_t R;
3682 struct {
3683 uint32_t PWD_HI:32; /* Password High */
3684 } B;
3685 } SSCM_PWCMPH_32B_tag;
3686
3687 typedef union { /* SSCM_PWCMPL - Password Comparison Register Low */
3688 uint32_t R;
3689 struct {
3690 uint32_t PWD_LO:32; /* Password Low */
3691 } B;
3692 } SSCM_PWCMPL_32B_tag;
3693
3694 typedef union { /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */
3695 uint32_t R;
3696 struct {
3697 uint32_t P2BOOT:30; /* boot location 2nd processor */
3698 uint32_t DVLE:1; /* VLE mode for 2nd processor */
3699 uint32_t:1;
3700 } B;
3701 } SSCM_DPMBOOT_32B_tag;
3702
3703 typedef union { /* SSCM_DPMKEY - Boot Key Register */
3704 uint32_t R;
3705 struct {
3706 uint32_t KEY:32; /* Boot Control Key */
3707 } B;
3708 } SSCM_DPMKEY_32B_tag;
3709
3710 typedef union { /* SSCM_UOPS - User Option Status Register */
3711 uint32_t R;
3712 struct {
3713 uint32_t UOPT:32; /* User Option Bits */
3714 } B;
3715 } SSCM_UOPS_32B_tag;
3716
3717 typedef union { /* SSCM_SCTR - SSCM Control Register */
3718 uint32_t R;
3719 struct {
3720 uint32_t:29;
3721 uint32_t TFE:1; /* Test Flash Enable */
3722 uint32_t DSL:1; /* Disable Software-Controlled MBIST */
3723 uint32_t DSM:1; /* Disable Software-Controlled LBIST */
3724 } B;
3725 } SSCM_SCTR_32B_tag;
3726
3727 typedef union { /* SSCM_TF_INFO0 - TestFlash Information Register 0 */
3728 uint32_t R;
3729 struct {
3730 uint32_t TINFO0:32; /* General purpose TestFlash word 0 */
3731 } B;
3732 } SSCM_TF_INFO0_32B_tag;
3733
3734 typedef union { /* SSCM_TF_INFO1 - TestFlash Information Register 1 */
3735 uint32_t R;
3736 struct {
3737 uint32_t TINFO1:32; /* General purpose TestFlash word 1 */
3738 } B;
3739 } SSCM_TF_INFO1_32B_tag;
3740
3741 typedef union { /* SSCM_TF_INFO2 - TestFlash Information Register 2 */
3742 uint32_t R;
3743 struct {
3744 uint32_t TINFO2:32; /* General purpose TestFlash word 2 */
3745 } B;
3746 } SSCM_TF_INFO2_32B_tag;
3747
3748 typedef union { /* SSCM_TF_INFO3 - TestFlash Information Register 3 */
3749 uint32_t R;
3750 struct {
3751 uint32_t TINFO3:32; /* General purpose TestFlash word */
3752 } B;
3753 } SSCM_TF_INFO3_32B_tag;
3754
3755
3756
3757 typedef struct SSCM_struct_tag { /* start of SSCM_tag */
3758 /* SSCM_STATUS - System Status Register */
3759 SSCM_STATUS_16B_tag STATUS; /* offset: 0x0000 size: 16 bit */
3760 /* SSCM_MEMCONFIG - System Memory Configuration Register */
3761 SSCM_MEMCONFIG_16B_tag MEMCONFIG; /* offset: 0x0002 size: 16 bit */
3762 int8_t SSCM_reserved_0004[2];
3763 /* SSCM_ERROR - Error Configuration */
3764 SSCM_ERROR_16B_tag ERROR; /* offset: 0x0006 size: 16 bit */
3765 /* SSCM_DEBUGPORT - Debug Status Port Register */
3766 SSCM_DEBUGPORT_16B_tag DEBUGPORT; /* offset: 0x0008 size: 16 bit */
3767 int8_t SSCM_reserved_000A[2];
3768 /* SSCM_PWCMPH - Password Comparison Register High */
3769 SSCM_PWCMPH_32B_tag PWCMPH; /* offset: 0x000C size: 32 bit */
3770 /* SSCM_PWCMPL - Password Comparison Register Low */
3771 SSCM_PWCMPL_32B_tag PWCMPL; /* offset: 0x0010 size: 32 bit */
3772 int8_t SSCM_reserved_0014[4];
3773 /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */
3774 SSCM_DPMBOOT_32B_tag DPMBOOT; /* offset: 0x0018 size: 32 bit */
3775 /* SSCM_DPMKEY - Boot Key Register */
3776 SSCM_DPMKEY_32B_tag DPMKEY; /* offset: 0x001C size: 32 bit */
3777 /* SSCM_UOPS - User Option Status Register */
3778 SSCM_UOPS_32B_tag UOPS; /* offset: 0x0020 size: 32 bit */
3779 /* SSCM_SCTR - SSCM Control Register */
3780 SSCM_SCTR_32B_tag SCTR; /* offset: 0x0024 size: 32 bit */
3781 /* SSCM_TF_INFO0 - TestFlash Information Register 0 */
3782 SSCM_TF_INFO0_32B_tag TF_INFO0; /* offset: 0x0028 size: 32 bit */
3783 /* SSCM_TF_INFO1 - TestFlash Information Register 1 */
3784 SSCM_TF_INFO1_32B_tag TF_INFO1; /* offset: 0x002C size: 32 bit */
3785 /* SSCM_TF_INFO2 - TestFlash Information Register 2 */
3786 SSCM_TF_INFO2_32B_tag TF_INFO2; /* offset: 0x0030 size: 32 bit */
3787 /* SSCM_TF_INFO3 - TestFlash Information Register 3 */
3788 SSCM_TF_INFO3_32B_tag TF_INFO3; /* offset: 0x0034 size: 32 bit */
3789 } SSCM_tag;
3790
3791
3792#define SSCM (*(volatile SSCM_tag *) 0xC3FD8000UL)
3793
3794
3795
3796/****************************************************************/
3797/* */
3798/* Module: ME */
3799/* */
3800/****************************************************************/
3801
3802 typedef union { /* ME_GS - Global Status Register */
3803 uint32_t R;
3804 struct {
3805#ifndef USE_FIELD_ALIASES_ME
3806 uint32_t S_CURRENT_MODE:4; /* Current device mode status */
3807#else
3808 uint32_t S_CURRENTMODE:4; /* deprecated name - please avoid */
3809#endif
3810 uint32_t S_MTRANS:1; /* Mode transition status */
3811 uint32_t:3;
3812 uint32_t S_PDO:1; /* Output power-down status */
3813 uint32_t:2;
3814 uint32_t S_MVR:1; /* Main voltage regulator status */
3815 uint32_t:2;
3816#ifndef USE_FIELD_ALIASES_ME
3817 uint32_t S_FLA:2; /* Flash availability status */
3818#else
3819 uint32_t S_CFLA:2; /* deprecated name - please avoid */
3820#endif
3821 uint32_t:8;
3822 uint32_t S_PLL1:1; /* Secondary PLL status */
3823 uint32_t S_PLL0:1; /* System PLL status */
3824#ifndef USE_FIELD_ALIASES_ME
3825 uint32_t S_XOSC:1; /* System crystal oscillator status */
3826#else
3827 uint32_t S_OSC:1; /* deprecated name - please avoid */
3828#endif
3829#ifndef USE_FIELD_ALIASES_ME
3830 uint32_t S_IRCOSC:1; /* System RC oscillator status */
3831#else
3832 uint32_t S_RC:1; /* deprecated name - please avoid */
3833#endif
3834 uint32_t S_SYSCLK:4; /* System clock switch status */
3835 } B;
3836 } ME_GS_32B_tag;
3837
3838 typedef union { /* ME_MCTL - Mode Control Register */
3839 uint32_t R;
3840 struct {
3841 uint32_t TARGET_MODE:4; /* Target device mode */
3842 uint32_t:12;
3843 uint32_t KEY:16; /* Control key */
3844 } B;
3845 } ME_MCTL_32B_tag;
3846
3847 typedef union { /* ME_MEN - Mode Enable Register */
3848 uint32_t R;
3849 struct {
3850 uint32_t:21;
3851 uint32_t STOP0:1; /* STOP0 mode enable */
3852 uint32_t:1;
3853 uint32_t HALT0:1; /* HALT0 mode enable */
3854 uint32_t RUN3:1; /* RUN3 mode enable */
3855 uint32_t RUN2:1; /* RUN2 mode enable */
3856 uint32_t RUN1:1; /* RUN1 mode enable */
3857 uint32_t RUN0:1; /* RUN0 mode enable */
3858 uint32_t DRUN:1; /* DRUN mode enable */
3859 uint32_t SAFE:1; /* SAFE mode enable */
3860 uint32_t:1;
3861 uint32_t RESET:1; /* RESET mode enable */
3862 } B;
3863 } ME_MEN_32B_tag;
3864
3865 typedef union { /* ME_IS - Interrupt Status Register */
3866 uint32_t R;
3867 struct {
3868 uint32_t:28;
3869#ifndef USE_FIELD_ALIASES_ME
3870 uint32_t I_ICONF:1; /* Invalid mode config interrupt */
3871#else
3872 uint32_t I_CONF:1; /* deprecated name - please avoid */
3873#endif
3874#ifndef USE_FIELD_ALIASES_ME
3875 uint32_t I_IMODE:1; /* Invalid mode interrupt */
3876#else
3877 uint32_t I_MODE:1; /* deprecated name - please avoid */
3878#endif
3879 uint32_t I_SAFE:1; /* SAFE mode interrupt */
3880#ifndef USE_FIELD_ALIASES_ME
3881 uint32_t I_MTC:1; /* Mode transition complete interrupt */
3882#else
3883 uint32_t I_TC:1; /* deprecated name - please avoid */
3884#endif
3885 } B;
3886 } ME_IS_32B_tag;
3887
3888 typedef union { /* ME_IM - Interrupt Mask Register */
3889 uint32_t R;
3890 struct {
3891 uint32_t:28;
3892#ifndef USE_FIELD_ALIASES_ME
3893 uint32_t M_ICONF:1; /* Invalid mode config interrupt mask */
3894#else
3895 uint32_t M_CONF:1; /* deprecated name - please avoid */
3896#endif
3897#ifndef USE_FIELD_ALIASES_ME
3898 uint32_t M_IMODE:1; /* Invalid mode interrupt mask */
3899#else
3900 uint32_t M_MODE:1; /* deprecated name - please avoid */
3901#endif
3902 uint32_t M_SAFE:1; /* SAFE mode interrupt mask */
3903#ifndef USE_FIELD_ALIASES_ME
3904 uint32_t M_MTC:1; /* Mode transition complete interrupt mask */
3905#else
3906 uint32_t M_TC:1; /* deprecated name - please avoid */
3907#endif
3908 } B;
3909 } ME_IM_32B_tag;
3910
3911 typedef union { /* ME_IMTS - Invalid Mode Transition Status Register */
3912 uint32_t R;
3913 struct {
3914 uint32_t:27;
3915 uint32_t S_MTI:1; /* Mode Transition Illegal status */
3916 uint32_t S_MRI:1; /* Mode Request Illegal status */
3917 uint32_t S_DMA:1; /* Disabled Mode Access status */
3918 uint32_t S_NMA:1; /* Non-existing Mode Access status */
3919 uint32_t S_SEA:1; /* Safe Event Active status */
3920 } B;
3921 } ME_IMTS_32B_tag;
3922
3923 typedef union { /* ME_DMTS - Debug Mode Transition Status Register */
3924 uint32_t R;
3925 struct {
3926 uint32_t PREVIOUS_MODE:4; /* Previous Device Mode */
3927 uint32_t:4;
3928 uint32_t MPH_BUSY:1; /* MC_ME/MC_PCU Handshake Busy Indicator */
3929 uint32_t:2;
3930 uint32_t PMC_PROG:1; /* MC_PCU Mode Change in Process Indicator */
3931 uint32_t CORE_DBG:1; /* Processor is in Debug Mode Indicator */
3932 uint32_t:2;
3933 uint32_t SMR:1; /* SAFE Mode Request */
3934 uint32_t:1;
3935 uint32_t VREG_CSRC_SC:1; /* Main VREG Clock Source State Change Indicator */
3936 uint32_t CSRC_CSRC_SC:1; /* Other Clock Source State Change Indicator */
3937 uint32_t IRCOSC_SC:1; /* IRCOSC State Change Indicator */
3938 uint32_t SCSRC_SC:1; /* Secondary System Clock Sources State Change Indicator */
3939 uint32_t SYSCLK_SW:1; /* System Clock Switching pending Status Indicator */
3940 uint32_t:1;
3941 uint32_t FLASH_SC:1; /* FLASH State Change Indicator */
3942 uint32_t CDP_PRPH_0_143:1; /* Clock Disable Process Pending Status for Periph. 0-143 */
3943 uint32_t:4;
3944 uint32_t CDP_PRPH_64_95:1; /* Clock Disable Process Pending Status for Periph. 64-95 */
3945 uint32_t CDP_PRPH_32_63:1; /* Clock Disable Process Pending Status for Periph. 32-63 */
3946 uint32_t CDP_PRPH_0_31:1; /* Clock Disable Process Pending Status for Periph. 0-31 */
3947 } B;
3948 } ME_DMTS_32B_tag;
3949
3950 typedef union { /* ME_RESET_MC - RESET Mode Configuration Register */
3951 uint32_t R;
3952 struct {
3953 uint32_t:8;
3954 uint32_t PDO:1; /* IOs output power-down control */
3955 uint32_t:2;
3956 uint32_t MVRON:1; /* Main voltage regulator control */
3957 uint32_t:2;
3958 uint32_t FLAON:2; /* Flash power-down control */
3959 uint32_t:8;
3960#ifndef USE_FIELD_ALIASES_ME
3961 uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
3962#else
3963 uint32_t PLL2ON:1; /* deprecated name - please avoid */
3964#endif
3965#ifndef USE_FIELD_ALIASES_ME
3966 uint32_t PLL0ON:1; /* System PLL control */
3967#else
3968 uint32_t PLL1ON:1; /* deprecated name - please avoid */
3969#endif
3970#ifndef USE_FIELD_ALIASES_ME
3971 uint32_t XOSCON:1; /* System crystal oscillator control */
3972#else
3973 uint32_t XOSC0ON:1; /* deprecated name - please avoid */
3974#endif
3975#ifndef USE_FIELD_ALIASES_ME
3976 uint32_t IRCOSCON:1; /* System RC oscillator control */
3977#else
3978 uint32_t IRCON:1; /* deprecated name - please avoid */
3979#endif
3980 uint32_t SYSCLK:4; /* System clock switch control */
3981 } B;
3982 } ME_RESET_MC_32B_tag;
3983
3984 typedef union { /* ME_SAFE_MC - Mode Configuration Register */
3985 uint32_t R;
3986 struct {
3987 uint32_t:8;
3988 uint32_t PDO:1; /* IOs output power-down control */
3989 uint32_t:2;
3990 uint32_t MVRON:1; /* Main voltage regulator control */
3991 uint32_t:2;
3992 uint32_t FLAON:2; /* Flash power-down control */
3993 uint32_t:8;
3994#ifndef USE_FIELD_ALIASES_ME
3995 uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
3996#else
3997 uint32_t PLL2ON:1; /* deprecated name - please avoid */
3998#endif
3999#ifndef USE_FIELD_ALIASES_ME
4000 uint32_t PLL0ON:1; /* System PLL control */
4001#else
4002 uint32_t PLL1ON:1; /* deprecated name - please avoid */
4003#endif
4004#ifndef USE_FIELD_ALIASES_ME
4005 uint32_t XOSCON:1; /* System crystal oscillator control */
4006#else
4007 uint32_t XOSC0ON:1; /* deprecated name - please avoid */
4008#endif
4009#ifndef USE_FIELD_ALIASES_ME
4010 uint32_t IRCOSCON:1; /* System RC oscillator control */
4011#else
4012 uint32_t IRCON:1; /* deprecated name - please avoid */
4013#endif
4014 uint32_t SYSCLK:4; /* System clock switch control */
4015 } B;
4016 } ME_SAFE_MC_32B_tag;
4017
4018 typedef union { /* ME_DRUN_MC - DRUN Mode Configuration Register */
4019 uint32_t R;
4020 struct {
4021 uint32_t:8;
4022 uint32_t PDO:1; /* IOs output power-down control */
4023 uint32_t:2;
4024 uint32_t MVRON:1; /* Main voltage regulator control */
4025 uint32_t:2;
4026 uint32_t FLAON:2; /* Flash power-down control */
4027 uint32_t:8;
4028#ifndef USE_FIELD_ALIASES_ME
4029 uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
4030#else
4031 uint32_t PLL2ON:1; /* deprecated name - please avoid */
4032#endif
4033#ifndef USE_FIELD_ALIASES_ME
4034 uint32_t PLL0ON:1; /* System PLL control */
4035#else
4036 uint32_t PLL1ON:1; /* deprecated name - please avoid */
4037#endif
4038#ifndef USE_FIELD_ALIASES_ME
4039 uint32_t XOSCON:1; /* System crystal oscillator control */
4040#else
4041 uint32_t XOSC0ON:1; /* deprecated name - please avoid */
4042#endif
4043#ifndef USE_FIELD_ALIASES_ME
4044 uint32_t IRCOSCON:1; /* System RC oscillator control */
4045#else
4046 uint32_t IRCON:1; /* deprecated name - please avoid */
4047#endif
4048 uint32_t SYSCLK:4; /* System clock switch control */
4049 } B;
4050 } ME_DRUN_MC_32B_tag;
4051
4052
4053 /* Register layout for all registers RUN_MC... */
4054
4055 typedef union { /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
4056 uint32_t R;
4057 struct {
4058 uint32_t:8;
4059 uint32_t PDO:1; /* IOs output power-down control */
4060 uint32_t:2;
4061 uint32_t MVRON:1; /* Main voltage regulator control */
4062 uint32_t:2;
4063 uint32_t FLAON:2; /* Flash power-down control */
4064 uint32_t:8;
4065#ifndef USE_FIELD_ALIASES_ME
4066 uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
4067#else
4068 uint32_t PLL2ON:1; /* deprecated name - please avoid */
4069#endif
4070#ifndef USE_FIELD_ALIASES_ME
4071 uint32_t PLL0ON:1; /* System PLL control */
4072#else
4073 uint32_t PLL1ON:1; /* deprecated name - please avoid */
4074#endif
4075#ifndef USE_FIELD_ALIASES_ME
4076 uint32_t XOSCON:1; /* System crystal oscillator control */
4077#else
4078 uint32_t XOSC0ON:1; /* deprecated name - please avoid */
4079#endif
4080#ifndef USE_FIELD_ALIASES_ME
4081 uint32_t IRCOSCON:1; /* System RC oscillator control */
4082#else
4083 uint32_t IRCON:1; /* deprecated name - please avoid */
4084#endif
4085 uint32_t SYSCLK:4; /* System clock switch control */
4086 } B;
4087 } ME_RUN_MC_32B_tag;
4088
4089 typedef union { /* ME_HALT0_MC - HALT0 Mode Configuration Register */
4090 uint32_t R;
4091 struct {
4092 uint32_t:8;
4093 uint32_t PDO:1; /* IOs output power-down control */
4094 uint32_t:2;
4095 uint32_t MVRON:1; /* Main voltage regulator control */
4096 uint32_t:2;
4097 uint32_t FLAON:2; /* Flash power-down control */
4098 uint32_t:8;
4099#ifndef USE_FIELD_ALIASES_ME
4100 uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
4101#else
4102 uint32_t PLL2ON:1; /* deprecated name - please avoid */
4103#endif
4104#ifndef USE_FIELD_ALIASES_ME
4105 uint32_t PLL0ON:1; /* System PLL control */
4106#else
4107 uint32_t PLL1ON:1; /* deprecated name - please avoid */
4108#endif
4109#ifndef USE_FIELD_ALIASES_ME
4110 uint32_t XOSCON:1; /* System crystal oscillator control */
4111#else
4112 uint32_t XOSC0ON:1; /* deprecated name - please avoid */
4113#endif
4114#ifndef USE_FIELD_ALIASES_ME
4115 uint32_t IRCOSCON:1; /* System RC oscillator control */
4116#else
4117 uint32_t IRCON:1; /* deprecated name - please avoid */
4118#endif
4119 uint32_t SYSCLK:4; /* System clock switch control */
4120 } B;
4121 } ME_HALT0_MC_32B_tag;
4122
4123 typedef union { /* ME_STOP0_MC - STOP0 Mode Configration Register */
4124 uint32_t R;
4125 struct {
4126 uint32_t:8;
4127 uint32_t PDO:1; /* IOs output power-down control */
4128 uint32_t:2;
4129 uint32_t MVRON:1; /* Main voltage regulator control */
4130 uint32_t:2;
4131 uint32_t FLAON:2; /* Flash power-down control */
4132 uint32_t:8;
4133#ifndef USE_FIELD_ALIASES_ME
4134 uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
4135#else
4136 uint32_t PLL2ON:1; /* deprecated name - please avoid */
4137#endif
4138#ifndef USE_FIELD_ALIASES_ME
4139 uint32_t PLL0ON:1; /* System PLL control */
4140#else
4141 uint32_t PLL1ON:1; /* deprecated name - please avoid */
4142#endif
4143#ifndef USE_FIELD_ALIASES_ME
4144 uint32_t XOSCON:1; /* System crystal oscillator control */
4145#else
4146 uint32_t XOSC0ON:1; /* deprecated name - please avoid */
4147#endif
4148#ifndef USE_FIELD_ALIASES_ME
4149 uint32_t IRCOSCON:1; /* System RC oscillator control */
4150#else
4151 uint32_t IRCON:1; /* deprecated name - please avoid */
4152#endif
4153 uint32_t SYSCLK:4; /* System clock switch control */
4154 } B;
4155 } ME_STOP0_MC_32B_tag;
4156
4157 typedef union { /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */
4158 uint32_t R;
4159 struct {
4160 uint32_t:8;
4161 uint32_t PDO:1; /* IOs output power-down control */
4162 uint32_t:2;
4163 uint32_t MVRON:1; /* Main voltage regulator control */
4164 uint32_t:2;
4165 uint32_t FLAON:2; /* Flash power-down control */
4166 uint32_t:8;
4167#ifndef USE_FIELD_ALIASES_ME
4168 uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
4169#else
4170 uint32_t PLL2ON:1; /* deprecated name - please avoid */
4171#endif
4172#ifndef USE_FIELD_ALIASES_ME
4173 uint32_t PLL0ON:1; /* System PLL control */
4174#else
4175 uint32_t PLL1ON:1; /* deprecated name - please avoid */
4176#endif
4177#ifndef USE_FIELD_ALIASES_ME
4178 uint32_t XOSCON:1; /* System crystal oscillator control */
4179#else
4180 uint32_t XOSC0ON:1; /* deprecated name - please avoid */
4181#endif
4182#ifndef USE_FIELD_ALIASES_ME
4183 uint32_t IRCOSCON:1; /* System RC oscillator control */
4184#else
4185 uint32_t IRCON:1; /* deprecated name - please avoid */
4186#endif
4187 uint32_t SYSCLK:4; /* System clock switch control */
4188 } B;
4189 } ME_STANDBY0_MC_32B_tag;
4190
4191 typedef union { /* ME_PS0 - Peripheral Status Register 0 */
4192 uint32_t R;
4193 struct {
4194 uint32_t:7;
4195 uint32_t S_FLEXRAY:1; /* FlexRay status */
4196 uint32_t:6;
4197 uint32_t S_FLEXCAN1:1; /* FlexCAN1 status */
4198 uint32_t S_FLEXCAN0:1; /* FlexCAN0 status */
4199 uint32_t:9;
4200 uint32_t S_DSPI2:1; /* DSPI2 status */
4201 uint32_t S_DSPI1:1; /* DSPI1 status */
4202 uint32_t S_DSPI0:1; /* DSPI0 status */
4203 uint32_t:4;
4204 } B;
4205 } ME_PS0_32B_tag;
4206
4207 typedef union { /* ME_PS1 - Peripheral Status Register 1 */
4208 uint32_t R;
4209 struct {
4210 uint32_t:1;
4211 uint32_t S_SWG:1; /* SWG status */
4212 uint32_t:3;
4213 uint32_t S_CRC:1; /* CRC status */
4214 uint32_t:8;
4215 uint32_t S_LIN_FLEX1:1; /* LinFlex1 status */
4216 uint32_t S_LIN_FLEX0:1; /* LinFlex0 status */
4217 uint32_t:5;
4218 uint32_t S_FLEXPWM1:1; /* FlexPWM1 status */
4219 uint32_t S_FLEXPWM0:1; /* FlexPWM0 status */
4220 uint32_t S_ETIMER2:1; /* eTimer2 status */
4221 uint32_t S_ETIMER1:1; /* eTimer1 status */
4222 uint32_t S_ETIMER0:1; /* eTimer0 status */
4223 uint32_t:2;
4224 uint32_t S_CTU:1; /* CTU status */
4225 uint32_t:1;
4226 uint32_t S_ADC1:1; /* ADC1 status */
4227 uint32_t S_ADC0:1; /* ADC0 status */
4228 } B;
4229 } ME_PS1_32B_tag;
4230
4231 typedef union { /* ME_PS2 - Peripheral Status Register 2 */
4232 uint32_t R;
4233 struct {
4234 uint32_t:3;
4235 uint32_t S_PIT:1; /* PIT status */
4236 uint32_t:28;
4237 } B;
4238 } ME_PS2_32B_tag;
4239
4240
4241 /* Register layout for all registers RUN_PC... */
4242
4243 typedef union { /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
4244 uint32_t R;
4245 struct {
4246 uint32_t:24;
4247 uint32_t RUN3:1; /* Peripheral control during RUN3 */
4248 uint32_t RUN2:1; /* Peripheral control during RUN2 */
4249 uint32_t RUN1:1; /* Peripheral control during RUN1 */
4250 uint32_t RUN0:1; /* Peripheral control during RUN0 */
4251 uint32_t DRUN:1; /* Peripheral control during DRUN */
4252 uint32_t SAFE:1; /* Peripheral control during SAFE */
4253 uint32_t TEST:1; /* Peripheral control during TEST */
4254 uint32_t RESET:1; /* Peripheral control during RESET */
4255 } B;
4256 } ME_RUN_PC_32B_tag;
4257
4258
4259 /* Register layout for all registers LP_PC... */
4260
4261 typedef union { /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
4262 uint32_t R;
4263 struct {
4264 uint32_t:21;
4265 uint32_t STOP0:1; /* Peripheral control during STOP0 */
4266 uint32_t:1;
4267 uint32_t HALT0:1; /* Peripheral control during HALT0 */
4268 uint32_t:8;
4269 } B;
4270 } ME_LP_PC_32B_tag;
4271
4272
4273 /* Register layout for all registers PCTL... */
4274
4275 typedef union { /* ME_PCTL[0...143] - Peripheral Control Registers */
4276 uint8_t R;
4277 struct {
4278 uint8_t:1;
4279 uint8_t DBG_F:1; /* Peripheral control in debug mode */
4280 uint8_t LP_CFG:3; /* Peripheral configuration select for non-RUN modes */
4281 uint8_t RUN_CFG:3; /* Peripheral configuration select for RUN modes */
4282 } B;
4283 } ME_PCTL_8B_tag;
4284
4285
4286
4287
4288 /* Register layout for generated register(s) PS... */
4289
4290 typedef union { /* */
4291 uint32_t R;
4292 } ME_PS_32B_tag;
4293
4294
4295
4296
4297
4298
4299 typedef struct ME_struct_tag { /* start of ME_tag */
4300 /* ME_GS - Global Status Register */
4301 ME_GS_32B_tag GS; /* offset: 0x0000 size: 32 bit */
4302 /* ME_MCTL - Mode Control Register */
4303 ME_MCTL_32B_tag MCTL; /* offset: 0x0004 size: 32 bit */
4304 union {
4305 ME_MEN_32B_tag MER; /* deprecated - please avoid */
4306
4307 /* ME_MEN - Mode Enable Register */
4308 ME_MEN_32B_tag MEN; /* offset: 0x0008 size: 32 bit */
4309
4310 };
4311 /* ME_IS - Interrupt Status Register */
4312 ME_IS_32B_tag IS; /* offset: 0x000C size: 32 bit */
4313 /* ME_IM - Interrupt Mask Register */
4314 ME_IM_32B_tag IM; /* offset: 0x0010 size: 32 bit */
4315 /* ME_IMTS - Invalid Mode Transition Status Register */
4316 ME_IMTS_32B_tag IMTS; /* offset: 0x0014 size: 32 bit */
4317 /* ME_DMTS - Debug Mode Transition Status Register */
4318 ME_DMTS_32B_tag DMTS; /* offset: 0x0018 size: 32 bit */
4319 int8_t ME_reserved_001C_C[4];
4320 union {
4321 /* ME_RESET_MC - RESET Mode Configuration Register */
4322 ME_RESET_MC_32B_tag RESET_MC; /* offset: 0x0020 size: 32 bit */
4323
4324 ME_RESET_MC_32B_tag RESET; /* deprecated - please avoid */
4325
4326 };
4327 int8_t ME_reserved_0024_C[4];
4328 union {
4329 /* ME_SAFE_MC - Mode Configuration Register */
4330 ME_SAFE_MC_32B_tag SAFE_MC; /* offset: 0x0028 size: 32 bit */
4331
4332 ME_SAFE_MC_32B_tag SAFE; /* deprecated - please avoid */
4333
4334 };
4335 union {
4336 /* ME_DRUN_MC - DRUN Mode Configuration Register */
4337 ME_DRUN_MC_32B_tag DRUN_MC; /* offset: 0x002C size: 32 bit */
4338
4339 ME_DRUN_MC_32B_tag DRUN; /* deprecated - please avoid */
4340
4341 };
4342 union {
4343 /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
4344 ME_RUN_MC_32B_tag RUN_MC[4]; /* offset: 0x0030 (0x0004 x 4) */
4345
4346 ME_RUN_MC_32B_tag RUN[4]; /* offset: 0x0030 (0x0004 x 4) */ /* deprecated - please avoid */
4347
4348 struct {
4349 /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
4350 ME_RUN_MC_32B_tag RUN0_MC; /* offset: 0x0030 size: 32 bit */
4351 ME_RUN_MC_32B_tag RUN1_MC; /* offset: 0x0034 size: 32 bit */
4352 ME_RUN_MC_32B_tag RUN2_MC; /* offset: 0x0038 size: 32 bit */
4353 ME_RUN_MC_32B_tag RUN3_MC; /* offset: 0x003C size: 32 bit */
4354 };
4355
4356 };
4357 union {
4358 /* ME_HALT0_MC - HALT0 Mode Configuration Register */
4359 ME_HALT0_MC_32B_tag HALT0_MC; /* offset: 0x0040 size: 32 bit */
4360
4361 ME_HALT0_MC_32B_tag HALT0; /* deprecated - please avoid */
4362
4363 };
4364 int8_t ME_reserved_0044_C[4];
4365 union {
4366 /* ME_STOP0_MC - STOP0 Mode Configration Register */
4367 ME_STOP0_MC_32B_tag STOP0_MC; /* offset: 0x0048 size: 32 bit */
4368
4369 ME_STOP0_MC_32B_tag STOP0; /* deprecated - please avoid */
4370
4371 };
4372 int8_t ME_reserved_004C_C[8];
4373 union {
4374 /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */
4375 ME_STANDBY0_MC_32B_tag STANDBY0_MC; /* offset: 0x0054 size: 32 bit */
4376
4377 ME_STANDBY0_MC_32B_tag STANDBY0; /* deprecated - please avoid */
4378
4379 };
4380 int8_t ME_reserved_0058_C[8];
4381 union {
4382 ME_PS_32B_tag PS[3]; /* offset: 0x0060 (0x0004 x 3) */
4383
4384 struct {
4385 /* ME_PS0 - Peripheral Status Register 0 */
4386 ME_PS0_32B_tag PS0; /* offset: 0x0060 size: 32 bit */
4387 /* ME_PS1 - Peripheral Status Register 1 */
4388 ME_PS1_32B_tag PS1; /* offset: 0x0064 size: 32 bit */
4389 /* ME_PS2 - Peripheral Status Register 2 */
4390 ME_PS2_32B_tag PS2; /* offset: 0x0068 size: 32 bit */
4391 };
4392
4393 };
4394 int8_t ME_reserved_006C_C[20];
4395 union {
4396 ME_RUN_PC_32B_tag RUNPC[8]; /* offset: 0x0080 (0x0004 x 8) */
4397
4398 /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
4399 ME_RUN_PC_32B_tag RUN_PC[8]; /* offset: 0x0080 (0x0004 x 8) */
4400
4401 struct {
4402 /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
4403 ME_RUN_PC_32B_tag RUN_PC0; /* offset: 0x0080 size: 32 bit */
4404 ME_RUN_PC_32B_tag RUN_PC1; /* offset: 0x0084 size: 32 bit */
4405 ME_RUN_PC_32B_tag RUN_PC2; /* offset: 0x0088 size: 32 bit */
4406 ME_RUN_PC_32B_tag RUN_PC3; /* offset: 0x008C size: 32 bit */
4407 ME_RUN_PC_32B_tag RUN_PC4; /* offset: 0x0090 size: 32 bit */
4408 ME_RUN_PC_32B_tag RUN_PC5; /* offset: 0x0094 size: 32 bit */
4409 ME_RUN_PC_32B_tag RUN_PC6; /* offset: 0x0098 size: 32 bit */
4410 ME_RUN_PC_32B_tag RUN_PC7; /* offset: 0x009C size: 32 bit */
4411 };
4412
4413 };
4414 union {
4415 ME_LP_PC_32B_tag LPPC[8]; /* offset: 0x00A0 (0x0004 x 8) */
4416
4417 /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
4418 ME_LP_PC_32B_tag LP_PC[8]; /* offset: 0x00A0 (0x0004 x 8) */
4419
4420 struct {
4421 /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
4422 ME_LP_PC_32B_tag LP_PC0; /* offset: 0x00A0 size: 32 bit */
4423 ME_LP_PC_32B_tag LP_PC1; /* offset: 0x00A4 size: 32 bit */
4424 ME_LP_PC_32B_tag LP_PC2; /* offset: 0x00A8 size: 32 bit */
4425 ME_LP_PC_32B_tag LP_PC3; /* offset: 0x00AC size: 32 bit */
4426 ME_LP_PC_32B_tag LP_PC4; /* offset: 0x00B0 size: 32 bit */
4427 ME_LP_PC_32B_tag LP_PC5; /* offset: 0x00B4 size: 32 bit */
4428 ME_LP_PC_32B_tag LP_PC6; /* offset: 0x00B8 size: 32 bit */
4429 ME_LP_PC_32B_tag LP_PC7; /* offset: 0x00BC size: 32 bit */
4430 };
4431
4432 };
4433 union {
4434 /* ME_PCTL[0...143] - Peripheral Control Registers */
4435 ME_PCTL_8B_tag PCTL[144]; /* offset: 0x00C0 (0x0001 x 144) */
4436
4437 struct {
4438 /* ME_PCTL[0...143] - Peripheral Control Registers */
4439 ME_PCTL_8B_tag PCTL0; /* offset: 0x00C0 size: 8 bit */
4440 ME_PCTL_8B_tag PCTL1; /* offset: 0x00C1 size: 8 bit */
4441 ME_PCTL_8B_tag PCTL2; /* offset: 0x00C2 size: 8 bit */
4442 ME_PCTL_8B_tag PCTL3; /* offset: 0x00C3 size: 8 bit */
4443 ME_PCTL_8B_tag PCTL4; /* offset: 0x00C4 size: 8 bit */
4444 ME_PCTL_8B_tag PCTL5; /* offset: 0x00C5 size: 8 bit */
4445 ME_PCTL_8B_tag PCTL6; /* offset: 0x00C6 size: 8 bit */
4446 ME_PCTL_8B_tag PCTL7; /* offset: 0x00C7 size: 8 bit */
4447 ME_PCTL_8B_tag PCTL8; /* offset: 0x00C8 size: 8 bit */
4448 ME_PCTL_8B_tag PCTL9; /* offset: 0x00C9 size: 8 bit */
4449 ME_PCTL_8B_tag PCTL10; /* offset: 0x00CA size: 8 bit */
4450 ME_PCTL_8B_tag PCTL11; /* offset: 0x00CB size: 8 bit */
4451 ME_PCTL_8B_tag PCTL12; /* offset: 0x00CC size: 8 bit */
4452 ME_PCTL_8B_tag PCTL13; /* offset: 0x00CD size: 8 bit */
4453 ME_PCTL_8B_tag PCTL14; /* offset: 0x00CE size: 8 bit */
4454 ME_PCTL_8B_tag PCTL15; /* offset: 0x00CF size: 8 bit */
4455 ME_PCTL_8B_tag PCTL16; /* offset: 0x00D0 size: 8 bit */
4456 ME_PCTL_8B_tag PCTL17; /* offset: 0x00D1 size: 8 bit */
4457 ME_PCTL_8B_tag PCTL18; /* offset: 0x00D2 size: 8 bit */
4458 ME_PCTL_8B_tag PCTL19; /* offset: 0x00D3 size: 8 bit */
4459 ME_PCTL_8B_tag PCTL20; /* offset: 0x00D4 size: 8 bit */
4460 ME_PCTL_8B_tag PCTL21; /* offset: 0x00D5 size: 8 bit */
4461 ME_PCTL_8B_tag PCTL22; /* offset: 0x00D6 size: 8 bit */
4462 ME_PCTL_8B_tag PCTL23; /* offset: 0x00D7 size: 8 bit */
4463 ME_PCTL_8B_tag PCTL24; /* offset: 0x00D8 size: 8 bit */
4464 ME_PCTL_8B_tag PCTL25; /* offset: 0x00D9 size: 8 bit */
4465 ME_PCTL_8B_tag PCTL26; /* offset: 0x00DA size: 8 bit */
4466 ME_PCTL_8B_tag PCTL27; /* offset: 0x00DB size: 8 bit */
4467 ME_PCTL_8B_tag PCTL28; /* offset: 0x00DC size: 8 bit */
4468 ME_PCTL_8B_tag PCTL29; /* offset: 0x00DD size: 8 bit */
4469 ME_PCTL_8B_tag PCTL30; /* offset: 0x00DE size: 8 bit */
4470 ME_PCTL_8B_tag PCTL31; /* offset: 0x00DF size: 8 bit */
4471 ME_PCTL_8B_tag PCTL32; /* offset: 0x00E0 size: 8 bit */
4472 ME_PCTL_8B_tag PCTL33; /* offset: 0x00E1 size: 8 bit */
4473 ME_PCTL_8B_tag PCTL34; /* offset: 0x00E2 size: 8 bit */
4474 ME_PCTL_8B_tag PCTL35; /* offset: 0x00E3 size: 8 bit */
4475 ME_PCTL_8B_tag PCTL36; /* offset: 0x00E4 size: 8 bit */
4476 ME_PCTL_8B_tag PCTL37; /* offset: 0x00E5 size: 8 bit */
4477 ME_PCTL_8B_tag PCTL38; /* offset: 0x00E6 size: 8 bit */
4478 ME_PCTL_8B_tag PCTL39; /* offset: 0x00E7 size: 8 bit */
4479 ME_PCTL_8B_tag PCTL40; /* offset: 0x00E8 size: 8 bit */
4480 ME_PCTL_8B_tag PCTL41; /* offset: 0x00E9 size: 8 bit */
4481 ME_PCTL_8B_tag PCTL42; /* offset: 0x00EA size: 8 bit */
4482 ME_PCTL_8B_tag PCTL43; /* offset: 0x00EB size: 8 bit */
4483 ME_PCTL_8B_tag PCTL44; /* offset: 0x00EC size: 8 bit */
4484 ME_PCTL_8B_tag PCTL45; /* offset: 0x00ED size: 8 bit */
4485 ME_PCTL_8B_tag PCTL46; /* offset: 0x00EE size: 8 bit */
4486 ME_PCTL_8B_tag PCTL47; /* offset: 0x00EF size: 8 bit */
4487 ME_PCTL_8B_tag PCTL48; /* offset: 0x00F0 size: 8 bit */
4488 ME_PCTL_8B_tag PCTL49; /* offset: 0x00F1 size: 8 bit */
4489 ME_PCTL_8B_tag PCTL50; /* offset: 0x00F2 size: 8 bit */
4490 ME_PCTL_8B_tag PCTL51; /* offset: 0x00F3 size: 8 bit */
4491 ME_PCTL_8B_tag PCTL52; /* offset: 0x00F4 size: 8 bit */
4492 ME_PCTL_8B_tag PCTL53; /* offset: 0x00F5 size: 8 bit */
4493 ME_PCTL_8B_tag PCTL54; /* offset: 0x00F6 size: 8 bit */
4494 ME_PCTL_8B_tag PCTL55; /* offset: 0x00F7 size: 8 bit */
4495 ME_PCTL_8B_tag PCTL56; /* offset: 0x00F8 size: 8 bit */
4496 ME_PCTL_8B_tag PCTL57; /* offset: 0x00F9 size: 8 bit */
4497 ME_PCTL_8B_tag PCTL58; /* offset: 0x00FA size: 8 bit */
4498 ME_PCTL_8B_tag PCTL59; /* offset: 0x00FB size: 8 bit */
4499 ME_PCTL_8B_tag PCTL60; /* offset: 0x00FC size: 8 bit */
4500 ME_PCTL_8B_tag PCTL61; /* offset: 0x00FD size: 8 bit */
4501 ME_PCTL_8B_tag PCTL62; /* offset: 0x00FE size: 8 bit */
4502 ME_PCTL_8B_tag PCTL63; /* offset: 0x00FF size: 8 bit */
4503 ME_PCTL_8B_tag PCTL64; /* offset: 0x0100 size: 8 bit */
4504 ME_PCTL_8B_tag PCTL65; /* offset: 0x0101 size: 8 bit */
4505 ME_PCTL_8B_tag PCTL66; /* offset: 0x0102 size: 8 bit */
4506 ME_PCTL_8B_tag PCTL67; /* offset: 0x0103 size: 8 bit */
4507 ME_PCTL_8B_tag PCTL68; /* offset: 0x0104 size: 8 bit */
4508 ME_PCTL_8B_tag PCTL69; /* offset: 0x0105 size: 8 bit */
4509 ME_PCTL_8B_tag PCTL70; /* offset: 0x0106 size: 8 bit */
4510 ME_PCTL_8B_tag PCTL71; /* offset: 0x0107 size: 8 bit */
4511 ME_PCTL_8B_tag PCTL72; /* offset: 0x0108 size: 8 bit */
4512 ME_PCTL_8B_tag PCTL73; /* offset: 0x0109 size: 8 bit */
4513 ME_PCTL_8B_tag PCTL74; /* offset: 0x010A size: 8 bit */
4514 ME_PCTL_8B_tag PCTL75; /* offset: 0x010B size: 8 bit */
4515 ME_PCTL_8B_tag PCTL76; /* offset: 0x010C size: 8 bit */
4516 ME_PCTL_8B_tag PCTL77; /* offset: 0x010D size: 8 bit */
4517 ME_PCTL_8B_tag PCTL78; /* offset: 0x010E size: 8 bit */
4518 ME_PCTL_8B_tag PCTL79; /* offset: 0x010F size: 8 bit */
4519 ME_PCTL_8B_tag PCTL80; /* offset: 0x0110 size: 8 bit */
4520 ME_PCTL_8B_tag PCTL81; /* offset: 0x0111 size: 8 bit */
4521 ME_PCTL_8B_tag PCTL82; /* offset: 0x0112 size: 8 bit */
4522 ME_PCTL_8B_tag PCTL83; /* offset: 0x0113 size: 8 bit */
4523 ME_PCTL_8B_tag PCTL84; /* offset: 0x0114 size: 8 bit */
4524 ME_PCTL_8B_tag PCTL85; /* offset: 0x0115 size: 8 bit */
4525 ME_PCTL_8B_tag PCTL86; /* offset: 0x0116 size: 8 bit */
4526 ME_PCTL_8B_tag PCTL87; /* offset: 0x0117 size: 8 bit */
4527 ME_PCTL_8B_tag PCTL88; /* offset: 0x0118 size: 8 bit */
4528 ME_PCTL_8B_tag PCTL89; /* offset: 0x0119 size: 8 bit */
4529 ME_PCTL_8B_tag PCTL90; /* offset: 0x011A size: 8 bit */
4530 ME_PCTL_8B_tag PCTL91; /* offset: 0x011B size: 8 bit */
4531 ME_PCTL_8B_tag PCTL92; /* offset: 0x011C size: 8 bit */
4532 ME_PCTL_8B_tag PCTL93; /* offset: 0x011D size: 8 bit */
4533 ME_PCTL_8B_tag PCTL94; /* offset: 0x011E size: 8 bit */
4534 ME_PCTL_8B_tag PCTL95; /* offset: 0x011F size: 8 bit */
4535 ME_PCTL_8B_tag PCTL96; /* offset: 0x0120 size: 8 bit */
4536 ME_PCTL_8B_tag PCTL97; /* offset: 0x0121 size: 8 bit */
4537 ME_PCTL_8B_tag PCTL98; /* offset: 0x0122 size: 8 bit */
4538 ME_PCTL_8B_tag PCTL99; /* offset: 0x0123 size: 8 bit */
4539 ME_PCTL_8B_tag PCTL100; /* offset: 0x0124 size: 8 bit */
4540 ME_PCTL_8B_tag PCTL101; /* offset: 0x0125 size: 8 bit */
4541 ME_PCTL_8B_tag PCTL102; /* offset: 0x0126 size: 8 bit */
4542 ME_PCTL_8B_tag PCTL103; /* offset: 0x0127 size: 8 bit */
4543 ME_PCTL_8B_tag PCTL104; /* offset: 0x0128 size: 8 bit */
4544 ME_PCTL_8B_tag PCTL105; /* offset: 0x0129 size: 8 bit */
4545 ME_PCTL_8B_tag PCTL106; /* offset: 0x012A size: 8 bit */
4546 ME_PCTL_8B_tag PCTL107; /* offset: 0x012B size: 8 bit */
4547 ME_PCTL_8B_tag PCTL108; /* offset: 0x012C size: 8 bit */
4548 ME_PCTL_8B_tag PCTL109; /* offset: 0x012D size: 8 bit */
4549 ME_PCTL_8B_tag PCTL110; /* offset: 0x012E size: 8 bit */
4550 ME_PCTL_8B_tag PCTL111; /* offset: 0x012F size: 8 bit */
4551 ME_PCTL_8B_tag PCTL112; /* offset: 0x0130 size: 8 bit */
4552 ME_PCTL_8B_tag PCTL113; /* offset: 0x0131 size: 8 bit */
4553 ME_PCTL_8B_tag PCTL114; /* offset: 0x0132 size: 8 bit */
4554 ME_PCTL_8B_tag PCTL115; /* offset: 0x0133 size: 8 bit */
4555 ME_PCTL_8B_tag PCTL116; /* offset: 0x0134 size: 8 bit */
4556 ME_PCTL_8B_tag PCTL117; /* offset: 0x0135 size: 8 bit */
4557 ME_PCTL_8B_tag PCTL118; /* offset: 0x0136 size: 8 bit */
4558 ME_PCTL_8B_tag PCTL119; /* offset: 0x0137 size: 8 bit */
4559 ME_PCTL_8B_tag PCTL120; /* offset: 0x0138 size: 8 bit */
4560 ME_PCTL_8B_tag PCTL121; /* offset: 0x0139 size: 8 bit */
4561 ME_PCTL_8B_tag PCTL122; /* offset: 0x013A size: 8 bit */
4562 ME_PCTL_8B_tag PCTL123; /* offset: 0x013B size: 8 bit */
4563 ME_PCTL_8B_tag PCTL124; /* offset: 0x013C size: 8 bit */
4564 ME_PCTL_8B_tag PCTL125; /* offset: 0x013D size: 8 bit */
4565 ME_PCTL_8B_tag PCTL126; /* offset: 0x013E size: 8 bit */
4566 ME_PCTL_8B_tag PCTL127; /* offset: 0x013F size: 8 bit */
4567 ME_PCTL_8B_tag PCTL128; /* offset: 0x0140 size: 8 bit */
4568 ME_PCTL_8B_tag PCTL129; /* offset: 0x0141 size: 8 bit */
4569 ME_PCTL_8B_tag PCTL130; /* offset: 0x0142 size: 8 bit */
4570 ME_PCTL_8B_tag PCTL131; /* offset: 0x0143 size: 8 bit */
4571 ME_PCTL_8B_tag PCTL132; /* offset: 0x0144 size: 8 bit */
4572 ME_PCTL_8B_tag PCTL133; /* offset: 0x0145 size: 8 bit */
4573 ME_PCTL_8B_tag PCTL134; /* offset: 0x0146 size: 8 bit */
4574 ME_PCTL_8B_tag PCTL135; /* offset: 0x0147 size: 8 bit */
4575 ME_PCTL_8B_tag PCTL136; /* offset: 0x0148 size: 8 bit */
4576 ME_PCTL_8B_tag PCTL137; /* offset: 0x0149 size: 8 bit */
4577 ME_PCTL_8B_tag PCTL138; /* offset: 0x014A size: 8 bit */
4578 ME_PCTL_8B_tag PCTL139; /* offset: 0x014B size: 8 bit */
4579 ME_PCTL_8B_tag PCTL140; /* offset: 0x014C size: 8 bit */
4580 ME_PCTL_8B_tag PCTL141; /* offset: 0x014D size: 8 bit */
4581 ME_PCTL_8B_tag PCTL142; /* offset: 0x014E size: 8 bit */
4582 ME_PCTL_8B_tag PCTL143; /* offset: 0x014F size: 8 bit */
4583 };
4584
4585 };
4586 } ME_tag;
4587
4588
4589#define ME (*(volatile ME_tag *) 0xC3FDC000UL)
4590
4591
4592
4593/****************************************************************/
4594/* */
4595/* Module: OSC */
4596/* */
4597/****************************************************************/
4598
4599 typedef union { /* OSC_CTL - Control Register */
4600 uint32_t R;
4601 struct {
4602 uint32_t OSCBYP:1; /* High Frequency Oscillator Bypass */
4603 uint32_t:7;
4604 uint32_t EOCV:8; /* End of Count Value */
4605 uint32_t M_OSC:1; /* High Frequency Oscillator Clock Interrupt Mask */
4606 uint32_t:2;
4607 uint32_t OSCDIV:5; /* High Frequency Oscillator Division Factor */
4608 uint32_t I_OSC:1; /* High Frequency Oscillator Clock Interrupt */
4609 uint32_t:5;
4610 uint32_t S_OSC:1;
4611 uint32_t OSCON:1; } B;
4612 } OSC_CTL_32B_tag;
4613
4614
4615
4616 typedef struct OSC_struct_tag { /* start of OSC_tag */
4617 /* OSC_CTL - Control Register */
4618 OSC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */
4619 } OSC_tag;
4620
4621
4622#define OSC (*(volatile OSC_tag *) 0xC3FE0000UL)
4623
4624
4625
4626/****************************************************************/
4627/* */
4628/* Module: RC */
4629/* */
4630/****************************************************************/
4631
4632 typedef union { /* RC_CTL - Control Register */
4633 uint32_t R;
4634 struct {
4635 uint32_t:10;
4636 uint32_t RCTRIM:6; /* Main RC Trimming Bits */
4637 uint32_t:3;
4638 uint32_t RCDIV:5; /* Main RC Clock Division Factor */
4639 uint32_t:2;
4640 uint32_t S_RC_STDBY:1; /* MRC Oscillator Powerdown Status */
4641 uint32_t:5;
4642 } B;
4643 } RC_CTL_32B_tag;
4644
4645
4646
4647 typedef struct RC_struct_tag { /* start of RC_tag */
4648 /* RC_CTL - Control Register */
4649 RC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */
4650 } RC_tag;
4651
4652
4653#define RC (*(volatile RC_tag *) 0xC3FE0060UL)
4654
4655
4656
4657/****************************************************************/
4658/* */
4659/* Module: PLLD */
4660/* */
4661/****************************************************************/
4662
4663 typedef union { /* PLLD_CR - Control Register */
4664 uint32_t R;
4665 struct {
4666 uint32_t:2;
4667 uint32_t IDF:4; /* PLL Input Division Factor */
4668 uint32_t ODF:2; /* PLL Output Division Factor */
4669 uint32_t:1;
4670 uint32_t NDIV:7; /* PLL Loop Division Factor */
4671 uint32_t:7;
4672 uint32_t EN_PLL_SW:1; /* Enable Progressive Clock Switching */
4673 uint32_t MODE:1; /* Activate 1:1 Mode */
4674 uint32_t UNLOCK_ONCE:1; /* PLL Loss of Lock */
4675 uint32_t M_LOCK:1; /* Mask for the i_lock Output Interrupt */
4676 uint32_t I_LOCK:1; /* PLL Lock Signal Toggle Indicator */
4677 uint32_t S_LOCK:1; /* PLL has Aquired Lock */
4678 uint32_t PLL_FAIL_MASK:1; /* PLL Fail Mask */
4679 uint32_t PLL_FAIL_FLAG:1; /* PLL Fail Flag */
4680 uint32_t PLL_ON:1; /* PLL ON Bit */
4681 } B;
4682 } PLLD_CR_32B_tag;
4683
4684 typedef union { /* PLLD_MR - PLLD Modulation Register */
4685 uint32_t R;
4686 struct {
4687 uint32_t STRB_BYPASS:1; /* Strobe Bypass */
4688 uint32_t:1;
4689 uint32_t SPRD_SEL:1; /* Spread Type Selection */
4690 uint32_t MOD_PERIOD:13; /* Modulation Period */
4691#ifndef USE_FIELD_ALIASES_PLLD
4692 uint32_t SSCG_EN:1; /* Spread Spectrum Clock Generation Enable */
4693#else
4694 uint32_t FM_EN:1; /* deprecated name - please avoid */
4695#endif
4696 uint32_t INC_STEP:15; /* Increment Step */
4697 } B;
4698 } PLLD_MR_32B_tag;
4699
4700
4701
4702 typedef struct PLLD_struct_tag { /* start of PLLD_tag */
4703 /* PLLD_CR - Control Register */
4704 PLLD_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */
4705 /* PLLD_MR - PLLD Modulation Register */
4706 PLLD_MR_32B_tag MR; /* offset: 0x0004 size: 32 bit */
4707
4708 uint32_t plld_reserved[6];
4709 } PLLD_tag;
4710
4711
4712#define PLLD0 (*(volatile PLLD_tag *) 0xC3FE00A0UL)
4713#define PLLD1 (*(volatile PLLD_tag *) 0xC3FE00C0UL)
4714
4715
4716
4717/****************************************************************/
4718/* */
4719/* Module: CMU */
4720/* */
4721/****************************************************************/
4722
4723 typedef union { /* CMU_CSR - Control Status Register */
4724 uint32_t R;
4725 struct {
4726 uint32_t:8;
4727 uint32_t SFM:1; /* Start Frequency Measure */
4728 uint32_t:13;
4729#ifndef USE_FIELD_ALIASES_RGM
4730 uint32_t CKSEL1:2; /* RC Oscillator(s) Selection Bit */
4731#else
4732 uint32_t CLKSEL1:2; /* deprecated name - please avoid */
4733#endif
4734 uint32_t:5;
4735 uint32_t RCDIV:2; /* RCfast Clock Division Factor */
4736 uint32_t CME_A:1; /* PLL_A Clock Monitor Enable */
4737 } B;
4738 } CMU_CSR_32B_tag;
4739
4740 typedef union { /* CMU_FDR - Frequency Display Register */
4741 uint32_t R;
4742 struct {
4743 uint32_t:12;
4744 uint32_t FD:20; /* Measured Frequency Bits */
4745 } B;
4746 } CMU_FDR_32B_tag;
4747
4748 typedef union { /* CMU_HFREFR_A - High Frequency Reference Register */
4749 uint32_t R;
4750 struct {
4751 uint32_t:20;
4752 uint32_t HFREF_A:12; /* High Frequency Reference Value */
4753 } B;
4754 } CMU_HFREFR_A_32B_tag;
4755
4756 typedef union { /* CMU_LFREFR_A - Low Frequency Reference Register */
4757 uint32_t R;
4758 struct {
4759 uint32_t:20;
4760 uint32_t LFREF_A:12; /* Low Frequency Reference Value */
4761 } B;
4762 } CMU_LFREFR_A_32B_tag;
4763
4764 typedef union { /* CMU_ISR - Interrupt Status Register */
4765 uint32_t R;
4766 struct {
4767 uint32_t:28;
4768 uint32_t FLCI_A:1; /* PLL_A Clock Frequency less than Reference Clock Interrupt */
4769#ifndef USE_FIELD_ALIASES_RGM
4770 uint32_t FHH_AI:1; /* PLL_A Clock Frequency higher than high Reference Interrupt */
4771#else
4772 uint32_t FHHI_A:1; /* deprecated name - please avoid */
4773#endif
4774 uint32_t FLLI_A:1; /* PLL_A Clock Frequency less than low Reference Interrupt */
4775 uint32_t OLRI:1; /* Oscillator Frequency less than RC Frequency Interrupt */
4776 } B;
4777 } CMU_ISR_32B_tag;
4778
4779 typedef union { /* CMU_IMR - Interrupt Mask Register */
4780 uint32_t R;
4781 } CMU_IMR_32B_tag;
4782
4783 typedef union { /* CMU_MDR - Measurement Duration Register */
4784 uint32_t R;
4785 struct {
4786 uint32_t:12;
4787 uint32_t MD:20; /* Measurment Duration Bits */
4788 } B;
4789 } CMU_MDR_32B_tag;
4790
4791
4792
4793 typedef struct CMU_struct_tag { /* start of CMU_tag */
4794 /* CMU_CSR - Control Status Register */
4795 CMU_CSR_32B_tag CSR; /* offset: 0x0000 size: 32 bit */
4796 /* CMU_FDR - Frequency Display Register */
4797 CMU_FDR_32B_tag FDR; /* offset: 0x0004 size: 32 bit */
4798 /* CMU_HFREFR_A - High Frequency Reference Register */
4799 CMU_HFREFR_A_32B_tag HFREFR_A; /* offset: 0x0008 size: 32 bit */
4800 /* CMU_LFREFR_A - Low Frequency Reference Register */
4801 CMU_LFREFR_A_32B_tag LFREFR_A; /* offset: 0x000C size: 32 bit */
4802 /* CMU_ISR - Interrupt Status Register */
4803 CMU_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */
4804 /* CMU_IMR - Interrupt Mask Register */
4805 CMU_IMR_32B_tag IMR; /* offset: 0x0014 size: 32 bit */
4806 /* CMU_MDR - Measurement Duration Register */
4807 CMU_MDR_32B_tag MDR; /* offset: 0x0018 size: 32 bit */
4808 } CMU_tag;
4809
4810
4811#define CMU0 (*(volatile CMU_tag *) 0xC3FE0100UL)
4812#define CMU1 (*(volatile CMU_tag *) 0xC3FE0120UL)
4813#define CMU2 (*(volatile CMU_tag *) 0xC3FE0140UL)
4814
4815
4816
4817/****************************************************************/
4818/* */
4819/* Module: CGM */
4820/* */
4821/****************************************************************/
4822
4823 typedef union { /* Output Clock Enable Register */
4824 uint32_t R;
4825 uint8_t BYTE[4]; /* individual bytes can be accessed */
4826 uint16_t HALF[2]; /* individual halfwords can be accessed */
4827 uint32_t WORD; /* individual words can be accessed */
4828 struct {
4829 uint32_t:31;
4830 uint32_t EN:1; /* Clock Enable Bit */
4831 } B;
4832 } CGM_OC_EN_32B_tag;
4833
4834 typedef union { /* Output Clock Division Select Register */
4835 uint32_t R;
4836 uint8_t BYTE[4]; /* individual bytes can be accessed */
4837 uint16_t HALF[2]; /* individual halfwords can be accessed */
4838 uint32_t WORD; /* individual words can be accessed */
4839 struct {
4840 uint32_t:2;
4841 uint32_t SELDIV:2; /* Output Clock Division Select */
4842 uint32_t SELCTL:4; /* Output Clock Source Selection Control */
4843 uint32_t:24;
4844 } B;
4845 } CGM_OCDS_SC_32B_tag;
4846
4847 typedef union { /* System Clock Select Status Register */
4848 uint32_t R;
4849 uint8_t BYTE[4]; /* individual bytes can be accessed */
4850 uint16_t HALF[2]; /* individual halfwords can be accessed */
4851 uint32_t WORD; /* individual words can be accessed */
4852 struct {
4853 uint32_t:4;
4854 uint32_t SELSTAT:4; /* System Clock Source Selection Status */
4855 uint32_t:24;
4856 } B;
4857 } CGM_SC_SS_32B_tag;
4858
4859 typedef union { /* System Clock Divider Configuration Register */
4860 uint32_t R;
4861 uint8_t BYTE[4]; /* individual bytes can be accessed */
4862 uint16_t HALF[2]; /* individual halfwords can be accessed */
4863 uint32_t WORD; /* individual words can be accessed */
4864 struct {
4865 uint32_t DE0:1; /* Divider 0 Enable */
4866 uint32_t:3;
4867 uint32_t DIV0:4; /* Divider 0 Value */
4868 uint32_t:24;
4869 } B;
4870 } CGM_SC_DC0_3_32B_tag;
4871
4872
4873 /* Register layout for all registers SC_DC... */
4874
4875 typedef union { /* System Clock Divider Configuration Register */
4876 uint8_t R;
4877 struct {
4878 uint8_t DE:1; /* Divider Enable */
4879 uint8_t:3;
4880 uint8_t DIV:4; /* Divider Division Value */
4881 } B;
4882 } CGM_SC_DC_8B_tag;
4883
4884
4885 /* Register layout for all registers AC_SC... */
4886
4887 typedef union { /* Auxiliary Clock Select Control Registers */
4888 uint32_t R;
4889 uint8_t BYTE[4]; /* individual bytes can be accessed */
4890 uint16_t HALF[2]; /* individual halfwords can be accessed */
4891 uint32_t WORD; /* individual words can be accessed */
4892 struct {
4893 uint32_t:4;
4894 uint32_t SELCTL:4; /* Auxliary Clock Source Selection Control */
4895 uint32_t:24;
4896 } B;
4897 } CGM_AC_SC_32B_tag;
4898
4899
4900 /* Register layout for all registers AC_DC0_3... */
4901
4902 typedef union { /* Auxiliary Clock Divider Configuration Registers */
4903 uint32_t R;
4904 struct {
4905 uint32_t DE0:1; /* Divider 0 Enable */
4906 uint32_t:3;
4907 uint32_t DIV0:4; /* Divider 0 Value */
4908 uint32_t DE1:1; /* Divider 1 Enable */
4909 uint32_t:3;
4910 uint32_t DIV1:4; /* Divider 1 Value */
4911 uint32_t:16;
4912 } B;
4913 } CGM_AC_DC0_3_32B_tag;
4914
4915
4916 typedef struct CGM_AUXCLK_struct_tag {
4917
4918 /* Auxiliary Clock Select Control Registers */
4919 CGM_AC_SC_32B_tag AC_SC; /* relative offset: 0x0000 */
4920 /* Auxiliary Clock Divider Configuration Registers */
4921 CGM_AC_DC0_3_32B_tag AC_DC0_3; /* relative offset: 0x0004 */
4922
4923 } CGM_AUXCLK_tag;
4924
4925
4926 typedef struct CGM_struct_tag { /* start of CGM_tag */
4927 OSC_CTL_32B_tag OSC_CTL; /* offset: 0x0000 size: 32 bit */
4928 int8_t CGM_reserved_0004[92];
4929 RC_CTL_32B_tag RC_CTL; /* offset: 0x0060 size: 32 bit */
4930 int8_t CGM_reserved_0064[60];
4931 PLLD_tag FMPLL[2]; /* offset: 0x00A0 (0x0020 x 2) */
4932 int8_t CGM_reserved_00E0[32];
4933 CMU_CSR_32B_tag CMU_0_CSR; /* offset: 0x0100 size: 32 bit */
4934 CMU_FDR_32B_tag CMU_0_FDR; /* offset: 0x0104 size: 32 bit */
4935 CMU_HFREFR_A_32B_tag CMU_0_HFREFR_A; /* offset: 0x0108 size: 32 bit */
4936 CMU_LFREFR_A_32B_tag CMU_0_LFREFR_A; /* offset: 0x010C size: 32 bit */
4937 CMU_ISR_32B_tag CMU_0_ISR; /* offset: 0x0110 size: 32 bit */
4938 CMU_IMR_32B_tag CMU_0_IMR; /* offset: 0x0114 size: 32 bit */
4939 CMU_MDR_32B_tag CMU_0_MDR; /* offset: 0x0118 size: 32 bit */
4940 int8_t CGM_reserved_011C[4];
4941 CMU_CSR_32B_tag CMU_1_CSR; /* offset: 0x0120 size: 32 bit */
4942 int8_t CGM_reserved_0124[4];
4943 CMU_HFREFR_A_32B_tag CMU_1_HFREFR_A; /* offset: 0x0128 size: 32 bit */
4944 CMU_LFREFR_A_32B_tag CMU_1_LFREFR_A; /* offset: 0x012C size: 32 bit */
4945 CMU_ISR_32B_tag CMU_1_ISR; /* offset: 0x0130 size: 32 bit */
4946 int8_t CGM_reserved_0134[572];
4947 union {
4948 /* Output Clock Enable Register */
4949 CGM_OC_EN_32B_tag OC_EN; /* offset: 0x0370 size: 32 bit */
4950
4951 CGM_OC_EN_32B_tag OCEN; /* deprecated - please avoid */
4952
4953 };
4954 union {
4955 /* Output Clock Division Select Register */
4956 CGM_OCDS_SC_32B_tag OCDS_SC; /* offset: 0x0374 size: 32 bit */
4957
4958 CGM_OCDS_SC_32B_tag OCDSSC; /* deprecated - please avoid */
4959
4960 };
4961 union {
4962 /* Output Clock Division Select Register */
4963 CGM_SC_SS_32B_tag SC_SS; /* offset: 0x0378 size: 32 bit */
4964
4965 CGM_SC_SS_32B_tag SCSS; /* deprecated - please avoid */
4966
4967 }; /* System Clock Select Status Register */
4968 union {
4969 struct {
4970 /* System Clock Divider Configuration Register */
4971 CGM_SC_DC_8B_tag SC_DC[2]; /* offset: 0x037C (0x0001 x 2) */
4972 int8_t CGM_reserved_037E_E0[2];
4973 };
4974
4975 struct {
4976 /* System Clock Divider Configuration Register */
4977 CGM_SC_DC_8B_tag SC_DC0; /* offset: 0x037C size: 8 bit */
4978 CGM_SC_DC_8B_tag SC_DC1; /* offset: 0x037D size: 8 bit */
4979 int8_t CGM_reserved_037E_E1[2];
4980 };
4981
4982 /* System Clock Divider Configuration Register */
4983 union {
4984 CGM_SC_DC0_3_32B_tag SC_DC0_3; /* offset: 0x037C size: 32 bit */
4985 CGM_SC_DC0_3_32B_tag SCDC; /* deprecated - please avoid */
4986 };
4987 };
4988 union {
4989 /* Register set AUXCLK */
4990 CGM_AUXCLK_tag AUXCLK[6]; /* offset: 0x0380 (0x0008 x 6) */
4991
4992 struct {
4993 union {
4994 /* Auxiliary Clock Select Control Registers */
4995 CGM_AC_SC_32B_tag AC0_SC; /* offset: 0x0380 size: 32 bit */
4996
4997 CGM_AC_SC_32B_tag AC0SC; /* deprecated - please avoid */
4998
4999 };
5000 union {
5001 /* Auxiliary Clock Divider Configuration Registers */
5002 CGM_AC_DC0_3_32B_tag AC0_DC0_3; /* offset: 0x0384 size: 32 bit */
5003
5004 CGM_AC_DC0_3_32B_tag AC0DC; /* deprecated - please avoid */
5005
5006 };
5007 union {
5008 /* Auxiliary Clock Select Control Registers */
5009 CGM_AC_SC_32B_tag AC1_SC; /* offset: 0x0388 size: 32 bit */
5010
5011 CGM_AC_SC_32B_tag AC1SC; /* deprecated - please avoid */
5012
5013 };
5014 union {
5015 /* Auxiliary Clock Divider Configuration Registers */
5016 CGM_AC_DC0_3_32B_tag AC1_DC0_3; /* offset: 0x038C size: 32 bit */
5017
5018 CGM_AC_DC0_3_32B_tag AC1DC; /* deprecated - please avoid */
5019
5020 };
5021 union {
5022 /* Auxiliary Clock Select Control Registers */
5023 CGM_AC_SC_32B_tag AC2_SC; /* offset: 0x0390 size: 32 bit */
5024
5025 CGM_AC_SC_32B_tag AC2SC; /* deprecated - please avoid */
5026
5027 };
5028 union {
5029 /* Auxiliary Clock Divider Configuration Registers */
5030 CGM_AC_DC0_3_32B_tag AC2_DC0_3; /* offset: 0x0394 size: 32 bit */
5031
5032 CGM_AC_DC0_3_32B_tag AC2DC; /* deprecated - please avoid */
5033
5034 };
5035 union {
5036 /* Auxiliary Clock Select Control Registers */
5037 CGM_AC_SC_32B_tag AC3_SC; /* offset: 0x0398 size: 32 bit */
5038
5039 CGM_AC_SC_32B_tag AC3SC; /* deprecated - please avoid */
5040
5041 };
5042 union {
5043 /* Auxiliary Clock Divider Configuration Registers */
5044 CGM_AC_DC0_3_32B_tag AC3_DC0_3; /* offset: 0x039C size: 32 bit */
5045
5046 CGM_AC_DC0_3_32B_tag AC3DC; /* deprecated - please avoid */
5047
5048 };
5049 union {
5050 /* Auxiliary Clock Select Control Registers */
5051 CGM_AC_SC_32B_tag AC4_SC; /* offset: 0x03A0 size: 32 bit */
5052
5053 CGM_AC_SC_32B_tag AC4SC; /* deprecated - please avoid */
5054
5055 };
5056 union {
5057 /* Auxiliary Clock Divider Configuration Registers */
5058 CGM_AC_DC0_3_32B_tag AC4_DC0_3; /* offset: 0x03A4 size: 32 bit */
5059
5060 CGM_AC_DC0_3_32B_tag AC4DC; /* deprecated - please avoid */
5061 };
5062 union {
5063 /* Auxiliary Clock Select Control Registers */
5064 CGM_AC_SC_32B_tag AC5_SC; /* offset: 0x03A8 size: 32 bit */
5065
5066 CGM_AC_SC_32B_tag AC5SC; /* deprecated - please avoid */
5067
5068 };
5069 union {
5070 /* Auxiliary Clock Divider Configuration Registers */
5071 CGM_AC_DC0_3_32B_tag AC5_DC0_3; /* offset: 0x03AC size: 32 bit */
5072
5073 CGM_AC_DC0_3_32B_tag AC5DC; /* deprecated - please avoid */
5074
5075 };
5076 };
5077
5078 };
5079 } CGM_tag;
5080
5081
5082#define CGM (*(volatile CGM_tag *) 0xC3FE0000UL)
5083
5084
5085
5086/****************************************************************/
5087/* */
5088/* Module: RGM */
5089/* */
5090/****************************************************************/
5091
5092 typedef union { /* Functional Event Status Register */
5093 uint16_t R;
5094 struct {
5095 uint16_t F_EXR:1; /* Flag for External Reset */
5096 uint16_t F_FCCU_HARD:1; /* Flag for FCCU hard reaction request */
5097 uint16_t F_FCCU_SOFT:1; /* Flag for FCCU soft reaction request */
5098 uint16_t F_ST_DONE:1; /* Flag for self-test completed */
5099#ifndef USE_FIELD_ALIASES_RGM
5100 uint16_t F_CMU12_FHL:1; /* Flag for CMU 1/2 clock freq. too high/low */
5101#else
5102 uint16_t F_CMU1_FHL:1; /* deprecated name - please avoid */
5103#endif
5104 uint16_t F_FL_ECC_RCC:1; /* Flag for Flash, ECC, or lock-step error */
5105 uint16_t F_PLL1:1; /* Flag for PLL1 fail */
5106 uint16_t F_SWT:1; /* Flag for Software Watchdog Timer */
5107 uint16_t F_FCCU_SAFE:1; /* Flag for FCCU SAFE mode request */
5108 uint16_t F_CMU0_FHL:1; /* Flag for CMU 0 clock freq. too high/low */
5109 uint16_t F_CMU0_OLR:1; /* Flag for oscillator freq. too low */
5110 uint16_t F_PLL0:1; /* Flag for PLL0 fail */
5111 uint16_t F_CWD:1; /* Flag for Core Watchdog Reset */
5112 uint16_t F_SOFT:1; /* Flag for software reset */
5113 uint16_t F_CORE:1; /* Flag for core reset */
5114 uint16_t F_JTAG:1; /* Flag for JTAG initiated reset */
5115 } B;
5116 } RGM_FES_16B_tag;
5117
5118 typedef union { /* Destructive Event Status Register */
5119 uint16_t R;
5120 struct {
5121#ifndef USE_FIELD_ALIASES_RGM
5122 uint16_t F_POR:1; /* Flag for Power on Reset */
5123#else
5124 uint16_t POR:1; /* deprecated name - please avoid */
5125#endif
5126 uint16_t:7;
5127 uint16_t F_COMP:1; /* Flag for comparator error */
5128 uint16_t F_LVD27_IO:1; /* Flag for 2.7V low-voltage detected (I/O) */
5129 uint16_t F_LVD27_FLASH:1; /* Flag for 2.7V low-voltage detected (Flash) */
5130 uint16_t F_LVD27_VREG:1; /* Flag for 2.7V low-voltage detected (VREG) */
5131 uint16_t:2;
5132 uint16_t F_HVD12:1; /* Flag for 1.2V high-voltage detected */
5133#ifndef USE_FIELD_ALIASES_RGM
5134 uint16_t F_LVD12:1; /* Flag for 1.2V low-voltage detected */
5135#else
5136 uint16_t F_LVD12_PD0:1; /* deprecated name - please avoid */
5137#endif
5138 } B;
5139 } RGM_DES_16B_tag;
5140
5141 typedef union { /* Functional Event Reset Disable Register */
5142 uint16_t R;
5143 struct {
5144 uint16_t D_EXR:1; /* Disable External Pad Event Reset */
5145 uint16_t D_FCCU_HARD:1; /* Disable FCCU hard reaction request */
5146 uint16_t D_FCCU_SOFT:1; /* Disable FCCU soft reaction request */
5147 uint16_t D_ST_DONE:1; /* Disable self-test completed */
5148#ifndef USE_FIELD_ALIASES_RGM
5149 uint16_t D_CMU12_FHL:1; /* Disable CMU 1/2 clock freq. too high/low */
5150#else
5151 uint16_t D_CMU1_FHL:1; /* deprecated name - please avoid */
5152#endif
5153 uint16_t D_FL_ECC_RCC:1; /* Disable Flash, ECC, or lock-step error */
5154 uint16_t D_PLL1:1; /* Disable PLL1 fail */
5155 uint16_t D_SWT:1; /* Disable Software Watchdog Timer */
5156 uint16_t D_FCCU_SAFE:1; /* Disable FCCU SAFE mode request */
5157 uint16_t D_CMU0_FHL:1; /* Disable CMU 0 clock freq. too high/low */
5158 uint16_t D_CMU0_OLR:1; /* Disable oscillator freq. too low */
5159 uint16_t D_PLL0:1; /* Disable PLL0 fail */
5160 uint16_t D_CWD:1; /* Disable Core Watchdog Reset */
5161 uint16_t D_SOFT:1; /* Disable software reset */
5162 uint16_t D_CORE:1; /* Disable core reset */
5163 uint16_t D_JTAG:1; /* Disable JTAG initiated reset */
5164 } B;
5165 } RGM_FERD_16B_tag;
5166
5167 typedef union { /* Destructive Event Reset Disable Register */
5168 uint16_t R;
5169 struct {
5170 uint16_t:8;
5171 uint16_t D_COMP:1; /* Disable comparator error */
5172 uint16_t D_LVD27_IO:1; /* Disable 2.7V low-voltage detected (I/O) */
5173 uint16_t D_LVD27_FLASH:1; /* Disable 2.7V low-voltage detected (Flash) */
5174 uint16_t D_LVD27_VREG:1; /* Disable 2.7V low-voltage detected (VREG) */
5175 uint16_t:2;
5176 uint16_t D_HVD12:1; /* Disable 1.2V high-voltage detected */
5177#ifndef USE_FIELD_ALIASES_RGM
5178 uint16_t D_LVD12:1; /* Disable 1.2V low-voltage detected */
5179#else
5180 uint16_t D_LVD12_PD0:1; /* deprecated name - please avoid */
5181#endif
5182 } B;
5183 } RGM_DERD_16B_tag;
5184
5185 typedef union { /* Functional Event Alternate Request Register */
5186 uint16_t R;
5187 struct {
5188 uint16_t:4;
5189#ifndef USE_FIELD_ALIASES_RGM
5190 uint16_t AR_CMU12_FHL:1; /* Alternate Request for CMU1/2 clock freq. too high/low */
5191#else
5192 uint16_t AR_CMU1_FHL:1; /* deprecated name - please avoid */
5193#endif
5194 uint16_t:1;
5195 uint16_t AR_PLL1:1; /* Alternate Request for PLL1 fail */
5196 uint16_t:1;
5197 uint16_t AR_FCCU_SAVE:1; /* Alternate Request for FCCU SAFE mode request */
5198 uint16_t AR_CMU0_FHL:1; /* Alternate Request for CMU0 clock freq.
5199 too high/low */
5200 uint16_t AR_CMU0_OLR:1; /* Alternate Request for oscillator freq. too low */
5201 uint16_t AR_PLL0:1; /* Alternate Request for PLL0 fail */
5202 uint16_t AR_CWD:1; /* Alternate Request for core watchdog reset */
5203 uint16_t:3;
5204 } B;
5205 } RGM_FEAR_16B_tag;
5206
5207 typedef union { /* Functional Event Short Sequence Register */
5208 uint16_t R;
5209 struct {
5210 uint16_t SS_EXR:1; /* Short Sequence for External Reset */
5211 uint16_t SS_FCCU_HARD:1; /* Short Sequence for FCCU hard reaction request */
5212 uint16_t SS_FCCU_SOFT:1; /* Short Sequence for FCCU soft reaction request */
5213 uint16_t SS_ST_DONE:1; /* Short Sequence for self-test completed */
5214#ifndef USE_FIELD_ALIASES_RGM
5215 uint16_t SS_CMU12_FHL:1; /* Short Sequence for CMU 1/2 clock freq. too high/low */
5216#else
5217 uint16_t SS_CMU1_FHL:1; /* deprecated name - please avoid */
5218#endif
5219 uint16_t SS_FL_ECC_RCC:1; /* Short Sequence for Flash, ECC, or lock-step error */
5220 uint16_t SS_PLL1:1; /* Short Sequence for PLL1 fail */
5221 uint16_t SS_SWT:1; /* Short Sequence for Software Watchdog Timer */
5222 uint16_t:1;
5223 uint16_t SS_CMU0_FHL:1; /* Short Sequence for CMU 0 clock freq. too high/low */
5224 uint16_t SS_CMU0_OLR:1; /* Short Sequence for oscillator freq. too low */
5225 uint16_t SS_PLL0:1; /* Short Sequence for PLL0 fail */
5226 uint16_t SS_CWD:1; /* Short Sequence for Core Watchdog Reset */
5227 uint16_t SS_SOFT:1; /* Short Sequence for software reset */
5228 uint16_t SS_CORE:1; /* Short Sequence for core reset */
5229 uint16_t SS_JTAG:1; /* Short Sequence for JTAG initiated reset */
5230 } B;
5231 } RGM_FESS_16B_tag;
5232
5233 typedef union { /* Functional Bidirectional Reset Enable Register */
5234 uint16_t R;
5235 struct {
5236 uint16_t BE_EXR:1; /* Bidirectional Reset Enable for External Reset */
5237 uint16_t BE_FCCU_HARD:1; /* Bidirectional Reset Enable for FCCU hard reaction request */
5238 uint16_t BE_FCCU_SOFT:1; /* Bidirectional Reset Enable for FCCU soft reaction request */
5239 uint16_t BE_ST_DONE:1; /* Bidirectional Reset Enable for self-test completed */
5240#ifndef USE_FIELD_ALIASES_RGM
5241 uint16_t BE_CMU12_FHL:1; /* Bidirectional Reset Enable for CMU 1/2 clock freq. too high/low */
5242#else
5243 uint16_t BE_CMU1_FHL:1; /* deprecated name - please avoid */
5244#endif
5245 uint16_t BE_FL_ECC_RCC:1; /* Bidirectional Reset Enable for Flash, ECC, or lock-step error */
5246 uint16_t BE_PLL1:1; /* Bidirectional Reset Enable for PLL1 fail */
5247 uint16_t BE_SWT:1; /* Bidirectional Reset Enable for Software Watchdog Timer */
5248 uint16_t:1;
5249 uint16_t BE_CMU0_FHL:1; /* Bidirectional Reset Enable for CMU 0 clock freq. too high/low */
5250 uint16_t BE_CMU0_OLR:1; /* Bidirectional Reset Enable for oscillator freq. too low */
5251 uint16_t BE_PLL0:1; /* Bidirectional Reset Enable for PLL0 fail */
5252 uint16_t BE_CWD:1; /* Bidirectional Reset Enable for Core Watchdog Reset */
5253 uint16_t BE_SOFT:1; /* Bidirectional Reset Enable for software reset */
5254 uint16_t BE_CORE:1; /* Bidirectional Reset Enable for core reset */
5255 uint16_t BE_JTAG:1; /* Bidirectional Reset Enable for JTAG initiated reset */
5256 } B;
5257 } RGM_FBRE_16B_tag;
5258
5259
5260
5261 typedef struct RGM_struct_tag { /* start of RGM_tag */
5262 /* Functional Event Status Register */
5263 RGM_FES_16B_tag FES; /* offset: 0x0000 size: 16 bit */
5264 /* Destructive Event Status Register */
5265 RGM_DES_16B_tag DES; /* offset: 0x0002 size: 16 bit */
5266 /* Functional Event Reset Disable Register */
5267 RGM_FERD_16B_tag FERD; /* offset: 0x0004 size: 16 bit */
5268 /* Destructive Event Reset Disable Register */
5269 RGM_DERD_16B_tag DERD; /* offset: 0x0006 size: 16 bit */
5270 int8_t RGM_reserved_0008[8];
5271 /* Functional Event Alternate Request Register */
5272 RGM_FEAR_16B_tag FEAR; /* offset: 0x0010 size: 16 bit */
5273 int8_t RGM_reserved_0012[6];
5274 /* Functional Event Short Sequence Register */
5275 RGM_FESS_16B_tag FESS; /* offset: 0x0018 size: 16 bit */
5276 int8_t RGM_reserved_001A[2];
5277 /* Functional Bidirectional Reset Enable Register */
5278 RGM_FBRE_16B_tag FBRE; /* offset: 0x001C size: 16 bit */
5279 } RGM_tag;
5280
5281
5282#define RGM (*(volatile RGM_tag *) 0xC3FE4000UL)
5283
5284
5285
5286/****************************************************************/
5287/* */
5288/* Module: PCU */
5289/* */
5290/****************************************************************/
5291
5292
5293 /* Register layout for all registers PCONF... */
5294
5295 typedef union { /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */
5296 uint32_t R;
5297 struct {
5298 uint32_t:18;
5299 uint32_t STBY0:1; /* Power domain control during STBY0 */
5300 uint32_t:2;
5301 uint32_t STOP0:1; /* Power domain control during STOP0 */
5302 uint32_t:1;
5303 uint32_t HALT0:1; /* Power domain control during HALT0 */
5304 uint32_t RUN3:1; /* Power domain control during RUN3 */
5305 uint32_t RUN2:1; /* Power domain control during RUN2 */
5306 uint32_t RUN1:1; /* Power domain control during RUN1 */
5307 uint32_t RUN0:1; /* Power domain control during RUN0 */
5308 uint32_t DRUN:1; /* Power domain control during DRUN */
5309 uint32_t SAFE:1; /* Power domain control during SAFE */
5310 uint32_t TEST:1; /* Power domain control during TEST */
5311 uint32_t RST:1; /* Power domain control during RST */
5312 } B;
5313 } PCU_PCONF_32B_tag;
5314
5315 typedef union { /* PCU_PSTAT - Power Domain Status Register */
5316 uint32_t R;
5317 struct {
5318 uint32_t:16;
5319 uint32_t PD15:1; /* Power Status for Power Domain 15 */
5320 uint32_t PD14:1; /* Power Status for Power Domain 14 */
5321 uint32_t PD13:1; /* Power Status for Power Domain 13 */
5322 uint32_t PD12:1; /* Power Status for Power Domain 12 */
5323 uint32_t PD11:1; /* Power Status for Power Domain 11 */
5324 uint32_t PD10:1; /* Power Status for Power Domain 10 */
5325 uint32_t PD9:1; /* Power Status for Power Domain 9 */
5326 uint32_t PD8:1; /* Power Status for Power Domain 8 */
5327 uint32_t PD7:1; /* Power Status for Power Domain 7 */
5328 uint32_t PD6:1; /* Power Status for Power Domain 6 */
5329 uint32_t PD5:1; /* Power Status for Power Domain 5 */
5330 uint32_t PD4:1; /* Power Status for Power Domain 4 */
5331 uint32_t PD3:1; /* Power Status for Power Domain 3 */
5332 uint32_t PD2:1; /* Power Status for Power Domain 2 */
5333 uint32_t PD1:1; /* Power Status for Power Domain 1 */
5334 uint32_t PD0:1; /* Power Status for Power Domain 0 */
5335 } B;
5336 } PCU_PSTAT_32B_tag;
5337
5338
5339
5340 typedef struct PCU_struct_tag { /* start of PCU_tag */
5341 union {
5342 /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */
5343 PCU_PCONF_32B_tag PCONF[16]; /* offset: 0x0000 (0x0004 x 16) */
5344
5345 struct {
5346 /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */
5347 PCU_PCONF_32B_tag PCONF0; /* offset: 0x0000 size: 32 bit */
5348 PCU_PCONF_32B_tag PCONF1; /* offset: 0x0004 size: 32 bit */
5349 PCU_PCONF_32B_tag PCONF2; /* offset: 0x0008 size: 32 bit */
5350 PCU_PCONF_32B_tag PCONF3; /* offset: 0x000C size: 32 bit */
5351 PCU_PCONF_32B_tag PCONF4; /* offset: 0x0010 size: 32 bit */
5352 PCU_PCONF_32B_tag PCONF5; /* offset: 0x0014 size: 32 bit */
5353 PCU_PCONF_32B_tag PCONF6; /* offset: 0x0018 size: 32 bit */
5354 PCU_PCONF_32B_tag PCONF7; /* offset: 0x001C size: 32 bit */
5355 PCU_PCONF_32B_tag PCONF8; /* offset: 0x0020 size: 32 bit */
5356 PCU_PCONF_32B_tag PCONF9; /* offset: 0x0024 size: 32 bit */
5357 PCU_PCONF_32B_tag PCONF10; /* offset: 0x0028 size: 32 bit */
5358 PCU_PCONF_32B_tag PCONF11; /* offset: 0x002C size: 32 bit */
5359 PCU_PCONF_32B_tag PCONF12; /* offset: 0x0030 size: 32 bit */
5360 PCU_PCONF_32B_tag PCONF13; /* offset: 0x0034 size: 32 bit */
5361 PCU_PCONF_32B_tag PCONF14; /* offset: 0x0038 size: 32 bit */
5362 PCU_PCONF_32B_tag PCONF15; /* offset: 0x003C size: 32 bit */
5363 };
5364
5365 };
5366 /* PCU_PSTAT - Power Domain Status Register */
5367 PCU_PSTAT_32B_tag PSTAT; /* offset: 0x0040 size: 32 bit */
5368 } PCU_tag;
5369
5370
5371#define PCU (*(volatile PCU_tag *) 0xC3FE8000UL)
5372
5373
5374
5375/****************************************************************/
5376/* */
5377/* Module: PMUCTRL */
5378/* */
5379/****************************************************************/
5380
5381 typedef union { /* PMUCTRL_STATHVD - PMU Status Register HVD */
5382 uint32_t R;
5383 struct {
5384 uint32_t:11;
5385 uint32_t HVDT_LPB:5; /* High Voltage Detector trimming bits LPB bus */
5386 uint32_t:6;
5387 uint32_t HVD_M:1; /* High Voltage Detector Main */
5388 uint32_t HVD_B:1; /* High Voltage Detector Backup */
5389 uint32_t:4;
5390 uint32_t HVD_LP:4; /* High Voltage Detector trimming bits LP bus */
5391 } B;
5392 } PMUCTRL_STATHVD_32B_tag;
5393
5394 typedef union { /* PMUCTRL_STATLVD - PMU Status Register LVD */
5395 uint32_t R;
5396 struct {
5397 uint32_t:11;
5398 uint32_t LVDT_LPB:5; /* Ligh Voltage Detector trimming bits LPB bus */
5399 uint32_t:6;
5400 uint32_t LVD_M:1; /* Ligh Voltage Detector Main */
5401 uint32_t LVD_B:1; /* Ligh Voltage Detector Backup */
5402 uint32_t:4;
5403 uint32_t LVD_LP:4; /* Ligh Voltage Detector trimming bits LP bus */
5404 } B;
5405 } PMUCTRL_STATLVD_32B_tag;
5406
5407 typedef union { /* PMUCTRL_STATIREG - PMU Status Register IREG */
5408 uint32_t R;
5409 struct {
5410 uint32_t:28;
5411 uint32_t IIREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */
5412 } B;
5413 } PMUCTRL_STATIREG_32B_tag;
5414
5415 typedef union { /* PMUCTRL_STATEREG - PMU Status Register EREG */
5416 uint32_t R;
5417 struct {
5418 uint32_t:28;
5419 uint32_t EEREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */
5420 } B;
5421 } PMUCTRL_STATEREG_32B_tag;
5422
5423 typedef union { /* PMUCTRL_STATUS - PMU Status Register STATUS */
5424 uint32_t R;
5425 struct {
5426 uint32_t EBMM:1; /* External Ballast Management Mode */
5427 uint32_t AEBD:1; /* Automatic External Ballast Detection */
5428 uint32_t ENPN:1; /* External NPN status flag */
5429 uint32_t:13;
5430 uint32_t CTB:2; /* Configuration Trace Bits */
5431 uint32_t:6;
5432 uint32_t CBS:4; /* Current BIST Status */
5433 uint32_t CPCS:4; /* Current Pmu Configuration Status */
5434 } B;
5435 } PMUCTRL_STATUS_32B_tag;
5436
5437 typedef union { /* PMUCTRL_CTRL - PMU Control Register */
5438 uint32_t R;
5439 struct {
5440 uint32_t:30;
5441 uint32_t SILHT:2; /* Start Idle or LVD or HVD BIST Test */
5442 } B;
5443 } PMUCTRL_CTRL_32B_tag;
5444
5445 typedef union { /* PMUCTRL_MASKF - PMU Mask Fault Register */
5446 uint32_t R;
5447 struct {
5448 uint32_t MF_BB:4; /* Mask Fault Bypass Balast */
5449 uint32_t:28;
5450 } B;
5451 } PMUCTRL_MASKF_32B_tag;
5452
5453 typedef union { /* PMUCTRL_FAULT - PMU Fault Monitor Register */
5454 uint32_t R;
5455 struct {
5456 uint32_t BB_LV:4; /* Bypass Ballast Low Voltage */
5457 uint32_t:9;
5458 uint32_t FLNCF:1; /* FLash voltage monitor Non Critical Fault */
5459 uint32_t IONCF:1; /* IO voltage monitor Non Critical Fault */
5460 uint32_t RENCF:1; /* REgulator voltage monitor Non Critical Fault */
5461 uint32_t:13;
5462 uint32_t LHCF:1; /* Low High voltage detector Critical Fault */
5463 uint32_t LNCF:1; /* Low voltage detector Non Critical Fault */
5464 uint32_t HNCF:1; /* High voltage detector Non Critical Fault */
5465 } B;
5466 } PMUCTRL_FAULT_32B_tag;
5467
5468 typedef union { /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */
5469 uint32_t R;
5470 struct {
5471 uint32_t:10;
5472 uint32_t MFVMP:1; /* Main Flash Voltage Monitor interrupt Pending */
5473 uint32_t BFVMP:1; /* Backup Flash Voltage Monitor interrupt Pending */
5474 uint32_t MIVMP:1; /* MAin IO Voltage Monitor interrupt Pending */
5475 uint32_t BIVMP:1; /* Backup IO Voltage Monitor interrupt Pending */
5476 uint32_t MRVMP:1; /* Main Regulator Voltage Monitor interrupt Pending */
5477 uint32_t BRVMP:1; /* Backup Regulator Voltage Monitor interrupt Pending */
5478 uint32_t:12;
5479 uint32_t MLVDP:1; /* Main Low Voltage Detector error interrupt Pending */
5480 uint32_t BLVDP:1; /* Backup Low Voltage Detector error interrupt Pending */
5481 uint32_t MHVDP:1; /* Main High Voltage Detector error interrupt Pending */
5482 uint32_t BHVDP:1; /* Backup High Voltage Detector error interrupt Pending */
5483 } B;
5484 } PMUCTRL_IRQS_32B_tag;
5485
5486 typedef union { /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */
5487 uint32_t R;
5488 struct {
5489 uint32_t:10;
5490 uint32_t MFVME:1; /* Main Flash Voltage Monitor interrupt Enable */
5491 uint32_t BFVME:1; /* Backup Flash Voltage Monitor interrupt Enable */
5492 uint32_t MIVME:1; /* MAin IO Voltage Monitor interrupt Enable */
5493 uint32_t BIVME:1; /* Backup IO Voltage Monitor interrupt Enable */
5494 uint32_t MRVME:1; /* Main Regulator Voltage Monitor interrupt Enable */
5495 uint32_t BRVME:1; /* Backup Regulator Voltage Monitor interrupt Enable */
5496 uint32_t:12;
5497 uint32_t MLVDE:1; /* Main Low Voltage Detector error interrupt Enable */
5498 uint32_t BLVDE:1; /* Backup Low Voltage Detector error interrupt Enable */
5499 uint32_t MHVDE:1; /* Main High Voltage Detector error interrupt Enable */
5500 uint32_t BHVDE:1; /* Backup High Voltage Detector error interrupt Enable */
5501 } B;
5502 } PMUCTRL_IRQE_32B_tag;
5503
5504
5505
5506 typedef struct PMUCTRL_struct_tag { /* start of PMUCTRL_tag */
5507 int8_t PMUCTRL_reserved_0000[4];
5508 /* PMUCTRL_STATHVD - PMU Status Register HVD */
5509 PMUCTRL_STATHVD_32B_tag STATHVD; /* offset: 0x0004 size: 32 bit */
5510 /* PMUCTRL_STATLVD - PMU Status Register LVD */
5511 PMUCTRL_STATLVD_32B_tag STATLVD; /* offset: 0x0008 size: 32 bit */
5512 int8_t PMUCTRL_reserved_000C[20];
5513 /* PMUCTRL_STATIREG - PMU Status Register IREG */
5514 PMUCTRL_STATIREG_32B_tag STATIREG; /* offset: 0x0020 size: 32 bit */
5515 /* PMUCTRL_STATEREG - PMU Status Register EREG */
5516 PMUCTRL_STATEREG_32B_tag STATEREG; /* offset: 0x0024 size: 32 bit */
5517 int8_t PMUCTRL_reserved_0028[24];
5518 /* PMUCTRL_STATUS - PMU Status Register STATUS */
5519 PMUCTRL_STATUS_32B_tag STATUS; /* offset: 0x0040 size: 32 bit */
5520 /* PMUCTRL_CTRL - PMU Control Register */
5521 PMUCTRL_CTRL_32B_tag CTRL; /* offset: 0x0044 size: 32 bit */
5522 int8_t PMUCTRL_reserved_0048[40];
5523 /* PMUCTRL_MASKF - PMU Mask Fault Register */
5524 PMUCTRL_MASKF_32B_tag MASKF; /* offset: 0x0070 size: 32 bit */
5525 /* PMUCTRL_FAULT - PMU Fault Monitor Register */
5526 PMUCTRL_FAULT_32B_tag FAULT; /* offset: 0x0074 size: 32 bit */
5527 /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */
5528 PMUCTRL_IRQS_32B_tag IRQS; /* offset: 0x0078 size: 32 bit */
5529 /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */
5530 PMUCTRL_IRQE_32B_tag IRQE; /* offset: 0x007C size: 32 bit */
5531 } PMUCTRL_tag;
5532
5533
5534#define PMUCTRL (*(volatile PMUCTRL_tag *) 0xC3FE8080UL)
5535
5536
5537
5538/****************************************************************/
5539/* */
5540/* Module: PIT_RTI */
5541/* */
5542/****************************************************************/
5543
5544 typedef union { /* PIT_RTI_PITMCR - PIT Module Control Register */
5545 uint32_t R;
5546 struct {
5547 uint32_t:30;
5548 uint32_t MDIS:1; /* Module Disable. Disable the module clock */
5549 uint32_t FRZ:1; /* Freeze. Allows the timers to be stoppedwhen the device enters debug mode */
5550 } B;
5551 } PIT_RTI_PITMCR_32B_tag;
5552
5553
5554 /* Register layout for all registers LDVAL... */
5555
5556 typedef union { /* PIT_RTI_LDVAL - Timer Load Value Register */
5557 uint32_t R;
5558 struct {
5559 uint32_t TSV:32; /* Time Start Value Bits */
5560 } B;
5561 } PIT_RTI_LDVAL_32B_tag;
5562
5563
5564 /* Register layout for all registers CVAL... */
5565
5566 typedef union { /* PIT_RTI_CVAL - Current Timer Value Register */
5567 uint32_t R;
5568 struct {
5569 uint32_t TVL:32; /* Current Timer Value Bits */
5570 } B;
5571 } PIT_RTI_CVAL_32B_tag;
5572
5573
5574 /* Register layout for all registers TCTRL... */
5575
5576 typedef union { /* PIT_RTI_TCTRL - Timer Control Register */
5577 uint32_t R;
5578 struct {
5579 uint32_t:30;
5580 uint32_t TIE:1; /* Timer Interrupt Enable Bit */
5581 uint32_t TEN:1; /* Timer Enable Bit */
5582 } B;
5583 } PIT_RTI_TCTRL_32B_tag;
5584
5585
5586 /* Register layout for all registers TFLG... */
5587
5588 typedef union { /* PIT_RTI_TFLG - Timer Flag Register */
5589 uint32_t R;
5590 struct {
5591 uint32_t:31;
5592 uint32_t TIF:1; /* Timer Interrupt Flag Bit */
5593 } B;
5594 } PIT_RTI_TFLG_32B_tag;
5595
5596
5597 typedef struct PIT_RTI_CHANNEL_struct_tag {
5598
5599 /* PIT_RTI_LDVAL - Timer Load Value Register */
5600 PIT_RTI_LDVAL_32B_tag LDVAL; /* relative offset: 0x0000 */
5601 /* PIT_RTI_CVAL - Current Timer Value Register */
5602 PIT_RTI_CVAL_32B_tag CVAL; /* relative offset: 0x0004 */
5603 /* PIT_RTI_TCTRL - Timer Control Register */
5604 PIT_RTI_TCTRL_32B_tag TCTRL; /* relative offset: 0x0008 */
5605 /* PIT_RTI_TFLG - Timer Flag Register */
5606 PIT_RTI_TFLG_32B_tag TFLG; /* relative offset: 0x000C */
5607
5608 } PIT_RTI_CHANNEL_tag;
5609
5610
5611 typedef struct PIT_RTI_struct_tag { /* start of PIT_RTI_tag */
5612 /* PIT_RTI_PITMCR - PIT Module Control Register */
5613 PIT_RTI_PITMCR_32B_tag PITMCR; /* offset: 0x0000 size: 32 bit */
5614 int8_t PIT_RTI_reserved_0004_C[252];
5615 union {
5616 /* Register set CHANNEL */
5617 PIT_RTI_CHANNEL_tag CHANNEL[4]; /* offset: 0x0100 (0x0010 x 4) */
5618
5619 PIT_RTI_CHANNEL_tag CH[4]; /* offset: 0x0100 (0x0010 x 4) */
5620
5621 struct {
5622 /* PIT_RTI_LDVAL - Timer Load Value Register */
5623 PIT_RTI_LDVAL_32B_tag LDVAL0; /* offset: 0x0100 size: 32 bit */
5624 /* PIT_RTI_CVAL - Current Timer Value Register */
5625 PIT_RTI_CVAL_32B_tag CVAL0; /* offset: 0x0104 size: 32 bit */
5626 /* PIT_RTI_TCTRL - Timer Control Register */
5627 PIT_RTI_TCTRL_32B_tag TCTRL0; /* offset: 0x0108 size: 32 bit */
5628 /* PIT_RTI_TFLG - Timer Flag Register */
5629 PIT_RTI_TFLG_32B_tag TFLG0; /* offset: 0x010C size: 32 bit */
5630 /* PIT_RTI_LDVAL - Timer Load Value Register */
5631 PIT_RTI_LDVAL_32B_tag LDVAL1; /* offset: 0x0110 size: 32 bit */
5632 /* PIT_RTI_CVAL - Current Timer Value Register */
5633 PIT_RTI_CVAL_32B_tag CVAL1; /* offset: 0x0114 size: 32 bit */
5634 /* PIT_RTI_TCTRL - Timer Control Register */
5635 PIT_RTI_TCTRL_32B_tag TCTRL1; /* offset: 0x0118 size: 32 bit */
5636 /* PIT_RTI_TFLG - Timer Flag Register */
5637 PIT_RTI_TFLG_32B_tag TFLG1; /* offset: 0x011C size: 32 bit */
5638 /* PIT_RTI_LDVAL - Timer Load Value Register */
5639 PIT_RTI_LDVAL_32B_tag LDVAL2; /* offset: 0x0120 size: 32 bit */
5640 /* PIT_RTI_CVAL - Current Timer Value Register */
5641 PIT_RTI_CVAL_32B_tag CVAL2; /* offset: 0x0124 size: 32 bit */
5642 /* PIT_RTI_TCTRL - Timer Control Register */
5643 PIT_RTI_TCTRL_32B_tag TCTRL2; /* offset: 0x0128 size: 32 bit */
5644 /* PIT_RTI_TFLG - Timer Flag Register */
5645 PIT_RTI_TFLG_32B_tag TFLG2; /* offset: 0x012C size: 32 bit */
5646 /* PIT_RTI_LDVAL - Timer Load Value Register */
5647 PIT_RTI_LDVAL_32B_tag LDVAL3; /* offset: 0x0130 size: 32 bit */
5648 /* PIT_RTI_CVAL - Current Timer Value Register */
5649 PIT_RTI_CVAL_32B_tag CVAL3; /* offset: 0x0134 size: 32 bit */
5650 /* PIT_RTI_TCTRL - Timer Control Register */
5651 PIT_RTI_TCTRL_32B_tag TCTRL3; /* offset: 0x0138 size: 32 bit */
5652 /* PIT_RTI_TFLG - Timer Flag Register */
5653 PIT_RTI_TFLG_32B_tag TFLG3; /* offset: 0x013C size: 32 bit */
5654 };
5655
5656 };
5657 } PIT_RTI_tag;
5658
5659
5660#define PIT_RTI (*(volatile PIT_RTI_tag *) 0xC3FF0000UL)
5661
5662
5663
5664/****************************************************************/
5665/* */
5666/* Module: ADC */
5667/* */
5668/****************************************************************/
5669
5670 typedef union { /* module configuration register */
5671 uint32_t R;
5672 struct {
5673 uint32_t OWREN:1; /* Overwrite enable */
5674 uint32_t WLSIDE:1; /* Write Left/right Alligned */
5675 uint32_t MODE:1; /* One Shot/Scan Mode Selectiom */
5676 uint32_t EDGLEV:1; /* edge or level selection for external start trigger */
5677 uint32_t TRGEN:1; /* external trigger enable */
5678 uint32_t EDGE:1; /* start trigger egde /level detection */
5679 uint32_t XSTRTEN:1; /* EXTERNAL START ENABLE */
5680 uint32_t NSTART:1; /* start normal conversion */
5681 uint32_t:1;
5682 uint32_t JTRGEN:1; /* Injectin External Trigger Enable */
5683 uint32_t JEDGE:1; /* start trigger egde /level detection for injected */
5684 uint32_t JSTART:1; /* injected conversion start */
5685 uint32_t:2;
5686 uint32_t CTUEN:1; /* CTU enabaled */
5687 uint32_t:8;
5688 uint32_t ADCLKSEL:1; /* Select which clock for device */
5689 uint32_t ABORTCHAIN:1; /* abort chain conversion */
5690 uint32_t ABORT:1; /* abort current conversion */
5691#ifndef USE_FIELD_ALIASES_ADC
5692 uint32_t ACKO:1; /* Auto Clock Off Enable */
5693#else
5694 uint32_t ACK0:1; /* deprecated name - please avoid */
5695#endif
5696 uint32_t OFFREFRESH:1; /* offset phase selection */
5697 uint32_t OFFCANC:1; /* offset phase cancellation selection */
5698 uint32_t:2;
5699 uint32_t PWDN:1; /* Power Down Enable */
5700 } B;
5701 } ADC_MCR_32B_tag;
5702
5703 typedef union { /* module status register */
5704 uint32_t R;
5705 struct {
5706 uint32_t:7;
5707 uint32_t NSTART:1; /* normal conversion status */
5708 uint32_t JABORT:1; /* Injection chain abort status */
5709 uint32_t:2;
5710 uint32_t JSTART:1; /* Injection Start status */
5711 uint32_t:3;
5712 uint32_t CTUSTART:1; /* ctu start status */
5713 uint32_t CHADDR:7; /* which address conv is goin on */
5714 uint32_t:3;
5715#ifndef USE_FIELD_ALIASES_ADC
5716 uint32_t ACKO:1; /* Auto Clock Off Enable status */
5717#else
5718 uint32_t ACK0:1; /* deprecated name - please avoid */
5719#endif
5720 uint32_t OFFREFRESH:1; /* offset refresh status */
5721 uint32_t OFFCANC:1; /* offset phase cancellation status */
5722 uint32_t ADCSTATUS:3; /* status of ADC FSM */
5723 } B;
5724 } ADC_MSR_32B_tag;
5725
5726 typedef union { /* Interrupt status register */
5727 uint32_t R;
5728 struct {
5729 uint32_t:25;
5730 uint32_t OFFCANCOVR:1; /* Offset cancellation phase over */
5731 uint32_t EOFFSET:1; /* error in offset refresh */
5732 uint32_t EOCTU:1; /* end of CTU channel conversion */
5733 uint32_t JEOC:1; /* end of injected channel conversion */
5734 uint32_t JECH:1; /* end ofinjected chain conversion */
5735 uint32_t EOC:1; /* end of channel conversion */
5736 uint32_t ECH:1; /* end of chain conversion */
5737 } B;
5738 } ADC_ISR_32B_tag;
5739
5740 typedef union { /* CHANNEL PENDING REGISTER 0 */
5741 uint32_t R;
5742 struct {
5743#ifndef USE_FIELD_ALIASES_ADC
5744 uint32_t EOC_CH31:1; /* Channel 31 conversion over */
5745#else
5746 uint32_t EOC31:1; /* deprecated name - please avoid */
5747#endif
5748#ifndef USE_FIELD_ALIASES_ADC
5749 uint32_t EOC_CH30:1; /* Channel 30 conversion over */
5750#else
5751 uint32_t EOC30:1; /* deprecated name - please avoid */
5752#endif
5753#ifndef USE_FIELD_ALIASES_ADC
5754 uint32_t EOC_CH29:1; /* Channel 29 conversion over */
5755#else
5756 uint32_t EOC29:1; /* deprecated name - please avoid */
5757#endif
5758#ifndef USE_FIELD_ALIASES_ADC
5759 uint32_t EOC_CH28:1; /* Channel 28 conversion over */
5760#else
5761 uint32_t EOC28:1; /* deprecated name - please avoid */
5762#endif
5763#ifndef USE_FIELD_ALIASES_ADC
5764 uint32_t EOC_CH27:1; /* Channel 27 conversion over */
5765#else
5766 uint32_t EOC27:1; /* deprecated name - please avoid */
5767#endif
5768#ifndef USE_FIELD_ALIASES_ADC
5769 uint32_t EOC_CH26:1; /* Channel 26 conversion over */
5770#else
5771 uint32_t EOC26:1; /* deprecated name - please avoid */
5772#endif
5773#ifndef USE_FIELD_ALIASES_ADC
5774 uint32_t EOC_CH25:1; /* Channel 25 conversion over */
5775#else
5776 uint32_t EOC25:1; /* deprecated name - please avoid */
5777#endif
5778#ifndef USE_FIELD_ALIASES_ADC
5779 uint32_t EOC_CH24:1; /* Channel 24 conversion over */
5780#else
5781 uint32_t EOC24:1; /* deprecated name - please avoid */
5782#endif
5783#ifndef USE_FIELD_ALIASES_ADC
5784 uint32_t EOC_CH23:1; /* Channel 23 conversion over */
5785#else
5786 uint32_t EOC23:1; /* deprecated name - please avoid */
5787#endif
5788#ifndef USE_FIELD_ALIASES_ADC
5789 uint32_t EOC_CH22:1; /* Channel 22 conversion over */
5790#else
5791 uint32_t EOC22:1; /* deprecated name - please avoid */
5792#endif
5793#ifndef USE_FIELD_ALIASES_ADC
5794 uint32_t EOC_CH21:1; /* Channel 21 conversion over */
5795#else
5796 uint32_t EOC21:1; /* deprecated name - please avoid */
5797#endif
5798#ifndef USE_FIELD_ALIASES_ADC
5799 uint32_t EOC_CH20:1; /* Channel 20 conversion over */
5800#else
5801 uint32_t EOC20:1; /* deprecated name - please avoid */
5802#endif
5803#ifndef USE_FIELD_ALIASES_ADC
5804 uint32_t EOC_CH19:1; /* Channel 19 conversion over */
5805#else
5806 uint32_t EOC19:1; /* deprecated name - please avoid */
5807#endif
5808#ifndef USE_FIELD_ALIASES_ADC
5809 uint32_t EOC_CH18:1; /* Channel 18 conversion over */
5810#else
5811 uint32_t EOC18:1; /* deprecated name - please avoid */
5812#endif
5813#ifndef USE_FIELD_ALIASES_ADC
5814 uint32_t EOC_CH17:1; /* Channel 17 conversion over */
5815#else
5816 uint32_t EOC17:1; /* deprecated name - please avoid */
5817#endif
5818#ifndef USE_FIELD_ALIASES_ADC
5819 uint32_t EOC_CH16:1; /* Channel 16 conversion over */
5820#else
5821 uint32_t EOC16:1; /* deprecated name - please avoid */
5822#endif
5823#ifndef USE_FIELD_ALIASES_ADC
5824 uint32_t EOC_CH15:1; /* Channel 15 conversion over */
5825#else
5826 uint32_t EOC15:1; /* deprecated name - please avoid */
5827#endif
5828#ifndef USE_FIELD_ALIASES_ADC
5829 uint32_t EOC_CH14:1; /* Channel 14 conversion over */
5830#else
5831 uint32_t EOC14:1; /* deprecated name - please avoid */
5832#endif
5833#ifndef USE_FIELD_ALIASES_ADC
5834 uint32_t EOC_CH13:1; /* Channel 13 conversion over */
5835#else
5836 uint32_t EOC13:1; /* deprecated name - please avoid */
5837#endif
5838#ifndef USE_FIELD_ALIASES_ADC
5839 uint32_t EOC_CH12:1; /* Channel 12 conversion over */
5840#else
5841 uint32_t EOC12:1; /* deprecated name - please avoid */
5842#endif
5843#ifndef USE_FIELD_ALIASES_ADC
5844 uint32_t EOC_CH11:1; /* Channel 11 conversion over */
5845#else
5846 uint32_t EOC11:1; /* deprecated name - please avoid */
5847#endif
5848#ifndef USE_FIELD_ALIASES_ADC
5849 uint32_t EOC_CH10:1; /* Channel 10 conversion over */
5850#else
5851 uint32_t EOC10:1; /* deprecated name - please avoid */
5852#endif
5853#ifndef USE_FIELD_ALIASES_ADC
5854 uint32_t EOC_CH9:1; /* Channel 9 conversion over */
5855#else
5856 uint32_t EOC9:1; /* deprecated name - please avoid */
5857#endif
5858#ifndef USE_FIELD_ALIASES_ADC
5859 uint32_t EOC_CH8:1; /* Channel 8 conversion over */
5860#else
5861 uint32_t EOC8:1; /* deprecated name - please avoid */
5862#endif
5863#ifndef USE_FIELD_ALIASES_ADC
5864 uint32_t EOC_CH7:1; /* Channel 7 conversion over */
5865#else
5866 uint32_t EOC7:1; /* deprecated name - please avoid */
5867#endif
5868#ifndef USE_FIELD_ALIASES_ADC
5869 uint32_t EOC_CH6:1; /* Channel 6 conversion over */
5870#else
5871 uint32_t EOC6:1; /* deprecated name - please avoid */
5872#endif
5873#ifndef USE_FIELD_ALIASES_ADC
5874 uint32_t EOC_CH5:1; /* Channel 5 conversion over */
5875#else
5876 uint32_t EOC5:1; /* deprecated name - please avoid */
5877#endif
5878#ifndef USE_FIELD_ALIASES_ADC
5879 uint32_t EOC_CH4:1; /* Channel 4 conversion over */
5880#else
5881 uint32_t EOC4:1; /* deprecated name - please avoid */
5882#endif
5883#ifndef USE_FIELD_ALIASES_ADC
5884 uint32_t EOC_CH3:1; /* Channel 3 conversion over */
5885#else
5886 uint32_t EOC3:1; /* deprecated name - please avoid */
5887#endif
5888#ifndef USE_FIELD_ALIASES_ADC
5889 uint32_t EOC_CH2:1; /* Channel 2 conversion over */
5890#else
5891 uint32_t EOC2:1; /* deprecated name - please avoid */
5892#endif
5893#ifndef USE_FIELD_ALIASES_ADC
5894 uint32_t EOC_CH1:1; /* Channel 1 conversion over */
5895#else
5896 uint32_t EOC1:1; /* deprecated name - please avoid */
5897#endif
5898#ifndef USE_FIELD_ALIASES_ADC
5899 uint32_t EOC_CH0:1; /* Channel 0 conversion over */
5900#else
5901 uint32_t EOC0:1; /* deprecated name - please avoid */
5902#endif
5903 } B;
5904 } ADC_CEOCFR0_32B_tag;
5905
5906 typedef union { /* CHANNEL PENDING REGISTER 1 */
5907 uint32_t R;
5908 struct {
5909 uint32_t EOC_CH63:1; /* Channel 63 conversion over */
5910 uint32_t EOC_CH62:1; /* Channel 62 conversion over */
5911 uint32_t EOC_CH61:1; /* Channel 61 conversion over */
5912 uint32_t EOC_CH60:1; /* Channel 60 conversion over */
5913 uint32_t EOC_CH59:1; /* Channel 59 conversion over */
5914 uint32_t EOC_CH58:1; /* Channel 58 conversion over */
5915 uint32_t EOC_CH57:1; /* Channel 57 conversion over */
5916 uint32_t EOC_CH56:1; /* Channel 56 conversion over */
5917 uint32_t EOC_CH55:1; /* Channel 55 conversion over */
5918 uint32_t EOC_CH54:1; /* Channel 54 conversion over */
5919 uint32_t EOC_CH53:1; /* Channel 53 conversion over */
5920 uint32_t EOC_CH52:1; /* Channel 52 conversion over */
5921 uint32_t EOC_CH51:1; /* Channel 51 conversion over */
5922 uint32_t EOC_CH50:1; /* Channel 50 conversion over */
5923 uint32_t EOC_CH49:1; /* Channel 49 conversion over */
5924 uint32_t EOC_CH48:1; /* Channel 48 conversion over */
5925 uint32_t EOC_CH47:1; /* Channel 47 conversion over */
5926 uint32_t EOC_CH46:1; /* Channel 46 conversion over */
5927 uint32_t EOC_CH45:1; /* Channel 45 conversion over */
5928 uint32_t EOC_CH44:1; /* Channel 44 conversion over */
5929 uint32_t EOC_CH43:1; /* Channel 43 conversion over */
5930 uint32_t EOC_CH42:1; /* Channel 42 conversion over */
5931 uint32_t EOC_CH41:1; /* Channel 41 conversion over */
5932 uint32_t EOC_CH40:1; /* Channel 40 conversion over */
5933 uint32_t EOC_CH39:1; /* Channel 39 conversion over */
5934 uint32_t EOC_CH38:1; /* Channel 38 conversion over */
5935 uint32_t EOC_CH37:1; /* Channel 37 conversion over */
5936 uint32_t EOC_CH36:1; /* Channel 36 conversion over */
5937 uint32_t EOC_CH35:1; /* Channel 35 conversion over */
5938 uint32_t EOC_CH34:1; /* Channel 34 conversion over */
5939 uint32_t EOC_CH33:1; /* Channel 33 conversion over */
5940 uint32_t EOC_CH32:1; /* Channel 32 conversion over */
5941 } B;
5942 } ADC_CEOCFR1_32B_tag;
5943
5944 typedef union { /* CHANNEL PENDING REGISTER 2 */
5945 uint32_t R;
5946 struct {
5947 uint32_t EOC_CH95:1; /* Channel 95 conversion over */
5948 uint32_t EOC_CH94:1; /* Channel 94 conversion over */
5949 uint32_t EOC_CH93:1; /* Channel 93 conversion over */
5950 uint32_t EOC_CH92:1; /* Channel 92 conversion over */
5951 uint32_t EOC_CH91:1; /* Channel 91 conversion over */
5952 uint32_t EOC_CH90:1; /* Channel 90 conversion over */
5953 uint32_t EOC_CH89:1; /* Channel 89 conversion over */
5954 uint32_t EOC_CH88:1; /* Channel 88 conversion over */
5955 uint32_t EOC_CH87:1; /* Channel 87 conversion over */
5956 uint32_t EOC_CH86:1; /* Channel 86 conversion over */
5957 uint32_t EOC_CH85:1; /* Channel 85 conversion over */
5958 uint32_t EOC_CH84:1; /* Channel 84 conversion over */
5959 uint32_t EOC_CH83:1; /* Channel 83 conversion over */
5960 uint32_t EOC_CH82:1; /* Channel 82 conversion over */
5961 uint32_t EOC_CH81:1; /* Channel 81 conversion over */
5962 uint32_t EOC_CH80:1; /* Channel 80 conversion over */
5963 uint32_t EOC_CH79:1; /* Channel 79 conversion over */
5964 uint32_t EOC_CH78:1; /* Channel 78 conversion over */
5965 uint32_t EOC_CH77:1; /* Channel 77 conversion over */
5966 uint32_t EOC_CH76:1; /* Channel 76 conversion over */
5967 uint32_t EOC_CH75:1; /* Channel 75 conversion over */
5968 uint32_t EOC_CH74:1; /* Channel 74 conversion over */
5969 uint32_t EOC_CH73:1; /* Channel 73 conversion over */
5970 uint32_t EOC_CH72:1; /* Channel 72 conversion over */
5971 uint32_t EOC_CH71:1; /* Channel 71 conversion over */
5972 uint32_t EOC_CH70:1; /* Channel 70 conversion over */
5973 uint32_t EOC_CH69:1; /* Channel 69 conversion over */
5974 uint32_t EOC_CH68:1; /* Channel 68 conversion over */
5975 uint32_t EOC_CH67:1; /* Channel 67 conversion over */
5976 uint32_t EOC_CH66:1; /* Channel 66 conversion over */
5977 uint32_t EOC_CH65:1; /* Channel 65 conversion over */
5978 uint32_t EOC_CH64:1; /* Channel 64 conversion over */
5979 } B;
5980 } ADC_CEOCFR2_32B_tag;
5981
5982 typedef union { /* interrupt mask register */
5983 uint32_t R;
5984 struct {
5985 uint32_t:25;
5986 uint32_t MSKOFFCANCOVR:1; /* mask bit for Calibration over */
5987 uint32_t MSKEOFFSET:1; /* mask bit for Error in offset refresh */
5988 uint32_t MSKEOCTU:1; /* mask bit for EOCTU */
5989 uint32_t MSKJEOC:1; /* mask bit for JEOC */
5990 uint32_t MSKJECH:1; /* mask bit for JECH */
5991 uint32_t MSKEOC:1; /* mask bit for EOC */
5992 uint32_t MSKECH:1; /* mask bit for ECH */
5993 } B;
5994 } ADC_IMR_32B_tag;
5995
5996 typedef union { /* CHANNEL INTERRUPT MASK REGISTER 0 */
5997 uint32_t R;
5998 struct {
5999 uint32_t CIM31:1; /* Channel 31 mask register */
6000 uint32_t CIM30:1; /* Channel 30 mask register */
6001 uint32_t CIM29:1; /* Channel 29 mask register */
6002 uint32_t CIM28:1; /* Channel 28 mask register */
6003 uint32_t CIM27:1; /* Channel 27 mask register */
6004 uint32_t CIM26:1; /* Channel 26 mask register */
6005 uint32_t CIM25:1; /* Channel 25 mask register */
6006 uint32_t CIM24:1; /* Channel 24 mask register */
6007 uint32_t CIM23:1; /* Channel 23 mask register */
6008 uint32_t CIM22:1; /* Channel 22 mask register */
6009 uint32_t CIM21:1; /* Channel 21 mask register */
6010 uint32_t CIM20:1; /* Channel 20 mask register */
6011 uint32_t CIM19:1; /* Channel 19 mask register */
6012 uint32_t CIM18:1; /* Channel 18 mask register */
6013 uint32_t CIM17:1; /* Channel 17 mask register */
6014 uint32_t CIM16:1; /* Channel 16 mask register */
6015 uint32_t CIM15:1; /* Channel 15 mask register */
6016 uint32_t CIM14:1; /* Channel 14 mask register */
6017 uint32_t CIM13:1; /* Channel 13 mask register */
6018 uint32_t CIM12:1; /* Channel 12 mask register */
6019 uint32_t CIM11:1; /* Channel 11 mask register */
6020 uint32_t CIM10:1; /* Channel 10 mask register */
6021 uint32_t CIM9:1; /* Channel 9 mask register */
6022 uint32_t CIM8:1; /* Channel 8 mask register */
6023 uint32_t CIM7:1; /* Channel 7 mask register */
6024 uint32_t CIM6:1; /* Channel 6 mask register */
6025 uint32_t CIM5:1; /* Channel 5 mask register */
6026 uint32_t CIM4:1; /* Channel 4 mask register */
6027 uint32_t CIM3:1; /* Channel 3 mask register */
6028 uint32_t CIM2:1; /* Channel 2 mask register */
6029 uint32_t CIM1:1; /* Channel 1 mask register */
6030 uint32_t CIM0:1; /* Channel 0 mask register */
6031 } B;
6032 } ADC_CIMR0_32B_tag;
6033
6034 typedef union { /* CHANNEL INTERRUPT MASK REGISTER 1 */
6035 uint32_t R;
6036 struct {
6037 uint32_t CIM63:1; /* Channel 63 mask register */
6038 uint32_t CIM62:1; /* Channel 62 mask register */
6039 uint32_t CIM61:1; /* Channel 61 mask register */
6040 uint32_t CIM60:1; /* Channel 60 mask register */
6041 uint32_t CIM59:1; /* Channel 59 mask register */
6042 uint32_t CIM58:1; /* Channel 58 mask register */
6043 uint32_t CIM57:1; /* Channel 57 mask register */
6044 uint32_t CIM56:1; /* Channel 56 mask register */
6045 uint32_t CIM55:1; /* Channel 55 mask register */
6046 uint32_t CIM54:1; /* Channel 54 mask register */
6047 uint32_t CIM53:1; /* Channel 53 mask register */
6048 uint32_t CIM52:1; /* Channel 52 mask register */
6049 uint32_t CIM51:1; /* Channel 51 mask register */
6050 uint32_t CIM50:1; /* Channel 50 mask register */
6051 uint32_t CIM49:1; /* Channel 49 mask register */
6052 uint32_t CIM48:1; /* Channel 48 mask register */
6053 uint32_t CIM47:1; /* Channel 47 mask register */
6054 uint32_t CIM46:1; /* Channel 46 mask register */
6055 uint32_t CIM45:1; /* Channel 45 mask register */
6056 uint32_t CIM44:1; /* Channel 44 mask register */
6057 uint32_t CIM43:1; /* Channel 43 mask register */
6058 uint32_t CIM42:1; /* Channel 42 mask register */
6059 uint32_t CIM41:1; /* Channel 41 mask register */
6060 uint32_t CIM40:1; /* Channel 40 mask register */
6061 uint32_t CIM39:1; /* Channel 39 mask register */
6062 uint32_t CIM38:1; /* Channel 38 mask register */
6063 uint32_t CIM37:1; /* Channel 37 mask register */
6064 uint32_t CIM36:1; /* Channel 36 mask register */
6065 uint32_t CIM35:1; /* Channel 35 mask register */
6066 uint32_t CIM34:1; /* Channel 34 mask register */
6067 uint32_t CIM33:1; /* Channel 33 mask register */
6068 uint32_t CIM32:1; /* Channel 32 mask register */
6069 } B;
6070 } ADC_CIMR1_32B_tag;
6071
6072 typedef union { /* CHANNEL INTERRUPT MASK REGISTER 2 */
6073 uint32_t R;
6074 struct {
6075 uint32_t CIM95:1; /* Channel 95 mask register */
6076 uint32_t CIM94:1; /* Channel 94 mask register */
6077 uint32_t CIM93:1; /* Channel 93 mask register */
6078 uint32_t CIM92:1; /* Channel 92 mask register */
6079 uint32_t CIM91:1; /* Channel 91 mask register */
6080 uint32_t CIM90:1; /* Channel 90 mask register */
6081 uint32_t CIM89:1; /* Channel 89 mask register */
6082 uint32_t CIM88:1; /* Channel 88 mask register */
6083 uint32_t CIM87:1; /* Channel 87 mask register */
6084 uint32_t CIM86:1; /* Channel 86 mask register */
6085 uint32_t CIM85:1; /* Channel 85 mask register */
6086 uint32_t CIM84:1; /* Channel 84 mask register */
6087 uint32_t CIM83:1; /* Channel 83 mask register */
6088 uint32_t CIM82:1; /* Channel 82 mask register */
6089 uint32_t CIM81:1; /* Channel 81 mask register */
6090 uint32_t CIM80:1; /* Channel 80 mask register */
6091 uint32_t CIM79:1; /* Channel 79 mask register */
6092 uint32_t CIM78:1; /* Channel 78 mask register */
6093 uint32_t CIM77:1; /* Channel 77 mask register */
6094 uint32_t CIM76:1; /* Channel 76 mask register */
6095 uint32_t CIM75:1; /* Channel 75 mask register */
6096 uint32_t CIM74:1; /* Channel 74 mask register */
6097 uint32_t CIM73:1; /* Channel 73 mask register */
6098 uint32_t CIM72:1; /* Channel 72 mask register */
6099 uint32_t CIM71:1; /* Channel 71 mask register */
6100 uint32_t CIM70:1; /* Channel 70 mask register */
6101 uint32_t CIM69:1; /* Channel 69 mask register */
6102 uint32_t CIM68:1; /* Channel 68 mask register */
6103 uint32_t CIM67:1; /* Channel 67 mask register */
6104 uint32_t CIM66:1; /* Channel 66 mask register */
6105 uint32_t CIM65:1; /* Channel 65 mask register */
6106 uint32_t CIM64:1; /* Channel 64 mask register */
6107 } B;
6108 } ADC_CIMR2_32B_tag;
6109
6110 typedef union { /* Watchdog Threshold interrupt status register */
6111 uint32_t R;
6112 struct {
6113 uint32_t:24;
6114 uint32_t WDG3H:1; /* Interrupt generated on the value being higher than the HTHV 3 */
6115 uint32_t WDG2H:1; /* Interrupt generated on the value being higher than the HTHV 2 */
6116 uint32_t WDG1H:1; /* Interrupt generated on the value being higher than the HTHV 1 */
6117 uint32_t WDG0H:1; /* Interrupt generated on the value being higher than the HTHV 0 */
6118 uint32_t WDG3L:1; /* Interrupt generated on the value being lower than the LTHV 3 */
6119 uint32_t WDG2L:1; /* Interrupt generated on the value being lower than the LTHV 2 */
6120 uint32_t WDG1L:1; /* Interrupt generated on the value being lower than the LTHV 1 */
6121 uint32_t WDG0L:1; /* Interrupt generated on the value being lower than the LTHV 0 */
6122 } B;
6123 } ADC_WTISR_32B_tag;
6124
6125 typedef union { /* Watchdog interrupt MASK register */
6126 uint32_t R;
6127 struct {
6128 uint32_t:24;
6129 uint32_t MSKWDG3H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 3 */
6130 uint32_t MSKWDG2H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 2 */
6131 uint32_t MSKWDG1H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 1 */
6132 uint32_t MSKWDG0H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 0 */
6133 uint32_t MSKWDG3L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 3 */
6134 uint32_t MSKWDG2L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 2 */
6135 uint32_t MSKWDG1L:1; /* MAsk enable for Interrupt generated on the value being lower than the LTHV 1 */
6136 uint32_t MSKWDG0L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 0 */
6137 } B;
6138 } ADC_WTIMR_32B_tag;
6139
6140 typedef union { /* DMAE register */
6141 uint32_t R;
6142 struct {
6143 uint32_t:30;
6144 uint32_t DCLR:1; /* DMA clear sequence enable */
6145 uint32_t DMAEN:1; /* DMA global enable */
6146 } B;
6147 } ADC_DMAE_32B_tag;
6148
6149 typedef union { /* DMA REGISTER 0 */
6150 uint32_t R;
6151 struct {
6152 uint32_t DMA31:1; /* Channel 31 DMA Enable */
6153 uint32_t DMA30:1; /* Channel 30 DMA Enable */
6154 uint32_t DMA29:1; /* Channel 29 DMA Enable */
6155 uint32_t DMA28:1; /* Channel 28 DMA Enable */
6156 uint32_t DMA27:1; /* Channel 27 DMA Enable */
6157 uint32_t DMA26:1; /* Channel 26 DMA Enable */
6158 uint32_t DMA25:1; /* Channel 25 DMA Enable */
6159 uint32_t DMA24:1; /* Channel 24 DMA Enable */
6160 uint32_t DMA23:1; /* Channel 23 DMA Enable */
6161 uint32_t DMA22:1; /* Channel 22 DMA Enable */
6162 uint32_t DMA21:1; /* Channel 21 DMA Enable */
6163 uint32_t DMA20:1; /* Channel 20 DMA Enable */
6164 uint32_t DMA19:1; /* Channel 19 DMA Enable */
6165 uint32_t DMA18:1; /* Channel 18 DMA Enable */
6166 uint32_t DMA17:1; /* Channel 17 DMA Enable */
6167 uint32_t DMA16:1; /* Channel 16 DMA Enable */
6168 uint32_t DMA15:1; /* Channel 15 DMA Enable */
6169 uint32_t DMA14:1; /* Channel 14 DMA Enable */
6170 uint32_t DMA13:1; /* Channel 13 DMA Enable */
6171 uint32_t DMA12:1; /* Channel 12 DMA Enable */
6172 uint32_t DMA11:1; /* Channel 11 DMA Enable */
6173 uint32_t DMA10:1; /* Channel 10 DMA Enable */
6174 uint32_t DMA9:1; /* Channel 9 DMA Enable */
6175 uint32_t DMA8:1; /* Channel 8 DMA Enable */
6176 uint32_t DMA7:1; /* Channel 7 DMA Enable */
6177 uint32_t DMA6:1; /* Channel 6 DMA Enable */
6178 uint32_t DMA5:1; /* Channel 5 DMA Enable */
6179 uint32_t DMA4:1; /* Channel 4 DMA Enable */
6180 uint32_t DMA3:1; /* Channel 3 DMA Enable */
6181 uint32_t DMA2:1; /* Channel 2 DMA Enable */
6182 uint32_t DMA1:1; /* Channel 1 DMA Enable */
6183 uint32_t DMA0:1; /* Channel 0 DMA Enable */
6184 } B;
6185 } ADC_DMAR0_32B_tag;
6186
6187 typedef union { /* DMA REGISTER 1 */
6188 uint32_t R;
6189 struct {
6190 uint32_t DMA63:1; /* Channel 63 DMA Enable */
6191 uint32_t DMA62:1; /* Channel 62 DMA Enable */
6192 uint32_t DMA61:1; /* Channel 61 DMA Enable */
6193 uint32_t DMA60:1; /* Channel 60 DMA Enable */
6194 uint32_t DMA59:1; /* Channel 59 DMA Enable */
6195 uint32_t DMA58:1; /* Channel 58 DMA Enable */
6196 uint32_t DMA57:1; /* Channel 57 DMA Enable */
6197 uint32_t DMA56:1; /* Channel 56 DMA Enable */
6198 uint32_t DMA55:1; /* Channel 55 DMA Enable */
6199 uint32_t DMA54:1; /* Channel 54 DMA Enable */
6200 uint32_t DMA53:1; /* Channel 53 DMA Enable */
6201 uint32_t DMA52:1; /* Channel 52 DMA Enable */
6202 uint32_t DMA51:1; /* Channel 51 DMA Enable */
6203 uint32_t DMA50:1; /* Channel 50 DMA Enable */
6204 uint32_t DMA49:1; /* Channel 49 DMA Enable */
6205 uint32_t DMA48:1; /* Channel 48 DMA Enable */
6206 uint32_t DMA47:1; /* Channel 47 DMA Enable */
6207 uint32_t DMA46:1; /* Channel 46 DMA Enable */
6208 uint32_t DMA45:1; /* Channel 45 DMA Enable */
6209 uint32_t DMA44:1; /* Channel 44 DMA Enable */
6210 uint32_t DMA43:1; /* Channel 43 DMA Enable */
6211 uint32_t DMA42:1; /* Channel 42 DMA Enable */
6212 uint32_t DMA41:1; /* Channel 41 DMA Enable */
6213 uint32_t DMA40:1; /* Channel 40 DMA Enable */
6214 uint32_t DMA39:1; /* Channel 39 DMA Enable */
6215 uint32_t DMA38:1; /* Channel 38 DMA Enable */
6216 uint32_t DMA37:1; /* Channel 37 DMA Enable */
6217 uint32_t DMA36:1; /* Channel 36 DMA Enable */
6218 uint32_t DMA35:1; /* Channel 35 DMA Enable */
6219 uint32_t DMA34:1; /* Channel 34 DMA Enable */
6220 uint32_t DMA33:1; /* Channel 33 DMA Enable */
6221 uint32_t DMA32:1; /* Channel 32 DMA Enable */
6222 } B;
6223 } ADC_DMAR1_32B_tag;
6224
6225 typedef union { /* DMA REGISTER 2 */
6226 uint32_t R;
6227 struct {
6228 uint32_t DMA95:1; /* Channel 95 DMA Enable */
6229 uint32_t DMA94:1; /* Channel 94 DMA Enable */
6230 uint32_t DMA93:1; /* Channel 93 DMA Enable */
6231 uint32_t DMA92:1; /* Channel 92 DMA Enable */
6232 uint32_t DMA91:1; /* Channel 91 DMA Enable */
6233 uint32_t DMA90:1; /* Channel 90 DMA Enable */
6234 uint32_t DMA89:1; /* Channel 89 DMA Enable */
6235 uint32_t DMA88:1; /* Channel 88 DMA Enable */
6236 uint32_t DMA87:1; /* Channel 87 DMA Enable */
6237 uint32_t DMA86:1; /* Channel 86 DMA Enable */
6238 uint32_t DMA85:1; /* Channel 85 DMA Enable */
6239 uint32_t DMA84:1; /* Channel 84 DMA Enable */
6240 uint32_t DMA83:1; /* Channel 83 DMA Enable */
6241 uint32_t DMA82:1; /* Channel 82 DMA Enable */
6242 uint32_t DMA81:1; /* Channel 81 DMA Enable */
6243 uint32_t DMA80:1; /* Channel 80 DMA Enable */
6244 uint32_t DMA79:1; /* Channel 79 DMA Enable */
6245 uint32_t DMA78:1; /* Channel 78 DMA Enable */
6246 uint32_t DMA77:1; /* Channel 77 DMA Enable */
6247 uint32_t DMA76:1; /* Channel 76 DMA Enable */
6248 uint32_t DMA75:1; /* Channel 75 DMA Enable */
6249 uint32_t DMA74:1; /* Channel 74 DMA Enable */
6250 uint32_t DMA73:1; /* Channel 73 DMA Enable */
6251 uint32_t DMA72:1; /* Channel 72 DMA Enable */
6252 uint32_t DMA71:1; /* Channel 71 DMA Enable */
6253 uint32_t DMA70:1; /* Channel 70 DMA Enable */
6254 uint32_t DMA69:1; /* Channel 69 DMA Enable */
6255 uint32_t DMA68:1; /* Channel 68 DMA Enable */
6256 uint32_t DMA67:1; /* Channel 67 DMA Enable */
6257 uint32_t DMA66:1; /* Channel 66 DMA Enable */
6258 uint32_t DMA65:1; /* Channel 65 DMA Enable */
6259 uint32_t DMA64:1; /* Channel 64 DMA Enable */
6260 } B;
6261 } ADC_DMAR2_32B_tag;
6262
6263
6264 /* Register layout for all registers TRC... */
6265
6266 typedef union { /* Threshold Control register C */
6267 uint32_t R;
6268 struct {
6269 uint32_t:16;
6270 uint32_t THREN:1; /* Threshold enable */
6271 uint32_t THRINV:1; /* invert the output pin */
6272 uint32_t THROP:1; /* output pin register */
6273 uint32_t:6;
6274 uint32_t THRCH:7; /* Choose channel for threshold register */
6275 } B;
6276 } ADC_TRC_32B_tag;
6277
6278
6279 /* Register layout for all registers THRHLR... */
6280
6281 typedef union { /* Upper Threshold register */
6282 uint32_t R;
6283 struct {
6284 uint32_t:4;
6285 uint32_t THRH:12; /* high threshold value s */
6286 uint32_t:4;
6287 uint32_t THRL:12; /* low threshold value s */
6288 } B;
6289 } ADC_THRHLR_32B_tag;
6290
6291
6292 /* Register layout for all registers THRALT... */
6293
6294 typedef union { /* alternate Upper Threshold register */
6295 uint32_t R;
6296 struct {
6297 uint32_t:6;
6298 uint32_t THRH:10; /* high threshold value s */
6299 uint32_t:6;
6300 uint32_t THRL:10; /* low threshold value s */
6301 } B;
6302 } ADC_THRALT_32B_tag;
6303
6304 typedef union { /* PRESAMPLING CONTROL REGISTER */
6305 uint32_t R;
6306 struct {
6307 uint32_t:25;
6308 uint32_t PREVAL2:2; /* INternal Voltage selection for Presampling */
6309 uint32_t PREVAL1:2; /* INternal Voltage selection for Presampling */
6310 uint32_t PREVAL0:2; /* INternal Voltage selection for Presampling */
6311#ifndef USE_FIELD_ALIASES_ADC
6312 uint32_t PRECONV:1; /* Presampled value */
6313#else
6314 uint32_t PREONCE:1; /* deprecated name - please avoid */
6315#endif
6316 } B;
6317 } ADC_PSCR_32B_tag;
6318
6319 typedef union { /* Presampling Register 0 */
6320 uint32_t R;
6321 struct {
6322 uint32_t PRES31:1; /* Channel 31 Presampling Enable */
6323 uint32_t PRES30:1; /* Channel 30 Presampling Enable */
6324 uint32_t PRES29:1; /* Channel 29 Presampling Enable */
6325 uint32_t PRES28:1; /* Channel 28 Presampling Enable */
6326 uint32_t PRES27:1; /* Channel 27 Presampling Enable */
6327 uint32_t PRES26:1; /* Channel 26 Presampling Enable */
6328 uint32_t PRES25:1; /* Channel 25 Presampling Enable */
6329 uint32_t PRES24:1; /* Channel 24 Presampling Enable */
6330 uint32_t PRES23:1; /* Channel 23 Presampling Enable */
6331 uint32_t PRES22:1; /* Channel 22 Presampling Enable */
6332 uint32_t PRES21:1; /* Channel 21 Presampling Enable */
6333 uint32_t PRES20:1; /* Channel 20 Presampling Enable */
6334 uint32_t PRES19:1; /* Channel 19 Presampling Enable */
6335 uint32_t PRES18:1; /* Channel 18 Presampling Enable */
6336 uint32_t PRES17:1; /* Channel 17 Presampling Enable */
6337 uint32_t PRES16:1; /* Channel 16 Presampling Enable */
6338 uint32_t PRES15:1; /* Channel 15 Presampling Enable */
6339 uint32_t PRES14:1; /* Channel 14 Presampling Enable */
6340 uint32_t PRES13:1; /* Channel 13 Presampling Enable */
6341 uint32_t PRES12:1; /* Channel 12 Presampling Enable */
6342 uint32_t PRES11:1; /* Channel 11 Presampling Enable */
6343 uint32_t PRES10:1; /* Channel 10 Presampling Enable */
6344 uint32_t PRES9:1; /* Channel 9 Presampling Enable */
6345 uint32_t PRES8:1; /* Channel 8 Presampling Enable */
6346 uint32_t PRES7:1; /* Channel 7 Presampling Enable */
6347 uint32_t PRES6:1; /* Channel 6 Presampling Enable */
6348 uint32_t PRES5:1; /* Channel 5 Presampling Enable */
6349 uint32_t PRES4:1; /* Channel 4 Presampling Enable */
6350 uint32_t PRES3:1; /* Channel 3 Presampling Enable */
6351 uint32_t PRES2:1; /* Channel 2 Presampling Enable */
6352 uint32_t PRES1:1; /* Channel 1presampling Enable */
6353 uint32_t PRES0:1; /* Channel 0 Presampling Enable */
6354 } B;
6355 } ADC_PSR0_32B_tag;
6356
6357 typedef union { /* Presampling REGISTER 1 */
6358 uint32_t R;
6359 struct {
6360 uint32_t PRES63:1; /* Channel 63 Presampling Enable */
6361 uint32_t PRES62:1; /* Channel 62 Presampling Enable */
6362 uint32_t PRES61:1; /* Channel 61 Presampling Enable */
6363 uint32_t PRES60:1; /* Channel 60 Presampling Enable */
6364 uint32_t PRES59:1; /* Channel 59 Presampling Enable */
6365 uint32_t PRES58:1; /* Channel 58 Presampling Enable */
6366 uint32_t PRES57:1; /* Channel 57 Presampling Enable */
6367 uint32_t PRES56:1; /* Channel 56 Presampling Enable */
6368 uint32_t PRES55:1; /* Channel 55 Presampling Enable */
6369 uint32_t PRES54:1; /* Channel 54 Presampling Enable */
6370 uint32_t PRES53:1; /* Channel 53 Presampling Enable */
6371 uint32_t PRES52:1; /* Channel 52 Presampling Enable */
6372 uint32_t PRES51:1; /* Channel 51 Presampling Enable */
6373 uint32_t PRES50:1; /* Channel 50 Presampling Enable */
6374 uint32_t PRES49:1; /* Channel 49 Presampling Enable */
6375 uint32_t PRES48:1; /* Channel 48 Presampling Enable */
6376 uint32_t PRES47:1; /* Channel 47 Presampling Enable */
6377 uint32_t PRES46:1; /* Channel 46 Presampling Enable */
6378 uint32_t PRES45:1; /* Channel 45 Presampling Enable */
6379 uint32_t PRES44:1; /* Channel 44 Presampling Enable */
6380 uint32_t PRES43:1; /* Channel 43 Presampling Enable */
6381 uint32_t PRES42:1; /* Channel 42 Presampling Enable */
6382 uint32_t PRES41:1; /* Channel 41 Presampling Enable */
6383 uint32_t PRES40:1; /* Channel 40 Presampling Enable */
6384 uint32_t PRES39:1; /* Channel 39 Presampling Enable */
6385 uint32_t PRES38:1; /* Channel 38 Presampling Enable */
6386 uint32_t PRES37:1; /* Channel 37 Presampling Enable */
6387 uint32_t PRES36:1; /* Channel 36 Presampling Enable */
6388 uint32_t PRES35:1; /* Channel 35 Presampling Enable */
6389 uint32_t PRES34:1; /* Channel 34 Presampling Enable */
6390 uint32_t PRES33:1; /* Channel 33 Presampling Enable */
6391 uint32_t PRES32:1; /* Channel 32 Presampling Enable */
6392 } B;
6393 } ADC_PSR1_32B_tag;
6394
6395 typedef union { /* Presampling REGISTER 2 */
6396 uint32_t R;
6397 struct {
6398 uint32_t PRES95:1; /* Channel 95 Presampling Enable */
6399 uint32_t PRES94:1; /* Channel 94 Presampling Enable */
6400 uint32_t PRES93:1; /* Channel 93 Presampling Enable */
6401 uint32_t PRES92:1; /* Channel 92 Presampling Enable */
6402 uint32_t PRES91:1; /* Channel 91 Presampling Enable */
6403 uint32_t PRES90:1; /* Channel 90 Presampling Enable */
6404 uint32_t PRES89:1; /* Channel 89 Presampling Enable */
6405 uint32_t PRES88:1; /* Channel 88 Presampling Enable */
6406 uint32_t PRES87:1; /* Channel 87 Presampling Enable */
6407 uint32_t PRES86:1; /* Channel 86 Presampling Enable */
6408 uint32_t PRES85:1; /* Channel 85 Presampling Enable */
6409 uint32_t PRES84:1; /* Channel 84 Presampling Enable */
6410 uint32_t PRES83:1; /* Channel 83 Presampling Enable */
6411 uint32_t PRES82:1; /* Channel 82 Presampling Enable */
6412 uint32_t PRES81:1; /* Channel 81 Presampling Enable */
6413 uint32_t PRES80:1; /* Channel 80 Presampling Enable */
6414 uint32_t PRES79:1; /* Channel 79 Presampling Enable */
6415 uint32_t PRES78:1; /* Channel 78 Presampling Enable */
6416 uint32_t PRES77:1; /* Channel 77 Presampling Enable */
6417 uint32_t PRES76:1; /* Channel 76 Presampling Enable */
6418 uint32_t PRES75:1; /* Channel 75 Presampling Enable */
6419 uint32_t PRES74:1; /* Channel 74 Presampling Enable */
6420 uint32_t PRES73:1; /* Channel 73 Presampling Enable */
6421 uint32_t PRES72:1; /* Channel 72 Presampling Enable */
6422 uint32_t PRES71:1; /* Channel 71 Presampling Enable */
6423 uint32_t PRES70:1; /* Channel 70 Presampling Enable */
6424 uint32_t PRES69:1; /* Channel 69 Presampling Enable */
6425 uint32_t PRES68:1; /* Channel 68 Presampling Enable */
6426 uint32_t PRES67:1; /* Channel 67 Presampling Enable */
6427 uint32_t PRES66:1; /* Channel 66 Presampling Enable */
6428 uint32_t PRES65:1; /* Channel 65 Presampling Enable */
6429 uint32_t PRES64:1; /* Channel 64 Presampling Enable */
6430 } B;
6431 } ADC_PSR2_32B_tag;
6432
6433
6434 /* Register layout for all registers CTR... */
6435
6436 typedef union { /* conversion timing register */
6437 uint32_t R;
6438 struct {
6439 uint32_t:16;
6440 uint32_t INPLATCH:1; /* configuration bits for the LATCHING PHASE duration */
6441 uint32_t:1;
6442 uint32_t OFFSHIFT:2; /* configuration for offset shift characteristics */
6443 uint32_t:1;
6444 uint32_t INPCMP:2; /* configuration bits for the COMPARISON duration */
6445 uint32_t:1;
6446#ifndef USE_FIELD_ALIASES_ADC
6447 uint32_t INSAMP:8; /* configuration bits for the SAMPLING PHASE duration */
6448#else
6449 uint32_t INPSAMP:8;
6450#endif
6451 } B;
6452 } ADC_CTR_32B_tag;
6453
6454 typedef union { /* NORMAL CONVERSION MASK REGISTER 0 */
6455 uint32_t R;
6456 struct {
6457 uint32_t CH31:1; /* Channel 31 Normal Sampling Enable */
6458 uint32_t CH30:1; /* Channel 30 Normal Sampling Enable */
6459 uint32_t CH29:1; /* Channel 29 Normal Sampling Enable */
6460 uint32_t CH28:1; /* Channel 28 Normal Sampling Enable */
6461 uint32_t CH27:1; /* Channel 27 Normal Sampling Enable */
6462 uint32_t CH26:1; /* Channel 26 Normal Sampling Enable */
6463 uint32_t CH25:1; /* Channel 25 Normal Sampling Enable */
6464 uint32_t CH24:1; /* Channel 24 Normal Sampling Enable */
6465 uint32_t CH23:1; /* Channel 23 Normal Sampling Enable */
6466 uint32_t CH22:1; /* Channel 22 Normal Sampling Enable */
6467 uint32_t CH21:1; /* Channel 21 Normal Sampling Enable */
6468 uint32_t CH20:1; /* Channel 20 Normal Sampling Enable */
6469 uint32_t CH19:1; /* Channel 19 Normal Sampling Enable */
6470 uint32_t CH18:1; /* Channel 18 Normal Sampling Enable */
6471 uint32_t CH17:1; /* Channel 17 Normal Sampling Enable */
6472 uint32_t CH16:1; /* Channel 16 Normal Sampling Enable */
6473 uint32_t CH15:1; /* Channel 15 Normal Sampling Enable */
6474 uint32_t CH14:1; /* Channel 14 Normal Sampling Enable */
6475 uint32_t CH13:1; /* Channel 13 Normal Sampling Enable */
6476 uint32_t CH12:1; /* Channel 12 Normal Sampling Enable */
6477 uint32_t CH11:1; /* Channel 11 Normal Sampling Enable */
6478 uint32_t CH10:1; /* Channel 10 Normal Sampling Enable */
6479 uint32_t CH9:1; /* Channel 9 Normal Sampling Enable */
6480 uint32_t CH8:1; /* Channel 8 Normal Sampling Enable */
6481 uint32_t CH7:1; /* Channel 7 Normal Sampling Enable */
6482 uint32_t CH6:1; /* Channel 6 Normal Sampling Enable */
6483 uint32_t CH5:1; /* Channel 5 Normal Sampling Enable */
6484 uint32_t CH4:1; /* Channel 4 Normal Sampling Enable */
6485 uint32_t CH3:1; /* Channel 3 Normal Sampling Enable */
6486 uint32_t CH2:1; /* Channel 2 Normal Sampling Enable */
6487 uint32_t CH1:1; /* Channel 1 Normal Sampling Enable */
6488 uint32_t CH0:1; /* Channel 0 Normal Sampling Enable */
6489 } B;
6490 } ADC_NCMR0_32B_tag;
6491
6492 typedef union { /* NORMAL CONVERSION MASK REGISTER 1 */
6493 uint32_t R;
6494 struct {
6495 uint32_t CH63:1; /* Channel 63 Normal Sampling Enable */
6496 uint32_t CH62:1; /* Channel 62 Normal Sampling Enable */
6497 uint32_t CH61:1; /* Channel 61 Normal Sampling Enable */
6498 uint32_t CH60:1; /* Channel 60 Normal Sampling Enable */
6499 uint32_t CH59:1; /* Channel 59 Normal Sampling Enable */
6500 uint32_t CH58:1; /* Channel 58 Normal Sampling Enable */
6501 uint32_t CH57:1; /* Channel 57 Normal Sampling Enable */
6502 uint32_t CH56:1; /* Channel 56 Normal Sampling Enable */
6503 uint32_t CH55:1; /* Channel 55 Normal Sampling Enable */
6504 uint32_t CH54:1; /* Channel 54 Normal Sampling Enable */
6505 uint32_t CH53:1; /* Channel 53 Normal Sampling Enable */
6506 uint32_t CH52:1; /* Channel 52 Normal Sampling Enable */
6507 uint32_t CH51:1; /* Channel 51 Normal Sampling Enable */
6508 uint32_t CH50:1; /* Channel 50 Normal Sampling Enable */
6509 uint32_t CH49:1; /* Channel 49 Normal Sampling Enable */
6510 uint32_t CH48:1; /* Channel 48 Normal Sampling Enable */
6511 uint32_t CH47:1; /* Channel 47 Normal Sampling Enable */
6512 uint32_t CH46:1; /* Channel 46 Normal Sampling Enable */
6513 uint32_t CH45:1; /* Channel 45 Normal Sampling Enable */
6514 uint32_t CH44:1; /* Channel 44 Normal Sampling Enable */
6515 uint32_t CH43:1; /* Channel 43 Normal Sampling Enable */
6516 uint32_t CH42:1; /* Channel 42 Normal Sampling Enable */
6517 uint32_t CH41:1; /* Channel 41 Normal Sampling Enable */
6518 uint32_t CH40:1; /* Channel 40 Normal Sampling Enable */
6519 uint32_t CH39:1; /* Channel 39 Normal Sampling Enable */
6520 uint32_t CH38:1; /* Channel 38 Normal Sampling Enable */
6521 uint32_t CH37:1; /* Channel 37 Normal Sampling Enable */
6522 uint32_t CH36:1; /* Channel 36 Normal Sampling Enable */
6523 uint32_t CH35:1; /* Channel 35 Normal Sampling Enable */
6524 uint32_t CH34:1; /* Channel 34 Normal Sampling Enable */
6525 uint32_t CH33:1; /* Channel 33 Normal Sampling Enable */
6526 uint32_t CH32:1; /* Channel 32 Normal Sampling Enable */
6527 } B;
6528 } ADC_NCMR1_32B_tag;
6529
6530 typedef union { /* NORMAL CONVERSION MASK REGISTER 2 */
6531 uint32_t R;
6532 struct {
6533 uint32_t CH95:1; /* Channel 95 Normal Sampling Enable */
6534 uint32_t CH94:1; /* Channel 94 Normal Sampling Enable */
6535 uint32_t CH93:1; /* Channel 93 Normal Sampling Enable */
6536 uint32_t CH92:1; /* Channel 92 Normal Sampling Enable */
6537 uint32_t CH91:1; /* Channel 91 Normal Sampling Enable */
6538 uint32_t CH90:1; /* Channel 90 Normal Sampling Enable */
6539 uint32_t CH89:1; /* Channel 89 Normal Sampling Enable */
6540 uint32_t CH88:1; /* Channel 88 Normal Sampling Enable */
6541 uint32_t CH87:1; /* Channel 87 Normal Sampling Enable */
6542 uint32_t CH86:1; /* Channel 86 Normal Sampling Enable */
6543 uint32_t CH85:1; /* Channel 85 Normal Sampling Enable */
6544 uint32_t CH84:1; /* Channel 84 Normal Sampling Enable */
6545 uint32_t CH83:1; /* Channel 83 Normal Sampling Enable */
6546 uint32_t CH82:1; /* Channel 82 Normal Sampling Enable */
6547 uint32_t CH81:1; /* Channel 81 Normal Sampling Enable */
6548 uint32_t CH80:1; /* Channel 80 Normal Sampling Enable */
6549 uint32_t CH79:1; /* Channel 79 Normal Sampling Enable */
6550 uint32_t CH78:1; /* Channel 78 Normal Sampling Enable */
6551 uint32_t CH77:1; /* Channel 77 Normal Sampling Enable */
6552 uint32_t CH76:1; /* Channel 76 Normal Sampling Enable */
6553 uint32_t CH75:1; /* Channel 75 Normal Sampling Enable */
6554 uint32_t CH74:1; /* Channel 74 Normal Sampling Enable */
6555 uint32_t CH73:1; /* Channel 73 Normal Sampling Enable */
6556 uint32_t CH72:1; /* Channel 72 Normal Sampling Enable */
6557 uint32_t CH71:1; /* Channel 71 Normal Sampling Enable */
6558 uint32_t CH70:1; /* Channel 70 Normal Sampling Enable */
6559 uint32_t CH69:1; /* Channel 69 Normal Sampling Enable */
6560 uint32_t CH68:1; /* Channel 68 Normal Sampling Enable */
6561 uint32_t CH67:1; /* Channel 67 Normal Sampling Enable */
6562 uint32_t CH66:1; /* Channel 66 Normal Sampling Enable */
6563 uint32_t CH65:1; /* Channel 65 Normal Sampling Enable */
6564 uint32_t CH64:1; /* Channel 64 Normal Sampling Enable */
6565 } B;
6566 } ADC_NCMR2_32B_tag;
6567
6568 typedef union { /* Injected Conversion Mask Register 0 */
6569 uint32_t R;
6570 struct {
6571 uint32_t CH31:1; /* Channel 31 Injected Sampling Enable */
6572 uint32_t CH30:1; /* Channel 30 Injected Sampling Enable */
6573 uint32_t CH29:1; /* Channel 29 Injected Sampling Enable */
6574 uint32_t CH28:1; /* Channel 28 Injected Sampling Enable */
6575 uint32_t CH27:1; /* Channel 27 Injected Sampling Enable */
6576 uint32_t CH26:1; /* Channel 26 Injected Sampling Enable */
6577 uint32_t CH25:1; /* Channel 25 Injected Sampling Enable */
6578 uint32_t CH24:1; /* Channel 24 Injected Sampling Enable */
6579 uint32_t CH23:1; /* Channel 23 Injected Sampling Enable */
6580 uint32_t CH22:1; /* Channel 22 Injected Sampling Enable */
6581 uint32_t CH21:1; /* Channel 21 Injected Sampling Enable */
6582 uint32_t CH20:1; /* Channel 20 Injected Sampling Enable */
6583 uint32_t CH19:1; /* Channel 19 Injected Sampling Enable */
6584 uint32_t CH18:1; /* Channel 18 Injected Sampling Enable */
6585 uint32_t CH17:1; /* Channel 17 Injected Sampling Enable */
6586 uint32_t CH16:1; /* Channel 16 Injected Sampling Enable */
6587 uint32_t CH15:1; /* Channel 15 Injected Sampling Enable */
6588 uint32_t CH14:1; /* Channel 14 Injected Sampling Enable */
6589 uint32_t CH13:1; /* Channel 13 Injected Sampling Enable */
6590 uint32_t CH12:1; /* Channel 12 Injected Sampling Enable */
6591 uint32_t CH11:1; /* Channel 11 Injected Sampling Enable */
6592 uint32_t CH10:1; /* Channel 10 Injected Sampling Enable */
6593 uint32_t CH9:1; /* Channel 9 Injected Sampling Enable */
6594 uint32_t CH8:1; /* Channel 8 Injected Sampling Enable */
6595 uint32_t CH7:1; /* Channel 7 Injected Sampling Enable */
6596 uint32_t CH6:1; /* Channel 6 Injected Sampling Enable */
6597 uint32_t CH5:1; /* Channel 5 Injected Sampling Enable */
6598 uint32_t CH4:1; /* Channel 4 Injected Sampling Enable */
6599 uint32_t CH3:1; /* Channel 3 Injected Sampling Enable */
6600 uint32_t CH2:1; /* Channel 2 Injected Sampling Enable */
6601 uint32_t CH1:1; /* Channel 1 injected Sampling Enable */
6602 uint32_t CH0:1; /* Channel 0 injected Sampling Enable */
6603 } B;
6604 } ADC_JCMR0_32B_tag;
6605
6606 typedef union { /* INJECTED CONVERSION MASK REGISTER 1 */
6607 uint32_t R;
6608 struct {
6609 uint32_t CH63:1; /* Channel 63 Injected Sampling Enable */
6610 uint32_t CH62:1; /* Channel 62 Injected Sampling Enable */
6611 uint32_t CH61:1; /* Channel 61 Injected Sampling Enable */
6612 uint32_t CH60:1; /* Channel 60 Injected Sampling Enable */
6613 uint32_t CH59:1; /* Channel 59 Injected Sampling Enable */
6614 uint32_t CH58:1; /* Channel 58 Injected Sampling Enable */
6615 uint32_t CH57:1; /* Channel 57 Injected Sampling Enable */
6616 uint32_t CH56:1; /* Channel 56 Injected Sampling Enable */
6617 uint32_t CH55:1; /* Channel 55 Injected Sampling Enable */
6618 uint32_t CH54:1; /* Channel 54 Injected Sampling Enable */
6619 uint32_t CH53:1; /* Channel 53 Injected Sampling Enable */
6620 uint32_t CH52:1; /* Channel 52 Injected Sampling Enable */
6621 uint32_t CH51:1; /* Channel 51 Injected Sampling Enable */
6622 uint32_t CH50:1; /* Channel 50 Injected Sampling Enable */
6623 uint32_t CH49:1; /* Channel 49 Injected Sampling Enable */
6624 uint32_t CH48:1; /* Channel 48 Injected Sampling Enable */
6625 uint32_t CH47:1; /* Channel 47 Injected Sampling Enable */
6626 uint32_t CH46:1; /* Channel 46 Injected Sampling Enable */
6627 uint32_t CH45:1; /* Channel 45 Injected Sampling Enable */
6628 uint32_t CH44:1; /* Channel 44 Injected Sampling Enable */
6629 uint32_t CH43:1; /* Channel 43 Injected Sampling Enable */
6630 uint32_t CH42:1; /* Channel 42 Injected Sampling Enable */
6631 uint32_t CH41:1; /* Channel 41 Injected Sampling Enable */
6632 uint32_t CH40:1; /* Channel 40 Injected Sampling Enable */
6633 uint32_t CH39:1; /* Channel 39 Injected Sampling Enable */
6634 uint32_t CH38:1; /* Channel 38 Injected Sampling Enable */
6635 uint32_t CH37:1; /* Channel 37 Injected Sampling Enable */
6636 uint32_t CH36:1; /* Channel 36 Injected Sampling Enable */
6637 uint32_t CH35:1; /* Channel 35 Injected Sampling Enable */
6638 uint32_t CH34:1; /* Channel 34 Injected Sampling Enable */
6639 uint32_t CH33:1; /* Channel 33 Injected Sampling Enable */
6640 uint32_t CH32:1; /* Channel 32 Injected Sampling Enable */
6641 } B;
6642 } ADC_JCMR1_32B_tag;
6643
6644 typedef union { /* INJECTED CONVERSION MASK REGISTER 2 */
6645 uint32_t R;
6646 struct {
6647 uint32_t CH95:1; /* Channel 95 Injected Sampling Enable */
6648 uint32_t CH94:1; /* Channel 94 Injected Sampling Enable */
6649 uint32_t CH93:1; /* Channel 93 Injected Sampling Enable */
6650 uint32_t CH92:1; /* Channel 92 Injected Sampling Enable */
6651 uint32_t CH91:1; /* Channel 91 Injected Sampling Enable */
6652 uint32_t CH90:1; /* Channel 90 Injected Sampling Enable */
6653 uint32_t CH89:1; /* Channel 89 Injected Sampling Enable */
6654 uint32_t CH88:1; /* Channel 88 Injected Sampling Enable */
6655 uint32_t CH87:1; /* Channel 87 Injected Sampling Enable */
6656 uint32_t CH86:1; /* Channel 86 Injected Sampling Enable */
6657 uint32_t CH85:1; /* Channel 85 Injected Sampling Enable */
6658 uint32_t CH84:1; /* Channel 84 Injected Sampling Enable */
6659 uint32_t CH83:1; /* Channel 83 Injected Sampling Enable */
6660 uint32_t CH82:1; /* Channel 82 Injected Sampling Enable */
6661 uint32_t CH81:1; /* Channel 81 Injected Sampling Enable */
6662 uint32_t CH80:1; /* Channel 80 Injected Sampling Enable */
6663 uint32_t CH79:1; /* Channel 79 Injected Sampling Enable */
6664 uint32_t CH78:1; /* Channel 78 Injected Sampling Enable */
6665 uint32_t CH77:1; /* Channel 77 Injected Sampling Enable */
6666 uint32_t CH76:1; /* Channel 76 Injected Sampling Enable */
6667 uint32_t CH75:1; /* Channel 75 Injected Sampling Enable */
6668 uint32_t CH74:1; /* Channel 74 Injected Sampling Enable */
6669 uint32_t CH73:1; /* Channel 73 Injected Sampling Enable */
6670 uint32_t CH72:1; /* Channel 72 Injected Sampling Enable */
6671 uint32_t CH71:1; /* Channel 71 Injected Sampling Enable */
6672 uint32_t CH70:1; /* Channel 70 Injected Sampling Enable */
6673 uint32_t CH69:1; /* Channel 69 Injected Sampling Enable */
6674 uint32_t CH68:1; /* Channel 68 Injected Sampling Enable */
6675 uint32_t CH67:1; /* Channel 67 Injected Sampling Enable */
6676 uint32_t CH66:1; /* Channel 66 Injected Sampling Enable */
6677 uint32_t CH65:1; /* Channel 65 Injected Sampling Enable */
6678 uint32_t CH64:1; /* Channel 64 Injected Sampling Enable */
6679 } B;
6680 } ADC_JCMR2_32B_tag;
6681
6682 typedef union { /* Offset Word Regsiter */
6683 uint32_t R;
6684 struct {
6685 uint32_t:15;
6686 uint32_t OFFSETLOAD:1; /* load_offset */
6687 uint32_t:8;
6688#ifndef USE_FIELD_ALIASES_ADC
6689 uint32_t OFFSET_WORD:8; /* OFFSET word coeff.generated at the end of offset cancellation is lathed int o this register */
6690#else
6691 uint32_t OFFSETWORD:8;
6692#endif
6693 } B;
6694 } ADC_OFFWR_32B_tag;
6695
6696 typedef union { /* Decode Signal Delay Register */
6697 uint32_t R;
6698 struct {
6699 uint32_t:24;
6700 uint32_t DSD:8; /* take into account the settling time of the external mux */
6701 } B;
6702 } ADC_DSDR_32B_tag;
6703
6704 typedef union { /* Power Down Dealy Register */
6705 uint32_t R;
6706 struct {
6707 uint32_t:24;
6708 uint32_t PDED:8; /* The delay between the power down bit reset and the starting of conversion */
6709 } B;
6710 } ADC_PDEDR_32B_tag;
6711
6712
6713 /* Register layout for all registers CDR... */
6714
6715 typedef union { /* CHANNEL DATA REGS */
6716 uint32_t R;
6717 struct {
6718 uint32_t:12;
6719 uint32_t VALID:1; /* validity of data */
6720 uint32_t OVERW:1; /* overwrite data */
6721 uint32_t RESULT:2; /* reflects mode conversion */
6722 uint32_t:6;
6723 uint32_t CDATA:10; /* Channel 0 converted data */
6724 } B;
6725 } ADC_CDR_32B_tag;
6726
6727 typedef union { /* Upper Threshold register 4 is not contiguous to 3 */
6728 uint32_t R;
6729 struct {
6730 uint32_t:4;
6731 uint32_t THRH:12; /* high threshold value s */
6732 uint32_t:4;
6733 uint32_t THRL:12; /* low threshold value s */
6734 } B;
6735 } ADC_THRHLR4_32B_tag;
6736
6737 typedef union { /* Upper Threshold register 5 */
6738 uint32_t R;
6739 struct {
6740 uint32_t:4;
6741 uint32_t THRH:12; /* high threshold value s */
6742 uint32_t:4;
6743 uint32_t THRL:12; /* low threshold value s */
6744 } B;
6745 } ADC_THRHLR5_32B_tag;
6746
6747 typedef union { /* Upper Threshold register 6 */
6748 uint32_t R;
6749 struct {
6750 uint32_t:4;
6751 uint32_t THRH:12; /* high threshold value s */
6752 uint32_t:4;
6753 uint32_t THRL:12; /* low threshold value s */
6754 } B;
6755 } ADC_THRHLR6_32B_tag;
6756
6757 typedef union { /* Upper Threshold register 7 */
6758 uint32_t R;
6759 struct {
6760 uint32_t:4;
6761 uint32_t THRH:12; /* high threshold value s */
6762 uint32_t:4;
6763 uint32_t THRL:12; /* low threshold value s */
6764 } B;
6765 } ADC_THRHLR7_32B_tag;
6766
6767 typedef union { /* Upper Threshold register 8 */
6768 uint32_t R;
6769 struct {
6770 uint32_t:4;
6771 uint32_t THRH:12; /* high threshold value s */
6772 uint32_t:4;
6773 uint32_t THRL:12; /* low threshold value s */
6774 } B;
6775 } ADC_THRHLR8_32B_tag;
6776
6777 typedef union { /* Upper Threshold register 9 */
6778 uint32_t R;
6779 struct {
6780 uint32_t:4;
6781 uint32_t THRH:12; /* high threshold value s */
6782 uint32_t:4;
6783 uint32_t THRL:12; /* low threshold value s */
6784 } B;
6785 } ADC_THRHLR9_32B_tag;
6786
6787 typedef union { /* Upper Threshold register 10 */
6788 uint32_t R;
6789 struct {
6790 uint32_t:4;
6791 uint32_t THRH:12; /* high threshold value s */
6792 uint32_t:4;
6793 uint32_t THRL:12; /* low threshold value s */
6794 } B;
6795 } ADC_THRHLR10_32B_tag;
6796
6797 typedef union { /* Upper Threshold register 11 */
6798 uint32_t R;
6799 struct {
6800 uint32_t:4;
6801 uint32_t THRH:12; /* high threshold value s */
6802 uint32_t:4;
6803 uint32_t THRL:12; /* low threshold value s */
6804 } B;
6805 } ADC_THRHLR11_32B_tag;
6806
6807 typedef union { /* Upper Threshold register 12 */
6808 uint32_t R;
6809 struct {
6810 uint32_t:4;
6811 uint32_t THRH:12; /* high threshold value s */
6812 uint32_t:4;
6813 uint32_t THRL:12; /* low threshold value s */
6814 } B;
6815 } ADC_THRHLR12_32B_tag;
6816
6817 typedef union { /* Upper Threshold register 13 */
6818 uint32_t R;
6819 struct {
6820 uint32_t:4;
6821 uint32_t THRH:12; /* high threshold value s */
6822 uint32_t:4;
6823 uint32_t THRL:12; /* low threshold value s */
6824 } B;
6825 } ADC_THRHLR13_32B_tag;
6826
6827 typedef union { /* Upper Threshold register 14 */
6828 uint32_t R;
6829 struct {
6830 uint32_t:4;
6831 uint32_t THRH:12; /* high threshold value s */
6832 uint32_t:4;
6833 uint32_t THRL:12; /* low threshold value s */
6834 } B;
6835 } ADC_THRHLR14_32B_tag;
6836
6837 typedef union { /* Upper Threshold register 15 */
6838 uint32_t R;
6839 struct {
6840 uint32_t:4;
6841 uint32_t THRH:12; /* high threshold value s */
6842 uint32_t:4;
6843 uint32_t THRL:12; /* low threshold value s */
6844 } B;
6845 } ADC_THRHLR15_32B_tag;
6846
6847
6848 /* Register layout for all registers CWSELR... */
6849
6850 typedef union { /* Channel Watchdog Select register */
6851 uint32_t R;
6852 struct {
6853 uint32_t WSEL_CH7:4; /* Channel Watchdog select for channel 7+R*8 */
6854 uint32_t WSEL_CH6:4; /* Channel Watchdog select for channel 6+R*8 */
6855 uint32_t WSEL_CH5:4; /* Channel Watchdog select for channel 5+R*8 */
6856 uint32_t WSEL_CH4:4; /* Channel Watchdog select for channel 4+R*8 */
6857 uint32_t WSEL_CH3:4; /* Channel Watchdog select for channel 3+R*8 */
6858 uint32_t WSEL_CH2:4; /* Channel Watchdog select for channel 2+R*8 */
6859 uint32_t WSEL_CH1:4; /* Channel Watchdog select for channel 1+R*8 */
6860 uint32_t WSEL_CH0:4; /* Channel Watchdog select for channel 0+R*8 */
6861 } B;
6862 } ADC_CWSELR_32B_tag;
6863
6864
6865 /* Register layout for all registers CWENR... */
6866
6867 typedef union { /* Channel Watchdog Enable Register */
6868 uint32_t R;
6869 struct {
6870 uint32_t:16;
6871 uint32_t CWEN15PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6872 uint32_t CWEN14PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6873 uint32_t CWEN13PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6874 uint32_t CWEN12PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6875 uint32_t CWEN11PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6876 uint32_t CWEN10PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6877 uint32_t CWEN09PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6878 uint32_t CWEN08PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6879 uint32_t CWEN07PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6880 uint32_t CWEN06PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6881 uint32_t CWEN05PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6882 uint32_t CWEN04PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6883 uint32_t CWEN03PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6884 uint32_t CWEN02PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6885 uint32_t CWEN01PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6886 uint32_t CWEN00PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6887 } B;
6888 } ADC_CWENR_32B_tag;
6889
6890
6891 /* Register layout for all registers AWORR... */
6892
6893 typedef union { /* Analog Watchdog Out of Range Register */
6894 uint32_t R;
6895 struct {
6896 uint32_t AWOR_CH31:1; /* Channel 31+R*32 converted data out of range */
6897 uint32_t AWOR_CH30:1; /* Channel 30+R*32 converted data out of range */
6898 uint32_t AWOR_CH29:1; /* Channel 29+R*32 converted data out of range */
6899 uint32_t AWOR_CH28:1; /* Channel 28+R*32 converted data out of range */
6900 uint32_t AWOR_CH27:1; /* Channel 27+R*32 converted data out of range */
6901 uint32_t AWOR_CH26:1; /* Channel 26+R*32 converted data out of range */
6902 uint32_t AWOR_CH25:1; /* Channel 25+R*32 converted data out of range */
6903 uint32_t AWOR_CH24:1; /* Channel 24+R*32 converted data out of range */
6904 uint32_t AWOR_CH23:1; /* Channel 23+R*32 converted data out of range */
6905 uint32_t AWOR_CH22:1; /* Channel 22+R*32 converted data out of range */
6906 uint32_t AWOR_CH21:1; /* Channel 21+R*32 converted data out of range */
6907 uint32_t AWOR_CH20:1; /* Channel 20+R*32 converted data out of range */
6908 uint32_t AWOR_CH19:1; /* Channel 19+R*32 converted data out of range */
6909 uint32_t AWOR_CH18:1; /* Channel 18+R*32 converted data out of range */
6910 uint32_t AWOR_CH17:1; /* Channel 17+R*32 converted data out of range */
6911 uint32_t AWOR_CH16:1; /* Channel 16+R*32 converted data out of range */
6912 uint32_t AWOR_CH15:1; /* Channel 15+R*32 converted data out of range */
6913 uint32_t AWOR_CH14:1; /* Channel 14+R*32 converted data out of range */
6914 uint32_t AWOR_CH13:1; /* Channel 13+R*32 converted data out of range */
6915 uint32_t AWOR_CH12:1; /* Channel 12+R*32 converted data out of range */
6916 uint32_t AWOR_CH11:1; /* Channel 11+R*32 converted data out of range */
6917 uint32_t AWOR_CH10:1; /* Channel 10+R*32 converted data out of range */
6918 uint32_t AWOR_CH9:1; /* Channel 9+R*32 converted data out of range */
6919 uint32_t AWOR_CH8:1; /* Channel 8+R*32 converted data out of range */
6920 uint32_t AWOR_CH7:1; /* Channel 7+R*32 converted data out of range */
6921 uint32_t AWOR_CH6:1; /* Channel 6+R*32 converted data out of range */
6922 uint32_t AWOR_CH5:1; /* Channel 5+R*32 converted data out of range */
6923 uint32_t AWOR_CH4:1; /* Channel 4+R*32 converted data out of range */
6924 uint32_t AWOR_CH3:1; /* Channel 3+R*32 converted data out of range */
6925 uint32_t AWOR_CH2:1; /* Channel 2+R*32 converted data out of range */
6926 uint32_t AWOR_CH1:1; /* Channel 1+R*32 converted data out of range */
6927 uint32_t AWOR_CH0:1; /* Channel 0+R*32 converted data out of range */
6928 } B;
6929 } ADC_AWORR_32B_tag;
6930
6931 typedef union { /* SELF TEST CONFIGURATION REGISTER 1 */
6932 uint32_t R;
6933 struct {
6934 uint32_t INPSAMP_C:8; /* Sampling phase duration for the test conversions - algorithm C */
6935 uint32_t INPSAMP_RC:8; /* Sampling phase duration for the test conversions - algorithm RC */
6936 uint32_t INPSAMP_S:8; /* Sampling phase duration for the test conversions - algorithm S */
6937 uint32_t:5;
6938 uint32_t ST_INPCMP:2; /* Configuration bit for comparison phase duration for self test channel */
6939 uint32_t ST_INPLATCH:1; /* Configuration bit for Latching phase duration for self test channel */
6940 } B;
6941 } ADC_STCR1_32B_tag;
6942
6943 typedef union { /* SELF TEST CONFIGURATION REGISTER 2 */
6944 uint32_t R;
6945 struct {
6946 uint32_t:5;
6947 uint32_t SERR:1; /* Error fault injection bit (write only) */
6948 uint32_t MSKSTWDTERR:1; /* Interrupt enable (STSR2.WDTERR status bit) */
6949 uint32_t:1;
6950 uint32_t MSKST_EOC:1; /* Interrupt enable bit for STSR2.ST_EOC */
6951 uint32_t:4;
6952 uint32_t MSKWDG_EOA_C:1; /* Interrupt enable (WDG_EOA_C status bit) */
6953 uint32_t MSKWDG_EOA_RC:1; /* Interrupt enable (WDG_EOA_RC status bit) */
6954 uint32_t MSKWDG_EOA_S:1; /* Interrupt enable (WDG_EOA_S status bit) */
6955 uint32_t MSKERR_C:1; /* Interrupt enable (ERR_C status bit) */
6956 uint32_t MSKERR_RC:1; /* Interrupt enable (ERR_RC status bit) */
6957 uint32_t MSKERR_S2:1; /* Interrupt enable (ERR_S2 status bit) */
6958 uint32_t MSKERR_S1:1; /* Interrupt enable (ERR_S1 status bit) */
6959 uint32_t MSKERR_S0:1; /* Interrupt enable (ERR_S0 status bit) */
6960 uint32_t:3;
6961 uint32_t EN:1; /* Self testing channel enable */
6962 uint32_t:4;
6963 uint32_t FMA_C:1; /* Fault mapping for the algorithm C */
6964 uint32_t FMAR_C:1; /* Fault mapping for the algorithm RC */
6965 uint32_t FMA_S:1; /* Fault mapping for the algorithm BGAP */
6966 } B;
6967 } ADC_STCR2_32B_tag;
6968
6969 typedef union { /* SELF TEST CONFIGURATION REGISTER 3 */
6970 uint32_t R;
6971 struct {
6972 uint32_t:22;
6973 uint32_t ALG:2; /* Algorithm scheduling */
6974 uint32_t:8;
6975 } B;
6976 } ADC_STCR3_32B_tag;
6977
6978 typedef union { /* SELF TEST BAUD RATE REGISTER */
6979 uint32_t R;
6980 struct {
6981 uint32_t:13;
6982 uint32_t WDT:3; /* Watchdog timer value */
6983 uint32_t:8;
6984 uint32_t BR:8; /* Baud rate for the selected algorithm in SCAN mode */
6985 } B;
6986 } ADC_STBRR_32B_tag;
6987
6988 typedef union { /* SELF TEST STATUS REGISTER 1 */
6989 uint32_t R;
6990 struct {
6991 uint32_t:6;
6992 uint32_t WDTERR:1; /* Watchdog timer error */
6993 uint32_t OVERWR:1; /* Overwrite error */
6994 uint32_t ST_EOC:1; /* Self test EOC bit */
6995 uint32_t:4;
6996 uint32_t WDG_EOA_C:1; /* Algorithm C completed without error */
6997 uint32_t WDG_EOA_RC:1; /* Algorithm RC completed without error */
6998 uint32_t WDG_EOA_S:1; /* Algorithm S completed without error */
6999 uint32_t ERR_C:1; /* Error on the self testing channel (algorithm C) */
7000 uint32_t ERR_RC:1; /* Error on the self testing channel (algorithm RC) */
7001 uint32_t ERR_S2:1; /* Error on the self testing channel (algorithm SUPPLY, step 2) */
7002 uint32_t ERR_S1:1; /* Error on the self testing channel (algorithm SUPPLY, step 1) */
7003 uint32_t ERR_S0:1; /* Error on the self testing channel (algorithm SUPPLY, step 0) */
7004 uint32_t:1;
7005 uint32_t STEP_C:5; /* Step of algorithm C when ERR_C has occurred */
7006 uint32_t STEP_RC:5; /* Step of algorithm RC when ERR_RC has occurred */
7007 } B;
7008 } ADC_STSR1_32B_tag;
7009
7010 typedef union { /* SELF TEST STATUS REGISTER 2 */
7011 uint32_t R;
7012 struct {
7013 uint32_t OVFL:1; /* Overflow bit */
7014 uint32_t:3;
7015 uint32_t DATA1:12; /* Test channel converted data when ERR_S1 has occurred */
7016 uint32_t:4;
7017 uint32_t DATA0:12; /* Test channel converted data when ERR_S1 has occurred */
7018 } B;
7019 } ADC_STSR2_32B_tag;
7020
7021 typedef union { /* SELF TEST STATUS REGISTER 3 */
7022 uint32_t R;
7023 struct {
7024 uint32_t:4;
7025 uint32_t DATA1:12; /* Test channel converted data when ERR_S0 has occurred */
7026 uint32_t:4;
7027 uint32_t DATA0:12; /* Test channel converted data when ERR_S0 has occurred */
7028 } B;
7029 } ADC_STSR3_32B_tag;
7030
7031 typedef union { /* SELF TEST STATUS REGISTER 4 */
7032 uint32_t R;
7033 struct {
7034 uint32_t:4;
7035 uint32_t DATA1:12; /* Test channel converted data when ERR_C has occurred */
7036 uint32_t:4;
7037 uint32_t DATA0:12; /* Test channel converted data when ERR_C has occurred */
7038 } B;
7039 } ADC_STSR4_32B_tag;
7040
7041 typedef union { /* SELF TEST DATA REGISTER 1 */
7042 uint32_t R;
7043 struct {
7044 uint32_t:12;
7045 uint32_t VALID:1; /* Valid data */
7046 uint32_t OVERWR:1; /* Overwrite data */
7047 uint32_t:6;
7048 uint32_t TCDATA:12; /* Test channel converted data */
7049 } B;
7050 } ADC_STDR1_32B_tag;
7051
7052 typedef union { /* SELF TEST DATA REGISTER 2 */
7053 uint32_t R;
7054 struct {
7055 uint32_t FDATA:12; /* Fractional part of the ratio TEST for algorithm S */
7056 uint32_t VALID:1; /* Valid data */
7057 uint32_t OVERWR:1; /* Overwrite data */
7058 uint32_t:6;
7059 uint32_t IDATA:12; /* Integer part of the ratio TEST for algorithm S */
7060 } B;
7061 } ADC_STDR2_32B_tag;
7062
7063 typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 0 */
7064 uint32_t R;
7065 struct {
7066 uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */
7067 uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm S */
7068 uint32_t:2;
7069 uint32_t THRH:12; /* High threshold value for channel 0 */
7070 uint32_t:4;
7071 uint32_t THRL:12; /* Low threshold value for channel 0 */
7072 } B;
7073 } ADC_STAW0R_32B_tag;
7074
7075 typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1A */
7076 uint32_t R;
7077 struct {
7078 uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */
7079 uint32_t:3;
7080 uint32_t THRH:12; /* High threshold value for test channel - algorithm S */
7081 uint32_t:4;
7082 uint32_t THRL:12; /* Low threshold value for test channel - algorithm S */
7083 } B;
7084 } ADC_STAW1AR_32B_tag;
7085
7086 typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1B */
7087 uint32_t R;
7088 struct {
7089 uint32_t:4;
7090 uint32_t THRH:12; /* High threshold value for test channel - algorithm S */
7091 uint32_t:4;
7092 uint32_t THRL:12; /* Low threshold value for test channel - algorithm S */
7093 } B;
7094 } ADC_STAW1BR_32B_tag;
7095
7096 typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 2 */
7097 uint32_t R;
7098 struct {
7099 uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */
7100 uint32_t:19;
7101 uint32_t THRL:12; /* Low threshold value for channel */
7102 } B;
7103 } ADC_STAW2R_32B_tag;
7104
7105 typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 3 */
7106 uint32_t R;
7107 struct {
7108 uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm RC */
7109 uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm RC */
7110 uint32_t:2;
7111 uint32_t THRH:12; /* High threshold value for channel 3 */
7112 uint32_t:4;
7113 uint32_t THRL:12; /* Low threshold value for channel 3 */
7114 } B;
7115 } ADC_STAW3R_32B_tag;
7116
7117 typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 4 */
7118 uint32_t R;
7119 struct {
7120 uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm C */
7121 uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm C */
7122 uint32_t:2;
7123 uint32_t THRH:12; /* High threshold value for channel 4 */
7124 uint32_t:4;
7125 uint32_t THRL:12; /* Low threshold value for channel 4 */
7126 } B;
7127 } ADC_STAW4R_32B_tag;
7128
7129 typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 5 */
7130 uint32_t R;
7131 struct {
7132 uint32_t:4;
7133 uint32_t THRH:12; /* High threshold value for algorithm C */
7134 uint32_t:4;
7135 uint32_t THRL:12; /* Low threshold value for algorithm C */
7136 } B;
7137 } ADC_STAW5R_32B_tag;
7138
7139
7140
7141 typedef struct ADC_struct_tag { /* start of ADC_tag */
7142 /* module configuration register */
7143 ADC_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */
7144 /* module status register */
7145 ADC_MSR_32B_tag MSR; /* offset: 0x0004 size: 32 bit */
7146 int8_t ADC_reserved_0008[8];
7147 /* Interrupt status register */
7148 ADC_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */
7149 union {
7150 ADC_CEOCFR0_32B_tag CEOCFR[3]; /* offset: 0x0014 (0x0004 x 3) */
7151
7152 struct {
7153 /* CHANNEL PENDING REGISTER 0 */
7154 ADC_CEOCFR0_32B_tag CEOCFR0; /* offset: 0x0014 size: 32 bit */
7155 /* CHANNEL PENDING REGISTER 1 */
7156 ADC_CEOCFR1_32B_tag CEOCFR1; /* offset: 0x0018 size: 32 bit */
7157 /* CHANNEL PENDING REGISTER 2 */
7158 ADC_CEOCFR2_32B_tag CEOCFR2; /* offset: 0x001C size: 32 bit */
7159 };
7160
7161 };
7162 /* interrupt mask register */
7163 ADC_IMR_32B_tag IMR; /* offset: 0x0020 size: 32 bit */
7164 union {
7165 ADC_CIMR0_32B_tag CIMR[3]; /* offset: 0x0024 (0x0004 x 3) */
7166
7167 struct {
7168 /* CHANNEL INTERRUPT MASK REGISTER 0 */
7169 ADC_CIMR0_32B_tag CIMR0; /* offset: 0x0024 size: 32 bit */
7170 /* CHANNEL INTERRUPT MASK REGISTER 1 */
7171 ADC_CIMR1_32B_tag CIMR1; /* offset: 0x0028 size: 32 bit */
7172 /* CHANNEL INTERRUPT MASK REGISTER 2 */
7173 ADC_CIMR2_32B_tag CIMR2; /* offset: 0x002C size: 32 bit */
7174 };
7175
7176 };
7177 /* Watchdog Threshold interrupt status register */
7178 ADC_WTISR_32B_tag WTISR; /* offset: 0x0030 size: 32 bit */
7179 /* Watchdog interrupt MASK register */
7180 ADC_WTIMR_32B_tag WTIMR; /* offset: 0x0034 size: 32 bit */
7181 int8_t ADC_reserved_0038[8];
7182 /* DMAE register */
7183 ADC_DMAE_32B_tag DMAE; /* offset: 0x0040 size: 32 bit */
7184 union {
7185 ADC_DMAR0_32B_tag DMAR[3]; /* offset: 0x0044 (0x0004 x 3) */
7186
7187 struct {
7188 /* DMA REGISTER 0 */
7189 ADC_DMAR0_32B_tag DMAR0; /* offset: 0x0044 size: 32 bit */
7190 /* DMA REGISTER 1 */
7191 ADC_DMAR1_32B_tag DMAR1; /* offset: 0x0048 size: 32 bit */
7192 /* DMA REGISTER 2 */
7193 ADC_DMAR2_32B_tag DMAR2; /* offset: 0x004C size: 32 bit */
7194 };
7195
7196 };
7197 union {
7198 /* Threshold Control register C */
7199 ADC_TRC_32B_tag TRC[4]; /* offset: 0x0050 (0x0004 x 4) */
7200
7201 struct {
7202 /* Threshold Control register C */
7203 ADC_TRC_32B_tag TRC0; /* offset: 0x0050 size: 32 bit */
7204 ADC_TRC_32B_tag TRC1; /* offset: 0x0054 size: 32 bit */
7205 ADC_TRC_32B_tag TRC2; /* offset: 0x0058 size: 32 bit */
7206 ADC_TRC_32B_tag TRC3; /* offset: 0x005C size: 32 bit */
7207 };
7208
7209 };
7210 union {
7211 /* Upper Threshold register */
7212 ADC_THRHLR_32B_tag THRHLR[4]; /* offset: 0x0060 (0x0004 x 4) */
7213
7214 struct {
7215 /* Upper Threshold register */
7216 ADC_THRHLR_32B_tag THRHLR0; /* offset: 0x0060 size: 32 bit */
7217 ADC_THRHLR_32B_tag THRHLR1; /* offset: 0x0064 size: 32 bit */
7218 ADC_THRHLR_32B_tag THRHLR2; /* offset: 0x0068 size: 32 bit */
7219 ADC_THRHLR_32B_tag THRHLR3; /* offset: 0x006C size: 32 bit */
7220 };
7221
7222 };
7223 union {
7224 /* alternate Upper Threshold register */
7225 ADC_THRALT_32B_tag THRALT[4]; /* offset: 0x0070 (0x0004 x 4) */
7226
7227 struct {
7228 /* alternate Upper Threshold register */
7229 ADC_THRALT_32B_tag THRALT0; /* offset: 0x0070 size: 32 bit */
7230 ADC_THRALT_32B_tag THRALT1; /* offset: 0x0074 size: 32 bit */
7231 ADC_THRALT_32B_tag THRALT2; /* offset: 0x0078 size: 32 bit */
7232 ADC_THRALT_32B_tag THRALT3; /* offset: 0x007C size: 32 bit */
7233 };
7234
7235 };
7236 /* PRESAMPLING CONTROL REGISTER */
7237 ADC_PSCR_32B_tag PSCR; /* offset: 0x0080 size: 32 bit */
7238 union {
7239 ADC_PSR0_32B_tag PSR[3]; /* offset: 0x0084 (0x0004 x 3) */
7240
7241 struct {
7242 /* Presampling Register 0 */
7243 ADC_PSR0_32B_tag PSR0; /* offset: 0x0084 size: 32 bit */
7244 /* Presampling REGISTER 1 */
7245 ADC_PSR1_32B_tag PSR1; /* offset: 0x0088 size: 32 bit */
7246 /* Presampling REGISTER 2 */
7247 ADC_PSR2_32B_tag PSR2; /* offset: 0x008C size: 32 bit */
7248 };
7249
7250 };
7251 int8_t ADC_reserved_0090_C[4];
7252 union {
7253 /* conversion timing register */
7254 ADC_CTR_32B_tag CTR[3]; /* offset: 0x0094 (0x0004 x 3) */
7255
7256 struct {
7257 /* conversion timing register */
7258 ADC_CTR_32B_tag CTR0; /* offset: 0x0094 size: 32 bit */
7259 ADC_CTR_32B_tag CTR1; /* offset: 0x0098 size: 32 bit */
7260 ADC_CTR_32B_tag CTR2; /* offset: 0x009C size: 32 bit */
7261 };
7262
7263 };
7264 int8_t ADC_reserved_00A0_C[4];
7265 union {
7266 ADC_NCMR0_32B_tag NCMR[3]; /* offset: 0x00A4 (0x0004 x 3) */
7267
7268 struct {
7269 /* NORMAL CONVERSION MASK REGISTER 0 */
7270 ADC_NCMR0_32B_tag NCMR0; /* offset: 0x00A4 size: 32 bit */
7271 /* NORMAL CONVERSION MASK REGISTER 1 */
7272 ADC_NCMR1_32B_tag NCMR1; /* offset: 0x00A8 size: 32 bit */
7273 /* NORMAL CONVERSION MASK REGISTER 2 */
7274 ADC_NCMR2_32B_tag NCMR2; /* offset: 0x00AC size: 32 bit */
7275 };
7276
7277 };
7278 int8_t ADC_reserved_00B0_C[4];
7279 union {
7280 ADC_JCMR0_32B_tag JCMR[3]; /* offset: 0x00B4 (0x0004 x 3) */
7281
7282 struct {
7283 /* Injected Conversion Mask Register 0 */
7284 ADC_JCMR0_32B_tag JCMR0; /* offset: 0x00B4 size: 32 bit */
7285 /* INJECTED CONVERSION MASK REGISTER 1 */
7286 ADC_JCMR1_32B_tag JCMR1; /* offset: 0x00B8 size: 32 bit */
7287 /* INJECTED CONVERSION MASK REGISTER 2 */
7288 ADC_JCMR2_32B_tag JCMR2; /* offset: 0x00BC size: 32 bit */
7289 };
7290
7291 };
7292 /* Offset Word Regsiter */
7293 ADC_OFFWR_32B_tag OFFWR; /* offset: 0x00C0 size: 32 bit */
7294 /* Decode Signal Delay Register */
7295 ADC_DSDR_32B_tag DSDR; /* offset: 0x00C4 size: 32 bit */
7296 /* Power Down Dealy Register */
7297 ADC_PDEDR_32B_tag PDEDR; /* offset: 0x00C8 size: 32 bit */
7298 int8_t ADC_reserved_00CC_C[52];
7299 union {
7300 /* CHANNEL DATA REGS */
7301 ADC_CDR_32B_tag CDR[96]; /* offset: 0x0100 (0x0004 x 96) */
7302
7303 struct {
7304 /* CHANNEL DATA REGS */
7305 ADC_CDR_32B_tag CDR0; /* offset: 0x0100 size: 32 bit */
7306 ADC_CDR_32B_tag CDR1; /* offset: 0x0104 size: 32 bit */
7307 ADC_CDR_32B_tag CDR2; /* offset: 0x0108 size: 32 bit */
7308 ADC_CDR_32B_tag CDR3; /* offset: 0x010C size: 32 bit */
7309 ADC_CDR_32B_tag CDR4; /* offset: 0x0110 size: 32 bit */
7310 ADC_CDR_32B_tag CDR5; /* offset: 0x0114 size: 32 bit */
7311 ADC_CDR_32B_tag CDR6; /* offset: 0x0118 size: 32 bit */
7312 ADC_CDR_32B_tag CDR7; /* offset: 0x011C size: 32 bit */
7313 ADC_CDR_32B_tag CDR8; /* offset: 0x0120 size: 32 bit */
7314 ADC_CDR_32B_tag CDR9; /* offset: 0x0124 size: 32 bit */
7315 ADC_CDR_32B_tag CDR10; /* offset: 0x0128 size: 32 bit */
7316 ADC_CDR_32B_tag CDR11; /* offset: 0x012C size: 32 bit */
7317 ADC_CDR_32B_tag CDR12; /* offset: 0x0130 size: 32 bit */
7318 ADC_CDR_32B_tag CDR13; /* offset: 0x0134 size: 32 bit */
7319 ADC_CDR_32B_tag CDR14; /* offset: 0x0138 size: 32 bit */
7320 ADC_CDR_32B_tag CDR15; /* offset: 0x013C size: 32 bit */
7321 ADC_CDR_32B_tag CDR16; /* offset: 0x0140 size: 32 bit */
7322 ADC_CDR_32B_tag CDR17; /* offset: 0x0144 size: 32 bit */
7323 ADC_CDR_32B_tag CDR18; /* offset: 0x0148 size: 32 bit */
7324 ADC_CDR_32B_tag CDR19; /* offset: 0x014C size: 32 bit */
7325 ADC_CDR_32B_tag CDR20; /* offset: 0x0150 size: 32 bit */
7326 ADC_CDR_32B_tag CDR21; /* offset: 0x0154 size: 32 bit */
7327 ADC_CDR_32B_tag CDR22; /* offset: 0x0158 size: 32 bit */
7328 ADC_CDR_32B_tag CDR23; /* offset: 0x015C size: 32 bit */
7329 ADC_CDR_32B_tag CDR24; /* offset: 0x0160 size: 32 bit */
7330 ADC_CDR_32B_tag CDR25; /* offset: 0x0164 size: 32 bit */
7331 ADC_CDR_32B_tag CDR26; /* offset: 0x0168 size: 32 bit */
7332 ADC_CDR_32B_tag CDR27; /* offset: 0x016C size: 32 bit */
7333 ADC_CDR_32B_tag CDR28; /* offset: 0x0170 size: 32 bit */
7334 ADC_CDR_32B_tag CDR29; /* offset: 0x0174 size: 32 bit */
7335 ADC_CDR_32B_tag CDR30; /* offset: 0x0178 size: 32 bit */
7336 ADC_CDR_32B_tag CDR31; /* offset: 0x017C size: 32 bit */
7337 ADC_CDR_32B_tag CDR32; /* offset: 0x0180 size: 32 bit */
7338 ADC_CDR_32B_tag CDR33; /* offset: 0x0184 size: 32 bit */
7339 ADC_CDR_32B_tag CDR34; /* offset: 0x0188 size: 32 bit */
7340 ADC_CDR_32B_tag CDR35; /* offset: 0x018C size: 32 bit */
7341 ADC_CDR_32B_tag CDR36; /* offset: 0x0190 size: 32 bit */
7342 ADC_CDR_32B_tag CDR37; /* offset: 0x0194 size: 32 bit */
7343 ADC_CDR_32B_tag CDR38; /* offset: 0x0198 size: 32 bit */
7344 ADC_CDR_32B_tag CDR39; /* offset: 0x019C size: 32 bit */
7345 ADC_CDR_32B_tag CDR40; /* offset: 0x01A0 size: 32 bit */
7346 ADC_CDR_32B_tag CDR41; /* offset: 0x01A4 size: 32 bit */
7347 ADC_CDR_32B_tag CDR42; /* offset: 0x01A8 size: 32 bit */
7348 ADC_CDR_32B_tag CDR43; /* offset: 0x01AC size: 32 bit */
7349 ADC_CDR_32B_tag CDR44; /* offset: 0x01B0 size: 32 bit */
7350 ADC_CDR_32B_tag CDR45; /* offset: 0x01B4 size: 32 bit */
7351 ADC_CDR_32B_tag CDR46; /* offset: 0x01B8 size: 32 bit */
7352 ADC_CDR_32B_tag CDR47; /* offset: 0x01BC size: 32 bit */
7353 ADC_CDR_32B_tag CDR48; /* offset: 0x01C0 size: 32 bit */
7354 ADC_CDR_32B_tag CDR49; /* offset: 0x01C4 size: 32 bit */
7355 ADC_CDR_32B_tag CDR50; /* offset: 0x01C8 size: 32 bit */
7356 ADC_CDR_32B_tag CDR51; /* offset: 0x01CC size: 32 bit */
7357 ADC_CDR_32B_tag CDR52; /* offset: 0x01D0 size: 32 bit */
7358 ADC_CDR_32B_tag CDR53; /* offset: 0x01D4 size: 32 bit */
7359 ADC_CDR_32B_tag CDR54; /* offset: 0x01D8 size: 32 bit */
7360 ADC_CDR_32B_tag CDR55; /* offset: 0x01DC size: 32 bit */
7361 ADC_CDR_32B_tag CDR56; /* offset: 0x01E0 size: 32 bit */
7362 ADC_CDR_32B_tag CDR57; /* offset: 0x01E4 size: 32 bit */
7363 ADC_CDR_32B_tag CDR58; /* offset: 0x01E8 size: 32 bit */
7364 ADC_CDR_32B_tag CDR59; /* offset: 0x01EC size: 32 bit */
7365 ADC_CDR_32B_tag CDR60; /* offset: 0x01F0 size: 32 bit */
7366 ADC_CDR_32B_tag CDR61; /* offset: 0x01F4 size: 32 bit */
7367 ADC_CDR_32B_tag CDR62; /* offset: 0x01F8 size: 32 bit */
7368 ADC_CDR_32B_tag CDR63; /* offset: 0x01FC size: 32 bit */
7369 ADC_CDR_32B_tag CDR64; /* offset: 0x0200 size: 32 bit */
7370 ADC_CDR_32B_tag CDR65; /* offset: 0x0204 size: 32 bit */
7371 ADC_CDR_32B_tag CDR66; /* offset: 0x0208 size: 32 bit */
7372 ADC_CDR_32B_tag CDR67; /* offset: 0x020C size: 32 bit */
7373 ADC_CDR_32B_tag CDR68; /* offset: 0x0210 size: 32 bit */
7374 ADC_CDR_32B_tag CDR69; /* offset: 0x0214 size: 32 bit */
7375 ADC_CDR_32B_tag CDR70; /* offset: 0x0218 size: 32 bit */
7376 ADC_CDR_32B_tag CDR71; /* offset: 0x021C size: 32 bit */
7377 ADC_CDR_32B_tag CDR72; /* offset: 0x0220 size: 32 bit */
7378 ADC_CDR_32B_tag CDR73; /* offset: 0x0224 size: 32 bit */
7379 ADC_CDR_32B_tag CDR74; /* offset: 0x0228 size: 32 bit */
7380 ADC_CDR_32B_tag CDR75; /* offset: 0x022C size: 32 bit */
7381 ADC_CDR_32B_tag CDR76; /* offset: 0x0230 size: 32 bit */
7382 ADC_CDR_32B_tag CDR77; /* offset: 0x0234 size: 32 bit */
7383 ADC_CDR_32B_tag CDR78; /* offset: 0x0238 size: 32 bit */
7384 ADC_CDR_32B_tag CDR79; /* offset: 0x023C size: 32 bit */
7385 ADC_CDR_32B_tag CDR80; /* offset: 0x0240 size: 32 bit */
7386 ADC_CDR_32B_tag CDR81; /* offset: 0x0244 size: 32 bit */
7387 ADC_CDR_32B_tag CDR82; /* offset: 0x0248 size: 32 bit */
7388 ADC_CDR_32B_tag CDR83; /* offset: 0x024C size: 32 bit */
7389 ADC_CDR_32B_tag CDR84; /* offset: 0x0250 size: 32 bit */
7390 ADC_CDR_32B_tag CDR85; /* offset: 0x0254 size: 32 bit */
7391 ADC_CDR_32B_tag CDR86; /* offset: 0x0258 size: 32 bit */
7392 ADC_CDR_32B_tag CDR87; /* offset: 0x025C size: 32 bit */
7393 ADC_CDR_32B_tag CDR88; /* offset: 0x0260 size: 32 bit */
7394 ADC_CDR_32B_tag CDR89; /* offset: 0x0264 size: 32 bit */
7395 ADC_CDR_32B_tag CDR90; /* offset: 0x0268 size: 32 bit */
7396 ADC_CDR_32B_tag CDR91; /* offset: 0x026C size: 32 bit */
7397 ADC_CDR_32B_tag CDR92; /* offset: 0x0270 size: 32 bit */
7398 ADC_CDR_32B_tag CDR93; /* offset: 0x0274 size: 32 bit */
7399 ADC_CDR_32B_tag CDR94; /* offset: 0x0278 size: 32 bit */
7400 ADC_CDR_32B_tag CDR95; /* offset: 0x027C size: 32 bit */
7401 };
7402
7403 };
7404 /* Upper Threshold register 4 is not contiguous to 3 */
7405 ADC_THRHLR4_32B_tag THRHLR4; /* offset: 0x0280 size: 32 bit */
7406 /* Upper Threshold register 5 */
7407 ADC_THRHLR5_32B_tag THRHLR5; /* offset: 0x0284 size: 32 bit */
7408 /* Upper Threshold register 6 */
7409 ADC_THRHLR6_32B_tag THRHLR6; /* offset: 0x0288 size: 32 bit */
7410 /* Upper Threshold register 7 */
7411 ADC_THRHLR7_32B_tag THRHLR7; /* offset: 0x028C size: 32 bit */
7412 /* Upper Threshold register 8 */
7413 ADC_THRHLR8_32B_tag THRHLR8; /* offset: 0x0290 size: 32 bit */
7414 /* Upper Threshold register 9 */
7415 ADC_THRHLR9_32B_tag THRHLR9; /* offset: 0x0294 size: 32 bit */
7416 /* Upper Threshold register 10 */
7417 ADC_THRHLR10_32B_tag THRHLR10; /* offset: 0x0298 size: 32 bit */
7418 /* Upper Threshold register 11 */
7419 ADC_THRHLR11_32B_tag THRHLR11; /* offset: 0x029C size: 32 bit */
7420 /* Upper Threshold register 12 */
7421 ADC_THRHLR12_32B_tag THRHLR12; /* offset: 0x02A0 size: 32 bit */
7422 /* Upper Threshold register 13 */
7423 ADC_THRHLR13_32B_tag THRHLR13; /* offset: 0x02A4 size: 32 bit */
7424 /* Upper Threshold register 14 */
7425 ADC_THRHLR14_32B_tag THRHLR14; /* offset: 0x02A8 size: 32 bit */
7426 /* Upper Threshold register 15 */
7427 ADC_THRHLR15_32B_tag THRHLR15; /* offset: 0x02AC size: 32 bit */
7428 union {
7429 /* Channel Watchdog Select register */
7430 ADC_CWSELR_32B_tag CWSELR[12]; /* offset: 0x02B0 (0x0004 x 12) */
7431
7432 struct {
7433 /* Channel Watchdog Select register */
7434 ADC_CWSELR_32B_tag CWSELR0; /* offset: 0x02B0 size: 32 bit */
7435 ADC_CWSELR_32B_tag CWSELR1; /* offset: 0x02B4 size: 32 bit */
7436 ADC_CWSELR_32B_tag CWSELR2; /* offset: 0x02B8 size: 32 bit */
7437 ADC_CWSELR_32B_tag CWSELR3; /* offset: 0x02BC size: 32 bit */
7438 ADC_CWSELR_32B_tag CWSELR4; /* offset: 0x02C0 size: 32 bit */
7439 ADC_CWSELR_32B_tag CWSELR5; /* offset: 0x02C4 size: 32 bit */
7440 ADC_CWSELR_32B_tag CWSELR6; /* offset: 0x02C8 size: 32 bit */
7441 ADC_CWSELR_32B_tag CWSELR7; /* offset: 0x02CC size: 32 bit */
7442 ADC_CWSELR_32B_tag CWSELR8; /* offset: 0x02D0 size: 32 bit */
7443 ADC_CWSELR_32B_tag CWSELR9; /* offset: 0x02D4 size: 32 bit */
7444 ADC_CWSELR_32B_tag CWSELR10; /* offset: 0x02D8 size: 32 bit */
7445 ADC_CWSELR_32B_tag CWSELR11; /* offset: 0x02DC size: 32 bit */
7446 };
7447
7448 };
7449 union {
7450 /* Channel Watchdog Enable Register */
7451 ADC_CWENR_32B_tag CWENR[3]; /* offset: 0x02E0 (0x0004 x 3) */
7452
7453 struct {
7454 /* Channel Watchdog Enable Register */
7455 ADC_CWENR_32B_tag CWENR0; /* offset: 0x02E0 size: 32 bit */
7456 ADC_CWENR_32B_tag CWENR1; /* offset: 0x02E4 size: 32 bit */
7457 ADC_CWENR_32B_tag CWENR2; /* offset: 0x02E8 size: 32 bit */
7458 };
7459
7460 };
7461 int8_t ADC_reserved_02EC_C[4];
7462 union {
7463 /* Analog Watchdog Out of Range Register */
7464 ADC_AWORR_32B_tag AWORR[3]; /* offset: 0x02F0 (0x0004 x 3) */
7465
7466 struct {
7467 /* Analog Watchdog Out of Range Register */
7468 ADC_AWORR_32B_tag AWORR0; /* offset: 0x02F0 size: 32 bit */
7469 ADC_AWORR_32B_tag AWORR1; /* offset: 0x02F4 size: 32 bit */
7470 ADC_AWORR_32B_tag AWORR2; /* offset: 0x02F8 size: 32 bit */
7471 };
7472
7473 };
7474 int8_t ADC_reserved_02FC[68];
7475 /* SELF TEST CONFIGURATION REGISTER 1 */
7476 ADC_STCR1_32B_tag STCR1; /* offset: 0x0340 size: 32 bit */
7477 /* SELF TEST CONFIGURATION REGISTER 2 */
7478 ADC_STCR2_32B_tag STCR2; /* offset: 0x0344 size: 32 bit */
7479 /* SELF TEST CONFIGURATION REGISTER 3 */
7480 ADC_STCR3_32B_tag STCR3; /* offset: 0x0348 size: 32 bit */
7481 /* SELF TEST BAUD RATE REGISTER */
7482 ADC_STBRR_32B_tag STBRR; /* offset: 0x034C size: 32 bit */
7483 /* SELF TEST STATUS REGISTER 1 */
7484 ADC_STSR1_32B_tag STSR1; /* offset: 0x0350 size: 32 bit */
7485 /* SELF TEST STATUS REGISTER 2 */
7486 ADC_STSR2_32B_tag STSR2; /* offset: 0x0354 size: 32 bit */
7487 /* SELF TEST STATUS REGISTER 3 */
7488 ADC_STSR3_32B_tag STSR3; /* offset: 0x0358 size: 32 bit */
7489 /* SELF TEST STATUS REGISTER 4 */
7490 ADC_STSR4_32B_tag STSR4; /* offset: 0x035C size: 32 bit */
7491 int8_t ADC_reserved_0360[16];
7492 /* SELF TEST DATA REGISTER 1 */
7493 ADC_STDR1_32B_tag STDR1; /* offset: 0x0370 size: 32 bit */
7494 /* SELF TEST DATA REGISTER 2 */
7495 ADC_STDR2_32B_tag STDR2; /* offset: 0x0374 size: 32 bit */
7496 int8_t ADC_reserved_0378[8];
7497 /* SELF TEST ANALOG WATCHDOG REGISTER 0 */
7498 ADC_STAW0R_32B_tag STAW0R; /* offset: 0x0380 size: 32 bit */
7499 /* SELF TEST ANALOG WATCHDOG REGISTER 1A */
7500 ADC_STAW1AR_32B_tag STAW1AR; /* offset: 0x0384 size: 32 bit */
7501 /* SELF TEST ANALOG WATCHDOG REGISTER 1B */
7502 ADC_STAW1BR_32B_tag STAW1BR; /* offset: 0x0388 size: 32 bit */
7503 /* SELF TEST ANALOG WATCHDOG REGISTER 2 */
7504 ADC_STAW2R_32B_tag STAW2R; /* offset: 0x038C size: 32 bit */
7505 /* SELF TEST ANALOG WATCHDOG REGISTER 3 */
7506 ADC_STAW3R_32B_tag STAW3R; /* offset: 0x0390 size: 32 bit */
7507 /* SELF TEST ANALOG WATCHDOG REGISTER 4 */
7508 ADC_STAW4R_32B_tag STAW4R; /* offset: 0x0394 size: 32 bit */
7509 /* SELF TEST ANALOG WATCHDOG REGISTER 5 */
7510 ADC_STAW5R_32B_tag STAW5R; /* offset: 0x0398 size: 32 bit */
7511 } ADC_tag;
7512
7513
7514#define ADC0 (*(volatile ADC_tag *) 0xFFE00000UL)
7515#define ADC1 (*(volatile ADC_tag *) 0xFFE04000UL)
7516
7517
7518
7519/****************************************************************/
7520/* */
7521/* Module: CTU */
7522/* */
7523/****************************************************************/
7524
7525 typedef union { /* Trigger Generator Subunit Input Selection register */
7526 uint32_t R;
7527 struct {
7528 uint32_t I15_FE:1; /* ext_signal Falling Edge */
7529 uint32_t I15_RE:1; /* ext_signal Rising Edge */
7530 uint32_t I14_FE:1; /* eTimer2 Falling Edge Enable */
7531 uint32_t I14_RE:1; /* eTimer2 Rising Edge Enable */
7532 uint32_t I13_FE:1; /* eTimer1 Falling Edge Enable */
7533 uint32_t I13_RE:1; /* eTimer1 Rising Edge Enable */
7534 uint32_t I12_FE:1; /* RPWM ch3 Falling Edge Enable */
7535 uint32_t I12_RE:1; /* RPWM ch3 Rising Edge Enable */
7536 uint32_t I11_FE:1; /* RPWM ch2 Falling Edge Enable */
7537 uint32_t I11_RE:1; /* RPWM ch2 Rising Edge Enable */
7538 uint32_t I10_FE:1; /* RPWM ch1 Falling Edge Enable */
7539 uint32_t I10_RE:1; /* RPWM ch1 Rising Edge Enable */
7540 uint32_t I9_FE:1; /* RPWM ch0 Falling Edge Enable */
7541 uint32_t I9_RE:1; /* RPWM ch0 Rising Edge Enable */
7542 uint32_t I8_FE:1; /* PWM ch3 even trig Falling edge Enable */
7543 uint32_t I8_RE:1; /* PWM ch3 even trig Rising edge Enable */
7544 uint32_t I7_FE:1; /* PWM ch2 even trig Falling edge Enable */
7545 uint32_t I7_RE:1; /* PWM ch2 even trig Rising edge Enable */
7546 uint32_t I6_FE:1; /* PWM ch1 even trig Falling edge Enable */
7547 uint32_t I6_RE:1; /* PWM ch1 even trig Rising edge Enable */
7548 uint32_t I5_FE:1; /* PWM ch0 even trig Falling edge Enable */
7549 uint32_t I5_RE:1; /* PWM ch0 even trig Rising edge Enable */
7550 uint32_t I4_FE:1; /* PWM ch3 odd trig Falling edge Enable */
7551 uint32_t I4_RE:1; /* PWM ch3 odd trig Rising edge Enable */
7552 uint32_t I3_FE:1; /* PWM ch2 odd trig Falling edge Enable */
7553 uint32_t I3_RE:1; /* PWM ch2 odd trig Rising edge Enable */
7554 uint32_t I2_FE:1; /* PWM ch1 odd trig Falling edge Enable */
7555 uint32_t I2_RE:1; /* PWM ch1 odd trig Rising edge Enable */
7556 uint32_t I1_FE:1; /* PWM ch0 odd trig Falling edge Enable */
7557 uint32_t I1_RE:1; /* PWM ch0 odd trig Rising edge Enable */
7558 uint32_t I0_FE:1; /* PWM Reload Falling Edge Enable */
7559 uint32_t I0_RE:1; /* PWM Reload Rising Edge Enable */
7560 } B;
7561 } CTU_TGSISR_32B_tag;
7562
7563 typedef union { /* Trigger Generator Subunit Control Register */
7564 uint16_t R;
7565 struct {
7566 uint16_t:7;
7567#ifndef USE_FIELD_ALIASES_CTU
7568 uint16_t ET_TM:1; /* Toggle Mode Enable */
7569#else
7570 uint16_t ETTM:1; /* deprecated name - please avoid */
7571#endif
7572 uint16_t PRES:2; /* TGS Prescaler Selection */
7573#ifndef USE_FIELD_ALIASES_CTU
7574 uint16_t MRS_SM:5; /* MRS Selection in Sequential Mode */
7575#else
7576 uint16_t MRSSM:5; /* deprecated name - please avoid */
7577#endif
7578#ifndef USE_FIELD_ALIASES_CTU
7579 uint16_t TGS_M:1; /* Trigger Generator Subunit Mode */
7580#else
7581 uint16_t TGSM:1; /* deprecated name - please avoid */
7582#endif
7583 } B;
7584 } CTU_TGSCR_16B_tag;
7585
7586 typedef union { /* */
7587 uint16_t R;
7588 } CTU_TCR_16B_tag;
7589
7590 typedef union { /* TGS Counter Compare Register */
7591 uint16_t R;
7592#ifndef USE_FIELD_ALIASES_CTU
7593 struct {
7594 uint16_t TGSCCV:16; /* deprecated field -- do not use */
7595 } B;
7596#endif
7597 } CTU_TGSCCR_16B_tag;
7598
7599 typedef union { /* TGS Counter Reload Register */
7600 uint16_t R;
7601#ifndef USE_FIELD_ALIASES_CTU
7602 struct {
7603 uint16_t TGSCRV:16; /* deprecated field -- do not use */
7604 } B;
7605#endif
7606 } CTU_TGSCRR_16B_tag;
7607
7608 typedef union { /* Commands List Control Register 1 */
7609 uint32_t R;
7610 struct {
7611 uint32_t:3;
7612 uint32_t T3INDEX:5; /* Trigger 3 First Command address */
7613 uint32_t:3;
7614 uint32_t T2INDEX:5; /* Trigger 2 First Command address */
7615 uint32_t:3;
7616 uint32_t T1INDEX:5; /* Trigger 1 First Command address */
7617 uint32_t:3;
7618 uint32_t T0INDEX:5; /* Trigger 0 First Command address */
7619 } B;
7620 } CTU_CLCR1_32B_tag;
7621
7622 typedef union { /* Commands List Control Register 2 */
7623 uint32_t R;
7624 struct {
7625 uint32_t:3;
7626 uint32_t T7INDEX:5; /* Trigger 7 First Command address */
7627 uint32_t:3;
7628 uint32_t T6INDEX:5; /* Trigger 6 First Command address */
7629 uint32_t:3;
7630 uint32_t T5INDEX:5; /* Trigger 5 First Command address */
7631 uint32_t:3;
7632 uint32_t T4INDEX:5; /* Trigger 4 First Command address */
7633 } B;
7634 } CTU_CLCR2_32B_tag;
7635
7636 typedef union { /* Trigger Handler Control Register 1 */
7637 uint32_t R;
7638 struct {
7639 uint32_t:1;
7640 uint32_t T3_E:1; /* Trigger 3 enable */
7641 uint32_t T3_ETE:1; /* Trigger 3 Ext Trigger output enable */
7642 uint32_t T3_T4E:1; /* Trigger 3 Timer4 output enable */
7643 uint32_t T3_T3E:1; /* Trigger 3 Timer3 output enable */
7644 uint32_t T3_T2E:1; /* Trigger 3 Timer2 output enable */
7645 uint32_t T3_T1E:1; /* Trigger 3 Timer1 output enable */
7646 uint32_t T3_ADCE:1; /* Trigger 3 ADC Command output enable */
7647 uint32_t:1;
7648 uint32_t T2_E:1; /* Trigger 2 enable */
7649 uint32_t T2_ETE:1; /* Trigger 2 Ext Trigger output enable */
7650 uint32_t T2_T4E:1; /* Trigger 2 Timer4 output enable */
7651 uint32_t T2_T3E:1; /* Trigger 2 Timer3 output enable */
7652 uint32_t T2_T2E:1; /* Trigger 2 Timer2 output enable */
7653 uint32_t T2_T1E:1; /* Trigger 2 Timer1 output enable */
7654 uint32_t T2_ADCE:1; /* Trigger 2 ADC Command output enable */
7655 uint32_t:1;
7656 uint32_t T1_E:1; /* Trigger 1 enable */
7657 uint32_t T1_ETE:1; /* Trigger 1 Ext Trigger output enable */
7658 uint32_t T1_T4E:1; /* Trigger 1 Timer4 output enable */
7659 uint32_t T1_T3E:1; /* Trigger 1 Timer3 output enable */
7660 uint32_t T1_T2E:1; /* Trigger 1 Timer2 output enable */
7661 uint32_t T1_T1E:1; /* Trigger 1 Timer1 output enable */
7662 uint32_t T1_ADCE:1; /* Trigger 1 ADC Command output enable */
7663 uint32_t:1;
7664 uint32_t T0_E:1; /* Trigger 0 enable */
7665 uint32_t T0_ETE:1; /* Trigger 0 Ext Trigger output enable */
7666 uint32_t T0_T4E:1; /* Trigger 0 Timer4 output enable */
7667 uint32_t T0_T3E:1; /* Trigger 0 Timer3 output enable */
7668 uint32_t T0_T2E:1; /* Trigger 0 Timer2 output enable */
7669 uint32_t T0_T1E:1; /* Trigger 0 Timer1 output enable */
7670 uint32_t T0_ADCE:1; /* Trigger 0 ADC Command output enable */
7671 } B;
7672 } CTU_THCR1_32B_tag;
7673
7674 typedef union { /* Trigger Handler Control Register 2 */
7675 uint32_t R;
7676 struct {
7677 uint32_t:1;
7678 uint32_t T7_E:1; /* Trigger 7 enable */
7679 uint32_t T7_ETE:1; /* Trigger 7 Ext Trigger output enable */
7680 uint32_t T7_T4E:1; /* Trigger 7 Timer4 output enable */
7681 uint32_t T7_T3E:1; /* Trigger 7 Timer3 output enable */
7682 uint32_t T7_T2E:1; /* Trigger 7 Timer2 output enable */
7683 uint32_t T7_T1E:1; /* Trigger 7 Timer1 output enable */
7684 uint32_t T7_ADCE:1; /* Trigger 7 ADC Command output enable */
7685 uint32_t:1;
7686 uint32_t T6_E:1; /* Trigger 6 enable */
7687 uint32_t T6_ETE:1; /* Trigger 6 Ext Trigger output enable */
7688 uint32_t T6_T4E:1; /* Trigger 6 Timer4 output enable */
7689 uint32_t T6_T3E:1; /* Trigger 6 Timer3 output enable */
7690 uint32_t T6_T2E:1; /* Trigger 6 Timer2 output enable */
7691 uint32_t T6_T1E:1; /* Trigger 6 Timer1 output enable */
7692 uint32_t T6_ADCE:1; /* Trigger 6 ADC Command output enable */
7693 uint32_t:1;
7694 uint32_t T5_E:1; /* Trigger 5 enable */
7695 uint32_t T5_ETE:1; /* Trigger 5 Ext Trigger output enable */
7696 uint32_t T5_T4E:1; /* Trigger 5 Timer4 output enable */
7697 uint32_t T5_T3E:1; /* Trigger 5 Timer3 output enable */
7698 uint32_t T5_T2E:1; /* Trigger 5 Timer2 output enable */
7699 uint32_t T5_T1E:1; /* Trigger 5 Timer1 output enable */
7700 uint32_t T5_ADCE:1; /* Trigger 5 ADC Command output enable */
7701 uint32_t:1;
7702 uint32_t T4_E:1; /* Trigger 4 enable */
7703 uint32_t T4_ETE:1; /* Trigger 4 Ext Trigger output enable */
7704 uint32_t T4_T4E:1; /* Trigger 4 Timer4 output enable */
7705 uint32_t T4_T3E:1; /* Trigger 4 Timer3 output enable */
7706 uint32_t T4_T2E:1; /* Trigger 4 Timer2 output enable */
7707 uint32_t T4_T1E:1; /* Trigger 4 Timer1 output enable */
7708 uint32_t T4_ADCE:1; /* Trigger 4 ADC Command output enable */
7709 } B;
7710 } CTU_THCR2_32B_tag;
7711
7712
7713 /* Register layout for all registers CLR_DCM... */
7714
7715 typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
7716 uint16_t R;
7717 struct {
7718 uint16_t CIR:1; /* Command Interrupt Request */
7719 uint16_t LC:1; /* Last Command */
7720 uint16_t CMS:1; /* Conversion Mode Selection */
7721 uint16_t FIFO:3; /* FIFO for ADC A/B */
7722 uint16_t:1;
7723 uint16_t CHB:4; /* ADC unit B channel number */
7724 uint16_t:1;
7725 uint16_t CHA:4; /* ADC unit A channel number */
7726 } B;
7727 } CTU_CLR_DCM_16B_tag;
7728
7729
7730 /* Register layout for all registers CLR_SCM... */
7731
7732 typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
7733 uint16_t R;
7734 struct {
7735 uint16_t CIR:1; /* Command Interrupt Request */
7736 uint16_t LC:1; /* Last Command */
7737 uint16_t CMS:1; /* Conversion Mode Selection */
7738 uint16_t FIFO:3; /* FIFO for ADC A/B */
7739 uint16_t:4;
7740 uint16_t SU:1; /* Selection ADC Unit */
7741 uint16_t:1;
7742 uint16_t CH:4; /* ADC unit channel number */
7743 } B;
7744 } CTU_CLR_SCM_16B_tag;
7745
7746
7747 /* Register layout for all registers CLR... */
7748
7749
7750 typedef union { /* Control Register */
7751 uint16_t R;
7752 struct {
7753 uint16_t EMPTY_CLR7:1; /* Empty Clear 7 */
7754 uint16_t EMPTY_CLR6:1; /* Empty Clear 6 */
7755 uint16_t EMPTY_CLR5:1; /* Empty Clear 5 */
7756 uint16_t EMPTY_CLR4:1; /* Empty Clear 4 */
7757 uint16_t EMPTY_CLR3:1; /* Empty Clear 3 */
7758 uint16_t EMPTY_CLR2:1; /* Empty Clear 2 */
7759 uint16_t EMPTY_CLR1:1; /* Empty Clear 1 */
7760 uint16_t EMPTY_CLR0:1; /* Empty Clear 0 */
7761#ifndef USE_FIELD_ALIASES_CTU
7762 uint16_t DMA_EN7:1; /* Enable DMA interface for FIFO 7 */
7763#else
7764 uint16_t DMAEN7:1; /* Enable DMA interface for FIFO 7 */
7765#endif
7766#ifndef USE_FIELD_ALIASES_CTU
7767 uint16_t DMA_EN6:1; /* Enable DMA interface for FIFO 6 */
7768#else
7769 uint16_t DMAEN6:1; /* Enable DMA interface for FIFO 6 */
7770#endif
7771#ifndef USE_FIELD_ALIASES_CTU
7772 uint16_t DMA_EN5:1; /* Enable DMA interface for FIFO 5 */
7773#else
7774 uint16_t DMAEN5:1; /* Enable DMA interface for FIFO 5 */
7775#endif
7776#ifndef USE_FIELD_ALIASES_CTU
7777 uint16_t DMA_EN4:1; /* Enable DMA interface for FIFO 4 */
7778#else
7779 uint16_t DMAEN4:1; /* Enable DMA interface for FIFO 4 */
7780#endif
7781#ifndef USE_FIELD_ALIASES_CTU
7782 uint16_t DMA_EN3:1; /* Enable DMA interface for FIFO 3 */
7783#else
7784 uint16_t DMAEN3:1; /* Enable DMA interface for FIFO 3 */
7785#endif
7786#ifndef USE_FIELD_ALIASES_CTU
7787 uint16_t DMA_EN2:1; /* Enable DMA interface for FIFO 2 */
7788#else
7789 uint16_t DMAEN2:1; /* Enable DMA interface for FIFO 2 */
7790#endif
7791#ifndef USE_FIELD_ALIASES_CTU
7792 uint16_t DMA_EN1:1; /* Enable DMA interface for FIFO 1 */
7793#else
7794 uint16_t DMAEN1:1; /* Enable DMA interface for FIFO 1 */
7795#endif
7796#ifndef USE_FIELD_ALIASES_CTU
7797 uint16_t DMA_EN0:1; /* Enable DMA interface for FIFO 0 */
7798#else
7799 uint16_t DMAEN0:1; /* Enable DMA interface for FIFO 0 */
7800#endif
7801 } B;
7802 } CTU_CR_16B_tag;
7803
7804 typedef union { /* Control Register FIFO */
7805 uint32_t R;
7806 struct {
7807 uint32_t FIFO_OVERRUN_EN7:1; /* FIFO 7 OVERRUN Enable Interrupt */
7808 uint32_t FIFO_OVERFLOW_EN7:1; /* FIFO 7 OVERFLOW Enable Interrupt */
7809 uint32_t FIFO_EMPTY_EN7:1; /* FIFO 7 EMPTY Enable Interrupt */
7810 uint32_t FIFO_FULL_EN7:1; /* FIFO 7 FULL Enable Interrupt */
7811 uint32_t FIFO_OVERRUN_EN6:1; /* FIFO 6 OVERRUN Enable Interrupt */
7812 uint32_t FIFO_OVERFLOW_EN6:1; /* FIFO 6 OVERFLOW Enable Interrupt */
7813 uint32_t FIFO_EMPTY_EN6:1; /* FIFO 6 EMPTY Enable Interrupt */
7814 uint32_t FIFO_FULL_EN6:1; /* FIFO 6 FULL Enable Interrupt */
7815 uint32_t FIFO_OVERRUN_EN5:1; /* FIFO 5 OVERRUN Enable Interrupt */
7816 uint32_t FIFO_OVERFLOW_EN5:1; /* FIFO 5 OVERFLOW Enable Interrupt */
7817 uint32_t FIFO_EMPTY_EN5:1; /* FIFO 5 EMPTY Enable Interrupt */
7818 uint32_t FIFO_FULL_EN5:1; /* FIFO 5 FULL Enable Interrupt */
7819 uint32_t FIFO_OVERRUN_EN4:1; /* FIFO 4 OVERRUN Enable Interrupt */
7820 uint32_t FIFO_OVERFLOW_EN4:1; /* FIFO 4 OVERFLOW Enable Interrupt */
7821 uint32_t FIFO_EMPTY_EN4:1; /* FIFO 4 EMPTY Enable Interrupt */
7822 uint32_t FIFO_FULL_EN4:1; /* FIFO 4 FULL Enable Interrupt */
7823 uint32_t FIFO_OVERRUN_EN3:1; /* FIFO 3 OVERRUN Enable Interrupt */
7824 uint32_t FIFO_OVERFLOW_EN3:1; /* FIFO 3 OVERFLOW Enable Interrupt */
7825 uint32_t FIFO_EMPTY_EN3:1; /* FIFO 3 EMPTY Enable Interrupt */
7826 uint32_t FIFO_FULL_EN3:1; /* FIFO 3 FULL Enable Interrupt */
7827 uint32_t FIFO_OVERRUN_EN2:1; /* FIFO 2 OVERRUN Enable Interrupt */
7828 uint32_t FIFO_OVERFLOW_EN2:1; /* FIFO 2 OVERFLOW Enable Interrupt */
7829 uint32_t FIFO_EMPTY_EN2:1; /* FIFO 2 EMPTY Enable Interrupt */
7830 uint32_t FIFO_FULL_EN2:1; /* FIFO 2 FULL Enable Interrupt */
7831 uint32_t FIFO_OVERRUN_EN1:1; /* FIFO 1 OVERRUN Enable Interrupt */
7832 uint32_t FIFO_OVERFLOW_EN1:1; /* FIFO 1 OVERFLOW Enable Interrupt */
7833 uint32_t FIFO_EMPTY_EN1:1; /* FIFO 1 EMPTY Enable Interrupt */
7834 uint32_t FIFO_FULL_EN1:1; /* FIFO 1 FULL Enable Interrupt */
7835 uint32_t FIFO_OVERRUN_EN0:1; /* FIFO 0 OVERRUN Enable Interrupt */
7836 uint32_t FIFO_OVERFLOW_EN0:1; /* FIFO 0 OVERFLOW Enable Interrupt */
7837 uint32_t FIFO_EMPTY_EN0:1; /* FIFO 0 EMPTY Enable Interrupt */
7838 uint32_t FIFO_FULL_EN0:1; /* FIFO 0 FULL Enable Interrupt */
7839 } B;
7840 } CTU_FCR_32B_tag;
7841
7842 typedef union { /* Threshold 1 Register */
7843 uint32_t R;
7844 struct {
7845 uint32_t THRESHOLD3:8; /* Threshlod FIFO 3 */
7846 uint32_t THRESHOLD2:8; /* Threshlod FIFO 2 */
7847 uint32_t THRESHOLD1:8; /* Threshlod FIFO 1 */
7848 uint32_t THRESHOLD0:8; /* Threshlod FIFO 0 */
7849 } B;
7850 } CTU_TH1_32B_tag;
7851
7852 typedef union { /* Threshold 2 Register */
7853 uint32_t R;
7854 struct {
7855 uint32_t THRESHOLD7:8; /* Threshlod FIFO 7 */
7856 uint32_t THRESHOLD6:8; /* Threshlod FIFO 6 */
7857 uint32_t THRESHOLD5:8; /* Threshlod FIFO 5 */
7858 uint32_t THRESHOLD4:8; /* Threshlod FIFO 4 */
7859 } B;
7860 } CTU_TH2_32B_tag;
7861
7862 typedef union { /* Status Register */
7863 uint32_t R;
7864 struct {
7865 uint32_t FIFO_OVERRUN7:1; /* FIFO 7 OVERRUN Flag */
7866 uint32_t FIFO_OVERFLOW7:1; /* FIFO 7 OVERFLOW Flag */
7867 uint32_t FIFO_EMPTY7:1; /* FIFO 7 EMPTY Flag */
7868 uint32_t FIFO_FULL7:1; /* FIFO 7 FULL Flag */
7869 uint32_t FIFO_OVERRUN6:1; /* FIFO 6 OVERRUN Flag */
7870 uint32_t FIFO_OVERFLOW6:1; /* FIFO 6 OVERFLOW Flag */
7871 uint32_t FIFO_EMPTY6:1; /* FIFO 6 EMPTY Flag */
7872 uint32_t FIFO_FULL6:1; /* FIFO 6 FULL Flag */
7873 uint32_t FIFO_OVERRUN5:1; /* FIFO 5 OVERRUN Flag */
7874 uint32_t FIFO_OVERFLOW5:1; /* FIFO 5 OVERFLOW Flag */
7875 uint32_t FIFO_EMPTY5:1; /* FIFO 5 EMPTY Flag */
7876 uint32_t FIFO_FULL5:1; /* FIFO 5 FULL Flag */
7877 uint32_t FIFO_OVERRUN4:1; /* FIFO 4 OVERRUN Flag */
7878 uint32_t FIFO_OVERFLOW4:1; /* FIFO 4 OVERFLOW Flag */
7879 uint32_t FIFO_EMPTY4:1; /* FIFO 4 EMPTY Flag */
7880 uint32_t FIFO_FULL4:1; /* FIFO 4 FULL Flag */
7881 uint32_t FIFO_OVERRUN3:1; /* FIFO 3 OVERRUN Flag */
7882 uint32_t FIFO_OVERFLOW3:1; /* FIFO 3 OVERFLOW Flag */
7883 uint32_t FIFO_EMPTY3:1; /* FIFO 3 EMPTY Flag */
7884 uint32_t FIFO_FULL3:1; /* FIFO 3 FULL Flag */
7885 uint32_t FIFO_OVERRUN2:1; /* FIFO 2 OVERRUN Flag */
7886 uint32_t FIFO_OVERFLOW2:1; /* FIFO 2 OVERFLOW Flag */
7887 uint32_t FIFO_EMPTY2:1; /* FIFO 2 EMPTY Flag */
7888 uint32_t FIFO_FULL2:1; /* FIFO 2 FULL Flag */
7889 uint32_t FIFO_OVERRUN1:1; /* FIFO 1 OVERRUN Flag */
7890 uint32_t FIFO_OVERFLOW1:1; /* FIFO 1 OVERFLOW Flag */
7891 uint32_t FIFO_EMPTY1:1; /* FIFO 1 EMPTY Flag */
7892 uint32_t FIFO_FULL1:1; /* FIFO 1 FULL Flag */
7893 uint32_t FIFO_OVERRUN0:1; /* FIFO 0 OVERRUN Flag */
7894 uint32_t FIFO_OVERFLOW0:1; /* FIFO 0 OVERFLOW Flag */
7895 uint32_t FIFO_EMPTY0:1; /* FIFO 0 EMPTY Flag */
7896 uint32_t FIFO_FULL0:1; /* FIFO 0 FULL Flag */
7897 } B;
7898 } CTU_STS_32B_tag;
7899
7900
7901 /* Register layout for all registers FR... */
7902
7903 typedef union { /* FIFO Right Aligned register */
7904 uint32_t R;
7905 struct {
7906 uint32_t:11;
7907 uint32_t ADC:1; /* ADC Unit */
7908 uint32_t N_CH:4; /* Number Channel */
7909 uint32_t:4;
7910 uint32_t DATA:12; /* Data Fifo */
7911 } B;
7912 } CTU_FR_32B_tag;
7913
7914
7915 /* Register layout for all registers FL... */
7916
7917 typedef union { /* FIFO Left Aligned register */
7918 uint32_t R;
7919 struct {
7920 uint32_t:11;
7921 uint32_t ADC:1; /* ADC Unit */
7922 uint32_t N_CH:4; /* Number Channel */
7923 uint32_t:1;
7924 uint32_t DATA:12; /* Data Fifo */
7925 uint32_t:3;
7926 } B;
7927 } CTU_FL_32B_tag;
7928
7929 typedef union { /* CTU Error Flag Register */
7930 uint16_t R;
7931 struct {
7932 uint16_t:3;
7933 uint16_t CS:1; /* Counter Status */
7934 uint16_t ET_OE:1; /* ExtTrigger Generation Overrun */
7935 uint16_t ERR_CMP:1; /* Set if counter reaches TGSCCR register */
7936 uint16_t T4_OE:1; /* Timer4 Generation Overrun */
7937 uint16_t T3_OE:1; /* Timer3 Generation Overrun */
7938 uint16_t T2_OE:1; /* Timer2 Generation Overrun */
7939 uint16_t T1_OE:1; /* Timer1 Generation Overrun */
7940#ifndef USE_FIELD_ALIASES_CTU
7941 uint16_t ADC_OE:1; /* ADC Command Generation Overrun */
7942#else
7943 uint16_t ADCOE:1; /* ADC Command Generation Overrun */
7944#endif
7945#ifndef USE_FIELD_ALIASES_CTU
7946 uint16_t TGS_OSM:1; /* TGS Overrun */
7947#else
7948 uint16_t TGSOSM:1; /* TGS Overrun */
7949#endif
7950#ifndef USE_FIELD_ALIASES_CTU
7951 uint16_t MRS_O:1; /* MRS Overrun */
7952#else
7953 uint16_t MRSO:1; /* TGS Overrun */
7954#endif
7955 uint16_t ICE:1; /* Invalid Command Error */
7956#ifndef USE_FIELD_ALIASES_CTU
7957 uint16_t SM_TO:1; /* Trigger Overrun */
7958#else
7959 uint16_t SMTO:1; /* Trigger Overrun */
7960#endif
7961#ifndef USE_FIELD_ALIASES_CTU
7962 uint16_t MRS_RE:1; /* MRS Reload Error */
7963#else
7964 uint16_t MRSRE:1; /* MRS Reload Error */
7965#endif
7966 } B;
7967 } CTU_CTUEFR_16B_tag;
7968
7969 typedef union { /* CTU Interrupt Flag Register */
7970 uint16_t R;
7971 struct {
7972 uint16_t:4;
7973 uint16_t S_E_B:1; /* Slice time OK */
7974 uint16_t S_E_A:1; /* Slice time OK */
7975#ifndef USE_FIELD_ALIASES_CTU
7976 uint16_t ADC_I:1; /* ADC Command Interrupt Flag */
7977#else
7978 uint16_t ADC:1;
7979#endif
7980#ifndef USE_FIELD_ALIASES_CTU
7981 uint16_t T7_I:1; /* Trigger 7 Interrupt Flag */
7982#else
7983 uint16_t T7:1;
7984#endif
7985#ifndef USE_FIELD_ALIASES_CTU
7986 uint16_t T6_I:1; /* Trigger 6 Interrupt Flag */
7987#else
7988 uint16_t T6:1;
7989#endif
7990#ifndef USE_FIELD_ALIASES_CTU
7991 uint16_t T5_I:1; /* Trigger 5 Interrupt Flag */
7992#else
7993 uint16_t T5:1;
7994#endif
7995#ifndef USE_FIELD_ALIASES_CTU
7996 uint16_t T4_I:1; /* Trigger 4 Interrupt Flag */
7997#else
7998 uint16_t T4:1;
7999#endif
8000#ifndef USE_FIELD_ALIASES_CTU
8001 uint16_t T3_I:1; /* Trigger 3 Interrupt Flag */
8002#else
8003 uint16_t T3:1;
8004#endif
8005#ifndef USE_FIELD_ALIASES_CTU
8006 uint16_t T2_I:1; /* Trigger 2 Interrupt Flag */
8007#else
8008 uint16_t T2:1;
8009#endif
8010#ifndef USE_FIELD_ALIASES_CTU
8011 uint16_t T1_I:1; /* Trigger 1 Interrupt Flag */
8012#else
8013 uint16_t T1:1;
8014#endif
8015#ifndef USE_FIELD_ALIASES_CTU
8016 uint16_t T0_I:1; /* Trigger 0 Interrupt Flag */
8017#else
8018 uint16_t T0:1;
8019#endif
8020#ifndef USE_FIELD_ALIASES_CTU
8021 uint16_t MRS_I:1; /* MRS Interrupt Flag */
8022#else
8023 uint16_t MRS:1;
8024#endif
8025 } B;
8026 } CTU_CTUIFR_16B_tag;
8027
8028 typedef union { /* CTU Interrupt/DMA Register */
8029 uint16_t R;
8030 struct {
8031#ifndef USE_FIELD_ALIASES_CTU
8032 uint16_t T7_I:1; /* Trigger 7 Interrupt Enable */
8033#else
8034 uint16_t T7IE:1;
8035#endif
8036#ifndef USE_FIELD_ALIASES_CTU
8037 uint16_t T6_I:1; /* Trigger 6 Interrupt Enable */
8038#else
8039 uint16_t T6IE:1;
8040#endif
8041#ifndef USE_FIELD_ALIASES_CTU
8042 uint16_t T5_I:1; /* Trigger 5 Interrupt Enable */
8043#else
8044 uint16_t T5IE:1;
8045#endif
8046#ifndef USE_FIELD_ALIASES_CTU
8047 uint16_t T4_I:1; /* Trigger 4 Interrupt Enable */
8048#else
8049 uint16_t T4IE:1;
8050#endif
8051#ifndef USE_FIELD_ALIASES_CTU
8052 uint16_t T3_I:1; /* Trigger 3 Interrupt Enable */
8053#else
8054 uint16_t T3IE:1;
8055#endif
8056#ifndef USE_FIELD_ALIASES_CTU
8057 uint16_t T2_I:1; /* Trigger 2 Interrupt Enable */
8058#else
8059 uint16_t T2IE:1;
8060#endif
8061#ifndef USE_FIELD_ALIASES_CTU
8062 uint16_t T1_I:1; /* Trigger 1 Interrupt Enable */
8063#else
8064 uint16_t T1IE:1;
8065#endif
8066#ifndef USE_FIELD_ALIASES_CTU
8067 uint16_t T0_I:1; /* Trigger 0 Interrupt Enable */
8068#else
8069 uint16_t T0IE:1;
8070#endif
8071 uint16_t:2;
8072 uint16_t SAF_CNT_B_EN:1; /* Conversion time counter enabled */
8073 uint16_t SAF_CNT_A_EN:1; /* Conversion time counter enabled */
8074 uint16_t DMA_DE:1; /* DMA and gre bit */
8075#ifndef USE_FIELD_ALIASES_CTU
8076 uint16_t MRS_DMAE:1; /* DMA Transfer Enable */
8077#else
8078 uint16_t MRSDMAE:1;
8079#endif
8080#ifndef USE_FIELD_ALIASES_CTU
8081 uint16_t MRS_IE:1; /* MRS Interrupt Enable */
8082#else
8083 uint16_t MRSIE:1;
8084#endif
8085 uint16_t IEE:1; /* Interrupt Error Enable */
8086 } B;
8087 } CTU_CTUIR_16B_tag;
8088
8089 typedef union { /* Control On-Time Register */
8090 uint16_t R;
8091 struct {
8092 uint16_t:8;
8093#ifndef USE_FIELD_ALIASES_CTU
8094 uint16_t COTR_COTR:8; /* Control On-Time Register and Guard Time */
8095#else
8096 uint16_t COTR:8;
8097#endif
8098 } B;
8099 } CTU_COTR_16B_tag;
8100
8101 typedef union { /* CTU Control Register */
8102 uint16_t R;
8103 struct {
8104#ifndef USE_FIELD_ALIASES_CTU
8105 uint16_t T7_SG:1; /* Trigger 7 Software Generated */
8106#else
8107 uint16_t T7SG:1;
8108#endif
8109#ifndef USE_FIELD_ALIASES_CTU
8110 uint16_t T6_SG:1; /* Trigger 6 Software Generated */
8111#else
8112 uint16_t T6SG:1;
8113#endif
8114#ifndef USE_FIELD_ALIASES_CTU
8115 uint16_t T5_SG:1; /* Trigger 5 Software Generated */
8116#else
8117 uint16_t T5SG:1;
8118#endif
8119#ifndef USE_FIELD_ALIASES_CTU
8120 uint16_t T4_SG:1; /* Trigger 4 Software Generated */
8121#else
8122 uint16_t T4SG:1;
8123#endif
8124#ifndef USE_FIELD_ALIASES_CTU
8125 uint16_t T3_SG:1; /* Trigger 3 Software Generated */
8126#else
8127 uint16_t T3SG:1;
8128#endif
8129#ifndef USE_FIELD_ALIASES_CTU
8130 uint16_t T2_SG:1; /* Trigger 2 Software Generated */
8131#else
8132 uint16_t T2SG:1;
8133#endif
8134#ifndef USE_FIELD_ALIASES_CTU
8135 uint16_t T1_SG:1; /* Trigger 1 Software Generated */
8136#else
8137 uint16_t T1SG:1;
8138#endif
8139#ifndef USE_FIELD_ALIASES_CTU
8140 uint16_t T0_SG:1; /* Trigger 0 Software Generated */
8141#else
8142 uint16_t T0SG:1;
8143#endif
8144#ifndef USE_FIELD_ALIASES_CTU
8145 uint16_t CTU_ADC_RESET:1; /* CTU ADC State Machine Reset */
8146#else
8147 uint16_t CTUADCRESET:1;
8148#endif
8149#ifndef USE_FIELD_ALIASES_CTU
8150 uint16_t CTU_ODIS:1; /* CTU Output Disable */
8151#else
8152 uint16_t CTUODIS:1;
8153#endif
8154#ifndef USE_FIELD_ALIASES_CTU
8155 uint16_t FILTER_EN:1; /* Synchronize Filter Register value */
8156#else
8157 uint16_t FILTERENABLE:1;
8158#endif
8159 uint16_t CGRE:1; /* Clear GRE */
8160 uint16_t FGRE:1; /* GRE Flag */
8161#ifndef USE_FIELD_ALIASES_CTU
8162 uint16_t MRS_SG:1; /* MRS Software Generated */
8163#else
8164 uint16_t MRSSG:1;
8165#endif
8166 uint16_t GRE:1; /* General Reload Enable */
8167#ifndef USE_FIELD_ALIASES_CTU
8168 uint16_t TGSISR_RE:1; /* TGSISR Reload Enable */
8169#else
8170 uint16_t TGSISRRE:1;
8171#endif
8172 } B;
8173 } CTU_CTUCR_16B_tag;
8174
8175 typedef union { /* CTU Digital Filter Register */
8176 uint16_t R;
8177 struct {
8178 uint16_t:8;
8179#ifndef USE_FIELD_ALIASES_CTU
8180 uint16_t FILTER_VALUE:8; /* Filter Value */
8181#else
8182 uint16_t FILTERVALUE:8; /* deprecated name - please avoid */
8183#endif
8184 } B;
8185 } CTU_FILTER_16B_tag;
8186
8187 typedef union { /* CTU Expected A Value Register */
8188 uint16_t R;
8189 struct {
8190 uint16_t EXPECTED_A_VALUE:16; /* Expected A Value */
8191 } B;
8192 } CTU_EXPECTED_A_16B_tag;
8193
8194 typedef union { /* CTU Expected B Value Register */
8195 uint16_t R;
8196 struct {
8197 uint16_t EXPECTED_B_VALUE:16; /* Expected B Value */
8198 } B;
8199 } CTU_EXPECTED_B_16B_tag;
8200
8201 typedef union { /* CTU Counter Range Register */
8202 uint16_t R;
8203 struct {
8204 uint16_t:8;
8205 uint16_t CNT_RANGE_VALUE:8; /* Counter Range Value */
8206 } B;
8207 } CTU_CNT_RANGE_16B_tag;
8208
8209
8210 /* Register layout for generated register(s) FRA... */
8211
8212 typedef union { /* */
8213 uint32_t R;
8214 } CTU_FRA_32B_tag;
8215
8216
8217 /* Register layout for generated register(s) FLA... */
8218
8219 typedef union { /* */
8220 uint32_t R;
8221 } CTU_FLA_32B_tag;
8222
8223
8224
8225 typedef struct CTU_struct_tag { /* start of CTU_tag */
8226 /* Trigger Generator Subunit Input Selection register */
8227 CTU_TGSISR_32B_tag TGSISR; /* offset: 0x0000 size: 32 bit */
8228 /* Trigger Generator Subunit Control Register */
8229 CTU_TGSCR_16B_tag TGSCR; /* offset: 0x0004 size: 16 bit */
8230 union {
8231 CTU_TCR_16B_tag TCR[8]; /* offset: 0x0006 (0x0002 x 8) */
8232
8233 struct {
8234 CTU_TCR_16B_tag T0CR; /* offset: 0x0006 size: 16 bit */
8235 CTU_TCR_16B_tag T1CR; /* offset: 0x0008 size: 16 bit */
8236 CTU_TCR_16B_tag T2CR; /* offset: 0x000A size: 16 bit */
8237 CTU_TCR_16B_tag T3CR; /* offset: 0x000C size: 16 bit */
8238 CTU_TCR_16B_tag T4CR; /* offset: 0x000E size: 16 bit */
8239 CTU_TCR_16B_tag T5CR; /* offset: 0x0010 size: 16 bit */
8240 CTU_TCR_16B_tag T6CR; /* offset: 0x0012 size: 16 bit */
8241 CTU_TCR_16B_tag T7CR; /* offset: 0x0014 size: 16 bit */
8242 };
8243
8244 };
8245 /* TGS Counter Compare Register */
8246 CTU_TGSCCR_16B_tag TGSCCR; /* offset: 0x0016 size: 16 bit */
8247 /* TGS Counter Reload Register */
8248 CTU_TGSCRR_16B_tag TGSCRR; /* offset: 0x0018 size: 16 bit */
8249 int8_t CTU_reserved_001A[2];
8250 /* Commands List Control Register 1 */
8251 CTU_CLCR1_32B_tag CLCR1; /* offset: 0x001C size: 32 bit */
8252 /* Commands List Control Register 2 */
8253 CTU_CLCR2_32B_tag CLCR2; /* offset: 0x0020 size: 32 bit */
8254 /* Trigger Handler Control Register 1 */
8255 CTU_THCR1_32B_tag THCR1; /* offset: 0x0024 size: 32 bit */
8256 /* Trigger Handler Control Register 2 */
8257 CTU_THCR2_32B_tag THCR2; /* offset: 0x0028 size: 32 bit */
8258 union {
8259 /* Command List Register. View: BIT13, BIT9 */
8260 CTU_CLR_SCM_16B_tag CLR[24]; /* offset: 0x002C (0x0002 x 24) */ /* deprecated name - please avoid */
8261
8262 /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
8263 CTU_CLR_SCM_16B_tag CLR_SCM[24]; /* offset: 0x002C (0x0002 x 24) */
8264
8265 /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
8266 CTU_CLR_DCM_16B_tag CLR_DCM[24]; /* offset: 0x002C (0x0002 x 24) */
8267
8268 struct {
8269 /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
8270 CTU_CLR_SCM_16B_tag CLR_SCM1; /* offset: 0x002C size: 16 bit */
8271 CTU_CLR_SCM_16B_tag CLR_SCM2; /* offset: 0x002E size: 16 bit */
8272 CTU_CLR_SCM_16B_tag CLR_SCM3; /* offset: 0x0030 size: 16 bit */
8273 CTU_CLR_SCM_16B_tag CLR_SCM4; /* offset: 0x0032 size: 16 bit */
8274 CTU_CLR_SCM_16B_tag CLR_SCM5; /* offset: 0x0034 size: 16 bit */
8275 CTU_CLR_SCM_16B_tag CLR_SCM6; /* offset: 0x0036 size: 16 bit */
8276 CTU_CLR_SCM_16B_tag CLR_SCM7; /* offset: 0x0038 size: 16 bit */
8277 CTU_CLR_SCM_16B_tag CLR_SCM8; /* offset: 0x003A size: 16 bit */
8278 CTU_CLR_SCM_16B_tag CLR_SCM9; /* offset: 0x003C size: 16 bit */
8279 CTU_CLR_SCM_16B_tag CLR_SCM10; /* offset: 0x003E size: 16 bit */
8280 CTU_CLR_SCM_16B_tag CLR_SCM11; /* offset: 0x0040 size: 16 bit */
8281 CTU_CLR_SCM_16B_tag CLR_SCM12; /* offset: 0x0042 size: 16 bit */
8282 CTU_CLR_SCM_16B_tag CLR_SCM13; /* offset: 0x0044 size: 16 bit */
8283 CTU_CLR_SCM_16B_tag CLR_SCM14; /* offset: 0x0046 size: 16 bit */
8284 CTU_CLR_SCM_16B_tag CLR_SCM15; /* offset: 0x0048 size: 16 bit */
8285 CTU_CLR_SCM_16B_tag CLR_SCM16; /* offset: 0x004A size: 16 bit */
8286 CTU_CLR_SCM_16B_tag CLR_SCM17; /* offset: 0x004C size: 16 bit */
8287 CTU_CLR_SCM_16B_tag CLR_SCM18; /* offset: 0x004E size: 16 bit */
8288 CTU_CLR_SCM_16B_tag CLR_SCM19; /* offset: 0x0050 size: 16 bit */
8289 CTU_CLR_SCM_16B_tag CLR_SCM20; /* offset: 0x0052 size: 16 bit */
8290 CTU_CLR_SCM_16B_tag CLR_SCM21; /* offset: 0x0054 size: 16 bit */
8291 CTU_CLR_SCM_16B_tag CLR_SCM22; /* offset: 0x0056 size: 16 bit */
8292 CTU_CLR_SCM_16B_tag CLR_SCM23; /* offset: 0x0058 size: 16 bit */
8293 CTU_CLR_SCM_16B_tag CLR_SCM24; /* offset: 0x005A size: 16 bit */
8294 };
8295
8296 struct {
8297 /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
8298 CTU_CLR_DCM_16B_tag CLR_DCM1; /* offset: 0x002C size: 16 bit */
8299 CTU_CLR_DCM_16B_tag CLR_DCM2; /* offset: 0x002E size: 16 bit */
8300 CTU_CLR_DCM_16B_tag CLR_DCM3; /* offset: 0x0030 size: 16 bit */
8301 CTU_CLR_DCM_16B_tag CLR_DCM4; /* offset: 0x0032 size: 16 bit */
8302 CTU_CLR_DCM_16B_tag CLR_DCM5; /* offset: 0x0034 size: 16 bit */
8303 CTU_CLR_DCM_16B_tag CLR_DCM6; /* offset: 0x0036 size: 16 bit */
8304 CTU_CLR_DCM_16B_tag CLR_DCM7; /* offset: 0x0038 size: 16 bit */
8305 CTU_CLR_DCM_16B_tag CLR_DCM8; /* offset: 0x003A size: 16 bit */
8306 CTU_CLR_DCM_16B_tag CLR_DCM9; /* offset: 0x003C size: 16 bit */
8307 CTU_CLR_DCM_16B_tag CLR_DCM10; /* offset: 0x003E size: 16 bit */
8308 CTU_CLR_DCM_16B_tag CLR_DCM11; /* offset: 0x0040 size: 16 bit */
8309 CTU_CLR_DCM_16B_tag CLR_DCM12; /* offset: 0x0042 size: 16 bit */
8310 CTU_CLR_DCM_16B_tag CLR_DCM13; /* offset: 0x0044 size: 16 bit */
8311 CTU_CLR_DCM_16B_tag CLR_DCM14; /* offset: 0x0046 size: 16 bit */
8312 CTU_CLR_DCM_16B_tag CLR_DCM15; /* offset: 0x0048 size: 16 bit */
8313 CTU_CLR_DCM_16B_tag CLR_DCM16; /* offset: 0x004A size: 16 bit */
8314 CTU_CLR_DCM_16B_tag CLR_DCM17; /* offset: 0x004C size: 16 bit */
8315 CTU_CLR_DCM_16B_tag CLR_DCM18; /* offset: 0x004E size: 16 bit */
8316 CTU_CLR_DCM_16B_tag CLR_DCM19; /* offset: 0x0050 size: 16 bit */
8317 CTU_CLR_DCM_16B_tag CLR_DCM20; /* offset: 0x0052 size: 16 bit */
8318 CTU_CLR_DCM_16B_tag CLR_DCM21; /* offset: 0x0054 size: 16 bit */
8319 CTU_CLR_DCM_16B_tag CLR_DCM22; /* offset: 0x0056 size: 16 bit */
8320 CTU_CLR_DCM_16B_tag CLR_DCM23; /* offset: 0x0058 size: 16 bit */
8321 CTU_CLR_DCM_16B_tag CLR_DCM24; /* offset: 0x005A size: 16 bit */
8322 };
8323
8324 };
8325 int8_t CTU_reserved_005C[16];
8326 /* Control Register */
8327 CTU_CR_16B_tag CR; /* offset: 0x006C size: 16 bit */
8328 int8_t CTU_reserved_006E[2];
8329 /* Control Register FIFO */
8330 CTU_FCR_32B_tag FCR; /* offset: 0x0070 size: 32 bit */
8331 /* Threshold 1 Register */
8332 CTU_TH1_32B_tag TH1; /* offset: 0x0074 size: 32 bit */
8333 /* Threshold 2 Register */
8334 CTU_TH2_32B_tag TH2; /* offset: 0x0078 size: 32 bit */
8335 union {
8336 /* Status Register */
8337 CTU_STS_32B_tag STS; /* offset: 0x007C size: 32 bit */
8338
8339 CTU_STS_32B_tag STATUS; /* deprecated - please avoid */
8340
8341 };
8342 union {
8343 CTU_FRA_32B_tag FRA[8]; /* offset: 0x0080 (0x0004 x 8) */
8344
8345 /* FIFO Right Aligned register */
8346 CTU_FR_32B_tag FR[8]; /* offset: 0x0080 (0x0004 x 8) */
8347
8348 struct {
8349 /* FIFO Right Aligned register */
8350 CTU_FR_32B_tag FR0; /* offset: 0x0080 size: 32 bit */
8351 CTU_FR_32B_tag FR1; /* offset: 0x0084 size: 32 bit */
8352 CTU_FR_32B_tag FR2; /* offset: 0x0088 size: 32 bit */
8353 CTU_FR_32B_tag FR3; /* offset: 0x008C size: 32 bit */
8354 CTU_FR_32B_tag FR4; /* offset: 0x0090 size: 32 bit */
8355 CTU_FR_32B_tag FR5; /* offset: 0x0094 size: 32 bit */
8356 CTU_FR_32B_tag FR6; /* offset: 0x0098 size: 32 bit */
8357 CTU_FR_32B_tag FR7; /* offset: 0x009C size: 32 bit */
8358 };
8359
8360 };
8361 union {
8362 CTU_FLA_32B_tag FLA[8]; /* offset: 0x00A0 (0x0004 x 8) */
8363
8364 /* FIFO Left Aligned register */
8365 CTU_FL_32B_tag FL[8]; /* offset: 0x00A0 (0x0004 x 8) */
8366
8367 struct {
8368 /* FIFO Left Aligned register */
8369 CTU_FL_32B_tag FL0; /* offset: 0x00A0 size: 32 bit */
8370 CTU_FL_32B_tag FL1; /* offset: 0x00A4 size: 32 bit */
8371 CTU_FL_32B_tag FL2; /* offset: 0x00A8 size: 32 bit */
8372 CTU_FL_32B_tag FL3; /* offset: 0x00AC size: 32 bit */
8373 CTU_FL_32B_tag FL4; /* offset: 0x00B0 size: 32 bit */
8374 CTU_FL_32B_tag FL5; /* offset: 0x00B4 size: 32 bit */
8375 CTU_FL_32B_tag FL6; /* offset: 0x00B8 size: 32 bit */
8376 CTU_FL_32B_tag FL7; /* offset: 0x00BC size: 32 bit */
8377 };
8378
8379 };
8380 /* CTU Error Flag Register */
8381 CTU_CTUEFR_16B_tag CTUEFR; /* offset: 0x00C0 size: 16 bit */
8382 /* CTU Interrupt Flag Register */
8383 CTU_CTUIFR_16B_tag CTUIFR; /* offset: 0x00C2 size: 16 bit */
8384 /* CTU Interrupt/DMA Register */
8385 CTU_CTUIR_16B_tag CTUIR; /* offset: 0x00C4 size: 16 bit */
8386 /* Control On-Time Register */
8387 CTU_COTR_16B_tag COTR; /* offset: 0x00C6 size: 16 bit */
8388 /* CTU Control Register */
8389 CTU_CTUCR_16B_tag CTUCR; /* offset: 0x00C8 size: 16 bit */
8390 union {
8391 /* CTU Digital Filter Register */
8392 CTU_FILTER_16B_tag FILTER; /* offset: 0x00CA size: 16 bit */
8393
8394 CTU_FILTER_16B_tag CTUFILTER; /* deprecated - please avoid */
8395
8396 };
8397 /* CTU Expected A Value Register */
8398 CTU_EXPECTED_A_16B_tag EXPECTED_A; /* offset: 0x00CC size: 16 bit */
8399
8400 /* CTU Expected B Value Register */
8401 CTU_EXPECTED_B_16B_tag EXPECTED_B; /* offset: 0x00CE size: 16 bit */
8402 /* CTU Counter Range Register */
8403 CTU_CNT_RANGE_16B_tag CNT_RANGE; /* offset: 0x00D0 size: 16 bit */
8404 } CTU_tag;
8405
8406
8407#define CTU (*(volatile CTU_tag *) 0xFFE0C000UL)
8408
8409
8410
8411/****************************************************************/
8412/* */
8413/* Module: mcTIMER */
8414/* */
8415/****************************************************************/
8416
8417
8418 /* Register layout for all registers COMP1... */
8419
8420 typedef union { /* Compare Register 1 */
8421 uint16_t R;
8422 struct {
8423 uint16_t COMP1:16; /* deprecated definition -- do not use */
8424 } B;
8425 } mcTIMER_COMP1_16B_tag;
8426
8427
8428 /* Register layout for all registers COMP2... */
8429
8430 typedef union { /* Compare Register 2 */
8431 uint16_t R;
8432 struct {
8433 uint16_t COMP2:16; /* deprecated definition -- do not use */
8434 } B;
8435 } mcTIMER_COMP2_16B_tag;
8436
8437
8438 /* Register layout for all registers CAPT1... */
8439
8440 typedef union { /* Capture Register 1 */
8441 uint16_t R;
8442 struct {
8443 uint16_t CAPT1:16; /* deprecated definition -- do not use */
8444 } B;
8445 } mcTIMER_CAPT1_16B_tag;
8446
8447
8448 /* Register layout for all registers CAPT2... */
8449
8450 typedef union { /* Capture Register 2 */
8451 uint16_t R;
8452 struct {
8453 uint16_t CAPT2:16; /* deprecated definition -- do not use */
8454 } B;
8455 } mcTIMER_CAPT2_16B_tag;
8456
8457
8458 /* Register layout for all registers LOAD... */
8459
8460 typedef union { /* Load Register */
8461 uint16_t R;
8462 struct {
8463 uint16_t LOAD:16; /* deprecated definition -- do not use */
8464 } B;
8465 } mcTIMER_LOAD_16B_tag;
8466
8467
8468 /* Register layout for all registers HOLD... */
8469
8470 typedef union { /* Hold Register */
8471 uint16_t R;
8472 struct {
8473 uint16_t HOLD:16; /* deprecated definition -- do not use */
8474 } B;
8475 } mcTIMER_HOLD_16B_tag;
8476
8477
8478 /* Register layout for all registers CNTR... */
8479
8480 typedef union { /* Counter Register */
8481 uint16_t R;
8482 struct {
8483 uint16_t CNTR:16; /* deprecated definition -- do not use */
8484 } B;
8485 } mcTIMER_CNTR_16B_tag;
8486
8487
8488 /* Register layout for all registers CTRL1... */
8489
8490 typedef union { /* Control Register */
8491 uint16_t R;
8492 struct {
8493 uint16_t CNTMODE:3; /* Count Mode */
8494 uint16_t PRISRC:5; /* Primary Count Source */
8495 uint16_t ONCE:1; /* Count Once */
8496 uint16_t LENGTH:1; /* Count Length */
8497 uint16_t DIR:1; /* Count Direction */
8498 uint16_t SECSRC:5; /* Secondary Count Source */
8499 } B;
8500 } mcTIMER_CTRL1_16B_tag;
8501
8502
8503 /* Register layout for all registers CTRL2... */
8504
8505 typedef union { /* Control Register 2 */
8506 uint16_t R;
8507 struct {
8508 uint16_t OEN:1; /* Output Enable */
8509 uint16_t RDNT:1; /* Redundant Channel Enable */
8510 uint16_t INPUT:1; /* External Input Signal */
8511 uint16_t VAL:1; /* Forced OFLAG Value */
8512 uint16_t FORCE:1; /* Force the OFLAG output */
8513 uint16_t COFRC:1; /* Co-channel OFLAG Force */
8514 uint16_t COINIT:2; /* Co-channel Initialization */
8515 uint16_t SIPS:1; /* Secondary Source Input Polarity Select */
8516 uint16_t PIPS:1; /* Primary Source Input Polarity Select */
8517 uint16_t OPS:1; /* Output Polarity Select */
8518 uint16_t MSTR:1; /* Master Mode */
8519 uint16_t OUTMODE:4; /* Output Mode */
8520 } B;
8521 } mcTIMER_CTRL2_16B_tag;
8522
8523
8524 /* Register layout for all registers CTRL3... */
8525
8526 typedef union { /* Control Register 3 */
8527 uint16_t R;
8528 struct {
8529 uint16_t STPEN:1; /* Stop Action Enable */
8530 uint16_t ROC:2; /* Reload On Capture */
8531 uint16_t FMODE:1; /* Fault Safing Mode */
8532 uint16_t FDIS:4; /* Fault Disable Mask */
8533 uint16_t C2FCNT:3; /* CAPT2 FIFO Word Count */
8534 uint16_t C1FCNT:3; /* CAPT1 FIFO Word Count */
8535 uint16_t DBGEN:2; /* Debug Actions Enable */
8536 } B;
8537 } mcTIMER_CTRL3_16B_tag;
8538
8539
8540 /* Register layout for all registers STS... */
8541
8542 typedef union { /* Status Register */
8543 uint16_t R;
8544 struct {
8545 uint16_t:6;
8546 uint16_t WDF:1; /* Watchdog Time-out Flag */
8547 uint16_t RCF:1; /* Redundant Channel Flag */
8548 uint16_t ICF2:1; /* Input Capture 2 Flag */
8549 uint16_t ICF1:1; /* Input Capture 1 Flag */
8550 uint16_t IEHF:1; /* Input Edge High Flag */
8551 uint16_t IELF:1; /* Input Edge Low Flag */
8552 uint16_t TOF:1; /* Timer Overflow Flag */
8553 uint16_t TCF2:1; /* Timer Compare 2 Flag */
8554 uint16_t TCF1:1; /* Timer Compare 1 Flag */
8555 uint16_t TCF:1; /* Timer Compare Flag */
8556 } B;
8557 } mcTIMER_STS_16B_tag;
8558
8559
8560 /* Register layout for all registers INTDMA... */
8561
8562 typedef union { /* Interrupt and DMA Enable Register */
8563 uint16_t R;
8564 struct {
8565 uint16_t ICF2DE:1; /* Input Capture 2 Flag DMA Enable */
8566 uint16_t ICF1DE:1; /* Input Capture 1 Flag DMA Enable */
8567 uint16_t CMPLD2DE:1; /* Comparator Load Register 2 Flag DMA Enable */
8568 uint16_t CMPLD1DE:1; /* Comparator Load Register 1 Flag DMA Enable */
8569 uint16_t:2;
8570 uint16_t WDFIE:1; /* Watchdog Flag Interrupt Enable */
8571 uint16_t RCFIE:1; /* Redundant Channel Flag Interrupt Enable */
8572 uint16_t ICF2IE:1; /* Input Capture 2 Flag Interrupt Enable */
8573 uint16_t ICF1IE:1; /* Input Capture 1 Flag Interrupt Enable */
8574 uint16_t IEHFIE:1; /* Input Edge High Flag Interrupt Enable */
8575 uint16_t IELFIE:1; /* Input Edge Low Flag Interrupt Enable */
8576 uint16_t TOFIE:1; /* Timer Overflow Flag Interrupt Enable */
8577 uint16_t TCF2IE:1; /* Timer Compare 2 Flag Interrupt Enable */
8578 uint16_t TCF1IE:1; /* Timer Compare 1 Flag Interrupt Enable */
8579 uint16_t TCFIE:1; /* Timer Compare Flag Interrupt Enable */
8580 } B;
8581 } mcTIMER_INTDMA_16B_tag;
8582
8583
8584 /* Register layout for all registers CMPLD1... */
8585
8586 typedef union { /* Comparator Load Register 1 */
8587 uint16_t R;
8588 struct {
8589 uint16_t CMPLD1:16; /* deprecated definition -- do not use */
8590 } B;
8591 } mcTIMER_CMPLD1_16B_tag;
8592
8593
8594 /* Register layout for all registers CMPLD2... */
8595
8596 typedef union { /* Comparator Load Register 2 */
8597 uint16_t R;
8598 struct {
8599 uint16_t CMPLD2:16; /* deprecated definition -- do not use */
8600 } B;
8601 } mcTIMER_CMPLD2_16B_tag;
8602
8603
8604 /* Register layout for all registers CCCTRL... */
8605
8606 typedef union { /* Compare and Capture Control Register */
8607 uint16_t R;
8608 struct {
8609 uint16_t CLC2:3; /* Compare Load Control 2 */
8610 uint16_t CLC1:3; /* Compare Load Control 1 */
8611 uint16_t CMPMODE:2; /* Compare Mode */
8612 uint16_t CPT2MODE:2; /* Capture 2 Mode Control */
8613 uint16_t CPT1MODE:2; /* Capture 1 Mode Control */
8614 uint16_t CFWM:2; /* Capture FIFO Water Mark */
8615 uint16_t ONESHOT:1; /* One Shot Capture Mode */
8616 uint16_t ARM:1; /* Arm Capture */
8617 } B;
8618 } mcTIMER_CCCTRL_16B_tag;
8619
8620
8621 /* Register layout for all registers FILT... */
8622
8623 typedef union { /* Input Filter Register */
8624 uint16_t R;
8625 struct {
8626 uint16_t:5;
8627#ifndef USE_FIELD_ALIASES_mcTIMER
8628 uint16_t FILT_CNT:3; /* Input Filter Sample Count */
8629#else
8630 uint16_t FILTCNT:3; /* deprecated name - please avoid */
8631#endif
8632#ifndef USE_FIELD_ALIASES_mcTIMER
8633 uint16_t FILT_PER:8; /* Input Filter Sample Period */
8634#else
8635 uint16_t FILTPER:8; /* deprecated name - please avoid */
8636#endif
8637 } B;
8638 } mcTIMER_FILT_16B_tag;
8639
8640 typedef union { /* Watchdog Time-out Register */
8641 uint16_t R;
8642 struct {
8643 uint16_t WDTOL:16; /* deprecated definition -- do not use */
8644 } B;
8645 } mcTIMER_WDTOL_16B_tag;
8646
8647 typedef union { /* Watchdog Time-out Register */
8648 uint16_t R;
8649 struct {
8650 uint16_t WDTOH:16; /* deprecated definition -- do not use */
8651 } B;
8652 } mcTIMER_WDTOH_16B_tag;
8653
8654 typedef union { /* Fault Control Register */
8655 uint16_t R;
8656 struct {
8657 uint16_t:3;
8658 uint16_t FTEST:1; /* Fault Test */
8659 uint16_t FIE:4; /* Fault Interrupt Enable */
8660 uint16_t:4;
8661 uint16_t FLVL:4; /* Fault Active Logic Level */
8662 } B;
8663 } mcTIMER_FCTRL_16B_tag;
8664
8665 typedef union { /* Fault Status Register */
8666 uint16_t R;
8667 struct {
8668 uint16_t:4;
8669 uint16_t FFPIN:4; /* Filtered Fault Pin */
8670 uint16_t:4;
8671 uint16_t FFLAG:4; /* Fault Flag */
8672 } B;
8673 } mcTIMER_FSTS_16B_tag;
8674
8675 typedef union { /* Fault Filter Registers */
8676 uint16_t R;
8677 struct {
8678 uint16_t:5;
8679#ifndef USE_FIELD_ALIASES_mcTIMER
8680 uint16_t FFPIN:3; /* Fault Filter Sample Count */
8681#else
8682 uint16_t FFILTCNT:3; /* deprecated name - please avoid */
8683#endif
8684#ifndef USE_FIELD_ALIASES_mcTIMER
8685 uint16_t FFILT_PER:8; /* Fault Filter Sample Period */
8686#else
8687 uint16_t FFILTPER:8; /* deprecated name - please avoid */
8688#endif
8689 } B;
8690 } mcTIMER_FFILT_16B_tag;
8691
8692 typedef union { /* Channel Enable Registers */
8693 uint16_t R;
8694 struct {
8695 uint16_t:8;
8696 uint16_t ENBL:8; /* Timer Channel Enable */
8697 } B;
8698 } mcTIMER_ENBL_16B_tag;
8699
8700 typedef union { /* DMA Request 0 Select Registers */
8701 uint16_t R;
8702 struct {
8703 uint16_t:11;
8704 uint16_t DREQ0V:5; /* DMA Request Select */
8705 } B;
8706 } mcTIMER_DREQ0_16B_tag;
8707
8708 typedef union { /* DMA Request 1 Select Registers */
8709 uint16_t R;
8710 struct {
8711 uint16_t:11;
8712 uint16_t DREQ1V:5; /* DMA Request Select */
8713 } B;
8714 } mcTIMER_DREQ1_16B_tag;
8715
8716 typedef union { /* DMA Request 2 Select Registers */
8717 uint16_t R;
8718 struct {
8719 uint16_t:11;
8720 uint16_t DREQ2V:5; /* DMA Request Select */
8721 } B;
8722 } mcTIMER_DREQ2_16B_tag;
8723
8724 typedef union { /* DMA Request 3 Select Registers */
8725 uint16_t R;
8726 struct {
8727 uint16_t:11;
8728 uint16_t DREQ3V:5; /* DMA Request Select */
8729 } B;
8730 } mcTIMER_DREQ3_16B_tag;
8731
8732
8733 /* Register layout for generated register(s) DREQ... */
8734
8735 typedef union { /* */
8736 uint16_t R;
8737 } mcTIMER_DREQ_16B_tag;
8738
8739
8740 typedef struct mcTIMER_CHANNEL_struct_tag {
8741
8742 /* Compare Register 1 */
8743 mcTIMER_COMP1_16B_tag COMP1; /* relative offset: 0x0000 */
8744 /* Compare Register 2 */
8745 mcTIMER_COMP2_16B_tag COMP2; /* relative offset: 0x0002 */
8746 /* Capture Register 1 */
8747 mcTIMER_CAPT1_16B_tag CAPT1; /* relative offset: 0x0004 */
8748 /* Capture Register 2 */
8749 mcTIMER_CAPT2_16B_tag CAPT2; /* relative offset: 0x0006 */
8750 /* Load Register */
8751 mcTIMER_LOAD_16B_tag LOAD; /* relative offset: 0x0008 */
8752 /* Hold Register */
8753 mcTIMER_HOLD_16B_tag HOLD; /* relative offset: 0x000A */
8754 /* Counter Register */
8755 mcTIMER_CNTR_16B_tag CNTR; /* relative offset: 0x000C */
8756 union {
8757 /* Control Register */
8758 mcTIMER_CTRL1_16B_tag CTRL1; /* relative offset: 0x000E */
8759 mcTIMER_CTRL1_16B_tag CTRL; /* deprecated - please avoid */
8760 };
8761 /* Control Register 2 */
8762 mcTIMER_CTRL2_16B_tag CTRL2; /* relative offset: 0x0010 */
8763 /* Control Register 3 */
8764 mcTIMER_CTRL3_16B_tag CTRL3; /* relative offset: 0x0012 */
8765 /* Status Register */
8766 mcTIMER_STS_16B_tag STS; /* relative offset: 0x0014 */
8767 /* Interrupt and DMA Enable Register */
8768 mcTIMER_INTDMA_16B_tag INTDMA; /* relative offset: 0x0016 */
8769 /* Comparator Load Register 1 */
8770 mcTIMER_CMPLD1_16B_tag CMPLD1; /* relative offset: 0x0018 */
8771 /* Comparator Load Register 2 */
8772 mcTIMER_CMPLD2_16B_tag CMPLD2; /* relative offset: 0x001A */
8773 /* Compare and Capture Control Register */
8774 mcTIMER_CCCTRL_16B_tag CCCTRL; /* relative offset: 0x001C */
8775 /* Input Filter Register */
8776 mcTIMER_FILT_16B_tag FILT; /* relative offset: 0x001E */
8777
8778 } mcTIMER_CHANNEL_tag;
8779
8780
8781 typedef struct mcTIMER_struct_tag { /* start of mcTIMER_tag */
8782 union {
8783 /* Register set CHANNEL */
8784 mcTIMER_CHANNEL_tag CHANNEL[6]; /* offset: 0x0000 (0x0020 x 6) */
8785
8786 struct {
8787 /* Compare Register 1 */
8788 mcTIMER_COMP1_16B_tag COMP10; /* offset: 0x0000 size: 16 bit */
8789 /* Compare Register 2 */
8790 mcTIMER_COMP2_16B_tag COMP20; /* offset: 0x0002 size: 16 bit */
8791 /* Capture Register 1 */
8792 mcTIMER_CAPT1_16B_tag CAPT10; /* offset: 0x0004 size: 16 bit */
8793 /* Capture Register 2 */
8794 mcTIMER_CAPT2_16B_tag CAPT20; /* offset: 0x0006 size: 16 bit */
8795 /* Load Register */
8796 mcTIMER_LOAD_16B_tag LOAD0; /* offset: 0x0008 size: 16 bit */
8797 /* Hold Register */
8798 mcTIMER_HOLD_16B_tag HOLD0; /* offset: 0x000A size: 16 bit */
8799 /* Counter Register */
8800 mcTIMER_CNTR_16B_tag CNTR0; /* offset: 0x000C size: 16 bit */
8801 /* Control Register */
8802 mcTIMER_CTRL1_16B_tag CTRL10; /* offset: 0x000E size: 16 bit */
8803 /* Control Register 2 */
8804 mcTIMER_CTRL2_16B_tag CTRL20; /* offset: 0x0010 size: 16 bit */
8805 /* Control Register 3 */
8806 mcTIMER_CTRL3_16B_tag CTRL30; /* offset: 0x0012 size: 16 bit */
8807 /* Status Register */
8808 mcTIMER_STS_16B_tag STS0; /* offset: 0x0014 size: 16 bit */
8809 /* Interrupt and DMA Enable Register */
8810 mcTIMER_INTDMA_16B_tag INTDMA0; /* offset: 0x0016 size: 16 bit */
8811 /* Comparator Load Register 1 */
8812 mcTIMER_CMPLD1_16B_tag CMPLD10; /* offset: 0x0018 size: 16 bit */
8813 /* Comparator Load Register 2 */
8814 mcTIMER_CMPLD2_16B_tag CMPLD20; /* offset: 0x001A size: 16 bit */
8815 /* Compare and Capture Control Register */
8816 mcTIMER_CCCTRL_16B_tag CCCTRL0; /* offset: 0x001C size: 16 bit */
8817 /* Input Filter Register */
8818 mcTIMER_FILT_16B_tag FILT0; /* offset: 0x001E size: 16 bit */
8819 /* Compare Register 1 */
8820 mcTIMER_COMP1_16B_tag COMP11; /* offset: 0x0020 size: 16 bit */
8821 /* Compare Register 2 */
8822 mcTIMER_COMP2_16B_tag COMP21; /* offset: 0x0022 size: 16 bit */
8823 /* Capture Register 1 */
8824 mcTIMER_CAPT1_16B_tag CAPT11; /* offset: 0x0024 size: 16 bit */
8825 /* Capture Register 2 */
8826 mcTIMER_CAPT2_16B_tag CAPT21; /* offset: 0x0026 size: 16 bit */
8827 /* Load Register */
8828 mcTIMER_LOAD_16B_tag LOAD1; /* offset: 0x0028 size: 16 bit */
8829 /* Hold Register */
8830 mcTIMER_HOLD_16B_tag HOLD1; /* offset: 0x002A size: 16 bit */
8831 /* Counter Register */
8832 mcTIMER_CNTR_16B_tag CNTR1; /* offset: 0x002C size: 16 bit */
8833 /* Control Register */
8834 mcTIMER_CTRL1_16B_tag CTRL11; /* offset: 0x002E size: 16 bit */
8835 /* Control Register 2 */
8836 mcTIMER_CTRL2_16B_tag CTRL21; /* offset: 0x0030 size: 16 bit */
8837 /* Control Register 3 */
8838 mcTIMER_CTRL3_16B_tag CTRL31; /* offset: 0x0032 size: 16 bit */
8839 /* Status Register */
8840 mcTIMER_STS_16B_tag STS1; /* offset: 0x0034 size: 16 bit */
8841 /* Interrupt and DMA Enable Register */
8842 mcTIMER_INTDMA_16B_tag INTDMA1; /* offset: 0x0036 size: 16 bit */
8843 /* Comparator Load Register 1 */
8844 mcTIMER_CMPLD1_16B_tag CMPLD11; /* offset: 0x0038 size: 16 bit */
8845 /* Comparator Load Register 2 */
8846 mcTIMER_CMPLD2_16B_tag CMPLD21; /* offset: 0x003A size: 16 bit */
8847 /* Compare and Capture Control Register */
8848 mcTIMER_CCCTRL_16B_tag CCCTRL1; /* offset: 0x003C size: 16 bit */
8849 /* Input Filter Register */
8850 mcTIMER_FILT_16B_tag FILT1; /* offset: 0x003E size: 16 bit */
8851 /* Compare Register 1 */
8852 mcTIMER_COMP1_16B_tag COMP12; /* offset: 0x0040 size: 16 bit */
8853 /* Compare Register 2 */
8854 mcTIMER_COMP2_16B_tag COMP22; /* offset: 0x0042 size: 16 bit */
8855 /* Capture Register 1 */
8856 mcTIMER_CAPT1_16B_tag CAPT12; /* offset: 0x0044 size: 16 bit */
8857 /* Capture Register 2 */
8858 mcTIMER_CAPT2_16B_tag CAPT22; /* offset: 0x0046 size: 16 bit */
8859 /* Load Register */
8860 mcTIMER_LOAD_16B_tag LOAD2; /* offset: 0x0048 size: 16 bit */
8861 /* Hold Register */
8862 mcTIMER_HOLD_16B_tag HOLD2; /* offset: 0x004A size: 16 bit */
8863 /* Counter Register */
8864 mcTIMER_CNTR_16B_tag CNTR2; /* offset: 0x004C size: 16 bit */
8865 /* Control Register */
8866 mcTIMER_CTRL1_16B_tag CTRL12; /* offset: 0x004E size: 16 bit */
8867 /* Control Register 2 */
8868 mcTIMER_CTRL2_16B_tag CTRL22; /* offset: 0x0050 size: 16 bit */
8869 /* Control Register 3 */
8870 mcTIMER_CTRL3_16B_tag CTRL32; /* offset: 0x0052 size: 16 bit */
8871 /* Status Register */
8872 mcTIMER_STS_16B_tag STS2; /* offset: 0x0054 size: 16 bit */
8873 /* Interrupt and DMA Enable Register */
8874 mcTIMER_INTDMA_16B_tag INTDMA2; /* offset: 0x0056 size: 16 bit */
8875 /* Comparator Load Register 1 */
8876 mcTIMER_CMPLD1_16B_tag CMPLD12; /* offset: 0x0058 size: 16 bit */
8877 /* Comparator Load Register 2 */
8878 mcTIMER_CMPLD2_16B_tag CMPLD22; /* offset: 0x005A size: 16 bit */
8879 /* Compare and Capture Control Register */
8880 mcTIMER_CCCTRL_16B_tag CCCTRL2; /* offset: 0x005C size: 16 bit */
8881 /* Input Filter Register */
8882 mcTIMER_FILT_16B_tag FILT2; /* offset: 0x005E size: 16 bit */
8883 /* Compare Register 1 */
8884 mcTIMER_COMP1_16B_tag COMP13; /* offset: 0x0060 size: 16 bit */
8885 /* Compare Register 2 */
8886 mcTIMER_COMP2_16B_tag COMP23; /* offset: 0x0062 size: 16 bit */
8887 /* Capture Register 1 */
8888 mcTIMER_CAPT1_16B_tag CAPT13; /* offset: 0x0064 size: 16 bit */
8889 /* Capture Register 2 */
8890 mcTIMER_CAPT2_16B_tag CAPT23; /* offset: 0x0066 size: 16 bit */
8891 /* Load Register */
8892 mcTIMER_LOAD_16B_tag LOAD3; /* offset: 0x0068 size: 16 bit */
8893 /* Hold Register */
8894 mcTIMER_HOLD_16B_tag HOLD3; /* offset: 0x006A size: 16 bit */
8895 /* Counter Register */
8896 mcTIMER_CNTR_16B_tag CNTR3; /* offset: 0x006C size: 16 bit */
8897 /* Control Register */
8898 mcTIMER_CTRL1_16B_tag CTRL13; /* offset: 0x006E size: 16 bit */
8899 /* Control Register 2 */
8900 mcTIMER_CTRL2_16B_tag CTRL23; /* offset: 0x0070 size: 16 bit */
8901 /* Control Register 3 */
8902 mcTIMER_CTRL3_16B_tag CTRL33; /* offset: 0x0072 size: 16 bit */
8903 /* Status Register */
8904 mcTIMER_STS_16B_tag STS3; /* offset: 0x0074 size: 16 bit */
8905 /* Interrupt and DMA Enable Register */
8906 mcTIMER_INTDMA_16B_tag INTDMA3; /* offset: 0x0076 size: 16 bit */
8907 /* Comparator Load Register 1 */
8908 mcTIMER_CMPLD1_16B_tag CMPLD13; /* offset: 0x0078 size: 16 bit */
8909 /* Comparator Load Register 2 */
8910 mcTIMER_CMPLD2_16B_tag CMPLD23; /* offset: 0x007A size: 16 bit */
8911 /* Compare and Capture Control Register */
8912 mcTIMER_CCCTRL_16B_tag CCCTRL3; /* offset: 0x007C size: 16 bit */
8913 /* Input Filter Register */
8914 mcTIMER_FILT_16B_tag FILT3; /* offset: 0x007E size: 16 bit */
8915 /* Compare Register 1 */
8916 mcTIMER_COMP1_16B_tag COMP14; /* offset: 0x0080 size: 16 bit */
8917 /* Compare Register 2 */
8918 mcTIMER_COMP2_16B_tag COMP24; /* offset: 0x0082 size: 16 bit */
8919 /* Capture Register 1 */
8920 mcTIMER_CAPT1_16B_tag CAPT14; /* offset: 0x0084 size: 16 bit */
8921 /* Capture Register 2 */
8922 mcTIMER_CAPT2_16B_tag CAPT24; /* offset: 0x0086 size: 16 bit */
8923 /* Load Register */
8924 mcTIMER_LOAD_16B_tag LOAD4; /* offset: 0x0088 size: 16 bit */
8925 /* Hold Register */
8926 mcTIMER_HOLD_16B_tag HOLD4; /* offset: 0x008A size: 16 bit */
8927 /* Counter Register */
8928 mcTIMER_CNTR_16B_tag CNTR4; /* offset: 0x008C size: 16 bit */
8929 /* Control Register */
8930 mcTIMER_CTRL1_16B_tag CTRL14; /* offset: 0x008E size: 16 bit */
8931 /* Control Register 2 */
8932 mcTIMER_CTRL2_16B_tag CTRL24; /* offset: 0x0090 size: 16 bit */
8933 /* Control Register 3 */
8934 mcTIMER_CTRL3_16B_tag CTRL34; /* offset: 0x0092 size: 16 bit */
8935 /* Status Register */
8936 mcTIMER_STS_16B_tag STS4; /* offset: 0x0094 size: 16 bit */
8937 /* Interrupt and DMA Enable Register */
8938 mcTIMER_INTDMA_16B_tag INTDMA4; /* offset: 0x0096 size: 16 bit */
8939 /* Comparator Load Register 1 */
8940 mcTIMER_CMPLD1_16B_tag CMPLD14; /* offset: 0x0098 size: 16 bit */
8941 /* Comparator Load Register 2 */
8942 mcTIMER_CMPLD2_16B_tag CMPLD24; /* offset: 0x009A size: 16 bit */
8943 /* Compare and Capture Control Register */
8944 mcTIMER_CCCTRL_16B_tag CCCTRL4; /* offset: 0x009C size: 16 bit */
8945 /* Input Filter Register */
8946 mcTIMER_FILT_16B_tag FILT4; /* offset: 0x009E size: 16 bit */
8947 /* Compare Register 1 */
8948 mcTIMER_COMP1_16B_tag COMP15; /* offset: 0x00A0 size: 16 bit */
8949 /* Compare Register 2 */
8950 mcTIMER_COMP2_16B_tag COMP25; /* offset: 0x00A2 size: 16 bit */
8951 /* Capture Register 1 */
8952 mcTIMER_CAPT1_16B_tag CAPT15; /* offset: 0x00A4 size: 16 bit */
8953 /* Capture Register 2 */
8954 mcTIMER_CAPT2_16B_tag CAPT25; /* offset: 0x00A6 size: 16 bit */
8955 /* Load Register */
8956 mcTIMER_LOAD_16B_tag LOAD5; /* offset: 0x00A8 size: 16 bit */
8957 /* Hold Register */
8958 mcTIMER_HOLD_16B_tag HOLD5; /* offset: 0x00AA size: 16 bit */
8959 /* Counter Register */
8960 mcTIMER_CNTR_16B_tag CNTR5; /* offset: 0x00AC size: 16 bit */
8961 /* Control Register */
8962 mcTIMER_CTRL1_16B_tag CTRL15; /* offset: 0x00AE size: 16 bit */
8963 /* Control Register 2 */
8964 mcTIMER_CTRL2_16B_tag CTRL25; /* offset: 0x00B0 size: 16 bit */
8965 /* Control Register 3 */
8966 mcTIMER_CTRL3_16B_tag CTRL35; /* offset: 0x00B2 size: 16 bit */
8967 /* Status Register */
8968 mcTIMER_STS_16B_tag STS5; /* offset: 0x00B4 size: 16 bit */
8969 /* Interrupt and DMA Enable Register */
8970 mcTIMER_INTDMA_16B_tag INTDMA5; /* offset: 0x00B6 size: 16 bit */
8971 /* Comparator Load Register 1 */
8972 mcTIMER_CMPLD1_16B_tag CMPLD15; /* offset: 0x00B8 size: 16 bit */
8973 /* Comparator Load Register 2 */
8974 mcTIMER_CMPLD2_16B_tag CMPLD25; /* offset: 0x00BA size: 16 bit */
8975 /* Compare and Capture Control Register */
8976 mcTIMER_CCCTRL_16B_tag CCCTRL5; /* offset: 0x00BC size: 16 bit */
8977 /* Input Filter Register */
8978 mcTIMER_FILT_16B_tag FILT5; /* offset: 0x00BE size: 16 bit */
8979 };
8980
8981 };
8982 int8_t mcTIMER_reserved_00C0[64];
8983 /* Watchdog Time-out Register */
8984 mcTIMER_WDTOL_16B_tag WDTOL; /* offset: 0x0100 size: 16 bit */
8985 /* Watchdog Time-out Register */
8986 mcTIMER_WDTOH_16B_tag WDTOH; /* offset: 0x0102 size: 16 bit */
8987 /* Fault Control Register */
8988 mcTIMER_FCTRL_16B_tag FCTRL; /* offset: 0x0104 size: 16 bit */
8989 /* Fault Status Register */
8990 mcTIMER_FSTS_16B_tag FSTS; /* offset: 0x0106 size: 16 bit */
8991 /* Fault Filter Registers */
8992 mcTIMER_FFILT_16B_tag FFILT; /* offset: 0x0108 size: 16 bit */
8993 int8_t mcTIMER_reserved_010A[2];
8994 /* Channel Enable Registers */
8995 mcTIMER_ENBL_16B_tag ENBL; /* offset: 0x010C size: 16 bit */
8996 int8_t mcTIMER_reserved_010E_C[2];
8997 union {
8998 mcTIMER_DREQ_16B_tag DREQ[4]; /* offset: 0x0110 (0x0002 x 4) */
8999
9000 struct {
9001 /* DMA Request 0 Select Registers */
9002 mcTIMER_DREQ0_16B_tag DREQ0; /* offset: 0x0110 size: 16 bit */
9003 /* DMA Request 1 Select Registers */
9004 mcTIMER_DREQ1_16B_tag DREQ1; /* offset: 0x0112 size: 16 bit */
9005 /* DMA Request 2 Select Registers */
9006 mcTIMER_DREQ2_16B_tag DREQ2; /* offset: 0x0114 size: 16 bit */
9007 /* DMA Request 3 Select Registers */
9008 mcTIMER_DREQ3_16B_tag DREQ3; /* offset: 0x0116 size: 16 bit */
9009 };
9010
9011 };
9012 } mcTIMER_tag;
9013
9014
9015#define mcTIMER0 (*(volatile mcTIMER_tag *) 0xFFE18000UL)
9016#define mcTIMER1 (*(volatile mcTIMER_tag *) 0xFFE1C000UL)
9017#define mcTIMER2 (*(volatile mcTIMER_tag *) 0xFFE20000UL)
9018
9019
9020
9021/****************************************************************/
9022/* */
9023/* Module: mcPWM */
9024/* */
9025/****************************************************************/
9026
9027
9028 /* Register layout for all registers CNT... */
9029
9030 typedef union { /* Counter Register */
9031 uint16_t R;
9032 } mcPWM_CNT_16B_tag;
9033
9034
9035 /* Register layout for all registers INIT... */
9036
9037 typedef union { /* Initial Counter Register */
9038 uint16_t R;
9039 } mcPWM_INIT_16B_tag;
9040
9041
9042 /* Register layout for all registers CTRL2... */
9043
9044 typedef union { /* Control 2 Register */
9045 uint16_t R;
9046 struct {
9047 uint16_t DBGEN:1; /* Debug Enable */
9048 uint16_t WAITEN:1; /* Wait Enable */
9049 uint16_t INDEP:1; /* Independent or Complementary Pair Operation */
9050#ifndef USE_FIELD_ALIASES_mcPWM
9051 uint16_t PWM23_INIT:1; /* PWM23 Initial Value */
9052#else
9053 uint16_t PWMA_INIT:1; /* deprecated name - please avoid */
9054#endif
9055#ifndef USE_FIELD_ALIASES_mcPWM
9056 uint16_t PWM45_INIT:1; /* PWM23 Initial Value */
9057#else
9058 uint16_t PWMB_INIT:1; /* deprecated name - please avoid */
9059#endif
9060 uint16_t PWMX_INIT:1; /* PWMX Initial Value */
9061 uint16_t INIT_SEL:2; /* Initialization Control Select */
9062 uint16_t FRCEN:1; /* Force Initialization enable */
9063 uint16_t FORCE:1; /* Force Initialization */
9064 uint16_t FORCE_SEL:3; /* Force Source Select */
9065 uint16_t RELOAD_SEL:1; /* Reload Source Select */
9066 uint16_t CLK_SEL:2; /* Clock Source Select */
9067 } B;
9068 } mcPWM_CTRL2_16B_tag;
9069
9070
9071 /* Register layout for all registers CTRL1... */
9072
9073 typedef union { /* Control Register */
9074 uint16_t R;
9075 struct {
9076 uint16_t LDFQ:4; /* Load Frequency */
9077 uint16_t HALF:1; /* Half Cycle Reload */
9078 uint16_t FULL:1; /* Full Cycle Reload */
9079 uint16_t DT:2; /* Deadtime */
9080 uint16_t:1;
9081 uint16_t PRSC:3; /* Prescaler */
9082 uint16_t:1;
9083 uint16_t LDMOD:1; /* Load Mode Select */
9084 uint16_t:1;
9085#ifndef USE_FIELD_ALIASES_mcPWM
9086 uint16_t DBL_EN:1; /* Double Switching Enable */
9087#else
9088 uint16_t DBLEN:1; /* deprecated name - please avoid */
9089#endif
9090 } B;
9091 } mcPWM_CTRL1_16B_tag;
9092
9093
9094 /* Register layout for all registers VAL_0... */
9095
9096 typedef union { /* Value Register 0 */
9097 uint16_t R;
9098 } mcPWM_VAL_0_16B_tag;
9099
9100
9101 /* Register layout for all registers VAL_1... */
9102
9103 typedef union { /* Value Register 1 */
9104 uint16_t R;
9105 } mcPWM_VAL_1_16B_tag;
9106
9107
9108 /* Register layout for all registers VAL_2... */
9109
9110 typedef union { /* Value Register 2 */
9111 uint16_t R;
9112 } mcPWM_VAL_2_16B_tag;
9113
9114
9115 /* Register layout for all registers VAL_3... */
9116
9117 typedef union { /* Value Register 3 */
9118 uint16_t R;
9119 } mcPWM_VAL_3_16B_tag;
9120
9121
9122 /* Register layout for all registers VAL_4... */
9123
9124 typedef union { /* Value Register 4 */
9125 uint16_t R;
9126 } mcPWM_VAL_4_16B_tag;
9127
9128
9129 /* Register layout for all registers VAL_5... */
9130
9131 typedef union { /* Value Register 5 */
9132 uint16_t R;
9133 } mcPWM_VAL_5_16B_tag;
9134
9135 /* Register layout for all registers OCTRL... */
9136
9137 typedef union { /* Output Control Register */
9138 uint16_t R;
9139 struct {
9140 uint16_t PWMA_IN:1; /* PWMA Input */
9141 uint16_t PWMB_IN:1; /* PWMB Input */
9142 uint16_t PWMX_IN:1; /* PWMX Input */
9143 uint16_t:2;
9144 uint16_t POLA:1; /* PWMA Output Polarity */
9145 uint16_t POLB:1; /* PWMB Output Polarity */
9146 uint16_t POLX:1; /* PWMX Output Polarity */
9147 uint16_t:2;
9148 uint16_t PWMAFS:2; /* PWMA Fault State */
9149 uint16_t PWMBFS:2; /* PWMB Fault State */
9150 uint16_t PWMXFS:2; /* PWMX Fault State */
9151 } B;
9152 } mcPWM_OCTRL_16B_tag;
9153
9154
9155 /* Register layout for all registers STS... */
9156
9157 typedef union { /* Status Register */
9158 uint16_t R;
9159 struct {
9160 uint16_t:1;
9161 uint16_t RUF:1; /* Registers Updated Flag */
9162 uint16_t REF:1; /* Reload Error Flag */
9163 uint16_t RF:1; /* Reload Flag */
9164 uint16_t CFA1:1; /* Capture Flag A1 */
9165 uint16_t CFA0:1; /* Capture Flag A0 */
9166 uint16_t CFB1:1; /* Capture Flag B1 */
9167 uint16_t CFB0:1; /* Capture Flag B0 */
9168 uint16_t CFX1:1; /* Capture Flag X1 */
9169 uint16_t CFX0:1; /* Capture Flag X0 */
9170 uint16_t CMPF:6; /* Compare Flags */
9171 } B;
9172 } mcPWM_STS_16B_tag;
9173
9174
9175 /* Register layout for all registers INTEN... */
9176
9177 typedef union { /* Interrupt Enable Registers */
9178 uint16_t R;
9179 struct {
9180 uint16_t:2;
9181 uint16_t REIE:1; /* Reload Error Interrupt Enable */
9182 uint16_t RIE:1; /* Reload Interrupt Enable */
9183 uint16_t CA1IE:1; /* Capture A1 Interrupt Enable */
9184 uint16_t CA0IE:1; /* Capture A0 Interrupt Enable */
9185 uint16_t CB1IE:1; /* Capture B1 Interrupt Enable */
9186 uint16_t CB0IE:1; /* Capture B0 Interrupt Enable */
9187 uint16_t CX1IE:1; /* Capture X1 Interrupt Enable */
9188 uint16_t CX0IE:1; /* Capture X0 Interrupt Enable */
9189 uint16_t CMPIE:6; /* Compare Interrupt Enables */
9190 } B;
9191 } mcPWM_INTEN_16B_tag;
9192
9193
9194 /* Register layout for all registers DMAEN... */
9195
9196 typedef union { /* DMA Enable Registers */
9197 uint16_t R;
9198 struct {
9199 uint16_t:6;
9200 uint16_t VALDE:1; /* Value Register DMA Enable */
9201 uint16_t FAND:1; /* FIFO Watermark AND Control */
9202 uint16_t CAPTDE:2; /* Capture DMA Enable Source Select */
9203 uint16_t CA1DE:1; /* Capture A1 FIFO DMA Enable */
9204 uint16_t CA0DE:1; /* Capture A0 FIFO DMA Enable */
9205 uint16_t CB1DE:1; /* Capture B1 FIFO DMA Enable */
9206 uint16_t CB0DE:1; /* Capture B0 FIFO DMA Enable */
9207 uint16_t CX1DE:1; /* Capture X1 FIFO DMA Enable */
9208 uint16_t CX0DE:1; /* Capture X0 FIFO DMA Enable */
9209 } B;
9210 } mcPWM_DMAEN_16B_tag;
9211
9212
9213 /* Register layout for all registers TCTRL... */
9214
9215 typedef union { /* Output Trigger Control Registers */
9216 uint16_t R;
9217 struct {
9218 uint16_t:10;
9219 uint16_t OUT_TRIG_EN:6; /* Output Trigger Enables */
9220 } B;
9221 } mcPWM_TCTRL_16B_tag;
9222
9223
9224 /* Register layout for all registers DISMAP... */
9225
9226 typedef union { /* Fault Disable Mapping Registers */
9227 uint16_t R;
9228 struct {
9229 uint16_t:4;
9230 uint16_t DISX:4; /* PWMX Fault Disable Mask */
9231 uint16_t DISB:4; /* PWMB Fault Disable Mask */
9232 uint16_t DISA:4; /* PWMA Fault Disable Mask */
9233 } B;
9234 } mcPWM_DISMAP_16B_tag;
9235
9236
9237 /* Register layout for all registers DTCNT0... */
9238
9239 typedef union { /* Deadtime Count Register 0 */
9240 uint16_t R;
9241 struct {
9242 uint16_t:5;
9243 uint16_t DTCNT0:11; /* Deadtime Count Register 0 */
9244 } B;
9245 } mcPWM_DTCNT0_16B_tag;
9246
9247
9248 /* Register layout for all registers DTCNT1... */
9249
9250 typedef union { /* Deadtime Count Register 1 */
9251 uint16_t R;
9252 struct {
9253 uint16_t:5;
9254 uint16_t DTCNT1:11; /* Deadtime Count Register 1 */
9255 } B;
9256 } mcPWM_DTCNT1_16B_tag;
9257
9258 /* Register layout for all registers CAPTCTRLX... */
9259
9260 typedef union { /* Capture Control X Register */
9261 uint16_t R;
9262 struct {
9263 uint16_t CX1CNT:3; /* Capture X1 FIFO Word Count */
9264 uint16_t CX0CNT:3; /* Capture X0 FIFO Word Count */
9265 uint16_t CFXWM:2; /* Capture X FIFOs Water Mark */
9266#ifndef USE_FIELD_ALIASES_mcPWM
9267 uint16_t EDGCNTXEN:1; /* Edge Counter X Enable */
9268#else
9269 uint16_t EDGCNTX_EN:1; /* deprecated name - please avoid */
9270#endif
9271#ifndef USE_FIELD_ALIASES_mcPWM
9272 uint16_t INPSELX:1; /* Input Select X */
9273#else
9274 uint16_t INP_SELX:1; /* deprecated name - please avoid */
9275#endif
9276 uint16_t EDGX1:2; /* Edge X 1 */
9277 uint16_t EDGX0:2; /* Edge X 0 */
9278 uint16_t ONESHOTX:1; /* One Shot Mode X */
9279 uint16_t ARMX:1; /* Arm X */
9280 } B;
9281 } mcPWM_CAPTCTRLX_16B_tag;
9282
9283
9284 /* Register layout for all registers CAPTCMPX... */
9285
9286 typedef union { /* Capture Compare X Register */
9287 uint16_t R;
9288 struct {
9289 uint16_t EDGCNTX:8; /* Edge Counter X */
9290 uint16_t EDGCMPX:8; /* Edge Compare X */
9291 } B;
9292 } mcPWM_CAPTCMPX_16B_tag;
9293
9294
9295 /* Register layout for all registers CVAL0... */
9296
9297 typedef union { /* Capture Value 0 Register */
9298 uint16_t R;
9299 struct {
9300 uint16_t CAPTVAL0:16; /* Captured value from submodule counter */
9301 } B;
9302 } mcPWM_CVAL0_16B_tag;
9303
9304
9305 /* Register layout for all registers CVAL0CYC... */
9306
9307 typedef union { /* Capture Value 0 Cycle Register */
9308 uint16_t R;
9309 struct {
9310 uint16_t:12;
9311 uint16_t CVAL0CYC:4; /* Capture Value 0 Cycle */
9312 } B;
9313 } mcPWM_CVAL0CYC_16B_tag;
9314
9315
9316 /* Register layout for all registers CVAL1... */
9317
9318 typedef union { /* Capture Value 1 Register */
9319 uint16_t R;
9320 struct {
9321 uint16_t CAPTVAL1:16; /* Captured value from submodule counter */
9322 } B;
9323 } mcPWM_CVAL1_16B_tag;
9324
9325
9326 /* Register layout for all registers CVAL1CYC... */
9327
9328 typedef union { /* Capture Value 1 Cycle Register */
9329 uint16_t R;
9330 struct {
9331 uint16_t:12;
9332 uint16_t CVAL1CYC:4; /* Capture Value 1 Cycle */
9333 } B;
9334 } mcPWM_CVAL1CYC_16B_tag;
9335
9336
9337 /* Register layout for all registers CVAL3... */
9338
9339 typedef union { /* Capture Value 3 Register */
9340 uint16_t R;
9341 struct {
9342 uint16_t CAPTVAL3:16; /* Captured value from submodule counter */
9343 } B;
9344 } mcPWM_CVAL3_16B_tag;
9345
9346
9347 /* Register layout for all registers CVAL3CYC... */
9348
9349 typedef union { /* Capture Value 3 Cycle Register */
9350 uint16_t R;
9351 struct {
9352 uint16_t:12;
9353 uint16_t CVAL3CYC:4; /* Capture Value 3 Cycle */
9354 } B;
9355 } mcPWM_CVAL3CYC_16B_tag;
9356
9357
9358 /* Register layout for all registers CVAL4... */
9359
9360 typedef union { /* Capture Value 4 Register */
9361 uint16_t R;
9362 struct {
9363 uint16_t CAPTVAL4:16; /* Captured value from submodule counter */
9364 } B;
9365 } mcPWM_CVAL4_16B_tag;
9366
9367
9368 /* Register layout for all registers CVAL4CYC... */
9369
9370 typedef union { /* Capture Value 4 Cycle Register */
9371 uint16_t R;
9372 struct {
9373 uint16_t:12;
9374 uint16_t CVAL4CYC:4; /* Capture Value 4 Cycle */
9375 } B;
9376 } mcPWM_CVAL4CYC_16B_tag;
9377
9378
9379 /* Register layout for all registers CVAL5... */
9380
9381 typedef union { /* Capture Value 5 Register */
9382 uint16_t R;
9383 struct {
9384 uint16_t CAPTVAL5:16; /* Captured value from submodule counter */
9385 } B;
9386 } mcPWM_CVAL5_16B_tag;
9387
9388
9389 /* Register layout for all registers CVAL5CYC... */
9390
9391 typedef union { /* Capture Value 5 Cycle Register */
9392 uint16_t R;
9393 struct {
9394 uint16_t:12;
9395 uint16_t CVAL5CYC:4; /* Capture Value 5 Cycle */
9396 } B;
9397 } mcPWM_CVAL5CYC_16B_tag;
9398
9399 typedef union { /* Output Enable Register */
9400 uint16_t R;
9401 struct {
9402 uint16_t:4;
9403 uint16_t PWMA_EN:4; /* PWMA Output Enables */
9404 uint16_t PWMB_EN:4; /* PWMB Output Enables */
9405 uint16_t PWMX_EN:4; /* PWMX Output Enables */
9406 } B;
9407 } mcPWM_OUTEN_16B_tag;
9408
9409 typedef union { /* Mask Register */
9410 uint16_t R;
9411 struct {
9412 uint16_t:4;
9413 uint16_t MASKA:4; /* PWMA Masks */
9414 uint16_t MASKB:4; /* PWMB Masks */
9415 uint16_t MASKX:4; /* PWMX Masks */
9416 } B;
9417 } mcPWM_MASK_16B_tag;
9418
9419 typedef union { /* Software Controlled Output Register */
9420 uint16_t R;
9421 struct {
9422 uint16_t:8;
9423#ifndef USE_FIELD_ALIASES_mcPWM
9424 uint16_t OUT23_3:1; /* Software Controlled Output 23_3 */
9425#else
9426 uint16_t OUTA_3:1; /* deprecated name - please avoid */
9427#endif
9428#ifndef USE_FIELD_ALIASES_mcPWM
9429 uint16_t OUT45_3:1; /* Software Controlled Output 45_3 */
9430#else
9431 uint16_t OUTB_3:1; /* deprecated name - please avoid */
9432#endif
9433#ifndef USE_FIELD_ALIASES_mcPWM
9434 uint16_t OUT23_2:1; /* Software Controlled Output 23_2 */
9435#else
9436 uint16_t OUTA_2:1; /* deprecated name - please avoid */
9437#endif
9438#ifndef USE_FIELD_ALIASES_mcPWM
9439 uint16_t OUT45_2:1; /* Software Controlled Output 45_2 */
9440#else
9441 uint16_t OUTB_2:1; /* deprecated name - please avoid */
9442#endif
9443#ifndef USE_FIELD_ALIASES_mcPWM
9444 uint16_t OUT23_1:1; /* Software Controlled Output 23_1 */
9445#else
9446 uint16_t OUTA_1:1; /* deprecated name - please avoid */
9447#endif
9448#ifndef USE_FIELD_ALIASES_mcPWM
9449 uint16_t OUT45_1:1; /* Software Controlled Output 45_1 */
9450#else
9451 uint16_t OUTB_1:1; /* deprecated name - please avoid */
9452#endif
9453#ifndef USE_FIELD_ALIASES_mcPWM
9454 uint16_t OUT23_0:1; /* Software Controlled Output 23_0 */
9455#else
9456 uint16_t OUTA_0:1; /* deprecated name - please avoid */
9457#endif
9458#ifndef USE_FIELD_ALIASES_mcPWM
9459 uint16_t OUT45_0:1; /* Software Controlled Output 45_0 */
9460#else
9461 uint16_t OUTB_0:1; /* deprecated name - please avoid */
9462#endif
9463 } B;
9464 } mcPWM_SWCOUT_16B_tag;
9465
9466 typedef union { /* Deadtime Source Select Register */
9467 uint16_t R;
9468 struct {
9469#ifndef USE_FIELD_ALIASES_mcPWM
9470 uint16_t SEL23_3:2; /* PWM23_3 Control Select */
9471#else
9472 uint16_t SELA_3:2; /* deprecated name - please avoid */
9473#endif
9474#ifndef USE_FIELD_ALIASES_mcPWM
9475 uint16_t SEL45_3:2; /* PWM45_3 Control Select */
9476#else
9477 uint16_t SELB_3:2; /* deprecated name - please avoid */
9478#endif
9479#ifndef USE_FIELD_ALIASES_mcPWM
9480 uint16_t SEL23_2:2; /* PWM23_2 Control Select */
9481#else
9482 uint16_t SELA_2:2; /* deprecated name - please avoid */
9483#endif
9484#ifndef USE_FIELD_ALIASES_mcPWM
9485 uint16_t SEL45_2:2; /* PWM45_2 Control Select */
9486#else
9487 uint16_t SELB_2:2; /* deprecated name - please avoid */
9488#endif
9489#ifndef USE_FIELD_ALIASES_mcPWM
9490 uint16_t SEL23_1:2; /* PWM23_1 Control Select */
9491#else
9492 uint16_t SELA_1:2; /* deprecated name - please avoid */
9493#endif
9494#ifndef USE_FIELD_ALIASES_mcPWM
9495 uint16_t SEL45_1:2; /* PWM45_1 Control Select */
9496#else
9497 uint16_t SELB_1:2; /* deprecated name - please avoid */
9498#endif
9499#ifndef USE_FIELD_ALIASES_mcPWM
9500 uint16_t SEL23_0:2; /* PWM23_0 Control Select */
9501#else
9502 uint16_t SELA_0:2; /* deprecated name - please avoid */
9503#endif
9504#ifndef USE_FIELD_ALIASES_mcPWM
9505 uint16_t SEL45_0:2; /* PWM45_0 Control Select */
9506#else
9507 uint16_t SELB_0:2; /* deprecated name - please avoid */
9508#endif
9509 } B;
9510 } mcPWM_DTSRCSEL_16B_tag;
9511
9512 typedef union { /* Master Control Register */
9513 uint16_t R;
9514 struct {
9515 uint16_t IPOL:4; /* Current Polarity */
9516 uint16_t RUN:4; /* Run */
9517#ifndef USE_FIELD_ALIASES_mcPWM
9518 uint16_t CLOK:4; /* Clear Load Okay */
9519#else
9520 uint16_t CLDOK:4; /* deprecated name - please avoid */
9521#endif
9522 uint16_t LDOK:4; /* Load Okay */
9523 } B;
9524 } mcPWM_MCTRL_16B_tag;
9525
9526 typedef union { /* Fault Control Register */
9527 uint16_t R;
9528 struct {
9529 uint16_t FLVL:4; /* Fault Level */
9530 uint16_t FAUTO:4; /* Automatic Fault Clearing */
9531 uint16_t FSAFE:4; /* Fault Safety Mode */
9532 uint16_t FIE:4; /* Fault Interrupt Enables */
9533 } B;
9534 } mcPWM_FCTRL_16B_tag;
9535
9536 typedef union { /* Fault Status Register */
9537 uint16_t R;
9538 struct {
9539 uint16_t:3;
9540 uint16_t FTEST:1; /* Fault Test */
9541 uint16_t FFPIN:4; /* Filtered Fault Pins */
9542 uint16_t:4;
9543 uint16_t FFLAG:4; /* Fault Flags */
9544 } B;
9545 } mcPWM_FSTS_16B_tag;
9546
9547 typedef union { /* Fault Filter Register */
9548 uint16_t R;
9549 struct {
9550 uint16_t:5;
9551 uint16_t FILT_CNT:3; /* Fault Filter Count */
9552 uint16_t FILT_PER:8; /* Fault Filter Period */
9553 } B;
9554 } mcPWM_FFILT_16B_tag;
9555
9556
9557 /* Register layout for generated register(s) VAL... */
9558
9559 typedef union { /* */
9560 uint16_t R;
9561 } mcPWM_VAL_16B_tag;
9562
9563
9564 typedef struct mcPWM_SUBMOD_struct_tag {
9565
9566 /* Counter Register */
9567 mcPWM_CNT_16B_tag CNT; /* relative offset: 0x0000 */
9568 /* Initial Counter Register */
9569 mcPWM_INIT_16B_tag INIT; /* relative offset: 0x0002 */
9570 /* Control 2 Register */
9571 mcPWM_CTRL2_16B_tag CTRL2; /* relative offset: 0x0004 */
9572 union {
9573 /* Control Register */
9574 mcPWM_CTRL1_16B_tag CTRL1; /* relative offset: 0x0006 */
9575 mcPWM_CTRL1_16B_tag CTRL; /* deprecated - please avoid */
9576 };
9577 /* Value Register 0 */
9578
9579 union {
9580
9581 struct {
9582
9583 mcPWM_VAL_0_16B_tag VAL_0; /* relative offset: 0x0008 */
9584 /* Value Register 1 */
9585 mcPWM_VAL_1_16B_tag VAL_1; /* relative offset: 0x000A */
9586 /* Value Register 2 */
9587 mcPWM_VAL_2_16B_tag VAL_2; /* relative offset: 0x000C */
9588 /* Value Register 3 */
9589 mcPWM_VAL_3_16B_tag VAL_3; /* relative offset: 0x000E */
9590 /* Value Register 4 */
9591 mcPWM_VAL_4_16B_tag VAL_4; /* relative offset: 0x0010 */
9592 /* Value Register 5 */
9593 mcPWM_VAL_5_16B_tag VAL_5; /* relative offset: 0x0012 */
9594
9595 };
9596
9597 mcPWM_VAL_0_16B_tag VAL[6]; /* offset: 0x0008 size: 16 bit */
9598
9599 };
9600 int8_t mcPWM_reserved_0014[4];
9601 /* Output Control Register */
9602 mcPWM_OCTRL_16B_tag OCTRL; /* relative offset: 0x0018 */
9603 /* Status Register */
9604 mcPWM_STS_16B_tag STS; /* relative offset: 0x001A */
9605 /* Interrupt Enable Registers */
9606 mcPWM_INTEN_16B_tag INTEN; /* relative offset: 0x001C */
9607 /* DMA Enable Registers */
9608 mcPWM_DMAEN_16B_tag DMAEN; /* relative offset: 0x001E */
9609 /* Output Trigger Control Registers */
9610 mcPWM_TCTRL_16B_tag TCTRL; /* relative offset: 0x0020 */
9611 /* Fault Disable Mapping Registers */
9612 mcPWM_DISMAP_16B_tag DISMAP; /* relative offset: 0x0022 */
9613 /* Deadtime Count Register 0 */
9614 mcPWM_DTCNT0_16B_tag DTCNT0; /* relative offset: 0x0024 */
9615 /* Deadtime Count Register 1 */
9616 mcPWM_DTCNT1_16B_tag DTCNT1; /* relative offset: 0x0026 */
9617 /* Capture Control A Register */
9618 int8_t mcPWM_reserved_0028[8];
9619 /* Capture Control X Register */
9620 mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX; /* relative offset: 0x0030 */
9621 union {
9622 /* Capture Compare X Register */
9623 mcPWM_CAPTCMPX_16B_tag CAPTCMPX; /* relative offset: 0x0032 */
9624 mcPWM_CAPTCMPX_16B_tag CAPTCOMPX; /* deprecated - please avoid */
9625 };
9626 /* Capture Value 0 Register */
9627 mcPWM_CVAL0_16B_tag CVAL0; /* relative offset: 0x0034 */
9628 union {
9629 /* Capture Value 0 Cycle Register */
9630 mcPWM_CVAL0CYC_16B_tag CVAL0CYC; /* relative offset: 0x0036 */
9631 mcPWM_CVAL0CYC_16B_tag CVAL0C; /* deprecated - please avoid */
9632 };
9633 /* Capture Value 1 Register */
9634 mcPWM_CVAL1_16B_tag CVAL1; /* relative offset: 0x0038 */
9635 union {
9636 /* Capture Value 1 Cycle Register */
9637 mcPWM_CVAL1CYC_16B_tag CVAL1CYC; /* relative offset: 0x003A */
9638 mcPWM_CVAL1CYC_16B_tag CVAL1C; /* deprecated - please avoid */
9639 };
9640 /* Capture Value 2 Register */
9641 int8_t mcPWM_SUBMOD_reserved_003C[16];
9642 int8_t mcPWM_SUBMOD_reserved_004C[4];
9643
9644 } mcPWM_SUBMOD_tag;
9645
9646
9647 typedef struct mcPWM_struct_tag { /* start of mcPWM_tag */
9648 union {
9649 /* Register set SUBMOD */
9650 mcPWM_SUBMOD_tag SUBMOD[4]; /* offset: 0x0000 (0x0050 x 4) */
9651
9652 mcPWM_SUBMOD_tag SUB[4]; /* offset: 0x0000 (0x0050 x 4) */
9653
9654 struct {
9655 /* Counter Register */
9656 mcPWM_CNT_16B_tag CNT0; /* offset: 0x0000 size: 16 bit */
9657 /* Initial Counter Register */
9658 mcPWM_INIT_16B_tag INIT0; /* offset: 0x0002 size: 16 bit */
9659 /* Control 2 Register */
9660 mcPWM_CTRL2_16B_tag CTRL20; /* offset: 0x0004 size: 16 bit */
9661 /* Control Register */
9662 mcPWM_CTRL1_16B_tag CTRL10; /* offset: 0x0006 size: 16 bit */
9663 /* Value Register 0 */
9664 mcPWM_VAL_0_16B_tag VAL_00; /* offset: 0x0008 size: 16 bit */
9665 /* Value Register 1 */
9666 mcPWM_VAL_1_16B_tag VAL_10; /* offset: 0x000A size: 16 bit */
9667 /* Value Register 2 */
9668 mcPWM_VAL_2_16B_tag VAL_20; /* offset: 0x000C size: 16 bit */
9669 /* Value Register 3 */
9670 mcPWM_VAL_3_16B_tag VAL_30; /* offset: 0x000E size: 16 bit */
9671 /* Value Register 4 */
9672 mcPWM_VAL_4_16B_tag VAL_40; /* offset: 0x0010 size: 16 bit */
9673 /* Value Register 5 */
9674 mcPWM_VAL_5_16B_tag VAL_50; /* offset: 0x0012 size: 16 bit */
9675 int8_t mcPWM_reserved_0014[4];
9676 /* Output Control Register */
9677 mcPWM_OCTRL_16B_tag OCTRL0; /* offset: 0x0018 size: 16 bit */
9678 /* Status Register */
9679 mcPWM_STS_16B_tag STS0; /* offset: 0x001A size: 16 bit */
9680 /* Interrupt Enable Registers */
9681 mcPWM_INTEN_16B_tag INTEN0; /* offset: 0x001C size: 16 bit */
9682 /* DMA Enable Registers */
9683 mcPWM_DMAEN_16B_tag DMAEN0; /* offset: 0x001E size: 16 bit */
9684 /* Output Trigger Control Registers */
9685 mcPWM_TCTRL_16B_tag TCTRL0; /* offset: 0x0020 size: 16 bit */
9686 /* Fault Disable Mapping Registers */
9687 mcPWM_DISMAP_16B_tag DISMAP0; /* offset: 0x0022 size: 16 bit */
9688 /* Deadtime Count Register 0 */
9689 mcPWM_DTCNT0_16B_tag DTCNT00; /* offset: 0x0024 size: 16 bit */
9690 /* Deadtime Count Register 1 */
9691 mcPWM_DTCNT1_16B_tag DTCNT10; /* offset: 0x0026 size: 16 bit */
9692 int8_t mcPWM_reserved_0028[8];
9693 /* Capture Control X Register */
9694 mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX0; /* offset: 0x0030 size: 16 bit */
9695 /* Capture Compare X Register */
9696 mcPWM_CAPTCMPX_16B_tag CAPTCMPX0; /* offset: 0x0032 size: 16 bit */
9697 /* Capture Value 0 Register */
9698 mcPWM_CVAL0_16B_tag CVAL00; /* offset: 0x0034 size: 16 bit */
9699 /* Capture Value 0 Cycle Register */
9700 mcPWM_CVAL0CYC_16B_tag CVAL0CYC0; /* offset: 0x0036 size: 16 bit */
9701 /* Capture Value 1 Register */
9702 mcPWM_CVAL1_16B_tag CVAL10; /* offset: 0x0038 size: 16 bit */
9703 /* Capture Value 1 Cycle Register */
9704 mcPWM_CVAL1CYC_16B_tag CVAL1CYC0; /* offset: 0x003A size: 16 bit */
9705 int8_t mcPWM_reserved_003c[16];
9706 int8_t mcPWM_reserved_004C_I2[4];
9707 /* Counter Register */
9708 mcPWM_CNT_16B_tag CNT1; /* offset: 0x0050 size: 16 bit */
9709 /* Initial Counter Register */
9710 mcPWM_INIT_16B_tag INIT1; /* offset: 0x0052 size: 16 bit */
9711 /* Control 2 Register */
9712 mcPWM_CTRL2_16B_tag CTRL21; /* offset: 0x0054 size: 16 bit */
9713 /* Control Register */
9714 mcPWM_CTRL1_16B_tag CTRL11; /* offset: 0x0056 size: 16 bit */
9715 /* Value Register 0 */
9716 mcPWM_VAL_0_16B_tag VAL_01; /* offset: 0x0058 size: 16 bit */
9717 /* Value Register 1 */
9718 mcPWM_VAL_1_16B_tag VAL_11; /* offset: 0x005A size: 16 bit */
9719 /* Value Register 2 */
9720 mcPWM_VAL_2_16B_tag VAL_21; /* offset: 0x005C size: 16 bit */
9721 /* Value Register 3 */
9722 mcPWM_VAL_3_16B_tag VAL_31; /* offset: 0x005E size: 16 bit */
9723 /* Value Register 4 */
9724 mcPWM_VAL_4_16B_tag VAL_41; /* offset: 0x0060 size: 16 bit */
9725 /* Value Register 5 */
9726 mcPWM_VAL_5_16B_tag VAL_51; /* offset: 0x0062 size: 16 bit */
9727 int8_t mcPWM_reserved_0064[4];
9728 /* Output Control Register */
9729 mcPWM_OCTRL_16B_tag OCTRL1; /* offset: 0x0068 size: 16 bit */
9730 /* Status Register */
9731 mcPWM_STS_16B_tag STS1; /* offset: 0x006A size: 16 bit */
9732 /* Interrupt Enable Registers */
9733 mcPWM_INTEN_16B_tag INTEN1; /* offset: 0x006C size: 16 bit */
9734 /* DMA Enable Registers */
9735 mcPWM_DMAEN_16B_tag DMAEN1; /* offset: 0x006E size: 16 bit */
9736 /* Output Trigger Control Registers */
9737 mcPWM_TCTRL_16B_tag TCTRL1; /* offset: 0x0070 size: 16 bit */
9738 /* Fault Disable Mapping Registers */
9739 mcPWM_DISMAP_16B_tag DISMAP1; /* offset: 0x0072 size: 16 bit */
9740 /* Deadtime Count Register 0 */
9741 mcPWM_DTCNT0_16B_tag DTCNT01; /* offset: 0x0074 size: 16 bit */
9742 /* Deadtime Count Register 1 */
9743 mcPWM_DTCNT1_16B_tag DTCNT11; /* offset: 0x0076 size: 16 bit */
9744 /* Capture Control A Register */
9745 int8_t mcPWM_reserved_0078[8];
9746 /* Capture Control X Register */
9747 mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX1; /* offset: 0x0080 size: 16 bit */
9748 /* Capture Compare X Register */
9749 mcPWM_CAPTCMPX_16B_tag CAPTCMPX1; /* offset: 0x0082 size: 16 bit */
9750 /* Capture Value 0 Register */
9751 mcPWM_CVAL0_16B_tag CVAL01; /* offset: 0x0084 size: 16 bit */
9752 /* Capture Value 0 Cycle Register */
9753 mcPWM_CVAL0CYC_16B_tag CVAL0CYC1; /* offset: 0x0086 size: 16 bit */
9754 /* Capture Value 1 Register */
9755 mcPWM_CVAL1_16B_tag CVAL11; /* offset: 0x0088 size: 16 bit */
9756 /* Capture Value 1 Cycle Register */
9757 mcPWM_CVAL1CYC_16B_tag CVAL1CYC1; /* offset: 0x008A size: 16 bit */
9758 int8_t mcPWM_reserved_008c[16];
9759 int8_t mcPWM_reserved_009C_I2[4];
9760 /* Counter Register */
9761 mcPWM_CNT_16B_tag CNT2; /* offset: 0x00A0 size: 16 bit */
9762 /* Initial Counter Register */
9763 mcPWM_INIT_16B_tag INIT2; /* offset: 0x00A2 size: 16 bit */
9764 /* Control 2 Register */
9765 mcPWM_CTRL2_16B_tag CTRL22; /* offset: 0x00A4 size: 16 bit */
9766 /* Control Register */
9767 mcPWM_CTRL1_16B_tag CTRL12; /* offset: 0x00A6 size: 16 bit */
9768 /* Value Register 0 */
9769 mcPWM_VAL_0_16B_tag VAL_02; /* offset: 0x00A8 size: 16 bit */
9770 /* Value Register 1 */
9771 mcPWM_VAL_1_16B_tag VAL_12; /* offset: 0x00AA size: 16 bit */
9772 /* Value Register 2 */
9773 mcPWM_VAL_2_16B_tag VAL_22; /* offset: 0x00AC size: 16 bit */
9774 /* Value Register 3 */
9775 mcPWM_VAL_3_16B_tag VAL_32; /* offset: 0x00AE size: 16 bit */
9776 /* Value Register 4 */
9777 mcPWM_VAL_4_16B_tag VAL_42; /* offset: 0x00B0 size: 16 bit */
9778 /* Value Register 5 */
9779 mcPWM_VAL_5_16B_tag VAL_52; /* offset: 0x00B2 size: 16 bit */
9780 int8_t mcPWM_reserved_00b4[4];
9781 /* Output Control Register */
9782 mcPWM_OCTRL_16B_tag OCTRL2; /* offset: 0x00B8 size: 16 bit */
9783 /* Status Register */
9784 mcPWM_STS_16B_tag STS2; /* offset: 0x00BA size: 16 bit */
9785 /* Interrupt Enable Registers */
9786 mcPWM_INTEN_16B_tag INTEN2; /* offset: 0x00BC size: 16 bit */
9787 /* DMA Enable Registers */
9788 mcPWM_DMAEN_16B_tag DMAEN2; /* offset: 0x00BE size: 16 bit */
9789 /* Output Trigger Control Registers */
9790 mcPWM_TCTRL_16B_tag TCTRL2; /* offset: 0x00C0 size: 16 bit */
9791 /* Fault Disable Mapping Registers */
9792 mcPWM_DISMAP_16B_tag DISMAP2; /* offset: 0x00C2 size: 16 bit */
9793 /* Deadtime Count Register 0 */
9794 mcPWM_DTCNT0_16B_tag DTCNT02; /* offset: 0x00C4 size: 16 bit */
9795 /* Deadtime Count Register 1 */
9796 mcPWM_DTCNT1_16B_tag DTCNT12; /* offset: 0x00C6 size: 16 bit */
9797 /* Capture Control A Register */
9798 int8_t mcPWM_reserved_00c8[8];
9799 /* Capture Control X Register */
9800 mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX2; /* offset: 0x00D0 size: 16 bit */
9801 /* Capture Compare X Register */
9802 mcPWM_CAPTCMPX_16B_tag CAPTCMPX2; /* offset: 0x00D2 size: 16 bit */
9803 /* Capture Value 0 Register */
9804 mcPWM_CVAL0_16B_tag CVAL02; /* offset: 0x00D4 size: 16 bit */
9805 /* Capture Value 0 Cycle Register */
9806 mcPWM_CVAL0CYC_16B_tag CVAL0CYC2; /* offset: 0x00D6 size: 16 bit */
9807 /* Capture Value 1 Register */
9808 mcPWM_CVAL1_16B_tag CVAL12; /* offset: 0x00D8 size: 16 bit */
9809 /* Capture Value 1 Cycle Register */
9810 mcPWM_CVAL1CYC_16B_tag CVAL1CYC2; /* offset: 0x00DA size: 16 bit */
9811 int8_t mcPWM_reserved_00dc[16];
9812 int8_t mcPWM_reserved_00EC_I2[4];
9813 /* Counter Register */
9814 mcPWM_CNT_16B_tag CNT3; /* offset: 0x00F0 size: 16 bit */
9815 /* Initial Counter Register */
9816 mcPWM_INIT_16B_tag INIT3; /* offset: 0x00F2 size: 16 bit */
9817 /* Control 2 Register */
9818 mcPWM_CTRL2_16B_tag CTRL23; /* offset: 0x00F4 size: 16 bit */
9819 /* Control Register */
9820 mcPWM_CTRL1_16B_tag CTRL13; /* offset: 0x00F6 size: 16 bit */
9821 /* Value Register 0 */
9822 mcPWM_VAL_0_16B_tag VAL_03; /* offset: 0x00F8 size: 16 bit */
9823 /* Value Register 1 */
9824 mcPWM_VAL_1_16B_tag VAL_13; /* offset: 0x00FA size: 16 bit */
9825 /* Value Register 2 */
9826 mcPWM_VAL_2_16B_tag VAL_23; /* offset: 0x00FC size: 16 bit */
9827 /* Value Register 3 */
9828 mcPWM_VAL_3_16B_tag VAL_33; /* offset: 0x00FE size: 16 bit */
9829 /* Value Register 4 */
9830 mcPWM_VAL_4_16B_tag VAL_43; /* offset: 0x0100 size: 16 bit */
9831 /* Value Register 5 */
9832 mcPWM_VAL_5_16B_tag VAL_53; /* offset: 0x0102 size: 16 bit */
9833 int8_t mcPWM_reserved_00104[4];
9834 /* Output Control Register */
9835 mcPWM_OCTRL_16B_tag OCTRL3; /* offset: 0x0108 size: 16 bit */
9836 /* Status Register */
9837 mcPWM_STS_16B_tag STS3; /* offset: 0x010A size: 16 bit */
9838 /* Interrupt Enable Registers */
9839 mcPWM_INTEN_16B_tag INTEN3; /* offset: 0x010C size: 16 bit */
9840 /* DMA Enable Registers */
9841 mcPWM_DMAEN_16B_tag DMAEN3; /* offset: 0x010E size: 16 bit */
9842 /* Output Trigger Control Registers */
9843 mcPWM_TCTRL_16B_tag TCTRL3; /* offset: 0x0110 size: 16 bit */
9844 /* Fault Disable Mapping Registers */
9845 mcPWM_DISMAP_16B_tag DISMAP3; /* offset: 0x0112 size: 16 bit */
9846 /* Deadtime Count Register 0 */
9847 mcPWM_DTCNT0_16B_tag DTCNT03; /* offset: 0x0114 size: 16 bit */
9848 /* Deadtime Count Register 1 */
9849 mcPWM_DTCNT1_16B_tag DTCNT13; /* offset: 0x0116 size: 16 bit */
9850 /* Capture Control A Register */
9851 int8_t mcPWM_reserved_00118[8];
9852 /* Capture Control X Register */
9853 mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX3; /* offset: 0x0120 size: 16 bit */
9854 /* Capture Compare X Register */
9855 mcPWM_CAPTCMPX_16B_tag CAPTCMPX3; /* offset: 0x0122 size: 16 bit */
9856 /* Capture Value 0 Register */
9857 mcPWM_CVAL0_16B_tag CVAL03; /* offset: 0x0124 size: 16 bit */
9858 /* Capture Value 0 Cycle Register */
9859 mcPWM_CVAL0CYC_16B_tag CVAL0CYC3; /* offset: 0x0126 size: 16 bit */
9860 /* Capture Value 1 Register */
9861 mcPWM_CVAL1_16B_tag CVAL13; /* offset: 0x0128 size: 16 bit */
9862 /* Capture Value 1 Cycle Register */
9863 mcPWM_CVAL1CYC_16B_tag CVAL1CYC3; /* offset: 0x012A size: 16 bit */
9864 int8_t mcPWM_reserved_0012c[16];
9865 int8_t mcPWM_reserved_013C_E2[4];
9866 };
9867
9868 };
9869 /* Output Enable Register */
9870 mcPWM_OUTEN_16B_tag OUTEN; /* offset: 0x0140 size: 16 bit */
9871 /* Mask Register */
9872 mcPWM_MASK_16B_tag MASK; /* offset: 0x0142 size: 16 bit */
9873 /* Software Controlled Output Register */
9874 mcPWM_SWCOUT_16B_tag SWCOUT; /* offset: 0x0144 size: 16 bit */
9875 /* Deadtime Source Select Register */
9876 mcPWM_DTSRCSEL_16B_tag DTSRCSEL; /* offset: 0x0146 size: 16 bit */
9877 /* Master Control Register */
9878 mcPWM_MCTRL_16B_tag MCTRL; /* offset: 0x0148 size: 16 bit */
9879 int8_t mcPWM_reserved_014A[2];
9880 /* Fault Control Register */
9881 mcPWM_FCTRL_16B_tag FCTRL; /* offset: 0x014C size: 16 bit */
9882 /* Fault Status Register */
9883 mcPWM_FSTS_16B_tag FSTS; /* offset: 0x014E size: 16 bit */
9884 /* Fault Filter Register */
9885 mcPWM_FFILT_16B_tag FFILT; /* offset: 0x0150 size: 16 bit */
9886 } mcPWM_tag;
9887
9888
9889#define mcPWM_A (*(volatile mcPWM_tag *) 0xFFE24000UL)
9890#define mcPWM_B (*(volatile mcPWM_tag *) 0xFFE28000UL)
9891
9892
9893
9894/****************************************************************/
9895/* */
9896/* Module: LINFLEX */
9897/* */
9898/****************************************************************/
9899
9900 typedef union { /* LIN Control Register */
9901 uint32_t R;
9902 struct {
9903 uint32_t:16;
9904 uint32_t CCD:1; /* Checksum Calculation Disable */
9905 uint32_t CFD:1; /* Checksum Field Disable */
9906 uint32_t LASE:1; /* LIN Auto Synchronization Enable */
9907#ifndef USE_FIELD_ALIASES_LINFLEX
9908 uint32_t AUTOWU:1; /* Auto Wake Up */
9909#else
9910 uint32_t AWUM:1; /* deprecated name - please avoid */
9911#endif
9912 uint32_t MBL:4; /* Master Break Length */
9913 uint32_t BF:1; /* By-Pass Filter */
9914#ifndef USE_FIELD_ALIASES_LINFLEX
9915 uint32_t SLFM:1; /* Selftest Mode */
9916#else
9917 uint32_t SFTM:1; /* deprecated name - please avoid */
9918#endif
9919 uint32_t LBKM:1; /* Loopback Mode */
9920 uint32_t MME:1; /* Master Mode Enable */
9921#ifndef USE_FIELD_ALIASES_LINFLEX
9922 uint32_t SSBL:1; /* Slave Mode Synch Break Length */
9923#else
9924 uint32_t SSDT:1; /* deprecated name - please avoid */
9925#endif
9926 uint32_t RBLM:1; /* Receiver Buffer Locked Mode */
9927 uint32_t SLEEP:1; /* Sleep Mode Request */
9928 uint32_t INIT:1; /* Initialization Mode Request */
9929 } B;
9930 } LINFLEX_LINCR1_32B_tag;
9931
9932 typedef union { /* LIN Interrupt Enable Register */
9933 uint32_t R;
9934 struct {
9935 uint32_t:16;
9936 uint32_t SZIE:1; /* Stuck at Zero Interrupt Enable */
9937 uint32_t OCIE:1; /* Output Compare Interrupt Enable */
9938 uint32_t BEIE:1; /* Bit Error Interrupt Enable */
9939 uint32_t CEIE:1; /* Checksum Error Interrupt Enable */
9940 uint32_t HEIE:1; /* Header Error Interrupt Enable */
9941 uint32_t:2;
9942 uint32_t FEIE:1; /* Frame Error Interrupt Enable */
9943 uint32_t BOIE:1; /* Buffer Overrun Error Interrupt Enable */
9944 uint32_t LSIE:1; /* LIN State Interrupt Enable */
9945 uint32_t WUIE:1; /* Wakeup Interrupt Enable */
9946 uint32_t DBFIE:1; /* Data Buffer Full Interrupt Enable */
9947#ifndef USE_FIELD_ALIASES_LINFLEX
9948 uint32_t DBEIE_TOIE:1; /* Data Buffer Empty Interrupt Enable */
9949#else
9950 uint32_t DBEIE:1; /* deprecated name - please avoid */
9951#endif
9952 uint32_t DRIE:1; /* Data Reception complete Interrupt Enable */
9953 uint32_t DTIE:1; /* Data Transmitted Interrupt Enable */
9954 uint32_t HRIE:1; /* Header Received Interrupt Enable */
9955 } B;
9956 } LINFLEX_LINIER_32B_tag;
9957
9958 typedef union { /* LIN Status Register */
9959 uint32_t R;
9960 struct {
9961 uint32_t:16;
9962 uint32_t LINS:4; /* LIN State */
9963 uint32_t:2;
9964 uint32_t RMB:1; /* Release Message Buffer */
9965 uint32_t:1;
9966#ifndef USE_FIELD_ALIASES_LINFLEX
9967 uint32_t RXBUSY:1; /* Receiver Busy Flag */
9968#else
9969 uint32_t RBSY:1; /* deprecated name - please avoid */
9970#endif
9971#ifndef USE_FIELD_ALIASES_LINFLEX
9972 uint32_t RDI:1; /* LIN Receive Signal */
9973#else
9974 uint32_t RPS:1; /* deprecated name - please avoid */
9975#endif
9976 uint32_t WUF:1; /* Wake Up Flag */
9977 uint32_t DBFF:1; /* Data Buffer Full Flag */
9978 uint32_t DBEF:1; /* Data Buffer Empty Flag */
9979 uint32_t DRF:1; /* Data Reception Completed Flag */
9980 uint32_t DTF:1; /* Data Transmission Completed Flag */
9981 uint32_t HRF:1; /* Header Received Flag */
9982 } B;
9983 } LINFLEX_LINSR_32B_tag;
9984
9985 typedef union { /* LIN Error Status Register */
9986 uint32_t R;
9987 struct {
9988 uint32_t:16;
9989 uint32_t SZF:1; /* Stuck at Zero Flag */
9990 uint32_t OCF:1; /* Output Compare Flag */
9991 uint32_t BEF:1; /* Bit Error Flag */
9992 uint32_t CEF:1; /* Checksum Error Flag */
9993 uint32_t SFEF:1; /* Sync Field Error Flag */
9994#ifndef USE_FIELD_ALIASES_LINFLEX
9995 uint32_t SDEF:1; /* Sync Delimiter Error Flag */
9996#else
9997 uint32_t BDEF:1; /* deprecated name - please avoid */
9998#endif
9999 uint32_t IDPEF:1; /* ID Parity Error Flag */
10000 uint32_t FEF:1; /* Framing Error Flag */
10001 uint32_t BOF:1; /* Buffer Overrun Flag */
10002 uint32_t:6;
10003 uint32_t NF:1; /* Noise Flag */
10004 } B;
10005 } LINFLEX_LINESR_32B_tag;
10006
10007 typedef union { /* UART Mode Control Register */
10008 uint32_t R;
10009 struct {
10010 uint32_t:16;
10011 uint32_t TDFL_TFC:3; /* Transmitter Data Field Length/TX FIFO Counter */
10012 uint32_t RDFL_RFC0:3; /* Reception Data Field Length/RX FIFO Counter */
10013 uint32_t RFBM:1; /* RX FIFO/ Buffer Mode */
10014 uint32_t TFBM:1; /* TX FIFO/ Buffer Mode */
10015 uint32_t WL1:1; /* Word Length in UART mode - bit 1 */
10016 uint32_t PC1:1; /* Parity Check - bit 1 */
10017 uint32_t RXEN:1; /* Receiver Enable */
10018 uint32_t TXEN:1; /* Transmitter Enable */
10019#ifndef USE_FIELD_ALIASES_LINFLEX
10020 uint32_t PC0:1; /* Parity Check - bit 0 */
10021#else
10022 uint32_t OP:1; /* deprecated name - please avoid */
10023#endif
10024 uint32_t PCE:1; /* Parity Control Enable */
10025#ifndef USE_FIELD_ALIASES_LINFLEX
10026 uint32_t WL0:1; /* Word Length in UART Mode - bit 0 */
10027#else
10028 uint32_t WL:1; /* deprecated name - please avoid */
10029#endif
10030 uint32_t UART:1; /* UART Mode */
10031 } B;
10032 } LINFLEX_UARTCR_32B_tag;
10033
10034 typedef union { /* UART Mode Status Register */
10035 uint32_t R;
10036 struct {
10037 uint32_t:16;
10038 uint32_t SZF:1; /* Stuck at Zero Flag */
10039 uint32_t OCF:1; /* Output Compare Flag */
10040 uint32_t PE:4; /* Parity Error Flag */
10041 uint32_t RMB:1; /* Release Message Buffer */
10042 uint32_t FEF:1; /* Framing Error Flag */
10043 uint32_t BOF:1; /* Buffer Overrun Flag */
10044 uint32_t RDI:1; /* Receiver Data Input Signal */
10045 uint32_t WUF:1; /* Wakeup Flag */
10046 uint32_t:1;
10047 uint32_t TO:1; /* Time Out */
10048#ifndef USE_FIELD_ALIASES_LINFLEX
10049 uint32_t DRF_RFE:1; /* Data Reception Completed Flag/RX FIFO Empty Flag */
10050#else
10051 uint32_t DRF:1; /* deprecated name - please avoid */
10052#endif
10053#ifndef USE_FIELD_ALIASES_LINFLEX
10054 uint32_t DTF_TFF:1; /* Data Transmission Completed Flag/TX FIFO Full Flag */
10055#else
10056 uint32_t DTF:1; /* deprecated name - please avoid */
10057#endif
10058 uint32_t NF:1; /* Noise Flag */
10059 } B;
10060 } LINFLEX_UARTSR_32B_tag;
10061
10062 typedef union { /* LIN Time-Out Control Status Register */
10063 uint32_t R;
10064 struct {
10065 uint32_t:21;
10066#ifndef USE_FIELD_ALIASES_LINFLEX
10067 uint32_t MODE:1; /* Time-out Counter Mode */
10068#else
10069 uint32_t LTOM:1; /* deprecated name - please avoid */
10070#endif
10071 uint32_t IOT:1; /* Idle on Timeout */
10072 uint32_t TOCE:1; /* Time-Out Counter Enable */
10073 uint32_t CNT:8; /* Counter Value */
10074 } B;
10075 } LINFLEX_LINTCSR_32B_tag;
10076
10077 typedef union { /* LIN Output Compare Register */
10078 uint32_t R;
10079 struct {
10080 uint32_t:16;
10081 uint32_t OC2:8; /* Output Compare Value 2 */
10082 uint32_t OC1:8; /* Output Compare Value 1 */
10083 } B;
10084 } LINFLEX_LINOCR_32B_tag;
10085
10086 typedef union { /* LIN Time-Out Control Register */
10087 uint32_t R;
10088 struct {
10089 uint32_t:20;
10090 uint32_t RTO:4; /* Response Time-Out Value */
10091 uint32_t:1;
10092 uint32_t HTO:7; /* Header Time-Out Value */
10093 } B;
10094 } LINFLEX_LINTOCR_32B_tag;
10095
10096 typedef union { /* LIN Fractional Baud Rate Register */
10097 uint32_t R;
10098 struct {
10099 uint32_t:28;
10100#ifndef USE_FIELD_ALIASES_LINFLEX
10101 uint32_t FBR:4; /* Fractional Baud Rates */
10102#else
10103 uint32_t DIV_F:4; /* deprecated name - please avoid */
10104#endif
10105 } B;
10106 } LINFLEX_LINFBRR_32B_tag;
10107
10108 typedef union { /* LIN Integer Baud Rate Register */
10109 uint32_t R;
10110 struct {
10111 uint32_t:13;
10112#ifndef USE_FIELD_ALIASES_LINFLEX
10113 uint32_t IBR:19; /* Integer Baud Rates */
10114#else
10115 uint32_t DIV_M:19; /* deprecated name - please avoid */
10116#endif
10117 } B;
10118 } LINFLEX_LINIBRR_32B_tag;
10119
10120 typedef union { /* LIN Checksum Field Register */
10121 uint32_t R;
10122 struct {
10123 uint32_t:24;
10124 uint32_t CF:8; /* Checksum Bits */
10125 } B;
10126 } LINFLEX_LINCFR_32B_tag;
10127
10128 typedef union { /* LIN Control Register 2 */
10129 uint32_t R;
10130 struct {
10131 uint32_t:17;
10132 uint32_t IOBE:1; /* Idle on Bit Error */
10133 uint32_t IOPE:1; /* Idle on Identifier Parity Error */
10134 uint32_t WURQ:1; /* Wakeup Generate Request */
10135 uint32_t DDRQ:1; /* Data Discard Request */
10136 uint32_t DTRQ:1; /* Data Transmission Request */
10137 uint32_t ABRQ:1; /* Abort Request */
10138 uint32_t HTRQ:1; /* Header Transmission Request */
10139 uint32_t:8;
10140 } B;
10141 } LINFLEX_LINCR2_32B_tag;
10142
10143 typedef union { /* Buffer Identifier Register */
10144 uint32_t R;
10145 struct {
10146 uint32_t:16;
10147 uint32_t DFL:6; /* Data Field Length */
10148 uint32_t DIR:1; /* Direction */
10149 uint32_t CCS:1; /* Classic Checksum */
10150 uint32_t:2;
10151 uint32_t ID:6; /* Identifier */
10152 } B;
10153 } LINFLEX_BIDR_32B_tag;
10154
10155 typedef union { /* Buffer Data Register Least Significant */
10156 uint32_t R;
10157 struct {
10158 uint32_t DATA3:8; /* Data3 */
10159 uint32_t DATA2:8; /* Data2 */
10160 uint32_t DATA1:8; /* Data1 */
10161 uint32_t DATA0:8; /* Data0 */
10162 } B;
10163 } LINFLEX_BDRL_32B_tag;
10164
10165 typedef union { /* Buffer Data Register Most Significant */
10166 uint32_t R;
10167 struct {
10168 uint32_t DATA7:8; /* Data7 */
10169 uint32_t DATA6:8; /* Data6 */
10170 uint32_t DATA5:8; /* Data5 */
10171 uint32_t DATA4:8; /* Data4 */
10172 } B;
10173 } LINFLEX_BDRM_32B_tag;
10174
10175 typedef union { /* Identifier Filter Enable Register */
10176 uint32_t R;
10177 struct {
10178 uint32_t:24;
10179 uint32_t FACT:8; /* Filter Active */
10180 } B;
10181 } LINFLEX_IFER_32B_tag;
10182
10183 typedef union { /* Identifier Filter Match Index */
10184 uint32_t R;
10185 struct {
10186 uint32_t:28;
10187 uint32_t IFMI_IFMI:4; /* Filter Match Index */
10188 } B;
10189 } LINFLEX_IFMI_32B_tag;
10190
10191 typedef union { /* Identifier Filter Mode Register */
10192 uint32_t R;
10193 struct {
10194 uint32_t:28;
10195 uint32_t IFM:4; /* Filter Mode */
10196 } B;
10197 } LINFLEX_IFMR_32B_tag;
10198
10199
10200 /* Register layout for all registers IFCR... */
10201
10202 typedef union { /* Identifier Filter Control Register */
10203 uint32_t R;
10204 struct {
10205 uint32_t:16;
10206 uint32_t DFL:6; /* Data Field Length */
10207 uint32_t DIR:1; /* Direction */
10208 uint32_t CCS:1; /* Classic Checksum */
10209 uint32_t:2;
10210 uint32_t ID:6; /* Identifier */
10211 } B;
10212 } LINFLEX_IFCR_32B_tag;
10213
10214 typedef union { /* Global Control Register */
10215 uint32_t R;
10216 struct {
10217 uint32_t:26;
10218 uint32_t TDFBM:1; /* Transmit Data First Bit MSB */
10219 uint32_t RDFBM:1; /* Received Data First Bit MSB */
10220 uint32_t TDLIS:1; /* Transmit Data Level Inversion Selection */
10221 uint32_t RDLIS:1; /* Received Data Level Inversion Selection */
10222 uint32_t STOP:1; /* 1/2 stop bit configuration */
10223 uint32_t SR:1; /* Soft Reset */
10224 } B;
10225 } LINFLEX_GCR_32B_tag;
10226
10227 typedef union { /* UART Preset Time Out Register */
10228 uint32_t R;
10229 struct {
10230 uint32_t:20;
10231 uint32_t PTO:12; /* Preset Time Out */
10232 } B;
10233 } LINFLEX_UARTPTO_32B_tag;
10234
10235 typedef union { /* UART Current Time Out Register */
10236 uint32_t R;
10237 struct {
10238 uint32_t:20;
10239 uint32_t CTO:12; /* Current Time Out */
10240 } B;
10241 } LINFLEX_UARTCTO_32B_tag;
10242
10243 typedef union { /* DMA TX Enable Register */
10244 uint32_t R;
10245 struct {
10246 uint32_t:17;
10247 uint32_t DTE:15; /* DMA Tx channel Enable */
10248 } B;
10249 } LINFLEX_DMATXE_32B_tag;
10250
10251 typedef union { /* DMA RX Enable Register */
10252 uint32_t R;
10253 struct {
10254 uint32_t:17;
10255 uint32_t DRE:15; /* DMA Rx channel Enable */
10256 } B;
10257 } LINFLEX_DMARXE_32B_tag;
10258
10259
10260
10261 typedef struct LINFLEX_struct_tag { /* start of LINFLEX_tag */
10262 /* LIN Control Register */
10263 LINFLEX_LINCR1_32B_tag LINCR1; /* offset: 0x0000 size: 32 bit */
10264 /* LIN Interrupt Enable Register */
10265 LINFLEX_LINIER_32B_tag LINIER; /* offset: 0x0004 size: 32 bit */
10266 /* LIN Status Register */
10267 LINFLEX_LINSR_32B_tag LINSR; /* offset: 0x0008 size: 32 bit */
10268 /* LIN Error Status Register */
10269 LINFLEX_LINESR_32B_tag LINESR; /* offset: 0x000C size: 32 bit */
10270 /* UART Mode Control Register */
10271 LINFLEX_UARTCR_32B_tag UARTCR; /* offset: 0x0010 size: 32 bit */
10272 /* UART Mode Status Register */
10273 LINFLEX_UARTSR_32B_tag UARTSR; /* offset: 0x0014 size: 32 bit */
10274 /* LIN Time-Out Control Status Register */
10275 LINFLEX_LINTCSR_32B_tag LINTCSR; /* offset: 0x0018 size: 32 bit */
10276 /* LIN Output Compare Register */
10277 LINFLEX_LINOCR_32B_tag LINOCR; /* offset: 0x001C size: 32 bit */
10278 /* LIN Time-Out Control Register */
10279 LINFLEX_LINTOCR_32B_tag LINTOCR; /* offset: 0x0020 size: 32 bit */
10280 /* LIN Fractional Baud Rate Register */
10281 LINFLEX_LINFBRR_32B_tag LINFBRR; /* offset: 0x0024 size: 32 bit */
10282 /* LIN Integer Baud Rate Register */
10283 LINFLEX_LINIBRR_32B_tag LINIBRR; /* offset: 0x0028 size: 32 bit */
10284 /* LIN Checksum Field Register */
10285 LINFLEX_LINCFR_32B_tag LINCFR; /* offset: 0x002C size: 32 bit */
10286 /* LIN Control Register 2 */
10287 LINFLEX_LINCR2_32B_tag LINCR2; /* offset: 0x0030 size: 32 bit */
10288 /* Buffer Identifier Register */
10289 LINFLEX_BIDR_32B_tag BIDR; /* offset: 0x0034 size: 32 bit */
10290 /* Buffer Data Register Least Significant */
10291 LINFLEX_BDRL_32B_tag BDRL; /* offset: 0x0038 size: 32 bit */
10292 /* Buffer Data Register Most Significant */
10293 LINFLEX_BDRM_32B_tag BDRM; /* offset: 0x003C size: 32 bit */
10294 /* Identifier Filter Enable Register */
10295 LINFLEX_IFER_32B_tag IFER; /* offset: 0x0040 size: 32 bit */
10296 /* Identifier Filter Match Index */
10297 LINFLEX_IFMI_32B_tag IFMI; /* offset: 0x0044 size: 32 bit */
10298 /* Identifier Filter Mode Register */
10299 LINFLEX_IFMR_32B_tag IFMR; /* offset: 0x0048 size: 32 bit */
10300 union {
10301 /* Identifier Filter Control Register */
10302 LINFLEX_IFCR_32B_tag IFCR[8]; /* offset: 0x004C (0x0004 x 8) */
10303
10304 struct {
10305 /* Identifier Filter Control Register */
10306 LINFLEX_IFCR_32B_tag IFCR0; /* offset: 0x004C size: 32 bit */
10307 LINFLEX_IFCR_32B_tag IFCR1; /* offset: 0x0050 size: 32 bit */
10308 LINFLEX_IFCR_32B_tag IFCR2; /* offset: 0x0054 size: 32 bit */
10309 LINFLEX_IFCR_32B_tag IFCR3; /* offset: 0x0058 size: 32 bit */
10310 LINFLEX_IFCR_32B_tag IFCR4; /* offset: 0x005C size: 32 bit */
10311 LINFLEX_IFCR_32B_tag IFCR5; /* offset: 0x0060 size: 32 bit */
10312 LINFLEX_IFCR_32B_tag IFCR6; /* offset: 0x0064 size: 32 bit */
10313 LINFLEX_IFCR_32B_tag IFCR7; /* offset: 0x0068 size: 32 bit */
10314 };
10315
10316 };
10317 int8_t LINFLEX_reserved_006C[32];
10318 /* Global Control Register */
10319 LINFLEX_GCR_32B_tag GCR; /* offset: 0x008C size: 32 bit */
10320 /* UART Preset Time Out Register */
10321 LINFLEX_UARTPTO_32B_tag UARTPTO; /* offset: 0x0090 size: 32 bit */
10322 /* UART Current Time Out Register */
10323 LINFLEX_UARTCTO_32B_tag UARTCTO; /* offset: 0x0094 size: 32 bit */
10324 /* DMA TX Enable Register */
10325 LINFLEX_DMATXE_32B_tag DMATXE; /* offset: 0x0098 size: 32 bit */
10326 /* DMA RX Enable Register */
10327 LINFLEX_DMARXE_32B_tag DMARXE; /* offset: 0x009C size: 32 bit */
10328 } LINFLEX_tag;
10329
10330
10331#define LINFLEX0 (*(volatile LINFLEX_tag *) 0xFFE40000UL)
10332#define LINFLEX1 (*(volatile LINFLEX_tag *) 0xFFE44000UL)
10333
10334
10335
10336/****************************************************************/
10337/* */
10338/* Module: CRC */
10339/* */
10340/****************************************************************/
10341
10342
10343 /* Register layout for all registers CFG... */
10344
10345 typedef union { /* CRC_CFG - CRC Configuration register */
10346 uint32_t R;
10347 uint8_t BYTE[4]; /* individual bytes can be accessed */
10348 uint16_t HALF[2]; /* individual halfwords can be accessed */
10349 uint32_t WORD; /* individual words can be accessed */
10350 struct {
10351 uint32_t:29;
10352 uint32_t POLYG:1; /* Polynomal selection 0- CRC-CCITT, 1- CRC-CRC-32 INV selection */
10353 uint32_t SWAP:1; /* SWAP selection */
10354 uint32_t INV:1; /* INV selection */
10355 } B;
10356 } CRC_CFG_32B_tag;
10357
10358
10359 /* Register layout for all registers INP... */
10360
10361 typedef union { /* CRC_INP - CRC Input register */
10362 uint32_t R;
10363 uint8_t BYTE[4]; /* individual bytes can be accessed */
10364 uint16_t HALF[2]; /* individual halfwords can be accessed */
10365 uint32_t WORD; /* individual words can be accessed */
10366 } CRC_INP_32B_tag;
10367
10368
10369 /* Register layout for all registers CSTAT... */
10370
10371 typedef union { /* CRC_STATUS - CRC Status register */
10372 uint32_t R;
10373 uint8_t BYTE[4]; /* individual bytes can be accessed */
10374 uint16_t HALF[2]; /* individual halfwords can be accessed */
10375 uint32_t WORD; /* individual words can be accessed */
10376 } CRC_CSTAT_32B_tag;
10377
10378
10379 /* Register layout for all registers OUTP... */
10380
10381 typedef union { /* CRC_STATUS - CRC OUTPUT register */
10382 uint32_t R;
10383 uint8_t BYTE[4]; /* individual bytes can be accessed */
10384 uint16_t HALF[2]; /* individual halfwords can be accessed */
10385 uint32_t WORD; /* individual words can be accessed */
10386 } CRC_OUTP_32B_tag;
10387
10388
10389 typedef struct CRC_CNTX_struct_tag {
10390
10391 /* CRC_CFG - CRC Configuration register */
10392 CRC_CFG_32B_tag CFG; /* relative offset: 0x0000 */
10393 /* CRC_INP - CRC Input register */
10394 CRC_INP_32B_tag INP; /* relative offset: 0x0004 */
10395 /* CRC_STATUS - CRC Status register */
10396 CRC_CSTAT_32B_tag CSTAT; /* relative offset: 0x0008 */
10397 /* CRC_STATUS - CRC OUTPUT register */
10398 CRC_OUTP_32B_tag OUTP; /* relative offset: 0x000C */
10399
10400 } CRC_CNTX_tag;
10401
10402
10403 typedef struct CRC_struct_tag { /* start of CRC_tag */
10404 union {
10405 /* Register set CNTX */
10406 CRC_CNTX_tag CNTX[3]; /* offset: 0x0000 (0x0010 x 3) */
10407
10408 struct {
10409 /* CRC_CFG - CRC Configuration register */
10410 CRC_CFG_32B_tag CFG0; /* offset: 0x0000 size: 32 bit */
10411 /* CRC_INP - CRC Input register */
10412 CRC_INP_32B_tag INP0; /* offset: 0x0004 size: 32 bit */
10413 /* CRC_STATUS - CRC Status register */
10414 CRC_CSTAT_32B_tag CSTAT0; /* offset: 0x0008 size: 32 bit */
10415 /* CRC_STATUS - CRC OUTPUT register */
10416 CRC_OUTP_32B_tag OUTP0; /* offset: 0x000C size: 32 bit */
10417 /* CRC_CFG - CRC Configuration register */
10418 CRC_CFG_32B_tag CFG1; /* offset: 0x0010 size: 32 bit */
10419 /* CRC_INP - CRC Input register */
10420 CRC_INP_32B_tag INP1; /* offset: 0x0014 size: 32 bit */
10421 /* CRC_STATUS - CRC Status register */
10422 CRC_CSTAT_32B_tag CSTAT1; /* offset: 0x0018 size: 32 bit */
10423 /* CRC_STATUS - CRC OUTPUT register */
10424 CRC_OUTP_32B_tag OUTP1; /* offset: 0x001C size: 32 bit */
10425 /* CRC_CFG - CRC Configuration register */
10426 CRC_CFG_32B_tag CFG2; /* offset: 0x0020 size: 32 bit */
10427 /* CRC_INP - CRC Input register */
10428 CRC_INP_32B_tag INP2; /* offset: 0x0024 size: 32 bit */
10429 /* CRC_STATUS - CRC Status register */
10430 CRC_CSTAT_32B_tag CSTAT2; /* offset: 0x0028 size: 32 bit */
10431 /* CRC_STATUS - CRC OUTPUT register */
10432 CRC_OUTP_32B_tag OUTP2; /* offset: 0x002C size: 32 bit */
10433 };
10434
10435 };
10436 } CRC_tag;
10437
10438
10439#define CRC (*(volatile CRC_tag *) 0xFFE68000UL)
10440
10441
10442
10443/****************************************************************/
10444/* */
10445/* Module: FCCU */
10446/* */
10447/****************************************************************/
10448
10449 typedef union { /* FCCU Control Register */
10450 uint32_t R;
10451 struct {
10452 uint32_t:23;
10453 uint32_t NVML:1; /* NVM configuration loaded */
10454 uint32_t OPS:2; /* Operation status */
10455 uint32_t:1;
10456 uint32_t OPR:5; /* Operation run */
10457 } B;
10458 } FCCU_CTRL_32B_tag;
10459
10460 typedef union { /* FCCU CTRL Key Register */
10461 uint32_t R;
10462 } FCCU_CTRLK_32B_tag;
10463
10464 typedef union { /* FCCU Configuration Register */
10465 uint32_t R;
10466 struct {
10467 uint32_t:10;
10468 uint32_t RCCE1:1; /* RCC1 enable */
10469 uint32_t RCCE0:1; /* RCC0 enable */
10470 uint32_t SMRT:4; /* Safe Mode Request Timer */
10471 uint32_t:4;
10472 uint32_t CM:1; /* Config mode */
10473 uint32_t SM:1; /* Switching mode */
10474 uint32_t PS:1; /* Polarity Selection */
10475 uint32_t FOM:3; /* Fault Output Mode Selection */
10476 uint32_t FOP:6; /* Fault Output Prescaler */
10477 } B;
10478 } FCCU_CFG_32B_tag;
10479
10480 typedef union { /* FCCU CF Configuration Register 0 */
10481 uint32_t R;
10482 struct {
10483 uint32_t CFC31:1; /* CF 31 configuration */
10484 uint32_t CFC30:1; /* CF 30 configuration */
10485 uint32_t CFC29:1; /* CF 29 configuration */
10486 uint32_t CFC28:1; /* CF 28 configuration */
10487 uint32_t CFC27:1; /* CF 27 configuration */
10488 uint32_t CFC26:1; /* CF 26 configuration */
10489 uint32_t CFC25:1; /* CF 25 configuration */
10490 uint32_t CFC24:1; /* CF 24 configuration */
10491 uint32_t CFC23:1; /* CF 23 configuration */
10492 uint32_t CFC22:1; /* CF 22 configuration */
10493 uint32_t CFC21:1; /* CF 21 configuration */
10494 uint32_t CFC20:1; /* CF 20 configuration */
10495 uint32_t CFC19:1; /* CF 19 configuration */
10496 uint32_t CFC18:1; /* CF 18 configuration */
10497 uint32_t CFC17:1; /* CF 17 configuration */
10498 uint32_t CFC16:1; /* CF 16 configuration */
10499 uint32_t CFC15:1; /* CF 15 configuration */
10500 uint32_t CFC14:1; /* CF 14 configuration */
10501 uint32_t CFC13:1; /* CF 13 configuration */
10502 uint32_t CFC12:1; /* CF 12 configuration */
10503 uint32_t CFC11:1; /* CF 11 configuration */
10504 uint32_t CFC10:1; /* CF 10 configuration */
10505 uint32_t CFC9:1; /* CF 9 configuration */
10506 uint32_t CFC8:1; /* CF 8 configuration */
10507 uint32_t CFC7:1; /* CF 7 configuration */
10508 uint32_t CFC6:1; /* CF 6 configuration */
10509 uint32_t CFC5:1; /* CF 5 configuration */
10510 uint32_t CFC4:1; /* CF 4 configuration */
10511 uint32_t CFC3:1; /* CF 3 configuration */
10512 uint32_t CFC2:1; /* CF 2 configuration */
10513 uint32_t CFC1:1; /* CF 1 configuration */
10514 uint32_t CFC0:1; /* CF 0 configuration */
10515 } B;
10516 } FCCU_CF_CFG0_32B_tag;
10517
10518 typedef union { /* FCCU CF Configuration Register 1 */
10519 uint32_t R;
10520 struct {
10521 uint32_t CFC63:1; /* CF 63 configuration */
10522 uint32_t CFC62:1; /* CF 62 configuration */
10523 uint32_t CFC61:1; /* CF 61 configuration */
10524 uint32_t CFC60:1; /* CF 60 configuration */
10525 uint32_t CFC59:1; /* CF 59 configuration */
10526 uint32_t CFC58:1; /* CF 58 configuration */
10527 uint32_t CFC57:1; /* CF 57 configuration */
10528 uint32_t CFC56:1; /* CF 56 configuration */
10529 uint32_t CFC55:1; /* CF 55 configuration */
10530 uint32_t CFC54:1; /* CF 54 configuration */
10531 uint32_t CFC53:1; /* CF 53 configuration */
10532 uint32_t CFC52:1; /* CF 52 configuration */
10533 uint32_t CFC51:1; /* CF 51 configuration */
10534 uint32_t CFC50:1; /* CF 50 configuration */
10535 uint32_t CFC49:1; /* CF 49 configuration */
10536 uint32_t CFC48:1; /* CF 48 configuration */
10537 uint32_t CFC47:1; /* CF 47 configuration */
10538 uint32_t CFC46:1; /* CF 46 configuration */
10539 uint32_t CFC45:1; /* CF 45 configuration */
10540 uint32_t CFC44:1; /* CF 44 configuration */
10541 uint32_t CFC43:1; /* CF 43 configuration */
10542 uint32_t CFC42:1; /* CF 42 configuration */
10543 uint32_t CFC41:1; /* CF 41 configuration */
10544 uint32_t CFC40:1; /* CF 40 configuration */
10545 uint32_t CFC39:1; /* CF 39 configuration */
10546 uint32_t CFC38:1; /* CF 38 configuration */
10547 uint32_t CFC37:1; /* CF 37 configuration */
10548 uint32_t CFC36:1; /* CF 36 configuration */
10549 uint32_t CFC35:1; /* CF 35 configuration */
10550 uint32_t CFC34:1; /* CF 34 configuration */
10551 uint32_t CFC33:1; /* CF 33 configuration */
10552 uint32_t CFC32:1; /* CF 32 configuration */
10553 } B;
10554 } FCCU_CF_CFG1_32B_tag;
10555
10556 typedef union { /* FCCU CF Configuration Register 2 */
10557 uint32_t R;
10558 struct {
10559 uint32_t CFC95:1; /* CF 95 configuration */
10560 uint32_t CFC94:1; /* CF 94 configuration */
10561 uint32_t CFC93:1; /* CF 93 configuration */
10562 uint32_t CFC92:1; /* CF 92 configuration */
10563 uint32_t CFC91:1; /* CF 91 configuration */
10564 uint32_t CFC90:1; /* CF 90 configuration */
10565 uint32_t CFC89:1; /* CF 89 configuration */
10566 uint32_t CFC88:1; /* CF 88 configuration */
10567 uint32_t CFC87:1; /* CF 87 configuration */
10568 uint32_t CFC86:1; /* CF 86 configuration */
10569 uint32_t CFC85:1; /* CF 85 configuration */
10570 uint32_t CFC84:1; /* CF 84 configuration */
10571 uint32_t CFC83:1; /* CF 83 configuration */
10572 uint32_t CFC82:1; /* CF 82 configuration */
10573 uint32_t CFC81:1; /* CF 81 configuration */
10574 uint32_t CFC80:1; /* CF 80 configuration */
10575 uint32_t CFC79:1; /* CF 79 configuration */
10576 uint32_t CFC78:1; /* CF 78 configuration */
10577 uint32_t CFC77:1; /* CF 77 configuration */
10578 uint32_t CFC76:1; /* CF 76 configuration */
10579 uint32_t CFC75:1; /* CF 75 configuration */
10580 uint32_t CFC74:1; /* CF 74 configuration */
10581 uint32_t CFC73:1; /* CF 73 configuration */
10582 uint32_t CFC72:1; /* CF 72 configuration */
10583 uint32_t CFC71:1; /* CF 71 configuration */
10584 uint32_t CFC70:1; /* CF 70 configuration */
10585 uint32_t CFC69:1; /* CF 69 configuration */
10586 uint32_t CFC68:1; /* CF 68 configuration */
10587 uint32_t CFC67:1; /* CF 67 configuration */
10588 uint32_t CFC66:1; /* CF 66 configuration */
10589 uint32_t CFC65:1; /* CF 65 configuration */
10590 uint32_t CFC64:1; /* CF 64 configuration */
10591 } B;
10592 } FCCU_CF_CFG2_32B_tag;
10593
10594 typedef union { /* FCCU CF Configuration Register 3 */
10595 uint32_t R;
10596 struct {
10597 uint32_t CFC127:1; /* CF 127 configuration */
10598 uint32_t CFC126:1; /* CF 126 configuration */
10599 uint32_t CFC125:1; /* CF 125 configuration */
10600 uint32_t CFC124:1; /* CF 124 configuration */
10601 uint32_t CFC123:1; /* CF 123 configuration */
10602 uint32_t CFC122:1; /* CF 122 configuration */
10603 uint32_t CFC121:1; /* CF 121 configuration */
10604 uint32_t CFC120:1; /* CF 120 configuration */
10605 uint32_t CFC119:1; /* CF 119 configuration */
10606 uint32_t CFC118:1; /* CF 118 configuration */
10607 uint32_t CFC117:1; /* CF 117 configuration */
10608 uint32_t CFC116:1; /* CF 116 configuration */
10609 uint32_t CFC115:1; /* CF 115 configuration */
10610 uint32_t CFC114:1; /* CF 114 configuration */
10611 uint32_t CFC113:1; /* CF 113 configuration */
10612 uint32_t CFC112:1; /* CF 112 configuration */
10613 uint32_t CFC111:1; /* CF 111 configuration */
10614 uint32_t CFC110:1; /* CF 110 configuration */
10615 uint32_t CFC109:1; /* CF 109 configuration */
10616 uint32_t CFC108:1; /* CF 108 configuration */
10617 uint32_t CFC107:1; /* CF 107 configuration */
10618 uint32_t CFC106:1; /* CF 106 configuration */
10619 uint32_t CFC105:1; /* CF 105 configuration */
10620 uint32_t CFC104:1; /* CF 104 configuration */
10621 uint32_t CFC103:1; /* CF 103 configuration */
10622 uint32_t CFC102:1; /* CF 102 configuration */
10623 uint32_t CFC101:1; /* CF 101 configuration */
10624 uint32_t CFC100:1; /* CF 100 configuration */
10625 uint32_t CFC99:1; /* CF 99 configuration */
10626 uint32_t CFC98:1; /* CF 98 configuration */
10627 uint32_t CFC97:1; /* CF 97 configuration */
10628 uint32_t CFC96:1; /* CF 96 configuration */
10629 } B;
10630 } FCCU_CF_CFG3_32B_tag;
10631
10632 typedef union { /* FCCU NCF Configuration Register 0 */
10633 uint32_t R;
10634 struct {
10635 uint32_t NCFC31:1; /* NCF 31 configuration */
10636 uint32_t NCFC30:1; /* NCF 30 configuration */
10637 uint32_t NCFC29:1; /* NCF 29 configuration */
10638 uint32_t NCFC28:1; /* NCF 28 configuration */
10639 uint32_t NCFC27:1; /* NCF 27 configuration */
10640 uint32_t NCFC26:1; /* NCF 26 configuration */
10641 uint32_t NCFC25:1; /* NCF 25 configuration */
10642 uint32_t NCFC24:1; /* NCF 24 configuration */
10643 uint32_t NCFC23:1; /* NCF 23 configuration */
10644 uint32_t NCFC22:1; /* NCF 22 configuration */
10645 uint32_t NCFC21:1; /* NCF 21 configuration */
10646 uint32_t NCFC20:1; /* NCF 20 configuration */
10647 uint32_t NCFC19:1; /* NCF 19 configuration */
10648 uint32_t NCFC18:1; /* NCF 18 configuration */
10649 uint32_t NCFC17:1; /* NCF 17 configuration */
10650 uint32_t NCFC16:1; /* NCF 16 configuration */
10651 uint32_t NCFC15:1; /* NCF 15 configuration */
10652 uint32_t NCFC14:1; /* NCF 14 configuration */
10653 uint32_t NCFC13:1; /* NCF 13 configuration */
10654 uint32_t NCFC12:1; /* NCF 12 configuration */
10655 uint32_t NCFC11:1; /* NCF 11 configuration */
10656 uint32_t NCFC10:1; /* NCF 10 configuration */
10657 uint32_t NCFC9:1; /* NCF 9 configuration */
10658 uint32_t NCFC8:1; /* NCF 8 configuration */
10659 uint32_t NCFC7:1; /* NCF 7 configuration */
10660 uint32_t NCFC6:1; /* NCF 6 configuration */
10661 uint32_t NCFC5:1; /* NCF 5 configuration */
10662 uint32_t NCFC4:1; /* NCF 4 configuration */
10663 uint32_t NCFC3:1; /* NCF 3 configuration */
10664 uint32_t NCFC2:1; /* NCF 2 configuration */
10665 uint32_t NCFC1:1; /* NCF 1 configuration */
10666 uint32_t NCFC0:1; /* NCF 0 configuration */
10667 } B;
10668 } FCCU_NCF_CFG0_32B_tag;
10669
10670 typedef union { /* FCCU NCF Configuration Register 1 */
10671 uint32_t R;
10672 struct {
10673 uint32_t NCFC63:1; /* NCF 63 configuration */
10674 uint32_t NCFC62:1; /* NCF 62 configuration */
10675 uint32_t NCFC61:1; /* NCF 61 configuration */
10676 uint32_t NCFC60:1; /* NCF 60 configuration */
10677 uint32_t NCFC59:1; /* NCF 59 configuration */
10678 uint32_t NCFC58:1; /* NCF 58 configuration */
10679 uint32_t NCFC57:1; /* NCF 57 configuration */
10680 uint32_t NCFC56:1; /* NCF 56 configuration */
10681 uint32_t NCFC55:1; /* NCF 55 configuration */
10682 uint32_t NCFC54:1; /* NCF 54 configuration */
10683 uint32_t NCFC53:1; /* NCF 53 configuration */
10684 uint32_t NCFC52:1; /* NCF 52 configuration */
10685 uint32_t NCFC51:1; /* NCF 51 configuration */
10686 uint32_t NCFC50:1; /* NCF 50 configuration */
10687 uint32_t NCFC49:1; /* NCF 49 configuration */
10688 uint32_t NCFC48:1; /* NCF 48 configuration */
10689 uint32_t NCFC47:1; /* NCF 47 configuration */
10690 uint32_t NCFC46:1; /* NCF 46 configuration */
10691 uint32_t NCFC45:1; /* NCF 45 configuration */
10692 uint32_t NCFC44:1; /* NCF 44 configuration */
10693 uint32_t NCFC43:1; /* NCF 43 configuration */
10694 uint32_t NCFC42:1; /* NCF 42 configuration */
10695 uint32_t NCFC41:1; /* NCF 41 configuration */
10696 uint32_t NCFC40:1; /* NCF 40 configuration */
10697 uint32_t NCFC39:1; /* NCF 39 configuration */
10698 uint32_t NCFC38:1; /* NCF 38 configuration */
10699 uint32_t NCFC37:1; /* NCF 37 configuration */
10700 uint32_t NCFC36:1; /* NCF 36 configuration */
10701 uint32_t NCFC35:1; /* NCF 35 configuration */
10702 uint32_t NCFC34:1; /* NCF 34 configuration */
10703 uint32_t NCFC33:1; /* NCF 33 configuration */
10704 uint32_t NCFC32:1; /* NCF 32 configuration */
10705 } B;
10706 } FCCU_NCF_CFG1_32B_tag;
10707
10708 typedef union { /* FCCU NCF Configuration Register 2 */
10709 uint32_t R;
10710 struct {
10711 uint32_t NCFC95:1; /* NCF 95 configuration */
10712 uint32_t NCFC94:1; /* NCF 94 configuration */
10713 uint32_t NCFC93:1; /* NCF 93 configuration */
10714 uint32_t NCFC92:1; /* NCF 92 configuration */
10715 uint32_t NCFC91:1; /* NCF 91 configuration */
10716 uint32_t NCFC90:1; /* NCF 90 configuration */
10717 uint32_t NCFC89:1; /* NCF 89 configuration */
10718 uint32_t NCFC88:1; /* NCF 88 configuration */
10719 uint32_t NCFC87:1; /* NCF 87 configuration */
10720 uint32_t NCFC86:1; /* NCF 86 configuration */
10721 uint32_t NCFC85:1; /* NCF 85 configuration */
10722 uint32_t NCFC84:1; /* NCF 84 configuration */
10723 uint32_t NCFC83:1; /* NCF 83 configuration */
10724 uint32_t NCFC82:1; /* NCF 82 configuration */
10725 uint32_t NCFC81:1; /* NCF 81 configuration */
10726 uint32_t NCFC80:1; /* NCF 80 configuration */
10727 uint32_t NCFC79:1; /* NCF 79 configuration */
10728 uint32_t NCFC78:1; /* NCF 78 configuration */
10729 uint32_t NCFC77:1; /* NCF 77 configuration */
10730 uint32_t NCFC76:1; /* NCF 76 configuration */
10731 uint32_t NCFC75:1; /* NCF 75 configuration */
10732 uint32_t NCFC74:1; /* NCF 74 configuration */
10733 uint32_t NCFC73:1; /* NCF 73 configuration */
10734 uint32_t NCFC72:1; /* NCF 72 configuration */
10735 uint32_t NCFC71:1; /* NCF 71 configuration */
10736 uint32_t NCFC70:1; /* NCF 70 configuration */
10737 uint32_t NCFC69:1; /* NCF 69 configuration */
10738 uint32_t NCFC68:1; /* NCF 68 configuration */
10739 uint32_t NCFC67:1; /* NCF 67 configuration */
10740 uint32_t NCFC66:1; /* NCF 66 configuration */
10741 uint32_t NCFC65:1; /* NCF 65 configuration */
10742 uint32_t NCFC64:1; /* NCF 64 configuration */
10743 } B;
10744 } FCCU_NCF_CFG2_32B_tag;
10745
10746 typedef union { /* FCCU NCF Configuration Register 3 */
10747 uint32_t R;
10748 struct {
10749 uint32_t NCFC127:1; /* NCF 127 configuration */
10750 uint32_t NCFC126:1; /* NCF 126 configuration */
10751 uint32_t NCFC125:1; /* NCF 125 configuration */
10752 uint32_t NCFC124:1; /* NCF 124 configuration */
10753 uint32_t NCFC123:1; /* NCF 123 configuration */
10754 uint32_t NCFC122:1; /* NCF 122 configuration */
10755 uint32_t NCFC121:1; /* NCF 121 configuration */
10756 uint32_t NCFC120:1; /* NCF 120 configuration */
10757 uint32_t NCFC119:1; /* NCF 119 configuration */
10758 uint32_t NCFC118:1; /* NCF 118 configuration */
10759 uint32_t NCFC117:1; /* NCF 117 configuration */
10760 uint32_t NCFC116:1; /* NCF 116 configuration */
10761 uint32_t NCFC115:1; /* NCF 115 configuration */
10762 uint32_t NCFC114:1; /* NCF 114 configuration */
10763 uint32_t NCFC113:1; /* NCF 113 configuration */
10764 uint32_t NCFC112:1; /* NCF 112 configuration */
10765 uint32_t NCFC111:1; /* NCF 111 configuration */
10766 uint32_t NCFC110:1; /* NCF 110 configuration */
10767 uint32_t NCFC109:1; /* NCF 109 configuration */
10768 uint32_t NCFC108:1; /* NCF 108 configuration */
10769 uint32_t NCFC107:1; /* NCF 107 configuration */
10770 uint32_t NCFC106:1; /* NCF 106 configuration */
10771 uint32_t NCFC105:1; /* NCF 105 configuration */
10772 uint32_t NCFC104:1; /* NCF 104 configuration */
10773 uint32_t NCFC103:1; /* NCF 103 configuration */
10774 uint32_t NCFC102:1; /* NCF 102 configuration */
10775 uint32_t NCFC101:1; /* NCF 101 configuration */
10776 uint32_t NCFC100:1; /* NCF 100 configuration */
10777 uint32_t NCFC99:1; /* NCF 99 configuration */
10778 uint32_t NCFC98:1; /* NCF 98 configuration */
10779 uint32_t NCFC97:1; /* NCF 97 configuration */
10780 uint32_t NCFC96:1; /* NCF 96 configuration */
10781 } B;
10782 } FCCU_NCF_CFG3_32B_tag;
10783
10784 typedef union { /* FCCU CFS Configuration Register 0 */
10785 uint32_t R;
10786 struct {
10787 uint32_t CFSC15:2; /* CF 15 state configuration */
10788 uint32_t CFSC14:2; /* CF 14 state configuration */
10789 uint32_t CFSC13:2; /* CF 13 state configuration */
10790 uint32_t CFSC12:2; /* CF 12 state configuration */
10791 uint32_t CFSC11:2; /* CF 11 state configuration */
10792 uint32_t CFSC10:2; /* CF 10 state configuration */
10793 uint32_t CFSC9:2; /* CF 9 state configuration */
10794 uint32_t CFSC8:2; /* CF 8 state configuration */
10795 uint32_t CFSC7:2; /* CF 7 state configuration */
10796 uint32_t CFSC6:2; /* CF 6 state configuration */
10797 uint32_t CFSC5:2; /* CF 5 state configuration */
10798 uint32_t CFSC4:2; /* CF 4 state configuration */
10799 uint32_t CFSC3:2; /* CF 3 state configuration */
10800 uint32_t CFSC2:2; /* CF 2 state configuration */
10801 uint32_t CFSC1:2; /* CF 1 state configuration */
10802 uint32_t CFSC0:2; /* CF 0 state configuration */
10803 } B;
10804 } FCCU_CFS_CFG0_32B_tag;
10805
10806 typedef union { /* FCCU CFS Configuration Register 1 */
10807 uint32_t R;
10808 struct {
10809 uint32_t CFSC31:2; /* CF 31 state configuration */
10810 uint32_t CFSC30:2; /* CF 30 state configuration */
10811 uint32_t CFSC29:2; /* CF 29 state configuration */
10812 uint32_t CFSC28:2; /* CF 28 state configuration */
10813 uint32_t CFSC27:2; /* CF 27 state configuration */
10814 uint32_t CFSC26:2; /* CF 26 state configuration */
10815 uint32_t CFSC25:2; /* CF 25 state configuration */
10816 uint32_t CFSC24:2; /* CF 24 state configuration */
10817 uint32_t CFSC23:2; /* CF 23 state configuration */
10818 uint32_t CFSC22:2; /* CF 22 state configuration */
10819 uint32_t CFSC21:2; /* CF 21 state configuration */
10820 uint32_t CFSC20:2; /* CF 20 state configuration */
10821 uint32_t CFSC19:2; /* CF 19 state configuration */
10822 uint32_t CFSC18:2; /* CF 18 state configuration */
10823 uint32_t CFSC17:2; /* CF 17 state configuration */
10824 uint32_t CFSC16:2; /* CF 16 state configuration */
10825 } B;
10826 } FCCU_CFS_CFG1_32B_tag;
10827
10828 typedef union { /* FCCU CFS Configuration Register 2 */
10829 uint32_t R;
10830 struct {
10831 uint32_t CFSC47:2; /* CF 47 state configuration */
10832 uint32_t CFSC46:2; /* CF 46 state configuration */
10833 uint32_t CFSC45:2; /* CF 45 state configuration */
10834 uint32_t CFSC44:2; /* CF 44 state configuration */
10835 uint32_t CFSC43:2; /* CF 43 state configuration */
10836 uint32_t CFSC42:2; /* CF 42 state configuration */
10837 uint32_t CFSC41:2; /* CF 41 state configuration */
10838 uint32_t CFSC40:2; /* CF 40 state configuration */
10839 uint32_t CFSC39:2; /* CF 39 state configuration */
10840 uint32_t CFSC38:2; /* CF 38 state configuration */
10841 uint32_t CFSC37:2; /* CF 37 state configuration */
10842 uint32_t CFSC36:2; /* CF 36 state configuration */
10843 uint32_t CFSC35:2; /* CF 35 state configuration */
10844 uint32_t CFSC34:2; /* CF 34 state configuration */
10845 uint32_t CFSC33:2; /* CF 33 state configuration */
10846 uint32_t CFSC32:2; /* CF 32 state configuration */
10847 } B;
10848 } FCCU_CFS_CFG2_32B_tag;
10849
10850 typedef union { /* FCCU CFS Configuration Register 3 */
10851 uint32_t R;
10852 struct {
10853 uint32_t CFSC63:2; /* CF 63 state configuration */
10854 uint32_t CFSC62:2; /* CF 62 state configuration */
10855 uint32_t CFSC61:2; /* CF 61 state configuration */
10856 uint32_t CFSC60:2; /* CF 60 state configuration */
10857 uint32_t CFSC59:2; /* CF 59 state configuration */
10858 uint32_t CFSC58:2; /* CF 58 state configuration */
10859 uint32_t CFSC57:2; /* CF 57 state configuration */
10860 uint32_t CFSC56:2; /* CF 56 state configuration */
10861 uint32_t CFSC55:2; /* CF 55 state configuration */
10862 uint32_t CFSC54:2; /* CF 54 state configuration */
10863 uint32_t CFSC53:2; /* CF 53 state configuration */
10864 uint32_t CFSC52:2; /* CF 52 state configuration */
10865 uint32_t CFSC51:2; /* CF 51 state configuration */
10866 uint32_t CFSC50:2; /* CF 50 state configuration */
10867 uint32_t CFSC49:2; /* CF 49 state configuration */
10868 uint32_t CFSC48:2; /* CF 48 state configuration */
10869 } B;
10870 } FCCU_CFS_CFG3_32B_tag;
10871
10872 typedef union { /* FCCU CFS Configuration Register 4 */
10873 uint32_t R;
10874 struct {
10875 uint32_t CFSC79:2; /* CF 79 state configuration */
10876 uint32_t CFSC78:2; /* CF 78 state configuration */
10877 uint32_t CFSC77:2; /* CF 77 state configuration */
10878 uint32_t CFSC76:2; /* CF 76 state configuration */
10879 uint32_t CFSC75:2; /* CF 75 state configuration */
10880 uint32_t CFSC74:2; /* CF 74 state configuration */
10881 uint32_t CFSC73:2; /* CF 73 state configuration */
10882 uint32_t CFSC72:2; /* CF 72 state configuration */
10883 uint32_t CFSC71:2; /* CF 71 state configuration */
10884 uint32_t CFSC70:2; /* CF 70 state configuration */
10885 uint32_t CFSC69:2; /* CF 69 state configuration */
10886 uint32_t CFSC68:2; /* CF 68 state configuration */
10887 uint32_t CFSC67:2; /* CF 67 state configuration */
10888 uint32_t CFSC66:2; /* CF 66 state configuration */
10889 uint32_t CFSC65:2; /* CF 65 state configuration */
10890 uint32_t CFSC64:2; /* CF 64 state configuration */
10891 } B;
10892 } FCCU_CFS_CFG4_32B_tag;
10893
10894 typedef union { /* FCCU CFS Configuration Register 5 */
10895 uint32_t R;
10896 struct {
10897 uint32_t CFSC95:2; /* CF 95 state configuration */
10898 uint32_t CFSC94:2; /* CF 94 state configuration */
10899 uint32_t CFSC93:2; /* CF 93 state configuration */
10900 uint32_t CFSC92:2; /* CF 92 state configuration */
10901 uint32_t CFSC91:2; /* CF 91 state configuration */
10902 uint32_t CFSC90:2; /* CF 90 state configuration */
10903 uint32_t CFSC89:2; /* CF 89 state configuration */
10904 uint32_t CFSC88:2; /* CF 88 state configuration */
10905 uint32_t CFSC87:2; /* CF 87 state configuration */
10906 uint32_t CFSC86:2; /* CF 86 state configuration */
10907 uint32_t CFSC85:2; /* CF 85 state configuration */
10908 uint32_t CFSC84:2; /* CF 84 state configuration */
10909 uint32_t CFSC83:2; /* CF 83 state configuration */
10910 uint32_t CFSC82:2; /* CF 82 state configuration */
10911 uint32_t CFSC81:2; /* CF 81 state configuration */
10912 uint32_t CFSC80:2; /* CF 80 state configuration */
10913 } B;
10914 } FCCU_CFS_CFG5_32B_tag;
10915
10916 typedef union { /* FCCU CFS Configuration Register 6 */
10917 uint32_t R;
10918 struct {
10919 uint32_t CFSC111:2; /* CF 111 state configuration */
10920 uint32_t CFSC110:2; /* CF 110 state configuration */
10921 uint32_t CFSC109:2; /* CF 109 state configuration */
10922 uint32_t CFSC108:2; /* CF 108 state configuration */
10923 uint32_t CFSC107:2; /* CF 107 state configuration */
10924 uint32_t CFSC106:2; /* CF 106 state configuration */
10925 uint32_t CFSC105:2; /* CF 105 state configuration */
10926 uint32_t CFSC104:2; /* CF 104 state configuration */
10927 uint32_t CFSC103:2; /* CF 103 state configuration */
10928 uint32_t CFSC102:2; /* CF 102 state configuration */
10929 uint32_t CFSC101:2; /* CF 101 state configuration */
10930 uint32_t CFSC100:2; /* CF 100 state configuration */
10931 uint32_t CFSC99:2; /* CF 99 state configuration */
10932 uint32_t CFSC98:2; /* CF 98 state configuration */
10933 uint32_t CFSC97:2; /* CF 97 state configuration */
10934 uint32_t CFSC96:2; /* CF 96 state configuration */
10935 } B;
10936 } FCCU_CFS_CFG6_32B_tag;
10937
10938 typedef union { /* FCCU CFS Configuration Register 7 */
10939 uint32_t R;
10940 struct {
10941 uint32_t CFSC127:2; /* CF 127 state configuration */
10942 uint32_t CFSC126:2; /* CF 126 state configuration */
10943 uint32_t CFSC125:2; /* CF 125 state configuration */
10944 uint32_t CFSC124:2; /* CF 124 state configuration */
10945 uint32_t CFSC123:2; /* CF 123 state configuration */
10946 uint32_t CFSC122:2; /* CF 122 state configuration */
10947 uint32_t CFSC121:2; /* CF 121 state configuration */
10948 uint32_t CFSC120:2; /* CF 120 state configuration */
10949 uint32_t CFSC119:2; /* CF 119 state configuration */
10950 uint32_t CFSC118:2; /* CF 118 state configuration */
10951 uint32_t CFSC117:2; /* CF 117 state configuration */
10952 uint32_t CFSC116:2; /* CF 116 state configuration */
10953 uint32_t CFSC115:2; /* CF 115 state configuration */
10954 uint32_t CFSC114:2; /* CF 114 state configuration */
10955 uint32_t CFSC113:2; /* CF 113 state configuration */
10956 uint32_t CFSC112:2; /* CF 112 state configuration */
10957 } B;
10958 } FCCU_CFS_CFG7_32B_tag;
10959
10960 typedef union { /* FCCU NCFS Configuration Register 0 */
10961 uint32_t R;
10962 struct {
10963 uint32_t NCFSC15:2; /* NCF 15 state configuration */
10964 uint32_t NCFSC14:2; /* NCF 14 state configuration */
10965 uint32_t NCFSC13:2; /* NCF 13 state configuration */
10966 uint32_t NCFSC12:2; /* NCF 12 state configuration */
10967 uint32_t NCFSC11:2; /* NCF 11 state configuration */
10968 uint32_t NCFSC10:2; /* NCF 10 state configuration */
10969 uint32_t NCFSC9:2; /* NCF 9 state configuration */
10970 uint32_t NCFSC8:2; /* NCF 8 state configuration */
10971 uint32_t NCFSC7:2; /* NCF 7 state configuration */
10972 uint32_t NCFSC6:2; /* NCF 6 state configuration */
10973 uint32_t NCFSC5:2; /* NCF 5 state configuration */
10974 uint32_t NCFSC4:2; /* NCF 4 state configuration */
10975 uint32_t NCFSC3:2; /* NCF 3 state configuration */
10976 uint32_t NCFSC2:2; /* NCF 2 state configuration */
10977 uint32_t NCFSC1:2; /* NCF 1 state configuration */
10978 uint32_t NCFSC0:2; /* NCF 0 state configuration */
10979 } B;
10980 } FCCU_NCFS_CFG0_32B_tag;
10981
10982 typedef union { /* FCCU NCFS Configuration Register 1 */
10983 uint32_t R;
10984 struct {
10985 uint32_t NCFSC31:2; /* NCF 31 state configuration */
10986 uint32_t NCFSC30:2; /* NCF 30 state configuration */
10987 uint32_t NCFSC29:2; /* NCF 29 state configuration */
10988 uint32_t NCFSC28:2; /* NCF 28 state configuration */
10989 uint32_t NCFSC27:2; /* NCF 27 state configuration */
10990 uint32_t NCFSC26:2; /* NCF 26 state configuration */
10991 uint32_t NCFSC25:2; /* NCF 25 state configuration */
10992 uint32_t NCFSC24:2; /* NCF 24 state configuration */
10993 uint32_t NCFSC23:2; /* NCF 23 state configuration */
10994 uint32_t NCFSC22:2; /* NCF 22 state configuration */
10995 uint32_t NCFSC21:2; /* NCF 21 state configuration */
10996 uint32_t NCFSC20:2; /* NCF 20 state configuration */
10997 uint32_t NCFSC19:2; /* NCF 19 state configuration */
10998 uint32_t NCFSC18:2; /* NCF 18 state configuration */
10999 uint32_t NCFSC17:2; /* NCF 17 state configuration */
11000 uint32_t NCFSC16:2; /* NCF 16 state configuration */
11001 } B;
11002 } FCCU_NCFS_CFG1_32B_tag;
11003
11004 typedef union { /* FCCU NCFS Configuration Register 2 */
11005 uint32_t R;
11006 struct {
11007 uint32_t NCFSC47:2; /* NCF 47 state configuration */
11008 uint32_t NCFSC46:2; /* NCF 46 state configuration */
11009 uint32_t NCFSC45:2; /* NCF 45 state configuration */
11010 uint32_t NCFSC44:2; /* NCF 44 state configuration */
11011 uint32_t NCFSC43:2; /* NCF 43 state configuration */
11012 uint32_t NCFSC42:2; /* NCF 42 state configuration */
11013 uint32_t NCFSC41:2; /* NCF 41 state configuration */
11014 uint32_t NCFSC40:2; /* NCF 40 state configuration */
11015 uint32_t NCFSC39:2; /* NCF 39 state configuration */
11016 uint32_t NCFSC38:2; /* NCF 38 state configuration */
11017 uint32_t NCFSC37:2; /* NCF 37 state configuration */
11018 uint32_t NCFSC36:2; /* NCF 36 state configuration */
11019 uint32_t NCFSC35:2; /* NCF 35 state configuration */
11020 uint32_t NCFSC34:2; /* NCF 34 state configuration */
11021 uint32_t NCFSC33:2; /* NCF 33 state configuration */
11022 uint32_t NCFSC32:2; /* NCF 32 state configuration */
11023 } B;
11024 } FCCU_NCFS_CFG2_32B_tag;
11025
11026 typedef union { /* FCCU NCFS Configuration Register 3 */
11027 uint32_t R;
11028 struct {
11029 uint32_t NCFSC63:2; /* NCF 63 state configuration */
11030 uint32_t NCFSC62:2; /* NCF 62 state configuration */
11031 uint32_t NCFSC61:2; /* NCF 61 state configuration */
11032 uint32_t NCFSC60:2; /* NCF 60 state configuration */
11033 uint32_t NCFSC59:2; /* NCF 59 state configuration */
11034 uint32_t NCFSC58:2; /* NCF 58 state configuration */
11035 uint32_t NCFSC57:2; /* NCF 57 state configuration */
11036 uint32_t NCFSC56:2; /* NCF 56 state configuration */
11037 uint32_t NCFSC55:2; /* NCF 55 state configuration */
11038 uint32_t NCFSC54:2; /* NCF 54 state configuration */
11039 uint32_t NCFSC53:2; /* NCF 53 state configuration */
11040 uint32_t NCFSC52:2; /* NCF 52 state configuration */
11041 uint32_t NCFSC51:2; /* NCF 51 state configuration */
11042 uint32_t NCFSC50:2; /* NCF 50 state configuration */
11043 uint32_t NCFSC49:2; /* NCF 49 state configuration */
11044 uint32_t NCFSC48:2; /* NCF 48 state configuration */
11045 } B;
11046 } FCCU_NCFS_CFG3_32B_tag;
11047
11048 typedef union { /* FCCU NCFS Configuration Register 4 */
11049 uint32_t R;
11050 struct {
11051 uint32_t NCFSC79:2; /* NCF 79 state configuration */
11052 uint32_t NCFSC78:2; /* NCF 78 state configuration */
11053 uint32_t NCFSC77:2; /* NCF 77 state configuration */
11054 uint32_t NCFSC76:2; /* NCF 76 state configuration */
11055 uint32_t NCFSC75:2; /* NCF 75 state configuration */
11056 uint32_t NCFSC74:2; /* NCF 74 state configuration */
11057 uint32_t NCFSC73:2; /* NCF 73 state configuration */
11058 uint32_t NCFSC72:2; /* NCF 72 state configuration */
11059 uint32_t NCFSC71:2; /* NCF 71 state configuration */
11060 uint32_t NCFSC70:2; /* NCF 70 state configuration */
11061 uint32_t NCFSC69:2; /* NCF 69 state configuration */
11062 uint32_t NCFSC68:2; /* NCF 68 state configuration */
11063 uint32_t NCFSC67:2; /* NCF 67 state configuration */
11064 uint32_t NCFSC66:2; /* NCF 66 state configuration */
11065 uint32_t NCFSC65:2; /* NCF 65 state configuration */
11066 uint32_t NCFSC64:2; /* NCF 64 state configuration */
11067 } B;
11068 } FCCU_NCFS_CFG4_32B_tag;
11069
11070 typedef union { /* FCCU NCFS Configuration Register 5 */
11071 uint32_t R;
11072 struct {
11073 uint32_t NCFSC95:2; /* NCF 95 state configuration */
11074 uint32_t NCFSC94:2; /* NCF 94 state configuration */
11075 uint32_t NCFSC93:2; /* NCF 93 state configuration */
11076 uint32_t NCFSC92:2; /* NCF 92 state configuration */
11077 uint32_t NCFSC91:2; /* NCF 91 state configuration */
11078 uint32_t NCFSC90:2; /* NCF 90 state configuration */
11079 uint32_t NCFSC89:2; /* NCF 89 state configuration */
11080 uint32_t NCFSC88:2; /* NCF 88 state configuration */
11081 uint32_t NCFSC87:2; /* NCF 87 state configuration */
11082 uint32_t NCFSC86:2; /* NCF 86 state configuration */
11083 uint32_t NCFSC85:2; /* NCF 85 state configuration */
11084 uint32_t NCFSC84:2; /* NCF 84 state configuration */
11085 uint32_t NCFSC83:2; /* NCF 83 state configuration */
11086 uint32_t NCFSC82:2; /* NCF 82 state configuration */
11087 uint32_t NCFSC81:2; /* NCF 81 state configuration */
11088 uint32_t NCFSC80:2; /* NCF 80 state configuration */
11089 } B;
11090 } FCCU_NCFS_CFG5_32B_tag;
11091
11092 typedef union { /* FCCU NCFS Configuration Register 6 */
11093 uint32_t R;
11094 struct {
11095 uint32_t NCFSC111:2; /* NCF 111 state configuration */
11096 uint32_t NCFSC110:2; /* NCF 110 state configuration */
11097 uint32_t NCFSC109:2; /* NCF 109 state configuration */
11098 uint32_t NCFSC108:2; /* NCF 108 state configuration */
11099 uint32_t NCFSC107:2; /* NCF 107 state configuration */
11100 uint32_t NCFSC106:2; /* NCF 106 state configuration */
11101 uint32_t NCFSC105:2; /* NCF 105 state configuration */
11102 uint32_t NCFSC104:2; /* NCF 104 state configuration */
11103 uint32_t NCFSC103:2; /* NCF 103 state configuration */
11104 uint32_t NCFSC102:2; /* NCF 102 state configuration */
11105 uint32_t NCFSC101:2; /* NCF 101 state configuration */
11106 uint32_t NCFSC100:2; /* NCF 100 state configuration */
11107 uint32_t NCFSC99:2; /* NCF 99 state configuration */
11108 uint32_t NCFSC98:2; /* NCF 98 state configuration */
11109 uint32_t NCFSC97:2; /* NCF 97 state configuration */
11110 uint32_t NCFSC96:2; /* NCF 96 state configuration */
11111 } B;
11112 } FCCU_NCFS_CFG6_32B_tag;
11113
11114 typedef union { /* FCCU NCFS Configuration Register 7 */
11115 uint32_t R;
11116 struct {
11117 uint32_t NCFSC127:2; /* NCF 127 state configuration */
11118 uint32_t NCFSC126:2; /* NCF 126 state configuration */
11119 uint32_t NCFSC125:2; /* NCF 125 state configuration */
11120 uint32_t NCFSC124:2; /* NCF 124 state configuration */
11121 uint32_t NCFSC123:2; /* NCF 123 state configuration */
11122 uint32_t NCFSC122:2; /* NCF 122 state configuration */
11123 uint32_t NCFSC121:2; /* NCF 121 state configuration */
11124 uint32_t NCFSC120:2; /* NCF 120 state configuration */
11125 uint32_t NCFSC119:2; /* NCF 119 state configuration */
11126 uint32_t NCFSC118:2; /* NCF 118 state configuration */
11127 uint32_t NCFSC117:2; /* NCF 117 state configuration */
11128 uint32_t NCFSC116:2; /* NCF 116 state configuration */
11129 uint32_t NCFSC115:2; /* NCF 115 state configuration */
11130 uint32_t NCFSC114:2; /* NCF 114 state configuration */
11131 uint32_t NCFSC113:2; /* NCF 113 state configuration */
11132 uint32_t NCFSC112:2; /* NCF 112 state configuration */
11133 } B;
11134 } FCCU_NCFS_CFG7_32B_tag;
11135
11136 typedef union { /* FCCU CF Status Register 0 */
11137 uint32_t R;
11138 struct {
11139 uint32_t CFS31:1; /* CF 31 status */
11140 uint32_t CFS30:1; /* CF 30 status */
11141 uint32_t CFS29:1; /* CF 29 status */
11142 uint32_t CFS28:1; /* CF 28 status */
11143 uint32_t CFS27:1; /* CF 27 status */
11144 uint32_t CFS26:1; /* CF 26 status */
11145 uint32_t CFS25:1; /* CF 25 status */
11146 uint32_t CFS24:1; /* CF 24 status */
11147 uint32_t CFS23:1; /* CF 23 status */
11148 uint32_t CFS22:1; /* CF 22 status */
11149 uint32_t CFS21:1; /* CF 21 status */
11150 uint32_t CFS20:1; /* CF 20 status */
11151 uint32_t CFS19:1; /* CF 19 status */
11152 uint32_t CFS18:1; /* CF 18 status */
11153 uint32_t CFS17:1; /* CF 17 status */
11154 uint32_t CFS16:1; /* CF 16 status */
11155 uint32_t CFS15:1; /* CF 15 status */
11156 uint32_t CFS14:1; /* CF 14 status */
11157 uint32_t CFS13:1; /* CF 13 status */
11158 uint32_t CFS12:1; /* CF 12 status */
11159 uint32_t CFS11:1; /* CF 11 status */
11160 uint32_t CFS10:1; /* CF 10 status */
11161 uint32_t CFS9:1; /* CF 9 status */
11162 uint32_t CFS8:1; /* CF 8 status */
11163 uint32_t CFS7:1; /* CF 7 status */
11164 uint32_t CFS6:1; /* CF 6 status */
11165 uint32_t CFS5:1; /* CF 5 status */
11166 uint32_t CFS4:1; /* CF 4 status */
11167 uint32_t CFS3:1; /* CF 3 status */
11168 uint32_t CFS2:1; /* CF 2 status */
11169 uint32_t CFS1:1; /* CF 1 status */
11170 uint32_t CFS0:1; /* CF 0 status */
11171 } B;
11172 } FCCU_CFS0_32B_tag;
11173
11174 typedef union { /* FCCU CF Status Register 1 */
11175 uint32_t R;
11176 struct {
11177 uint32_t CFS63:1; /* CF 63 status */
11178 uint32_t CFS62:1; /* CF 62 status */
11179 uint32_t CFS61:1; /* CF 61 status */
11180 uint32_t CFS60:1; /* CF 60 status */
11181 uint32_t CFS59:1; /* CF 59 status */
11182 uint32_t CFS58:1; /* CF 58 status */
11183 uint32_t CFS57:1; /* CF 57 status */
11184 uint32_t CFS56:1; /* CF 56 status */
11185 uint32_t CFS55:1; /* CF 55 status */
11186 uint32_t CFS54:1; /* CF 54 status */
11187 uint32_t CFS53:1; /* CF 53 status */
11188 uint32_t CFS52:1; /* CF 52 status */
11189 uint32_t CFS51:1; /* CF 51 status */
11190 uint32_t CFS50:1; /* CF 50 status */
11191 uint32_t CFS49:1; /* CF 49 status */
11192 uint32_t CFS48:1; /* CF 48 status */
11193 uint32_t CFS47:1; /* CF 47 status */
11194 uint32_t CFS46:1; /* CF 46 status */
11195 uint32_t CFS45:1; /* CF 45 status */
11196 uint32_t CFS44:1; /* CF 44 status */
11197 uint32_t CFS43:1; /* CF 43 status */
11198 uint32_t CFS42:1; /* CF 42 status */
11199 uint32_t CFS41:1; /* CF 41 status */
11200 uint32_t CFS40:1; /* CF 40 status */
11201 uint32_t CFS39:1; /* CF 39 status */
11202 uint32_t CFS38:1; /* CF 38 status */
11203 uint32_t CFS37:1; /* CF 37 status */
11204 uint32_t CFS36:1; /* CF 36 status */
11205 uint32_t CFS35:1; /* CF 35 status */
11206 uint32_t CFS34:1; /* CF 34 status */
11207 uint32_t CFS33:1; /* CF 33 status */
11208 uint32_t CFS32:1; /* CF 32 status */
11209 } B;
11210 } FCCU_CFS1_32B_tag;
11211
11212 typedef union { /* FCCU CF Status Register 2 */
11213 uint32_t R;
11214 struct {
11215 uint32_t CFS95:1; /* CF 95 status */
11216 uint32_t CFS94:1; /* CF 94 status */
11217 uint32_t CFS93:1; /* CF 93 status */
11218 uint32_t CFS92:1; /* CF 92 status */
11219 uint32_t CFS91:1; /* CF 91 status */
11220 uint32_t CFS90:1; /* CF 90 status */
11221 uint32_t CFS89:1; /* CF 89 status */
11222 uint32_t CFS88:1; /* CF 88 status */
11223 uint32_t CFS87:1; /* CF 87 status */
11224 uint32_t CFS86:1; /* CF 86 status */
11225 uint32_t CFS85:1; /* CF 85 status */
11226 uint32_t CFS84:1; /* CF 84 status */
11227 uint32_t CFS83:1; /* CF 83 status */
11228 uint32_t CFS82:1; /* CF 82 status */
11229 uint32_t CFS81:1; /* CF 81 status */
11230 uint32_t CFS80:1; /* CF 80 status */
11231 uint32_t CFS79:1; /* CF 79 status */
11232 uint32_t CFS78:1; /* CF 78 status */
11233 uint32_t CFS77:1; /* CF 77 status */
11234 uint32_t CFS76:1; /* CF 76 status */
11235 uint32_t CFS75:1; /* CF 75 status */
11236 uint32_t CFS74:1; /* CF 74 status */
11237 uint32_t CFS73:1; /* CF 73 status */
11238 uint32_t CFS72:1; /* CF 72 status */
11239 uint32_t CFS71:1; /* CF 71 status */
11240 uint32_t CFS70:1; /* CF 70 status */
11241 uint32_t CFS69:1; /* CF 69 status */
11242 uint32_t CFS68:1; /* CF 68 status */
11243 uint32_t CFS67:1; /* CF 67 status */
11244 uint32_t CFS66:1; /* CF 66 status */
11245 uint32_t CFS65:1; /* CF 65 status */
11246 uint32_t CFS64:1; /* CF 64 status */
11247 } B;
11248 } FCCU_CFS2_32B_tag;
11249
11250 typedef union { /* FCCU CF Status Register 3 */
11251 uint32_t R;
11252 struct {
11253 uint32_t CFS127:1; /* CF 127 status */
11254 uint32_t CFS126:1; /* CF 126 status */
11255 uint32_t CFS125:1; /* CF 125 status */
11256 uint32_t CFS124:1; /* CF 124 status */
11257 uint32_t CFS123:1; /* CF 123 status */
11258 uint32_t CFS122:1; /* CF 122 status */
11259 uint32_t CFS121:1; /* CF 121 status */
11260 uint32_t CFS120:1; /* CF 120 status */
11261 uint32_t CFS119:1; /* CF 119 status */
11262 uint32_t CFS118:1; /* CF 118 status */
11263 uint32_t CFS117:1; /* CF 117 status */
11264 uint32_t CFS116:1; /* CF 116 status */
11265 uint32_t CFS115:1; /* CF 115 status */
11266 uint32_t CFS114:1; /* CF 114 status */
11267 uint32_t CFS113:1; /* CF 113 status */
11268 uint32_t CFS112:1; /* CF 112 status */
11269 uint32_t CFS111:1; /* CF 111 status */
11270 uint32_t CFS110:1; /* CF 110 status */
11271 uint32_t CFS109:1; /* CF 109 status */
11272 uint32_t CFS108:1; /* CF 108 status */
11273 uint32_t CFS107:1; /* CF 107 status */
11274 uint32_t CFS106:1; /* CF 106 status */
11275 uint32_t CFS105:1; /* CF 105 status */
11276 uint32_t CFS104:1; /* CF 104 status */
11277 uint32_t CFS103:1; /* CF 103 status */
11278 uint32_t CFS102:1; /* CF 102 status */
11279 uint32_t CFS101:1; /* CF 101 status */
11280 uint32_t CFS100:1; /* CF 100 status */
11281 uint32_t CFS99:1; /* CF 99 status */
11282 uint32_t CFS98:1; /* CF 98 status */
11283 uint32_t CFS97:1; /* CF 97 status */
11284 uint32_t CFS96:1; /* CF 96 status */
11285 } B;
11286 } FCCU_CFS3_32B_tag;
11287
11288 typedef union { /* FCCU_CFK - FCCU CF Key Register */
11289 uint32_t R;
11290 } FCCU_CFK_32B_tag;
11291
11292 typedef union { /* FCCU NCF Status Register 0 */
11293 uint32_t R;
11294 struct {
11295 uint32_t NCFS31:1; /* NCF 31 status */
11296 uint32_t NCFS30:1; /* NCF 30 status */
11297 uint32_t NCFS29:1; /* NCF 29 status */
11298 uint32_t NCFS28:1; /* NCF 28 status */
11299 uint32_t NCFS27:1; /* NCF 27 status */
11300 uint32_t NCFS26:1; /* NCF 26 status */
11301 uint32_t NCFS25:1; /* NCF 25 status */
11302 uint32_t NCFS24:1; /* NCF 24 status */
11303 uint32_t NCFS23:1; /* NCF 23 status */
11304 uint32_t NCFS22:1; /* NCF 22 status */
11305 uint32_t NCFS21:1; /* NCF 21 status */
11306 uint32_t NCFS20:1; /* NCF 20 status */
11307 uint32_t NCFS19:1; /* NCF 19 status */
11308 uint32_t NCFS18:1; /* NCF 18 status */
11309 uint32_t NCFS17:1; /* NCF 17 status */
11310 uint32_t NCFS16:1; /* NCF 16 status */
11311 uint32_t NCFS15:1; /* NCF 15 status */
11312 uint32_t NCFS14:1; /* NCF 14 status */
11313 uint32_t NCFS13:1; /* NCF 13 status */
11314 uint32_t NCFS12:1; /* NCF 12 status */
11315 uint32_t NCFS11:1; /* NCF 11 status */
11316 uint32_t NCFS10:1; /* NCF 10 status */
11317 uint32_t NCFS9:1; /* NCF 9 status */
11318 uint32_t NCFS8:1; /* NCF 8 status */
11319 uint32_t NCFS7:1; /* NCF 7 status */
11320 uint32_t NCFS6:1; /* NCF 6 status */
11321 uint32_t NCFS5:1; /* NCF 5 status */
11322 uint32_t NCFS4:1; /* NCF 4 status */
11323 uint32_t NCFS3:1; /* NCF 3 status */
11324 uint32_t NCFS2:1; /* NCF 2 status */
11325 uint32_t NCFS1:1; /* NCF 1 status */
11326 uint32_t NCFS0:1; /* NCF 0 status */
11327 } B;
11328 } FCCU_NCFS0_32B_tag;
11329
11330 typedef union { /* FCCU NCF Status Register 1 */
11331 uint32_t R;
11332 struct {
11333 uint32_t NCFS63:1; /* NCF 63 status */
11334 uint32_t NCFS62:1; /* NCF 62 status */
11335 uint32_t NCFS61:1; /* NCF 61 status */
11336 uint32_t NCFS60:1; /* NCF 60 status */
11337 uint32_t NCFS59:1; /* NCF 59 status */
11338 uint32_t NCFS58:1; /* NCF 58 status */
11339 uint32_t NCFS57:1; /* NCF 57 status */
11340 uint32_t NCFS56:1; /* NCF 56 status */
11341 uint32_t NCFS55:1; /* NCF 55 status */
11342 uint32_t NCFS54:1; /* NCF 54 status */
11343 uint32_t NCFS53:1; /* NCF 53 status */
11344 uint32_t NCFS52:1; /* NCF 52 status */
11345 uint32_t NCFS51:1; /* NCF 51 status */
11346 uint32_t NCFS50:1; /* NCF 50 status */
11347 uint32_t NCFS49:1; /* NCF 49 status */
11348 uint32_t NCFS48:1; /* NCF 48 status */
11349 uint32_t NCFS47:1; /* NCF 47 status */
11350 uint32_t NCFS46:1; /* NCF 46 status */
11351 uint32_t NCFS45:1; /* NCF 45 status */
11352 uint32_t NCFS44:1; /* NCF 44 status */
11353 uint32_t NCFS43:1; /* NCF 43 status */
11354 uint32_t NCFS42:1; /* NCF 42 status */
11355 uint32_t NCFS41:1; /* NCF 41 status */
11356 uint32_t NCFS40:1; /* NCF 40 status */
11357 uint32_t NCFS39:1; /* NCF 39 status */
11358 uint32_t NCFS38:1; /* NCF 38 status */
11359 uint32_t NCFS37:1; /* NCF 37 status */
11360 uint32_t NCFS36:1; /* NCF 36 status */
11361 uint32_t NCFS35:1; /* NCF 35 status */
11362 uint32_t NCFS34:1; /* NCF 34 status */
11363 uint32_t NCFS33:1; /* NCF 33 status */
11364 uint32_t NCFS32:1; /* NCF 32 status */
11365 } B;
11366 } FCCU_NCFS1_32B_tag;
11367
11368 typedef union { /* FCCU NCF Status Register 2 */
11369 uint32_t R;
11370 struct {
11371 uint32_t NCFS95:1; /* NCF 95 status */
11372 uint32_t NCFS94:1; /* NCF 94 status */
11373 uint32_t NCFS93:1; /* NCF 93 status */
11374 uint32_t NCFS92:1; /* NCF 92 status */
11375 uint32_t NCFS91:1; /* NCF 91 status */
11376 uint32_t NCFS90:1; /* NCF 90 status */
11377 uint32_t NCFS89:1; /* NCF 89 status */
11378 uint32_t NCFS88:1; /* NCF 88 status */
11379 uint32_t NCFS87:1; /* NCF 87 status */
11380 uint32_t NCFS86:1; /* NCF 86 status */
11381 uint32_t NCFS85:1; /* NCF 85 status */
11382 uint32_t NCFS84:1; /* NCF 84 status */
11383 uint32_t NCFS83:1; /* NCF 83 status */
11384 uint32_t NCFS82:1; /* NCF 82 status */
11385 uint32_t NCFS81:1; /* NCF 81 status */
11386 uint32_t NCFS80:1; /* NCF 80 status */
11387 uint32_t NCFS79:1; /* NCF 79 status */
11388 uint32_t NCFS78:1; /* NCF 78 status */
11389 uint32_t NCFS77:1; /* NCF 77 status */
11390 uint32_t NCFS76:1; /* NCF 76 status */
11391 uint32_t NCFS75:1; /* NCF 75 status */
11392 uint32_t NCFS74:1; /* NCF 74 status */
11393 uint32_t NCFS73:1; /* NCF 73 status */
11394 uint32_t NCFS72:1; /* NCF 72 status */
11395 uint32_t NCFS71:1; /* NCF 71 status */
11396 uint32_t NCFS70:1; /* NCF 70 status */
11397 uint32_t NCFS69:1; /* NCF 69 status */
11398 uint32_t NCFS68:1; /* NCF 68 status */
11399 uint32_t NCFS67:1; /* NCF 67 status */
11400 uint32_t NCFS66:1; /* NCF 66 status */
11401 uint32_t NCFS65:1; /* NCF 65 status */
11402 uint32_t NCFS64:1; /* NCF 64 status */
11403 } B;
11404 } FCCU_NCFS2_32B_tag;
11405
11406 typedef union { /* FCCU NCF Status Register 3 */
11407 uint32_t R;
11408 struct {
11409 uint32_t NCFS127:1; /* NCF 127 status */
11410 uint32_t NCFS126:1; /* NCF 126 status */
11411 uint32_t NCFS125:1; /* NCF 125 status */
11412 uint32_t NCFS124:1; /* NCF 124 status */
11413 uint32_t NCFS123:1; /* NCF 123 status */
11414 uint32_t NCFS122:1; /* NCF 122 status */
11415 uint32_t NCFS121:1; /* NCF 121 status */
11416 uint32_t NCFS120:1; /* NCF 120 status */
11417 uint32_t NCFS119:1; /* NCF 119 status */
11418 uint32_t NCFS118:1; /* NCF 118 status */
11419 uint32_t NCFS117:1; /* NCF 117 status */
11420 uint32_t NCFS116:1; /* NCF 116 status */
11421 uint32_t NCFS115:1; /* NCF 115 status */
11422 uint32_t NCFS114:1; /* NCF 114 status */
11423 uint32_t NCFS113:1; /* NCF 113 status */
11424 uint32_t NCFS112:1; /* NCF 112 status */
11425 uint32_t NCFS111:1; /* NCF 111 status */
11426 uint32_t NCFS110:1; /* NCF 110 status */
11427 uint32_t NCFS109:1; /* NCF 109 status */
11428 uint32_t NCFS108:1; /* NCF 108 status */
11429 uint32_t NCFS107:1; /* NCF 107 status */
11430 uint32_t NCFS106:1; /* NCF 106 status */
11431 uint32_t NCFS105:1; /* NCF 105 status */
11432 uint32_t NCFS104:1; /* NCF 104 status */
11433 uint32_t NCFS103:1; /* NCF 103 status */
11434 uint32_t NCFS102:1; /* NCF 102 status */
11435 uint32_t NCFS101:1; /* NCF 101 status */
11436 uint32_t NCFS100:1; /* NCF 100 status */
11437 uint32_t NCFS99:1; /* NCF 99 status */
11438 uint32_t NCFS98:1; /* NCF 98 status */
11439 uint32_t NCFS97:1; /* NCF 97 status */
11440 uint32_t NCFS96:1; /* NCF 96 status */
11441 } B;
11442 } FCCU_NCFS3_32B_tag;
11443
11444 typedef union { /* FCCU_NCFK - FCCU NCF Key Register */
11445 uint32_t R;
11446 } FCCU_NCFK_32B_tag;
11447
11448 typedef union { /* FCCU NCF Enable Register 0 */
11449 uint32_t R;
11450 struct {
11451 uint32_t NCFE31:1; /* NCF 31 enable */
11452 uint32_t NCFE30:1; /* NCF 30 enable */
11453 uint32_t NCFE29:1; /* NCF 29 enable */
11454 uint32_t NCFE28:1; /* NCF 28 enable */
11455 uint32_t NCFE27:1; /* NCF 27 enable */
11456 uint32_t NCFE26:1; /* NCF 26 enable */
11457 uint32_t NCFE25:1; /* NCF 25 enable */
11458 uint32_t NCFE24:1; /* NCF 24 enable */
11459 uint32_t NCFE23:1; /* NCF 23 enable */
11460 uint32_t NCFE22:1; /* NCF 22 enable */
11461 uint32_t NCFE21:1; /* NCF 21 enable */
11462 uint32_t NCFE20:1; /* NCF 20 enable */
11463 uint32_t NCFE19:1; /* NCF 19 enable */
11464 uint32_t NCFE18:1; /* NCF 18 enable */
11465 uint32_t NCFE17:1; /* NCF 17 enable */
11466 uint32_t NCFE16:1; /* NCF 16 enable */
11467 uint32_t NCFE15:1; /* NCF 15 enable */
11468 uint32_t NCFE14:1; /* NCF 14 enable */
11469 uint32_t NCFE13:1; /* NCF 13 enable */
11470 uint32_t NCFE12:1; /* NCF 12 enable */
11471 uint32_t NCFE11:1; /* NCF 11 enable */
11472 uint32_t NCFE10:1; /* NCF 10 enable */
11473 uint32_t NCFE9:1; /* NCF 9 enable */
11474 uint32_t NCFE8:1; /* NCF 8 enable */
11475 uint32_t NCFE7:1; /* NCF 7 enable */
11476 uint32_t NCFE6:1; /* NCF 6 enable */
11477 uint32_t NCFE5:1; /* NCF 5 enable */
11478 uint32_t NCFE4:1; /* NCF 4 enable */
11479 uint32_t NCFE3:1; /* NCF 3 enable */
11480 uint32_t NCFE2:1; /* NCF 2 enable */
11481 uint32_t NCFE1:1; /* NCF 1 enable */
11482 uint32_t NCFE0:1; /* NCF 0 enable */
11483 } B;
11484 } FCCU_NCFE0_32B_tag;
11485
11486 typedef union { /* FCCU NCF Enable Register 1 */
11487 uint32_t R;
11488 struct {
11489 uint32_t NCFE63:1; /* NCF 63 enable */
11490 uint32_t NCFE62:1; /* NCF 62 enable */
11491 uint32_t NCFE61:1; /* NCF 61 enable */
11492 uint32_t NCFE60:1; /* NCF 60 enable */
11493 uint32_t NCFE59:1; /* NCF 59 enable */
11494 uint32_t NCFE58:1; /* NCF 58 enable */
11495 uint32_t NCFE57:1; /* NCF 57 enable */
11496 uint32_t NCFE56:1; /* NCF 56 enable */
11497 uint32_t NCFE55:1; /* NCF 55 enable */
11498 uint32_t NCFE54:1; /* NCF 54 enable */
11499 uint32_t NCFE53:1; /* NCF 53 enable */
11500 uint32_t NCFE52:1; /* NCF 52 enable */
11501 uint32_t NCFE51:1; /* NCF 51 enable */
11502 uint32_t NCFE50:1; /* NCF 50 enable */
11503 uint32_t NCFE49:1; /* NCF 49 enable */
11504 uint32_t NCFE48:1; /* NCF 48 enable */
11505 uint32_t NCFE47:1; /* NCF 47 enable */
11506 uint32_t NCFE46:1; /* NCF 46 enable */
11507 uint32_t NCFE45:1; /* NCF 45 enable */
11508 uint32_t NCFE44:1; /* NCF 44 enable */
11509 uint32_t NCFE43:1; /* NCF 43 enable */
11510 uint32_t NCFE42:1; /* NCF 42 enable */
11511 uint32_t NCFE41:1; /* NCF 41 enable */
11512 uint32_t NCFE40:1; /* NCF 40 enable */
11513 uint32_t NCFE39:1; /* NCF 39 enable */
11514 uint32_t NCFE38:1; /* NCF 38 enable */
11515 uint32_t NCFE37:1; /* NCF 37 enable */
11516 uint32_t NCFE36:1; /* NCF 36 enable */
11517 uint32_t NCFE35:1; /* NCF 35 enable */
11518 uint32_t NCFE34:1; /* NCF 34 enable */
11519 uint32_t NCFE33:1; /* NCF 33 enable */
11520 uint32_t NCFE32:1; /* NCF 32 enable */
11521 } B;
11522 } FCCU_NCFE1_32B_tag;
11523
11524 typedef union { /* FCCU NCF Enable Register 2 */
11525 uint32_t R;
11526 struct {
11527 uint32_t NCFE95:1; /* NCF 95 enable */
11528 uint32_t NCFE94:1; /* NCF 94 enable */
11529 uint32_t NCFE93:1; /* NCF 93 enable */
11530 uint32_t NCFE92:1; /* NCF 92 enable */
11531 uint32_t NCFE91:1; /* NCF 91 enable */
11532 uint32_t NCFE90:1; /* NCF 90 enable */
11533 uint32_t NCFE89:1; /* NCF 89 enable */
11534 uint32_t NCFE88:1; /* NCF 88 enable */
11535 uint32_t NCFE87:1; /* NCF 87 enable */
11536 uint32_t NCFE86:1; /* NCF 86 enable */
11537 uint32_t NCFE85:1; /* NCF 85 enable */
11538 uint32_t NCFE84:1; /* NCF 84 enable */
11539 uint32_t NCFE83:1; /* NCF 83 enable */
11540 uint32_t NCFE82:1; /* NCF 82 enable */
11541 uint32_t NCFE81:1; /* NCF 81 enable */
11542 uint32_t NCFE80:1; /* NCF 80 enable */
11543 uint32_t NCFE79:1; /* NCF 79 enable */
11544 uint32_t NCFE78:1; /* NCF 78 enable */
11545 uint32_t NCFE77:1; /* NCF 77 enable */
11546 uint32_t NCFE76:1; /* NCF 76 enable */
11547 uint32_t NCFE75:1; /* NCF 75 enable */
11548 uint32_t NCFE74:1; /* NCF 74 enable */
11549 uint32_t NCFE73:1; /* NCF 73 enable */
11550 uint32_t NCFE72:1; /* NCF 72 enable */
11551 uint32_t NCFE71:1; /* NCF 71 enable */
11552 uint32_t NCFE70:1; /* NCF 70 enable */
11553 uint32_t NCFE69:1; /* NCF 69 enable */
11554 uint32_t NCFE68:1; /* NCF 68 enable */
11555 uint32_t NCFE67:1; /* NCF 67 enable */
11556 uint32_t NCFE66:1; /* NCF 66 enable */
11557 uint32_t NCFE65:1; /* NCF 65 enable */
11558 uint32_t NCFE64:1; /* NCF 64 enable */
11559 } B;
11560 } FCCU_NCFE2_32B_tag;
11561
11562 typedef union { /* FCCU NCF Enable Register 3 */
11563 uint32_t R;
11564 struct {
11565 uint32_t NCFE127:1; /* NCF 127 enable */
11566 uint32_t NCFE126:1; /* NCF 126 enable */
11567 uint32_t NCFE125:1; /* NCF 125 enable */
11568 uint32_t NCFE124:1; /* NCF 124 enable */
11569 uint32_t NCFE123:1; /* NCF 123 enable */
11570 uint32_t NCFE122:1; /* NCF 122 enable */
11571 uint32_t NCFE121:1; /* NCF 121 enable */
11572 uint32_t NCFE120:1; /* NCF 120 enable */
11573 uint32_t NCFE119:1; /* NCF 119 enable */
11574 uint32_t NCFE118:1; /* NCF 118 enable */
11575 uint32_t NCFE117:1; /* NCF 117 enable */
11576 uint32_t NCFE116:1; /* NCF 116 enable */
11577 uint32_t NCFE115:1; /* NCF 115 enable */
11578 uint32_t NCFE114:1; /* NCF 114 enable */
11579 uint32_t NCFE113:1; /* NCF 113 enable */
11580 uint32_t NCFE112:1; /* NCF 112 enable */
11581 uint32_t NCFE111:1; /* NCF 111 enable */
11582 uint32_t NCFE110:1; /* NCF 110 enable */
11583 uint32_t NCFE109:1; /* NCF 109 enable */
11584 uint32_t NCFE108:1; /* NCF 108 enable */
11585 uint32_t NCFE107:1; /* NCF 107 enable */
11586 uint32_t NCFE106:1; /* NCF 106 enable */
11587 uint32_t NCFE105:1; /* NCF 105 enable */
11588 uint32_t NCFE104:1; /* NCF 104 enable */
11589 uint32_t NCFE103:1; /* NCF 103 enable */
11590 uint32_t NCFE102:1; /* NCF 102 enable */
11591 uint32_t NCFE101:1; /* NCF 101 enable */
11592 uint32_t NCFE100:1; /* NCF 100 enable */
11593 uint32_t NCFE99:1; /* NCF 99 enable */
11594 uint32_t NCFE98:1; /* NCF 98 enable */
11595 uint32_t NCFE97:1; /* NCF 97 enable */
11596 uint32_t NCFE96:1; /* NCF 96 enable */
11597 } B;
11598 } FCCU_NCFE3_32B_tag;
11599
11600 typedef union { /* FCCU NCF Time-out Enable Register 0 */
11601 uint32_t R;
11602 struct {
11603 uint32_t NCFTOE31:1; /* NCF 31 time-out enable */
11604 uint32_t NCFTOE30:1; /* NCF 30 time-out enable */
11605 uint32_t NCFTOE29:1; /* NCF 29 time-out enable */
11606 uint32_t NCFTOE28:1; /* NCF 28 time-out enable */
11607 uint32_t NCFTOE27:1; /* NCF 27 time-out enable */
11608 uint32_t NCFTOE26:1; /* NCF 26 time-out enable */
11609 uint32_t NCFTOE25:1; /* NCF 25 time-out enable */
11610 uint32_t NCFTOE24:1; /* NCF 24 time-out enable */
11611 uint32_t NCFTOE23:1; /* NCF 23 time-out enable */
11612 uint32_t NCFTOE22:1; /* NCF 22 time-out enable */
11613 uint32_t NCFTOE21:1; /* NCF 21 time-out enable */
11614 uint32_t NCFTOE20:1; /* NCF 20 time-out enable */
11615 uint32_t NCFTOE19:1; /* NCF 19 time-out enable */
11616 uint32_t NCFTOE18:1; /* NCF 18 time-out enable */
11617 uint32_t NCFTOE17:1; /* NCF 17 time-out enable */
11618 uint32_t NCFTOE16:1; /* NCF 16 time-out enable */
11619 uint32_t NCFTOE15:1; /* NCF 15 time-out enable */
11620 uint32_t NCFTOE14:1; /* NCF 14 time-out enable */
11621 uint32_t NCFTOE13:1; /* NCF 13 time-out enable */
11622 uint32_t NCFTOE12:1; /* NCF 12 time-out enable */
11623 uint32_t NCFTOE11:1; /* NCF 11 time-out enable */
11624 uint32_t NCFTOE10:1; /* NCF 10 time-out enable */
11625 uint32_t NCFTOE9:1; /* NCF 9 time-out enable */
11626 uint32_t NCFTOE8:1; /* NCF 8 time-out enable */
11627 uint32_t NCFTOE7:1; /* NCF 7 time-out enable */
11628 uint32_t NCFTOE6:1; /* NCF 6 time-out enable */
11629 uint32_t NCFTOE5:1; /* NCF 5 time-out enable */
11630 uint32_t NCFTOE4:1; /* NCF 4 time-out enable */
11631 uint32_t NCFTOE3:1; /* NCF 3 time-out enable */
11632 uint32_t NCFTOE2:1; /* NCF 2 time-out enable */
11633 uint32_t NCFTOE1:1; /* NCF 1 time-out enable */
11634 uint32_t NCFTOE0:1; /* NCF 0 time-out enable */
11635 } B;
11636 } FCCU_NCF_TOE0_32B_tag;
11637
11638 typedef union { /* FCCU NCF Time-out Enable Register 1 */
11639 uint32_t R;
11640 struct {
11641 uint32_t NCFTOE63:1; /* NCF 63 time-out enable */
11642 uint32_t NCFTOE62:1; /* NCF 62 time-out enable */
11643 uint32_t NCFTOE61:1; /* NCF 61 time-out enable */
11644 uint32_t NCFTOE60:1; /* NCF 60 time-out enable */
11645 uint32_t NCFTOE59:1; /* NCF 59 time-out enable */
11646 uint32_t NCFTOE58:1; /* NCF 58 time-out enable */
11647 uint32_t NCFTOE57:1; /* NCF 57 time-out enable */
11648 uint32_t NCFTOE56:1; /* NCF 56 time-out enable */
11649 uint32_t NCFTOE55:1; /* NCF 55 time-out enable */
11650 uint32_t NCFTOE54:1; /* NCF 54 time-out enable */
11651 uint32_t NCFTOE53:1; /* NCF 53 time-out enable */
11652 uint32_t NCFTOE52:1; /* NCF 52 time-out enable */
11653 uint32_t NCFTOE51:1; /* NCF 51 time-out enable */
11654 uint32_t NCFTOE50:1; /* NCF 50 time-out enable */
11655 uint32_t NCFTOE49:1; /* NCF 49 time-out enable */
11656 uint32_t NCFTOE48:1; /* NCF 48 time-out enable */
11657 uint32_t NCFTOE47:1; /* NCF 47 time-out enable */
11658 uint32_t NCFTOE46:1; /* NCF 46 time-out enable */
11659 uint32_t NCFTOE45:1; /* NCF 45 time-out enable */
11660 uint32_t NCFTOE44:1; /* NCF 44 time-out enable */
11661 uint32_t NCFTOE43:1; /* NCF 43 time-out enable */
11662 uint32_t NCFTOE42:1; /* NCF 42 time-out enable */
11663 uint32_t NCFTOE41:1; /* NCF 41 time-out enable */
11664 uint32_t NCFTOE40:1; /* NCF 40 time-out enable */
11665 uint32_t NCFTOE39:1; /* NCF 39 time-out enable */
11666 uint32_t NCFTOE38:1; /* NCF 38 time-out enable */
11667 uint32_t NCFTOE37:1; /* NCF 37 time-out enable */
11668 uint32_t NCFTOE36:1; /* NCF 36 time-out enable */
11669 uint32_t NCFTOE35:1; /* NCF 35 time-out enable */
11670 uint32_t NCFTOE34:1; /* NCF 34 time-out enable */
11671 uint32_t NCFTOE33:1; /* NCF 33 time-out enable */
11672 uint32_t NCFTOE32:1; /* NCF 32 time-out enable */
11673 } B;
11674 } FCCU_NCF_TOE1_32B_tag;
11675
11676 typedef union { /* FCCU NCF Time-out Enable Register 2 */
11677 uint32_t R;
11678 struct {
11679 uint32_t NCFTOE95:1; /* NCF 95 time-out enable */
11680 uint32_t NCFTOE94:1; /* NCF 94 time-out enable */
11681 uint32_t NCFTOE93:1; /* NCF 93 time-out enable */
11682 uint32_t NCFTOE92:1; /* NCF 92 time-out enable */
11683 uint32_t NCFTOE91:1; /* NCF 91 time-out enable */
11684 uint32_t NCFTOE90:1; /* NCF 90 time-out enable */
11685 uint32_t NCFTOE89:1; /* NCF 89 time-out enable */
11686 uint32_t NCFTOE88:1; /* NCF 88 time-out enable */
11687 uint32_t NCFTOE87:1; /* NCF 87 time-out enable */
11688 uint32_t NCFTOE86:1; /* NCF 86 time-out enable */
11689 uint32_t NCFTOE85:1; /* NCF 85 time-out enable */
11690 uint32_t NCFTOE84:1; /* NCF 84 time-out enable */
11691 uint32_t NCFTOE83:1; /* NCF 83 time-out enable */
11692 uint32_t NCFTOE82:1; /* NCF 82 time-out enable */
11693 uint32_t NCFTOE81:1; /* NCF 81 time-out enable */
11694 uint32_t NCFTOE80:1; /* NCF 80 time-out enable */
11695 uint32_t NCFTOE79:1; /* NCF 79 time-out enable */
11696 uint32_t NCFTOE78:1; /* NCF 78 time-out enable */
11697 uint32_t NCFTOE77:1; /* NCF 77 time-out enable */
11698 uint32_t NCFTOE76:1; /* NCF 76 time-out enable */
11699 uint32_t NCFTOE75:1; /* NCF 75 time-out enable */
11700 uint32_t NCFTOE74:1; /* NCF 74 time-out enable */
11701 uint32_t NCFTOE73:1; /* NCF 73 time-out enable */
11702 uint32_t NCFTOE72:1; /* NCF 72 time-out enable */
11703 uint32_t NCFTOE71:1; /* NCF 71 time-out enable */
11704 uint32_t NCFTOE70:1; /* NCF 70 time-out enable */
11705 uint32_t NCFTOE69:1; /* NCF 69 time-out enable */
11706 uint32_t NCFTOE68:1; /* NCF 68 time-out enable */
11707 uint32_t NCFTOE67:1; /* NCF 67 time-out enable */
11708 uint32_t NCFTOE66:1; /* NCF 66 time-out enable */
11709 uint32_t NCFTOE65:1; /* NCF 65 time-out enable */
11710 uint32_t NCFTOE64:1; /* NCF 64 time-out enable */
11711 } B;
11712 } FCCU_NCF_TOE2_32B_tag;
11713
11714 typedef union { /* FCCU NCF Time-out Enable Register 3 */
11715 uint32_t R;
11716 struct {
11717 uint32_t NCFTOE127:1; /* NCF 127 time-out enable */
11718 uint32_t NCFTOE126:1; /* NCF 126 time-out enable */
11719 uint32_t NCFTOE125:1; /* NCF 125 time-out enable */
11720 uint32_t NCFTOE124:1; /* NCF 124 time-out enable */
11721 uint32_t NCFTOE123:1; /* NCF 123 time-out enable */
11722 uint32_t NCFTOE122:1; /* NCF 122 time-out enable */
11723 uint32_t NCFTOE121:1; /* NCF 121 time-out enable */
11724 uint32_t NCFTOE120:1; /* NCF 120 time-out enable */
11725 uint32_t NCFTOE119:1; /* NCF 119 time-out enable */
11726 uint32_t NCFTOE118:1; /* NCF 118 time-out enable */
11727 uint32_t NCFTOE117:1; /* NCF 117 time-out enable */
11728 uint32_t NCFTOE116:1; /* NCF 116 time-out enable */
11729 uint32_t NCFTOE115:1; /* NCF 115 time-out enable */
11730 uint32_t NCFTOE114:1; /* NCF 114 time-out enable */
11731 uint32_t NCFTOE113:1; /* NCF 113 time-out enable */
11732 uint32_t NCFTOE112:1; /* NCF 112 time-out enable */
11733 uint32_t NCFTOE111:1; /* NCF 111 time-out enable */
11734 uint32_t NCFTOE110:1; /* NCF 110 time-out enable */
11735 uint32_t NCFTOE109:1; /* NCF 109 time-out enable */
11736 uint32_t NCFTOE108:1; /* NCF 108 time-out enable */
11737 uint32_t NCFTOE107:1; /* NCF 107 time-out enable */
11738 uint32_t NCFTOE106:1; /* NCF 106 time-out enable */
11739 uint32_t NCFTOE105:1; /* NCF 105 time-out enable */
11740 uint32_t NCFTOE104:1; /* NCF 104 time-out enable */
11741 uint32_t NCFTOE103:1; /* NCF 103 time-out enable */
11742 uint32_t NCFTOE102:1; /* NCF 102 time-out enable */
11743 uint32_t NCFTOE101:1; /* NCF 101 time-out enable */
11744 uint32_t NCFTOE100:1; /* NCF 100 time-out enable */
11745 uint32_t NCFTOE99:1; /* NCF 99 time-out enable */
11746 uint32_t NCFTOE98:1; /* NCF 98 time-out enable */
11747 uint32_t NCFTOE97:1; /* NCF 97 time-out enable */
11748 uint32_t NCFTOE96:1; /* NCF 96 time-out enable */
11749 } B;
11750 } FCCU_NCF_TOE3_32B_tag;
11751
11752 typedef union { /* FCCU_NCF_TO - FCCU NCF Time-out Register */
11753 uint32_t R;
11754 } FCCU_NCF_TO_32B_tag;
11755
11756 typedef union { /* FCCU_CFG_TO - FCCU CFG Timeout Register */
11757 uint32_t R;
11758 struct {
11759 uint32_t:29;
11760 uint32_t TO:3; /* Configuration time-out */
11761 } B;
11762 } FCCU_CFG_TO_32B_tag;
11763
11764 typedef union { /* FCCU_EINOUT - FCCU IO Control Register */
11765 uint32_t R;
11766 struct {
11767 uint32_t:26;
11768 uint32_t EIN1:1; /* Error input 1 */
11769 uint32_t EIN0:1; /* Error input 0 */
11770 uint32_t:2;
11771 uint32_t EOUT1:1; /* Error out 1 */
11772 uint32_t EOUT0:1; /* Error out 0 */
11773 } B;
11774 } FCCU_EINOUT_32B_tag;
11775
11776 typedef union { /* FCCU_STAT - FCCU Status Register */
11777 uint32_t R;
11778 struct {
11779 uint32_t:29;
11780 uint32_t STATUS:3; /* FCCU status */
11781 } B;
11782 } FCCU_STAT_32B_tag;
11783
11784 typedef union { /* FCCU_NAFS - FCCU NA Freeze Status Register */
11785 uint32_t R;
11786 struct {
11787 uint32_t:24;
11788 uint32_t N2AFSTATUS:8; /* Normal to Alarm Frozen Status */
11789 } B;
11790 } FCCU_NAFS_32B_tag;
11791
11792 typedef union { /* FCCU_AFFS - FCCU AF Freeze Status Register */
11793 uint32_t R;
11794 struct {
11795 uint32_t:22;
11796 uint32_t AFFS_SRC:2; /* Fault source */
11797 uint32_t A2AFSTATUS:8; /* Alarm to Fault Frozen Status */
11798 } B;
11799 } FCCU_AFFS_32B_tag;
11800
11801 typedef union { /* FCCU_NFFS - FCCU NF Freeze Status Register */
11802 uint32_t R;
11803 struct {
11804 uint32_t:22;
11805 uint32_t NFFS_SRC:2; /* Fault source */
11806 uint32_t NFFS_NFFS:8; /* Normal to Fault Frozen Status */
11807 } B;
11808 } FCCU_NFFS_32B_tag;
11809
11810 typedef union { /* FCCU_FAFS - FCCU FA Freeze Status Register */
11811 uint32_t R;
11812 struct {
11813 uint32_t:24;
11814 uint32_t FAFS_FAFS:8; /* Fault to Normal Frozen Status */
11815 } B;
11816 } FCCU_FAFS_32B_tag;
11817
11818 typedef union { /* FCCU_SCFS - FCCU SC Freeze Status Register */
11819 uint32_t R;
11820 struct {
11821 uint32_t:30;
11822 uint32_t RCCS1:1; /* RCC1 Status */
11823 uint32_t RCCS0:1; /* RCC0 Status */
11824 } B;
11825 } FCCU_SCFS_32B_tag;
11826
11827 typedef union { /* FCCU_CFF - FCCU CF Fake Register */
11828 uint32_t R;
11829 struct {
11830 uint32_t:25;
11831 uint32_t FCFC:7; /* Fake critical fault code */
11832 } B;
11833 } FCCU_CFF_32B_tag;
11834
11835 typedef union { /* FCCU_NCFF - FCCU NCF Fake Register */
11836 uint32_t R;
11837 struct {
11838 uint32_t:25;
11839 uint32_t FNCFC:7; /* Fake non-critical fault code */
11840 } B;
11841 } FCCU_NCFF_32B_tag;
11842
11843 typedef union { /* FCCU_IRQ_STAT - FCCU IRQ Status Register */
11844 uint32_t R;
11845 struct {
11846 uint32_t:29;
11847 uint32_t NMI_STAT:1; /* NMI Interrupt Status */
11848 uint32_t ALRM_STAT:1; /* Alarm Interrupt Status */
11849 uint32_t CFG_TO_STAT:1; /* Configuration Time-out Status */
11850 } B;
11851 } FCCU_IRQ_STAT_32B_tag;
11852
11853 typedef union { /* FCCU_IRQ_EN - FCCU IRQ Enable Register */
11854 uint32_t R;
11855 struct {
11856 uint32_t:31;
11857 uint32_t CFG_TO_IEN:1; /* Configuration Time-out Interrupt Enable */
11858 } B;
11859 } FCCU_IRQ_EN_32B_tag;
11860
11861 typedef union { /* FCCU_XTMR - FCCU XTMR Register */
11862 uint32_t R;
11863 struct {
11864 uint32_t XTMR_XTMR:32; /* Alarm/Watchdog/safe request timer */
11865 } B;
11866 } FCCU_XTMR_32B_tag;
11867
11868 typedef union { /* FCCU_MCS - FCCU MCS Register */
11869 uint32_t R;
11870 struct {
11871 uint32_t VL3:1; /* Valid */
11872 uint32_t FS3:1; /* Fault Status */
11873 uint32_t:2;
11874 uint32_t MCS3:4; /* Magic Carpet oldest state */
11875 uint32_t VL2:1; /* Valid */
11876 uint32_t FS2:1; /* Fault Status */
11877 uint32_t:2;
11878 uint32_t MCS2:4; /* Magic Carpet previous-previous state */
11879 uint32_t VL1:1; /* Valid */
11880 uint32_t FS1:1; /* Fault Status */
11881 uint32_t:2;
11882 uint32_t MCS1:4; /* Magic Carpet previous state */
11883 uint32_t VL0:1; /* Valid */
11884 uint32_t FS0:1; /* Fault Status */
11885 uint32_t:2;
11886 uint32_t MCS0:4; /* Magic Carpet latest state */
11887 } B;
11888 } FCCU_MCS_32B_tag;
11889
11890
11891 /* Register layout for generated register(s) CF_CFG... */
11892
11893 typedef union { /* */
11894 uint32_t R;
11895 } FCCU_CF_CFG_32B_tag;
11896
11897
11898 /* Register layout for generated register(s) NCF_CFG... */
11899
11900 typedef union { /* */
11901 uint32_t R;
11902 } FCCU_NCF_CFG_32B_tag;
11903
11904
11905 /* Register layout for generated register(s) CFS_CFG... */
11906
11907 typedef union { /* */
11908 uint32_t R;
11909 } FCCU_CFS_CFG_32B_tag;
11910
11911
11912 /* Register layout for generated register(s) NCFS_CFG... */
11913
11914 typedef union { /* */
11915 uint32_t R;
11916 } FCCU_NCFS_CFG_32B_tag;
11917
11918
11919 /* Register layout for generated register(s) CFS... */
11920
11921 typedef union { /* */
11922 uint32_t R;
11923 } FCCU_CFS_32B_tag;
11924
11925
11926 /* Register layout for generated register(s) NCFS... */
11927
11928 typedef union { /* */
11929 uint32_t R;
11930 } FCCU_NCFS_32B_tag;
11931
11932
11933 /* Register layout for generated register(s) NCFE... */
11934
11935 typedef union { /* */
11936 uint32_t R;
11937 } FCCU_NCFE_32B_tag;
11938
11939
11940 /* Register layout for generated register(s) NCF_TOE... */
11941
11942 typedef union { /* */
11943 uint32_t R;
11944 } FCCU_NCF_TOE_32B_tag;
11945
11946
11947
11948 typedef struct FCCU_struct_tag { /* start of FCCU_tag */
11949 /* FCCU Control Register */
11950 FCCU_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */
11951 /* FCCU CTRL Key Register */
11952 FCCU_CTRLK_32B_tag CTRLK; /* offset: 0x0004 size: 32 bit */
11953 /* FCCU Configuration Register */
11954 FCCU_CFG_32B_tag CFG; /* offset: 0x0008 size: 32 bit */
11955 union {
11956 FCCU_CF_CFG_32B_tag CF_CFG[4]; /* offset: 0x000C (0x0004 x 4) */
11957
11958 struct {
11959 /* FCCU CF Configuration Register 0 */
11960 FCCU_CF_CFG0_32B_tag CF_CFG0; /* offset: 0x000C size: 32 bit */
11961 /* FCCU CF Configuration Register 1 */
11962 FCCU_CF_CFG1_32B_tag CF_CFG1; /* offset: 0x0010 size: 32 bit */
11963 /* FCCU CF Configuration Register 2 */
11964 FCCU_CF_CFG2_32B_tag CF_CFG2; /* offset: 0x0014 size: 32 bit */
11965 /* FCCU CF Configuration Register 3 */
11966 FCCU_CF_CFG3_32B_tag CF_CFG3; /* offset: 0x0018 size: 32 bit */
11967 };
11968
11969 };
11970 union {
11971 FCCU_NCF_CFG_32B_tag NCF_CFG[4]; /* offset: 0x001C (0x0004 x 4) */
11972
11973 struct {
11974 /* FCCU NCF Configuration Register 0 */
11975 FCCU_NCF_CFG0_32B_tag NCF_CFG0; /* offset: 0x001C size: 32 bit */
11976 /* FCCU NCF Configuration Register 1 */
11977 FCCU_NCF_CFG1_32B_tag NCF_CFG1; /* offset: 0x0020 size: 32 bit */
11978 /* FCCU NCF Configuration Register 2 */
11979 FCCU_NCF_CFG2_32B_tag NCF_CFG2; /* offset: 0x0024 size: 32 bit */
11980 /* FCCU NCF Configuration Register 3 */
11981 FCCU_NCF_CFG3_32B_tag NCF_CFG3; /* offset: 0x0028 size: 32 bit */
11982 };
11983
11984 };
11985 union {
11986 FCCU_CFS_CFG_32B_tag CFS_CFG[8]; /* offset: 0x002C (0x0004 x 8) */
11987
11988 struct {
11989 /* FCCU CFS Configuration Register 0 */
11990 FCCU_CFS_CFG0_32B_tag CFS_CFG0; /* offset: 0x002C size: 32 bit */
11991 /* FCCU CFS Configuration Register 1 */
11992 FCCU_CFS_CFG1_32B_tag CFS_CFG1; /* offset: 0x0030 size: 32 bit */
11993 /* FCCU CFS Configuration Register 2 */
11994 FCCU_CFS_CFG2_32B_tag CFS_CFG2; /* offset: 0x0034 size: 32 bit */
11995 /* FCCU CFS Configuration Register 3 */
11996 FCCU_CFS_CFG3_32B_tag CFS_CFG3; /* offset: 0x0038 size: 32 bit */
11997 /* FCCU CFS Configuration Register 4 */
11998 FCCU_CFS_CFG4_32B_tag CFS_CFG4; /* offset: 0x003C size: 32 bit */
11999 /* FCCU CFS Configuration Register 5 */
12000 FCCU_CFS_CFG5_32B_tag CFS_CFG5; /* offset: 0x0040 size: 32 bit */
12001 /* FCCU CFS Configuration Register 6 */
12002 FCCU_CFS_CFG6_32B_tag CFS_CFG6; /* offset: 0x0044 size: 32 bit */
12003 /* FCCU CFS Configuration Register 7 */
12004 FCCU_CFS_CFG7_32B_tag CFS_CFG7; /* offset: 0x0048 size: 32 bit */
12005 };
12006
12007 };
12008 union {
12009 FCCU_NCFS_CFG_32B_tag NCFS_CFG[8]; /* offset: 0x004C (0x0004 x 8) */
12010
12011 struct {
12012 /* FCCU NCFS Configuration Register 0 */
12013 FCCU_NCFS_CFG0_32B_tag NCFS_CFG0; /* offset: 0x004C size: 32 bit */
12014 /* FCCU NCFS Configuration Register 1 */
12015 FCCU_NCFS_CFG1_32B_tag NCFS_CFG1; /* offset: 0x0050 size: 32 bit */
12016 /* FCCU NCFS Configuration Register 2 */
12017 FCCU_NCFS_CFG2_32B_tag NCFS_CFG2; /* offset: 0x0054 size: 32 bit */
12018 /* FCCU NCFS Configuration Register 3 */
12019 FCCU_NCFS_CFG3_32B_tag NCFS_CFG3; /* offset: 0x0058 size: 32 bit */
12020 /* FCCU NCFS Configuration Register 4 */
12021 FCCU_NCFS_CFG4_32B_tag NCFS_CFG4; /* offset: 0x005C size: 32 bit */
12022 /* FCCU NCFS Configuration Register 5 */
12023 FCCU_NCFS_CFG5_32B_tag NCFS_CFG5; /* offset: 0x0060 size: 32 bit */
12024 /* FCCU NCFS Configuration Register 6 */
12025 FCCU_NCFS_CFG6_32B_tag NCFS_CFG6; /* offset: 0x0064 size: 32 bit */
12026 /* FCCU NCFS Configuration Register 7 */
12027 FCCU_NCFS_CFG7_32B_tag NCFS_CFG7; /* offset: 0x0068 size: 32 bit */
12028 };
12029
12030 };
12031 union {
12032 FCCU_CFS_32B_tag CFS[4]; /* offset: 0x006C (0x0004 x 4) */
12033
12034 struct {
12035 /* FCCU CF Status Register 0 */
12036 FCCU_CFS0_32B_tag CFS0; /* offset: 0x006C size: 32 bit */
12037 /* FCCU CF Status Register 1 */
12038 FCCU_CFS1_32B_tag CFS1; /* offset: 0x0070 size: 32 bit */
12039 /* FCCU CF Status Register 2 */
12040 FCCU_CFS2_32B_tag CFS2; /* offset: 0x0074 size: 32 bit */
12041 /* FCCU CF Status Register 3 */
12042 FCCU_CFS3_32B_tag CFS3; /* offset: 0x0078 size: 32 bit */
12043 };
12044
12045 };
12046 /* FCCU_CFK - FCCU CF Key Register */
12047 FCCU_CFK_32B_tag CFK; /* offset: 0x007C size: 32 bit */
12048 union {
12049 FCCU_NCFS_32B_tag NCFS[4]; /* offset: 0x0080 (0x0004 x 4) */
12050
12051 struct {
12052 /* FCCU NCF Status Register 0 */
12053 FCCU_NCFS0_32B_tag NCFS0; /* offset: 0x0080 size: 32 bit */
12054 /* FCCU NCF Status Register 1 */
12055 FCCU_NCFS1_32B_tag NCFS1; /* offset: 0x0084 size: 32 bit */
12056 /* FCCU NCF Status Register 2 */
12057 FCCU_NCFS2_32B_tag NCFS2; /* offset: 0x0088 size: 32 bit */
12058 /* FCCU NCF Status Register 3 */
12059 FCCU_NCFS3_32B_tag NCFS3; /* offset: 0x008C size: 32 bit */
12060 };
12061
12062 };
12063 /* FCCU_NCFK - FCCU NCF Key Register */
12064 FCCU_NCFK_32B_tag NCFK; /* offset: 0x0090 size: 32 bit */
12065 union {
12066 FCCU_NCFE_32B_tag NCFE[4]; /* offset: 0x0094 (0x0004 x 4) */
12067
12068 struct {
12069 /* FCCU NCF Enable Register 0 */
12070 FCCU_NCFE0_32B_tag NCFE0; /* offset: 0x0094 size: 32 bit */
12071 /* FCCU NCF Enable Register 1 */
12072 FCCU_NCFE1_32B_tag NCFE1; /* offset: 0x0098 size: 32 bit */
12073 /* FCCU NCF Enable Register 2 */
12074 FCCU_NCFE2_32B_tag NCFE2; /* offset: 0x009C size: 32 bit */
12075 /* FCCU NCF Enable Register 3 */
12076 FCCU_NCFE3_32B_tag NCFE3; /* offset: 0x00A0 size: 32 bit */
12077 };
12078
12079 };
12080 union {
12081 FCCU_NCF_TOE_32B_tag NCF_TOE[4]; /* offset: 0x00A4 (0x0004 x 4) */
12082
12083 struct {
12084 /* FCCU NCF Time-out Enable Register 0 */
12085 FCCU_NCF_TOE0_32B_tag NCF_TOE0; /* offset: 0x00A4 size: 32 bit */
12086 /* FCCU NCF Time-out Enable Register 1 */
12087 FCCU_NCF_TOE1_32B_tag NCF_TOE1; /* offset: 0x00A8 size: 32 bit */
12088 /* FCCU NCF Time-out Enable Register 2 */
12089 FCCU_NCF_TOE2_32B_tag NCF_TOE2; /* offset: 0x00AC size: 32 bit */
12090 /* FCCU NCF Time-out Enable Register 3 */
12091 FCCU_NCF_TOE3_32B_tag NCF_TOE3; /* offset: 0x00B0 size: 32 bit */
12092 };
12093
12094 };
12095 /* FCCU_NCF_TO - FCCU NCF Time-out Register */
12096 FCCU_NCF_TO_32B_tag NCF_TO; /* offset: 0x00B4 size: 32 bit */
12097 /* FCCU_CFG_TO - FCCU CFG Timeout Register */
12098 FCCU_CFG_TO_32B_tag CFG_TO; /* offset: 0x00B8 size: 32 bit */
12099 /* FCCU_EINOUT - FCCU IO Control Register */
12100 FCCU_EINOUT_32B_tag EINOUT; /* offset: 0x00BC size: 32 bit */
12101 /* FCCU_STAT - FCCU Status Register */
12102 FCCU_STAT_32B_tag STAT; /* offset: 0x00C0 size: 32 bit */
12103 /* FCCU_NAFS - FCCU NA Freeze Status Register */
12104 FCCU_NAFS_32B_tag NAFS; /* offset: 0x00C4 size: 32 bit */
12105 /* FCCU_AFFS - FCCU AF Freeze Status Register */
12106 FCCU_AFFS_32B_tag AFFS; /* offset: 0x00C8 size: 32 bit */
12107 /* FCCU_NFFS - FCCU NF Freeze Status Register */
12108 FCCU_NFFS_32B_tag NFFS; /* offset: 0x00CC size: 32 bit */
12109 /* FCCU_FAFS - FCCU FA Freeze Status Register */
12110 FCCU_FAFS_32B_tag FAFS; /* offset: 0x00D0 size: 32 bit */
12111 /* FCCU_SCFS - FCCU SC Freeze Status Register */
12112 FCCU_SCFS_32B_tag SCFS; /* offset: 0x00D4 size: 32 bit */
12113 /* FCCU_CFF - FCCU CF Fake Register */
12114 FCCU_CFF_32B_tag CFF; /* offset: 0x00D8 size: 32 bit */
12115 /* FCCU_NCFF - FCCU NCF Fake Register */
12116 FCCU_NCFF_32B_tag NCFF; /* offset: 0x00DC size: 32 bit */
12117 /* FCCU_IRQ_STAT - FCCU IRQ Status Register */
12118 FCCU_IRQ_STAT_32B_tag IRQ_STAT; /* offset: 0x00E0 size: 32 bit */
12119 /* FCCU_IRQ_EN - FCCU IRQ Enable Register */
12120 FCCU_IRQ_EN_32B_tag IRQ_EN; /* offset: 0x00E4 size: 32 bit */
12121 /* FCCU_XTMR - FCCU XTMR Register */
12122 FCCU_XTMR_32B_tag XTMR; /* offset: 0x00E8 size: 32 bit */
12123 /* FCCU_MCS - FCCU MCS Register */
12124 FCCU_MCS_32B_tag MCS; /* offset: 0x00EC size: 32 bit */
12125 } FCCU_tag;
12126
12127
12128#define FCCU (*(volatile FCCU_tag *) 0xFFE6C000UL)
12129
12130
12131
12132/****************************************************************/
12133/* */
12134/* Module: SGENDIG */
12135/* */
12136/****************************************************************/
12137
12138 typedef union { /* SGENDIG_CTRL - SGENDIG Control Register */
12139 uint32_t R;
12140 struct {
12141 uint32_t LDOS:1; /* Operation Status */
12142 uint32_t IOAMPL:5; /* Define the AMPLitude value on I/O pad */
12143 uint32_t:2;
12144 uint32_t SEMASK:1; /* Sine wave generator Error MASK interrupt register */
12145 uint32_t:5;
12146 uint32_t S0H1:1; /* Operation Status */
12147 uint32_t PDS:1; /* Operation Status */
12148 uint32_t IOFREQ:16; /* Define the FREQuency value on I/O pad */
12149 } B;
12150 } SGENDIG_CTRL_32B_tag;
12151
12152 typedef union { /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */
12153 uint32_t R;
12154 struct {
12155 uint32_t:8;
12156 uint32_t SERR:1; /* Sine wave generator Error bit */
12157 uint32_t:3;
12158 uint32_t FERR:1; /* Sine wave generator Force Error bit */
12159 uint32_t:19;
12160 } B;
12161 } SGENDIG_IRQE_32B_tag;
12162
12163
12164
12165 typedef struct SGENDIG_struct_tag { /* start of SGENDIG_tag */
12166 /* SGENDIG_CTRL - SGENDIG Control Register */
12167 SGENDIG_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */
12168 /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */
12169 SGENDIG_IRQE_32B_tag IRQE; /* offset: 0x0004 size: 32 bit */
12170 } SGENDIG_tag;
12171
12172
12173#define SGENDIG (*(volatile SGENDIG_tag *) 0xFFE78000UL)
12174
12175
12176
12177/****************************************************************/
12178/* */
12179/* Module: PBRIDGE */
12180/* */
12181/****************************************************************/
12182
12183 typedef union { /* MPROT - Master Privilege Registers */
12184 uint32_t R;
12185 struct {
12186 uint32_t MPROT0_MBW:1; /* Master 0 Buffer Writes */
12187 uint32_t MPROT0_MTR:1; /* Master 0 Trusted for Reads */
12188 uint32_t MPROT0_MTW:1; /* Master 0 Trusted for Writes */
12189 uint32_t MPROT0_MPL:1; /* Master 0 Priviledge Level */
12190 uint32_t MPROT1_MBW:1; /* Master 1 Buffer Writes */
12191 uint32_t MPROT1_MTR:1; /* Master 1 Trusted for Reads */
12192 uint32_t MPROT1_MTW:1; /* Master 1 Trusted for Writes */
12193 uint32_t MPROT1_MPL:1; /* Master 1 Priviledge Level */
12194 uint32_t MPROT2_MBW:1; /* Master 2 Buffer Writes */
12195 uint32_t MPROT2_MTR:1; /* Master 2 Trusted for Reads */
12196 uint32_t MPROT2_MTW:1; /* Master 2 Trusted for Writes */
12197 uint32_t MPROT2_MPL:1; /* Master 2 Priviledge Level */
12198 uint32_t MPROT3_MBW:1; /* Master 3 Buffer Writes */
12199 uint32_t MPROT3_MTR:1; /* Master 3 Trusted for Reads */
12200 uint32_t MPROT3_MTW:1; /* Master 3 Trusted for Writes */
12201 uint32_t MPROT3_MPL:1; /* Master 3 Priviledge Level */
12202 uint32_t MPROT4_MBW:1; /* Master 4 Buffer Writes */
12203 uint32_t MPROT4_MTR:1; /* Master 4 Trusted for Reads */
12204 uint32_t MPROT4_MTW:1; /* Master 4 Trusted for Writes */
12205 uint32_t MPROT4_MPL:1; /* Master 4 Priviledge Level */
12206 uint32_t MPROT5_MBW:1; /* Master 5 Buffer Writes */
12207 uint32_t MPROT5_MTR:1; /* Master 5 Trusted for Reads */
12208 uint32_t MPROT5_MTW:1; /* Master 5 Trusted for Writes */
12209 uint32_t MPROT5_MPL:1; /* Master 5 Priviledge Level */
12210 uint32_t MPROT6_MBW:1; /* Master 6 Buffer Writes */
12211 uint32_t MPROT6_MTR:1; /* Master 6 Trusted for Reads */
12212 uint32_t MPROT6_MTW:1; /* Master 6 Trusted for Writes */
12213 uint32_t MPROT6_MPL:1; /* Master 6 Priviledge Level */
12214 uint32_t MPROT7_MBW:1; /* Master 7 Buffer Writes */
12215 uint32_t MPROT7_MTR:1; /* Master 7 Trusted for Reads */
12216 uint32_t MPROT7_MTW:1; /* Master 7 Trusted for Writes */
12217 uint32_t MPROT7_MPL:1; /* Master 7 Priviledge Level */
12218 } B;
12219 } PBRIDGE_MPROT_32B_tag;
12220
12221 typedef union { /* PACR0_7 - Peripheral Access Control Registers */
12222 uint32_t R;
12223 struct {
12224 uint32_t PACR0_BW:1; /* Buffer Writes */
12225 uint32_t PACR0_SP:1; /* Supervisor Protect */
12226 uint32_t PACR0_WP:1; /* Write Protect */
12227 uint32_t PACR0_TP:1; /* Trusted Protect */
12228 uint32_t PACR1_BW:1; /* Buffer Writes */
12229 uint32_t PACR1_SP:1; /* Supervisor Protect */
12230 uint32_t PACR1_WP:1; /* Write Protect */
12231 uint32_t PACR1_TP:1; /* Trusted Protect */
12232 uint32_t PACR2_BW:1; /* Buffer Writes */
12233 uint32_t PACR2_SP:1; /* Supervisor Protect */
12234 uint32_t PACR2_WP:1; /* Write Protect */
12235 uint32_t PACR2_TP:1; /* Trusted Protect */
12236 uint32_t PACR3_BW:1; /* Buffer Writes */
12237 uint32_t PACR3_SP:1; /* Supervisor Protect */
12238 uint32_t PACR3_WP:1; /* Write Protect */
12239 uint32_t PACR3_TP:1; /* Trusted Protect */
12240 uint32_t PACR4_BW:1; /* Buffer Writes */
12241 uint32_t PACR4_SP:1; /* Supervisor Protect */
12242 uint32_t PACR4_WP:1; /* Write Protect */
12243 uint32_t PACR4_TP:1; /* Trusted Protect */
12244 uint32_t PACR5_BW:1; /* Buffer Writes */
12245 uint32_t PACR5_SP:1; /* Supervisor Protect */
12246 uint32_t PACR5_WP:1; /* Write Protect */
12247 uint32_t PACR5_TP:1; /* Trusted Protect */
12248 uint32_t PACR6_BW:1; /* Buffer Writes */
12249 uint32_t PACR6_SP:1; /* Supervisor Protect */
12250 uint32_t PACR6_WP:1; /* Write Protect */
12251 uint32_t PACR6_TP:1; /* Trusted Protect */
12252 uint32_t PACR7_BW:1; /* Buffer Writes */
12253 uint32_t PACR7_SP:1; /* Supervisor Protect */
12254 uint32_t PACR7_WP:1; /* Write Protect */
12255 uint32_t PACR7_TP:1; /* Trusted Protect */
12256 } B;
12257 } PBRIDGE_PACR0_7_32B_tag;
12258
12259 typedef union { /* PACR8_15 - Peripheral Access Control Registers */
12260 uint32_t R;
12261 struct {
12262 uint32_t PACR8_BW:1; /* Buffer Writes */
12263 uint32_t PACR8_SP:1; /* Supervisor Protect */
12264 uint32_t PACR8_WP:1; /* Write Protect */
12265 uint32_t PACR8_TP:1; /* Trusted Protect */
12266 uint32_t PACR9_BW:1; /* Buffer Writes */
12267 uint32_t PACR9_SP:1; /* Supervisor Protect */
12268 uint32_t PACR9_WP:1; /* Write Protect */
12269 uint32_t PACR9_TP:1; /* Trusted Protect */
12270 uint32_t PACR10_BW:1; /* Buffer Writes */
12271 uint32_t PACR10_SP:1; /* Supervisor Protect */
12272 uint32_t PACR10_WP:1; /* Write Protect */
12273 uint32_t PACR10_TP:1; /* Trusted Protect */
12274 uint32_t PACR11_BW:1; /* Buffer Writes */
12275 uint32_t PACR11_SP:1; /* Supervisor Protect */
12276 uint32_t PACR11_WP:1; /* Write Protect */
12277 uint32_t PACR11_TP:1; /* Trusted Protect */
12278 uint32_t PACR12_BW:1; /* Buffer Writes */
12279 uint32_t PACR12_SP:1; /* Supervisor Protect */
12280 uint32_t PACR12_WP:1; /* Write Protect */
12281 uint32_t PACR12_TP:1; /* Trusted Protect */
12282 uint32_t PACR13_BW:1; /* Buffer Writes */
12283 uint32_t PACR13_SP:1; /* Supervisor Protect */
12284 uint32_t PACR13_WP:1; /* Write Protect */
12285 uint32_t PACR13_TP:1; /* Trusted Protect */
12286 uint32_t PACR14_BW:1; /* Buffer Writes */
12287 uint32_t PACR14_SP:1; /* Supervisor Protect */
12288 uint32_t PACR14_WP:1; /* Write Protect */
12289 uint32_t PACR14_TP:1; /* Trusted Protect */
12290 uint32_t PACR15_BW:1; /* Buffer Writes */
12291 uint32_t PACR15_SP:1; /* Supervisor Protect */
12292 uint32_t PACR15_WP:1; /* Write Protect */
12293 uint32_t PACR15_TP:1; /* Trusted Protect */
12294 } B;
12295 } PBRIDGE_PACR8_15_32B_tag;
12296
12297 typedef union { /* PACR16_23 - Peripheral Access Control Registers */
12298 uint32_t R;
12299 struct {
12300 uint32_t PACR16_BW:1; /* Buffer Writes */
12301 uint32_t PACR16_SP:1; /* Supervisor Protect */
12302 uint32_t PACR16_WP:1; /* Write Protect */
12303 uint32_t PACR16_TP:1; /* Trusted Protect */
12304 uint32_t PACR17_BW:1; /* Buffer Writes */
12305 uint32_t PACR17_SP:1; /* Supervisor Protect */
12306 uint32_t PACR17_WP:1; /* Write Protect */
12307 uint32_t PACR17_TP:1; /* Trusted Protect */
12308 uint32_t PACR18_BW:1; /* Buffer Writes */
12309 uint32_t PACR18_SP:1; /* Supervisor Protect */
12310 uint32_t PACR18_WP:1; /* Write Protect */
12311 uint32_t PACR18_TP:1; /* Trusted Protect */
12312 uint32_t PACR19_BW:1; /* Buffer Writes */
12313 uint32_t PACR19_SP:1; /* Supervisor Protect */
12314 uint32_t PACR19_WP:1; /* Write Protect */
12315 uint32_t PACR19_TP:1; /* Trusted Protect */
12316 uint32_t PACR20_BW:1; /* Buffer Writes */
12317 uint32_t PACR20_SP:1; /* Supervisor Protect */
12318 uint32_t PACR20_WP:1; /* Write Protect */
12319 uint32_t PACR20_TP:1; /* Trusted Protect */
12320 uint32_t PACR21_BW:1; /* Buffer Writes */
12321 uint32_t PACR21_SP:1; /* Supervisor Protect */
12322 uint32_t PACR21_WP:1; /* Write Protect */
12323 uint32_t PACR21_TP:1; /* Trusted Protect */
12324 uint32_t PACR22_BW:1; /* Buffer Writes */
12325 uint32_t PACR22_SP:1; /* Supervisor Protect */
12326 uint32_t PACR22_WP:1; /* Write Protect */
12327 uint32_t PACR22_TP:1; /* Trusted Protect */
12328 uint32_t PACR23_BW:1; /* Buffer Writes */
12329 uint32_t PACR23_SP:1; /* Supervisor Protect */
12330 uint32_t PACR23_WP:1; /* Write Protect */
12331 uint32_t PACR23_TP:1; /* Trusted Protect */
12332 } B;
12333 } PBRIDGE_PACR16_23_32B_tag;
12334
12335 typedef union { /* PACR24_31 - Peripheral Access Control Registers */
12336 uint32_t R;
12337 struct {
12338 uint32_t PACR24_BW:1; /* Buffer Writes */
12339 uint32_t PACR24_SP:1; /* Supervisor Protect */
12340 uint32_t PACR24_WP:1; /* Write Protect */
12341 uint32_t PACR24_TP:1; /* Trusted Protect */
12342 uint32_t PACR25_BW:1; /* Buffer Writes */
12343 uint32_t PACR25_SP:1; /* Supervisor Protect */
12344 uint32_t PACR25_WP:1; /* Write Protect */
12345 uint32_t PACR25_TP:1; /* Trusted Protect */
12346 uint32_t PACR26_BW:1; /* Buffer Writes */
12347 uint32_t PACR26_SP:1; /* Supervisor Protect */
12348 uint32_t PACR26_WP:1; /* Write Protect */
12349 uint32_t PACR26_TP:1; /* Trusted Protect */
12350 uint32_t PACR27_BW:1; /* Buffer Writes */
12351 uint32_t PACR27_SP:1; /* Supervisor Protect */
12352 uint32_t PACR27_WP:1; /* Write Protect */
12353 uint32_t PACR27_TP:1; /* Trusted Protect */
12354 uint32_t PACR28_BW:1; /* Buffer Writes */
12355 uint32_t PACR28_SP:1; /* Supervisor Protect */
12356 uint32_t PACR28_WP:1; /* Write Protect */
12357 uint32_t PACR28_TP:1; /* Trusted Protect */
12358 uint32_t PACR29_BW:1; /* Buffer Writes */
12359 uint32_t PACR29_SP:1; /* Supervisor Protect */
12360 uint32_t PACR29_WP:1; /* Write Protect */
12361 uint32_t PACR29_TP:1; /* Trusted Protect */
12362 uint32_t PACR30_BW:1; /* Buffer Writes */
12363 uint32_t PACR30_SP:1; /* Supervisor Protect */
12364 uint32_t PACR30_WP:1; /* Write Protect */
12365 uint32_t PACR30_TP:1; /* Trusted Protect */
12366 uint32_t PACR31_BW:1; /* Buffer Writes */
12367 uint32_t PACR31_SP:1; /* Supervisor Protect */
12368 uint32_t PACR31_WP:1; /* Write Protect */
12369 uint32_t PACR31_TP:1; /* Trusted Protect */
12370 } B;
12371 } PBRIDGE_PACR24_31_32B_tag;
12372
12373 typedef union { /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */
12374 uint32_t R;
12375 struct {
12376 uint32_t OPACR0_BW:1; /* Buffer Writes */
12377 uint32_t OPACR0_SP:1; /* Supervisor Protect */
12378 uint32_t OPACR0_WP:1; /* Write Protect */
12379 uint32_t OPACR0_TP:1; /* Trusted Protect */
12380 uint32_t OPACR1_BW:1; /* Buffer Writes */
12381 uint32_t OPACR1_SP:1; /* Supervisor Protect */
12382 uint32_t OPACR1_WP:1; /* Write Protect */
12383 uint32_t OPACR1_TP:1; /* Trusted Protect */
12384 uint32_t OPACR2_BW:1; /* Buffer Writes */
12385 uint32_t OPACR2_SP:1; /* Supervisor Protect */
12386 uint32_t OPACR2_WP:1; /* Write Protect */
12387 uint32_t OPACR2_TP:1; /* Trusted Protect */
12388 uint32_t OPACR3_BW:1; /* Buffer Writes */
12389 uint32_t OPACR3_SP:1; /* Supervisor Protect */
12390 uint32_t OPACR3_WP:1; /* Write Protect */
12391 uint32_t OPACR3_TP:1; /* Trusted Protect */
12392 uint32_t OPACR4_BW:1; /* Buffer Writes */
12393 uint32_t OPACR4_SP:1; /* Supervisor Protect */
12394 uint32_t OPACR4_WP:1; /* Write Protect */
12395 uint32_t OPACR4_TP:1; /* Trusted Protect */
12396 uint32_t OPACR5_BW:1; /* Buffer Writes */
12397 uint32_t OPACR5_SP:1; /* Supervisor Protect */
12398 uint32_t OPACR5_WP:1; /* Write Protect */
12399 uint32_t OPACR5_TP:1; /* Trusted Protect */
12400 uint32_t OPACR6_BW:1; /* Buffer Writes */
12401 uint32_t OPACR6_SP:1; /* Supervisor Protect */
12402 uint32_t OPACR6_WP:1; /* Write Protect */
12403 uint32_t OPACR6_TP:1; /* Trusted Protect */
12404 uint32_t OPACR7_BW:1; /* Buffer Writes */
12405 uint32_t OPACR7_SP:1; /* Supervisor Protect */
12406 uint32_t OPACR7_WP:1; /* Write Protect */
12407 uint32_t OPACR7_TP:1; /* Trusted Protect */
12408 } B;
12409 } PBRIDGE_OPACR0_7_32B_tag;
12410
12411 typedef union { /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */
12412 uint32_t R;
12413 struct {
12414 uint32_t OPACR8_BW:1; /* Buffer Writes */
12415 uint32_t OPACR8_SP:1; /* Supervisor Protect */
12416 uint32_t OPACR8_WP:1; /* Write Protect */
12417 uint32_t OPACR8_TP:1; /* Trusted Protect */
12418 uint32_t OPACR9_BW:1; /* Buffer Writes */
12419 uint32_t OPACR9_SP:1; /* Supervisor Protect */
12420 uint32_t OPACR9_WP:1; /* Write Protect */
12421 uint32_t OPACR9_TP:1; /* Trusted Protect */
12422 uint32_t OPACR10_BW:1; /* Buffer Writes */
12423 uint32_t OPACR10_SP:1; /* Supervisor Protect */
12424 uint32_t OPACR10_WP:1; /* Write Protect */
12425 uint32_t OPACR10_TP:1; /* Trusted Protect */
12426 uint32_t OPACR11_BW:1; /* Buffer Writes */
12427 uint32_t OPACR11_SP:1; /* Supervisor Protect */
12428 uint32_t OPACR11_WP:1; /* Write Protect */
12429 uint32_t OPACR11_TP:1; /* Trusted Protect */
12430 uint32_t OPACR12_BW:1; /* Buffer Writes */
12431 uint32_t OPACR12_SP:1; /* Supervisor Protect */
12432 uint32_t OPACR12_WP:1; /* Write Protect */
12433 uint32_t OPACR12_TP:1; /* Trusted Protect */
12434 uint32_t OPACR13_BW:1; /* Buffer Writes */
12435 uint32_t OPACR13_SP:1; /* Supervisor Protect */
12436 uint32_t OPACR13_WP:1; /* Write Protect */
12437 uint32_t OPACR13_TP:1; /* Trusted Protect */
12438 uint32_t OPACR14_BW:1; /* Buffer Writes */
12439 uint32_t OPACR14_SP:1; /* Supervisor Protect */
12440 uint32_t OPACR14_WP:1; /* Write Protect */
12441 uint32_t OPACR14_TP:1; /* Trusted Protect */
12442 uint32_t OPACR15_BW:1; /* Buffer Writes */
12443 uint32_t OPACR15_SP:1; /* Supervisor Protect */
12444 uint32_t OPACR15_WP:1; /* Write Protect */
12445 uint32_t OPACR15_TP:1; /* Trusted Protect */
12446 } B;
12447 } PBRIDGE_OPACR8_15_32B_tag;
12448
12449 typedef union { /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */
12450 uint32_t R;
12451 struct {
12452 uint32_t OPACR16_BW:1; /* Buffer Writes */
12453 uint32_t OPACR16_SP:1; /* Supervisor Protect */
12454 uint32_t OPACR16_WP:1; /* Write Protect */
12455 uint32_t OPACR16_TP:1; /* Trusted Protect */
12456 uint32_t OPACR17_BW:1; /* Buffer Writes */
12457 uint32_t OPACR17_SP:1; /* Supervisor Protect */
12458 uint32_t OPACR17_WP:1; /* Write Protect */
12459 uint32_t OPACR17_TP:1; /* Trusted Protect */
12460 uint32_t OPACR18_BW:1; /* Buffer Writes */
12461 uint32_t OPACR18_SP:1; /* Supervisor Protect */
12462 uint32_t OPACR18_WP:1; /* Write Protect */
12463 uint32_t OPACR18_TP:1; /* Trusted Protect */
12464 uint32_t OPACR19_BW:1; /* Buffer Writes */
12465 uint32_t OPACR19_SP:1; /* Supervisor Protect */
12466 uint32_t OPACR19_WP:1; /* Write Protect */
12467 uint32_t OPACR19_TP:1; /* Trusted Protect */
12468 uint32_t OPACR20_BW:1; /* Buffer Writes */
12469 uint32_t OPACR20_SP:1; /* Supervisor Protect */
12470 uint32_t OPACR20_WP:1; /* Write Protect */
12471 uint32_t OPACR20_TP:1; /* Trusted Protect */
12472 uint32_t OPACR21_BW:1; /* Buffer Writes */
12473 uint32_t OPACR21_SP:1; /* Supervisor Protect */
12474 uint32_t OPACR21_WP:1; /* Write Protect */
12475 uint32_t OPACR21_TP:1; /* Trusted Protect */
12476 uint32_t OPACR22_BW:1; /* Buffer Writes */
12477 uint32_t OPACR22_SP:1; /* Supervisor Protect */
12478 uint32_t OPACR22_WP:1; /* Write Protect */
12479 uint32_t OPACR22_TP:1; /* Trusted Protect */
12480 uint32_t OPACR23_BW:1; /* Buffer Writes */
12481 uint32_t OPACR23_SP:1; /* Supervisor Protect */
12482 uint32_t OPACR23_WP:1; /* Write Protect */
12483 uint32_t OPACR23_TP:1; /* Trusted Protect */
12484 } B;
12485 } PBRIDGE_OPACR16_23_32B_tag;
12486
12487 typedef union { /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */
12488 uint32_t R;
12489 struct {
12490 uint32_t OPACR24_BW:1; /* Buffer Writes */
12491 uint32_t OPACR24_SP:1; /* Supervisor Protect */
12492 uint32_t OPACR24_WP:1; /* Write Protect */
12493 uint32_t OPACR24_TP:1; /* Trusted Protect */
12494 uint32_t OPACR25_BW:1; /* Buffer Writes */
12495 uint32_t OPACR25_SP:1; /* Supervisor Protect */
12496 uint32_t OPACR25_WP:1; /* Write Protect */
12497 uint32_t OPACR25_TP:1; /* Trusted Protect */
12498 uint32_t OPACR26_BW:1; /* Buffer Writes */
12499 uint32_t OPACR26_SP:1; /* Supervisor Protect */
12500 uint32_t OPACR26_WP:1; /* Write Protect */
12501 uint32_t OPACR26_TP:1; /* Trusted Protect */
12502 uint32_t OPACR27_BW:1; /* Buffer Writes */
12503 uint32_t OPACR27_SP:1; /* Supervisor Protect */
12504 uint32_t OPACR27_WP:1; /* Write Protect */
12505 uint32_t OPACR27_TP:1; /* Trusted Protect */
12506 uint32_t OPACR28_BW:1; /* Buffer Writes */
12507 uint32_t OPACR28_SP:1; /* Supervisor Protect */
12508 uint32_t OPACR28_WP:1; /* Write Protect */
12509 uint32_t OPACR28_TP:1; /* Trusted Protect */
12510 uint32_t OPACR29_BW:1; /* Buffer Writes */
12511 uint32_t OPACR29_SP:1; /* Supervisor Protect */
12512 uint32_t OPACR29_WP:1; /* Write Protect */
12513 uint32_t OPACR29_TP:1; /* Trusted Protect */
12514 uint32_t OPACR30_BW:1; /* Buffer Writes */
12515 uint32_t OPACR30_SP:1; /* Supervisor Protect */
12516 uint32_t OPACR30_WP:1; /* Write Protect */
12517 uint32_t OPACR30_TP:1; /* Trusted Protect */
12518 uint32_t OPACR31_BW:1; /* Buffer Writes */
12519 uint32_t OPACR31_SP:1; /* Supervisor Protect */
12520 uint32_t OPACR31_WP:1; /* Write Protect */
12521 uint32_t OPACR31_TP:1; /* Trusted Protect */
12522 } B;
12523 } PBRIDGE_OPACR24_31_32B_tag;
12524
12525 typedef union { /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */
12526 uint32_t R;
12527 struct {
12528 uint32_t OPACR32_BW:1; /* Buffer Writes */
12529 uint32_t OPACR32_SP:1; /* Supervisor Protect */
12530 uint32_t OPACR32_WP:1; /* Write Protect */
12531 uint32_t OPACR32_TP:1; /* Trusted Protect */
12532 uint32_t OPACR33_BW:1; /* Buffer Writes */
12533 uint32_t OPACR33_SP:1; /* Supervisor Protect */
12534 uint32_t OPACR33_WP:1; /* Write Protect */
12535 uint32_t OPACR33_TP:1; /* Trusted Protect */
12536 uint32_t OPACR34_BW:1; /* Buffer Writes */
12537 uint32_t OPACR34_SP:1; /* Supervisor Protect */
12538 uint32_t OPACR34_WP:1; /* Write Protect */
12539 uint32_t OPACR34_TP:1; /* Trusted Protect */
12540 uint32_t OPACR35_BW:1; /* Buffer Writes */
12541 uint32_t OPACR35_SP:1; /* Supervisor Protect */
12542 uint32_t OPACR35_WP:1; /* Write Protect */
12543 uint32_t OPACR35_TP:1; /* Trusted Protect */
12544 uint32_t OPACR36_BW:1; /* Buffer Writes */
12545 uint32_t OPACR36_SP:1; /* Supervisor Protect */
12546 uint32_t OPACR36_WP:1; /* Write Protect */
12547 uint32_t OPACR36_TP:1; /* Trusted Protect */
12548 uint32_t OPACR37_BW:1; /* Buffer Writes */
12549 uint32_t OPACR37_SP:1; /* Supervisor Protect */
12550 uint32_t OPACR37_WP:1; /* Write Protect */
12551 uint32_t OPACR37_TP:1; /* Trusted Protect */
12552 uint32_t OPACR38_BW:1; /* Buffer Writes */
12553 uint32_t OPACR38_SP:1; /* Supervisor Protect */
12554 uint32_t OPACR38_WP:1; /* Write Protect */
12555 uint32_t OPACR38_TP:1; /* Trusted Protect */
12556 uint32_t OPACR39_BW:1; /* Buffer Writes */
12557 uint32_t OPACR39_SP:1; /* Supervisor Protect */
12558 uint32_t OPACR39_WP:1; /* Write Protect */
12559 uint32_t OPACR39_TP:1; /* Trusted Protect */
12560 } B;
12561 } PBRIDGE_OPACR32_39_32B_tag;
12562
12563 typedef union { /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */
12564 uint32_t R;
12565 struct {
12566 uint32_t OPACR40_BW:1; /* Buffer Writes */
12567 uint32_t OPACR40_SP:1; /* Supervisor Protect */
12568 uint32_t OPACR40_WP:1; /* Write Protect */
12569 uint32_t OPACR40_TP:1; /* Trusted Protect */
12570 uint32_t OPACR41_BW:1; /* Buffer Writes */
12571 uint32_t OPACR41_SP:1; /* Supervisor Protect */
12572 uint32_t OPACR41_WP:1; /* Write Protect */
12573 uint32_t OPACR41_TP:1; /* Trusted Protect */
12574 uint32_t OPACR42_BW:1; /* Buffer Writes */
12575 uint32_t OPACR42_SP:1; /* Supervisor Protect */
12576 uint32_t OPACR42_WP:1; /* Write Protect */
12577 uint32_t OPACR42_TP:1; /* Trusted Protect */
12578 uint32_t OPACR43_BW:1; /* Buffer Writes */
12579 uint32_t OPACR43_SP:1; /* Supervisor Protect */
12580 uint32_t OPACR43_WP:1; /* Write Protect */
12581 uint32_t OPACR43_TP:1; /* Trusted Protect */
12582 uint32_t OPACR44_BW:1; /* Buffer Writes */
12583 uint32_t OPACR44_SP:1; /* Supervisor Protect */
12584 uint32_t OPACR44_WP:1; /* Write Protect */
12585 uint32_t OPACR44_TP:1; /* Trusted Protect */
12586 uint32_t OPACR45_BW:1; /* Buffer Writes */
12587 uint32_t OPACR45_SP:1; /* Supervisor Protect */
12588 uint32_t OPACR45_WP:1; /* Write Protect */
12589 uint32_t OPACR45_TP:1; /* Trusted Protect */
12590 uint32_t OPACR46_BW:1; /* Buffer Writes */
12591 uint32_t OPACR46_SP:1; /* Supervisor Protect */
12592 uint32_t OPACR46_WP:1; /* Write Protect */
12593 uint32_t OPACR46_TP:1; /* Trusted Protect */
12594 uint32_t OPACR47_BW:1; /* Buffer Writes */
12595 uint32_t OPACR47_SP:1; /* Supervisor Protect */
12596 uint32_t OPACR47_WP:1; /* Write Protect */
12597 uint32_t OPACR47_TP:1; /* Trusted Protect */
12598 } B;
12599 } PBRIDGE_OPACR40_47_32B_tag;
12600
12601 typedef union { /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */
12602 uint32_t R;
12603 struct {
12604 uint32_t OPACR48_BW:1; /* Buffer Writes */
12605 uint32_t OPACR48_SP:1; /* Supervisor Protect */
12606 uint32_t OPACR48_WP:1; /* Write Protect */
12607 uint32_t OPACR48_TP:1; /* Trusted Protect */
12608 uint32_t OPACR49_BW:1; /* Buffer Writes */
12609 uint32_t OPACR49_SP:1; /* Supervisor Protect */
12610 uint32_t OPACR49_WP:1; /* Write Protect */
12611 uint32_t OPACR49_TP:1; /* Trusted Protect */
12612 uint32_t OPACR50_BW:1; /* Buffer Writes */
12613 uint32_t OPACR50_SP:1; /* Supervisor Protect */
12614 uint32_t OPACR50_WP:1; /* Write Protect */
12615 uint32_t OPACR50_TP:1; /* Trusted Protect */
12616 uint32_t OPACR51_BW:1; /* Buffer Writes */
12617 uint32_t OPACR51_SP:1; /* Supervisor Protect */
12618 uint32_t OPACR51_WP:1; /* Write Protect */
12619 uint32_t OPACR51_TP:1; /* Trusted Protect */
12620 uint32_t OPACR52_BW:1; /* Buffer Writes */
12621 uint32_t OPACR52_SP:1; /* Supervisor Protect */
12622 uint32_t OPACR52_WP:1; /* Write Protect */
12623 uint32_t OPACR52_TP:1; /* Trusted Protect */
12624 uint32_t OPACR53_BW:1; /* Buffer Writes */
12625 uint32_t OPACR53_SP:1; /* Supervisor Protect */
12626 uint32_t OPACR53_WP:1; /* Write Protect */
12627 uint32_t OPACR53_TP:1; /* Trusted Protect */
12628 uint32_t OPACR54_BW:1; /* Buffer Writes */
12629 uint32_t OPACR54_SP:1; /* Supervisor Protect */
12630 uint32_t OPACR54_WP:1; /* Write Protect */
12631 uint32_t OPACR54_TP:1; /* Trusted Protect */
12632 uint32_t OPACR55_BW:1; /* Buffer Writes */
12633 uint32_t OPACR55_SP:1; /* Supervisor Protect */
12634 uint32_t OPACR55_WP:1; /* Write Protect */
12635 uint32_t OPACR55_TP:1; /* Trusted Protect */
12636 } B;
12637 } PBRIDGE_OPACR48_55_32B_tag;
12638
12639 typedef union { /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */
12640 uint32_t R;
12641 struct {
12642 uint32_t OPACR56_BW:1; /* Buffer Writes */
12643 uint32_t OPACR56_SP:1; /* Supervisor Protect */
12644 uint32_t OPACR56_WP:1; /* Write Protect */
12645 uint32_t OPACR56_TP:1; /* Trusted Protect */
12646 uint32_t OPACR57_BW:1; /* Buffer Writes */
12647 uint32_t OPACR57_SP:1; /* Supervisor Protect */
12648 uint32_t OPACR57_WP:1; /* Write Protect */
12649 uint32_t OPACR57_TP:1; /* Trusted Protect */
12650 uint32_t OPACR58_BW:1; /* Buffer Writes */
12651 uint32_t OPACR58_SP:1; /* Supervisor Protect */
12652 uint32_t OPACR58_WP:1; /* Write Protect */
12653 uint32_t OPACR58_TP:1; /* Trusted Protect */
12654 uint32_t OPACR59_BW:1; /* Buffer Writes */
12655 uint32_t OPACR59_SP:1; /* Supervisor Protect */
12656 uint32_t OPACR59_WP:1; /* Write Protect */
12657 uint32_t OPACR59_TP:1; /* Trusted Protect */
12658 uint32_t OPACR60_BW:1; /* Buffer Writes */
12659 uint32_t OPACR60_SP:1; /* Supervisor Protect */
12660 uint32_t OPACR60_WP:1; /* Write Protect */
12661 uint32_t OPACR60_TP:1; /* Trusted Protect */
12662 uint32_t OPACR61_BW:1; /* Buffer Writes */
12663 uint32_t OPACR61_SP:1; /* Supervisor Protect */
12664 uint32_t OPACR61_WP:1; /* Write Protect */
12665 uint32_t OPACR61_TP:1; /* Trusted Protect */
12666 uint32_t OPACR62_BW:1; /* Buffer Writes */
12667 uint32_t OPACR62_SP:1; /* Supervisor Protect */
12668 uint32_t OPACR62_WP:1; /* Write Protect */
12669 uint32_t OPACR62_TP:1; /* Trusted Protect */
12670 uint32_t OPACR63_BW:1; /* Buffer Writes */
12671 uint32_t OPACR63_SP:1; /* Supervisor Protect */
12672 uint32_t OPACR63_WP:1; /* Write Protect */
12673 uint32_t OPACR63_TP:1; /* Trusted Protect */
12674 } B;
12675 } PBRIDGE_OPACR56_63_32B_tag;
12676
12677 typedef union { /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */
12678 uint32_t R;
12679 struct {
12680 uint32_t OPACR64_BW:1; /* Buffer Writes */
12681 uint32_t OPACR64_SP:1; /* Supervisor Protect */
12682 uint32_t OPACR64_WP:1; /* Write Protect */
12683 uint32_t OPACR64_TP:1; /* Trusted Protect */
12684 uint32_t OPACR65_BW:1; /* Buffer Writes */
12685 uint32_t OPACR65_SP:1; /* Supervisor Protect */
12686 uint32_t OPACR65_WP:1; /* Write Protect */
12687 uint32_t OPACR65_TP:1; /* Trusted Protect */
12688 uint32_t OPACR66_BW:1; /* Buffer Writes */
12689 uint32_t OPACR66_SP:1; /* Supervisor Protect */
12690 uint32_t OPACR66_WP:1; /* Write Protect */
12691 uint32_t OPACR66_TP:1; /* Trusted Protect */
12692 uint32_t OPACR67_BW:1; /* Buffer Writes */
12693 uint32_t OPACR67_SP:1; /* Supervisor Protect */
12694 uint32_t OPACR67_WP:1; /* Write Protect */
12695 uint32_t OPACR67_TP:1; /* Trusted Protect */
12696 uint32_t OPACR68_BW:1; /* Buffer Writes */
12697 uint32_t OPACR68_SP:1; /* Supervisor Protect */
12698 uint32_t OPACR68_WP:1; /* Write Protect */
12699 uint32_t OPACR68_TP:1; /* Trusted Protect */
12700 uint32_t OPACR69_BW:1; /* Buffer Writes */
12701 uint32_t OPACR69_SP:1; /* Supervisor Protect */
12702 uint32_t OPACR69_WP:1; /* Write Protect */
12703 uint32_t OPACR69_TP:1; /* Trusted Protect */
12704 uint32_t OPACR70_BW:1; /* Buffer Writes */
12705 uint32_t OPACR70_SP:1; /* Supervisor Protect */
12706 uint32_t OPACR70_WP:1; /* Write Protect */
12707 uint32_t OPACR70_TP:1; /* Trusted Protect */
12708 uint32_t OPACR71_BW:1; /* Buffer Writes */
12709 uint32_t OPACR71_SP:1; /* Supervisor Protect */
12710 uint32_t OPACR71_WP:1; /* Write Protect */
12711 uint32_t OPACR71_TP:1; /* Trusted Protect */
12712 } B;
12713 } PBRIDGE_OPACR64_71_32B_tag;
12714
12715 typedef union { /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */
12716 uint32_t R;
12717 struct {
12718 uint32_t OPACR72_BW:1; /* Buffer Writes */
12719 uint32_t OPACR72_SP:1; /* Supervisor Protect */
12720 uint32_t OPACR72_WP:1; /* Write Protect */
12721 uint32_t OPACR72_TP:1; /* Trusted Protect */
12722 uint32_t OPACR73_BW:1; /* Buffer Writes */
12723 uint32_t OPACR73_SP:1; /* Supervisor Protect */
12724 uint32_t OPACR73_WP:1; /* Write Protect */
12725 uint32_t OPACR73_TP:1; /* Trusted Protect */
12726 uint32_t OPACR74_BW:1; /* Buffer Writes */
12727 uint32_t OPACR74_SP:1; /* Supervisor Protect */
12728 uint32_t OPACR74_WP:1; /* Write Protect */
12729 uint32_t OPACR74_TP:1; /* Trusted Protect */
12730 uint32_t OPACR75_BW:1; /* Buffer Writes */
12731 uint32_t OPACR75_SP:1; /* Supervisor Protect */
12732 uint32_t OPACR75_WP:1; /* Write Protect */
12733 uint32_t OPACR75_TP:1; /* Trusted Protect */
12734 uint32_t OPACR76_BW:1; /* Buffer Writes */
12735 uint32_t OPACR76_SP:1; /* Supervisor Protect */
12736 uint32_t OPACR76_WP:1; /* Write Protect */
12737 uint32_t OPACR76_TP:1; /* Trusted Protect */
12738 uint32_t OPACR77_BW:1; /* Buffer Writes */
12739 uint32_t OPACR77_SP:1; /* Supervisor Protect */
12740 uint32_t OPACR77_WP:1; /* Write Protect */
12741 uint32_t OPACR77_TP:1; /* Trusted Protect */
12742 uint32_t OPACR78_BW:1; /* Buffer Writes */
12743 uint32_t OPACR78_SP:1; /* Supervisor Protect */
12744 uint32_t OPACR78_WP:1; /* Write Protect */
12745 uint32_t OPACR78_TP:1; /* Trusted Protect */
12746 uint32_t OPACR79_BW:1; /* Buffer Writes */
12747 uint32_t OPACR79_SP:1; /* Supervisor Protect */
12748 uint32_t OPACR79_WP:1; /* Write Protect */
12749 uint32_t OPACR79_TP:1; /* Trusted Protect */
12750 } B;
12751 } PBRIDGE_OPACR72_79_32B_tag;
12752
12753 typedef union { /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */
12754 uint32_t R;
12755 struct {
12756 uint32_t OPACR80_BW:1; /* Buffer Writes */
12757 uint32_t OPACR80_SP:1; /* Supervisor Protect */
12758 uint32_t OPACR80_WP:1; /* Write Protect */
12759 uint32_t OPACR80_TP:1; /* Trusted Protect */
12760 uint32_t OPACR81_BW:1; /* Buffer Writes */
12761 uint32_t OPACR81_SP:1; /* Supervisor Protect */
12762 uint32_t OPACR81_WP:1; /* Write Protect */
12763 uint32_t OPACR81_TP:1; /* Trusted Protect */
12764 uint32_t OPACR82_BW:1; /* Buffer Writes */
12765 uint32_t OPACR82_SP:1; /* Supervisor Protect */
12766 uint32_t OPACR82_WP:1; /* Write Protect */
12767 uint32_t OPACR82_TP:1; /* Trusted Protect */
12768 uint32_t OPACR83_BW:1; /* Buffer Writes */
12769 uint32_t OPACR83_SP:1; /* Supervisor Protect */
12770 uint32_t OPACR83_WP:1; /* Write Protect */
12771 uint32_t OPACR83_TP:1; /* Trusted Protect */
12772 uint32_t OPACR84_BW:1; /* Buffer Writes */
12773 uint32_t OPACR84_SP:1; /* Supervisor Protect */
12774 uint32_t OPACR84_WP:1; /* Write Protect */
12775 uint32_t OPACR84_TP:1; /* Trusted Protect */
12776 uint32_t OPACR85_BW:1; /* Buffer Writes */
12777 uint32_t OPACR85_SP:1; /* Supervisor Protect */
12778 uint32_t OPACR85_WP:1; /* Write Protect */
12779 uint32_t OPACR85_TP:1; /* Trusted Protect */
12780 uint32_t OPACR86_BW:1; /* Buffer Writes */
12781 uint32_t OPACR86_SP:1; /* Supervisor Protect */
12782 uint32_t OPACR86_WP:1; /* Write Protect */
12783 uint32_t OPACR86_TP:1; /* Trusted Protect */
12784 uint32_t OPACR87_BW:1; /* Buffer Writes */
12785 uint32_t OPACR87_SP:1; /* Supervisor Protect */
12786 uint32_t OPACR87_WP:1; /* Write Protect */
12787 uint32_t OPACR87_TP:1; /* Trusted Protect */
12788 } B;
12789 } PBRIDGE_OPACR80_87_32B_tag;
12790
12791 typedef union { /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */
12792 uint32_t R;
12793 struct {
12794 uint32_t OPACR88_BW:1; /* Buffer Writes */
12795 uint32_t OPACR88_SP:1; /* Supervisor Protect */
12796 uint32_t OPACR88_WP:1; /* Write Protect */
12797 uint32_t OPACR88_TP:1; /* Trusted Protect */
12798 uint32_t OPACR89_BW:1; /* Buffer Writes */
12799 uint32_t OPACR89_SP:1; /* Supervisor Protect */
12800 uint32_t OPACR89_WP:1; /* Write Protect */
12801 uint32_t OPACR89_TP:1; /* Trusted Protect */
12802 uint32_t OPACR90_BW:1; /* Buffer Writes */
12803 uint32_t OPACR90_SP:1; /* Supervisor Protect */
12804 uint32_t OPACR90_WP:1; /* Write Protect */
12805 uint32_t OPACR90_TP:1; /* Trusted Protect */
12806 uint32_t OPACR91_BW:1; /* Buffer Writes */
12807 uint32_t OPACR91_SP:1; /* Supervisor Protect */
12808 uint32_t OPACR91_WP:1; /* Write Protect */
12809 uint32_t OPACR91_TP:1; /* Trusted Protect */
12810 uint32_t OPACR92_BW:1; /* Buffer Writes */
12811 uint32_t OPACR92_SP:1; /* Supervisor Protect */
12812 uint32_t OPACR92_WP:1; /* Write Protect */
12813 uint32_t OPACR92_TP:1; /* Trusted Protect */
12814 uint32_t OPACR93_BW:1; /* Buffer Writes */
12815 uint32_t OPACR93_SP:1; /* Supervisor Protect */
12816 uint32_t OPACR93_WP:1; /* Write Protect */
12817 uint32_t OPACR93_TP:1; /* Trusted Protect */
12818 uint32_t OPACR94_BW:1; /* Buffer Writes */
12819 uint32_t OPACR94_SP:1; /* Supervisor Protect */
12820 uint32_t OPACR94_WP:1; /* Write Protect */
12821 uint32_t OPACR94_TP:1; /* Trusted Protect */
12822 uint32_t OPACR95_BW:1; /* Buffer Writes */
12823 uint32_t OPACR95_SP:1; /* Supervisor Protect */
12824 uint32_t OPACR95_WP:1; /* Write Protect */
12825 uint32_t OPACR95_TP:1; /* Trusted Protect */
12826 } B;
12827 } PBRIDGE_OPACR88_95_32B_tag;
12828
12829
12830
12831 typedef struct PBRIDGE_struct_tag { /* start of PBRIDGE_tag */
12832 /* MPROT - Master Privilege Registers */
12833 PBRIDGE_MPROT_32B_tag MPROT; /* offset: 0x0000 size: 32 bit */
12834 int8_t PBRIDGE_reserved_0004[28];
12835 /* PACR0_7 - Peripheral Access Control Registers */
12836 PBRIDGE_PACR0_7_32B_tag PACR0_7; /* offset: 0x0020 size: 32 bit */
12837 /* PACR8_15 - Peripheral Access Control Registers */
12838 PBRIDGE_PACR8_15_32B_tag PACR8_15; /* offset: 0x0024 size: 32 bit */
12839 /* PACR16_23 - Peripheral Access Control Registers */
12840 PBRIDGE_PACR16_23_32B_tag PACR16_23; /* offset: 0x0028 size: 32 bit */
12841 /* PACR24_31 - Peripheral Access Control Registers */
12842 PBRIDGE_PACR24_31_32B_tag PACR24_31; /* offset: 0x002C size: 32 bit */
12843 int8_t PBRIDGE_reserved_0030[16];
12844 /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */
12845 PBRIDGE_OPACR0_7_32B_tag OPACR0_7; /* offset: 0x0040 size: 32 bit */
12846 /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */
12847 PBRIDGE_OPACR8_15_32B_tag OPACR8_15; /* offset: 0x0044 size: 32 bit */
12848 /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */
12849 PBRIDGE_OPACR16_23_32B_tag OPACR16_23; /* offset: 0x0048 size: 32 bit */
12850 /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */
12851 PBRIDGE_OPACR24_31_32B_tag OPACR24_31; /* offset: 0x004C size: 32 bit */
12852 /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */
12853 PBRIDGE_OPACR32_39_32B_tag OPACR32_39; /* offset: 0x0050 size: 32 bit */
12854 /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */
12855 PBRIDGE_OPACR40_47_32B_tag OPACR40_47; /* offset: 0x0054 size: 32 bit */
12856 /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */
12857 PBRIDGE_OPACR48_55_32B_tag OPACR48_55; /* offset: 0x0058 size: 32 bit */
12858 /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */
12859 PBRIDGE_OPACR56_63_32B_tag OPACR56_63; /* offset: 0x005C size: 32 bit */
12860 /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */
12861 PBRIDGE_OPACR64_71_32B_tag OPACR64_71; /* offset: 0x0060 size: 32 bit */
12862 /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */
12863 PBRIDGE_OPACR72_79_32B_tag OPACR72_79; /* offset: 0x0064 size: 32 bit */
12864 /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */
12865 PBRIDGE_OPACR80_87_32B_tag OPACR80_87; /* offset: 0x0068 size: 32 bit */
12866 /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */
12867 PBRIDGE_OPACR88_95_32B_tag OPACR88_95; /* offset: 0x006C size: 32 bit */
12868 } PBRIDGE_tag;
12869
12870
12871#define PBRIDGE (*(volatile PBRIDGE_tag *) 0xFFF00000UL)
12872
12873
12874
12875/****************************************************************/
12876/* */
12877/* Module: MAX */
12878/* */
12879/****************************************************************/
12880
12881
12882 /* Register layout for all registers MPR... */
12883
12884 typedef union { /* Master Priority Register for slave port n */
12885 uint32_t R;
12886 struct {
12887 uint32_t:1;
12888 uint32_t MSTR_7:3; /* Master 7 Priority */
12889 uint32_t:1;
12890 uint32_t MSTR_6:3; /* Master 6 Priority */
12891 uint32_t:1;
12892 uint32_t MSTR_5:3; /* Master 5 Priority */
12893 uint32_t:1;
12894 uint32_t MSTR_4:3; /* Master 4 Priority */
12895 uint32_t:1;
12896 uint32_t MSTR_3:3; /* Master 3 Priority */
12897 uint32_t:1;
12898 uint32_t MSTR_2:3; /* Master 2 Priority */
12899 uint32_t:1;
12900 uint32_t MSTR_1:3; /* Master 1 Priority */
12901 uint32_t:1;
12902 uint32_t MSTR_0:3; /* Master 0 Priority */
12903 } B;
12904 } MAX_MPR_32B_tag;
12905
12906
12907 /* Register layout for all registers AMPR matches xxx */
12908
12909
12910 /* Register layout for all registers SGPCR... */
12911
12912 typedef union { /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
12913 uint32_t R;
12914 struct {
12915 uint32_t RO:1; /* Read Only */
12916 uint32_t HLP:1; /* Halt Low Priority */
12917 uint32_t:6;
12918 uint32_t HPE7:1; /* High Priority Enable */
12919 uint32_t HPE6:1; /* High Priority Enable */
12920 uint32_t HPE5:1; /* High Priority Enable */
12921 uint32_t HPE4:1; /* High Priority Enable */
12922 uint32_t HPE3:1; /* High Priority Enable */
12923 uint32_t HPE2:1; /* High Priority Enable */
12924 uint32_t HPE1:1; /* High Priority Enable */
12925 uint32_t HPE0:1; /* High Priority Enable */
12926 uint32_t:6;
12927 uint32_t ARB:2; /* Arbitration Mode */
12928 uint32_t:2;
12929 uint32_t PCTL:2; /* Parking Control */
12930 uint32_t:1;
12931 uint32_t PARK:3; /* Park */
12932 } B;
12933 } MAX_SGPCR_32B_tag;
12934
12935
12936 /* Register layout for all registers ASGPCR... */
12937
12938 typedef union { /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
12939 uint32_t R;
12940 struct {
12941 uint32_t:1;
12942 uint32_t HLP:1; /* Halt Low Priority */
12943 uint32_t:6;
12944 uint32_t HPE7:1; /* High Priority Enable */
12945 uint32_t HPE6:1; /* High Priority Enable */
12946 uint32_t HPE5:1; /* High Priority Enable */
12947 uint32_t HPE4:1; /* High Priority Enable */
12948 uint32_t HPE3:1; /* High Priority Enable */
12949 uint32_t HPE2:1; /* High Priority Enable */
12950 uint32_t HPE1:1; /* High Priority Enable */
12951 uint32_t HPE0:1; /* High Priority Enable */
12952 uint32_t:6;
12953 uint32_t ARB:2; /* Arbitration Mode */
12954 uint32_t:2;
12955 uint32_t PCTL:2; /* Parking Control */
12956 uint32_t:1;
12957 uint32_t PARK:3; /* Park */
12958 } B;
12959 } MAX_ASGPCR_32B_tag;
12960
12961
12962 /* Register layout for all registers MGPCR... */
12963
12964 typedef union { /* MAX_MGPCRn - Master General Purpose Control Register n */
12965 uint32_t R;
12966 struct {
12967 uint32_t:29;
12968 uint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */
12969 } B;
12970 } MAX_MGPCR_32B_tag;
12971
12972
12973 typedef struct MAX_SLAVE_PORT_struct_tag {
12974
12975 /* Master Priority Register for slave port n */
12976 MAX_MPR_32B_tag MPR; /* relative offset: 0x0000 */
12977 /* Alternate Master Priority Register for slave port n */
12978 MAX_MPR_32B_tag AMPR; /* relative offset: 0x0004 */
12979 int8_t MAX_SLAVE_PORT_reserved_0008[8];
12980 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
12981 MAX_SGPCR_32B_tag SGPCR; /* relative offset: 0x0010 */
12982 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
12983 MAX_ASGPCR_32B_tag ASGPCR; /* relative offset: 0x0014 */
12984 int8_t MAX_SLAVE_PORT_reserved_0018[232];
12985
12986 } MAX_SLAVE_PORT_tag;
12987
12988 typedef struct MAX_MASTER_PORT_struct_tag {
12989
12990 /* MAX_MGPCRn - Master General Purpose Control Register n */
12991 MAX_MGPCR_32B_tag MGPCR; /* relative offset: 0x0000 */
12992 int8_t MAX_MASTER_PORT_reserved_0004[252];
12993
12994 } MAX_MASTER_PORT_tag;
12995
12996
12997 typedef struct MAX_struct_tag { /* start of MAX_tag */
12998 union {
12999 /* Register set SLAVE_PORT */
13000 MAX_SLAVE_PORT_tag SLAVE_PORT[8]; /* offset: 0x0000 (0x0100 x 8) */
13001
13002 struct {
13003 /* Master Priority Register for slave port n */
13004 MAX_MPR_32B_tag MPR0; /* offset: 0x0000 size: 32 bit */
13005 /* Alternate Master Priority Register for slave port n */
13006 MAX_MPR_32B_tag AMPR0; /* offset: 0x0004 size: 32 bit */
13007 int8_t MAX_reserved_0008_I1[8];
13008 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13009 MAX_SGPCR_32B_tag SGPCR0; /* offset: 0x0010 size: 32 bit */
13010 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13011 MAX_ASGPCR_32B_tag ASGPCR0; /* offset: 0x0014 size: 32 bit */
13012 int8_t MAX_reserved_0018_I1[232];
13013 /* Master Priority Register for slave port n */
13014 MAX_MPR_32B_tag MPR1; /* offset: 0x0100 size: 32 bit */
13015 /* Alternate Master Priority Register for slave port n */
13016 MAX_MPR_32B_tag AMPR1; /* offset: 0x0104 size: 32 bit */
13017 int8_t MAX_reserved_0108_I1[8];
13018 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13019 MAX_SGPCR_32B_tag SGPCR1; /* offset: 0x0110 size: 32 bit */
13020 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13021 MAX_ASGPCR_32B_tag ASGPCR1; /* offset: 0x0114 size: 32 bit */
13022 int8_t MAX_reserved_0118_I1[232];
13023 /* Master Priority Register for slave port n */
13024 MAX_MPR_32B_tag MPR2; /* offset: 0x0200 size: 32 bit */
13025 /* Alternate Master Priority Register for slave port n */
13026 MAX_MPR_32B_tag AMPR2; /* offset: 0x0204 size: 32 bit */
13027 int8_t MAX_reserved_0208_I1[8];
13028 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13029 MAX_SGPCR_32B_tag SGPCR2; /* offset: 0x0210 size: 32 bit */
13030 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13031 MAX_ASGPCR_32B_tag ASGPCR2; /* offset: 0x0214 size: 32 bit */
13032 int8_t MAX_reserved_0218_I1[232];
13033 /* Master Priority Register for slave port n */
13034 MAX_MPR_32B_tag MPR3; /* offset: 0x0300 size: 32 bit */
13035 /* Alternate Master Priority Register for slave port n */
13036 MAX_MPR_32B_tag AMPR3; /* offset: 0x0304 size: 32 bit */
13037 int8_t MAX_reserved_0308_I1[8];
13038 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13039 MAX_SGPCR_32B_tag SGPCR3; /* offset: 0x0310 size: 32 bit */
13040 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13041 MAX_ASGPCR_32B_tag ASGPCR3; /* offset: 0x0314 size: 32 bit */
13042 int8_t MAX_reserved_0318_I1[232];
13043 /* Master Priority Register for slave port n */
13044 MAX_MPR_32B_tag MPR4; /* offset: 0x0400 size: 32 bit */
13045 /* Alternate Master Priority Register for slave port n */
13046 MAX_MPR_32B_tag AMPR4; /* offset: 0x0404 size: 32 bit */
13047 int8_t MAX_reserved_0408_I1[8];
13048 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13049 MAX_SGPCR_32B_tag SGPCR4; /* offset: 0x0410 size: 32 bit */
13050 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13051 MAX_ASGPCR_32B_tag ASGPCR4; /* offset: 0x0414 size: 32 bit */
13052 int8_t MAX_reserved_0418_I1[232];
13053 /* Master Priority Register for slave port n */
13054 MAX_MPR_32B_tag MPR5; /* offset: 0x0500 size: 32 bit */
13055 /* Alternate Master Priority Register for slave port n */
13056 MAX_MPR_32B_tag AMPR5; /* offset: 0x0504 size: 32 bit */
13057 int8_t MAX_reserved_0508_I1[8];
13058 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13059 MAX_SGPCR_32B_tag SGPCR5; /* offset: 0x0510 size: 32 bit */
13060 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13061 MAX_ASGPCR_32B_tag ASGPCR5; /* offset: 0x0514 size: 32 bit */
13062 int8_t MAX_reserved_0518_I1[232];
13063 /* Master Priority Register for slave port n */
13064 MAX_MPR_32B_tag MPR6; /* offset: 0x0600 size: 32 bit */
13065 /* Alternate Master Priority Register for slave port n */
13066 MAX_MPR_32B_tag AMPR6; /* offset: 0x0604 size: 32 bit */
13067 int8_t MAX_reserved_0608_I1[8];
13068 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13069 MAX_SGPCR_32B_tag SGPCR6; /* offset: 0x0610 size: 32 bit */
13070 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13071 MAX_ASGPCR_32B_tag ASGPCR6; /* offset: 0x0614 size: 32 bit */
13072 int8_t MAX_reserved_0618_I1[232];
13073 /* Master Priority Register for slave port n */
13074 MAX_MPR_32B_tag MPR7; /* offset: 0x0700 size: 32 bit */
13075 /* Alternate Master Priority Register for slave port n */
13076 MAX_MPR_32B_tag AMPR7; /* offset: 0x0704 size: 32 bit */
13077 int8_t MAX_reserved_0708_I1[8];
13078 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13079 MAX_SGPCR_32B_tag SGPCR7; /* offset: 0x0710 size: 32 bit */
13080 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13081 MAX_ASGPCR_32B_tag ASGPCR7; /* offset: 0x0714 size: 32 bit */
13082 int8_t MAX_reserved_0718_E1[232];
13083 };
13084
13085 };
13086 union {
13087 /* Register set MASTER_PORT */
13088 MAX_MASTER_PORT_tag MASTER_PORT[8]; /* offset: 0x0800 (0x0100 x 8) */
13089
13090 struct {
13091 /* MAX_MGPCRn - Master General Purpose Control Register n */
13092 MAX_MGPCR_32B_tag MGPCR0; /* offset: 0x0800 size: 32 bit */
13093 int8_t MAX_reserved_0804_I1[252];
13094 MAX_MGPCR_32B_tag MGPCR1; /* offset: 0x0900 size: 32 bit */
13095 int8_t MAX_reserved_0904_I1[252];
13096 MAX_MGPCR_32B_tag MGPCR2; /* offset: 0x0A00 size: 32 bit */
13097 int8_t MAX_reserved_0A04_I1[252];
13098 MAX_MGPCR_32B_tag MGPCR3; /* offset: 0x0B00 size: 32 bit */
13099 int8_t MAX_reserved_0B04_I1[252];
13100 MAX_MGPCR_32B_tag MGPCR4; /* offset: 0x0C00 size: 32 bit */
13101 int8_t MAX_reserved_0C04_I1[252];
13102 MAX_MGPCR_32B_tag MGPCR5; /* offset: 0x0D00 size: 32 bit */
13103 int8_t MAX_reserved_0D04_I1[252];
13104 MAX_MGPCR_32B_tag MGPCR6; /* offset: 0x0E00 size: 32 bit */
13105 int8_t MAX_reserved_0E04_I1[252];
13106 MAX_MGPCR_32B_tag MGPCR7; /* offset: 0x0F00 size: 32 bit */
13107 int8_t MAX_reserved_0F04_E1[252];
13108 };
13109
13110 };
13111 } MAX_tag;
13112
13113
13114#define MAX (*(volatile MAX_tag *) 0xFFF04000UL)
13115
13116
13117
13118/****************************************************************/
13119/* */
13120/* Module: MPU */
13121/* */
13122/****************************************************************/
13123
13124 typedef union { /* MPU_CESR - MPU Control/Error Status Register */
13125 uint32_t R;
13126 struct {
13127 uint32_t SPERR:8; /* Slave Port n Error */
13128 uint32_t:4;
13129 uint32_t HRL:4; /* Hardware Revision Level */
13130 uint32_t NSP:4; /* Number of Slave Ports */
13131 uint32_t NRGD:4; /* Number of Region Descriptors */
13132 uint32_t:7;
13133 uint32_t VLD:1; /* Valid bit */
13134 } B;
13135 } MPU_CESR_32B_tag;
13136
13137
13138 /* Register layout for all registers EAR... */
13139
13140 typedef union { /* MPU_EARn - MPU Error Address Register, Slave Port n */
13141 uint32_t R;
13142 struct {
13143 uint32_t EADDR:32; /* Error Address */
13144 } B;
13145 } MPU_EAR_32B_tag;
13146
13147
13148 /* Register layout for all registers EDR... */
13149
13150 typedef union { /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
13151 uint32_t R;
13152 struct {
13153 uint32_t EACD:16; /* Error Access Control Detail */
13154 uint32_t EPID:8; /* Error Process Identification */
13155 uint32_t EMN:4; /* Error Master Number */
13156 uint32_t EATTR:3; /* Error Attributes */
13157 uint32_t ERW:1; /* Error Read/Write */
13158 } B;
13159 } MPU_EDR_32B_tag;
13160
13161
13162 /* Register layout for all registers RGD_WORD0... */
13163
13164 typedef union { /* MPU_RGDn_Word0 - MPU Region Descriptor */
13165 uint32_t R;
13166 struct {
13167 uint32_t SRTADDR:27; /* Start Address */
13168 uint32_t:5;
13169 } B;
13170 } MPU_RGD_WORD0_32B_tag;
13171
13172
13173 /* Register layout for all registers RGD_WORD1... */
13174
13175 typedef union { /* MPU_RGDn_Word1 - MPU Region Descriptor */
13176 uint32_t R;
13177 struct {
13178 uint32_t ENDADDR:27; /* End Address */
13179 uint32_t:5;
13180 } B;
13181 } MPU_RGD_WORD1_32B_tag;
13182
13183
13184 /* Register layout for all registers RGD_WORD2... */
13185
13186 typedef union { /* MPU_RGDn_Word2 - MPU Region Descriptor */
13187 uint32_t R;
13188 struct {
13189 uint32_t M7RE:1; /* Bus Master 7 Read Enable */
13190 uint32_t M7WE:1; /* Bus Master 7 Write Enable */
13191 uint32_t M6RE:1; /* Bus Master 6 Read Enable */
13192 uint32_t M6WE:1; /* Bus Master 7 Write Enable */
13193 uint32_t M5RE:1; /* Bus Master 5 Read Enable */
13194 uint32_t M5WE:1; /* Bus Master 5 Write Enable */
13195 uint32_t M4RE:1; /* Bus Master 4 Read Enable */
13196 uint32_t M4WE:1; /* Bus Master 4 Write Enable */
13197 uint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */
13198 uint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */
13199 uint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */
13200 uint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */
13201 uint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */
13202 uint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */
13203 uint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */
13204 uint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */
13205 uint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */
13206 uint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */
13207 uint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */
13208 uint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */
13209 } B;
13210 } MPU_RGD_WORD2_32B_tag;
13211
13212
13213 /* Register layout for all registers RGD_WORD3... */
13214
13215 typedef union { /* MPU_RGDn_Word3 - MPU Region Descriptor */
13216 uint32_t R;
13217 struct {
13218 uint32_t PID:8; /* Process Identifier */
13219 uint32_t PIDMASK:8; /* Process Identifier Mask */
13220 uint32_t:15;
13221 uint32_t VLD:1; /* Valid */
13222 } B;
13223 } MPU_RGD_WORD3_32B_tag;
13224
13225
13226 /* Register layout for all registers RGDAAC... */
13227
13228 typedef union { /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */
13229 uint32_t R;
13230 struct {
13231 uint32_t M7RE:1; /* Bus Master 7 Read Enable */
13232 uint32_t M7WE:1; /* Bus Master 7 Write Enable */
13233 uint32_t M6RE:1; /* Bus Master 6 Read Enable */
13234 uint32_t M6WE:1; /* Bus Master 7 Write Enable */
13235 uint32_t M5RE:1; /* Bus Master 5 Read Enable */
13236 uint32_t M5WE:1; /* Bus Master 5 Write Enable */
13237 uint32_t M4RE:1; /* Bus Master 4 Read Enable */
13238 uint32_t M4WE:1; /* Bus Master 4 Write Enable */
13239 uint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */
13240 uint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */
13241 uint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */
13242 uint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */
13243 uint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */
13244 uint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */
13245 uint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */
13246 uint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */
13247 uint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */
13248 uint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */
13249 uint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */
13250 uint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */
13251 } B;
13252 } MPU_RGDAAC_32B_tag;
13253
13254
13255 typedef struct MPU_SLAVE_PORT_struct_tag {
13256
13257 /* MPU_EARn - MPU Error Address Register, Slave Port n */
13258 MPU_EAR_32B_tag EAR; /* relative offset: 0x0000 */
13259 /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
13260 MPU_EDR_32B_tag EDR; /* relative offset: 0x0004 */
13261
13262 } MPU_SLAVE_PORT_tag;
13263
13264 typedef struct MPU_REGION_struct_tag {
13265
13266 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13267 MPU_RGD_WORD0_32B_tag RGD_WORD0; /* relative offset: 0x0000 */
13268 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13269 MPU_RGD_WORD1_32B_tag RGD_WORD1; /* relative offset: 0x0004 */
13270 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13271 MPU_RGD_WORD2_32B_tag RGD_WORD2; /* relative offset: 0x0008 */
13272 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13273 MPU_RGD_WORD3_32B_tag RGD_WORD3; /* relative offset: 0x000C */
13274
13275 } MPU_REGION_tag;
13276
13277
13278 typedef struct MPU_struct_tag { /* start of MPU_tag */
13279 /* MPU_CESR - MPU Control/Error Status Register */
13280 MPU_CESR_32B_tag CESR; /* offset: 0x0000 size: 32 bit */
13281 int8_t MPU_reserved_0004_C[12];
13282 union {
13283 /* Register set SLAVE_PORT */
13284 MPU_SLAVE_PORT_tag SLAVE_PORT[4]; /* offset: 0x0010 (0x0008 x 4) */
13285
13286 struct {
13287 /* MPU_EARn - MPU Error Address Register, Slave Port n */
13288 MPU_EAR_32B_tag EAR0; /* offset: 0x0010 size: 32 bit */
13289 /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
13290 MPU_EDR_32B_tag EDR0; /* offset: 0x0014 size: 32 bit */
13291 /* MPU_EARn - MPU Error Address Register, Slave Port n */
13292 MPU_EAR_32B_tag EAR1; /* offset: 0x0018 size: 32 bit */
13293 /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
13294 MPU_EDR_32B_tag EDR1; /* offset: 0x001C size: 32 bit */
13295 /* MPU_EARn - MPU Error Address Register, Slave Port n */
13296 MPU_EAR_32B_tag EAR2; /* offset: 0x0020 size: 32 bit */
13297 /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
13298 MPU_EDR_32B_tag EDR2; /* offset: 0x0024 size: 32 bit */
13299 /* MPU_EARn - MPU Error Address Register, Slave Port n */
13300 MPU_EAR_32B_tag EAR3; /* offset: 0x0028 size: 32 bit */
13301 /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
13302 MPU_EDR_32B_tag EDR3; /* offset: 0x002C size: 32 bit */
13303 };
13304
13305 };
13306 int8_t MPU_reserved_0030_C[976];
13307 union {
13308 /* Register set REGION */
13309 MPU_REGION_tag REGION[16]; /* offset: 0x0400 (0x0010 x 16) */
13310
13311 struct {
13312 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13313 MPU_RGD_WORD0_32B_tag RGD0_WORD0; /* offset: 0x0400 size: 32 bit */
13314 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13315 MPU_RGD_WORD1_32B_tag RGD0_WORD1; /* offset: 0x0404 size: 32 bit */
13316 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13317 MPU_RGD_WORD2_32B_tag RGD0_WORD2; /* offset: 0x0408 size: 32 bit */
13318 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13319 MPU_RGD_WORD3_32B_tag RGD0_WORD3; /* offset: 0x040C size: 32 bit */
13320 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13321 MPU_RGD_WORD0_32B_tag RGD1_WORD0; /* offset: 0x0410 size: 32 bit */
13322 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13323 MPU_RGD_WORD1_32B_tag RGD1_WORD1; /* offset: 0x0414 size: 32 bit */
13324 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13325 MPU_RGD_WORD2_32B_tag RGD1_WORD2; /* offset: 0x0418 size: 32 bit */
13326 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13327 MPU_RGD_WORD3_32B_tag RGD1_WORD3; /* offset: 0x041C size: 32 bit */
13328 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13329 MPU_RGD_WORD0_32B_tag RGD2_WORD0; /* offset: 0x0420 size: 32 bit */
13330 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13331 MPU_RGD_WORD1_32B_tag RGD2_WORD1; /* offset: 0x0424 size: 32 bit */
13332 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13333 MPU_RGD_WORD2_32B_tag RGD2_WORD2; /* offset: 0x0428 size: 32 bit */
13334 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13335 MPU_RGD_WORD3_32B_tag RGD2_WORD3; /* offset: 0x042C size: 32 bit */
13336 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13337 MPU_RGD_WORD0_32B_tag RGD3_WORD0; /* offset: 0x0430 size: 32 bit */
13338 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13339 MPU_RGD_WORD1_32B_tag RGD3_WORD1; /* offset: 0x0434 size: 32 bit */
13340 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13341 MPU_RGD_WORD2_32B_tag RGD3_WORD2; /* offset: 0x0438 size: 32 bit */
13342 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13343 MPU_RGD_WORD3_32B_tag RGD3_WORD3; /* offset: 0x043C size: 32 bit */
13344 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13345 MPU_RGD_WORD0_32B_tag RGD4_WORD0; /* offset: 0x0440 size: 32 bit */
13346 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13347 MPU_RGD_WORD1_32B_tag RGD4_WORD1; /* offset: 0x0444 size: 32 bit */
13348 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13349 MPU_RGD_WORD2_32B_tag RGD4_WORD2; /* offset: 0x0448 size: 32 bit */
13350 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13351 MPU_RGD_WORD3_32B_tag RGD4_WORD3; /* offset: 0x044C size: 32 bit */
13352 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13353 MPU_RGD_WORD0_32B_tag RGD5_WORD0; /* offset: 0x0450 size: 32 bit */
13354 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13355 MPU_RGD_WORD1_32B_tag RGD5_WORD1; /* offset: 0x0454 size: 32 bit */
13356 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13357 MPU_RGD_WORD2_32B_tag RGD5_WORD2; /* offset: 0x0458 size: 32 bit */
13358 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13359 MPU_RGD_WORD3_32B_tag RGD5_WORD3; /* offset: 0x045C size: 32 bit */
13360 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13361 MPU_RGD_WORD0_32B_tag RGD6_WORD0; /* offset: 0x0460 size: 32 bit */
13362 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13363 MPU_RGD_WORD1_32B_tag RGD6_WORD1; /* offset: 0x0464 size: 32 bit */
13364 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13365 MPU_RGD_WORD2_32B_tag RGD6_WORD2; /* offset: 0x0468 size: 32 bit */
13366 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13367 MPU_RGD_WORD3_32B_tag RGD6_WORD3; /* offset: 0x046C size: 32 bit */
13368 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13369 MPU_RGD_WORD0_32B_tag RGD7_WORD0; /* offset: 0x0470 size: 32 bit */
13370 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13371 MPU_RGD_WORD1_32B_tag RGD7_WORD1; /* offset: 0x0474 size: 32 bit */
13372 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13373 MPU_RGD_WORD2_32B_tag RGD7_WORD2; /* offset: 0x0478 size: 32 bit */
13374 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13375 MPU_RGD_WORD3_32B_tag RGD7_WORD3; /* offset: 0x047C size: 32 bit */
13376 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13377 MPU_RGD_WORD0_32B_tag RGD8_WORD0; /* offset: 0x0480 size: 32 bit */
13378 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13379 MPU_RGD_WORD1_32B_tag RGD8_WORD1; /* offset: 0x0484 size: 32 bit */
13380 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13381 MPU_RGD_WORD2_32B_tag RGD8_WORD2; /* offset: 0x0488 size: 32 bit */
13382 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13383 MPU_RGD_WORD3_32B_tag RGD8_WORD3; /* offset: 0x048C size: 32 bit */
13384 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13385 MPU_RGD_WORD0_32B_tag RGD9_WORD0; /* offset: 0x0490 size: 32 bit */
13386 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13387 MPU_RGD_WORD1_32B_tag RGD9_WORD1; /* offset: 0x0494 size: 32 bit */
13388 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13389 MPU_RGD_WORD2_32B_tag RGD9_WORD2; /* offset: 0x0498 size: 32 bit */
13390 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13391 MPU_RGD_WORD3_32B_tag RGD9_WORD3; /* offset: 0x049C size: 32 bit */
13392 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13393 MPU_RGD_WORD0_32B_tag RGD10_WORD0; /* offset: 0x04A0 size: 32 bit */
13394 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13395 MPU_RGD_WORD1_32B_tag RGD10_WORD1; /* offset: 0x04A4 size: 32 bit */
13396 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13397 MPU_RGD_WORD2_32B_tag RGD10_WORD2; /* offset: 0x04A8 size: 32 bit */
13398 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13399 MPU_RGD_WORD3_32B_tag RGD10_WORD3; /* offset: 0x04AC size: 32 bit */
13400 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13401 MPU_RGD_WORD0_32B_tag RGD11_WORD0; /* offset: 0x04B0 size: 32 bit */
13402 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13403 MPU_RGD_WORD1_32B_tag RGD11_WORD1; /* offset: 0x04B4 size: 32 bit */
13404 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13405 MPU_RGD_WORD2_32B_tag RGD11_WORD2; /* offset: 0x04B8 size: 32 bit */
13406 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13407 MPU_RGD_WORD3_32B_tag RGD11_WORD3; /* offset: 0x04BC size: 32 bit */
13408 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13409 MPU_RGD_WORD0_32B_tag RGD12_WORD0; /* offset: 0x04C0 size: 32 bit */
13410 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13411 MPU_RGD_WORD1_32B_tag RGD12_WORD1; /* offset: 0x04C4 size: 32 bit */
13412 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13413 MPU_RGD_WORD2_32B_tag RGD12_WORD2; /* offset: 0x04C8 size: 32 bit */
13414 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13415 MPU_RGD_WORD3_32B_tag RGD12_WORD3; /* offset: 0x04CC size: 32 bit */
13416 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13417 MPU_RGD_WORD0_32B_tag RGD13_WORD0; /* offset: 0x04D0 size: 32 bit */
13418 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13419 MPU_RGD_WORD1_32B_tag RGD13_WORD1; /* offset: 0x04D4 size: 32 bit */
13420 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13421 MPU_RGD_WORD2_32B_tag RGD13_WORD2; /* offset: 0x04D8 size: 32 bit */
13422 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13423 MPU_RGD_WORD3_32B_tag RGD13_WORD3; /* offset: 0x04DC size: 32 bit */
13424 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13425 MPU_RGD_WORD0_32B_tag RGD14_WORD0; /* offset: 0x04E0 size: 32 bit */
13426 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13427 MPU_RGD_WORD1_32B_tag RGD14_WORD1; /* offset: 0x04E4 size: 32 bit */
13428 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13429 MPU_RGD_WORD2_32B_tag RGD14_WORD2; /* offset: 0x04E8 size: 32 bit */
13430 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13431 MPU_RGD_WORD3_32B_tag RGD14_WORD3; /* offset: 0x04EC size: 32 bit */
13432 /* MPU_RGDn_Word0 - MPU Region Descriptor */
13433 MPU_RGD_WORD0_32B_tag RGD15_WORD0; /* offset: 0x04F0 size: 32 bit */
13434 /* MPU_RGDn_Word1 - MPU Region Descriptor */
13435 MPU_RGD_WORD1_32B_tag RGD15_WORD1; /* offset: 0x04F4 size: 32 bit */
13436 /* MPU_RGDn_Word2 - MPU Region Descriptor */
13437 MPU_RGD_WORD2_32B_tag RGD15_WORD2; /* offset: 0x04F8 size: 32 bit */
13438 /* MPU_RGDn_Word3 - MPU Region Descriptor */
13439 MPU_RGD_WORD3_32B_tag RGD15_WORD3; /* offset: 0x04FC size: 32 bit */
13440 };
13441
13442 };
13443 int8_t MPU_reserved_0500_C[768];
13444 union {
13445 /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */
13446 MPU_RGDAAC_32B_tag RGDAAC[16]; /* offset: 0x0800 (0x0004 x 16) */
13447
13448 struct {
13449 /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */
13450 MPU_RGDAAC_32B_tag RGDAAC0; /* offset: 0x0800 size: 32 bit */
13451 MPU_RGDAAC_32B_tag RGDAAC1; /* offset: 0x0804 size: 32 bit */
13452 MPU_RGDAAC_32B_tag RGDAAC2; /* offset: 0x0808 size: 32 bit */
13453 MPU_RGDAAC_32B_tag RGDAAC3; /* offset: 0x080C size: 32 bit */
13454 MPU_RGDAAC_32B_tag RGDAAC4; /* offset: 0x0810 size: 32 bit */
13455 MPU_RGDAAC_32B_tag RGDAAC5; /* offset: 0x0814 size: 32 bit */
13456 MPU_RGDAAC_32B_tag RGDAAC6; /* offset: 0x0818 size: 32 bit */
13457 MPU_RGDAAC_32B_tag RGDAAC7; /* offset: 0x081C size: 32 bit */
13458 MPU_RGDAAC_32B_tag RGDAAC8; /* offset: 0x0820 size: 32 bit */
13459 MPU_RGDAAC_32B_tag RGDAAC9; /* offset: 0x0824 size: 32 bit */
13460 MPU_RGDAAC_32B_tag RGDAAC10; /* offset: 0x0828 size: 32 bit */
13461 MPU_RGDAAC_32B_tag RGDAAC11; /* offset: 0x082C size: 32 bit */
13462 MPU_RGDAAC_32B_tag RGDAAC12; /* offset: 0x0830 size: 32 bit */
13463 MPU_RGDAAC_32B_tag RGDAAC13; /* offset: 0x0834 size: 32 bit */
13464 MPU_RGDAAC_32B_tag RGDAAC14; /* offset: 0x0838 size: 32 bit */
13465 MPU_RGDAAC_32B_tag RGDAAC15; /* offset: 0x083C size: 32 bit */
13466 };
13467
13468 };
13469 } MPU_tag;
13470
13471
13472#define MPU (*(volatile MPU_tag *) 0xFFF10000UL)
13473
13474
13475
13476/****************************************************************/
13477/* */
13478/* Module: SEMA4 */
13479/* */
13480/****************************************************************/
13481
13482
13483 /* Register layout for all registers GATE... */
13484
13485 typedef union { /* SEMA4_GATEn - Semephores Gate Register */
13486 uint8_t R;
13487 struct {
13488 uint8_t:6;
13489 uint8_t GTFSM:2; /* Gate Finite State machine */
13490 } B;
13491 } SEMA4_GATE_8B_tag;
13492
13493 typedef union { /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */
13494 uint16_t R;
13495 struct {
13496 uint16_t INE:16; /* Interrupt Request Notification Enable */
13497 } B;
13498 } SEMA4_CP0INE_16B_tag;
13499
13500 typedef union { /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */
13501 uint16_t R;
13502 struct {
13503 uint16_t INE:16; /* Interrupt Request Notification Enable */
13504 } B;
13505 } SEMA4_CP1INE_16B_tag;
13506
13507 typedef union { /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */
13508 uint16_t R;
13509 struct {
13510 uint16_t GN:16; /* Gate 0 Notification */
13511 } B;
13512 } SEMA4_CP0NTF_16B_tag;
13513
13514 typedef union { /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */
13515 uint16_t R;
13516 struct {
13517 uint16_t GN:16; /* Gate 1 Notification */
13518 } B;
13519 } SEMA4_CP1NTF_16B_tag;
13520
13521 typedef union { /* SEMA4_RSTGT - Semaphores Reset Gate */
13522 uint16_t R;
13523 struct {
13524 uint16_t:2;
13525 uint16_t RSTGSM:2; /* Reset Gate Finite State Machine */
13526 uint16_t RSTGDP:7; /* Reset Gate Data Pattern */
13527 uint16_t RSTGMS:3; /* Reset Gate Bus Master */
13528 uint16_t RSTGTN:8; /* Reset Gate Number */
13529 } B;
13530 } SEMA4_RSTGT_16B_tag;
13531
13532 typedef union { /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */
13533 uint16_t R;
13534 struct {
13535 uint16_t:2;
13536 uint16_t RSTNSM:2; /* Reset Gate Finite State Machine */
13537 uint16_t RSTNDP:7; /* Reset Gate Data Pattern */
13538 uint16_t RSTNMS:3; /* Reset Gate Bus Master */
13539 uint16_t RSTNTN:8; /* Reset Gate Number */
13540 } B;
13541 } SEMA4_RSTNTF_16B_tag;
13542
13543
13544
13545 typedef struct SEMA4_struct_tag { /* start of SEMA4_tag */
13546 union {
13547 /* SEMA4_GATEn - Semephores Gate Register */
13548 SEMA4_GATE_8B_tag GATE[16]; /* offset: 0x0000 (0x0001 x 16) */
13549
13550 struct {
13551 /* SEMA4_GATEn - Semephores Gate Register */
13552 SEMA4_GATE_8B_tag GATE0; /* offset: 0x0000 size: 8 bit */
13553 SEMA4_GATE_8B_tag GATE1; /* offset: 0x0001 size: 8 bit */
13554 SEMA4_GATE_8B_tag GATE2; /* offset: 0x0002 size: 8 bit */
13555 SEMA4_GATE_8B_tag GATE3; /* offset: 0x0003 size: 8 bit */
13556 SEMA4_GATE_8B_tag GATE4; /* offset: 0x0004 size: 8 bit */
13557 SEMA4_GATE_8B_tag GATE5; /* offset: 0x0005 size: 8 bit */
13558 SEMA4_GATE_8B_tag GATE6; /* offset: 0x0006 size: 8 bit */
13559 SEMA4_GATE_8B_tag GATE7; /* offset: 0x0007 size: 8 bit */
13560 SEMA4_GATE_8B_tag GATE8; /* offset: 0x0008 size: 8 bit */
13561 SEMA4_GATE_8B_tag GATE9; /* offset: 0x0009 size: 8 bit */
13562 SEMA4_GATE_8B_tag GATE10; /* offset: 0x000A size: 8 bit */
13563 SEMA4_GATE_8B_tag GATE11; /* offset: 0x000B size: 8 bit */
13564 SEMA4_GATE_8B_tag GATE12; /* offset: 0x000C size: 8 bit */
13565 SEMA4_GATE_8B_tag GATE13; /* offset: 0x000D size: 8 bit */
13566 SEMA4_GATE_8B_tag GATE14; /* offset: 0x000E size: 8 bit */
13567 SEMA4_GATE_8B_tag GATE15; /* offset: 0x000F size: 8 bit */
13568 };
13569
13570 };
13571 int8_t SEMA4_reserved_0010[48];
13572 /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */
13573 SEMA4_CP0INE_16B_tag CP0INE; /* offset: 0x0040 size: 16 bit */
13574 int8_t SEMA4_reserved_0042[6];
13575 /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */
13576 SEMA4_CP1INE_16B_tag CP1INE; /* offset: 0x0048 size: 16 bit */
13577 int8_t SEMA4_reserved_004A[54];
13578 /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */
13579 SEMA4_CP0NTF_16B_tag CP0NTF; /* offset: 0x0080 size: 16 bit */
13580 int8_t SEMA4_reserved_0082[6];
13581 /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */
13582 SEMA4_CP1NTF_16B_tag CP1NTF; /* offset: 0x0088 size: 16 bit */
13583 int8_t SEMA4_reserved_008A[118];
13584 /* SEMA4_RSTGT - Semaphores Reset Gate */
13585 SEMA4_RSTGT_16B_tag RSTGT; /* offset: 0x0100 size: 16 bit */
13586 int8_t SEMA4_reserved_0102[2];
13587 /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */
13588 SEMA4_RSTNTF_16B_tag RSTNTF; /* offset: 0x0104 size: 16 bit */
13589 } SEMA4_tag;
13590
13591
13592#define SEMA4 (*(volatile SEMA4_tag *) 0xFFF24000UL)
13593
13594
13595
13596/****************************************************************/
13597/* */
13598/* Module: SWT */
13599/* */
13600/****************************************************************/
13601
13602 typedef union { /* SWT_CR - Control Register */
13603 uint32_t R;
13604 struct {
13605 uint32_t MAP0:1; /* Master Acces Protection for Master 0 */
13606 uint32_t MAP1:1; /* Master Acces Protection for Master 1 */
13607 uint32_t MAP2:1; /* Master Acces Protection for Master 2 */
13608 uint32_t MAP3:1; /* Master Acces Protection for Master 3 */
13609 uint32_t MAP4:1; /* Master Acces Protection for Master 4 */
13610 uint32_t MAP5:1; /* Master Acces Protection for Master 5 */
13611 uint32_t MAP6:1; /* Master Acces Protection for Master 6 */
13612 uint32_t MAP7:1; /* Master Acces Protection for Master 7 */
13613 uint32_t:14;
13614 uint32_t KEY:1; /* Keyed Service Mode */
13615 uint32_t RIA:1; /* Reset on Invalid Access */
13616 uint32_t WND:1; /* Window Mode */
13617 uint32_t ITR:1; /* Interrupt Then Reset */
13618 uint32_t HLK:1; /* Hard Lock */
13619 uint32_t SLK:1; /* Soft Lock */
13620 uint32_t:1;
13621 uint32_t STP:1; /* Stop Mode Control */
13622 uint32_t FRZ:1; /* Debug Mode Control */
13623 uint32_t WEN:1; /* Watchdog Enabled */
13624 } B;
13625 } SWT_CR_32B_tag;
13626
13627 typedef union { /* SWT_IR - SWT Interrupt Register */
13628 uint32_t R;
13629 struct {
13630 uint32_t:31;
13631 uint32_t TIF:1; /* Time Out Interrupt Flag */
13632 } B;
13633 } SWT_IR_32B_tag;
13634
13635 typedef union { /* SWT_TO - SWT Time-Out Register */
13636 uint32_t R;
13637 struct {
13638 uint32_t WTO:32; /* Watchdog Time Out Period */
13639 } B;
13640 } SWT_TO_32B_tag;
13641
13642 typedef union { /* SWT_WN - SWT Window Register */
13643 uint32_t R;
13644 struct {
13645 uint32_t WST:32; /* Watchdog Time Out Period */
13646 } B;
13647 } SWT_WN_32B_tag;
13648
13649 typedef union { /* SWT_SR - SWT Service Register */
13650 uint32_t R;
13651 struct {
13652 uint32_t:16;
13653 uint32_t WSC:16; /* Watchdog Service Code */
13654 } B;
13655 } SWT_SR_32B_tag;
13656
13657 typedef union { /* SWT_CO - SWT Counter Output Register */
13658 uint32_t R;
13659 struct {
13660 uint32_t CNT:32; /* Watchdog Count */
13661 } B;
13662 } SWT_CO_32B_tag;
13663
13664 typedef union { /* SWT_SK - SWT Service Key Register */
13665 uint32_t R;
13666 struct {
13667 uint32_t:16;
13668 uint32_t SERVICEKEY:16; /* Service Key */
13669 } B;
13670 } SWT_SK_32B_tag;
13671
13672
13673
13674 typedef struct SWT_struct_tag { /* start of SWT_tag */
13675 /* SWT_CR - Control Register */
13676 SWT_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */
13677 /* SWT_IR - SWT Interrupt Register */
13678 SWT_IR_32B_tag IR; /* offset: 0x0004 size: 32 bit */
13679 /* SWT_TO - SWT Time-Out Register */
13680 SWT_TO_32B_tag TO; /* offset: 0x0008 size: 32 bit */
13681 /* SWT_WN - SWT Window Register */
13682 SWT_WN_32B_tag WN; /* offset: 0x000C size: 32 bit */
13683 /* SWT_SR - SWT Service Register */
13684 SWT_SR_32B_tag SR; /* offset: 0x0010 size: 32 bit */
13685 /* SWT_CO - SWT Counter Output Register */
13686 SWT_CO_32B_tag CO; /* offset: 0x0014 size: 32 bit */
13687 /* SWT_SK - SWT Service Key Register */
13688 SWT_SK_32B_tag SK; /* offset: 0x0018 size: 32 bit */
13689 } SWT_tag;
13690
13691
13692#define SWT (*(volatile SWT_tag *) 0xFFF38000UL)
13693
13694
13695
13696/****************************************************************/
13697/* */
13698/* Module: STM */
13699/* */
13700/****************************************************************/
13701
13702 typedef union { /* STM_CR - Control Register */
13703 uint32_t R;
13704 struct {
13705 uint32_t:16;
13706 uint32_t CPS:8; /* Counter Prescaler */
13707 uint32_t:6;
13708 uint32_t FRZ:1; /* Freeze Control */
13709 uint32_t TEN:1; /* Timer Counter Enabled */
13710 } B;
13711 } STM_CR_32B_tag;
13712
13713 typedef union { /* STM_CNT - STM Count Register */
13714 uint32_t R;
13715 } STM_CNT_32B_tag;
13716
13717
13718 /* Register layout for all registers CCR... */
13719
13720 typedef union { /* STM_CCRn - STM Channel Control Register */
13721 uint32_t R;
13722 struct {
13723 uint32_t:31;
13724 uint32_t CEN:1; /* Channel Enable */
13725 } B;
13726 } STM_CCR_32B_tag;
13727
13728
13729 /* Register layout for all registers CIR... */
13730
13731 typedef union { /* STM_CIRn - STM Channel Interrupt Register */
13732 uint32_t R;
13733 struct {
13734 uint32_t:31;
13735 uint32_t CIF:1; /* Channel Interrupt Flag */
13736 } B;
13737 } STM_CIR_32B_tag;
13738
13739
13740 /* Register layout for all registers CMP... */
13741
13742 typedef union { /* STM_CMPn - STM Channel Compare Register */
13743 uint32_t R;
13744 } STM_CMP_32B_tag;
13745
13746
13747 typedef struct STM_CHANNEL_struct_tag {
13748
13749 /* STM_CCRn - STM Channel Control Register */
13750 STM_CCR_32B_tag CCR; /* relative offset: 0x0000 */
13751 /* STM_CIRn - STM Channel Interrupt Register */
13752 STM_CIR_32B_tag CIR; /* relative offset: 0x0004 */
13753 /* STM_CMPn - STM Channel Compare Register */
13754 STM_CMP_32B_tag CMP; /* relative offset: 0x0008 */
13755 int8_t STM_CHANNEL_reserved_000C[4];
13756
13757 } STM_CHANNEL_tag;
13758
13759
13760 typedef struct STM_struct_tag { /* start of STM_tag */
13761 union {
13762 STM_CR_32B_tag CR0; /* deprecated - please avoid */
13763
13764 /* STM_CR - Control Register */
13765 STM_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */
13766
13767 };
13768 union {
13769 STM_CNT_32B_tag CNT0; /* deprecated - please avoid */
13770
13771 /* STM_CNT - STM Count Register */
13772 STM_CNT_32B_tag CNT; /* offset: 0x0004 size: 32 bit */
13773
13774 };
13775 int8_t STM_reserved_0008_C[8];
13776 union {
13777 /* Register set CHANNEL */
13778 STM_CHANNEL_tag CHANNEL[4]; /* offset: 0x0010 (0x0010 x 4) */
13779
13780 struct {
13781 /* STM_CCRn - STM Channel Control Register */
13782 STM_CCR_32B_tag CCR0; /* offset: 0x0010 size: 32 bit */
13783 /* STM_CIRn - STM Channel Interrupt Register */
13784 STM_CIR_32B_tag CIR0; /* offset: 0x0014 size: 32 bit */
13785 /* STM_CMPn - STM Channel Compare Register */
13786 STM_CMP_32B_tag CMP0; /* offset: 0x0018 size: 32 bit */
13787 int8_t STM_reserved_001C_I1[4];
13788 /* STM_CCRn - STM Channel Control Register */
13789 STM_CCR_32B_tag CCR1; /* offset: 0x0020 size: 32 bit */
13790 /* STM_CIRn - STM Channel Interrupt Register */
13791 STM_CIR_32B_tag CIR1; /* offset: 0x0024 size: 32 bit */
13792 /* STM_CMPn - STM Channel Compare Register */
13793 STM_CMP_32B_tag CMP1; /* offset: 0x0028 size: 32 bit */
13794 int8_t STM_reserved_002C_I1[4];
13795 /* STM_CCRn - STM Channel Control Register */
13796 STM_CCR_32B_tag CCR2; /* offset: 0x0030 size: 32 bit */
13797 /* STM_CIRn - STM Channel Interrupt Register */
13798 STM_CIR_32B_tag CIR2; /* offset: 0x0034 size: 32 bit */
13799 /* STM_CMPn - STM Channel Compare Register */
13800 STM_CMP_32B_tag CMP2; /* offset: 0x0038 size: 32 bit */
13801 int8_t STM_reserved_003C_I1[4];
13802 /* STM_CCRn - STM Channel Control Register */
13803 STM_CCR_32B_tag CCR3; /* offset: 0x0040 size: 32 bit */
13804 /* STM_CIRn - STM Channel Interrupt Register */
13805 STM_CIR_32B_tag CIR3; /* offset: 0x0044 size: 32 bit */
13806 /* STM_CMPn - STM Channel Compare Register */
13807 STM_CMP_32B_tag CMP3; /* offset: 0x0048 size: 32 bit */
13808 int8_t STM_reserved_004C_E1[4];
13809 };
13810
13811 };
13812 } STM_tag;
13813
13814
13815#define STM (*(volatile STM_tag *) 0xFFF3C000UL)
13816
13817
13818
13819/****************************************************************/
13820/* */
13821/* Module: SPP_MCM */
13822/* */
13823/****************************************************************/
13824
13825 typedef union { /* SPP_MCM_PCT - Processor Core Type */
13826 uint16_t R;
13827 struct {
13828 uint16_t PCTYPE:16; /* Processor Core Type */
13829 } B;
13830 } SPP_MCM_PCT_16B_tag;
13831
13832 typedef union { /* SPP_MCM_PLREV - SOC-Defined Platform Revision */
13833 uint16_t R;
13834 struct {
13835 uint16_t PLREVISION:16; /* Platform Revision */
13836 } B;
13837 } SPP_MCM_PLREV_16B_tag;
13838
13839 typedef union { /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */
13840 uint32_t R;
13841 struct {
13842 uint32_t PMC:32; /* IPS Module Configuration */
13843 } B;
13844 } SPP_MCM_IOPMC_32B_tag;
13845
13846 typedef union { /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */
13847 uint8_t R;
13848 struct {
13849 uint8_t POR:1; /* Power on Reset */
13850#ifndef USE_FIELD_ALIASES_SPP_MCM
13851 uint8_t OFPLR:1; /* Off-Platform Reset */
13852#else
13853 uint8_t DIR:1; /* deprecated name - please avoid */
13854#endif
13855 uint8_t:6;
13856 } B;
13857 } SPP_MCM_MRSR_8B_tag;
13858
13859 typedef union { /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */
13860 uint8_t R;
13861 struct {
13862 uint8_t ENBWCR:1; /* Enable WCR */
13863 uint8_t:3;
13864 uint8_t PRILVL:4; /* Interrupt Priority Level */
13865 } B;
13866 } SPP_MCM_MWCR_8B_tag;
13867
13868 typedef union { /* SPP_MCM_MIR - Miscellaneous Interrupt Register */
13869 uint8_t R;
13870 struct {
13871 uint8_t FB0AI:1; /* Flash Bank 0 Abort Interrupt */
13872 uint8_t FB0SI:1; /* Flash Bank 0 Stall Interrupt */
13873 uint8_t FB1AI:1; /* Flash Bank 1 Abort Interrupt */
13874 uint8_t FB1SI:1; /* Flash Bank 1 Stall Interrupt */
13875 uint8_t FB2AI:1; /* Flash Bank 2 Abort Interrupt */
13876 uint8_t FB2SI:1; /* Flash Bank 2 Stall Interrupt */
13877 uint8_t:2;
13878 } B;
13879 } SPP_MCM_MIR_8B_tag;
13880
13881 typedef union { /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */
13882 uint32_t R;
13883 struct {
13884 uint32_t MUSERDCR:32; /* User Defined Control Register */
13885 } B;
13886 } SPP_MCM_MUDCR_32B_tag;
13887
13888 typedef union { /* SPP_MCM_ECR - ECC Configuration Register */
13889 uint8_t R;
13890 struct {
13891 uint8_t:2;
13892#ifndef USE_FIELD_ALIASES_SPP_MCM
13893 uint8_t EPR1BR:1; /* Enable Platform RAM 1-bit Reporting */
13894#else
13895 uint8_t ER1BR:1; /* deprecated name - please avoid */
13896#endif
13897#ifndef USE_FIELD_ALIASES_SPP_MCM
13898 uint8_t EPF1BR:1; /* Enable Platform FLASH 1-bit Reporting */
13899#else
13900 uint8_t EF1BR:1; /* deprecated name - please avoid */
13901#endif
13902 uint8_t:2;
13903#ifndef USE_FIELD_ALIASES_SPP_MCM
13904 uint8_t EPRNCR:1; /* Enable Platform RAM Non-Correctable Reporting */
13905#else
13906 uint8_t ERNCR:1; /* deprecated name - please avoid */
13907#endif
13908#ifndef USE_FIELD_ALIASES_SPP_MCM
13909 uint8_t EPFNCR:1; /* Enable Platform FLASH Non-Correctable Reporting */
13910#else
13911 uint8_t EFNCR:1; /* deprecated name - please avoid */
13912#endif
13913 } B;
13914 } SPP_MCM_ECR_8B_tag;
13915
13916 typedef union { /* SPP_MCM_ESR - ECC Status Register */
13917 uint8_t R;
13918 struct {
13919 uint8_t:2;
13920#ifndef USE_FIELD_ALIASES_SPP_MCM
13921 uint8_t PR1BC:1; /* Platform RAM 1-bit Correction */
13922#else
13923 uint8_t R1BC:1; /* deprecated name - please avoid */
13924#endif
13925#ifndef USE_FIELD_ALIASES_SPP_MCM
13926 uint8_t PF1BC:1; /* Platform FLASH 1-bit Correction */
13927#else
13928 uint8_t F1BC:1; /* deprecated name - please avoid */
13929#endif
13930 uint8_t:2;
13931#ifndef USE_FIELD_ALIASES_SPP_MCM
13932 uint8_t PRNCE:1; /* Platform RAM Non-Correctable Error */
13933#else
13934 uint8_t RNCE:1; /* deprecated name - please avoid */
13935#endif
13936#ifndef USE_FIELD_ALIASES_SPP_MCM
13937 uint8_t PFNCE:1; /* Platform FLASH Non-Correctable Error */
13938#else
13939 uint8_t FNCE:1; /* deprecated name - please avoid */
13940#endif
13941 } B;
13942 } SPP_MCM_ESR_8B_tag;
13943
13944 typedef union { /* SPP_MCM_EEGR - ECC Error Generation Register */
13945 uint16_t R;
13946 struct {
13947 uint16_t FRCAP:1; /* Force Platform RAM Error Injection Access Protection */
13948 uint16_t:1;
13949 uint16_t FRC1BI:1; /* Force Platform RAM Continuous 1-Bit Data Inversions */
13950 uint16_t FR11BI:1; /* Force Platform RAM One 1-Bit Data Inversion */
13951 uint16_t:2;
13952 uint16_t FRCNCI:1; /* Force Platform RAM Continuous Noncorrectable Data Inversions */
13953 uint16_t FR1NCI:1; /* Force Platform RAM One Noncorrectable Data Inversions */
13954 uint16_t:1;
13955 uint16_t ERRBIT:7; /* Error Bit Position */
13956 } B;
13957 } SPP_MCM_EEGR_16B_tag;
13958
13959 typedef union { /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */
13960 uint32_t R;
13961 } SPP_MCM_PFEAR_32B_tag;
13962
13963 typedef union { /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */
13964 uint8_t R;
13965 } SPP_MCM_PFEMR_8B_tag;
13966
13967 typedef union { /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */
13968 uint8_t R;
13969 struct {
13970#ifndef USE_FIELD_ALIASES_SPP_MCM
13971 uint8_t F_WRITE:1; /* AMBA-AHBH Write */
13972#else
13973 uint8_t WRITE:1; /* deprecated name - please avoid */
13974#endif
13975#ifndef USE_FIELD_ALIASES_SPP_MCM
13976 uint8_t F_SIZE:3; /* AMBA-AHBH Size */
13977#else
13978 uint8_t SIZE:3; /* deprecated name - please avoid */
13979#endif
13980#ifndef USE_FIELD_ALIASES_SPP_MCM
13981 uint8_t F_PROTECT:4; /* AMBA-AHBH PROT */
13982#else
13983 uint8_t PROTECTION:4; /* deprecated name - please avoid */
13984#endif
13985 } B;
13986 } SPP_MCM_PFEAT_8B_tag;
13987
13988 typedef union { /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */
13989 uint32_t R;
13990 } SPP_MCM_PFEDRH_32B_tag;
13991
13992 typedef union { /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */
13993 uint32_t R;
13994 } SPP_MCM_PFEDR_32B_tag;
13995
13996 typedef union { /* SPP_MCM_PREAR - Platform RAM ECC Address Register */
13997 uint32_t R;
13998 } SPP_MCM_PREAR_32B_tag;
13999
14000 typedef union { /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */
14001 uint8_t R;
14002 } SPP_MCM_PRESR_8B_tag;
14003
14004 typedef union { /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */
14005 uint8_t R;
14006 struct {
14007 uint8_t:4;
14008#ifndef USE_FIELD_ALIASES_SPP_MCM
14009 uint8_t PR_EMR:4; /* Platform RAM ECC Master Number */
14010#else
14011 uint8_t REMR:4; /* deprecated name - please avoid */
14012#endif
14013 } B;
14014 } SPP_MCM_PREMR_8B_tag;
14015
14016 typedef union { /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */
14017 uint8_t R;
14018 struct {
14019#ifndef USE_FIELD_ALIASES_SPP_MCM
14020 uint8_t R_WRITE:1; /* AMBA-AHBH Write */
14021#else
14022 uint8_t WRITE:1; /* deprecated name - please avoid */
14023#endif
14024#ifndef USE_FIELD_ALIASES_SPP_MCM
14025 uint8_t R_SIZE:3; /* AMBA-AHBH Size */
14026#else
14027 uint8_t SIZE:3; /* deprecated name - please avoid */
14028#endif
14029#ifndef USE_FIELD_ALIASES_SPP_MCM
14030 uint8_t R_PROTECT:4; /* AMBA-AHBH PROT */
14031#else
14032 uint8_t PROTECTION:4; /* deprecated name - please avoid */
14033#endif
14034 } B;
14035 } SPP_MCM_PREAT_8B_tag;
14036
14037 typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */
14038 uint32_t R;
14039 } SPP_MCM_PREDRH_32B_tag;
14040
14041 typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register */
14042 uint32_t R;
14043 } SPP_MCM_PREDR_32B_tag;
14044
14045
14046
14047 typedef struct SPP_MCM_struct_tag { /* start of SPP_MCM_tag */
14048 /* SPP_MCM_PCT - Processor Core Type */
14049 SPP_MCM_PCT_16B_tag PCT; /* offset: 0x0000 size: 16 bit */
14050 union {
14051 SPP_MCM_PLREV_16B_tag REV; /* deprecated - please avoid */
14052
14053 /* SPP_MCM_PLREV - SOC-Defined Platform Revision */
14054 SPP_MCM_PLREV_16B_tag PLREV; /* offset: 0x0002 size: 16 bit */
14055
14056 };
14057 int8_t SPP_MCM_reserved_0004_C[4];
14058 union {
14059 SPP_MCM_IOPMC_32B_tag MC; /* deprecated - please avoid */
14060
14061 /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */
14062 SPP_MCM_IOPMC_32B_tag IOPMC; /* offset: 0x0008 size: 32 bit */
14063
14064 };
14065 int8_t SPP_MCM_reserved_000C[3];
14066 /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */
14067 SPP_MCM_MRSR_8B_tag MRSR; /* offset: 0x000F size: 8 bit */
14068 int8_t SPP_MCM_reserved_0010[3];
14069 /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */
14070 SPP_MCM_MWCR_8B_tag MWCR; /* offset: 0x0013 size: 8 bit */
14071 int8_t SPP_MCM_reserved_0014[11];
14072 /* SPP_MCM_MIR - Miscellaneous Interrupt Register */
14073 SPP_MCM_MIR_8B_tag MIR; /* offset: 0x001F size: 8 bit */
14074 int8_t SPP_MCM_reserved_0020[4];
14075 /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */
14076 SPP_MCM_MUDCR_32B_tag MUDCR; /* offset: 0x0024 size: 32 bit */
14077 int8_t SPP_MCM_reserved_0028[27];
14078 /* SPP_MCM_ECR - ECC Configuration Register */
14079 SPP_MCM_ECR_8B_tag ECR; /* offset: 0x0043 size: 8 bit */
14080 int8_t SPP_MCM_reserved_0044[3];
14081 /* SPP_MCM_ESR - ECC Status Register */
14082 SPP_MCM_ESR_8B_tag ESR; /* offset: 0x0047 size: 8 bit */
14083 int8_t SPP_MCM_reserved_0048[2];
14084 /* SPP_MCM_EEGR - ECC Error Generation Register */
14085 SPP_MCM_EEGR_16B_tag EEGR; /* offset: 0x004A size: 16 bit */
14086 int8_t SPP_MCM_reserved_004C_C[4];
14087 union {
14088 /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */
14089 SPP_MCM_PFEAR_32B_tag PFEAR; /* offset: 0x0050 size: 32 bit */
14090
14091 SPP_MCM_PFEAR_32B_tag FEAR; /* deprecated - please avoid */
14092
14093 };
14094 int8_t SPP_MCM_reserved_0054_C[2];
14095 union {
14096 /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */
14097 SPP_MCM_PFEMR_8B_tag PFEMR; /* offset: 0x0056 size: 8 bit */
14098
14099 SPP_MCM_PFEMR_8B_tag FEMR; /* deprecated - please avoid */
14100
14101 };
14102 union {
14103 /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */
14104 SPP_MCM_PFEAT_8B_tag PFEAT; /* offset: 0x0057 size: 8 bit */
14105
14106 SPP_MCM_PFEAT_8B_tag FEAT; /* deprecated - please avoid */
14107
14108 };
14109 /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */
14110 SPP_MCM_PFEDRH_32B_tag PFEDRH; /* offset: 0x0058 size: 32 bit */
14111 union {
14112 /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */
14113 SPP_MCM_PFEDR_32B_tag PFEDR; /* offset: 0x005C size: 32 bit */
14114
14115 SPP_MCM_PFEDR_32B_tag FEDR; /* deprecated - please avoid */
14116
14117 };
14118 union {
14119 SPP_MCM_PREAR_32B_tag REAR; /* deprecated - please avoid */
14120
14121 /* SPP_MCM_PREAR - Platform RAM ECC Address Register */
14122 SPP_MCM_PREAR_32B_tag PREAR; /* offset: 0x0060 size: 32 bit */
14123
14124 };
14125 int8_t SPP_MCM_reserved_0064_C;
14126 union {
14127 SPP_MCM_PRESR_8B_tag RESR; /* deprecated - please avoid */
14128
14129 /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */
14130 SPP_MCM_PRESR_8B_tag PRESR; /* offset: 0x0065 size: 8 bit */
14131
14132 };
14133 union {
14134 SPP_MCM_PREMR_8B_tag REMR; /* deprecated - please avoid */
14135
14136 /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */
14137 SPP_MCM_PREMR_8B_tag PREMR; /* offset: 0x0066 size: 8 bit */
14138
14139 };
14140 union {
14141 SPP_MCM_PREAT_8B_tag REAT; /* deprecated - please avoid */
14142
14143 /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */
14144 SPP_MCM_PREAT_8B_tag PREAT; /* offset: 0x0067 size: 8 bit */
14145
14146 };
14147 /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */
14148 SPP_MCM_PREDRH_32B_tag PREDRH; /* offset: 0x0068 size: 32 bit */
14149 union {
14150 SPP_MCM_PREDR_32B_tag REDR; /* deprecated - please avoid */
14151
14152 /* SPP_MCM_PREDR - Platform RAM ECC Data Register */
14153 SPP_MCM_PREDR_32B_tag PREDR; /* offset: 0x006C size: 32 bit */
14154
14155 };
14156 } SPP_MCM_tag;
14157
14158
14159#define SPP_MCM (*(volatile SPP_MCM_tag *) 0xFFF40000UL)
14160
14161
14162
14163/****************************************************************/
14164/* */
14165/* Module: SPP_DMA2 */
14166/* */
14167/****************************************************************/
14168
14169 typedef union { /* SPP_DMA2_DMACR - DMA Control Register */
14170 uint32_t R;
14171 struct {
14172 uint32_t:14;
14173 uint32_t CX:1; /* Cancel Transfer */
14174 uint32_t ECX:1; /* Error Cancel Transfer */
14175 uint32_t GRP3PRI:2; /* Channel Group 3 Priority */
14176 uint32_t GRP2PRI:2; /* Channel Group 2 Priority */
14177 uint32_t GRP1PRI:2; /* Channel Group 1 Priority */
14178 uint32_t GRP0PRI:2; /* Channel Group 0 Priority */
14179 uint32_t EMLM:1; /* Enable Minor Loop Mapping */
14180 uint32_t CLM:1; /* Continuous Link Mode */
14181 uint32_t HALT:1; /* Halt DMA Operations */
14182 uint32_t HOE:1; /* Halt on Error */
14183 uint32_t ERGA:1; /* Enable Round Robin Group Arbitration */
14184 uint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */
14185 uint32_t EDBG:1; /* Enable Debug */
14186 uint32_t EBW:1; /* Enable Buffered Writes */
14187 } B;
14188 } SPP_DMA2_DMACR_32B_tag;
14189
14190 typedef union { /* SPP_DMA2_DMAES - DMA Error Status Register */
14191 uint32_t R;
14192 struct {
14193 uint32_t VLD:1; /* Logical OR of DMAERRH and DMAERRL status bits */
14194 uint32_t:14;
14195 uint32_t ECX:1; /* Transfer Cancelled */
14196 uint32_t GPE:1; /* Group Priority Error */
14197 uint32_t CPE:1; /* Channel Priority Error */
14198 uint32_t ERRCHN:6; /* Error Channel Number or Cancelled Channel Number */
14199 uint32_t SAE:1; /* Source Address Error */
14200 uint32_t SOE:1; /* Source Offset Error */
14201 uint32_t DAE:1; /* Destination Address Error */
14202 uint32_t DOE:1; /* Destination Offset Error */
14203 uint32_t NCE:1; /* Nbytes/Citer Configuration Error */
14204 uint32_t SGE:1; /* Scatter/Gather Configuration Error */
14205 uint32_t SBE:1; /* Source Bus Error */
14206 uint32_t DBE:1; /* Destination Bus Error */
14207 } B;
14208 } SPP_DMA2_DMAES_32B_tag;
14209
14210 typedef union { /* SPP_DMA2_DMAERQH - DMA Enable Request Register */
14211 uint32_t R;
14212 struct {
14213 uint32_t ERQ:32; /* DMA Enable Request */
14214 } B;
14215 } SPP_DMA2_DMAERQH_32B_tag;
14216
14217 typedef union { /* SPP_DMA2_DMAERQL - DMA Enable Request Register */
14218 uint32_t R;
14219 struct {
14220 uint32_t ERQ:32; /* DMA Enable Request */
14221 } B;
14222 } SPP_DMA2_DMAERQL_32B_tag;
14223
14224 typedef union { /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */
14225 uint32_t R;
14226 struct {
14227 uint32_t EEI:32; /* DMA Enable Error Interrupt */
14228 } B;
14229 } SPP_DMA2_DMAEEIH_32B_tag;
14230
14231 typedef union { /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */
14232 uint32_t R;
14233 struct {
14234 uint32_t EEI:32; /* DMA Enable Error Interrupt */
14235 } B;
14236 } SPP_DMA2_DMAEEIL_32B_tag;
14237
14238 typedef union { /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */
14239 uint8_t R;
14240 struct {
14241 uint8_t:1;
14242 uint8_t SERQ:7; /* Set Enable Request */
14243 } B;
14244 } SPP_DMA2_DMASERQ_8B_tag;
14245
14246 typedef union { /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */
14247 uint8_t R;
14248 struct {
14249 uint8_t:1;
14250 uint8_t CERQ:7; /* Clear Enable Request */
14251 } B;
14252 } SPP_DMA2_DMACERQ_8B_tag;
14253
14254 typedef union { /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */
14255 uint8_t R;
14256 struct {
14257 uint8_t:1;
14258 uint8_t SEEI:7; /* Set Enable Error Interrupt */
14259 } B;
14260 } SPP_DMA2_DMASEEI_8B_tag;
14261
14262 typedef union { /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */
14263 uint8_t R;
14264 struct {
14265 uint8_t:1;
14266 uint8_t CEEI:7; /* Clear Enable Error Interrupt */
14267 } B;
14268 } SPP_DMA2_DMACEEI_8B_tag;
14269
14270 typedef union { /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */
14271 uint8_t R;
14272 struct {
14273 uint8_t:1;
14274 uint8_t CINT:7; /* Clear Interrupt Request */
14275 } B;
14276 } SPP_DMA2_DMACINT_8B_tag;
14277
14278 typedef union { /* SPP_DMA2_DMACERR - DMA Clear Error */
14279 uint8_t R;
14280 struct {
14281 uint8_t:1;
14282 uint8_t CERR:7; /* Clear Error Indicator */
14283 } B;
14284 } SPP_DMA2_DMACERR_8B_tag;
14285
14286 typedef union { /* SPP_DMA2_DMASSRT - DMA Set START Bit */
14287 uint8_t R;
14288 struct {
14289 uint8_t:1;
14290 uint8_t SSRT:7; /* Set START Bit */
14291 } B;
14292 } SPP_DMA2_DMASSRT_8B_tag;
14293
14294 typedef union { /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */
14295 uint8_t R;
14296 struct {
14297 uint8_t:1;
14298 uint8_t CDNE:7; /* Clear DONE Status Bit */
14299 } B;
14300 } SPP_DMA2_DMACDNE_8B_tag;
14301
14302 typedef union { /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */
14303 uint32_t R;
14304 struct {
14305 uint32_t INT:32; /* DMA Interrupt Request */
14306 } B;
14307 } SPP_DMA2_DMAINTH_32B_tag;
14308
14309 typedef union { /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */
14310 uint32_t R;
14311 struct {
14312 uint32_t INT:32; /* DMA Interrupt Request */
14313 } B;
14314 } SPP_DMA2_DMAINTL_32B_tag;
14315
14316 typedef union { /* SPP_DMA2_DMAERRH - DMA Error Register */
14317 uint32_t R;
14318 struct {
14319 uint32_t ERR:32; /* DMA Error n */
14320 } B;
14321 } SPP_DMA2_DMAERRH_32B_tag;
14322
14323 typedef union { /* SPP_DMA2_DMAERRL - DMA Error Register */
14324 uint32_t R;
14325 struct {
14326 uint32_t ERR:32; /* DMA Error n */
14327 } B;
14328 } SPP_DMA2_DMAERRL_32B_tag;
14329
14330 typedef union { /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */
14331 uint32_t R;
14332 struct {
14333 uint32_t HRS:32; /* DMA Hardware Request Status */
14334 } B;
14335 } SPP_DMA2_DMAHRSH_32B_tag;
14336
14337 typedef union { /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */
14338 uint32_t R;
14339 struct {
14340 uint32_t HRS:32; /* DMA Hardware Request Status */
14341 } B;
14342 } SPP_DMA2_DMAHRSL_32B_tag;
14343
14344 typedef union { /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */
14345 uint32_t R;
14346 struct {
14347 uint32_t GPOR:32; /* DMA General Purpose Output */
14348 } B;
14349 } SPP_DMA2_DMAGPOR_32B_tag;
14350
14351
14352 /* Register layout for all registers DCHPRI... */
14353
14354 typedef union { /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */
14355 uint8_t R;
14356 struct {
14357 uint8_t ECP:1; /* Enable Channel Preemption */
14358 uint8_t DPA:1; /* Disable Preempt Ability */
14359 uint8_t GRPPRI:2; /* Channel n Current Group Priority */
14360 uint8_t CHPRI:4; /* Channel n Arbitration Priority */
14361 } B;
14362 } SPP_DMA2_DCHPRI_8B_tag;
14363
14364
14365 /* Register layout for all registers TCDWORD0_... */
14366
14367 typedef union { /* SPP_DMA2_TCDn Word0 - Source Address */
14368 uint32_t R;
14369 struct {
14370 uint32_t SADDR:32; /* Source Address */
14371 } B;
14372 } SPP_DMA2_TCDWORD0__32B_tag;
14373
14374
14375 /* Register layout for all registers TCDWORD4_... */
14376
14377 typedef union { /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14378 uint32_t R;
14379 struct {
14380 uint32_t SMOD:5; /* Source Address Modulo */
14381 uint32_t SSIZE:3; /* Source Data Transfer Size */
14382 uint32_t DMOD:5; /* Destination Address Module */
14383 uint32_t DSIZE:3; /* Destination Data Transfer Size */
14384 uint32_t SOFF:16; /* Source Address Signed Offset */
14385 } B;
14386 } SPP_DMA2_TCDWORD4__32B_tag;
14387
14388
14389 /* Register layout for all registers TCDWORD8_... */
14390
14391 typedef union { /* SPP_DMA2_TCDn Word2 - nbytes */
14392 uint32_t R;
14393 struct {
14394 uint32_t SMLOE:1; /* Source Minor Loop Offset Enable */
14395 uint32_t DMLOE:1; /* Destination Minor Loop Offset Enable */
14396 uint32_t MLOFF:20; /* Minor Loop Offset */
14397 uint32_t NBYTES:10; /* Inner Minor byte transfer Count */
14398 } B;
14399 } SPP_DMA2_TCDWORD8__32B_tag;
14400
14401
14402 /* Register layout for all registers TCDWORD12_... */
14403
14404 typedef union { /* SPP_DMA2_TCDn Word3 - slast */
14405 uint32_t R;
14406 struct {
14407 uint32_t SLAST:32; /* Last Source Address Adjustment */
14408 } B;
14409 } SPP_DMA2_TCDWORD12__32B_tag;
14410
14411
14412 /* Register layout for all registers TCDWORD16_... */
14413
14414 typedef union { /* SPP_DMA2_TCDn Word4 - daddr */
14415 uint32_t R;
14416 struct {
14417 uint32_t DADDR:32; /* Destination Address */
14418 } B;
14419 } SPP_DMA2_TCDWORD16__32B_tag;
14420
14421
14422 /* Register layout for all registers TCDWORD20_... */
14423
14424 typedef union { /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14425 uint32_t R;
14426 struct {
14427 uint32_t CITER_E_LINK:1; /* Enable Channel to channel linking on minor loop complete */
14428 uint32_t CITER_LINKCH:6; /* Link Channel Number */
14429 uint32_t CITER:9; /* Current Major Iteration Count */
14430 uint32_t DOFF:16; /* Destination Address Signed Offset */
14431 } B;
14432 } SPP_DMA2_TCDWORD20__32B_tag;
14433
14434
14435 /* Register layout for all registers TCDWORD24_... */
14436
14437 typedef union { /* SPP_DMA2_TCDn Word6 - dlast_sga */
14438 uint32_t R;
14439 struct {
14440 uint32_t DLAST_SGA:32; /* Last destination address adjustment */
14441 } B;
14442 } SPP_DMA2_TCDWORD24__32B_tag;
14443
14444
14445 /* Register layout for all registers TCDWORD28_... */
14446
14447 typedef union { /* SPP_DMA2_TCDn Word7 - biter, etc. */
14448 uint32_t R;
14449 struct {
14450
14451#ifndef USE_FIELD_ALIASES_SPP_DMA2
14452 uint32_t BITER_E_LINK:1; /* beginning ("major") iteration count */
14453#else
14454 uint32_t BITERE_LINK:1; /* deprecated name - please avoid */
14455#endif
14456 uint32_t BITER:15; /* Enable Channel to Channel linking on minor loop complete */
14457 uint32_t BWC:2; /* Bandwidth Control */
14458 uint32_t MAJOR_LINKCH:6; /* Link Channel Number */
14459 uint32_t DONE:1; /* channel done */
14460 uint32_t ACTIVE:1; /* Channel Active */
14461 uint32_t MAJOR_E_LINK:1; /* Enable Channel to Channel Linking on major loop complete */
14462 uint32_t E_SG:1; /* Enable Scatter/Gather Processing */
14463 uint32_t D_REQ:1; /* Disable Request */
14464 uint32_t INT_HALF:1; /* Enable an Interrupt when Major Counter is half complete */
14465 uint32_t INT_MAJ:1; /* Enable an Interrupt when Major Iteration count completes */
14466 uint32_t START:1; /* Channel Start */
14467 } B;
14468 } SPP_DMA2_TCDWORD28__32B_tag;
14469
14470
14471 typedef struct SPP_DMA2_CHANNEL_struct_tag {
14472
14473 /* SPP_DMA2_TCDn Word0 - Source Address */
14474 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_; /* relative offset: 0x0000 */
14475 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14476 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_; /* relative offset: 0x0004 */
14477 /* SPP_DMA2_TCDn Word2 - nbytes */
14478 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_; /* relative offset: 0x0008 */
14479 /* SPP_DMA2_TCDn Word3 - slast */
14480 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_; /* relative offset: 0x000C */
14481 /* SPP_DMA2_TCDn Word4 - daddr */
14482 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_; /* relative offset: 0x0010 */
14483 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14484 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_; /* relative offset: 0x0014 */
14485 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14486 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_; /* relative offset: 0x0018 */
14487 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14488 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_; /* relative offset: 0x001C */
14489
14490 } SPP_DMA2_CHANNEL_tag;
14491
14492
14493 typedef struct SPP_DMA2_struct_tag { /* start of SPP_DMA2_tag */
14494 /* SPP_DMA2_DMACR - DMA Control Register */
14495 SPP_DMA2_DMACR_32B_tag DMACR; /* offset: 0x0000 size: 32 bit */
14496 /* SPP_DMA2_DMAES - DMA Error Status Register */
14497 SPP_DMA2_DMAES_32B_tag DMAES; /* offset: 0x0004 size: 32 bit */
14498 /* SPP_DMA2_DMAERQH - DMA Enable Request Register */
14499 SPP_DMA2_DMAERQH_32B_tag DMAERQH; /* offset: 0x0008 size: 32 bit */
14500 /* SPP_DMA2_DMAERQL - DMA Enable Request Register */
14501 SPP_DMA2_DMAERQL_32B_tag DMAERQL; /* offset: 0x000C size: 32 bit */
14502 /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */
14503 SPP_DMA2_DMAEEIH_32B_tag DMAEEIH; /* offset: 0x0010 size: 32 bit */
14504 /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */
14505 SPP_DMA2_DMAEEIL_32B_tag DMAEEIL; /* offset: 0x0014 size: 32 bit */
14506 /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */
14507 SPP_DMA2_DMASERQ_8B_tag DMASERQ; /* offset: 0x0018 size: 8 bit */
14508 /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */
14509 SPP_DMA2_DMACERQ_8B_tag DMACERQ; /* offset: 0x0019 size: 8 bit */
14510 /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */
14511 SPP_DMA2_DMASEEI_8B_tag DMASEEI; /* offset: 0x001A size: 8 bit */
14512 /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */
14513 SPP_DMA2_DMACEEI_8B_tag DMACEEI; /* offset: 0x001B size: 8 bit */
14514 /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */
14515 SPP_DMA2_DMACINT_8B_tag DMACINT; /* offset: 0x001C size: 8 bit */
14516 /* SPP_DMA2_DMACERR - DMA Clear Error */
14517 SPP_DMA2_DMACERR_8B_tag DMACERR; /* offset: 0x001D size: 8 bit */
14518 /* SPP_DMA2_DMASSRT - DMA Set START Bit */
14519 SPP_DMA2_DMASSRT_8B_tag DMASSRT; /* offset: 0x001E size: 8 bit */
14520 /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */
14521 SPP_DMA2_DMACDNE_8B_tag DMACDNE; /* offset: 0x001F size: 8 bit */
14522 /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */
14523 SPP_DMA2_DMAINTH_32B_tag DMAINTH; /* offset: 0x0020 size: 32 bit */
14524 /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */
14525 SPP_DMA2_DMAINTL_32B_tag DMAINTL; /* offset: 0x0024 size: 32 bit */
14526 /* SPP_DMA2_DMAERRH - DMA Error Register */
14527 SPP_DMA2_DMAERRH_32B_tag DMAERRH; /* offset: 0x0028 size: 32 bit */
14528 /* SPP_DMA2_DMAERRL - DMA Error Register */
14529 SPP_DMA2_DMAERRL_32B_tag DMAERRL; /* offset: 0x002C size: 32 bit */
14530 /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */
14531 SPP_DMA2_DMAHRSH_32B_tag DMAHRSH; /* offset: 0x0030 size: 32 bit */
14532 /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */
14533 SPP_DMA2_DMAHRSL_32B_tag DMAHRSL; /* offset: 0x0034 size: 32 bit */
14534 /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */
14535 SPP_DMA2_DMAGPOR_32B_tag DMAGPOR; /* offset: 0x0038 size: 32 bit */
14536 int8_t SPP_DMA2_reserved_003C_C[196];
14537 union {
14538 /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */
14539 SPP_DMA2_DCHPRI_8B_tag DCHPRI[64]; /* offset: 0x0100 (0x0001 x 64) */
14540
14541 struct {
14542 /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */
14543 SPP_DMA2_DCHPRI_8B_tag DCHPRI0; /* offset: 0x0100 size: 8 bit */
14544 SPP_DMA2_DCHPRI_8B_tag DCHPRI1; /* offset: 0x0101 size: 8 bit */
14545 SPP_DMA2_DCHPRI_8B_tag DCHPRI2; /* offset: 0x0102 size: 8 bit */
14546 SPP_DMA2_DCHPRI_8B_tag DCHPRI3; /* offset: 0x0103 size: 8 bit */
14547 SPP_DMA2_DCHPRI_8B_tag DCHPRI4; /* offset: 0x0104 size: 8 bit */
14548 SPP_DMA2_DCHPRI_8B_tag DCHPRI5; /* offset: 0x0105 size: 8 bit */
14549 SPP_DMA2_DCHPRI_8B_tag DCHPRI6; /* offset: 0x0106 size: 8 bit */
14550 SPP_DMA2_DCHPRI_8B_tag DCHPRI7; /* offset: 0x0107 size: 8 bit */
14551 SPP_DMA2_DCHPRI_8B_tag DCHPRI8; /* offset: 0x0108 size: 8 bit */
14552 SPP_DMA2_DCHPRI_8B_tag DCHPRI9; /* offset: 0x0109 size: 8 bit */
14553 SPP_DMA2_DCHPRI_8B_tag DCHPRI10; /* offset: 0x010A size: 8 bit */
14554 SPP_DMA2_DCHPRI_8B_tag DCHPRI11; /* offset: 0x010B size: 8 bit */
14555 SPP_DMA2_DCHPRI_8B_tag DCHPRI12; /* offset: 0x010C size: 8 bit */
14556 SPP_DMA2_DCHPRI_8B_tag DCHPRI13; /* offset: 0x010D size: 8 bit */
14557 SPP_DMA2_DCHPRI_8B_tag DCHPRI14; /* offset: 0x010E size: 8 bit */
14558 SPP_DMA2_DCHPRI_8B_tag DCHPRI15; /* offset: 0x010F size: 8 bit */
14559 SPP_DMA2_DCHPRI_8B_tag DCHPRI16; /* offset: 0x0110 size: 8 bit */
14560 SPP_DMA2_DCHPRI_8B_tag DCHPRI17; /* offset: 0x0111 size: 8 bit */
14561 SPP_DMA2_DCHPRI_8B_tag DCHPRI18; /* offset: 0x0112 size: 8 bit */
14562 SPP_DMA2_DCHPRI_8B_tag DCHPRI19; /* offset: 0x0113 size: 8 bit */
14563 SPP_DMA2_DCHPRI_8B_tag DCHPRI20; /* offset: 0x0114 size: 8 bit */
14564 SPP_DMA2_DCHPRI_8B_tag DCHPRI21; /* offset: 0x0115 size: 8 bit */
14565 SPP_DMA2_DCHPRI_8B_tag DCHPRI22; /* offset: 0x0116 size: 8 bit */
14566 SPP_DMA2_DCHPRI_8B_tag DCHPRI23; /* offset: 0x0117 size: 8 bit */
14567 SPP_DMA2_DCHPRI_8B_tag DCHPRI24; /* offset: 0x0118 size: 8 bit */
14568 SPP_DMA2_DCHPRI_8B_tag DCHPRI25; /* offset: 0x0119 size: 8 bit */
14569 SPP_DMA2_DCHPRI_8B_tag DCHPRI26; /* offset: 0x011A size: 8 bit */
14570 SPP_DMA2_DCHPRI_8B_tag DCHPRI27; /* offset: 0x011B size: 8 bit */
14571 SPP_DMA2_DCHPRI_8B_tag DCHPRI28; /* offset: 0x011C size: 8 bit */
14572 SPP_DMA2_DCHPRI_8B_tag DCHPRI29; /* offset: 0x011D size: 8 bit */
14573 SPP_DMA2_DCHPRI_8B_tag DCHPRI30; /* offset: 0x011E size: 8 bit */
14574 SPP_DMA2_DCHPRI_8B_tag DCHPRI31; /* offset: 0x011F size: 8 bit */
14575 SPP_DMA2_DCHPRI_8B_tag DCHPRI32; /* offset: 0x0120 size: 8 bit */
14576 SPP_DMA2_DCHPRI_8B_tag DCHPRI33; /* offset: 0x0121 size: 8 bit */
14577 SPP_DMA2_DCHPRI_8B_tag DCHPRI34; /* offset: 0x0122 size: 8 bit */
14578 SPP_DMA2_DCHPRI_8B_tag DCHPRI35; /* offset: 0x0123 size: 8 bit */
14579 SPP_DMA2_DCHPRI_8B_tag DCHPRI36; /* offset: 0x0124 size: 8 bit */
14580 SPP_DMA2_DCHPRI_8B_tag DCHPRI37; /* offset: 0x0125 size: 8 bit */
14581 SPP_DMA2_DCHPRI_8B_tag DCHPRI38; /* offset: 0x0126 size: 8 bit */
14582 SPP_DMA2_DCHPRI_8B_tag DCHPRI39; /* offset: 0x0127 size: 8 bit */
14583 SPP_DMA2_DCHPRI_8B_tag DCHPRI40; /* offset: 0x0128 size: 8 bit */
14584 SPP_DMA2_DCHPRI_8B_tag DCHPRI41; /* offset: 0x0129 size: 8 bit */
14585 SPP_DMA2_DCHPRI_8B_tag DCHPRI42; /* offset: 0x012A size: 8 bit */
14586 SPP_DMA2_DCHPRI_8B_tag DCHPRI43; /* offset: 0x012B size: 8 bit */
14587 SPP_DMA2_DCHPRI_8B_tag DCHPRI44; /* offset: 0x012C size: 8 bit */
14588 SPP_DMA2_DCHPRI_8B_tag DCHPRI45; /* offset: 0x012D size: 8 bit */
14589 SPP_DMA2_DCHPRI_8B_tag DCHPRI46; /* offset: 0x012E size: 8 bit */
14590 SPP_DMA2_DCHPRI_8B_tag DCHPRI47; /* offset: 0x012F size: 8 bit */
14591 SPP_DMA2_DCHPRI_8B_tag DCHPRI48; /* offset: 0x0130 size: 8 bit */
14592 SPP_DMA2_DCHPRI_8B_tag DCHPRI49; /* offset: 0x0131 size: 8 bit */
14593 SPP_DMA2_DCHPRI_8B_tag DCHPRI50; /* offset: 0x0132 size: 8 bit */
14594 SPP_DMA2_DCHPRI_8B_tag DCHPRI51; /* offset: 0x0133 size: 8 bit */
14595 SPP_DMA2_DCHPRI_8B_tag DCHPRI52; /* offset: 0x0134 size: 8 bit */
14596 SPP_DMA2_DCHPRI_8B_tag DCHPRI53; /* offset: 0x0135 size: 8 bit */
14597 SPP_DMA2_DCHPRI_8B_tag DCHPRI54; /* offset: 0x0136 size: 8 bit */
14598 SPP_DMA2_DCHPRI_8B_tag DCHPRI55; /* offset: 0x0137 size: 8 bit */
14599 SPP_DMA2_DCHPRI_8B_tag DCHPRI56; /* offset: 0x0138 size: 8 bit */
14600 SPP_DMA2_DCHPRI_8B_tag DCHPRI57; /* offset: 0x0139 size: 8 bit */
14601 SPP_DMA2_DCHPRI_8B_tag DCHPRI58; /* offset: 0x013A size: 8 bit */
14602 SPP_DMA2_DCHPRI_8B_tag DCHPRI59; /* offset: 0x013B size: 8 bit */
14603 SPP_DMA2_DCHPRI_8B_tag DCHPRI60; /* offset: 0x013C size: 8 bit */
14604 SPP_DMA2_DCHPRI_8B_tag DCHPRI61; /* offset: 0x013D size: 8 bit */
14605 SPP_DMA2_DCHPRI_8B_tag DCHPRI62; /* offset: 0x013E size: 8 bit */
14606 SPP_DMA2_DCHPRI_8B_tag DCHPRI63; /* offset: 0x013F size: 8 bit */
14607 };
14608
14609 };
14610 int8_t SPP_DMA2_reserved_0140_C[3776];
14611 union {
14612 /* Register set CHANNEL */
14613 SPP_DMA2_CHANNEL_tag CHANNEL[64]; /* offset: 0x1000 (0x0020 x 64) */
14614
14615 struct {
14616 /* SPP_DMA2_TCDn Word0 - Source Address */
14617 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_0; /* offset: 0x1000 size: 32 bit */
14618 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14619 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_0; /* offset: 0x1004 size: 32 bit */
14620 /* SPP_DMA2_TCDn Word2 - nbytes */
14621 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_0; /* offset: 0x1008 size: 32 bit */
14622 /* SPP_DMA2_TCDn Word3 - slast */
14623 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_0; /* offset: 0x100C size: 32 bit */
14624 /* SPP_DMA2_TCDn Word4 - daddr */
14625 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_0; /* offset: 0x1010 size: 32 bit */
14626 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14627 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_0; /* offset: 0x1014 size: 32 bit */
14628 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14629 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_0; /* offset: 0x1018 size: 32 bit */
14630 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14631 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_0; /* offset: 0x101C size: 32 bit */
14632 /* SPP_DMA2_TCDn Word0 - Source Address */
14633 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_1; /* offset: 0x1020 size: 32 bit */
14634 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14635 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_1; /* offset: 0x1024 size: 32 bit */
14636 /* SPP_DMA2_TCDn Word2 - nbytes */
14637 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_1; /* offset: 0x1028 size: 32 bit */
14638 /* SPP_DMA2_TCDn Word3 - slast */
14639 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_1; /* offset: 0x102C size: 32 bit */
14640 /* SPP_DMA2_TCDn Word4 - daddr */
14641 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_1; /* offset: 0x1030 size: 32 bit */
14642 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14643 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_1; /* offset: 0x1034 size: 32 bit */
14644 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14645 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_1; /* offset: 0x1038 size: 32 bit */
14646 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14647 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_1; /* offset: 0x103C size: 32 bit */
14648 /* SPP_DMA2_TCDn Word0 - Source Address */
14649 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_2; /* offset: 0x1040 size: 32 bit */
14650 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14651 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_2; /* offset: 0x1044 size: 32 bit */
14652 /* SPP_DMA2_TCDn Word2 - nbytes */
14653 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_2; /* offset: 0x1048 size: 32 bit */
14654 /* SPP_DMA2_TCDn Word3 - slast */
14655 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_2; /* offset: 0x104C size: 32 bit */
14656 /* SPP_DMA2_TCDn Word4 - daddr */
14657 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_2; /* offset: 0x1050 size: 32 bit */
14658 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14659 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_2; /* offset: 0x1054 size: 32 bit */
14660 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14661 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_2; /* offset: 0x1058 size: 32 bit */
14662 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14663 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_2; /* offset: 0x105C size: 32 bit */
14664 /* SPP_DMA2_TCDn Word0 - Source Address */
14665 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_3; /* offset: 0x1060 size: 32 bit */
14666 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14667 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_3; /* offset: 0x1064 size: 32 bit */
14668 /* SPP_DMA2_TCDn Word2 - nbytes */
14669 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_3; /* offset: 0x1068 size: 32 bit */
14670 /* SPP_DMA2_TCDn Word3 - slast */
14671 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_3; /* offset: 0x106C size: 32 bit */
14672 /* SPP_DMA2_TCDn Word4 - daddr */
14673 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_3; /* offset: 0x1070 size: 32 bit */
14674 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14675 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_3; /* offset: 0x1074 size: 32 bit */
14676 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14677 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_3; /* offset: 0x1078 size: 32 bit */
14678 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14679 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_3; /* offset: 0x107C size: 32 bit */
14680 /* SPP_DMA2_TCDn Word0 - Source Address */
14681 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_4; /* offset: 0x1080 size: 32 bit */
14682 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14683 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_4; /* offset: 0x1084 size: 32 bit */
14684 /* SPP_DMA2_TCDn Word2 - nbytes */
14685 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_4; /* offset: 0x1088 size: 32 bit */
14686 /* SPP_DMA2_TCDn Word3 - slast */
14687 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_4; /* offset: 0x108C size: 32 bit */
14688 /* SPP_DMA2_TCDn Word4 - daddr */
14689 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_4; /* offset: 0x1090 size: 32 bit */
14690 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14691 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_4; /* offset: 0x1094 size: 32 bit */
14692 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14693 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_4; /* offset: 0x1098 size: 32 bit */
14694 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14695 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_4; /* offset: 0x109C size: 32 bit */
14696 /* SPP_DMA2_TCDn Word0 - Source Address */
14697 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_5; /* offset: 0x10A0 size: 32 bit */
14698 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14699 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_5; /* offset: 0x10A4 size: 32 bit */
14700 /* SPP_DMA2_TCDn Word2 - nbytes */
14701 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_5; /* offset: 0x10A8 size: 32 bit */
14702 /* SPP_DMA2_TCDn Word3 - slast */
14703 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_5; /* offset: 0x10AC size: 32 bit */
14704 /* SPP_DMA2_TCDn Word4 - daddr */
14705 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_5; /* offset: 0x10B0 size: 32 bit */
14706 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14707 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_5; /* offset: 0x10B4 size: 32 bit */
14708 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14709 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_5; /* offset: 0x10B8 size: 32 bit */
14710 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14711 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_5; /* offset: 0x10BC size: 32 bit */
14712 /* SPP_DMA2_TCDn Word0 - Source Address */
14713 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_6; /* offset: 0x10C0 size: 32 bit */
14714 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14715 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_6; /* offset: 0x10C4 size: 32 bit */
14716 /* SPP_DMA2_TCDn Word2 - nbytes */
14717 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_6; /* offset: 0x10C8 size: 32 bit */
14718 /* SPP_DMA2_TCDn Word3 - slast */
14719 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_6; /* offset: 0x10CC size: 32 bit */
14720 /* SPP_DMA2_TCDn Word4 - daddr */
14721 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_6; /* offset: 0x10D0 size: 32 bit */
14722 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14723 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_6; /* offset: 0x10D4 size: 32 bit */
14724 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14725 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_6; /* offset: 0x10D8 size: 32 bit */
14726 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14727 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_6; /* offset: 0x10DC size: 32 bit */
14728 /* SPP_DMA2_TCDn Word0 - Source Address */
14729 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_7; /* offset: 0x10E0 size: 32 bit */
14730 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14731 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_7; /* offset: 0x10E4 size: 32 bit */
14732 /* SPP_DMA2_TCDn Word2 - nbytes */
14733 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_7; /* offset: 0x10E8 size: 32 bit */
14734 /* SPP_DMA2_TCDn Word3 - slast */
14735 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_7; /* offset: 0x10EC size: 32 bit */
14736 /* SPP_DMA2_TCDn Word4 - daddr */
14737 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_7; /* offset: 0x10F0 size: 32 bit */
14738 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14739 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_7; /* offset: 0x10F4 size: 32 bit */
14740 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14741 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_7; /* offset: 0x10F8 size: 32 bit */
14742 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14743 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_7; /* offset: 0x10FC size: 32 bit */
14744 /* SPP_DMA2_TCDn Word0 - Source Address */
14745 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_8; /* offset: 0x1100 size: 32 bit */
14746 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14747 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_8; /* offset: 0x1104 size: 32 bit */
14748 /* SPP_DMA2_TCDn Word2 - nbytes */
14749 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_8; /* offset: 0x1108 size: 32 bit */
14750 /* SPP_DMA2_TCDn Word3 - slast */
14751 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_8; /* offset: 0x110C size: 32 bit */
14752 /* SPP_DMA2_TCDn Word4 - daddr */
14753 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_8; /* offset: 0x1110 size: 32 bit */
14754 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14755 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_8; /* offset: 0x1114 size: 32 bit */
14756 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14757 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_8; /* offset: 0x1118 size: 32 bit */
14758 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14759 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_8; /* offset: 0x111C size: 32 bit */
14760 /* SPP_DMA2_TCDn Word0 - Source Address */
14761 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_9; /* offset: 0x1120 size: 32 bit */
14762 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14763 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_9; /* offset: 0x1124 size: 32 bit */
14764 /* SPP_DMA2_TCDn Word2 - nbytes */
14765 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_9; /* offset: 0x1128 size: 32 bit */
14766 /* SPP_DMA2_TCDn Word3 - slast */
14767 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_9; /* offset: 0x112C size: 32 bit */
14768 /* SPP_DMA2_TCDn Word4 - daddr */
14769 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_9; /* offset: 0x1130 size: 32 bit */
14770 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14771 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_9; /* offset: 0x1134 size: 32 bit */
14772 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14773 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_9; /* offset: 0x1138 size: 32 bit */
14774 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14775 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_9; /* offset: 0x113C size: 32 bit */
14776 /* SPP_DMA2_TCDn Word0 - Source Address */
14777 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_10; /* offset: 0x1140 size: 32 bit */
14778 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14779 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_10; /* offset: 0x1144 size: 32 bit */
14780 /* SPP_DMA2_TCDn Word2 - nbytes */
14781 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_10; /* offset: 0x1148 size: 32 bit */
14782 /* SPP_DMA2_TCDn Word3 - slast */
14783 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_10; /* offset: 0x114C size: 32 bit */
14784 /* SPP_DMA2_TCDn Word4 - daddr */
14785 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_10; /* offset: 0x1150 size: 32 bit */
14786 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14787 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_10; /* offset: 0x1154 size: 32 bit */
14788 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14789 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_10; /* offset: 0x1158 size: 32 bit */
14790 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14791 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_10; /* offset: 0x115C size: 32 bit */
14792 /* SPP_DMA2_TCDn Word0 - Source Address */
14793 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_11; /* offset: 0x1160 size: 32 bit */
14794 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14795 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_11; /* offset: 0x1164 size: 32 bit */
14796 /* SPP_DMA2_TCDn Word2 - nbytes */
14797 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_11; /* offset: 0x1168 size: 32 bit */
14798 /* SPP_DMA2_TCDn Word3 - slast */
14799 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_11; /* offset: 0x116C size: 32 bit */
14800 /* SPP_DMA2_TCDn Word4 - daddr */
14801 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_11; /* offset: 0x1170 size: 32 bit */
14802 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14803 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_11; /* offset: 0x1174 size: 32 bit */
14804 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14805 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_11; /* offset: 0x1178 size: 32 bit */
14806 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14807 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_11; /* offset: 0x117C size: 32 bit */
14808 /* SPP_DMA2_TCDn Word0 - Source Address */
14809 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_12; /* offset: 0x1180 size: 32 bit */
14810 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14811 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_12; /* offset: 0x1184 size: 32 bit */
14812 /* SPP_DMA2_TCDn Word2 - nbytes */
14813 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_12; /* offset: 0x1188 size: 32 bit */
14814 /* SPP_DMA2_TCDn Word3 - slast */
14815 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_12; /* offset: 0x118C size: 32 bit */
14816 /* SPP_DMA2_TCDn Word4 - daddr */
14817 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_12; /* offset: 0x1190 size: 32 bit */
14818 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14819 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_12; /* offset: 0x1194 size: 32 bit */
14820 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14821 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_12; /* offset: 0x1198 size: 32 bit */
14822 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14823 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_12; /* offset: 0x119C size: 32 bit */
14824 /* SPP_DMA2_TCDn Word0 - Source Address */
14825 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_13; /* offset: 0x11A0 size: 32 bit */
14826 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14827 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_13; /* offset: 0x11A4 size: 32 bit */
14828 /* SPP_DMA2_TCDn Word2 - nbytes */
14829 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_13; /* offset: 0x11A8 size: 32 bit */
14830 /* SPP_DMA2_TCDn Word3 - slast */
14831 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_13; /* offset: 0x11AC size: 32 bit */
14832 /* SPP_DMA2_TCDn Word4 - daddr */
14833 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_13; /* offset: 0x11B0 size: 32 bit */
14834 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14835 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_13; /* offset: 0x11B4 size: 32 bit */
14836 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14837 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_13; /* offset: 0x11B8 size: 32 bit */
14838 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14839 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_13; /* offset: 0x11BC size: 32 bit */
14840 /* SPP_DMA2_TCDn Word0 - Source Address */
14841 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_14; /* offset: 0x11C0 size: 32 bit */
14842 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14843 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_14; /* offset: 0x11C4 size: 32 bit */
14844 /* SPP_DMA2_TCDn Word2 - nbytes */
14845 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_14; /* offset: 0x11C8 size: 32 bit */
14846 /* SPP_DMA2_TCDn Word3 - slast */
14847 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_14; /* offset: 0x11CC size: 32 bit */
14848 /* SPP_DMA2_TCDn Word4 - daddr */
14849 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_14; /* offset: 0x11D0 size: 32 bit */
14850 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14851 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_14; /* offset: 0x11D4 size: 32 bit */
14852 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14853 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_14; /* offset: 0x11D8 size: 32 bit */
14854 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14855 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_14; /* offset: 0x11DC size: 32 bit */
14856 /* SPP_DMA2_TCDn Word0 - Source Address */
14857 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_15; /* offset: 0x11E0 size: 32 bit */
14858 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14859 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_15; /* offset: 0x11E4 size: 32 bit */
14860 /* SPP_DMA2_TCDn Word2 - nbytes */
14861 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_15; /* offset: 0x11E8 size: 32 bit */
14862 /* SPP_DMA2_TCDn Word3 - slast */
14863 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_15; /* offset: 0x11EC size: 32 bit */
14864 /* SPP_DMA2_TCDn Word4 - daddr */
14865 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_15; /* offset: 0x11F0 size: 32 bit */
14866 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14867 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_15; /* offset: 0x11F4 size: 32 bit */
14868 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14869 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_15; /* offset: 0x11F8 size: 32 bit */
14870 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14871 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_15; /* offset: 0x11FC size: 32 bit */
14872 /* SPP_DMA2_TCDn Word0 - Source Address */
14873 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_16; /* offset: 0x1200 size: 32 bit */
14874 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14875 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_16; /* offset: 0x1204 size: 32 bit */
14876 /* SPP_DMA2_TCDn Word2 - nbytes */
14877 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_16; /* offset: 0x1208 size: 32 bit */
14878 /* SPP_DMA2_TCDn Word3 - slast */
14879 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_16; /* offset: 0x120C size: 32 bit */
14880 /* SPP_DMA2_TCDn Word4 - daddr */
14881 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_16; /* offset: 0x1210 size: 32 bit */
14882 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14883 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_16; /* offset: 0x1214 size: 32 bit */
14884 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14885 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_16; /* offset: 0x1218 size: 32 bit */
14886 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14887 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_16; /* offset: 0x121C size: 32 bit */
14888 /* SPP_DMA2_TCDn Word0 - Source Address */
14889 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_17; /* offset: 0x1220 size: 32 bit */
14890 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14891 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_17; /* offset: 0x1224 size: 32 bit */
14892 /* SPP_DMA2_TCDn Word2 - nbytes */
14893 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_17; /* offset: 0x1228 size: 32 bit */
14894 /* SPP_DMA2_TCDn Word3 - slast */
14895 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_17; /* offset: 0x122C size: 32 bit */
14896 /* SPP_DMA2_TCDn Word4 - daddr */
14897 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_17; /* offset: 0x1230 size: 32 bit */
14898 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14899 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_17; /* offset: 0x1234 size: 32 bit */
14900 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14901 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_17; /* offset: 0x1238 size: 32 bit */
14902 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14903 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_17; /* offset: 0x123C size: 32 bit */
14904 /* SPP_DMA2_TCDn Word0 - Source Address */
14905 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_18; /* offset: 0x1240 size: 32 bit */
14906 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14907 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_18; /* offset: 0x1244 size: 32 bit */
14908 /* SPP_DMA2_TCDn Word2 - nbytes */
14909 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_18; /* offset: 0x1248 size: 32 bit */
14910 /* SPP_DMA2_TCDn Word3 - slast */
14911 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_18; /* offset: 0x124C size: 32 bit */
14912 /* SPP_DMA2_TCDn Word4 - daddr */
14913 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_18; /* offset: 0x1250 size: 32 bit */
14914 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14915 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_18; /* offset: 0x1254 size: 32 bit */
14916 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14917 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_18; /* offset: 0x1258 size: 32 bit */
14918 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14919 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_18; /* offset: 0x125C size: 32 bit */
14920 /* SPP_DMA2_TCDn Word0 - Source Address */
14921 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_19; /* offset: 0x1260 size: 32 bit */
14922 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14923 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_19; /* offset: 0x1264 size: 32 bit */
14924 /* SPP_DMA2_TCDn Word2 - nbytes */
14925 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_19; /* offset: 0x1268 size: 32 bit */
14926 /* SPP_DMA2_TCDn Word3 - slast */
14927 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_19; /* offset: 0x126C size: 32 bit */
14928 /* SPP_DMA2_TCDn Word4 - daddr */
14929 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_19; /* offset: 0x1270 size: 32 bit */
14930 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14931 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_19; /* offset: 0x1274 size: 32 bit */
14932 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14933 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_19; /* offset: 0x1278 size: 32 bit */
14934 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14935 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_19; /* offset: 0x127C size: 32 bit */
14936 /* SPP_DMA2_TCDn Word0 - Source Address */
14937 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_20; /* offset: 0x1280 size: 32 bit */
14938 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14939 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_20; /* offset: 0x1284 size: 32 bit */
14940 /* SPP_DMA2_TCDn Word2 - nbytes */
14941 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_20; /* offset: 0x1288 size: 32 bit */
14942 /* SPP_DMA2_TCDn Word3 - slast */
14943 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_20; /* offset: 0x128C size: 32 bit */
14944 /* SPP_DMA2_TCDn Word4 - daddr */
14945 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_20; /* offset: 0x1290 size: 32 bit */
14946 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14947 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_20; /* offset: 0x1294 size: 32 bit */
14948 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14949 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_20; /* offset: 0x1298 size: 32 bit */
14950 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14951 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_20; /* offset: 0x129C size: 32 bit */
14952 /* SPP_DMA2_TCDn Word0 - Source Address */
14953 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_21; /* offset: 0x12A0 size: 32 bit */
14954 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14955 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_21; /* offset: 0x12A4 size: 32 bit */
14956 /* SPP_DMA2_TCDn Word2 - nbytes */
14957 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_21; /* offset: 0x12A8 size: 32 bit */
14958 /* SPP_DMA2_TCDn Word3 - slast */
14959 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_21; /* offset: 0x12AC size: 32 bit */
14960 /* SPP_DMA2_TCDn Word4 - daddr */
14961 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_21; /* offset: 0x12B0 size: 32 bit */
14962 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14963 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_21; /* offset: 0x12B4 size: 32 bit */
14964 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14965 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_21; /* offset: 0x12B8 size: 32 bit */
14966 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14967 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_21; /* offset: 0x12BC size: 32 bit */
14968 /* SPP_DMA2_TCDn Word0 - Source Address */
14969 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_22; /* offset: 0x12C0 size: 32 bit */
14970 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14971 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_22; /* offset: 0x12C4 size: 32 bit */
14972 /* SPP_DMA2_TCDn Word2 - nbytes */
14973 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_22; /* offset: 0x12C8 size: 32 bit */
14974 /* SPP_DMA2_TCDn Word3 - slast */
14975 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_22; /* offset: 0x12CC size: 32 bit */
14976 /* SPP_DMA2_TCDn Word4 - daddr */
14977 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_22; /* offset: 0x12D0 size: 32 bit */
14978 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14979 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_22; /* offset: 0x12D4 size: 32 bit */
14980 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14981 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_22; /* offset: 0x12D8 size: 32 bit */
14982 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14983 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_22; /* offset: 0x12DC size: 32 bit */
14984 /* SPP_DMA2_TCDn Word0 - Source Address */
14985 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_23; /* offset: 0x12E0 size: 32 bit */
14986 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14987 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_23; /* offset: 0x12E4 size: 32 bit */
14988 /* SPP_DMA2_TCDn Word2 - nbytes */
14989 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_23; /* offset: 0x12E8 size: 32 bit */
14990 /* SPP_DMA2_TCDn Word3 - slast */
14991 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_23; /* offset: 0x12EC size: 32 bit */
14992 /* SPP_DMA2_TCDn Word4 - daddr */
14993 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_23; /* offset: 0x12F0 size: 32 bit */
14994 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14995 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_23; /* offset: 0x12F4 size: 32 bit */
14996 /* SPP_DMA2_TCDn Word6 - dlast_sga */
14997 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_23; /* offset: 0x12F8 size: 32 bit */
14998 /* SPP_DMA2_TCDn Word7 - biter, etc. */
14999 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_23; /* offset: 0x12FC size: 32 bit */
15000 /* SPP_DMA2_TCDn Word0 - Source Address */
15001 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_24; /* offset: 0x1300 size: 32 bit */
15002 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15003 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_24; /* offset: 0x1304 size: 32 bit */
15004 /* SPP_DMA2_TCDn Word2 - nbytes */
15005 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_24; /* offset: 0x1308 size: 32 bit */
15006 /* SPP_DMA2_TCDn Word3 - slast */
15007 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_24; /* offset: 0x130C size: 32 bit */
15008 /* SPP_DMA2_TCDn Word4 - daddr */
15009 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_24; /* offset: 0x1310 size: 32 bit */
15010 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15011 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_24; /* offset: 0x1314 size: 32 bit */
15012 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15013 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_24; /* offset: 0x1318 size: 32 bit */
15014 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15015 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_24; /* offset: 0x131C size: 32 bit */
15016 /* SPP_DMA2_TCDn Word0 - Source Address */
15017 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_25; /* offset: 0x1320 size: 32 bit */
15018 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15019 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_25; /* offset: 0x1324 size: 32 bit */
15020 /* SPP_DMA2_TCDn Word2 - nbytes */
15021 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_25; /* offset: 0x1328 size: 32 bit */
15022 /* SPP_DMA2_TCDn Word3 - slast */
15023 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_25; /* offset: 0x132C size: 32 bit */
15024 /* SPP_DMA2_TCDn Word4 - daddr */
15025 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_25; /* offset: 0x1330 size: 32 bit */
15026 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15027 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_25; /* offset: 0x1334 size: 32 bit */
15028 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15029 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_25; /* offset: 0x1338 size: 32 bit */
15030 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15031 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_25; /* offset: 0x133C size: 32 bit */
15032 /* SPP_DMA2_TCDn Word0 - Source Address */
15033 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_26; /* offset: 0x1340 size: 32 bit */
15034 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15035 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_26; /* offset: 0x1344 size: 32 bit */
15036 /* SPP_DMA2_TCDn Word2 - nbytes */
15037 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_26; /* offset: 0x1348 size: 32 bit */
15038 /* SPP_DMA2_TCDn Word3 - slast */
15039 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_26; /* offset: 0x134C size: 32 bit */
15040 /* SPP_DMA2_TCDn Word4 - daddr */
15041 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_26; /* offset: 0x1350 size: 32 bit */
15042 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15043 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_26; /* offset: 0x1354 size: 32 bit */
15044 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15045 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_26; /* offset: 0x1358 size: 32 bit */
15046 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15047 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_26; /* offset: 0x135C size: 32 bit */
15048 /* SPP_DMA2_TCDn Word0 - Source Address */
15049 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_27; /* offset: 0x1360 size: 32 bit */
15050 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15051 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_27; /* offset: 0x1364 size: 32 bit */
15052 /* SPP_DMA2_TCDn Word2 - nbytes */
15053 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_27; /* offset: 0x1368 size: 32 bit */
15054 /* SPP_DMA2_TCDn Word3 - slast */
15055 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_27; /* offset: 0x136C size: 32 bit */
15056 /* SPP_DMA2_TCDn Word4 - daddr */
15057 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_27; /* offset: 0x1370 size: 32 bit */
15058 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15059 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_27; /* offset: 0x1374 size: 32 bit */
15060 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15061 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_27; /* offset: 0x1378 size: 32 bit */
15062 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15063 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_27; /* offset: 0x137C size: 32 bit */
15064 /* SPP_DMA2_TCDn Word0 - Source Address */
15065 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_28; /* offset: 0x1380 size: 32 bit */
15066 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15067 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_28; /* offset: 0x1384 size: 32 bit */
15068 /* SPP_DMA2_TCDn Word2 - nbytes */
15069 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_28; /* offset: 0x1388 size: 32 bit */
15070 /* SPP_DMA2_TCDn Word3 - slast */
15071 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_28; /* offset: 0x138C size: 32 bit */
15072 /* SPP_DMA2_TCDn Word4 - daddr */
15073 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_28; /* offset: 0x1390 size: 32 bit */
15074 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15075 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_28; /* offset: 0x1394 size: 32 bit */
15076 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15077 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_28; /* offset: 0x1398 size: 32 bit */
15078 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15079 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_28; /* offset: 0x139C size: 32 bit */
15080 /* SPP_DMA2_TCDn Word0 - Source Address */
15081 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_29; /* offset: 0x13A0 size: 32 bit */
15082 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15083 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_29; /* offset: 0x13A4 size: 32 bit */
15084 /* SPP_DMA2_TCDn Word2 - nbytes */
15085 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_29; /* offset: 0x13A8 size: 32 bit */
15086 /* SPP_DMA2_TCDn Word3 - slast */
15087 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_29; /* offset: 0x13AC size: 32 bit */
15088 /* SPP_DMA2_TCDn Word4 - daddr */
15089 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_29; /* offset: 0x13B0 size: 32 bit */
15090 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15091 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_29; /* offset: 0x13B4 size: 32 bit */
15092 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15093 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_29; /* offset: 0x13B8 size: 32 bit */
15094 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15095 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_29; /* offset: 0x13BC size: 32 bit */
15096 /* SPP_DMA2_TCDn Word0 - Source Address */
15097 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_30; /* offset: 0x13C0 size: 32 bit */
15098 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15099 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_30; /* offset: 0x13C4 size: 32 bit */
15100 /* SPP_DMA2_TCDn Word2 - nbytes */
15101 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_30; /* offset: 0x13C8 size: 32 bit */
15102 /* SPP_DMA2_TCDn Word3 - slast */
15103 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_30; /* offset: 0x13CC size: 32 bit */
15104 /* SPP_DMA2_TCDn Word4 - daddr */
15105 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_30; /* offset: 0x13D0 size: 32 bit */
15106 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15107 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_30; /* offset: 0x13D4 size: 32 bit */
15108 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15109 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_30; /* offset: 0x13D8 size: 32 bit */
15110 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15111 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_30; /* offset: 0x13DC size: 32 bit */
15112 /* SPP_DMA2_TCDn Word0 - Source Address */
15113 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_31; /* offset: 0x13E0 size: 32 bit */
15114 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15115 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_31; /* offset: 0x13E4 size: 32 bit */
15116 /* SPP_DMA2_TCDn Word2 - nbytes */
15117 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_31; /* offset: 0x13E8 size: 32 bit */
15118 /* SPP_DMA2_TCDn Word3 - slast */
15119 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_31; /* offset: 0x13EC size: 32 bit */
15120 /* SPP_DMA2_TCDn Word4 - daddr */
15121 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_31; /* offset: 0x13F0 size: 32 bit */
15122 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15123 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_31; /* offset: 0x13F4 size: 32 bit */
15124 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15125 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_31; /* offset: 0x13F8 size: 32 bit */
15126 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15127 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_31; /* offset: 0x13FC size: 32 bit */
15128 /* SPP_DMA2_TCDn Word0 - Source Address */
15129 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_32; /* offset: 0x1400 size: 32 bit */
15130 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15131 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_32; /* offset: 0x1404 size: 32 bit */
15132 /* SPP_DMA2_TCDn Word2 - nbytes */
15133 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_32; /* offset: 0x1408 size: 32 bit */
15134 /* SPP_DMA2_TCDn Word3 - slast */
15135 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_32; /* offset: 0x140C size: 32 bit */
15136 /* SPP_DMA2_TCDn Word4 - daddr */
15137 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_32; /* offset: 0x1410 size: 32 bit */
15138 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15139 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_32; /* offset: 0x1414 size: 32 bit */
15140 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15141 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_32; /* offset: 0x1418 size: 32 bit */
15142 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15143 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_32; /* offset: 0x141C size: 32 bit */
15144 /* SPP_DMA2_TCDn Word0 - Source Address */
15145 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_33; /* offset: 0x1420 size: 32 bit */
15146 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15147 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_33; /* offset: 0x1424 size: 32 bit */
15148 /* SPP_DMA2_TCDn Word2 - nbytes */
15149 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_33; /* offset: 0x1428 size: 32 bit */
15150 /* SPP_DMA2_TCDn Word3 - slast */
15151 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_33; /* offset: 0x142C size: 32 bit */
15152 /* SPP_DMA2_TCDn Word4 - daddr */
15153 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_33; /* offset: 0x1430 size: 32 bit */
15154 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15155 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_33; /* offset: 0x1434 size: 32 bit */
15156 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15157 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_33; /* offset: 0x1438 size: 32 bit */
15158 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15159 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_33; /* offset: 0x143C size: 32 bit */
15160 /* SPP_DMA2_TCDn Word0 - Source Address */
15161 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_34; /* offset: 0x1440 size: 32 bit */
15162 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15163 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_34; /* offset: 0x1444 size: 32 bit */
15164 /* SPP_DMA2_TCDn Word2 - nbytes */
15165 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_34; /* offset: 0x1448 size: 32 bit */
15166 /* SPP_DMA2_TCDn Word3 - slast */
15167 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_34; /* offset: 0x144C size: 32 bit */
15168 /* SPP_DMA2_TCDn Word4 - daddr */
15169 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_34; /* offset: 0x1450 size: 32 bit */
15170 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15171 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_34; /* offset: 0x1454 size: 32 bit */
15172 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15173 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_34; /* offset: 0x1458 size: 32 bit */
15174 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15175 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_34; /* offset: 0x145C size: 32 bit */
15176 /* SPP_DMA2_TCDn Word0 - Source Address */
15177 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_35; /* offset: 0x1460 size: 32 bit */
15178 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15179 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_35; /* offset: 0x1464 size: 32 bit */
15180 /* SPP_DMA2_TCDn Word2 - nbytes */
15181 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_35; /* offset: 0x1468 size: 32 bit */
15182 /* SPP_DMA2_TCDn Word3 - slast */
15183 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_35; /* offset: 0x146C size: 32 bit */
15184 /* SPP_DMA2_TCDn Word4 - daddr */
15185 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_35; /* offset: 0x1470 size: 32 bit */
15186 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15187 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_35; /* offset: 0x1474 size: 32 bit */
15188 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15189 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_35; /* offset: 0x1478 size: 32 bit */
15190 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15191 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_35; /* offset: 0x147C size: 32 bit */
15192 /* SPP_DMA2_TCDn Word0 - Source Address */
15193 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_36; /* offset: 0x1480 size: 32 bit */
15194 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15195 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_36; /* offset: 0x1484 size: 32 bit */
15196 /* SPP_DMA2_TCDn Word2 - nbytes */
15197 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_36; /* offset: 0x1488 size: 32 bit */
15198 /* SPP_DMA2_TCDn Word3 - slast */
15199 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_36; /* offset: 0x148C size: 32 bit */
15200 /* SPP_DMA2_TCDn Word4 - daddr */
15201 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_36; /* offset: 0x1490 size: 32 bit */
15202 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15203 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_36; /* offset: 0x1494 size: 32 bit */
15204 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15205 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_36; /* offset: 0x1498 size: 32 bit */
15206 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15207 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_36; /* offset: 0x149C size: 32 bit */
15208 /* SPP_DMA2_TCDn Word0 - Source Address */
15209 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_37; /* offset: 0x14A0 size: 32 bit */
15210 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15211 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_37; /* offset: 0x14A4 size: 32 bit */
15212 /* SPP_DMA2_TCDn Word2 - nbytes */
15213 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_37; /* offset: 0x14A8 size: 32 bit */
15214 /* SPP_DMA2_TCDn Word3 - slast */
15215 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_37; /* offset: 0x14AC size: 32 bit */
15216 /* SPP_DMA2_TCDn Word4 - daddr */
15217 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_37; /* offset: 0x14B0 size: 32 bit */
15218 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15219 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_37; /* offset: 0x14B4 size: 32 bit */
15220 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15221 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_37; /* offset: 0x14B8 size: 32 bit */
15222 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15223 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_37; /* offset: 0x14BC size: 32 bit */
15224 /* SPP_DMA2_TCDn Word0 - Source Address */
15225 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_38; /* offset: 0x14C0 size: 32 bit */
15226 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15227 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_38; /* offset: 0x14C4 size: 32 bit */
15228 /* SPP_DMA2_TCDn Word2 - nbytes */
15229 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_38; /* offset: 0x14C8 size: 32 bit */
15230 /* SPP_DMA2_TCDn Word3 - slast */
15231 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_38; /* offset: 0x14CC size: 32 bit */
15232 /* SPP_DMA2_TCDn Word4 - daddr */
15233 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_38; /* offset: 0x14D0 size: 32 bit */
15234 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15235 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_38; /* offset: 0x14D4 size: 32 bit */
15236 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15237 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_38; /* offset: 0x14D8 size: 32 bit */
15238 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15239 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_38; /* offset: 0x14DC size: 32 bit */
15240 /* SPP_DMA2_TCDn Word0 - Source Address */
15241 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_39; /* offset: 0x14E0 size: 32 bit */
15242 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15243 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_39; /* offset: 0x14E4 size: 32 bit */
15244 /* SPP_DMA2_TCDn Word2 - nbytes */
15245 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_39; /* offset: 0x14E8 size: 32 bit */
15246 /* SPP_DMA2_TCDn Word3 - slast */
15247 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_39; /* offset: 0x14EC size: 32 bit */
15248 /* SPP_DMA2_TCDn Word4 - daddr */
15249 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_39; /* offset: 0x14F0 size: 32 bit */
15250 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15251 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_39; /* offset: 0x14F4 size: 32 bit */
15252 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15253 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_39; /* offset: 0x14F8 size: 32 bit */
15254 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15255 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_39; /* offset: 0x14FC size: 32 bit */
15256 /* SPP_DMA2_TCDn Word0 - Source Address */
15257 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_40; /* offset: 0x1500 size: 32 bit */
15258 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15259 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_40; /* offset: 0x1504 size: 32 bit */
15260 /* SPP_DMA2_TCDn Word2 - nbytes */
15261 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_40; /* offset: 0x1508 size: 32 bit */
15262 /* SPP_DMA2_TCDn Word3 - slast */
15263 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_40; /* offset: 0x150C size: 32 bit */
15264 /* SPP_DMA2_TCDn Word4 - daddr */
15265 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_40; /* offset: 0x1510 size: 32 bit */
15266 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15267 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_40; /* offset: 0x1514 size: 32 bit */
15268 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15269 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_40; /* offset: 0x1518 size: 32 bit */
15270 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15271 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_40; /* offset: 0x151C size: 32 bit */
15272 /* SPP_DMA2_TCDn Word0 - Source Address */
15273 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_41; /* offset: 0x1520 size: 32 bit */
15274 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15275 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_41; /* offset: 0x1524 size: 32 bit */
15276 /* SPP_DMA2_TCDn Word2 - nbytes */
15277 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_41; /* offset: 0x1528 size: 32 bit */
15278 /* SPP_DMA2_TCDn Word3 - slast */
15279 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_41; /* offset: 0x152C size: 32 bit */
15280 /* SPP_DMA2_TCDn Word4 - daddr */
15281 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_41; /* offset: 0x1530 size: 32 bit */
15282 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15283 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_41; /* offset: 0x1534 size: 32 bit */
15284 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15285 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_41; /* offset: 0x1538 size: 32 bit */
15286 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15287 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_41; /* offset: 0x153C size: 32 bit */
15288 /* SPP_DMA2_TCDn Word0 - Source Address */
15289 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_42; /* offset: 0x1540 size: 32 bit */
15290 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15291 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_42; /* offset: 0x1544 size: 32 bit */
15292 /* SPP_DMA2_TCDn Word2 - nbytes */
15293 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_42; /* offset: 0x1548 size: 32 bit */
15294 /* SPP_DMA2_TCDn Word3 - slast */
15295 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_42; /* offset: 0x154C size: 32 bit */
15296 /* SPP_DMA2_TCDn Word4 - daddr */
15297 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_42; /* offset: 0x1550 size: 32 bit */
15298 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15299 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_42; /* offset: 0x1554 size: 32 bit */
15300 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15301 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_42; /* offset: 0x1558 size: 32 bit */
15302 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15303 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_42; /* offset: 0x155C size: 32 bit */
15304 /* SPP_DMA2_TCDn Word0 - Source Address */
15305 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_43; /* offset: 0x1560 size: 32 bit */
15306 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15307 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_43; /* offset: 0x1564 size: 32 bit */
15308 /* SPP_DMA2_TCDn Word2 - nbytes */
15309 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_43; /* offset: 0x1568 size: 32 bit */
15310 /* SPP_DMA2_TCDn Word3 - slast */
15311 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_43; /* offset: 0x156C size: 32 bit */
15312 /* SPP_DMA2_TCDn Word4 - daddr */
15313 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_43; /* offset: 0x1570 size: 32 bit */
15314 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15315 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_43; /* offset: 0x1574 size: 32 bit */
15316 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15317 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_43; /* offset: 0x1578 size: 32 bit */
15318 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15319 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_43; /* offset: 0x157C size: 32 bit */
15320 /* SPP_DMA2_TCDn Word0 - Source Address */
15321 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_44; /* offset: 0x1580 size: 32 bit */
15322 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15323 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_44; /* offset: 0x1584 size: 32 bit */
15324 /* SPP_DMA2_TCDn Word2 - nbytes */
15325 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_44; /* offset: 0x1588 size: 32 bit */
15326 /* SPP_DMA2_TCDn Word3 - slast */
15327 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_44; /* offset: 0x158C size: 32 bit */
15328 /* SPP_DMA2_TCDn Word4 - daddr */
15329 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_44; /* offset: 0x1590 size: 32 bit */
15330 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15331 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_44; /* offset: 0x1594 size: 32 bit */
15332 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15333 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_44; /* offset: 0x1598 size: 32 bit */
15334 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15335 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_44; /* offset: 0x159C size: 32 bit */
15336 /* SPP_DMA2_TCDn Word0 - Source Address */
15337 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_45; /* offset: 0x15A0 size: 32 bit */
15338 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15339 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_45; /* offset: 0x15A4 size: 32 bit */
15340 /* SPP_DMA2_TCDn Word2 - nbytes */
15341 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_45; /* offset: 0x15A8 size: 32 bit */
15342 /* SPP_DMA2_TCDn Word3 - slast */
15343 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_45; /* offset: 0x15AC size: 32 bit */
15344 /* SPP_DMA2_TCDn Word4 - daddr */
15345 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_45; /* offset: 0x15B0 size: 32 bit */
15346 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15347 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_45; /* offset: 0x15B4 size: 32 bit */
15348 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15349 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_45; /* offset: 0x15B8 size: 32 bit */
15350 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15351 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_45; /* offset: 0x15BC size: 32 bit */
15352 /* SPP_DMA2_TCDn Word0 - Source Address */
15353 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_46; /* offset: 0x15C0 size: 32 bit */
15354 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15355 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_46; /* offset: 0x15C4 size: 32 bit */
15356 /* SPP_DMA2_TCDn Word2 - nbytes */
15357 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_46; /* offset: 0x15C8 size: 32 bit */
15358 /* SPP_DMA2_TCDn Word3 - slast */
15359 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_46; /* offset: 0x15CC size: 32 bit */
15360 /* SPP_DMA2_TCDn Word4 - daddr */
15361 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_46; /* offset: 0x15D0 size: 32 bit */
15362 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15363 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_46; /* offset: 0x15D4 size: 32 bit */
15364 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15365 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_46; /* offset: 0x15D8 size: 32 bit */
15366 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15367 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_46; /* offset: 0x15DC size: 32 bit */
15368 /* SPP_DMA2_TCDn Word0 - Source Address */
15369 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_47; /* offset: 0x15E0 size: 32 bit */
15370 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15371 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_47; /* offset: 0x15E4 size: 32 bit */
15372 /* SPP_DMA2_TCDn Word2 - nbytes */
15373 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_47; /* offset: 0x15E8 size: 32 bit */
15374 /* SPP_DMA2_TCDn Word3 - slast */
15375 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_47; /* offset: 0x15EC size: 32 bit */
15376 /* SPP_DMA2_TCDn Word4 - daddr */
15377 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_47; /* offset: 0x15F0 size: 32 bit */
15378 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15379 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_47; /* offset: 0x15F4 size: 32 bit */
15380 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15381 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_47; /* offset: 0x15F8 size: 32 bit */
15382 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15383 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_47; /* offset: 0x15FC size: 32 bit */
15384 /* SPP_DMA2_TCDn Word0 - Source Address */
15385 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_48; /* offset: 0x1600 size: 32 bit */
15386 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15387 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_48; /* offset: 0x1604 size: 32 bit */
15388 /* SPP_DMA2_TCDn Word2 - nbytes */
15389 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_48; /* offset: 0x1608 size: 32 bit */
15390 /* SPP_DMA2_TCDn Word3 - slast */
15391 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_48; /* offset: 0x160C size: 32 bit */
15392 /* SPP_DMA2_TCDn Word4 - daddr */
15393 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_48; /* offset: 0x1610 size: 32 bit */
15394 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15395 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_48; /* offset: 0x1614 size: 32 bit */
15396 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15397 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_48; /* offset: 0x1618 size: 32 bit */
15398 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15399 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_48; /* offset: 0x161C size: 32 bit */
15400 /* SPP_DMA2_TCDn Word0 - Source Address */
15401 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_49; /* offset: 0x1620 size: 32 bit */
15402 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15403 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_49; /* offset: 0x1624 size: 32 bit */
15404 /* SPP_DMA2_TCDn Word2 - nbytes */
15405 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_49; /* offset: 0x1628 size: 32 bit */
15406 /* SPP_DMA2_TCDn Word3 - slast */
15407 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_49; /* offset: 0x162C size: 32 bit */
15408 /* SPP_DMA2_TCDn Word4 - daddr */
15409 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_49; /* offset: 0x1630 size: 32 bit */
15410 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15411 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_49; /* offset: 0x1634 size: 32 bit */
15412 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15413 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_49; /* offset: 0x1638 size: 32 bit */
15414 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15415 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_49; /* offset: 0x163C size: 32 bit */
15416 /* SPP_DMA2_TCDn Word0 - Source Address */
15417 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_50; /* offset: 0x1640 size: 32 bit */
15418 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15419 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_50; /* offset: 0x1644 size: 32 bit */
15420 /* SPP_DMA2_TCDn Word2 - nbytes */
15421 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_50; /* offset: 0x1648 size: 32 bit */
15422 /* SPP_DMA2_TCDn Word3 - slast */
15423 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_50; /* offset: 0x164C size: 32 bit */
15424 /* SPP_DMA2_TCDn Word4 - daddr */
15425 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_50; /* offset: 0x1650 size: 32 bit */
15426 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15427 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_50; /* offset: 0x1654 size: 32 bit */
15428 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15429 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_50; /* offset: 0x1658 size: 32 bit */
15430 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15431 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_50; /* offset: 0x165C size: 32 bit */
15432 /* SPP_DMA2_TCDn Word0 - Source Address */
15433 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_51; /* offset: 0x1660 size: 32 bit */
15434 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15435 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_51; /* offset: 0x1664 size: 32 bit */
15436 /* SPP_DMA2_TCDn Word2 - nbytes */
15437 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_51; /* offset: 0x1668 size: 32 bit */
15438 /* SPP_DMA2_TCDn Word3 - slast */
15439 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_51; /* offset: 0x166C size: 32 bit */
15440 /* SPP_DMA2_TCDn Word4 - daddr */
15441 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_51; /* offset: 0x1670 size: 32 bit */
15442 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15443 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_51; /* offset: 0x1674 size: 32 bit */
15444 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15445 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_51; /* offset: 0x1678 size: 32 bit */
15446 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15447 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_51; /* offset: 0x167C size: 32 bit */
15448 /* SPP_DMA2_TCDn Word0 - Source Address */
15449 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_52; /* offset: 0x1680 size: 32 bit */
15450 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15451 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_52; /* offset: 0x1684 size: 32 bit */
15452 /* SPP_DMA2_TCDn Word2 - nbytes */
15453 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_52; /* offset: 0x1688 size: 32 bit */
15454 /* SPP_DMA2_TCDn Word3 - slast */
15455 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_52; /* offset: 0x168C size: 32 bit */
15456 /* SPP_DMA2_TCDn Word4 - daddr */
15457 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_52; /* offset: 0x1690 size: 32 bit */
15458 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15459 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_52; /* offset: 0x1694 size: 32 bit */
15460 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15461 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_52; /* offset: 0x1698 size: 32 bit */
15462 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15463 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_52; /* offset: 0x169C size: 32 bit */
15464 /* SPP_DMA2_TCDn Word0 - Source Address */
15465 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_53; /* offset: 0x16A0 size: 32 bit */
15466 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15467 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_53; /* offset: 0x16A4 size: 32 bit */
15468 /* SPP_DMA2_TCDn Word2 - nbytes */
15469 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_53; /* offset: 0x16A8 size: 32 bit */
15470 /* SPP_DMA2_TCDn Word3 - slast */
15471 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_53; /* offset: 0x16AC size: 32 bit */
15472 /* SPP_DMA2_TCDn Word4 - daddr */
15473 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_53; /* offset: 0x16B0 size: 32 bit */
15474 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15475 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_53; /* offset: 0x16B4 size: 32 bit */
15476 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15477 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_53; /* offset: 0x16B8 size: 32 bit */
15478 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15479 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_53; /* offset: 0x16BC size: 32 bit */
15480 /* SPP_DMA2_TCDn Word0 - Source Address */
15481 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_54; /* offset: 0x16C0 size: 32 bit */
15482 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15483 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_54; /* offset: 0x16C4 size: 32 bit */
15484 /* SPP_DMA2_TCDn Word2 - nbytes */
15485 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_54; /* offset: 0x16C8 size: 32 bit */
15486 /* SPP_DMA2_TCDn Word3 - slast */
15487 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_54; /* offset: 0x16CC size: 32 bit */
15488 /* SPP_DMA2_TCDn Word4 - daddr */
15489 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_54; /* offset: 0x16D0 size: 32 bit */
15490 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15491 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_54; /* offset: 0x16D4 size: 32 bit */
15492 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15493 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_54; /* offset: 0x16D8 size: 32 bit */
15494 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15495 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_54; /* offset: 0x16DC size: 32 bit */
15496 /* SPP_DMA2_TCDn Word0 - Source Address */
15497 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_55; /* offset: 0x16E0 size: 32 bit */
15498 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15499 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_55; /* offset: 0x16E4 size: 32 bit */
15500 /* SPP_DMA2_TCDn Word2 - nbytes */
15501 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_55; /* offset: 0x16E8 size: 32 bit */
15502 /* SPP_DMA2_TCDn Word3 - slast */
15503 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_55; /* offset: 0x16EC size: 32 bit */
15504 /* SPP_DMA2_TCDn Word4 - daddr */
15505 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_55; /* offset: 0x16F0 size: 32 bit */
15506 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15507 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_55; /* offset: 0x16F4 size: 32 bit */
15508 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15509 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_55; /* offset: 0x16F8 size: 32 bit */
15510 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15511 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_55; /* offset: 0x16FC size: 32 bit */
15512 /* SPP_DMA2_TCDn Word0 - Source Address */
15513 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_56; /* offset: 0x1700 size: 32 bit */
15514 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15515 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_56; /* offset: 0x1704 size: 32 bit */
15516 /* SPP_DMA2_TCDn Word2 - nbytes */
15517 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_56; /* offset: 0x1708 size: 32 bit */
15518 /* SPP_DMA2_TCDn Word3 - slast */
15519 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_56; /* offset: 0x170C size: 32 bit */
15520 /* SPP_DMA2_TCDn Word4 - daddr */
15521 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_56; /* offset: 0x1710 size: 32 bit */
15522 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15523 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_56; /* offset: 0x1714 size: 32 bit */
15524 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15525 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_56; /* offset: 0x1718 size: 32 bit */
15526 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15527 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_56; /* offset: 0x171C size: 32 bit */
15528 /* SPP_DMA2_TCDn Word0 - Source Address */
15529 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_57; /* offset: 0x1720 size: 32 bit */
15530 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15531 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_57; /* offset: 0x1724 size: 32 bit */
15532 /* SPP_DMA2_TCDn Word2 - nbytes */
15533 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_57; /* offset: 0x1728 size: 32 bit */
15534 /* SPP_DMA2_TCDn Word3 - slast */
15535 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_57; /* offset: 0x172C size: 32 bit */
15536 /* SPP_DMA2_TCDn Word4 - daddr */
15537 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_57; /* offset: 0x1730 size: 32 bit */
15538 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15539 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_57; /* offset: 0x1734 size: 32 bit */
15540 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15541 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_57; /* offset: 0x1738 size: 32 bit */
15542 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15543 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_57; /* offset: 0x173C size: 32 bit */
15544 /* SPP_DMA2_TCDn Word0 - Source Address */
15545 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_58; /* offset: 0x1740 size: 32 bit */
15546 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15547 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_58; /* offset: 0x1744 size: 32 bit */
15548 /* SPP_DMA2_TCDn Word2 - nbytes */
15549 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_58; /* offset: 0x1748 size: 32 bit */
15550 /* SPP_DMA2_TCDn Word3 - slast */
15551 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_58; /* offset: 0x174C size: 32 bit */
15552 /* SPP_DMA2_TCDn Word4 - daddr */
15553 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_58; /* offset: 0x1750 size: 32 bit */
15554 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15555 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_58; /* offset: 0x1754 size: 32 bit */
15556 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15557 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_58; /* offset: 0x1758 size: 32 bit */
15558 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15559 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_58; /* offset: 0x175C size: 32 bit */
15560 /* SPP_DMA2_TCDn Word0 - Source Address */
15561 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_59; /* offset: 0x1760 size: 32 bit */
15562 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15563 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_59; /* offset: 0x1764 size: 32 bit */
15564 /* SPP_DMA2_TCDn Word2 - nbytes */
15565 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_59; /* offset: 0x1768 size: 32 bit */
15566 /* SPP_DMA2_TCDn Word3 - slast */
15567 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_59; /* offset: 0x176C size: 32 bit */
15568 /* SPP_DMA2_TCDn Word4 - daddr */
15569 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_59; /* offset: 0x1770 size: 32 bit */
15570 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15571 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_59; /* offset: 0x1774 size: 32 bit */
15572 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15573 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_59; /* offset: 0x1778 size: 32 bit */
15574 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15575 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_59; /* offset: 0x177C size: 32 bit */
15576 /* SPP_DMA2_TCDn Word0 - Source Address */
15577 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_60; /* offset: 0x1780 size: 32 bit */
15578 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15579 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_60; /* offset: 0x1784 size: 32 bit */
15580 /* SPP_DMA2_TCDn Word2 - nbytes */
15581 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_60; /* offset: 0x1788 size: 32 bit */
15582 /* SPP_DMA2_TCDn Word3 - slast */
15583 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_60; /* offset: 0x178C size: 32 bit */
15584 /* SPP_DMA2_TCDn Word4 - daddr */
15585 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_60; /* offset: 0x1790 size: 32 bit */
15586 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15587 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_60; /* offset: 0x1794 size: 32 bit */
15588 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15589 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_60; /* offset: 0x1798 size: 32 bit */
15590 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15591 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_60; /* offset: 0x179C size: 32 bit */
15592 /* SPP_DMA2_TCDn Word0 - Source Address */
15593 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_61; /* offset: 0x17A0 size: 32 bit */
15594 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15595 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_61; /* offset: 0x17A4 size: 32 bit */
15596 /* SPP_DMA2_TCDn Word2 - nbytes */
15597 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_61; /* offset: 0x17A8 size: 32 bit */
15598 /* SPP_DMA2_TCDn Word3 - slast */
15599 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_61; /* offset: 0x17AC size: 32 bit */
15600 /* SPP_DMA2_TCDn Word4 - daddr */
15601 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_61; /* offset: 0x17B0 size: 32 bit */
15602 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15603 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_61; /* offset: 0x17B4 size: 32 bit */
15604 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15605 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_61; /* offset: 0x17B8 size: 32 bit */
15606 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15607 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_61; /* offset: 0x17BC size: 32 bit */
15608 /* SPP_DMA2_TCDn Word0 - Source Address */
15609 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_62; /* offset: 0x17C0 size: 32 bit */
15610 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15611 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_62; /* offset: 0x17C4 size: 32 bit */
15612 /* SPP_DMA2_TCDn Word2 - nbytes */
15613 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_62; /* offset: 0x17C8 size: 32 bit */
15614 /* SPP_DMA2_TCDn Word3 - slast */
15615 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_62; /* offset: 0x17CC size: 32 bit */
15616 /* SPP_DMA2_TCDn Word4 - daddr */
15617 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_62; /* offset: 0x17D0 size: 32 bit */
15618 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15619 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_62; /* offset: 0x17D4 size: 32 bit */
15620 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15621 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_62; /* offset: 0x17D8 size: 32 bit */
15622 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15623 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_62; /* offset: 0x17DC size: 32 bit */
15624 /* SPP_DMA2_TCDn Word0 - Source Address */
15625 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_63; /* offset: 0x17E0 size: 32 bit */
15626 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15627 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_63; /* offset: 0x17E4 size: 32 bit */
15628 /* SPP_DMA2_TCDn Word2 - nbytes */
15629 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_63; /* offset: 0x17E8 size: 32 bit */
15630 /* SPP_DMA2_TCDn Word3 - slast */
15631 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_63; /* offset: 0x17EC size: 32 bit */
15632 /* SPP_DMA2_TCDn Word4 - daddr */
15633 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_63; /* offset: 0x17F0 size: 32 bit */
15634 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15635 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_63; /* offset: 0x17F4 size: 32 bit */
15636 /* SPP_DMA2_TCDn Word6 - dlast_sga */
15637 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_63; /* offset: 0x17F8 size: 32 bit */
15638 /* SPP_DMA2_TCDn Word7 - biter, etc. */
15639 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_63; /* offset: 0x17FC size: 32 bit */
15640 };
15641
15642 };
15643 } SPP_DMA2_tag;
15644
15645
15646#define SPP_DMA2 (*(volatile SPP_DMA2_tag *) 0xFFF44000UL)
15647
15648
15649
15650/****************************************************************/
15651/* */
15652/* Module: INTC */
15653/* */
15654/****************************************************************/
15655
15656 typedef union { /* BCR - Block Configuration Register */
15657 uint32_t R;
15658 struct {
15659 uint32_t:18;
15660 uint32_t VTES_PRC1:1; /* Vector Table Entry Size - Processor 1 */
15661 uint32_t:4;
15662 uint32_t HVEN_PRC1:1; /* Hardware Vector Enable - Processor 1 */
15663 uint32_t:2;
15664#ifndef USE_FIELD_ALIASES_INTC
15665 uint32_t VTES_PRC0:1; /* Vector Table Entry Size - Processor 0 */
15666#else
15667 uint32_t VTES:1; /* deprecated name - please avoid */
15668#endif
15669 uint32_t:4;
15670#ifndef USE_FIELD_ALIASES_INTC
15671 uint32_t HVEN_PRC0:1; /* Hardware Vector Enable - Processor 0 */
15672#else
15673 uint32_t HVEN:1; /* deprecated name - please avoid */
15674#endif
15675 } B;
15676 } INTC_BCR_32B_tag;
15677
15678 typedef union { /* CPR - Current Priority Register - Processor 0 */
15679 uint32_t R;
15680 struct {
15681 uint32_t:28;
15682 uint32_t PRI:4; /* Priority Bits */
15683 } B;
15684 } INTC_CPR_PRC0_32B_tag;
15685
15686 typedef union { /* CPR - Current Priority Register - Processor 1 */
15687 uint32_t R;
15688 struct {
15689 uint32_t:28;
15690 uint32_t PRI:4; /* Priority Bits */
15691 } B;
15692 } INTC_CPR_PRC1_32B_tag;
15693
15694 typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 0 */
15695 uint32_t R;
15696 struct {
15697#ifndef USE_FIELD_ALIASES_INTC
15698 uint32_t VTBA_PRC0:21; /* Vector Table Base Address - Processor 0 */
15699#else
15700 uint32_t VTBA:21; /* deprecated name - please avoid */
15701#endif
15702#ifndef USE_FIELD_ALIASES_INTC
15703 uint32_t INTEC_PRC0:9; /* Interrupt Vector - Processor 0 */
15704#else
15705 uint32_t INTVEC:9; /* deprecated name - please avoid */
15706#endif
15707 uint32_t:2;
15708 } B;
15709 } INTC_IACKR_PRC0_32B_tag;
15710
15711 typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 1 */
15712 uint32_t R;
15713 struct {
15714 uint32_t VTBA_PRC1:21; /* Vector Table Base Address - Processor 1 */
15715 uint32_t INTEC_PRC1:9; /* Interrupt Vector - Processor 1 */
15716 uint32_t:2;
15717 } B;
15718 } INTC_IACKR_PRC1_32B_tag;
15719
15720 typedef union { /* EOIR- End of Interrupt Register - Processor 0 */
15721 uint32_t R;
15722 } INTC_EOIR_PRC0_32B_tag;
15723
15724 typedef union { /* EOIR- End of Interrupt Register - Processor 1 */
15725 uint32_t R;
15726 } INTC_EOIR_PRC1_32B_tag;
15727
15728
15729 /* Register layout for all registers SSCIR... */
15730
15731 typedef union { /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */
15732 uint8_t R;
15733 struct {
15734 uint8_t:6;
15735 uint8_t SET:1; /* Set Flag bit */
15736 uint8_t CLR:1; /* Clear Flag bit */
15737 } B;
15738 } INTC_SSCIR_8B_tag;
15739
15740 typedef union { /* SSCIR0_3 - Software Set/Clear Interrupt Registers */
15741 uint32_t R;
15742 struct {
15743 uint32_t:6;
15744 uint32_t SET0:1; /* Set Flag 0 bit */
15745 uint32_t CLR0:1; /* Clear Flag 0 bit */
15746 uint32_t:6;
15747 uint32_t SET1:1; /* Set Flag 1 bit */
15748 uint32_t CLR1:1; /* Clear Flag 1 bit */
15749 uint32_t:6;
15750 uint32_t SET2:1; /* Set Flag 2 bit */
15751 uint32_t CLR2:1; /* Clear Flag 2 bit */
15752 uint32_t:6;
15753 uint32_t SET3:1; /* Set Flag 3 bit */
15754 uint32_t CLR3:1; /* Clear Flag 3 bit */
15755 } B;
15756 } INTC_SSCIR0_3_32B_tag;
15757
15758 typedef union { /* SSCIR4_7 - Software Set/Clear Interrupt Registers */
15759 uint32_t R;
15760 struct {
15761 uint32_t:6;
15762 uint32_t SET4:1; /* Set Flag 4 bit */
15763 uint32_t CLR4:1; /* Clear Flag 4 bit */
15764 uint32_t:6;
15765 uint32_t SET5:1; /* Set Flag 5 bit */
15766 uint32_t CLR5:1; /* Clear Flag 5 bit */
15767 uint32_t:6;
15768 uint32_t SET6:1; /* Set Flag 6 bit */
15769 uint32_t CLR6:1; /* Clear Flag 6 bit */
15770 uint32_t:6;
15771 uint32_t SET7:1; /* Set Flag 7 bit */
15772 uint32_t CLR7:1; /* Clear Flag 7 bit */
15773 } B;
15774 } INTC_SSCIR4_7_32B_tag;
15775
15776
15777 /* Register layout for all registers PSR... */
15778
15779 typedef union { /* PSR0-511 - Priority Select Registers */
15780 uint8_t R;
15781 struct {
15782 uint8_t PRC_SEL:2; /* Processor Select */
15783 uint8_t:2;
15784 uint8_t PRI:4; /* Priority Select */
15785 } B;
15786 } INTC_PSR_8B_tag;
15787
15788
15789 /* Register layout for all registers PSR... */
15790
15791 typedef union { /* PSR0_3 - 508_511 - Priority Select Registers */
15792 uint32_t R;
15793 struct {
15794 uint32_t PRC_SEL0:2; /* Processor Select - Entry 0 */
15795 uint32_t:2;
15796 uint32_t PRI0:4; /* Priority Select - Entry 0 */
15797 uint32_t PRC_SEL1:2; /* Processor Select - Entry 1 */
15798 uint32_t:2;
15799 uint32_t PRI1:4; /* Priority Select - Entry 1 */
15800 uint32_t PRC_SEL2:2; /* Processor Select - Entry 2 */
15801 uint32_t:2;
15802 uint32_t PRI2:4; /* Priority Select - Entry 2 */
15803 uint32_t PRC_SEL3:2; /* Processor Select - Entry 3 */
15804 uint32_t:2;
15805 uint32_t PRI3:4; /* Priority Select - Entry 3 */
15806 } B;
15807 } INTC_PSR_32B_tag;
15808
15809
15810
15811 typedef struct INTC_struct_tag { /* start of INTC_tag */
15812 union {
15813 INTC_BCR_32B_tag MCR; /* deprecated - please avoid */
15814
15815 /* BCR - Block Configuration Register */
15816 INTC_BCR_32B_tag BCR; /* offset: 0x0000 size: 32 bit */
15817
15818 };
15819 int8_t INTC_reserved_0004_C[4];
15820 union {
15821 /* CPR - Current Priority Register - Processor 0 */
15822 INTC_CPR_PRC0_32B_tag CPR_PRC0; /* offset: 0x0008 size: 32 bit */
15823
15824 INTC_CPR_PRC0_32B_tag CPR; /* deprecated - please avoid */
15825
15826 };
15827 /* CPR - Current Priority Register - Processor 1 */
15828 INTC_CPR_PRC1_32B_tag CPR_PRC1; /* offset: 0x000C size: 32 bit */
15829 union {
15830 /* IACKR- Interrupt Acknowledge Register - Processor 0 */
15831 INTC_IACKR_PRC0_32B_tag IACKR_PRC0; /* offset: 0x0010 size: 32 bit */
15832
15833 INTC_IACKR_PRC0_32B_tag IACKR; /* deprecated - please avoid */
15834
15835 };
15836 /* IACKR- Interrupt Acknowledge Register - Processor 1 */
15837 INTC_IACKR_PRC1_32B_tag IACKR_PRC1; /* offset: 0x0014 size: 32 bit */
15838 union {
15839 /* EOIR- End of Interrupt Register - Processor 0 */
15840 INTC_EOIR_PRC0_32B_tag EOIR_PRC0; /* offset: 0x0018 size: 32 bit */
15841
15842 INTC_EOIR_PRC0_32B_tag EOIR; /* deprecated - please avoid */
15843
15844 };
15845 /* EOIR- End of Interrupt Register - Processor 1 */
15846 INTC_EOIR_PRC1_32B_tag EOIR_PRC1; /* offset: 0x001C size: 32 bit */
15847 union {
15848 /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */
15849 INTC_SSCIR_8B_tag SSCIR[8]; /* offset: 0x0020 (0x0001 x 8) */
15850
15851 struct {
15852 /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */
15853 INTC_SSCIR_8B_tag SSCIR0; /* offset: 0x0020 size: 8 bit */
15854 INTC_SSCIR_8B_tag SSCIR1; /* offset: 0x0021 size: 8 bit */
15855 INTC_SSCIR_8B_tag SSCIR2; /* offset: 0x0022 size: 8 bit */
15856 INTC_SSCIR_8B_tag SSCIR3; /* offset: 0x0023 size: 8 bit */
15857 INTC_SSCIR_8B_tag SSCIR4; /* offset: 0x0024 size: 8 bit */
15858 INTC_SSCIR_8B_tag SSCIR5; /* offset: 0x0025 size: 8 bit */
15859 INTC_SSCIR_8B_tag SSCIR6; /* offset: 0x0026 size: 8 bit */
15860 INTC_SSCIR_8B_tag SSCIR7; /* offset: 0x0027 size: 8 bit */
15861 };
15862
15863 struct {
15864 /* SSCIR0_3 - Software Set/Clear Interrupt Registers */
15865 INTC_SSCIR0_3_32B_tag SSCIR0_3; /* offset: 0x0020 size: 32 bit */
15866 /* SSCIR4_7 - Software Set/Clear Interrupt Registers */
15867 INTC_SSCIR4_7_32B_tag SSCIR4_7; /* offset: 0x0024 size: 32 bit */
15868 };
15869
15870 };
15871 int8_t INTC_reserved_0028_C[24];
15872 union {
15873 /* PSR0_3 - 508_511 - Priority Select Registers */
15874 INTC_PSR_32B_tag PSR_32B[128]; /* offset: 0x0040 (0x0004 x 128) */
15875
15876 /* PSR0-511 - Priority Select Registers */
15877 INTC_PSR_8B_tag PSR[512]; /* offset: 0x0040 (0x0001 x 512) */
15878
15879 struct {
15880 /* PSR0_3 - 508_511 - Priority Select Registers */
15881 INTC_PSR_32B_tag PSR0_3; /* offset: 0x0040 size: 32 bit */
15882 INTC_PSR_32B_tag PSR4_7; /* offset: 0x0044 size: 32 bit */
15883 INTC_PSR_32B_tag PSR8_11; /* offset: 0x0048 size: 32 bit */
15884 INTC_PSR_32B_tag PSR12_15; /* offset: 0x004C size: 32 bit */
15885 INTC_PSR_32B_tag PSR16_19; /* offset: 0x0050 size: 32 bit */
15886 INTC_PSR_32B_tag PSR20_23; /* offset: 0x0054 size: 32 bit */
15887 INTC_PSR_32B_tag PSR24_27; /* offset: 0x0058 size: 32 bit */
15888 INTC_PSR_32B_tag PSR28_31; /* offset: 0x005C size: 32 bit */
15889 INTC_PSR_32B_tag PSR32_35; /* offset: 0x0060 size: 32 bit */
15890 INTC_PSR_32B_tag PSR36_39; /* offset: 0x0064 size: 32 bit */
15891 INTC_PSR_32B_tag PSR40_43; /* offset: 0x0068 size: 32 bit */
15892 INTC_PSR_32B_tag PSR44_47; /* offset: 0x006C size: 32 bit */
15893 INTC_PSR_32B_tag PSR48_51; /* offset: 0x0070 size: 32 bit */
15894 INTC_PSR_32B_tag PSR52_55; /* offset: 0x0074 size: 32 bit */
15895 INTC_PSR_32B_tag PSR56_59; /* offset: 0x0078 size: 32 bit */
15896 INTC_PSR_32B_tag PSR60_63; /* offset: 0x007C size: 32 bit */
15897 INTC_PSR_32B_tag PSR64_67; /* offset: 0x0080 size: 32 bit */
15898 INTC_PSR_32B_tag PSR68_71; /* offset: 0x0084 size: 32 bit */
15899 INTC_PSR_32B_tag PSR72_75; /* offset: 0x0088 size: 32 bit */
15900 INTC_PSR_32B_tag PSR76_79; /* offset: 0x008C size: 32 bit */
15901 INTC_PSR_32B_tag PSR80_83; /* offset: 0x0090 size: 32 bit */
15902 INTC_PSR_32B_tag PSR84_87; /* offset: 0x0094 size: 32 bit */
15903 INTC_PSR_32B_tag PSR88_91; /* offset: 0x0098 size: 32 bit */
15904 INTC_PSR_32B_tag PSR92_95; /* offset: 0x009C size: 32 bit */
15905 INTC_PSR_32B_tag PSR96_99; /* offset: 0x00A0 size: 32 bit */
15906 INTC_PSR_32B_tag PSR100_103; /* offset: 0x00A4 size: 32 bit */
15907 INTC_PSR_32B_tag PSR104_107; /* offset: 0x00A8 size: 32 bit */
15908 INTC_PSR_32B_tag PSR108_111; /* offset: 0x00AC size: 32 bit */
15909 INTC_PSR_32B_tag PSR112_115; /* offset: 0x00B0 size: 32 bit */
15910 INTC_PSR_32B_tag PSR116_119; /* offset: 0x00B4 size: 32 bit */
15911 INTC_PSR_32B_tag PSR120_123; /* offset: 0x00B8 size: 32 bit */
15912 INTC_PSR_32B_tag PSR124_127; /* offset: 0x00BC size: 32 bit */
15913 INTC_PSR_32B_tag PSR128_131; /* offset: 0x00C0 size: 32 bit */
15914 INTC_PSR_32B_tag PSR132_135; /* offset: 0x00C4 size: 32 bit */
15915 INTC_PSR_32B_tag PSR136_139; /* offset: 0x00C8 size: 32 bit */
15916 INTC_PSR_32B_tag PSR140_143; /* offset: 0x00CC size: 32 bit */
15917 INTC_PSR_32B_tag PSR144_147; /* offset: 0x00D0 size: 32 bit */
15918 INTC_PSR_32B_tag PSR148_151; /* offset: 0x00D4 size: 32 bit */
15919 INTC_PSR_32B_tag PSR152_155; /* offset: 0x00D8 size: 32 bit */
15920 INTC_PSR_32B_tag PSR156_159; /* offset: 0x00DC size: 32 bit */
15921 INTC_PSR_32B_tag PSR160_163; /* offset: 0x00E0 size: 32 bit */
15922 INTC_PSR_32B_tag PSR164_167; /* offset: 0x00E4 size: 32 bit */
15923 INTC_PSR_32B_tag PSR168_171; /* offset: 0x00E8 size: 32 bit */
15924 INTC_PSR_32B_tag PSR172_175; /* offset: 0x00EC size: 32 bit */
15925 INTC_PSR_32B_tag PSR176_179; /* offset: 0x00F0 size: 32 bit */
15926 INTC_PSR_32B_tag PSR180_183; /* offset: 0x00F4 size: 32 bit */
15927 INTC_PSR_32B_tag PSR184_187; /* offset: 0x00F8 size: 32 bit */
15928 INTC_PSR_32B_tag PSR188_191; /* offset: 0x00FC size: 32 bit */
15929 INTC_PSR_32B_tag PSR192_195; /* offset: 0x0100 size: 32 bit */
15930 INTC_PSR_32B_tag PSR196_199; /* offset: 0x0104 size: 32 bit */
15931 INTC_PSR_32B_tag PSR200_203; /* offset: 0x0108 size: 32 bit */
15932 INTC_PSR_32B_tag PSR204_207; /* offset: 0x010C size: 32 bit */
15933 INTC_PSR_32B_tag PSR208_211; /* offset: 0x0110 size: 32 bit */
15934 INTC_PSR_32B_tag PSR212_215; /* offset: 0x0114 size: 32 bit */
15935 INTC_PSR_32B_tag PSR216_219; /* offset: 0x0118 size: 32 bit */
15936 INTC_PSR_32B_tag PSR220_223; /* offset: 0x011C size: 32 bit */
15937 INTC_PSR_32B_tag PSR224_227; /* offset: 0x0120 size: 32 bit */
15938 INTC_PSR_32B_tag PSR228_231; /* offset: 0x0124 size: 32 bit */
15939 INTC_PSR_32B_tag PSR232_235; /* offset: 0x0128 size: 32 bit */
15940 INTC_PSR_32B_tag PSR236_239; /* offset: 0x012C size: 32 bit */
15941 INTC_PSR_32B_tag PSR240_243; /* offset: 0x0130 size: 32 bit */
15942 INTC_PSR_32B_tag PSR244_247; /* offset: 0x0134 size: 32 bit */
15943 INTC_PSR_32B_tag PSR248_251; /* offset: 0x0138 size: 32 bit */
15944 INTC_PSR_32B_tag PSR252_255; /* offset: 0x013C size: 32 bit */
15945 INTC_PSR_32B_tag PSR256_259; /* offset: 0x0140 size: 32 bit */
15946 INTC_PSR_32B_tag PSR260_263; /* offset: 0x0144 size: 32 bit */
15947 INTC_PSR_32B_tag PSR264_267; /* offset: 0x0148 size: 32 bit */
15948 INTC_PSR_32B_tag PSR268_271; /* offset: 0x014C size: 32 bit */
15949 INTC_PSR_32B_tag PSR272_275; /* offset: 0x0150 size: 32 bit */
15950 INTC_PSR_32B_tag PSR276_279; /* offset: 0x0154 size: 32 bit */
15951 INTC_PSR_32B_tag PSR280_283; /* offset: 0x0158 size: 32 bit */
15952 INTC_PSR_32B_tag PSR284_287; /* offset: 0x015C size: 32 bit */
15953 INTC_PSR_32B_tag PSR288_291; /* offset: 0x0160 size: 32 bit */
15954 INTC_PSR_32B_tag PSR292_295; /* offset: 0x0164 size: 32 bit */
15955 INTC_PSR_32B_tag PSR296_299; /* offset: 0x0168 size: 32 bit */
15956 INTC_PSR_32B_tag PSR300_303; /* offset: 0x016C size: 32 bit */
15957 INTC_PSR_32B_tag PSR304_307; /* offset: 0x0170 size: 32 bit */
15958 INTC_PSR_32B_tag PSR308_311; /* offset: 0x0174 size: 32 bit */
15959 INTC_PSR_32B_tag PSR312_315; /* offset: 0x0178 size: 32 bit */
15960 INTC_PSR_32B_tag PSR316_319; /* offset: 0x017C size: 32 bit */
15961 INTC_PSR_32B_tag PSR320_323; /* offset: 0x0180 size: 32 bit */
15962 INTC_PSR_32B_tag PSR324_327; /* offset: 0x0184 size: 32 bit */
15963 INTC_PSR_32B_tag PSR328_331; /* offset: 0x0188 size: 32 bit */
15964 INTC_PSR_32B_tag PSR332_335; /* offset: 0x018C size: 32 bit */
15965 INTC_PSR_32B_tag PSR336_339; /* offset: 0x0190 size: 32 bit */
15966 INTC_PSR_32B_tag PSR340_343; /* offset: 0x0194 size: 32 bit */
15967 INTC_PSR_32B_tag PSR344_347; /* offset: 0x0198 size: 32 bit */
15968 INTC_PSR_32B_tag PSR348_351; /* offset: 0x019C size: 32 bit */
15969 INTC_PSR_32B_tag PSR352_355; /* offset: 0x01A0 size: 32 bit */
15970 INTC_PSR_32B_tag PSR356_359; /* offset: 0x01A4 size: 32 bit */
15971 INTC_PSR_32B_tag PSR360_363; /* offset: 0x01A8 size: 32 bit */
15972 INTC_PSR_32B_tag PSR364_367; /* offset: 0x01AC size: 32 bit */
15973 INTC_PSR_32B_tag PSR368_371; /* offset: 0x01B0 size: 32 bit */
15974 INTC_PSR_32B_tag PSR372_375; /* offset: 0x01B4 size: 32 bit */
15975 INTC_PSR_32B_tag PSR376_379; /* offset: 0x01B8 size: 32 bit */
15976 INTC_PSR_32B_tag PSR380_383; /* offset: 0x01BC size: 32 bit */
15977 INTC_PSR_32B_tag PSR384_387; /* offset: 0x01C0 size: 32 bit */
15978 INTC_PSR_32B_tag PSR388_391; /* offset: 0x01C4 size: 32 bit */
15979 INTC_PSR_32B_tag PSR392_395; /* offset: 0x01C8 size: 32 bit */
15980 INTC_PSR_32B_tag PSR396_399; /* offset: 0x01CC size: 32 bit */
15981 INTC_PSR_32B_tag PSR400_403; /* offset: 0x01D0 size: 32 bit */
15982 INTC_PSR_32B_tag PSR404_407; /* offset: 0x01D4 size: 32 bit */
15983 INTC_PSR_32B_tag PSR408_411; /* offset: 0x01D8 size: 32 bit */
15984 INTC_PSR_32B_tag PSR412_415; /* offset: 0x01DC size: 32 bit */
15985 INTC_PSR_32B_tag PSR416_419; /* offset: 0x01E0 size: 32 bit */
15986 INTC_PSR_32B_tag PSR420_423; /* offset: 0x01E4 size: 32 bit */
15987 INTC_PSR_32B_tag PSR424_427; /* offset: 0x01E8 size: 32 bit */
15988 INTC_PSR_32B_tag PSR428_431; /* offset: 0x01EC size: 32 bit */
15989 INTC_PSR_32B_tag PSR432_435; /* offset: 0x01F0 size: 32 bit */
15990 INTC_PSR_32B_tag PSR436_439; /* offset: 0x01F4 size: 32 bit */
15991 INTC_PSR_32B_tag PSR440_443; /* offset: 0x01F8 size: 32 bit */
15992 INTC_PSR_32B_tag PSR444_447; /* offset: 0x01FC size: 32 bit */
15993 INTC_PSR_32B_tag PSR448_451; /* offset: 0x0200 size: 32 bit */
15994 INTC_PSR_32B_tag PSR452_455; /* offset: 0x0204 size: 32 bit */
15995 INTC_PSR_32B_tag PSR456_459; /* offset: 0x0208 size: 32 bit */
15996 INTC_PSR_32B_tag PSR460_463; /* offset: 0x020C size: 32 bit */
15997 INTC_PSR_32B_tag PSR464_467; /* offset: 0x0210 size: 32 bit */
15998 INTC_PSR_32B_tag PSR468_471; /* offset: 0x0214 size: 32 bit */
15999 INTC_PSR_32B_tag PSR472_475; /* offset: 0x0218 size: 32 bit */
16000 INTC_PSR_32B_tag PSR476_479; /* offset: 0x021C size: 32 bit */
16001 INTC_PSR_32B_tag PSR480_483; /* offset: 0x0220 size: 32 bit */
16002 INTC_PSR_32B_tag PSR484_487; /* offset: 0x0224 size: 32 bit */
16003 INTC_PSR_32B_tag PSR488_491; /* offset: 0x0228 size: 32 bit */
16004 INTC_PSR_32B_tag PSR492_495; /* offset: 0x022C size: 32 bit */
16005 INTC_PSR_32B_tag PSR496_499; /* offset: 0x0230 size: 32 bit */
16006 INTC_PSR_32B_tag PSR500_503; /* offset: 0x0234 size: 32 bit */
16007 INTC_PSR_32B_tag PSR504_507; /* offset: 0x0238 size: 32 bit */
16008 INTC_PSR_32B_tag PSR508_511; /* offset: 0x023C size: 32 bit */
16009 };
16010
16011 struct {
16012 /* PSR0-511 - Priority Select Registers */
16013 INTC_PSR_8B_tag PSR0; /* offset: 0x0040 size: 8 bit */
16014 INTC_PSR_8B_tag PSR1; /* offset: 0x0041 size: 8 bit */
16015 INTC_PSR_8B_tag PSR2; /* offset: 0x0042 size: 8 bit */
16016 INTC_PSR_8B_tag PSR3; /* offset: 0x0043 size: 8 bit */
16017 INTC_PSR_8B_tag PSR4; /* offset: 0x0044 size: 8 bit */
16018 INTC_PSR_8B_tag PSR5; /* offset: 0x0045 size: 8 bit */
16019 INTC_PSR_8B_tag PSR6; /* offset: 0x0046 size: 8 bit */
16020 INTC_PSR_8B_tag PSR7; /* offset: 0x0047 size: 8 bit */
16021 INTC_PSR_8B_tag PSR8; /* offset: 0x0048 size: 8 bit */
16022 INTC_PSR_8B_tag PSR9; /* offset: 0x0049 size: 8 bit */
16023 INTC_PSR_8B_tag PSR10; /* offset: 0x004A size: 8 bit */
16024 INTC_PSR_8B_tag PSR11; /* offset: 0x004B size: 8 bit */
16025 INTC_PSR_8B_tag PSR12; /* offset: 0x004C size: 8 bit */
16026 INTC_PSR_8B_tag PSR13; /* offset: 0x004D size: 8 bit */
16027 INTC_PSR_8B_tag PSR14; /* offset: 0x004E size: 8 bit */
16028 INTC_PSR_8B_tag PSR15; /* offset: 0x004F size: 8 bit */
16029 INTC_PSR_8B_tag PSR16; /* offset: 0x0050 size: 8 bit */
16030 INTC_PSR_8B_tag PSR17; /* offset: 0x0051 size: 8 bit */
16031 INTC_PSR_8B_tag PSR18; /* offset: 0x0052 size: 8 bit */
16032 INTC_PSR_8B_tag PSR19; /* offset: 0x0053 size: 8 bit */
16033 INTC_PSR_8B_tag PSR20; /* offset: 0x0054 size: 8 bit */
16034 INTC_PSR_8B_tag PSR21; /* offset: 0x0055 size: 8 bit */
16035 INTC_PSR_8B_tag PSR22; /* offset: 0x0056 size: 8 bit */
16036 INTC_PSR_8B_tag PSR23; /* offset: 0x0057 size: 8 bit */
16037 INTC_PSR_8B_tag PSR24; /* offset: 0x0058 size: 8 bit */
16038 INTC_PSR_8B_tag PSR25; /* offset: 0x0059 size: 8 bit */
16039 INTC_PSR_8B_tag PSR26; /* offset: 0x005A size: 8 bit */
16040 INTC_PSR_8B_tag PSR27; /* offset: 0x005B size: 8 bit */
16041 INTC_PSR_8B_tag PSR28; /* offset: 0x005C size: 8 bit */
16042 INTC_PSR_8B_tag PSR29; /* offset: 0x005D size: 8 bit */
16043 INTC_PSR_8B_tag PSR30; /* offset: 0x005E size: 8 bit */
16044 INTC_PSR_8B_tag PSR31; /* offset: 0x005F size: 8 bit */
16045 INTC_PSR_8B_tag PSR32; /* offset: 0x0060 size: 8 bit */
16046 INTC_PSR_8B_tag PSR33; /* offset: 0x0061 size: 8 bit */
16047 INTC_PSR_8B_tag PSR34; /* offset: 0x0062 size: 8 bit */
16048 INTC_PSR_8B_tag PSR35; /* offset: 0x0063 size: 8 bit */
16049 INTC_PSR_8B_tag PSR36; /* offset: 0x0064 size: 8 bit */
16050 INTC_PSR_8B_tag PSR37; /* offset: 0x0065 size: 8 bit */
16051 INTC_PSR_8B_tag PSR38; /* offset: 0x0066 size: 8 bit */
16052 INTC_PSR_8B_tag PSR39; /* offset: 0x0067 size: 8 bit */
16053 INTC_PSR_8B_tag PSR40; /* offset: 0x0068 size: 8 bit */
16054 INTC_PSR_8B_tag PSR41; /* offset: 0x0069 size: 8 bit */
16055 INTC_PSR_8B_tag PSR42; /* offset: 0x006A size: 8 bit */
16056 INTC_PSR_8B_tag PSR43; /* offset: 0x006B size: 8 bit */
16057 INTC_PSR_8B_tag PSR44; /* offset: 0x006C size: 8 bit */
16058 INTC_PSR_8B_tag PSR45; /* offset: 0x006D size: 8 bit */
16059 INTC_PSR_8B_tag PSR46; /* offset: 0x006E size: 8 bit */
16060 INTC_PSR_8B_tag PSR47; /* offset: 0x006F size: 8 bit */
16061 INTC_PSR_8B_tag PSR48; /* offset: 0x0070 size: 8 bit */
16062 INTC_PSR_8B_tag PSR49; /* offset: 0x0071 size: 8 bit */
16063 INTC_PSR_8B_tag PSR50; /* offset: 0x0072 size: 8 bit */
16064 INTC_PSR_8B_tag PSR51; /* offset: 0x0073 size: 8 bit */
16065 INTC_PSR_8B_tag PSR52; /* offset: 0x0074 size: 8 bit */
16066 INTC_PSR_8B_tag PSR53; /* offset: 0x0075 size: 8 bit */
16067 INTC_PSR_8B_tag PSR54; /* offset: 0x0076 size: 8 bit */
16068 INTC_PSR_8B_tag PSR55; /* offset: 0x0077 size: 8 bit */
16069 INTC_PSR_8B_tag PSR56; /* offset: 0x0078 size: 8 bit */
16070 INTC_PSR_8B_tag PSR57; /* offset: 0x0079 size: 8 bit */
16071 INTC_PSR_8B_tag PSR58; /* offset: 0x007A size: 8 bit */
16072 INTC_PSR_8B_tag PSR59; /* offset: 0x007B size: 8 bit */
16073 INTC_PSR_8B_tag PSR60; /* offset: 0x007C size: 8 bit */
16074 INTC_PSR_8B_tag PSR61; /* offset: 0x007D size: 8 bit */
16075 INTC_PSR_8B_tag PSR62; /* offset: 0x007E size: 8 bit */
16076 INTC_PSR_8B_tag PSR63; /* offset: 0x007F size: 8 bit */
16077 INTC_PSR_8B_tag PSR64; /* offset: 0x0080 size: 8 bit */
16078 INTC_PSR_8B_tag PSR65; /* offset: 0x0081 size: 8 bit */
16079 INTC_PSR_8B_tag PSR66; /* offset: 0x0082 size: 8 bit */
16080 INTC_PSR_8B_tag PSR67; /* offset: 0x0083 size: 8 bit */
16081 INTC_PSR_8B_tag PSR68; /* offset: 0x0084 size: 8 bit */
16082 INTC_PSR_8B_tag PSR69; /* offset: 0x0085 size: 8 bit */
16083 INTC_PSR_8B_tag PSR70; /* offset: 0x0086 size: 8 bit */
16084 INTC_PSR_8B_tag PSR71; /* offset: 0x0087 size: 8 bit */
16085 INTC_PSR_8B_tag PSR72; /* offset: 0x0088 size: 8 bit */
16086 INTC_PSR_8B_tag PSR73; /* offset: 0x0089 size: 8 bit */
16087 INTC_PSR_8B_tag PSR74; /* offset: 0x008A size: 8 bit */
16088 INTC_PSR_8B_tag PSR75; /* offset: 0x008B size: 8 bit */
16089 INTC_PSR_8B_tag PSR76; /* offset: 0x008C size: 8 bit */
16090 INTC_PSR_8B_tag PSR77; /* offset: 0x008D size: 8 bit */
16091 INTC_PSR_8B_tag PSR78; /* offset: 0x008E size: 8 bit */
16092 INTC_PSR_8B_tag PSR79; /* offset: 0x008F size: 8 bit */
16093 INTC_PSR_8B_tag PSR80; /* offset: 0x0090 size: 8 bit */
16094 INTC_PSR_8B_tag PSR81; /* offset: 0x0091 size: 8 bit */
16095 INTC_PSR_8B_tag PSR82; /* offset: 0x0092 size: 8 bit */
16096 INTC_PSR_8B_tag PSR83; /* offset: 0x0093 size: 8 bit */
16097 INTC_PSR_8B_tag PSR84; /* offset: 0x0094 size: 8 bit */
16098 INTC_PSR_8B_tag PSR85; /* offset: 0x0095 size: 8 bit */
16099 INTC_PSR_8B_tag PSR86; /* offset: 0x0096 size: 8 bit */
16100 INTC_PSR_8B_tag PSR87; /* offset: 0x0097 size: 8 bit */
16101 INTC_PSR_8B_tag PSR88; /* offset: 0x0098 size: 8 bit */
16102 INTC_PSR_8B_tag PSR89; /* offset: 0x0099 size: 8 bit */
16103 INTC_PSR_8B_tag PSR90; /* offset: 0x009A size: 8 bit */
16104 INTC_PSR_8B_tag PSR91; /* offset: 0x009B size: 8 bit */
16105 INTC_PSR_8B_tag PSR92; /* offset: 0x009C size: 8 bit */
16106 INTC_PSR_8B_tag PSR93; /* offset: 0x009D size: 8 bit */
16107 INTC_PSR_8B_tag PSR94; /* offset: 0x009E size: 8 bit */
16108 INTC_PSR_8B_tag PSR95; /* offset: 0x009F size: 8 bit */
16109 INTC_PSR_8B_tag PSR96; /* offset: 0x00A0 size: 8 bit */
16110 INTC_PSR_8B_tag PSR97; /* offset: 0x00A1 size: 8 bit */
16111 INTC_PSR_8B_tag PSR98; /* offset: 0x00A2 size: 8 bit */
16112 INTC_PSR_8B_tag PSR99; /* offset: 0x00A3 size: 8 bit */
16113 INTC_PSR_8B_tag PSR100; /* offset: 0x00A4 size: 8 bit */
16114 INTC_PSR_8B_tag PSR101; /* offset: 0x00A5 size: 8 bit */
16115 INTC_PSR_8B_tag PSR102; /* offset: 0x00A6 size: 8 bit */
16116 INTC_PSR_8B_tag PSR103; /* offset: 0x00A7 size: 8 bit */
16117 INTC_PSR_8B_tag PSR104; /* offset: 0x00A8 size: 8 bit */
16118 INTC_PSR_8B_tag PSR105; /* offset: 0x00A9 size: 8 bit */
16119 INTC_PSR_8B_tag PSR106; /* offset: 0x00AA size: 8 bit */
16120 INTC_PSR_8B_tag PSR107; /* offset: 0x00AB size: 8 bit */
16121 INTC_PSR_8B_tag PSR108; /* offset: 0x00AC size: 8 bit */
16122 INTC_PSR_8B_tag PSR109; /* offset: 0x00AD size: 8 bit */
16123 INTC_PSR_8B_tag PSR110; /* offset: 0x00AE size: 8 bit */
16124 INTC_PSR_8B_tag PSR111; /* offset: 0x00AF size: 8 bit */
16125 INTC_PSR_8B_tag PSR112; /* offset: 0x00B0 size: 8 bit */
16126 INTC_PSR_8B_tag PSR113; /* offset: 0x00B1 size: 8 bit */
16127 INTC_PSR_8B_tag PSR114; /* offset: 0x00B2 size: 8 bit */
16128 INTC_PSR_8B_tag PSR115; /* offset: 0x00B3 size: 8 bit */
16129 INTC_PSR_8B_tag PSR116; /* offset: 0x00B4 size: 8 bit */
16130 INTC_PSR_8B_tag PSR117; /* offset: 0x00B5 size: 8 bit */
16131 INTC_PSR_8B_tag PSR118; /* offset: 0x00B6 size: 8 bit */
16132 INTC_PSR_8B_tag PSR119; /* offset: 0x00B7 size: 8 bit */
16133 INTC_PSR_8B_tag PSR120; /* offset: 0x00B8 size: 8 bit */
16134 INTC_PSR_8B_tag PSR121; /* offset: 0x00B9 size: 8 bit */
16135 INTC_PSR_8B_tag PSR122; /* offset: 0x00BA size: 8 bit */
16136 INTC_PSR_8B_tag PSR123; /* offset: 0x00BB size: 8 bit */
16137 INTC_PSR_8B_tag PSR124; /* offset: 0x00BC size: 8 bit */
16138 INTC_PSR_8B_tag PSR125; /* offset: 0x00BD size: 8 bit */
16139 INTC_PSR_8B_tag PSR126; /* offset: 0x00BE size: 8 bit */
16140 INTC_PSR_8B_tag PSR127; /* offset: 0x00BF size: 8 bit */
16141 INTC_PSR_8B_tag PSR128; /* offset: 0x00C0 size: 8 bit */
16142 INTC_PSR_8B_tag PSR129; /* offset: 0x00C1 size: 8 bit */
16143 INTC_PSR_8B_tag PSR130; /* offset: 0x00C2 size: 8 bit */
16144 INTC_PSR_8B_tag PSR131; /* offset: 0x00C3 size: 8 bit */
16145 INTC_PSR_8B_tag PSR132; /* offset: 0x00C4 size: 8 bit */
16146 INTC_PSR_8B_tag PSR133; /* offset: 0x00C5 size: 8 bit */
16147 INTC_PSR_8B_tag PSR134; /* offset: 0x00C6 size: 8 bit */
16148 INTC_PSR_8B_tag PSR135; /* offset: 0x00C7 size: 8 bit */
16149 INTC_PSR_8B_tag PSR136; /* offset: 0x00C8 size: 8 bit */
16150 INTC_PSR_8B_tag PSR137; /* offset: 0x00C9 size: 8 bit */
16151 INTC_PSR_8B_tag PSR138; /* offset: 0x00CA size: 8 bit */
16152 INTC_PSR_8B_tag PSR139; /* offset: 0x00CB size: 8 bit */
16153 INTC_PSR_8B_tag PSR140; /* offset: 0x00CC size: 8 bit */
16154 INTC_PSR_8B_tag PSR141; /* offset: 0x00CD size: 8 bit */
16155 INTC_PSR_8B_tag PSR142; /* offset: 0x00CE size: 8 bit */
16156 INTC_PSR_8B_tag PSR143; /* offset: 0x00CF size: 8 bit */
16157 INTC_PSR_8B_tag PSR144; /* offset: 0x00D0 size: 8 bit */
16158 INTC_PSR_8B_tag PSR145; /* offset: 0x00D1 size: 8 bit */
16159 INTC_PSR_8B_tag PSR146; /* offset: 0x00D2 size: 8 bit */
16160 INTC_PSR_8B_tag PSR147; /* offset: 0x00D3 size: 8 bit */
16161 INTC_PSR_8B_tag PSR148; /* offset: 0x00D4 size: 8 bit */
16162 INTC_PSR_8B_tag PSR149; /* offset: 0x00D5 size: 8 bit */
16163 INTC_PSR_8B_tag PSR150; /* offset: 0x00D6 size: 8 bit */
16164 INTC_PSR_8B_tag PSR151; /* offset: 0x00D7 size: 8 bit */
16165 INTC_PSR_8B_tag PSR152; /* offset: 0x00D8 size: 8 bit */
16166 INTC_PSR_8B_tag PSR153; /* offset: 0x00D9 size: 8 bit */
16167 INTC_PSR_8B_tag PSR154; /* offset: 0x00DA size: 8 bit */
16168 INTC_PSR_8B_tag PSR155; /* offset: 0x00DB size: 8 bit */
16169 INTC_PSR_8B_tag PSR156; /* offset: 0x00DC size: 8 bit */
16170 INTC_PSR_8B_tag PSR157; /* offset: 0x00DD size: 8 bit */
16171 INTC_PSR_8B_tag PSR158; /* offset: 0x00DE size: 8 bit */
16172 INTC_PSR_8B_tag PSR159; /* offset: 0x00DF size: 8 bit */
16173 INTC_PSR_8B_tag PSR160; /* offset: 0x00E0 size: 8 bit */
16174 INTC_PSR_8B_tag PSR161; /* offset: 0x00E1 size: 8 bit */
16175 INTC_PSR_8B_tag PSR162; /* offset: 0x00E2 size: 8 bit */
16176 INTC_PSR_8B_tag PSR163; /* offset: 0x00E3 size: 8 bit */
16177 INTC_PSR_8B_tag PSR164; /* offset: 0x00E4 size: 8 bit */
16178 INTC_PSR_8B_tag PSR165; /* offset: 0x00E5 size: 8 bit */
16179 INTC_PSR_8B_tag PSR166; /* offset: 0x00E6 size: 8 bit */
16180 INTC_PSR_8B_tag PSR167; /* offset: 0x00E7 size: 8 bit */
16181 INTC_PSR_8B_tag PSR168; /* offset: 0x00E8 size: 8 bit */
16182 INTC_PSR_8B_tag PSR169; /* offset: 0x00E9 size: 8 bit */
16183 INTC_PSR_8B_tag PSR170; /* offset: 0x00EA size: 8 bit */
16184 INTC_PSR_8B_tag PSR171; /* offset: 0x00EB size: 8 bit */
16185 INTC_PSR_8B_tag PSR172; /* offset: 0x00EC size: 8 bit */
16186 INTC_PSR_8B_tag PSR173; /* offset: 0x00ED size: 8 bit */
16187 INTC_PSR_8B_tag PSR174; /* offset: 0x00EE size: 8 bit */
16188 INTC_PSR_8B_tag PSR175; /* offset: 0x00EF size: 8 bit */
16189 INTC_PSR_8B_tag PSR176; /* offset: 0x00F0 size: 8 bit */
16190 INTC_PSR_8B_tag PSR177; /* offset: 0x00F1 size: 8 bit */
16191 INTC_PSR_8B_tag PSR178; /* offset: 0x00F2 size: 8 bit */
16192 INTC_PSR_8B_tag PSR179; /* offset: 0x00F3 size: 8 bit */
16193 INTC_PSR_8B_tag PSR180; /* offset: 0x00F4 size: 8 bit */
16194 INTC_PSR_8B_tag PSR181; /* offset: 0x00F5 size: 8 bit */
16195 INTC_PSR_8B_tag PSR182; /* offset: 0x00F6 size: 8 bit */
16196 INTC_PSR_8B_tag PSR183; /* offset: 0x00F7 size: 8 bit */
16197 INTC_PSR_8B_tag PSR184; /* offset: 0x00F8 size: 8 bit */
16198 INTC_PSR_8B_tag PSR185; /* offset: 0x00F9 size: 8 bit */
16199 INTC_PSR_8B_tag PSR186; /* offset: 0x00FA size: 8 bit */
16200 INTC_PSR_8B_tag PSR187; /* offset: 0x00FB size: 8 bit */
16201 INTC_PSR_8B_tag PSR188; /* offset: 0x00FC size: 8 bit */
16202 INTC_PSR_8B_tag PSR189; /* offset: 0x00FD size: 8 bit */
16203 INTC_PSR_8B_tag PSR190; /* offset: 0x00FE size: 8 bit */
16204 INTC_PSR_8B_tag PSR191; /* offset: 0x00FF size: 8 bit */
16205 INTC_PSR_8B_tag PSR192; /* offset: 0x0100 size: 8 bit */
16206 INTC_PSR_8B_tag PSR193; /* offset: 0x0101 size: 8 bit */
16207 INTC_PSR_8B_tag PSR194; /* offset: 0x0102 size: 8 bit */
16208 INTC_PSR_8B_tag PSR195; /* offset: 0x0103 size: 8 bit */
16209 INTC_PSR_8B_tag PSR196; /* offset: 0x0104 size: 8 bit */
16210 INTC_PSR_8B_tag PSR197; /* offset: 0x0105 size: 8 bit */
16211 INTC_PSR_8B_tag PSR198; /* offset: 0x0106 size: 8 bit */
16212 INTC_PSR_8B_tag PSR199; /* offset: 0x0107 size: 8 bit */
16213 INTC_PSR_8B_tag PSR200; /* offset: 0x0108 size: 8 bit */
16214 INTC_PSR_8B_tag PSR201; /* offset: 0x0109 size: 8 bit */
16215 INTC_PSR_8B_tag PSR202; /* offset: 0x010A size: 8 bit */
16216 INTC_PSR_8B_tag PSR203; /* offset: 0x010B size: 8 bit */
16217 INTC_PSR_8B_tag PSR204; /* offset: 0x010C size: 8 bit */
16218 INTC_PSR_8B_tag PSR205; /* offset: 0x010D size: 8 bit */
16219 INTC_PSR_8B_tag PSR206; /* offset: 0x010E size: 8 bit */
16220 INTC_PSR_8B_tag PSR207; /* offset: 0x010F size: 8 bit */
16221 INTC_PSR_8B_tag PSR208; /* offset: 0x0110 size: 8 bit */
16222 INTC_PSR_8B_tag PSR209; /* offset: 0x0111 size: 8 bit */
16223 INTC_PSR_8B_tag PSR210; /* offset: 0x0112 size: 8 bit */
16224 INTC_PSR_8B_tag PSR211; /* offset: 0x0113 size: 8 bit */
16225 INTC_PSR_8B_tag PSR212; /* offset: 0x0114 size: 8 bit */
16226 INTC_PSR_8B_tag PSR213; /* offset: 0x0115 size: 8 bit */
16227 INTC_PSR_8B_tag PSR214; /* offset: 0x0116 size: 8 bit */
16228 INTC_PSR_8B_tag PSR215; /* offset: 0x0117 size: 8 bit */
16229 INTC_PSR_8B_tag PSR216; /* offset: 0x0118 size: 8 bit */
16230 INTC_PSR_8B_tag PSR217; /* offset: 0x0119 size: 8 bit */
16231 INTC_PSR_8B_tag PSR218; /* offset: 0x011A size: 8 bit */
16232 INTC_PSR_8B_tag PSR219; /* offset: 0x011B size: 8 bit */
16233 INTC_PSR_8B_tag PSR220; /* offset: 0x011C size: 8 bit */
16234 INTC_PSR_8B_tag PSR221; /* offset: 0x011D size: 8 bit */
16235 INTC_PSR_8B_tag PSR222; /* offset: 0x011E size: 8 bit */
16236 INTC_PSR_8B_tag PSR223; /* offset: 0x011F size: 8 bit */
16237 INTC_PSR_8B_tag PSR224; /* offset: 0x0120 size: 8 bit */
16238 INTC_PSR_8B_tag PSR225; /* offset: 0x0121 size: 8 bit */
16239 INTC_PSR_8B_tag PSR226; /* offset: 0x0122 size: 8 bit */
16240 INTC_PSR_8B_tag PSR227; /* offset: 0x0123 size: 8 bit */
16241 INTC_PSR_8B_tag PSR228; /* offset: 0x0124 size: 8 bit */
16242 INTC_PSR_8B_tag PSR229; /* offset: 0x0125 size: 8 bit */
16243 INTC_PSR_8B_tag PSR230; /* offset: 0x0126 size: 8 bit */
16244 INTC_PSR_8B_tag PSR231; /* offset: 0x0127 size: 8 bit */
16245 INTC_PSR_8B_tag PSR232; /* offset: 0x0128 size: 8 bit */
16246 INTC_PSR_8B_tag PSR233; /* offset: 0x0129 size: 8 bit */
16247 INTC_PSR_8B_tag PSR234; /* offset: 0x012A size: 8 bit */
16248 INTC_PSR_8B_tag PSR235; /* offset: 0x012B size: 8 bit */
16249 INTC_PSR_8B_tag PSR236; /* offset: 0x012C size: 8 bit */
16250 INTC_PSR_8B_tag PSR237; /* offset: 0x012D size: 8 bit */
16251 INTC_PSR_8B_tag PSR238; /* offset: 0x012E size: 8 bit */
16252 INTC_PSR_8B_tag PSR239; /* offset: 0x012F size: 8 bit */
16253 INTC_PSR_8B_tag PSR240; /* offset: 0x0130 size: 8 bit */
16254 INTC_PSR_8B_tag PSR241; /* offset: 0x0131 size: 8 bit */
16255 INTC_PSR_8B_tag PSR242; /* offset: 0x0132 size: 8 bit */
16256 INTC_PSR_8B_tag PSR243; /* offset: 0x0133 size: 8 bit */
16257 INTC_PSR_8B_tag PSR244; /* offset: 0x0134 size: 8 bit */
16258 INTC_PSR_8B_tag PSR245; /* offset: 0x0135 size: 8 bit */
16259 INTC_PSR_8B_tag PSR246; /* offset: 0x0136 size: 8 bit */
16260 INTC_PSR_8B_tag PSR247; /* offset: 0x0137 size: 8 bit */
16261 INTC_PSR_8B_tag PSR248; /* offset: 0x0138 size: 8 bit */
16262 INTC_PSR_8B_tag PSR249; /* offset: 0x0139 size: 8 bit */
16263 INTC_PSR_8B_tag PSR250; /* offset: 0x013A size: 8 bit */
16264 INTC_PSR_8B_tag PSR251; /* offset: 0x013B size: 8 bit */
16265 INTC_PSR_8B_tag PSR252; /* offset: 0x013C size: 8 bit */
16266 INTC_PSR_8B_tag PSR253; /* offset: 0x013D size: 8 bit */
16267 INTC_PSR_8B_tag PSR254; /* offset: 0x013E size: 8 bit */
16268 INTC_PSR_8B_tag PSR255; /* offset: 0x013F size: 8 bit */
16269 INTC_PSR_8B_tag PSR256; /* offset: 0x0140 size: 8 bit */
16270 INTC_PSR_8B_tag PSR257; /* offset: 0x0141 size: 8 bit */
16271 INTC_PSR_8B_tag PSR258; /* offset: 0x0142 size: 8 bit */
16272 INTC_PSR_8B_tag PSR259; /* offset: 0x0143 size: 8 bit */
16273 INTC_PSR_8B_tag PSR260; /* offset: 0x0144 size: 8 bit */
16274 INTC_PSR_8B_tag PSR261; /* offset: 0x0145 size: 8 bit */
16275 INTC_PSR_8B_tag PSR262; /* offset: 0x0146 size: 8 bit */
16276 INTC_PSR_8B_tag PSR263; /* offset: 0x0147 size: 8 bit */
16277 INTC_PSR_8B_tag PSR264; /* offset: 0x0148 size: 8 bit */
16278 INTC_PSR_8B_tag PSR265; /* offset: 0x0149 size: 8 bit */
16279 INTC_PSR_8B_tag PSR266; /* offset: 0x014A size: 8 bit */
16280 INTC_PSR_8B_tag PSR267; /* offset: 0x014B size: 8 bit */
16281 INTC_PSR_8B_tag PSR268; /* offset: 0x014C size: 8 bit */
16282 INTC_PSR_8B_tag PSR269; /* offset: 0x014D size: 8 bit */
16283 INTC_PSR_8B_tag PSR270; /* offset: 0x014E size: 8 bit */
16284 INTC_PSR_8B_tag PSR271; /* offset: 0x014F size: 8 bit */
16285 INTC_PSR_8B_tag PSR272; /* offset: 0x0150 size: 8 bit */
16286 INTC_PSR_8B_tag PSR273; /* offset: 0x0151 size: 8 bit */
16287 INTC_PSR_8B_tag PSR274; /* offset: 0x0152 size: 8 bit */
16288 INTC_PSR_8B_tag PSR275; /* offset: 0x0153 size: 8 bit */
16289 INTC_PSR_8B_tag PSR276; /* offset: 0x0154 size: 8 bit */
16290 INTC_PSR_8B_tag PSR277; /* offset: 0x0155 size: 8 bit */
16291 INTC_PSR_8B_tag PSR278; /* offset: 0x0156 size: 8 bit */
16292 INTC_PSR_8B_tag PSR279; /* offset: 0x0157 size: 8 bit */
16293 INTC_PSR_8B_tag PSR280; /* offset: 0x0158 size: 8 bit */
16294 INTC_PSR_8B_tag PSR281; /* offset: 0x0159 size: 8 bit */
16295 INTC_PSR_8B_tag PSR282; /* offset: 0x015A size: 8 bit */
16296 INTC_PSR_8B_tag PSR283; /* offset: 0x015B size: 8 bit */
16297 INTC_PSR_8B_tag PSR284; /* offset: 0x015C size: 8 bit */
16298 INTC_PSR_8B_tag PSR285; /* offset: 0x015D size: 8 bit */
16299 INTC_PSR_8B_tag PSR286; /* offset: 0x015E size: 8 bit */
16300 INTC_PSR_8B_tag PSR287; /* offset: 0x015F size: 8 bit */
16301 INTC_PSR_8B_tag PSR288; /* offset: 0x0160 size: 8 bit */
16302 INTC_PSR_8B_tag PSR289; /* offset: 0x0161 size: 8 bit */
16303 INTC_PSR_8B_tag PSR290; /* offset: 0x0162 size: 8 bit */
16304 INTC_PSR_8B_tag PSR291; /* offset: 0x0163 size: 8 bit */
16305 INTC_PSR_8B_tag PSR292; /* offset: 0x0164 size: 8 bit */
16306 INTC_PSR_8B_tag PSR293; /* offset: 0x0165 size: 8 bit */
16307 INTC_PSR_8B_tag PSR294; /* offset: 0x0166 size: 8 bit */
16308 INTC_PSR_8B_tag PSR295; /* offset: 0x0167 size: 8 bit */
16309 INTC_PSR_8B_tag PSR296; /* offset: 0x0168 size: 8 bit */
16310 INTC_PSR_8B_tag PSR297; /* offset: 0x0169 size: 8 bit */
16311 INTC_PSR_8B_tag PSR298; /* offset: 0x016A size: 8 bit */
16312 INTC_PSR_8B_tag PSR299; /* offset: 0x016B size: 8 bit */
16313 INTC_PSR_8B_tag PSR300; /* offset: 0x016C size: 8 bit */
16314 INTC_PSR_8B_tag PSR301; /* offset: 0x016D size: 8 bit */
16315 INTC_PSR_8B_tag PSR302; /* offset: 0x016E size: 8 bit */
16316 INTC_PSR_8B_tag PSR303; /* offset: 0x016F size: 8 bit */
16317 INTC_PSR_8B_tag PSR304; /* offset: 0x0170 size: 8 bit */
16318 INTC_PSR_8B_tag PSR305; /* offset: 0x0171 size: 8 bit */
16319 INTC_PSR_8B_tag PSR306; /* offset: 0x0172 size: 8 bit */
16320 INTC_PSR_8B_tag PSR307; /* offset: 0x0173 size: 8 bit */
16321 INTC_PSR_8B_tag PSR308; /* offset: 0x0174 size: 8 bit */
16322 INTC_PSR_8B_tag PSR309; /* offset: 0x0175 size: 8 bit */
16323 INTC_PSR_8B_tag PSR310; /* offset: 0x0176 size: 8 bit */
16324 INTC_PSR_8B_tag PSR311; /* offset: 0x0177 size: 8 bit */
16325 INTC_PSR_8B_tag PSR312; /* offset: 0x0178 size: 8 bit */
16326 INTC_PSR_8B_tag PSR313; /* offset: 0x0179 size: 8 bit */
16327 INTC_PSR_8B_tag PSR314; /* offset: 0x017A size: 8 bit */
16328 INTC_PSR_8B_tag PSR315; /* offset: 0x017B size: 8 bit */
16329 INTC_PSR_8B_tag PSR316; /* offset: 0x017C size: 8 bit */
16330 INTC_PSR_8B_tag PSR317; /* offset: 0x017D size: 8 bit */
16331 INTC_PSR_8B_tag PSR318; /* offset: 0x017E size: 8 bit */
16332 INTC_PSR_8B_tag PSR319; /* offset: 0x017F size: 8 bit */
16333 INTC_PSR_8B_tag PSR320; /* offset: 0x0180 size: 8 bit */
16334 INTC_PSR_8B_tag PSR321; /* offset: 0x0181 size: 8 bit */
16335 INTC_PSR_8B_tag PSR322; /* offset: 0x0182 size: 8 bit */
16336 INTC_PSR_8B_tag PSR323; /* offset: 0x0183 size: 8 bit */
16337 INTC_PSR_8B_tag PSR324; /* offset: 0x0184 size: 8 bit */
16338 INTC_PSR_8B_tag PSR325; /* offset: 0x0185 size: 8 bit */
16339 INTC_PSR_8B_tag PSR326; /* offset: 0x0186 size: 8 bit */
16340 INTC_PSR_8B_tag PSR327; /* offset: 0x0187 size: 8 bit */
16341 INTC_PSR_8B_tag PSR328; /* offset: 0x0188 size: 8 bit */
16342 INTC_PSR_8B_tag PSR329; /* offset: 0x0189 size: 8 bit */
16343 INTC_PSR_8B_tag PSR330; /* offset: 0x018A size: 8 bit */
16344 INTC_PSR_8B_tag PSR331; /* offset: 0x018B size: 8 bit */
16345 INTC_PSR_8B_tag PSR332; /* offset: 0x018C size: 8 bit */
16346 INTC_PSR_8B_tag PSR333; /* offset: 0x018D size: 8 bit */
16347 INTC_PSR_8B_tag PSR334; /* offset: 0x018E size: 8 bit */
16348 INTC_PSR_8B_tag PSR335; /* offset: 0x018F size: 8 bit */
16349 INTC_PSR_8B_tag PSR336; /* offset: 0x0190 size: 8 bit */
16350 INTC_PSR_8B_tag PSR337; /* offset: 0x0191 size: 8 bit */
16351 INTC_PSR_8B_tag PSR338; /* offset: 0x0192 size: 8 bit */
16352 INTC_PSR_8B_tag PSR339; /* offset: 0x0193 size: 8 bit */
16353 INTC_PSR_8B_tag PSR340; /* offset: 0x0194 size: 8 bit */
16354 INTC_PSR_8B_tag PSR341; /* offset: 0x0195 size: 8 bit */
16355 INTC_PSR_8B_tag PSR342; /* offset: 0x0196 size: 8 bit */
16356 INTC_PSR_8B_tag PSR343; /* offset: 0x0197 size: 8 bit */
16357 INTC_PSR_8B_tag PSR344; /* offset: 0x0198 size: 8 bit */
16358 INTC_PSR_8B_tag PSR345; /* offset: 0x0199 size: 8 bit */
16359 INTC_PSR_8B_tag PSR346; /* offset: 0x019A size: 8 bit */
16360 INTC_PSR_8B_tag PSR347; /* offset: 0x019B size: 8 bit */
16361 INTC_PSR_8B_tag PSR348; /* offset: 0x019C size: 8 bit */
16362 INTC_PSR_8B_tag PSR349; /* offset: 0x019D size: 8 bit */
16363 INTC_PSR_8B_tag PSR350; /* offset: 0x019E size: 8 bit */
16364 INTC_PSR_8B_tag PSR351; /* offset: 0x019F size: 8 bit */
16365 INTC_PSR_8B_tag PSR352; /* offset: 0x01A0 size: 8 bit */
16366 INTC_PSR_8B_tag PSR353; /* offset: 0x01A1 size: 8 bit */
16367 INTC_PSR_8B_tag PSR354; /* offset: 0x01A2 size: 8 bit */
16368 INTC_PSR_8B_tag PSR355; /* offset: 0x01A3 size: 8 bit */
16369 INTC_PSR_8B_tag PSR356; /* offset: 0x01A4 size: 8 bit */
16370 INTC_PSR_8B_tag PSR357; /* offset: 0x01A5 size: 8 bit */
16371 INTC_PSR_8B_tag PSR358; /* offset: 0x01A6 size: 8 bit */
16372 INTC_PSR_8B_tag PSR359; /* offset: 0x01A7 size: 8 bit */
16373 INTC_PSR_8B_tag PSR360; /* offset: 0x01A8 size: 8 bit */
16374 INTC_PSR_8B_tag PSR361; /* offset: 0x01A9 size: 8 bit */
16375 INTC_PSR_8B_tag PSR362; /* offset: 0x01AA size: 8 bit */
16376 INTC_PSR_8B_tag PSR363; /* offset: 0x01AB size: 8 bit */
16377 INTC_PSR_8B_tag PSR364; /* offset: 0x01AC size: 8 bit */
16378 INTC_PSR_8B_tag PSR365; /* offset: 0x01AD size: 8 bit */
16379 INTC_PSR_8B_tag PSR366; /* offset: 0x01AE size: 8 bit */
16380 INTC_PSR_8B_tag PSR367; /* offset: 0x01AF size: 8 bit */
16381 INTC_PSR_8B_tag PSR368; /* offset: 0x01B0 size: 8 bit */
16382 INTC_PSR_8B_tag PSR369; /* offset: 0x01B1 size: 8 bit */
16383 INTC_PSR_8B_tag PSR370; /* offset: 0x01B2 size: 8 bit */
16384 INTC_PSR_8B_tag PSR371; /* offset: 0x01B3 size: 8 bit */
16385 INTC_PSR_8B_tag PSR372; /* offset: 0x01B4 size: 8 bit */
16386 INTC_PSR_8B_tag PSR373; /* offset: 0x01B5 size: 8 bit */
16387 INTC_PSR_8B_tag PSR374; /* offset: 0x01B6 size: 8 bit */
16388 INTC_PSR_8B_tag PSR375; /* offset: 0x01B7 size: 8 bit */
16389 INTC_PSR_8B_tag PSR376; /* offset: 0x01B8 size: 8 bit */
16390 INTC_PSR_8B_tag PSR377; /* offset: 0x01B9 size: 8 bit */
16391 INTC_PSR_8B_tag PSR378; /* offset: 0x01BA size: 8 bit */
16392 INTC_PSR_8B_tag PSR379; /* offset: 0x01BB size: 8 bit */
16393 INTC_PSR_8B_tag PSR380; /* offset: 0x01BC size: 8 bit */
16394 INTC_PSR_8B_tag PSR381; /* offset: 0x01BD size: 8 bit */
16395 INTC_PSR_8B_tag PSR382; /* offset: 0x01BE size: 8 bit */
16396 INTC_PSR_8B_tag PSR383; /* offset: 0x01BF size: 8 bit */
16397 INTC_PSR_8B_tag PSR384; /* offset: 0x01C0 size: 8 bit */
16398 INTC_PSR_8B_tag PSR385; /* offset: 0x01C1 size: 8 bit */
16399 INTC_PSR_8B_tag PSR386; /* offset: 0x01C2 size: 8 bit */
16400 INTC_PSR_8B_tag PSR387; /* offset: 0x01C3 size: 8 bit */
16401 INTC_PSR_8B_tag PSR388; /* offset: 0x01C4 size: 8 bit */
16402 INTC_PSR_8B_tag PSR389; /* offset: 0x01C5 size: 8 bit */
16403 INTC_PSR_8B_tag PSR390; /* offset: 0x01C6 size: 8 bit */
16404 INTC_PSR_8B_tag PSR391; /* offset: 0x01C7 size: 8 bit */
16405 INTC_PSR_8B_tag PSR392; /* offset: 0x01C8 size: 8 bit */
16406 INTC_PSR_8B_tag PSR393; /* offset: 0x01C9 size: 8 bit */
16407 INTC_PSR_8B_tag PSR394; /* offset: 0x01CA size: 8 bit */
16408 INTC_PSR_8B_tag PSR395; /* offset: 0x01CB size: 8 bit */
16409 INTC_PSR_8B_tag PSR396; /* offset: 0x01CC size: 8 bit */
16410 INTC_PSR_8B_tag PSR397; /* offset: 0x01CD size: 8 bit */
16411 INTC_PSR_8B_tag PSR398; /* offset: 0x01CE size: 8 bit */
16412 INTC_PSR_8B_tag PSR399; /* offset: 0x01CF size: 8 bit */
16413 INTC_PSR_8B_tag PSR400; /* offset: 0x01D0 size: 8 bit */
16414 INTC_PSR_8B_tag PSR401; /* offset: 0x01D1 size: 8 bit */
16415 INTC_PSR_8B_tag PSR402; /* offset: 0x01D2 size: 8 bit */
16416 INTC_PSR_8B_tag PSR403; /* offset: 0x01D3 size: 8 bit */
16417 INTC_PSR_8B_tag PSR404; /* offset: 0x01D4 size: 8 bit */
16418 INTC_PSR_8B_tag PSR405; /* offset: 0x01D5 size: 8 bit */
16419 INTC_PSR_8B_tag PSR406; /* offset: 0x01D6 size: 8 bit */
16420 INTC_PSR_8B_tag PSR407; /* offset: 0x01D7 size: 8 bit */
16421 INTC_PSR_8B_tag PSR408; /* offset: 0x01D8 size: 8 bit */
16422 INTC_PSR_8B_tag PSR409; /* offset: 0x01D9 size: 8 bit */
16423 INTC_PSR_8B_tag PSR410; /* offset: 0x01DA size: 8 bit */
16424 INTC_PSR_8B_tag PSR411; /* offset: 0x01DB size: 8 bit */
16425 INTC_PSR_8B_tag PSR412; /* offset: 0x01DC size: 8 bit */
16426 INTC_PSR_8B_tag PSR413; /* offset: 0x01DD size: 8 bit */
16427 INTC_PSR_8B_tag PSR414; /* offset: 0x01DE size: 8 bit */
16428 INTC_PSR_8B_tag PSR415; /* offset: 0x01DF size: 8 bit */
16429 INTC_PSR_8B_tag PSR416; /* offset: 0x01E0 size: 8 bit */
16430 INTC_PSR_8B_tag PSR417; /* offset: 0x01E1 size: 8 bit */
16431 INTC_PSR_8B_tag PSR418; /* offset: 0x01E2 size: 8 bit */
16432 INTC_PSR_8B_tag PSR419; /* offset: 0x01E3 size: 8 bit */
16433 INTC_PSR_8B_tag PSR420; /* offset: 0x01E4 size: 8 bit */
16434 INTC_PSR_8B_tag PSR421; /* offset: 0x01E5 size: 8 bit */
16435 INTC_PSR_8B_tag PSR422; /* offset: 0x01E6 size: 8 bit */
16436 INTC_PSR_8B_tag PSR423; /* offset: 0x01E7 size: 8 bit */
16437 INTC_PSR_8B_tag PSR424; /* offset: 0x01E8 size: 8 bit */
16438 INTC_PSR_8B_tag PSR425; /* offset: 0x01E9 size: 8 bit */
16439 INTC_PSR_8B_tag PSR426; /* offset: 0x01EA size: 8 bit */
16440 INTC_PSR_8B_tag PSR427; /* offset: 0x01EB size: 8 bit */
16441 INTC_PSR_8B_tag PSR428; /* offset: 0x01EC size: 8 bit */
16442 INTC_PSR_8B_tag PSR429; /* offset: 0x01ED size: 8 bit */
16443 INTC_PSR_8B_tag PSR430; /* offset: 0x01EE size: 8 bit */
16444 INTC_PSR_8B_tag PSR431; /* offset: 0x01EF size: 8 bit */
16445 INTC_PSR_8B_tag PSR432; /* offset: 0x01F0 size: 8 bit */
16446 INTC_PSR_8B_tag PSR433; /* offset: 0x01F1 size: 8 bit */
16447 INTC_PSR_8B_tag PSR434; /* offset: 0x01F2 size: 8 bit */
16448 INTC_PSR_8B_tag PSR435; /* offset: 0x01F3 size: 8 bit */
16449 INTC_PSR_8B_tag PSR436; /* offset: 0x01F4 size: 8 bit */
16450 INTC_PSR_8B_tag PSR437; /* offset: 0x01F5 size: 8 bit */
16451 INTC_PSR_8B_tag PSR438; /* offset: 0x01F6 size: 8 bit */
16452 INTC_PSR_8B_tag PSR439; /* offset: 0x01F7 size: 8 bit */
16453 INTC_PSR_8B_tag PSR440; /* offset: 0x01F8 size: 8 bit */
16454 INTC_PSR_8B_tag PSR441; /* offset: 0x01F9 size: 8 bit */
16455 INTC_PSR_8B_tag PSR442; /* offset: 0x01FA size: 8 bit */
16456 INTC_PSR_8B_tag PSR443; /* offset: 0x01FB size: 8 bit */
16457 INTC_PSR_8B_tag PSR444; /* offset: 0x01FC size: 8 bit */
16458 INTC_PSR_8B_tag PSR445; /* offset: 0x01FD size: 8 bit */
16459 INTC_PSR_8B_tag PSR446; /* offset: 0x01FE size: 8 bit */
16460 INTC_PSR_8B_tag PSR447; /* offset: 0x01FF size: 8 bit */
16461 INTC_PSR_8B_tag PSR448; /* offset: 0x0200 size: 8 bit */
16462 INTC_PSR_8B_tag PSR449; /* offset: 0x0201 size: 8 bit */
16463 INTC_PSR_8B_tag PSR450; /* offset: 0x0202 size: 8 bit */
16464 INTC_PSR_8B_tag PSR451; /* offset: 0x0203 size: 8 bit */
16465 INTC_PSR_8B_tag PSR452; /* offset: 0x0204 size: 8 bit */
16466 INTC_PSR_8B_tag PSR453; /* offset: 0x0205 size: 8 bit */
16467 INTC_PSR_8B_tag PSR454; /* offset: 0x0206 size: 8 bit */
16468 INTC_PSR_8B_tag PSR455; /* offset: 0x0207 size: 8 bit */
16469 INTC_PSR_8B_tag PSR456; /* offset: 0x0208 size: 8 bit */
16470 INTC_PSR_8B_tag PSR457; /* offset: 0x0209 size: 8 bit */
16471 INTC_PSR_8B_tag PSR458; /* offset: 0x020A size: 8 bit */
16472 INTC_PSR_8B_tag PSR459; /* offset: 0x020B size: 8 bit */
16473 INTC_PSR_8B_tag PSR460; /* offset: 0x020C size: 8 bit */
16474 INTC_PSR_8B_tag PSR461; /* offset: 0x020D size: 8 bit */
16475 INTC_PSR_8B_tag PSR462; /* offset: 0x020E size: 8 bit */
16476 INTC_PSR_8B_tag PSR463; /* offset: 0x020F size: 8 bit */
16477 INTC_PSR_8B_tag PSR464; /* offset: 0x0210 size: 8 bit */
16478 INTC_PSR_8B_tag PSR465; /* offset: 0x0211 size: 8 bit */
16479 INTC_PSR_8B_tag PSR466; /* offset: 0x0212 size: 8 bit */
16480 INTC_PSR_8B_tag PSR467; /* offset: 0x0213 size: 8 bit */
16481 INTC_PSR_8B_tag PSR468; /* offset: 0x0214 size: 8 bit */
16482 INTC_PSR_8B_tag PSR469; /* offset: 0x0215 size: 8 bit */
16483 INTC_PSR_8B_tag PSR470; /* offset: 0x0216 size: 8 bit */
16484 INTC_PSR_8B_tag PSR471; /* offset: 0x0217 size: 8 bit */
16485 INTC_PSR_8B_tag PSR472; /* offset: 0x0218 size: 8 bit */
16486 INTC_PSR_8B_tag PSR473; /* offset: 0x0219 size: 8 bit */
16487 INTC_PSR_8B_tag PSR474; /* offset: 0x021A size: 8 bit */
16488 INTC_PSR_8B_tag PSR475; /* offset: 0x021B size: 8 bit */
16489 INTC_PSR_8B_tag PSR476; /* offset: 0x021C size: 8 bit */
16490 INTC_PSR_8B_tag PSR477; /* offset: 0x021D size: 8 bit */
16491 INTC_PSR_8B_tag PSR478; /* offset: 0x021E size: 8 bit */
16492 INTC_PSR_8B_tag PSR479; /* offset: 0x021F size: 8 bit */
16493 INTC_PSR_8B_tag PSR480; /* offset: 0x0220 size: 8 bit */
16494 INTC_PSR_8B_tag PSR481; /* offset: 0x0221 size: 8 bit */
16495 INTC_PSR_8B_tag PSR482; /* offset: 0x0222 size: 8 bit */
16496 INTC_PSR_8B_tag PSR483; /* offset: 0x0223 size: 8 bit */
16497 INTC_PSR_8B_tag PSR484; /* offset: 0x0224 size: 8 bit */
16498 INTC_PSR_8B_tag PSR485; /* offset: 0x0225 size: 8 bit */
16499 INTC_PSR_8B_tag PSR486; /* offset: 0x0226 size: 8 bit */
16500 INTC_PSR_8B_tag PSR487; /* offset: 0x0227 size: 8 bit */
16501 INTC_PSR_8B_tag PSR488; /* offset: 0x0228 size: 8 bit */
16502 INTC_PSR_8B_tag PSR489; /* offset: 0x0229 size: 8 bit */
16503 INTC_PSR_8B_tag PSR490; /* offset: 0x022A size: 8 bit */
16504 INTC_PSR_8B_tag PSR491; /* offset: 0x022B size: 8 bit */
16505 INTC_PSR_8B_tag PSR492; /* offset: 0x022C size: 8 bit */
16506 INTC_PSR_8B_tag PSR493; /* offset: 0x022D size: 8 bit */
16507 INTC_PSR_8B_tag PSR494; /* offset: 0x022E size: 8 bit */
16508 INTC_PSR_8B_tag PSR495; /* offset: 0x022F size: 8 bit */
16509 INTC_PSR_8B_tag PSR496; /* offset: 0x0230 size: 8 bit */
16510 INTC_PSR_8B_tag PSR497; /* offset: 0x0231 size: 8 bit */
16511 INTC_PSR_8B_tag PSR498; /* offset: 0x0232 size: 8 bit */
16512 INTC_PSR_8B_tag PSR499; /* offset: 0x0233 size: 8 bit */
16513 INTC_PSR_8B_tag PSR500; /* offset: 0x0234 size: 8 bit */
16514 INTC_PSR_8B_tag PSR501; /* offset: 0x0235 size: 8 bit */
16515 INTC_PSR_8B_tag PSR502; /* offset: 0x0236 size: 8 bit */
16516 INTC_PSR_8B_tag PSR503; /* offset: 0x0237 size: 8 bit */
16517 INTC_PSR_8B_tag PSR504; /* offset: 0x0238 size: 8 bit */
16518 INTC_PSR_8B_tag PSR505; /* offset: 0x0239 size: 8 bit */
16519 INTC_PSR_8B_tag PSR506; /* offset: 0x023A size: 8 bit */
16520 INTC_PSR_8B_tag PSR507; /* offset: 0x023B size: 8 bit */
16521 INTC_PSR_8B_tag PSR508; /* offset: 0x023C size: 8 bit */
16522 INTC_PSR_8B_tag PSR509; /* offset: 0x023D size: 8 bit */
16523 INTC_PSR_8B_tag PSR510; /* offset: 0x023E size: 8 bit */
16524 INTC_PSR_8B_tag PSR511; /* offset: 0x023F size: 8 bit */
16525 };
16526
16527 };
16528 } INTC_tag;
16529
16530
16531#define INTC (*(volatile INTC_tag *) 0xFFF48000UL)
16532
16533
16534
16535/****************************************************************/
16536/* */
16537/* Module: DSPI */
16538/* */
16539/****************************************************************/
16540
16541 typedef union DSPI_MCR_tag { /* MCR - Module Configuration Register */
16542 uint32_t R;
16543 struct {
16544 uint32_t MSTR:1; /* Master/Slave mode select */
16545 uint32_t CONT_SCKE:1; /* Continuous SCK Enable */
16546 uint32_t DCONF:2; /* DSPI Configuration */
16547 uint32_t FRZ:1; /* Freeze */
16548 uint32_t MTFE:1; /* Modified Timing Format Enable */
16549 uint32_t PCSSE:1; /* Peripheral Chip Select Strobe Enable */
16550 uint32_t ROOE:1; /* Receive FIFO Overflow Overwrite Enable */
16551 uint32_t PCSIS7:1; /* Peripheral Chip Select 7 Inactive State */
16552 uint32_t PCSIS6:1; /* Peripheral Chip Select 6 Inactive State */
16553 uint32_t PCSIS5:1; /* Peripheral Chip Select 5 Inactive State */
16554 uint32_t PCSIS4:1; /* Peripheral Chip Select 4 Inactive State */
16555 uint32_t PCSIS3:1; /* Peripheral Chip Select 3 Inactive State */
16556 uint32_t PCSIS2:1; /* Peripheral Chip Select 2 Inactive State */
16557 uint32_t PCSIS1:1; /* Peripheral Chip Select 1 Inactive State */
16558 uint32_t PCSIS0:1; /* Peripheral Chip Select 0 Inactive State */
16559 uint32_t DOZE:1; /* Doze Enable */
16560 uint32_t MDIS:1; /* Module Disable */
16561 uint32_t DIS_TXF:1; /* Disable Transmit FIFO */
16562 uint32_t DIS_RXF:1; /* Disable Receive FIFO */
16563 uint32_t CLR_TXF:1; /* Clear TX FIFO */
16564 uint32_t CLR_RXF:1; /* Clear RX FIFO */
16565 uint32_t SMPL_PT:2; /* Sample Point */
16566 uint32_t:7;
16567 uint32_t HALT:1; /* Halt */
16568 } B;
16569 } DSPI_MCR_32B_tag;
16570
16571 typedef union { /* TCR - Transfer Count Register */
16572 uint32_t R;
16573 struct {
16574#ifndef USE_FIELD_ALIASES_DSPI
16575 uint32_t SPI_TCNT:16; /* SPI Transfer Counter */
16576#else
16577 uint32_t TCNT:16; /* deprecated name - please avoid */
16578#endif
16579 uint32_t:16;
16580 } B;
16581 } DSPI_TCR_32B_tag;
16582
16583
16584 /* Register layout for all registers CTAR... */
16585
16586 typedef union DSPI_CTAR_tag { /* CTAR0-7 - Clock and Transfer Attribute Registers */
16587 uint32_t R;
16588 struct {
16589 uint32_t DBR:1; /* Double Baud Rate */
16590 uint32_t FMSZ:4; /* Frame Size */
16591 uint32_t CPOL:1; /* Clock Polarity */
16592 uint32_t CPHA:1; /* Clock Phase */
16593 uint32_t LSBFE:1; /* LSB First Enable */
16594 uint32_t PCSSCK:2; /* PCS to SCK Delay Prescaler */
16595 uint32_t PASC:2; /* After SCK Delay Prescaler */
16596 uint32_t PDT:2; /* Delay after Transfer Prescaler */
16597 uint32_t PBR:2; /* Baud Rate Prescaler */
16598 uint32_t CSSCK:4; /* PCS to SCK Delay Scaler */
16599 uint32_t ASC:4; /* After SCK Delay Scaler */
16600 uint32_t DT:4; /* Delay after Transfer Scaler */
16601 uint32_t BR:4; /* Baud Rate Scaler */
16602 } B;
16603 } DSPI_CTAR_32B_tag;
16604
16605 typedef union DSPI_SR_tag { /* SR - Status Register */
16606 uint32_t R;
16607 struct {
16608 uint32_t TCF:1; /* Transfer Complete Flag */
16609 uint32_t TXRXS:1; /* TX & RX Status */
16610 uint32_t:1;
16611 uint32_t EOQF:1; /* End of queue Flag */
16612 uint32_t TFUF:1; /* Transmit FIFO Underflow Flag */
16613 uint32_t:1;
16614 uint32_t TFFF:1; /* Transmit FIFO FIll Flag */
16615 uint32_t:5;
16616 uint32_t RFOF:1; /* Receive FIFO Overflow Flag */
16617 uint32_t:1;
16618 uint32_t RFDF:1; /* Receive FIFO Drain Flag */
16619 uint32_t:1;
16620 uint32_t TXCTR:4; /* TX FIFO Counter */
16621 uint32_t TXNXTPTR:4; /* Transmit Next Pointer */
16622 uint32_t RXCTR:4; /* RX FIFO Counter */
16623 uint32_t POPNXTPTR:4; /* Pop Next Pointer */
16624 } B;
16625 } DSPI_SR_32B_tag;
16626
16627 typedef union DSPI_RSER_tag { /* RSER - DMA/Interrupt Request Register */
16628 uint32_t R;
16629 struct {
16630#ifndef USE_FIELD_ALIASES_DSPI
16631 uint32_t TCF_RE:1; /* Transmission Complete Request Enable */
16632#else
16633 uint32_t TCFRE:1; /* deprecated name - please avoid */
16634#endif
16635 uint32_t:2;
16636#ifndef USE_FIELD_ALIASES_DSPI
16637 uint32_t EOQF_RE:1; /* DSPI Finished Request Enable */
16638#else
16639 uint32_t EOQFRE:1; /* deprecated name - please avoid */
16640#endif
16641#ifndef USE_FIELD_ALIASES_DSPI
16642 uint32_t TFUF_RE:1; /* Transmit FIFO Underflow Request Enable */
16643#else
16644 uint32_t TFUFRE:1; /* deprecated name - please avoid */
16645#endif
16646 uint32_t:1;
16647#ifndef USE_FIELD_ALIASES_DSPI
16648 uint32_t TFFF_RE:1; /* Transmit FIFO Fill Request Enable */
16649#else
16650 uint32_t TFFFRE:1; /* deprecated name - please avoid */
16651#endif
16652#ifndef USE_FIELD_ALIASES_DSPI
16653 uint32_t TFFF_DIRS:1; /* Transmit FIFO Fill DMA or Interrupt Request Select */
16654#else
16655 uint32_t TFFFDIRS:1; /* deprecated name - please avoid */
16656#endif
16657 uint32_t:4;
16658#ifndef USE_FIELD_ALIASES_DSPI
16659 uint32_t RFOF_RE:1; /* Receive FIFO overflow Request Enable */
16660#else
16661 uint32_t RFOFRE:1; /* deprecated name - please avoid */
16662#endif
16663 uint32_t:1;
16664#ifndef USE_FIELD_ALIASES_DSPI
16665 uint32_t RFDF_RE:1; /* Receive FIFO Drain Request Enable */
16666#else
16667 uint32_t RFDFRE:1; /* deprecated name - please avoid */
16668#endif
16669#ifndef USE_FIELD_ALIASES_DSPI
16670 uint32_t RFDF_DIRS:1; /* Receive FIFO Drain DMA or Interrupt Request Select */
16671#else
16672 uint32_t RFDFDIRS:1; /* deprecated name - please avoid */
16673#endif
16674 uint32_t:16;
16675 } B;
16676 } DSPI_RSER_32B_tag;
16677
16678 typedef union DSPI_PUSHR_tag { /* PUSHR - PUSH TX FIFO Register */
16679 uint32_t R;
16680 struct {
16681 uint32_t CONT:1; /* Continuous Peripheral Chip Select Enable */
16682 uint32_t CTAS:3; /* Clock and Transfer Attributes Select */
16683 uint32_t EOQ:1; /* End of Queue */
16684 uint32_t CTCNT:1; /* Clear SPI_TCNT */
16685 uint32_t:2;
16686 uint32_t PCS7:1; /* Peripheral Chip Select 7 */
16687 uint32_t PCS6:1; /* Peripheral Chip Select 6 */
16688 uint32_t PCS5:1; /* Peripheral Chip Select 5 */
16689 uint32_t PCS4:1; /* Peripheral Chip Select 4 */
16690 uint32_t PCS3:1; /* Peripheral Chip Select 3 */
16691 uint32_t PCS2:1; /* Peripheral Chip Select 2 */
16692 uint32_t PCS1:1; /* Peripheral Chip Select 1 */
16693 uint32_t PCS0:1; /* Peripheral Chip Select 0 */
16694 uint32_t TXDATA:16; /* Transmit Data */
16695 } B;
16696 } DSPI_PUSHR_32B_tag;
16697
16698 typedef union DSPI_POPR_tag { /* POPR - POP RX FIFO Register */
16699 uint32_t R;
16700 struct {
16701 uint32_t:16;
16702 uint32_t RXDATA:16; /* Receive Data */
16703 } B;
16704 } DSPI_POPR_32B_tag;
16705
16706
16707 /* Register layout for all registers TXFR... */
16708
16709 typedef union { /* Transmit FIFO Registers */
16710 uint32_t R;
16711 struct {
16712#ifndef USE_FIELD_ALIASES_DSPI
16713 uint32_t FIFO_TXCMD:16; /* Transmit Command */
16714#else
16715 uint32_t TXCMD:16; /* deprecated name - please avoid */
16716#endif
16717#ifndef USE_FIELD_ALIASES_DSPI
16718 uint32_t FIFO_TXDATA:16; /* Transmit Data */
16719#else
16720 uint32_t TXDATA:16; /* deprecated name - please avoid */
16721#endif
16722 } B;
16723 } DSPI_TXFR_32B_tag;
16724
16725
16726 /* Register layout for all registers RXFR... */
16727
16728 typedef union { /* Receive FIFO Registers */
16729 uint32_t R;
16730 struct {
16731 uint32_t:16;
16732#ifndef USE_FIELD_ALIASES_DSPI
16733 uint32_t FIFO_RXDATA:16; /* Transmit Data */
16734#else
16735 uint32_t RXDATA:16; /* deprecated name - please avoid */
16736#endif
16737 } B;
16738 } DSPI_RXFR_32B_tag;
16739
16740 typedef union { /* DSICR - DSI Configuration Register */
16741 uint32_t R;
16742 struct {
16743 uint32_t MTOE:1; /* Multiple Transfer Operation Enable */
16744 uint32_t:1;
16745 uint32_t MTOCNT:6; /* Multiple Transfer Operation Count */
16746 uint32_t:4;
16747 uint32_t TXSS:1; /* Transmit Data Source Select */
16748 uint32_t TPOL:1; /* Trigger Polarity */
16749 uint32_t TRRE:1; /* Trigger Reception Enable */
16750 uint32_t CID:1; /* Change in Data Transfer Enable */
16751 uint32_t DCONT:1; /* DSI Continuous Peripheral Chip Select Enable */
16752 uint32_t DSICTAS:3; /* DSI CLock and Transfer Attributes Select */
16753 uint32_t:4;
16754 uint32_t DPCS7:1; /* DSI Peripheral Chip Select 7 */
16755 uint32_t DPCS6:1; /* DSI Peripheral Chip Select 6 */
16756 uint32_t DPCS5:1; /* DSI Peripheral Chip Select 5 */
16757 uint32_t DPCS4:1; /* DSI Peripheral Chip Select 4 */
16758 uint32_t DPCS3:1; /* DSI Peripheral Chip Select 3 */
16759 uint32_t DPCS2:1; /* DSI Peripheral Chip Select 2 */
16760 uint32_t DPCS1:1; /* DSI Peripheral Chip Select 1 */
16761 uint32_t DPCS0:1; /* DSI Peripheral Chip Select 0 */
16762 } B;
16763 } DSPI_DSICR_32B_tag;
16764
16765 typedef union { /* SDR - DSI Serialization Data Register */
16766 uint32_t R;
16767 struct {
16768 uint32_t:16;
16769 uint32_t SER_DATA:16; /* Serialized Data */
16770 } B;
16771 } DSPI_SDR_32B_tag;
16772
16773 typedef union { /* ASDR - DSI Alternate Serialization Data Register */
16774 uint32_t R;
16775 struct {
16776 uint32_t:16;
16777 uint32_t ASER_DATA:16; /* Alternate Serialized Data */
16778 } B;
16779 } DSPI_ASDR_32B_tag;
16780
16781 typedef union { /* COMPR - DSI Transmit Comparison Register */
16782 uint32_t R;
16783 struct {
16784 uint32_t:16;
16785 uint32_t COMP_DATA:16; /* Compare Data */
16786 } B;
16787 } DSPI_COMPR_32B_tag;
16788
16789 typedef union { /* DDR - DSI Deserialization Data Register */
16790 uint32_t R;
16791 struct {
16792 uint32_t:16;
16793 uint32_t DESER_DATA:16; /* Deserialized Data */
16794 } B;
16795 } DSPI_DDR_32B_tag;
16796
16797 typedef union { /* DSICR1 - DSI Configuration Register 1 */
16798 uint32_t R;
16799 } DSPI_DSICR1_32B_tag;
16800
16801
16802
16803 typedef struct DSPI_tag { /* start of DSPI_tag */
16804 /* MCR - Module Configuration Register */
16805 DSPI_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */
16806 int8_t DSPI_reserved_0004[4];
16807 /* TCR - Transfer Count Register */
16808 DSPI_TCR_32B_tag TCR; /* offset: 0x0008 size: 32 bit */
16809 union {
16810 /* CTAR0-7 - Clock and Transfer Attribute Registers */
16811 DSPI_CTAR_32B_tag CTAR[8]; /* offset: 0x000C (0x0004 x 8) */
16812
16813 struct {
16814 /* CTAR0-7 - Clock and Transfer Attribute Registers */
16815 DSPI_CTAR_32B_tag CTAR0; /* offset: 0x000C size: 32 bit */
16816 DSPI_CTAR_32B_tag CTAR1; /* offset: 0x0010 size: 32 bit */
16817 DSPI_CTAR_32B_tag CTAR2; /* offset: 0x0014 size: 32 bit */
16818 DSPI_CTAR_32B_tag CTAR3; /* offset: 0x0018 size: 32 bit */
16819 DSPI_CTAR_32B_tag CTAR4; /* offset: 0x001C size: 32 bit */
16820 DSPI_CTAR_32B_tag CTAR5; /* offset: 0x0020 size: 32 bit */
16821 DSPI_CTAR_32B_tag CTAR6; /* offset: 0x0024 size: 32 bit */
16822 DSPI_CTAR_32B_tag CTAR7; /* offset: 0x0028 size: 32 bit */
16823 };
16824
16825 };
16826 /* SR - Status Register */
16827 DSPI_SR_32B_tag SR; /* offset: 0x002C size: 32 bit */
16828 /* RSER - DMA/Interrupt Request Register */
16829 DSPI_RSER_32B_tag RSER; /* offset: 0x0030 size: 32 bit */
16830 /* PUSHR - PUSH TX FIFO Register */
16831 DSPI_PUSHR_32B_tag PUSHR; /* offset: 0x0034 size: 32 bit */
16832 /* POPR - POP RX FIFO Register */
16833 DSPI_POPR_32B_tag POPR; /* offset: 0x0038 size: 32 bit */
16834 union {
16835 /* Transmit FIFO Registers */
16836 DSPI_TXFR_32B_tag TXFR[5]; /* offset: 0x003C (0x0004 x 5) */
16837
16838 struct {
16839 /* Transmit FIFO Registers */
16840 DSPI_TXFR_32B_tag TXFR0; /* offset: 0x003C size: 32 bit */
16841 DSPI_TXFR_32B_tag TXFR1; /* offset: 0x0040 size: 32 bit */
16842 DSPI_TXFR_32B_tag TXFR2; /* offset: 0x0044 size: 32 bit */
16843 DSPI_TXFR_32B_tag TXFR3; /* offset: 0x0048 size: 32 bit */
16844 DSPI_TXFR_32B_tag TXFR4; /* offset: 0x004C size: 32 bit */
16845 };
16846
16847 };
16848 int8_t DSPI_reserved_0050_C[44];
16849 union {
16850 /* Receive FIFO Registers */
16851 DSPI_RXFR_32B_tag RXFR[5]; /* offset: 0x007C (0x0004 x 5) */
16852
16853 struct {
16854 /* Receive FIFO Registers */
16855 DSPI_RXFR_32B_tag RXFR0; /* offset: 0x007C size: 32 bit */
16856 DSPI_RXFR_32B_tag RXFR1; /* offset: 0x0080 size: 32 bit */
16857 DSPI_RXFR_32B_tag RXFR2; /* offset: 0x0084 size: 32 bit */
16858 DSPI_RXFR_32B_tag RXFR3; /* offset: 0x0088 size: 32 bit */
16859 DSPI_RXFR_32B_tag RXFR4; /* offset: 0x008C size: 32 bit */
16860 };
16861
16862 };
16863 int8_t DSPI_reserved_0090[44];
16864 /* DSICR - DSI Configuration Register */
16865 DSPI_DSICR_32B_tag DSICR; /* offset: 0x00BC size: 32 bit */
16866 /* SDR - DSI Serialization Data Register */
16867 DSPI_SDR_32B_tag SDR; /* offset: 0x00C0 size: 32 bit */
16868 /* ASDR - DSI Alternate Serialization Data Register */
16869 DSPI_ASDR_32B_tag ASDR; /* offset: 0x00C4 size: 32 bit */
16870 /* COMPR - DSI Transmit Comparison Register */
16871 DSPI_COMPR_32B_tag COMPR; /* offset: 0x00C8 size: 32 bit */
16872 /* DDR - DSI Deserialization Data Register */
16873 DSPI_DDR_32B_tag DDR; /* offset: 0x00CC size: 32 bit */
16874 /* DSICR1 - DSI Configuration Register 1 */
16875 DSPI_DSICR1_32B_tag DSICR1; /* offset: 0x00D0 size: 32 bit */
16876 } DSPI_tag;
16877
16878
16879#define DSPI_A (*(volatile DSPI_tag *) 0xFFF90000UL)
16880#define DSPI_B (*(volatile DSPI_tag *) 0xFFF94000UL)
16881#define DSPI_C (*(volatile DSPI_tag *) 0xFFF98000UL)
16882
16883
16884
16885/****************************************************************/
16886/* */
16887/* Module: FLEXCAN */
16888/* */
16889/****************************************************************/
16890
16891 typedef union { /* MCR - Module Configuration Register */
16892 uint32_t R;
16893 struct {
16894 uint32_t MDIS:1; /* Module Disable */
16895 uint32_t FRZ:1; /* Freeze Enable */
16896 uint32_t FEN:1; /* FIFO Enable */
16897 uint32_t HALT:1; /* Halt Flexcan */
16898#ifndef USE_FIELD_ALIASES_FLEXCAN
16899 uint32_t NOT_RDY:1; /* Flexcan Not Ready */
16900#else
16901 uint32_t NOTRDY:1; /* deprecated name - please avoid */
16902#endif
16903#ifndef USE_FIELD_ALIASES_FLEXCAN
16904 uint32_t WAK_MSK:1; /* Wake Up Interrupt Mask */
16905#else
16906 uint32_t WAKMSK:1; /* deprecated name - please avoid */
16907#endif
16908#ifndef USE_FIELD_ALIASES_FLEXCAN
16909 uint32_t SOFT_RST:1; /* Soft Reset */
16910#else
16911 uint32_t SOFTRST:1; /* deprecated name - please avoid */
16912#endif
16913#ifndef USE_FIELD_ALIASES_FLEXCAN
16914 uint32_t FRZ_ACK:1; /* Freeze Mode Acknowledge */
16915#else
16916 uint32_t FRZACK:1; /* deprecated name - please avoid */
16917#endif
16918 uint32_t SUPV:1; /* Supervisor Mode */
16919#ifndef USE_FIELD_ALIASES_FLEXCAN
16920 uint32_t SLF_WAK:1; /* Self Wake Up */
16921#else
16922 uint32_t SLFWAK:1; /* deprecated name - please avoid */
16923#endif
16924#ifndef USE_FIELD_ALIASES_FLEXCAN
16925 uint32_t WRN_EN:1; /* Warning Interrupt Enable */
16926#else
16927 uint32_t WRNEN:1; /* deprecated name - please avoid */
16928#endif
16929#ifndef USE_FIELD_ALIASES_FLEXCAN
16930 uint32_t LPM_ACK:1; /* Low Power Mode Acknowledge */
16931#else
16932 uint32_t LPMACK:1; /* deprecated name - please avoid */
16933#endif
16934#ifndef USE_FIELD_ALIASES_FLEXCAN
16935 uint32_t WAK_SRC:1; /* Wake Up Source */
16936#else
16937 uint32_t WAKSRC:1; /* deprecated name - please avoid */
16938#endif
16939 uint32_t DOZE:1; /* Doze Mode Enable */
16940#ifndef USE_FIELD_ALIASES_FLEXCAN
16941 uint32_t SRX_DIS:1; /* Self Reception Disable */
16942#else
16943 uint32_t SRXDIS:1; /* deprecated name - please avoid */
16944#endif
16945 uint32_t BCC:1; /* Backwards Compatibility Configuration */
16946 uint32_t:2;
16947 uint32_t LPRIO_EN:1; /* Local Priority Enable */
16948 uint32_t AEN:1; /* Abort Enable */
16949 uint32_t:2;
16950 uint32_t IDAM:2; /* ID Acceptance Mode */
16951 uint32_t:2;
16952 uint32_t MAXMB:6; /* Maximum Number of Message Buffers */
16953 } B;
16954 } FLEXCAN_MCR_32B_tag;
16955
16956 typedef union { /* CTRL - Control Register */
16957 uint32_t R;
16958 struct {
16959 uint32_t PRESDIV:8; /* Prescaler Divsion Factor */
16960 uint32_t RJW:2; /* Resync Jump Width */
16961 uint32_t PSEG1:3; /* Phase Segment 1 */
16962 uint32_t PSEG2:3; /* Phase Segment 2 */
16963#ifndef USE_FIELD_ALIASES_FLEXCAN
16964 uint32_t BOFF_MSK:1; /* Bus Off Mask */
16965#else
16966 uint32_t BOFFMSK:1; /* deprecated name - please avoid */
16967#endif
16968#ifndef USE_FIELD_ALIASES_FLEXCAN
16969 uint32_t ERR_MSK:1; /* Error Mask */
16970#else
16971 uint32_t ERRMSK:1; /* deprecated name - please avoid */
16972#endif
16973#ifndef USE_FIELD_ALIASES_FLEXCAN
16974 uint32_t CLK_SRC:1; /* CAN Engine Clock Source */
16975#else
16976 uint32_t CLKSRC:1; /* deprecated name - please avoid */
16977#endif
16978 uint32_t LPB:1; /* Loop Back */
16979#ifndef USE_FIELD_ALIASES_FLEXCAN
16980 uint32_t TWRN_MSK:1; /* Tx Warning Interrupt Mask */
16981#else
16982 uint32_t TWRNMSK:1; /* deprecated name - please avoid */
16983#endif
16984#ifndef USE_FIELD_ALIASES_FLEXCAN
16985 uint32_t RWRN_MSK:1; /* Rx Warning Interrupt Mask */
16986#else
16987 uint32_t RWRNMSK:1; /* deprecated name - please avoid */
16988#endif
16989 uint32_t:2;
16990 uint32_t SMP:1; /* Sampling Mode */
16991#ifndef USE_FIELD_ALIASES_FLEXCAN
16992 uint32_t BOFF_REC:1; /* Bus Off Recovery Mode */
16993#else
16994 uint32_t BOFFREC:1; /* deprecated name - please avoid */
16995#endif
16996 uint32_t TSYN:1; /* Timer Sync Mode */
16997 uint32_t LBUF:1; /* Lowest Buffer Transmitted First */
16998 uint32_t LOM:1; /* Listen-Only Mode */
16999 uint32_t PROPSEG:3; /* Propagation Segment */
17000 } B;
17001 } FLEXCAN_CTRL_32B_tag;
17002
17003 typedef union { /* TIMER - Free Running Timer */
17004 uint32_t R;
17005 } FLEXCAN_TIMER_32B_tag;
17006
17007 typedef union { /* RXGMASK - Rx Global Mask Register */
17008 uint32_t R;
17009#ifndef USE_FIELD_ALIASES_FLEXCAN
17010 struct {
17011 uint32_t MI:32; /* deprecated field -- do not use */
17012 } B;
17013#endif
17014 } FLEXCAN_RXGMASK_32B_tag;
17015
17016 typedef union { /* RX14MASK - Rx 14 Mask Register */
17017 uint32_t R;
17018#ifndef USE_FIELD_ALIASES_FLEXCAN
17019 struct {
17020 uint32_t MI:32; /* deprecated field -- do not use */
17021 } B;
17022#endif
17023 } FLEXCAN_RX14MASK_32B_tag;
17024
17025 typedef union { /* RX15MASK - Rx 15 Mask Register */
17026 uint32_t R;
17027#ifndef USE_FIELD_ALIASES_FLEXCAN
17028 struct {
17029 uint32_t MI:32; /* deprecated field -- do not use */
17030 } B;
17031#endif
17032 } FLEXCAN_RX15MASK_32B_tag;
17033
17034 typedef union { /* ECR - Error Counter Register */
17035 uint32_t R;
17036 struct {
17037 uint32_t:16;
17038#ifndef USE_FIELD_ALIASES_FLEXCAN
17039 uint32_t RX_ERR_COUNTER:8; /* Rx Error Counter */
17040#else
17041 uint32_t RXECNT:8; /* deprecated name - please avoid */
17042#endif
17043#ifndef USE_FIELD_ALIASES_FLEXCAN
17044 uint32_t TX_ERR_COUNTER:8; /* Tx Error Counter */
17045#else
17046 uint32_t TXECNT:8; /* deprecated name - please avoid */
17047#endif
17048 } B;
17049 } FLEXCAN_ECR_32B_tag;
17050
17051 typedef union { /* ESR - Error and Status Register */
17052 uint32_t R;
17053 struct {
17054 uint32_t:14;
17055#ifndef USE_FIELD_ALIASES_FLEXCAN
17056 uint32_t TWRN_INT:1; /* Tx Warning Interrupt Flag */
17057#else
17058 uint32_t TWRNINT:1; /* deprecated name - please avoid */
17059#endif
17060#ifndef USE_FIELD_ALIASES_FLEXCAN
17061 uint32_t RWRN_INT:1; /* Rx Warning Interrupt Flag */
17062#else
17063 uint32_t RWRNINT:1; /* deprecated name - please avoid */
17064#endif
17065#ifndef USE_FIELD_ALIASES_FLEXCAN
17066 uint32_t BIT1_ERR:1; /* Bit 1 Error */
17067#else
17068 uint32_t BIT1ERR:1; /* deprecated name - please avoid */
17069#endif
17070#ifndef USE_FIELD_ALIASES_FLEXCAN
17071 uint32_t BIT0_ERR:1; /* Bit 0 Error */
17072#else
17073 uint32_t BIT0ERR:1; /* deprecated name - please avoid */
17074#endif
17075#ifndef USE_FIELD_ALIASES_FLEXCAN
17076 uint32_t ACK_ERR:1; /* Acknowledge Error */
17077#else
17078 uint32_t ACKERR:1; /* deprecated name - please avoid */
17079#endif
17080#ifndef USE_FIELD_ALIASES_FLEXCAN
17081 uint32_t CRC_ERR:1; /* Cyclic Redundancy Check Error */
17082#else
17083 uint32_t CRCERR:1; /* deprecated name - please avoid */
17084#endif
17085#ifndef USE_FIELD_ALIASES_FLEXCAN
17086 uint32_t FRM_ERR:1; /* Form Error */
17087#else
17088 uint32_t FRMERR:1; /* deprecated name - please avoid */
17089#endif
17090#ifndef USE_FIELD_ALIASES_FLEXCAN
17091 uint32_t STF_ERR:1; /* Stuffing Error */
17092#else
17093 uint32_t STFERR:1; /* deprecated name - please avoid */
17094#endif
17095#ifndef USE_FIELD_ALIASES_FLEXCAN
17096 uint32_t TX_WRN:1; /* Tx Error Counter */
17097#else
17098 uint32_t TXWRN:1; /* deprecated name - please avoid */
17099#endif
17100#ifndef USE_FIELD_ALIASES_FLEXCAN
17101 uint32_t RX_WRN:1; /* Rx Error Counter */
17102#else
17103 uint32_t RXWRN:1; /* deprecated name - please avoid */
17104#endif
17105 uint32_t IDLE:1; /* CAN bus Idle State */
17106 uint32_t TXRX:1; /* Current Flexcan Status */
17107#ifndef USE_FIELD_ALIASES_FLEXCAN
17108 uint32_t FLT_CONF:2; /* Fault Confinement State */
17109#else
17110 uint32_t FLTCONF:2; /* deprecated name - please avoid */
17111#endif
17112 uint32_t:1;
17113#ifndef USE_FIELD_ALIASES_FLEXCAN
17114 uint32_t BOFF_INT:1; /* Bus Off Interrupt */
17115#else
17116 uint32_t BOFFINT:1; /* deprecated name - please avoid */
17117#endif
17118#ifndef USE_FIELD_ALIASES_FLEXCAN
17119 uint32_t ERR_INT:1; /* Error Interrupt */
17120#else
17121 uint32_t ERRINT:1; /* deprecated name - please avoid */
17122#endif
17123#ifndef USE_FIELD_ALIASES_FLEXCAN
17124 uint32_t WAK_INT:1; /* Wake-Up Interrupt */
17125#else
17126 uint32_t WAKINT:1; /* deprecated name - please avoid */
17127#endif
17128 } B;
17129 } FLEXCAN_ESR_32B_tag;
17130
17131 typedef union { /* IMASK2 - Interrupt Masks 2 Register */
17132 uint32_t R;
17133 struct {
17134 uint32_t BUF63M:1; /* Buffer MB Mask 63 Bit */
17135 uint32_t BUF62M:1; /* Buffer MB Mask 62 Bit */
17136 uint32_t BUF61M:1; /* Buffer MB Mask 61 Bit */
17137 uint32_t BUF60M:1; /* Buffer MB Mask 60 Bit */
17138 uint32_t BUF59M:1; /* Buffer MB Mask 59 Bit */
17139 uint32_t BUF58M:1; /* Buffer MB Mask 58 Bit */
17140 uint32_t BUF57M:1; /* Buffer MB Mask 57 Bit */
17141 uint32_t BUF56M:1; /* Buffer MB Mask 56 Bit */
17142 uint32_t BUF55M:1; /* Buffer MB Mask 55 Bit */
17143 uint32_t BUF54M:1; /* Buffer MB Mask 54 Bit */
17144 uint32_t BUF53M:1; /* Buffer MB Mask 53 Bit */
17145 uint32_t BUF52M:1; /* Buffer MB Mask 52 Bit */
17146 uint32_t BUF51M:1; /* Buffer MB Mask 51 Bit */
17147 uint32_t BUF50M:1; /* Buffer MB Mask 50 Bit */
17148 uint32_t BUF49M:1; /* Buffer MB Mask 49 Bit */
17149 uint32_t BUF48M:1; /* Buffer MB Mask 48 Bit */
17150 uint32_t BUF47M:1; /* Buffer MB Mask 47 Bit */
17151 uint32_t BUF46M:1; /* Buffer MB Mask 46 Bit */
17152 uint32_t BUF45M:1; /* Buffer MB Mask 45 Bit */
17153 uint32_t BUF44M:1; /* Buffer MB Mask 44 Bit */
17154 uint32_t BUF43M:1; /* Buffer MB Mask 43 Bit */
17155 uint32_t BUF42M:1; /* Buffer MB Mask 42 Bit */
17156 uint32_t BUF41M:1; /* Buffer MB Mask 41 Bit */
17157 uint32_t BUF40M:1; /* Buffer MB Mask 40 Bit */
17158 uint32_t BUF39M:1; /* Buffer MB Mask 39 Bit */
17159 uint32_t BUF38M:1; /* Buffer MB Mask 38 Bit */
17160 uint32_t BUF37M:1; /* Buffer MB Mask 37 Bit */
17161 uint32_t BUF36M:1; /* Buffer MB Mask 36 Bit */
17162 uint32_t BUF35M:1; /* Buffer MB Mask 35 Bit */
17163 uint32_t BUF34M:1; /* Buffer MB Mask 34 Bit */
17164 uint32_t BUF33M:1; /* Buffer MB Mask 33 Bit */
17165 uint32_t BUF32M:1; /* Buffer MB Mask 32 Bit */
17166 } B;
17167 } FLEXCAN_IMASK2_32B_tag;
17168
17169 typedef union { /* IMASK1 - Interrupt Masks 1 Register */
17170 uint32_t R;
17171 struct {
17172 uint32_t BUF31M:1; /* Buffer MB Mask 31 Bit */
17173 uint32_t BUF30M:1; /* Buffer MB Mask 30 Bit */
17174 uint32_t BUF29M:1; /* Buffer MB Mask 29 Bit */
17175 uint32_t BUF28M:1; /* Buffer MB Mask 28 Bit */
17176 uint32_t BUF27M:1; /* Buffer MB Mask 27 Bit */
17177 uint32_t BUF26M:1; /* Buffer MB Mask 26 Bit */
17178 uint32_t BUF25M:1; /* Buffer MB Mask 25 Bit */
17179 uint32_t BUF24M:1; /* Buffer MB Mask 24 Bit */
17180 uint32_t BUF23M:1; /* Buffer MB Mask 23 Bit */
17181 uint32_t BUF22M:1; /* Buffer MB Mask 22 Bit */
17182 uint32_t BUF21M:1; /* Buffer MB Mask 21 Bit */
17183 uint32_t BUF20M:1; /* Buffer MB Mask 20 Bit */
17184 uint32_t BUF19M:1; /* Buffer MB Mask 19 Bit */
17185 uint32_t BUF18M:1; /* Buffer MB Mask 18 Bit */
17186 uint32_t BUF17M:1; /* Buffer MB Mask 17 Bit */
17187 uint32_t BUF16M:1; /* Buffer MB Mask 16 Bit */
17188 uint32_t BUF15M:1; /* Buffer MB Mask 15 Bit */
17189 uint32_t BUF14M:1; /* Buffer MB Mask 14 Bit */
17190 uint32_t BUF13M:1; /* Buffer MB Mask 13 Bit */
17191 uint32_t BUF12M:1; /* Buffer MB Mask 12 Bit */
17192 uint32_t BUF11M:1; /* Buffer MB Mask 11 Bit */
17193 uint32_t BUF10M:1; /* Buffer MB Mask 10 Bit */
17194#ifndef USE_FIELD_ALIASES_FLEXCAN
17195 uint32_t BUF9M:1; /* Buffer MB Mask 9 Bit */
17196#else
17197 uint32_t BUF09M:1; /* deprecated name - please avoid */
17198#endif
17199#ifndef USE_FIELD_ALIASES_FLEXCAN
17200 uint32_t BUF8M:1; /* Buffer MB Mask 8 Bit */
17201#else
17202 uint32_t BUF08M:1; /* deprecated name - please avoid */
17203#endif
17204#ifndef USE_FIELD_ALIASES_FLEXCAN
17205 uint32_t BUF7M:1; /* Buffer MB Mask 7 Bit */
17206#else
17207 uint32_t BUF07M:1; /* deprecated name - please avoid */
17208#endif
17209#ifndef USE_FIELD_ALIASES_FLEXCAN
17210 uint32_t BUF6M:1; /* Buffer MB Mask 6 Bit */
17211#else
17212 uint32_t BUF06M:1; /* deprecated name - please avoid */
17213#endif
17214#ifndef USE_FIELD_ALIASES_FLEXCAN
17215 uint32_t BUF5M:1; /* Buffer MB Mask 5 Bit */
17216#else
17217 uint32_t BUF05M:1; /* deprecated name - please avoid */
17218#endif
17219#ifndef USE_FIELD_ALIASES_FLEXCAN
17220 uint32_t BUF4M:1; /* Buffer MB Mask 4 Bit */
17221#else
17222 uint32_t BUF04M:1; /* deprecated name - please avoid */
17223#endif
17224#ifndef USE_FIELD_ALIASES_FLEXCAN
17225 uint32_t BUF3M:1; /* Buffer MB Mask 3 Bit */
17226#else
17227 uint32_t BUF03M:1; /* deprecated name - please avoid */
17228#endif
17229#ifndef USE_FIELD_ALIASES_FLEXCAN
17230 uint32_t BUF2M:1; /* Buffer MB Mask 2 Bit */
17231#else
17232 uint32_t BUF02M:1; /* deprecated name - please avoid */
17233#endif
17234#ifndef USE_FIELD_ALIASES_FLEXCAN
17235 uint32_t BUF1M:1; /* Buffer MB Mask 1 Bit */
17236#else
17237 uint32_t BUF01M:1; /* deprecated name - please avoid */
17238#endif
17239#ifndef USE_FIELD_ALIASES_FLEXCAN
17240 uint32_t BUF0M:1; /* Buffer MB Mask 0 Bit */
17241#else
17242 uint32_t BUF00M:1; /* deprecated name - please avoid */
17243#endif
17244 } B;
17245 } FLEXCAN_IMASK1_32B_tag;
17246
17247 typedef union { /* IFLAG2 - Interrupt Flags 2 Register */
17248 uint32_t R;
17249 struct {
17250 uint32_t BUF63I:1; /* Buffer MB Interrupt 63 Bit */
17251 uint32_t BUF62I:1; /* Buffer MB Interrupt 62 Bit */
17252 uint32_t BUF61I:1; /* Buffer MB Interrupt 61 Bit */
17253 uint32_t BUF60I:1; /* Buffer MB Interrupt 60 Bit */
17254 uint32_t BUF59I:1; /* Buffer MB Interrupt 59 Bit */
17255 uint32_t BUF58I:1; /* Buffer MB Interrupt 58 Bit */
17256 uint32_t BUF57I:1; /* Buffer MB Interrupt 57 Bit */
17257 uint32_t BUF56I:1; /* Buffer MB Interrupt 56 Bit */
17258 uint32_t BUF55I:1; /* Buffer MB Interrupt 55 Bit */
17259 uint32_t BUF54I:1; /* Buffer MB Interrupt 54 Bit */
17260 uint32_t BUF53I:1; /* Buffer MB Interrupt 53 Bit */
17261 uint32_t BUF52I:1; /* Buffer MB Interrupt 52 Bit */
17262 uint32_t BUF51I:1; /* Buffer MB Interrupt 51 Bit */
17263 uint32_t BUF50I:1; /* Buffer MB Interrupt 50 Bit */
17264 uint32_t BUF49I:1; /* Buffer MB Interrupt 49 Bit */
17265 uint32_t BUF48I:1; /* Buffer MB Interrupt 48 Bit */
17266 uint32_t BUF47I:1; /* Buffer MB Interrupt 47 Bit */
17267 uint32_t BUF46I:1; /* Buffer MB Interrupt 46 Bit */
17268 uint32_t BUF45I:1; /* Buffer MB Interrupt 45 Bit */
17269 uint32_t BUF44I:1; /* Buffer MB Interrupt 44 Bit */
17270 uint32_t BUF43I:1; /* Buffer MB Interrupt 43 Bit */
17271 uint32_t BUF42I:1; /* Buffer MB Interrupt 42 Bit */
17272 uint32_t BUF41I:1; /* Buffer MB Interrupt 41 Bit */
17273 uint32_t BUF40I:1; /* Buffer MB Interrupt 40 Bit */
17274 uint32_t BUF39I:1; /* Buffer MB Interrupt 39 Bit */
17275 uint32_t BUF38I:1; /* Buffer MB Interrupt 38 Bit */
17276 uint32_t BUF37I:1; /* Buffer MB Interrupt 37 Bit */
17277 uint32_t BUF36I:1; /* Buffer MB Interrupt 36 Bit */
17278 uint32_t BUF35I:1; /* Buffer MB Interrupt 35 Bit */
17279 uint32_t BUF34I:1; /* Buffer MB Interrupt 34 Bit */
17280 uint32_t BUF33I:1; /* Buffer MB Interrupt 33 Bit */
17281 uint32_t BUF32I:1; /* Buffer MB Interrupt 32 Bit */
17282 } B;
17283 } FLEXCAN_IFLAG2_32B_tag;
17284
17285 typedef union { /* IFLAG1 - Interrupt Flags 1 Register */
17286 uint32_t R;
17287 struct {
17288 uint32_t BUF31I:1; /* Buffer MB Interrupt 31 Bit */
17289 uint32_t BUF30I:1; /* Buffer MB Interrupt 30 Bit */
17290 uint32_t BUF29I:1; /* Buffer MB Interrupt 29 Bit */
17291 uint32_t BUF28I:1; /* Buffer MB Interrupt 28 Bit */
17292 uint32_t BUF27I:1; /* Buffer MB Interrupt 27 Bit */
17293 uint32_t BUF26I:1; /* Buffer MB Interrupt 26 Bit */
17294 uint32_t BUF25I:1; /* Buffer MB Interrupt 25 Bit */
17295 uint32_t BUF24I:1; /* Buffer MB Interrupt 24 Bit */
17296 uint32_t BUF23I:1; /* Buffer MB Interrupt 23 Bit */
17297 uint32_t BUF22I:1; /* Buffer MB Interrupt 22 Bit */
17298 uint32_t BUF21I:1; /* Buffer MB Interrupt 21 Bit */
17299 uint32_t BUF20I:1; /* Buffer MB Interrupt 20 Bit */
17300 uint32_t BUF19I:1; /* Buffer MB Interrupt 19 Bit */
17301 uint32_t BUF18I:1; /* Buffer MB Interrupt 18 Bit */
17302 uint32_t BUF17I:1; /* Buffer MB Interrupt 17 Bit */
17303 uint32_t BUF16I:1; /* Buffer MB Interrupt 16 Bit */
17304 uint32_t BUF15I:1; /* Buffer MB Interrupt 15 Bit */
17305 uint32_t BUF14I:1; /* Buffer MB Interrupt 14 Bit */
17306 uint32_t BUF13I:1; /* Buffer MB Interrupt 13 Bit */
17307 uint32_t BUF12I:1; /* Buffer MB Interrupt 12 Bit */
17308 uint32_t BUF11I:1; /* Buffer MB Interrupt 11 Bit */
17309 uint32_t BUF10I:1; /* Buffer MB Interrupt 10 Bit */
17310#ifndef USE_FIELD_ALIASES_FLEXCAN
17311 uint32_t BUF9I:1; /* Buffer MB Interrupt 9 Bit */
17312#else
17313 uint32_t BUF09I:1; /* deprecated name - please avoid */
17314#endif
17315#ifndef USE_FIELD_ALIASES_FLEXCAN
17316 uint32_t BUF8I:1; /* Buffer MB Interrupt 8 Bit */
17317#else
17318 uint32_t BUF08I:1; /* deprecated name - please avoid */
17319#endif
17320#ifndef USE_FIELD_ALIASES_FLEXCAN
17321 uint32_t BUF7I:1; /* Buffer MB Interrupt 7 Bit */
17322#else
17323 uint32_t BUF07I:1; /* deprecated name - please avoid */
17324#endif
17325#ifndef USE_FIELD_ALIASES_FLEXCAN
17326 uint32_t BUF6I:1; /* Buffer MB Interrupt 6 Bit */
17327#else
17328 uint32_t BUF06I:1; /* deprecated name - please avoid */
17329#endif
17330#ifndef USE_FIELD_ALIASES_FLEXCAN
17331 uint32_t BUF5I:1; /* Buffer MB Interrupt 5 Bit */
17332#else
17333 uint32_t BUF05I:1; /* deprecated name - please avoid */
17334#endif
17335#ifndef USE_FIELD_ALIASES_FLEXCAN
17336 uint32_t BUF4I:1; /* Buffer MB Interrupt 4 Bit */
17337#else
17338 uint32_t BUF04I:1; /* deprecated name - please avoid */
17339#endif
17340#ifndef USE_FIELD_ALIASES_FLEXCAN
17341 uint32_t BUF3I:1; /* Buffer MB Interrupt 3 Bit */
17342#else
17343 uint32_t BUF03I:1; /* deprecated name - please avoid */
17344#endif
17345#ifndef USE_FIELD_ALIASES_FLEXCAN
17346 uint32_t BUF2I:1; /* Buffer MB Interrupt 2 Bit */
17347#else
17348 uint32_t BUF02I:1; /* deprecated name - please avoid */
17349#endif
17350#ifndef USE_FIELD_ALIASES_FLEXCAN
17351 uint32_t BUF1I:1; /* Buffer MB Interrupt 1 Bit */
17352#else
17353 uint32_t BUF01I:1; /* deprecated name - please avoid */
17354#endif
17355#ifndef USE_FIELD_ALIASES_FLEXCAN
17356 uint32_t BUF0I:1; /* Buffer MB Interrupt 0 Bit */
17357#else
17358 uint32_t BUF00I:1; /* deprecated name - please avoid */
17359#endif
17360 } B;
17361 } FLEXCAN_IFLAG1_32B_tag;
17362
17363
17364 /* Register layout for all registers MSG_CS... */
17365
17366 typedef union { /* Message Buffer Control and Status */
17367 uint32_t R;
17368 struct {
17369 uint32_t:4;
17370 uint32_t CODE:4; /* Message Buffer Code */
17371 uint32_t:1;
17372 uint32_t SRR:1; /* Substitute Remote Request */
17373 uint32_t IDE:1; /* ID Extended Bit */
17374 uint32_t RTR:1; /* Remote Transmission Request */
17375 uint32_t LENGTH:4; /* Length of Data in Bytes */
17376 uint32_t TIMESTAMP:16; /* Free-Running Counter Time Stamp */
17377 } B;
17378 } FLEXCAN_MSG_CS_32B_tag;
17379
17380
17381 /* Register layout for all registers MSG_ID... */
17382
17383 typedef union { /* Message Buffer Identifier Field */
17384 uint32_t R;
17385 struct {
17386 uint32_t PRIO:3; /* Local Priority */
17387 uint32_t STD_ID:11;
17388 uint32_t EXT_ID:18;
17389 } B;
17390 } FLEXCAN_MSG_ID_32B_tag;
17391
17392
17393 /* Register layout for all registers MSG_BYTE0_3... */
17394
17395 typedef union { /* Message Buffer Data Register */
17396 uint32_t R;
17397 uint8_t BYTE[4]; /* individual bytes can be accessed */
17398 uint32_t WORD; /* individual words can be accessed */
17399 } FLEXCAN_MSG_DATA_32B_tag;
17400
17401 typedef union {
17402 uint8_t B[8]; /* Data buffer in Bytes (8 bits) */
17403 uint16_t H[4]; /* Data buffer in Half-words (16 bits) */
17404 uint32_t W[2]; /* Data buffer in words (32 bits) */
17405 uint32_t R[2]; /* Data buffer in words (32 bits) */
17406 } FLEXCAN_MSG_DATA2_32B_tag;
17407
17408 /* Register layout for all registers MSG_BYTE4_7 matches xxx */
17409
17410
17411 /* Register layout for all registers RXIMR... */
17412
17413 typedef union { /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */
17414 uint32_t R;
17415 } FLEXCAN_RXIMR_32B_tag;
17416
17417
17418 typedef struct FLEXCAN_MB_struct_tag {
17419
17420 union {
17421 /* Message Buffer Control and Status */
17422 FLEXCAN_MSG_CS_32B_tag MSG_CS; /* relative offset: 0x0000 */
17423 FLEXCAN_MSG_CS_32B_tag CS; /* deprecated - please avoid */
17424 };
17425 union {
17426 /* Message Buffer Identifier Field */
17427 FLEXCAN_MSG_ID_32B_tag MSG_ID; /* relative offset: 0x0004 */
17428 FLEXCAN_MSG_ID_32B_tag ID; /* deprecated - please avoid */
17429 };
17430 union { /* Message Buffer Data Register */
17431
17432 struct {
17433 FLEXCAN_MSG_DATA_32B_tag MSG_BYTE0_3; /* relative offset: 0x0008 */
17434 /* Message Buffer Data Register */
17435 FLEXCAN_MSG_DATA_32B_tag MSG_BYTE4_7; /* relative offset: 0x000C */
17436 };
17437
17438 FLEXCAN_MSG_DATA2_32B_tag DATA; /* relative offset: 0x000C */
17439
17440 };
17441
17442 } FLEXCAN_MB_tag;
17443
17444
17445 typedef struct FLEXCAN_struct_tag { /* start of FLEXCAN_tag */
17446 /* MCR - Module Configuration Register */
17447 FLEXCAN_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */
17448 union {
17449 /* CTRL - Control Register */
17450 FLEXCAN_CTRL_32B_tag CTRL; /* offset: 0x0004 size: 32 bit */
17451
17452 FLEXCAN_CTRL_32B_tag CR; /* deprecated - please avoid */
17453
17454 };
17455 /* TIMER - Free Running Timer */
17456 FLEXCAN_TIMER_32B_tag TIMER; /* offset: 0x0008 size: 32 bit */
17457 int8_t FLEXCAN_reserved_000C[4];
17458 /* RXGMASK - Rx Global Mask Register */
17459 FLEXCAN_RXGMASK_32B_tag RXGMASK; /* offset: 0x0010 size: 32 bit */
17460 /* RX14MASK - Rx 14 Mask Register */
17461 FLEXCAN_RX14MASK_32B_tag RX14MASK; /* offset: 0x0014 size: 32 bit */
17462 /* RX15MASK - Rx 15 Mask Register */
17463 FLEXCAN_RX15MASK_32B_tag RX15MASK; /* offset: 0x0018 size: 32 bit */
17464 /* ECR - Error Counter Register */
17465 FLEXCAN_ECR_32B_tag ECR; /* offset: 0x001C size: 32 bit */
17466 /* ESR - Error and Status Register */
17467 FLEXCAN_ESR_32B_tag ESR; /* offset: 0x0020 size: 32 bit */
17468 union {
17469 FLEXCAN_IMASK2_32B_tag IMRH; /* deprecated - please avoid */
17470
17471 /* IMASK2 - Interrupt Masks 2 Register */
17472 FLEXCAN_IMASK2_32B_tag IMASK2; /* offset: 0x0024 size: 32 bit */
17473
17474 };
17475 union {
17476 FLEXCAN_IMASK1_32B_tag IMRL; /* deprecated - please avoid */
17477
17478 /* IMASK1 - Interrupt Masks 1 Register */
17479 FLEXCAN_IMASK1_32B_tag IMASK1; /* offset: 0x0028 size: 32 bit */
17480
17481 };
17482 union {
17483 FLEXCAN_IFLAG2_32B_tag IFRH; /* deprecated - please avoid */
17484
17485 /* IFLAG2 - Interrupt Flags 2 Register */
17486 FLEXCAN_IFLAG2_32B_tag IFLAG2; /* offset: 0x002C size: 32 bit */
17487
17488 };
17489 union {
17490 FLEXCAN_IFLAG1_32B_tag IFRL; /* deprecated - please avoid */
17491
17492 /* IFLAG1 - Interrupt Flags 1 Register */
17493 FLEXCAN_IFLAG1_32B_tag IFLAG1; /* offset: 0x0030 size: 32 bit */
17494
17495 };
17496 int8_t FLEXCAN_reserved_0034_C[76];
17497 union {
17498 /* Register set MB */
17499 FLEXCAN_MB_tag MB[64]; /* offset: 0x0080 (0x0010 x 64) */
17500
17501 /* Alias name for MB */
17502 FLEXCAN_MB_tag BUF[64]; /* deprecated - please avoid */
17503
17504 struct {
17505 /* Message Buffer Control and Status */
17506 FLEXCAN_MSG_CS_32B_tag MSG0_CS; /* offset: 0x0080 size: 32 bit */
17507 /* Message Buffer Identifier Field */
17508 FLEXCAN_MSG_ID_32B_tag MSG0_ID; /* offset: 0x0084 size: 32 bit */
17509 /* Message Buffer Data Register */
17510 FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE0_3; /* offset: 0x0088 size: 32 bit */
17511 /* Message Buffer Data Register */
17512 FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE4_7; /* offset: 0x008C size: 32 bit */
17513 /* Message Buffer Control and Status */
17514 FLEXCAN_MSG_CS_32B_tag MSG1_CS; /* offset: 0x0090 size: 32 bit */
17515 /* Message Buffer Identifier Field */
17516 FLEXCAN_MSG_ID_32B_tag MSG1_ID; /* offset: 0x0094 size: 32 bit */
17517 /* Message Buffer Data Register */
17518 FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE0_3; /* offset: 0x0098 size: 32 bit */
17519 /* Message Buffer Data Register */
17520 FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE4_7; /* offset: 0x009C size: 32 bit */
17521 /* Message Buffer Control and Status */
17522 FLEXCAN_MSG_CS_32B_tag MSG2_CS; /* offset: 0x00A0 size: 32 bit */
17523 /* Message Buffer Identifier Field */
17524 FLEXCAN_MSG_ID_32B_tag MSG2_ID; /* offset: 0x00A4 size: 32 bit */
17525 /* Message Buffer Data Register */
17526 FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE0_3; /* offset: 0x00A8 size: 32 bit */
17527 /* Message Buffer Data Register */
17528 FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE4_7; /* offset: 0x00AC size: 32 bit */
17529 /* Message Buffer Control and Status */
17530 FLEXCAN_MSG_CS_32B_tag MSG3_CS; /* offset: 0x00B0 size: 32 bit */
17531 /* Message Buffer Identifier Field */
17532 FLEXCAN_MSG_ID_32B_tag MSG3_ID; /* offset: 0x00B4 size: 32 bit */
17533 /* Message Buffer Data Register */
17534 FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE0_3; /* offset: 0x00B8 size: 32 bit */
17535 /* Message Buffer Data Register */
17536 FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE4_7; /* offset: 0x00BC size: 32 bit */
17537 /* Message Buffer Control and Status */
17538 FLEXCAN_MSG_CS_32B_tag MSG4_CS; /* offset: 0x00C0 size: 32 bit */
17539 /* Message Buffer Identifier Field */
17540 FLEXCAN_MSG_ID_32B_tag MSG4_ID; /* offset: 0x00C4 size: 32 bit */
17541 /* Message Buffer Data Register */
17542 FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE0_3; /* offset: 0x00C8 size: 32 bit */
17543 /* Message Buffer Data Register */
17544 FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE4_7; /* offset: 0x00CC size: 32 bit */
17545 /* Message Buffer Control and Status */
17546 FLEXCAN_MSG_CS_32B_tag MSG5_CS; /* offset: 0x00D0 size: 32 bit */
17547 /* Message Buffer Identifier Field */
17548 FLEXCAN_MSG_ID_32B_tag MSG5_ID; /* offset: 0x00D4 size: 32 bit */
17549 /* Message Buffer Data Register */
17550 FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE0_3; /* offset: 0x00D8 size: 32 bit */
17551 /* Message Buffer Data Register */
17552 FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE4_7; /* offset: 0x00DC size: 32 bit */
17553 /* Message Buffer Control and Status */
17554 FLEXCAN_MSG_CS_32B_tag MSG6_CS; /* offset: 0x00E0 size: 32 bit */
17555 /* Message Buffer Identifier Field */
17556 FLEXCAN_MSG_ID_32B_tag MSG6_ID; /* offset: 0x00E4 size: 32 bit */
17557 /* Message Buffer Data Register */
17558 FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE0_3; /* offset: 0x00E8 size: 32 bit */
17559 /* Message Buffer Data Register */
17560 FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE4_7; /* offset: 0x00EC size: 32 bit */
17561 /* Message Buffer Control and Status */
17562 FLEXCAN_MSG_CS_32B_tag MSG7_CS; /* offset: 0x00F0 size: 32 bit */
17563 /* Message Buffer Identifier Field */
17564 FLEXCAN_MSG_ID_32B_tag MSG7_ID; /* offset: 0x00F4 size: 32 bit */
17565 /* Message Buffer Data Register */
17566 FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE0_3; /* offset: 0x00F8 size: 32 bit */
17567 /* Message Buffer Data Register */
17568 FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE4_7; /* offset: 0x00FC size: 32 bit */
17569 /* Message Buffer Control and Status */
17570 FLEXCAN_MSG_CS_32B_tag MSG8_CS; /* offset: 0x0100 size: 32 bit */
17571 /* Message Buffer Identifier Field */
17572 FLEXCAN_MSG_ID_32B_tag MSG8_ID; /* offset: 0x0104 size: 32 bit */
17573 /* Message Buffer Data Register */
17574 FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE0_3; /* offset: 0x0108 size: 32 bit */
17575 /* Message Buffer Data Register */
17576 FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE4_7; /* offset: 0x010C size: 32 bit */
17577 /* Message Buffer Control and Status */
17578 FLEXCAN_MSG_CS_32B_tag MSG9_CS; /* offset: 0x0110 size: 32 bit */
17579 /* Message Buffer Identifier Field */
17580 FLEXCAN_MSG_ID_32B_tag MSG9_ID; /* offset: 0x0114 size: 32 bit */
17581 /* Message Buffer Data Register */
17582 FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE0_3; /* offset: 0x0118 size: 32 bit */
17583 /* Message Buffer Data Register */
17584 FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE4_7; /* offset: 0x011C size: 32 bit */
17585 /* Message Buffer Control and Status */
17586 FLEXCAN_MSG_CS_32B_tag MSG10_CS; /* offset: 0x0120 size: 32 bit */
17587 /* Message Buffer Identifier Field */
17588 FLEXCAN_MSG_ID_32B_tag MSG10_ID; /* offset: 0x0124 size: 32 bit */
17589 /* Message Buffer Data Register */
17590 FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE0_3; /* offset: 0x0128 size: 32 bit */
17591 /* Message Buffer Data Register */
17592 FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE4_7; /* offset: 0x012C size: 32 bit */
17593 /* Message Buffer Control and Status */
17594 FLEXCAN_MSG_CS_32B_tag MSG11_CS; /* offset: 0x0130 size: 32 bit */
17595 /* Message Buffer Identifier Field */
17596 FLEXCAN_MSG_ID_32B_tag MSG11_ID; /* offset: 0x0134 size: 32 bit */
17597 /* Message Buffer Data Register */
17598 FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE0_3; /* offset: 0x0138 size: 32 bit */
17599 /* Message Buffer Data Register */
17600 FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE4_7; /* offset: 0x013C size: 32 bit */
17601 /* Message Buffer Control and Status */
17602 FLEXCAN_MSG_CS_32B_tag MSG12_CS; /* offset: 0x0140 size: 32 bit */
17603 /* Message Buffer Identifier Field */
17604 FLEXCAN_MSG_ID_32B_tag MSG12_ID; /* offset: 0x0144 size: 32 bit */
17605 /* Message Buffer Data Register */
17606 FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE0_3; /* offset: 0x0148 size: 32 bit */
17607 /* Message Buffer Data Register */
17608 FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE4_7; /* offset: 0x014C size: 32 bit */
17609 /* Message Buffer Control and Status */
17610 FLEXCAN_MSG_CS_32B_tag MSG13_CS; /* offset: 0x0150 size: 32 bit */
17611 /* Message Buffer Identifier Field */
17612 FLEXCAN_MSG_ID_32B_tag MSG13_ID; /* offset: 0x0154 size: 32 bit */
17613 /* Message Buffer Data Register */
17614 FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE0_3; /* offset: 0x0158 size: 32 bit */
17615 /* Message Buffer Data Register */
17616 FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE4_7; /* offset: 0x015C size: 32 bit */
17617 /* Message Buffer Control and Status */
17618 FLEXCAN_MSG_CS_32B_tag MSG14_CS; /* offset: 0x0160 size: 32 bit */
17619 /* Message Buffer Identifier Field */
17620 FLEXCAN_MSG_ID_32B_tag MSG14_ID; /* offset: 0x0164 size: 32 bit */
17621 /* Message Buffer Data Register */
17622 FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE0_3; /* offset: 0x0168 size: 32 bit */
17623 /* Message Buffer Data Register */
17624 FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE4_7; /* offset: 0x016C size: 32 bit */
17625 /* Message Buffer Control and Status */
17626 FLEXCAN_MSG_CS_32B_tag MSG15_CS; /* offset: 0x0170 size: 32 bit */
17627 /* Message Buffer Identifier Field */
17628 FLEXCAN_MSG_ID_32B_tag MSG15_ID; /* offset: 0x0174 size: 32 bit */
17629 /* Message Buffer Data Register */
17630 FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE0_3; /* offset: 0x0178 size: 32 bit */
17631 /* Message Buffer Data Register */
17632 FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE4_7; /* offset: 0x017C size: 32 bit */
17633 /* Message Buffer Control and Status */
17634 FLEXCAN_MSG_CS_32B_tag MSG16_CS; /* offset: 0x0180 size: 32 bit */
17635 /* Message Buffer Identifier Field */
17636 FLEXCAN_MSG_ID_32B_tag MSG16_ID; /* offset: 0x0184 size: 32 bit */
17637 /* Message Buffer Data Register */
17638 FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE0_3; /* offset: 0x0188 size: 32 bit */
17639 /* Message Buffer Data Register */
17640 FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE4_7; /* offset: 0x018C size: 32 bit */
17641 /* Message Buffer Control and Status */
17642 FLEXCAN_MSG_CS_32B_tag MSG17_CS; /* offset: 0x0190 size: 32 bit */
17643 /* Message Buffer Identifier Field */
17644 FLEXCAN_MSG_ID_32B_tag MSG17_ID; /* offset: 0x0194 size: 32 bit */
17645 /* Message Buffer Data Register */
17646 FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE0_3; /* offset: 0x0198 size: 32 bit */
17647 /* Message Buffer Data Register */
17648 FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE4_7; /* offset: 0x019C size: 32 bit */
17649 /* Message Buffer Control and Status */
17650 FLEXCAN_MSG_CS_32B_tag MSG18_CS; /* offset: 0x01A0 size: 32 bit */
17651 /* Message Buffer Identifier Field */
17652 FLEXCAN_MSG_ID_32B_tag MSG18_ID; /* offset: 0x01A4 size: 32 bit */
17653 /* Message Buffer Data Register */
17654 FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE0_3; /* offset: 0x01A8 size: 32 bit */
17655 /* Message Buffer Data Register */
17656 FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE4_7; /* offset: 0x01AC size: 32 bit */
17657 /* Message Buffer Control and Status */
17658 FLEXCAN_MSG_CS_32B_tag MSG19_CS; /* offset: 0x01B0 size: 32 bit */
17659 /* Message Buffer Identifier Field */
17660 FLEXCAN_MSG_ID_32B_tag MSG19_ID; /* offset: 0x01B4 size: 32 bit */
17661 /* Message Buffer Data Register */
17662 FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE0_3; /* offset: 0x01B8 size: 32 bit */
17663 /* Message Buffer Data Register */
17664 FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE4_7; /* offset: 0x01BC size: 32 bit */
17665 /* Message Buffer Control and Status */
17666 FLEXCAN_MSG_CS_32B_tag MSG20_CS; /* offset: 0x01C0 size: 32 bit */
17667 /* Message Buffer Identifier Field */
17668 FLEXCAN_MSG_ID_32B_tag MSG20_ID; /* offset: 0x01C4 size: 32 bit */
17669 /* Message Buffer Data Register */
17670 FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE0_3; /* offset: 0x01C8 size: 32 bit */
17671 /* Message Buffer Data Register */
17672 FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE4_7; /* offset: 0x01CC size: 32 bit */
17673 /* Message Buffer Control and Status */
17674 FLEXCAN_MSG_CS_32B_tag MSG21_CS; /* offset: 0x01D0 size: 32 bit */
17675 /* Message Buffer Identifier Field */
17676 FLEXCAN_MSG_ID_32B_tag MSG21_ID; /* offset: 0x01D4 size: 32 bit */
17677 /* Message Buffer Data Register */
17678 FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE0_3; /* offset: 0x01D8 size: 32 bit */
17679 /* Message Buffer Data Register */
17680 FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE4_7; /* offset: 0x01DC size: 32 bit */
17681 /* Message Buffer Control and Status */
17682 FLEXCAN_MSG_CS_32B_tag MSG22_CS; /* offset: 0x01E0 size: 32 bit */
17683 /* Message Buffer Identifier Field */
17684 FLEXCAN_MSG_ID_32B_tag MSG22_ID; /* offset: 0x01E4 size: 32 bit */
17685 /* Message Buffer Data Register */
17686 FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE0_3; /* offset: 0x01E8 size: 32 bit */
17687 /* Message Buffer Data Register */
17688 FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE4_7; /* offset: 0x01EC size: 32 bit */
17689 /* Message Buffer Control and Status */
17690 FLEXCAN_MSG_CS_32B_tag MSG23_CS; /* offset: 0x01F0 size: 32 bit */
17691 /* Message Buffer Identifier Field */
17692 FLEXCAN_MSG_ID_32B_tag MSG23_ID; /* offset: 0x01F4 size: 32 bit */
17693 /* Message Buffer Data Register */
17694 FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE0_3; /* offset: 0x01F8 size: 32 bit */
17695 /* Message Buffer Data Register */
17696 FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE4_7; /* offset: 0x01FC size: 32 bit */
17697 /* Message Buffer Control and Status */
17698 FLEXCAN_MSG_CS_32B_tag MSG24_CS; /* offset: 0x0200 size: 32 bit */
17699 /* Message Buffer Identifier Field */
17700 FLEXCAN_MSG_ID_32B_tag MSG24_ID; /* offset: 0x0204 size: 32 bit */
17701 /* Message Buffer Data Register */
17702 FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE0_3; /* offset: 0x0208 size: 32 bit */
17703 /* Message Buffer Data Register */
17704 FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE4_7; /* offset: 0x020C size: 32 bit */
17705 /* Message Buffer Control and Status */
17706 FLEXCAN_MSG_CS_32B_tag MSG25_CS; /* offset: 0x0210 size: 32 bit */
17707 /* Message Buffer Identifier Field */
17708 FLEXCAN_MSG_ID_32B_tag MSG25_ID; /* offset: 0x0214 size: 32 bit */
17709 /* Message Buffer Data Register */
17710 FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE0_3; /* offset: 0x0218 size: 32 bit */
17711 /* Message Buffer Data Register */
17712 FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE4_7; /* offset: 0x021C size: 32 bit */
17713 /* Message Buffer Control and Status */
17714 FLEXCAN_MSG_CS_32B_tag MSG26_CS; /* offset: 0x0220 size: 32 bit */
17715 /* Message Buffer Identifier Field */
17716 FLEXCAN_MSG_ID_32B_tag MSG26_ID; /* offset: 0x0224 size: 32 bit */
17717 /* Message Buffer Data Register */
17718 FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE0_3; /* offset: 0x0228 size: 32 bit */
17719 /* Message Buffer Data Register */
17720 FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE4_7; /* offset: 0x022C size: 32 bit */
17721 /* Message Buffer Control and Status */
17722 FLEXCAN_MSG_CS_32B_tag MSG27_CS; /* offset: 0x0230 size: 32 bit */
17723 /* Message Buffer Identifier Field */
17724 FLEXCAN_MSG_ID_32B_tag MSG27_ID; /* offset: 0x0234 size: 32 bit */
17725 /* Message Buffer Data Register */
17726 FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE0_3; /* offset: 0x0238 size: 32 bit */
17727 /* Message Buffer Data Register */
17728 FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE4_7; /* offset: 0x023C size: 32 bit */
17729 /* Message Buffer Control and Status */
17730 FLEXCAN_MSG_CS_32B_tag MSG28_CS; /* offset: 0x0240 size: 32 bit */
17731 /* Message Buffer Identifier Field */
17732 FLEXCAN_MSG_ID_32B_tag MSG28_ID; /* offset: 0x0244 size: 32 bit */
17733 /* Message Buffer Data Register */
17734 FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE0_3; /* offset: 0x0248 size: 32 bit */
17735 /* Message Buffer Data Register */
17736 FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE4_7; /* offset: 0x024C size: 32 bit */
17737 /* Message Buffer Control and Status */
17738 FLEXCAN_MSG_CS_32B_tag MSG29_CS; /* offset: 0x0250 size: 32 bit */
17739 /* Message Buffer Identifier Field */
17740 FLEXCAN_MSG_ID_32B_tag MSG29_ID; /* offset: 0x0254 size: 32 bit */
17741 /* Message Buffer Data Register */
17742 FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE0_3; /* offset: 0x0258 size: 32 bit */
17743 /* Message Buffer Data Register */
17744 FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE4_7; /* offset: 0x025C size: 32 bit */
17745 /* Message Buffer Control and Status */
17746 FLEXCAN_MSG_CS_32B_tag MSG30_CS; /* offset: 0x0260 size: 32 bit */
17747 /* Message Buffer Identifier Field */
17748 FLEXCAN_MSG_ID_32B_tag MSG30_ID; /* offset: 0x0264 size: 32 bit */
17749 /* Message Buffer Data Register */
17750 FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE0_3; /* offset: 0x0268 size: 32 bit */
17751 /* Message Buffer Data Register */
17752 FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE4_7; /* offset: 0x026C size: 32 bit */
17753 /* Message Buffer Control and Status */
17754 FLEXCAN_MSG_CS_32B_tag MSG31_CS; /* offset: 0x0270 size: 32 bit */
17755 /* Message Buffer Identifier Field */
17756 FLEXCAN_MSG_ID_32B_tag MSG31_ID; /* offset: 0x0274 size: 32 bit */
17757 /* Message Buffer Data Register */
17758 FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE0_3; /* offset: 0x0278 size: 32 bit */
17759 /* Message Buffer Data Register */
17760 FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE4_7; /* offset: 0x027C size: 32 bit */
17761 /* Message Buffer Control and Status */
17762 FLEXCAN_MSG_CS_32B_tag MSG32_CS; /* offset: 0x0280 size: 32 bit */
17763 /* Message Buffer Identifier Field */
17764 FLEXCAN_MSG_ID_32B_tag MSG32_ID; /* offset: 0x0284 size: 32 bit */
17765 /* Message Buffer Data Register */
17766 FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE0_3; /* offset: 0x0288 size: 32 bit */
17767 /* Message Buffer Data Register */
17768 FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE4_7; /* offset: 0x028C size: 32 bit */
17769 /* Message Buffer Control and Status */
17770 FLEXCAN_MSG_CS_32B_tag MSG33_CS; /* offset: 0x0290 size: 32 bit */
17771 /* Message Buffer Identifier Field */
17772 FLEXCAN_MSG_ID_32B_tag MSG33_ID; /* offset: 0x0294 size: 32 bit */
17773 /* Message Buffer Data Register */
17774 FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE0_3; /* offset: 0x0298 size: 32 bit */
17775 /* Message Buffer Data Register */
17776 FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE4_7; /* offset: 0x029C size: 32 bit */
17777 /* Message Buffer Control and Status */
17778 FLEXCAN_MSG_CS_32B_tag MSG34_CS; /* offset: 0x02A0 size: 32 bit */
17779 /* Message Buffer Identifier Field */
17780 FLEXCAN_MSG_ID_32B_tag MSG34_ID; /* offset: 0x02A4 size: 32 bit */
17781 /* Message Buffer Data Register */
17782 FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE0_3; /* offset: 0x02A8 size: 32 bit */
17783 /* Message Buffer Data Register */
17784 FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE4_7; /* offset: 0x02AC size: 32 bit */
17785 /* Message Buffer Control and Status */
17786 FLEXCAN_MSG_CS_32B_tag MSG35_CS; /* offset: 0x02B0 size: 32 bit */
17787 /* Message Buffer Identifier Field */
17788 FLEXCAN_MSG_ID_32B_tag MSG35_ID; /* offset: 0x02B4 size: 32 bit */
17789 /* Message Buffer Data Register */
17790 FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE0_3; /* offset: 0x02B8 size: 32 bit */
17791 /* Message Buffer Data Register */
17792 FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE4_7; /* offset: 0x02BC size: 32 bit */
17793 /* Message Buffer Control and Status */
17794 FLEXCAN_MSG_CS_32B_tag MSG36_CS; /* offset: 0x02C0 size: 32 bit */
17795 /* Message Buffer Identifier Field */
17796 FLEXCAN_MSG_ID_32B_tag MSG36_ID; /* offset: 0x02C4 size: 32 bit */
17797 /* Message Buffer Data Register */
17798 FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE0_3; /* offset: 0x02C8 size: 32 bit */
17799 /* Message Buffer Data Register */
17800 FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE4_7; /* offset: 0x02CC size: 32 bit */
17801 /* Message Buffer Control and Status */
17802 FLEXCAN_MSG_CS_32B_tag MSG37_CS; /* offset: 0x02D0 size: 32 bit */
17803 /* Message Buffer Identifier Field */
17804 FLEXCAN_MSG_ID_32B_tag MSG37_ID; /* offset: 0x02D4 size: 32 bit */
17805 /* Message Buffer Data Register */
17806 FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE0_3; /* offset: 0x02D8 size: 32 bit */
17807 /* Message Buffer Data Register */
17808 FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE4_7; /* offset: 0x02DC size: 32 bit */
17809 /* Message Buffer Control and Status */
17810 FLEXCAN_MSG_CS_32B_tag MSG38_CS; /* offset: 0x02E0 size: 32 bit */
17811 /* Message Buffer Identifier Field */
17812 FLEXCAN_MSG_ID_32B_tag MSG38_ID; /* offset: 0x02E4 size: 32 bit */
17813 /* Message Buffer Data Register */
17814 FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE0_3; /* offset: 0x02E8 size: 32 bit */
17815 /* Message Buffer Data Register */
17816 FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE4_7; /* offset: 0x02EC size: 32 bit */
17817 /* Message Buffer Control and Status */
17818 FLEXCAN_MSG_CS_32B_tag MSG39_CS; /* offset: 0x02F0 size: 32 bit */
17819 /* Message Buffer Identifier Field */
17820 FLEXCAN_MSG_ID_32B_tag MSG39_ID; /* offset: 0x02F4 size: 32 bit */
17821 /* Message Buffer Data Register */
17822 FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE0_3; /* offset: 0x02F8 size: 32 bit */
17823 /* Message Buffer Data Register */
17824 FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE4_7; /* offset: 0x02FC size: 32 bit */
17825 /* Message Buffer Control and Status */
17826 FLEXCAN_MSG_CS_32B_tag MSG40_CS; /* offset: 0x0300 size: 32 bit */
17827 /* Message Buffer Identifier Field */
17828 FLEXCAN_MSG_ID_32B_tag MSG40_ID; /* offset: 0x0304 size: 32 bit */
17829 /* Message Buffer Data Register */
17830 FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE0_3; /* offset: 0x0308 size: 32 bit */
17831 /* Message Buffer Data Register */
17832 FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE4_7; /* offset: 0x030C size: 32 bit */
17833 /* Message Buffer Control and Status */
17834 FLEXCAN_MSG_CS_32B_tag MSG41_CS; /* offset: 0x0310 size: 32 bit */
17835 /* Message Buffer Identifier Field */
17836 FLEXCAN_MSG_ID_32B_tag MSG41_ID; /* offset: 0x0314 size: 32 bit */
17837 /* Message Buffer Data Register */
17838 FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE0_3; /* offset: 0x0318 size: 32 bit */
17839 /* Message Buffer Data Register */
17840 FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE4_7; /* offset: 0x031C size: 32 bit */
17841 /* Message Buffer Control and Status */
17842 FLEXCAN_MSG_CS_32B_tag MSG42_CS; /* offset: 0x0320 size: 32 bit */
17843 /* Message Buffer Identifier Field */
17844 FLEXCAN_MSG_ID_32B_tag MSG42_ID; /* offset: 0x0324 size: 32 bit */
17845 /* Message Buffer Data Register */
17846 FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE0_3; /* offset: 0x0328 size: 32 bit */
17847 /* Message Buffer Data Register */
17848 FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE4_7; /* offset: 0x032C size: 32 bit */
17849 /* Message Buffer Control and Status */
17850 FLEXCAN_MSG_CS_32B_tag MSG43_CS; /* offset: 0x0330 size: 32 bit */
17851 /* Message Buffer Identifier Field */
17852 FLEXCAN_MSG_ID_32B_tag MSG43_ID; /* offset: 0x0334 size: 32 bit */
17853 /* Message Buffer Data Register */
17854 FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE0_3; /* offset: 0x0338 size: 32 bit */
17855 /* Message Buffer Data Register */
17856 FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE4_7; /* offset: 0x033C size: 32 bit */
17857 /* Message Buffer Control and Status */
17858 FLEXCAN_MSG_CS_32B_tag MSG44_CS; /* offset: 0x0340 size: 32 bit */
17859 /* Message Buffer Identifier Field */
17860 FLEXCAN_MSG_ID_32B_tag MSG44_ID; /* offset: 0x0344 size: 32 bit */
17861 /* Message Buffer Data Register */
17862 FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE0_3; /* offset: 0x0348 size: 32 bit */
17863 /* Message Buffer Data Register */
17864 FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE4_7; /* offset: 0x034C size: 32 bit */
17865 /* Message Buffer Control and Status */
17866 FLEXCAN_MSG_CS_32B_tag MSG45_CS; /* offset: 0x0350 size: 32 bit */
17867 /* Message Buffer Identifier Field */
17868 FLEXCAN_MSG_ID_32B_tag MSG45_ID; /* offset: 0x0354 size: 32 bit */
17869 /* Message Buffer Data Register */
17870 FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE0_3; /* offset: 0x0358 size: 32 bit */
17871 /* Message Buffer Data Register */
17872 FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE4_7; /* offset: 0x035C size: 32 bit */
17873 /* Message Buffer Control and Status */
17874 FLEXCAN_MSG_CS_32B_tag MSG46_CS; /* offset: 0x0360 size: 32 bit */
17875 /* Message Buffer Identifier Field */
17876 FLEXCAN_MSG_ID_32B_tag MSG46_ID; /* offset: 0x0364 size: 32 bit */
17877 /* Message Buffer Data Register */
17878 FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE0_3; /* offset: 0x0368 size: 32 bit */
17879 /* Message Buffer Data Register */
17880 FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE4_7; /* offset: 0x036C size: 32 bit */
17881 /* Message Buffer Control and Status */
17882 FLEXCAN_MSG_CS_32B_tag MSG47_CS; /* offset: 0x0370 size: 32 bit */
17883 /* Message Buffer Identifier Field */
17884 FLEXCAN_MSG_ID_32B_tag MSG47_ID; /* offset: 0x0374 size: 32 bit */
17885 /* Message Buffer Data Register */
17886 FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE0_3; /* offset: 0x0378 size: 32 bit */
17887 /* Message Buffer Data Register */
17888 FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE4_7; /* offset: 0x037C size: 32 bit */
17889 /* Message Buffer Control and Status */
17890 FLEXCAN_MSG_CS_32B_tag MSG48_CS; /* offset: 0x0380 size: 32 bit */
17891 /* Message Buffer Identifier Field */
17892 FLEXCAN_MSG_ID_32B_tag MSG48_ID; /* offset: 0x0384 size: 32 bit */
17893 /* Message Buffer Data Register */
17894 FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE0_3; /* offset: 0x0388 size: 32 bit */
17895 /* Message Buffer Data Register */
17896 FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE4_7; /* offset: 0x038C size: 32 bit */
17897 /* Message Buffer Control and Status */
17898 FLEXCAN_MSG_CS_32B_tag MSG49_CS; /* offset: 0x0390 size: 32 bit */
17899 /* Message Buffer Identifier Field */
17900 FLEXCAN_MSG_ID_32B_tag MSG49_ID; /* offset: 0x0394 size: 32 bit */
17901 /* Message Buffer Data Register */
17902 FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE0_3; /* offset: 0x0398 size: 32 bit */
17903 /* Message Buffer Data Register */
17904 FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE4_7; /* offset: 0x039C size: 32 bit */
17905 /* Message Buffer Control and Status */
17906 FLEXCAN_MSG_CS_32B_tag MSG50_CS; /* offset: 0x03A0 size: 32 bit */
17907 /* Message Buffer Identifier Field */
17908 FLEXCAN_MSG_ID_32B_tag MSG50_ID; /* offset: 0x03A4 size: 32 bit */
17909 /* Message Buffer Data Register */
17910 FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE0_3; /* offset: 0x03A8 size: 32 bit */
17911 /* Message Buffer Data Register */
17912 FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE4_7; /* offset: 0x03AC size: 32 bit */
17913 /* Message Buffer Control and Status */
17914 FLEXCAN_MSG_CS_32B_tag MSG51_CS; /* offset: 0x03B0 size: 32 bit */
17915 /* Message Buffer Identifier Field */
17916 FLEXCAN_MSG_ID_32B_tag MSG51_ID; /* offset: 0x03B4 size: 32 bit */
17917 /* Message Buffer Data Register */
17918 FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE0_3; /* offset: 0x03B8 size: 32 bit */
17919 /* Message Buffer Data Register */
17920 FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE4_7; /* offset: 0x03BC size: 32 bit */
17921 /* Message Buffer Control and Status */
17922 FLEXCAN_MSG_CS_32B_tag MSG52_CS; /* offset: 0x03C0 size: 32 bit */
17923 /* Message Buffer Identifier Field */
17924 FLEXCAN_MSG_ID_32B_tag MSG52_ID; /* offset: 0x03C4 size: 32 bit */
17925 /* Message Buffer Data Register */
17926 FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE0_3; /* offset: 0x03C8 size: 32 bit */
17927 /* Message Buffer Data Register */
17928 FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE4_7; /* offset: 0x03CC size: 32 bit */
17929 /* Message Buffer Control and Status */
17930 FLEXCAN_MSG_CS_32B_tag MSG53_CS; /* offset: 0x03D0 size: 32 bit */
17931 /* Message Buffer Identifier Field */
17932 FLEXCAN_MSG_ID_32B_tag MSG53_ID; /* offset: 0x03D4 size: 32 bit */
17933 /* Message Buffer Data Register */
17934 FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE0_3; /* offset: 0x03D8 size: 32 bit */
17935 /* Message Buffer Data Register */
17936 FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE4_7; /* offset: 0x03DC size: 32 bit */
17937 /* Message Buffer Control and Status */
17938 FLEXCAN_MSG_CS_32B_tag MSG54_CS; /* offset: 0x03E0 size: 32 bit */
17939 /* Message Buffer Identifier Field */
17940 FLEXCAN_MSG_ID_32B_tag MSG54_ID; /* offset: 0x03E4 size: 32 bit */
17941 /* Message Buffer Data Register */
17942 FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE0_3; /* offset: 0x03E8 size: 32 bit */
17943 /* Message Buffer Data Register */
17944 FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE4_7; /* offset: 0x03EC size: 32 bit */
17945 /* Message Buffer Control and Status */
17946 FLEXCAN_MSG_CS_32B_tag MSG55_CS; /* offset: 0x03F0 size: 32 bit */
17947 /* Message Buffer Identifier Field */
17948 FLEXCAN_MSG_ID_32B_tag MSG55_ID; /* offset: 0x03F4 size: 32 bit */
17949 /* Message Buffer Data Register */
17950 FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE0_3; /* offset: 0x03F8 size: 32 bit */
17951 /* Message Buffer Data Register */
17952 FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE4_7; /* offset: 0x03FC size: 32 bit */
17953 /* Message Buffer Control and Status */
17954 FLEXCAN_MSG_CS_32B_tag MSG56_CS; /* offset: 0x0400 size: 32 bit */
17955 /* Message Buffer Identifier Field */
17956 FLEXCAN_MSG_ID_32B_tag MSG56_ID; /* offset: 0x0404 size: 32 bit */
17957 /* Message Buffer Data Register */
17958 FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE0_3; /* offset: 0x0408 size: 32 bit */
17959 /* Message Buffer Data Register */
17960 FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE4_7; /* offset: 0x040C size: 32 bit */
17961 /* Message Buffer Control and Status */
17962 FLEXCAN_MSG_CS_32B_tag MSG57_CS; /* offset: 0x0410 size: 32 bit */
17963 /* Message Buffer Identifier Field */
17964 FLEXCAN_MSG_ID_32B_tag MSG57_ID; /* offset: 0x0414 size: 32 bit */
17965 /* Message Buffer Data Register */
17966 FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE0_3; /* offset: 0x0418 size: 32 bit */
17967 /* Message Buffer Data Register */
17968 FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE4_7; /* offset: 0x041C size: 32 bit */
17969 /* Message Buffer Control and Status */
17970 FLEXCAN_MSG_CS_32B_tag MSG58_CS; /* offset: 0x0420 size: 32 bit */
17971 /* Message Buffer Identifier Field */
17972 FLEXCAN_MSG_ID_32B_tag MSG58_ID; /* offset: 0x0424 size: 32 bit */
17973 /* Message Buffer Data Register */
17974 FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE0_3; /* offset: 0x0428 size: 32 bit */
17975 /* Message Buffer Data Register */
17976 FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE4_7; /* offset: 0x042C size: 32 bit */
17977 /* Message Buffer Control and Status */
17978 FLEXCAN_MSG_CS_32B_tag MSG59_CS; /* offset: 0x0430 size: 32 bit */
17979 /* Message Buffer Identifier Field */
17980 FLEXCAN_MSG_ID_32B_tag MSG59_ID; /* offset: 0x0434 size: 32 bit */
17981 /* Message Buffer Data Register */
17982 FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE0_3; /* offset: 0x0438 size: 32 bit */
17983 /* Message Buffer Data Register */
17984 FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE4_7; /* offset: 0x043C size: 32 bit */
17985 /* Message Buffer Control and Status */
17986 FLEXCAN_MSG_CS_32B_tag MSG60_CS; /* offset: 0x0440 size: 32 bit */
17987 /* Message Buffer Identifier Field */
17988 FLEXCAN_MSG_ID_32B_tag MSG60_ID; /* offset: 0x0444 size: 32 bit */
17989 /* Message Buffer Data Register */
17990 FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE0_3; /* offset: 0x0448 size: 32 bit */
17991 /* Message Buffer Data Register */
17992 FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE4_7; /* offset: 0x044C size: 32 bit */
17993 /* Message Buffer Control and Status */
17994 FLEXCAN_MSG_CS_32B_tag MSG61_CS; /* offset: 0x0450 size: 32 bit */
17995 /* Message Buffer Identifier Field */
17996 FLEXCAN_MSG_ID_32B_tag MSG61_ID; /* offset: 0x0454 size: 32 bit */
17997 /* Message Buffer Data Register */
17998 FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE0_3; /* offset: 0x0458 size: 32 bit */
17999 /* Message Buffer Data Register */
18000 FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE4_7; /* offset: 0x045C size: 32 bit */
18001 /* Message Buffer Control and Status */
18002 FLEXCAN_MSG_CS_32B_tag MSG62_CS; /* offset: 0x0460 size: 32 bit */
18003 /* Message Buffer Identifier Field */
18004 FLEXCAN_MSG_ID_32B_tag MSG62_ID; /* offset: 0x0464 size: 32 bit */
18005 /* Message Buffer Data Register */
18006 FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE0_3; /* offset: 0x0468 size: 32 bit */
18007 /* Message Buffer Data Register */
18008 FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE4_7; /* offset: 0x046C size: 32 bit */
18009 /* Message Buffer Control and Status */
18010 FLEXCAN_MSG_CS_32B_tag MSG63_CS; /* offset: 0x0470 size: 32 bit */
18011 /* Message Buffer Identifier Field */
18012 FLEXCAN_MSG_ID_32B_tag MSG63_ID; /* offset: 0x0474 size: 32 bit */
18013 /* Message Buffer Data Register */
18014 FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE0_3; /* offset: 0x0478 size: 32 bit */
18015 /* Message Buffer Data Register */
18016 FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE4_7; /* offset: 0x047C size: 32 bit */
18017 };
18018
18019 };
18020 int8_t FLEXCAN_reserved_0480_C[1024];
18021 union {
18022 /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */
18023 FLEXCAN_RXIMR_32B_tag RXIMR[64]; /* offset: 0x0880 (0x0004 x 64) */
18024
18025 struct {
18026 /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */
18027 FLEXCAN_RXIMR_32B_tag RXIMR0; /* offset: 0x0880 size: 32 bit */
18028 FLEXCAN_RXIMR_32B_tag RXIMR1; /* offset: 0x0884 size: 32 bit */
18029 FLEXCAN_RXIMR_32B_tag RXIMR2; /* offset: 0x0888 size: 32 bit */
18030 FLEXCAN_RXIMR_32B_tag RXIMR3; /* offset: 0x088C size: 32 bit */
18031 FLEXCAN_RXIMR_32B_tag RXIMR4; /* offset: 0x0890 size: 32 bit */
18032 FLEXCAN_RXIMR_32B_tag RXIMR5; /* offset: 0x0894 size: 32 bit */
18033 FLEXCAN_RXIMR_32B_tag RXIMR6; /* offset: 0x0898 size: 32 bit */
18034 FLEXCAN_RXIMR_32B_tag RXIMR7; /* offset: 0x089C size: 32 bit */
18035 FLEXCAN_RXIMR_32B_tag RXIMR8; /* offset: 0x08A0 size: 32 bit */
18036 FLEXCAN_RXIMR_32B_tag RXIMR9; /* offset: 0x08A4 size: 32 bit */
18037 FLEXCAN_RXIMR_32B_tag RXIMR10; /* offset: 0x08A8 size: 32 bit */
18038 FLEXCAN_RXIMR_32B_tag RXIMR11; /* offset: 0x08AC size: 32 bit */
18039 FLEXCAN_RXIMR_32B_tag RXIMR12; /* offset: 0x08B0 size: 32 bit */
18040 FLEXCAN_RXIMR_32B_tag RXIMR13; /* offset: 0x08B4 size: 32 bit */
18041 FLEXCAN_RXIMR_32B_tag RXIMR14; /* offset: 0x08B8 size: 32 bit */
18042 FLEXCAN_RXIMR_32B_tag RXIMR15; /* offset: 0x08BC size: 32 bit */
18043 FLEXCAN_RXIMR_32B_tag RXIMR16; /* offset: 0x08C0 size: 32 bit */
18044 FLEXCAN_RXIMR_32B_tag RXIMR17; /* offset: 0x08C4 size: 32 bit */
18045 FLEXCAN_RXIMR_32B_tag RXIMR18; /* offset: 0x08C8 size: 32 bit */
18046 FLEXCAN_RXIMR_32B_tag RXIMR19; /* offset: 0x08CC size: 32 bit */
18047 FLEXCAN_RXIMR_32B_tag RXIMR20; /* offset: 0x08D0 size: 32 bit */
18048 FLEXCAN_RXIMR_32B_tag RXIMR21; /* offset: 0x08D4 size: 32 bit */
18049 FLEXCAN_RXIMR_32B_tag RXIMR22; /* offset: 0x08D8 size: 32 bit */
18050 FLEXCAN_RXIMR_32B_tag RXIMR23; /* offset: 0x08DC size: 32 bit */
18051 FLEXCAN_RXIMR_32B_tag RXIMR24; /* offset: 0x08E0 size: 32 bit */
18052 FLEXCAN_RXIMR_32B_tag RXIMR25; /* offset: 0x08E4 size: 32 bit */
18053 FLEXCAN_RXIMR_32B_tag RXIMR26; /* offset: 0x08E8 size: 32 bit */
18054 FLEXCAN_RXIMR_32B_tag RXIMR27; /* offset: 0x08EC size: 32 bit */
18055 FLEXCAN_RXIMR_32B_tag RXIMR28; /* offset: 0x08F0 size: 32 bit */
18056 FLEXCAN_RXIMR_32B_tag RXIMR29; /* offset: 0x08F4 size: 32 bit */
18057 FLEXCAN_RXIMR_32B_tag RXIMR30; /* offset: 0x08F8 size: 32 bit */
18058 FLEXCAN_RXIMR_32B_tag RXIMR31; /* offset: 0x08FC size: 32 bit */
18059 FLEXCAN_RXIMR_32B_tag RXIMR32; /* offset: 0x0900 size: 32 bit */
18060 FLEXCAN_RXIMR_32B_tag RXIMR33; /* offset: 0x0904 size: 32 bit */
18061 FLEXCAN_RXIMR_32B_tag RXIMR34; /* offset: 0x0908 size: 32 bit */
18062 FLEXCAN_RXIMR_32B_tag RXIMR35; /* offset: 0x090C size: 32 bit */
18063 FLEXCAN_RXIMR_32B_tag RXIMR36; /* offset: 0x0910 size: 32 bit */
18064 FLEXCAN_RXIMR_32B_tag RXIMR37; /* offset: 0x0914 size: 32 bit */
18065 FLEXCAN_RXIMR_32B_tag RXIMR38; /* offset: 0x0918 size: 32 bit */
18066 FLEXCAN_RXIMR_32B_tag RXIMR39; /* offset: 0x091C size: 32 bit */
18067 FLEXCAN_RXIMR_32B_tag RXIMR40; /* offset: 0x0920 size: 32 bit */
18068 FLEXCAN_RXIMR_32B_tag RXIMR41; /* offset: 0x0924 size: 32 bit */
18069 FLEXCAN_RXIMR_32B_tag RXIMR42; /* offset: 0x0928 size: 32 bit */
18070 FLEXCAN_RXIMR_32B_tag RXIMR43; /* offset: 0x092C size: 32 bit */
18071 FLEXCAN_RXIMR_32B_tag RXIMR44; /* offset: 0x0930 size: 32 bit */
18072 FLEXCAN_RXIMR_32B_tag RXIMR45; /* offset: 0x0934 size: 32 bit */
18073 FLEXCAN_RXIMR_32B_tag RXIMR46; /* offset: 0x0938 size: 32 bit */
18074 FLEXCAN_RXIMR_32B_tag RXIMR47; /* offset: 0x093C size: 32 bit */
18075 FLEXCAN_RXIMR_32B_tag RXIMR48; /* offset: 0x0940 size: 32 bit */
18076 FLEXCAN_RXIMR_32B_tag RXIMR49; /* offset: 0x0944 size: 32 bit */
18077 FLEXCAN_RXIMR_32B_tag RXIMR50; /* offset: 0x0948 size: 32 bit */
18078 FLEXCAN_RXIMR_32B_tag RXIMR51; /* offset: 0x094C size: 32 bit */
18079 FLEXCAN_RXIMR_32B_tag RXIMR52; /* offset: 0x0950 size: 32 bit */
18080 FLEXCAN_RXIMR_32B_tag RXIMR53; /* offset: 0x0954 size: 32 bit */
18081 FLEXCAN_RXIMR_32B_tag RXIMR54; /* offset: 0x0958 size: 32 bit */
18082 FLEXCAN_RXIMR_32B_tag RXIMR55; /* offset: 0x095C size: 32 bit */
18083 FLEXCAN_RXIMR_32B_tag RXIMR56; /* offset: 0x0960 size: 32 bit */
18084 FLEXCAN_RXIMR_32B_tag RXIMR57; /* offset: 0x0964 size: 32 bit */
18085 FLEXCAN_RXIMR_32B_tag RXIMR58; /* offset: 0x0968 size: 32 bit */
18086 FLEXCAN_RXIMR_32B_tag RXIMR59; /* offset: 0x096C size: 32 bit */
18087 FLEXCAN_RXIMR_32B_tag RXIMR60; /* offset: 0x0970 size: 32 bit */
18088 FLEXCAN_RXIMR_32B_tag RXIMR61; /* offset: 0x0974 size: 32 bit */
18089 FLEXCAN_RXIMR_32B_tag RXIMR62; /* offset: 0x0978 size: 32 bit */
18090 FLEXCAN_RXIMR_32B_tag RXIMR63; /* offset: 0x097C size: 32 bit */
18091 };
18092
18093 };
18094 } FLEXCAN_tag;
18095
18096
18097#define FLEXCAN_A (*(volatile FLEXCAN_tag *) 0xFFFC0000UL)
18098#define FLEXCAN_B (*(volatile FLEXCAN_tag *) 0xFFFC4000UL)
18099
18100
18101
18102/****************************************************************/
18103/* */
18104/* Module: DMA_CH_MUX */
18105/* */
18106/****************************************************************/
18107
18108
18109 /* Register layout for all registers CHCONFIG... */
18110
18111 typedef union { /* CHCONFIG[0-15] - Channel Configuration Registers */
18112 uint8_t R;
18113 struct {
18114 uint8_t ENBL:1; /* DMA Channel Enable */
18115 uint8_t TRIG:1; /* DMA Channel Trigger Enable */
18116 uint8_t SOURCE:6; /* DMA Channel Source */
18117 } B;
18118 } DMA_CH_MUX_CHCONFIG_8B_tag;
18119
18120
18121
18122 typedef struct DMA_CH_MUX_struct_tag { /* start of DMA_CH_MUX_tag */
18123 union {
18124 /* CHCONFIG[0-15] - Channel Configuration Registers */
18125 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG[16]; /* offset: 0x0000 (0x0001 x 16) */
18126
18127 struct {
18128 /* CHCONFIG[0-15] - Channel Configuration Registers */
18129 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG0; /* offset: 0x0000 size: 8 bit */
18130 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG1; /* offset: 0x0001 size: 8 bit */
18131 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG2; /* offset: 0x0002 size: 8 bit */
18132 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG3; /* offset: 0x0003 size: 8 bit */
18133 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG4; /* offset: 0x0004 size: 8 bit */
18134 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG5; /* offset: 0x0005 size: 8 bit */
18135 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG6; /* offset: 0x0006 size: 8 bit */
18136 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG7; /* offset: 0x0007 size: 8 bit */
18137 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG8; /* offset: 0x0008 size: 8 bit */
18138 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG9; /* offset: 0x0009 size: 8 bit */
18139 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG10; /* offset: 0x000A size: 8 bit */
18140 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG11; /* offset: 0x000B size: 8 bit */
18141 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG12; /* offset: 0x000C size: 8 bit */
18142 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG13; /* offset: 0x000D size: 8 bit */
18143 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG14; /* offset: 0x000E size: 8 bit */
18144 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG15; /* offset: 0x000F size: 8 bit */
18145 };
18146
18147 };
18148 } DMA_CH_MUX_tag;
18149
18150
18151#define DMA_CH_MUX (*(volatile DMA_CH_MUX_tag *) 0xFFFDC000UL)
18152
18153
18154
18155/****************************************************************/
18156/* */
18157/* Module: FR */
18158/* */
18159/****************************************************************/
18160
18161 typedef union { /* Module Version Number */
18162 uint16_t R;
18163 struct {
18164 uint16_t CHIVER:8; /* VERSION NUMBER OF CHI */
18165 uint16_t PEVER:8; /* VERSION NUMBER OF PE */
18166 } B;
18167 } FR_MVR_16B_tag;
18168
18169 typedef union { /* Module Configuration Register */
18170 uint16_t R;
18171 struct {
18172 uint16_t MEN:1; /* Module Enable */
18173 uint16_t SBFF:1; /* System Bus Failure Freeze */
18174#ifndef USE_FIELD_ALIASES_FR
18175 uint16_t SCM:1; /* single channel device mode */
18176#else
18177 uint16_t SCMD:1; /* deprecated name - please avoid */
18178#endif
18179 uint16_t CHB:1; /* Channel B enable */
18180 uint16_t CHA:1; /* channel A enable */
18181 uint16_t SFFE:1; /* Sync. frame filter Enable */
18182 uint16_t ECCE:1; /* ECC Functionlity Enable */
18183 uint16_t TMODER:1; /* Functional Test mode */
18184 uint16_t FUM:1; /* FIFO Update Mode */
18185 uint16_t FAM:1; /* FIFO Address Mode */
18186 uint16_t:1;
18187 uint16_t CLKSEL:1; /* Protocol Engine clock source select */
18188 uint16_t BITRATE:3; /* Bus bit rate */
18189 uint16_t:1;
18190 } B;
18191 } FR_MCR_16B_tag;
18192
18193 typedef union { /* SYSTEM MEMORY BASE ADD HIGH REG */
18194 uint16_t R;
18195 struct {
18196 uint16_t SMBA_31_16:16; /* SYS_MEM_BASE_ADDR[31:16] */
18197 } B;
18198 } FR_SYMBADHR_16B_tag;
18199
18200 typedef union { /* SYSTEM MEMORY BASE ADD LOW REG */
18201 uint16_t R;
18202 struct {
18203 uint16_t SMBA_15_4:12; /* SYS_MEM_BASE_ADDR[15:4] */
18204 uint16_t:4;
18205 } B;
18206 } FR_SYMBADLR_16B_tag;
18207
18208 typedef union { /* STROBE SIGNAL CONTROL REGISTER */
18209 uint16_t R;
18210 struct {
18211 uint16_t WMD:1; /* DEFINES WRITE MODE OF REG */
18212 uint16_t:3;
18213 uint16_t SEL:4; /* STROBE SIGNSL SELECT */
18214 uint16_t:3;
18215 uint16_t ENB:1; /* STROBE SIGNAL ENABLE */
18216 uint16_t:2;
18217 uint16_t STBPSEL:2; /* STROBE PORT SELECT */
18218 } B;
18219 } FR_STBSCR_16B_tag;
18220
18221 typedef union { /* MESSAGE BUFFER DATA SIZE REGISTER */
18222 uint16_t R;
18223 struct {
18224 uint16_t:1;
18225 uint16_t MBSEG2DS:7; /* MESSAGE BUFFER SEGMENT 2 DATA SIZE */
18226 uint16_t:1;
18227 uint16_t MBSEG1DS:7; /* MESSAGE BUFFER SEGMENT 1 DATA SIZE */
18228 } B;
18229 } FR_MBDSR_16B_tag;
18230
18231 typedef union { /* MESS. BUFFER SEG. SIZE & UTILISATION REG */
18232 uint16_t R;
18233 struct {
18234 uint16_t:2;
18235 uint16_t LAST_MB_SEG1:6; /* LAST MESS BUFFER IN SEG 1 */
18236 uint16_t:2;
18237 uint16_t LAST_MB_UTIL:6; /* LAST MESSAGE BUFFER UTILISED */
18238 } B;
18239 } FR_MBSSUTR_16B_tag;
18240
18241 typedef union { /* PE DRAM ACCESS REGISTER */
18242 uint16_t R;
18243 struct {
18244 uint16_t INST:4; /* PE DRAM ACCESS INSTRUCTION */
18245 uint16_t ADDR:11; /* PE DRAM ACCESS ADDRESS */
18246 uint16_t DAD:1; /* PE DRAM ACCESS DONE */
18247 } B;
18248 } FR_PEDRAR_16B_tag;
18249
18250 typedef union { /* PE DRAM DATA REGISTER */
18251 uint16_t R;
18252 struct {
18253 uint16_t DATA:16; /* DATA TO BE READ OR WRITTEN */
18254 } B;
18255 } FR_PEDRDR_16B_tag;
18256
18257 typedef union { /* PROTOCOL OPERATION CONTROL REG */
18258 uint16_t R;
18259 struct {
18260 uint16_t WME:1; /* WRITE MODE EXTERNAL CORRECTION */
18261 uint16_t:3;
18262 uint16_t EOC_AP:2; /* EXTERNAL OFFSET CORRECTION APPLICATION */
18263 uint16_t ERC_AP:2; /* EXTERNAL RATE CORRECTION APPLICATION */
18264 uint16_t BSY:1; /* PROTOCOL CONTROL COMMAND WRITE BUSY */
18265 uint16_t:3;
18266 uint16_t POCCMD:4; /* PROTOCOL CONTROL COMMAND */
18267 } B;
18268 } FR_POCR_16B_tag;
18269
18270 typedef union { /* GLOBAL INTERRUPT FLAG & ENABLE REG */
18271 uint16_t R;
18272 struct {
18273 uint16_t MIF:1; /* MODULE INTERRUPT FLAG */
18274 uint16_t PRIF:1; /* PROTOCOL INTERRUPT FLAG */
18275 uint16_t CHIF:1; /* CHI INTERRUPT FLAG */
18276#ifndef USE_FIELD_ALIASES_FR
18277 uint16_t WUPIF:1; /* WAKEUP INTERRUPT FLAG */
18278#else
18279 uint16_t WKUPIF:1; /* deprecated name - please avoid */
18280#endif
18281#ifndef USE_FIELD_ALIASES_FR
18282 uint16_t FAFBIF:1; /* RECEIVE FIFO CHANNEL B ALMOST FULL INTERRUPT FLAG */
18283#else
18284 uint16_t FNEBIF:1; /* deprecated name - please avoid */
18285#endif
18286#ifndef USE_FIELD_ALIASES_FR
18287 uint16_t FAFAIF:1; /* RECEIVE FIFO CHANNEL A ALMOST FULL INTERRUPT FLAG */
18288#else
18289 uint16_t FNEAIF:1; /* deprecated name - please avoid */
18290#endif
18291 uint16_t RBIF:1; /* RECEIVE MESSAGE BUFFER INTERRUPT FLAG */
18292 uint16_t TBIF:1; /* TRANSMIT BUFFER INTERRUPT FLAG */
18293 uint16_t MIE:1; /* MODULE INTERRUPT ENABLE */
18294 uint16_t PRIE:1; /* PROTOCOL INTERRUPT ENABLE */
18295 uint16_t CHIE:1; /* CHI INTERRUPT ENABLE */
18296#ifndef USE_FIELD_ALIASES_FR
18297 uint16_t WUPIE:1; /* WAKEUP INTERRUPT ENABLE */
18298#else
18299 uint16_t WKUPIE:1; /* deprecated name - please avoid */
18300#endif
18301 uint16_t FNEBIE:1; /* RECEIVE FIFO CHANNEL B NOT EMPTY INTERRUPT ENABLE */
18302 uint16_t FNEAIE:1; /* RECEIVE FIFO CHANNEL A NOT EMPTY INTERRUPT ENABLE */
18303 uint16_t RBIE:1; /* RECEIVE BUFFER INTERRUPT ENABLE */
18304 uint16_t TBIE:1; /* TRANSMIT BUFFER INTERRUPT ENABLE */
18305 } B;
18306 } FR_GIFER_16B_tag;
18307
18308 typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 0 */
18309 uint16_t R;
18310 struct {
18311#ifndef USE_FIELD_ALIASES_FR
18312 uint16_t FATL_IF:1; /* FATAL PROTOCOL ERROR INTERRUPT FLAG */
18313#else
18314 uint16_t FATLIF:1; /* deprecated name - please avoid */
18315#endif
18316#ifndef USE_FIELD_ALIASES_FR
18317 uint16_t INTL_IF:1; /* INTERNAL PROTOCOL ERROR INTERRUPT FLAG */
18318#else
18319 uint16_t INTLIF:1; /* deprecated name - please avoid */
18320#endif
18321#ifndef USE_FIELD_ALIASES_FR
18322 uint16_t ILCF_IF:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT FLAG */
18323#else
18324 uint16_t ILCFIF:1; /* deprecated name - please avoid */
18325#endif
18326#ifndef USE_FIELD_ALIASES_FR
18327 uint16_t CSA_IF:1; /* COLDSTART ABORT INTERRUPT FLAG */
18328#else
18329 uint16_t CSAIF:1; /* deprecated name - please avoid */
18330#endif
18331#ifndef USE_FIELD_ALIASES_FR
18332 uint16_t MRC_IF:1; /* MISSING RATE CORRECTION INTERRUPT FLAG */
18333#else
18334 uint16_t MRCIF:1; /* deprecated name - please avoid */
18335#endif
18336#ifndef USE_FIELD_ALIASES_FR
18337 uint16_t MOC_IF:1; /* MISSING OFFSET CORRECTION INTERRUPT FLAG */
18338#else
18339 uint16_t MOCIF:1; /* deprecated name - please avoid */
18340#endif
18341#ifndef USE_FIELD_ALIASES_FR
18342 uint16_t CCL_IF:1; /* CLOCK CORRECTION LIMIT REACHED INTERRUPT FLAG */
18343#else
18344 uint16_t CCLIF:1; /* deprecated name - please avoid */
18345#endif
18346#ifndef USE_FIELD_ALIASES_FR
18347 uint16_t MXS_IF:1; /* MAX SYNC FRAMES DETECTED INTERRUPT FLAG */
18348#else
18349 uint16_t MXSIF:1; /* deprecated name - please avoid */
18350#endif
18351#ifndef USE_FIELD_ALIASES_FR
18352 uint16_t MTX_IF:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT FLAG */
18353#else
18354 uint16_t MTXIF:1; /* deprecated name - please avoid */
18355#endif
18356#ifndef USE_FIELD_ALIASES_FR
18357 uint16_t LTXB_IF:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT FLAG */
18358#else
18359 uint16_t LTXBIF:1; /* deprecated name - please avoid */
18360#endif
18361#ifndef USE_FIELD_ALIASES_FR
18362 uint16_t LTXA_IF:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT FLAG */
18363#else
18364 uint16_t LTXAIF:1; /* deprecated name - please avoid */
18365#endif
18366#ifndef USE_FIELD_ALIASES_FR
18367 uint16_t TBVB_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT FLAG */
18368#else
18369 uint16_t TBVBIF:1; /* deprecated name - please avoid */
18370#endif
18371#ifndef USE_FIELD_ALIASES_FR
18372 uint16_t TBVA_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT FLAG */
18373#else
18374 uint16_t TBVAIF:1; /* deprecated name - please avoid */
18375#endif
18376#ifndef USE_FIELD_ALIASES_FR
18377 uint16_t TI2_IF:1; /* TIMER 2 EXPIRED INTERRUPT FLAG */
18378#else
18379 uint16_t TI2IF:1; /* deprecated name - please avoid */
18380#endif
18381#ifndef USE_FIELD_ALIASES_FR
18382 uint16_t TI1_IF:1; /* TIMER 1 EXPIRED INTERRUPT FLAG */
18383#else
18384 uint16_t TI1IF:1; /* deprecated name - please avoid */
18385#endif
18386#ifndef USE_FIELD_ALIASES_FR
18387 uint16_t CYS_IF:1; /* CYCLE START INTERRUPT FLAG */
18388#else
18389 uint16_t CYSIF:1; /* deprecated name - please avoid */
18390#endif
18391 } B;
18392 } FR_PIFR0_16B_tag;
18393
18394 typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 1 */
18395 uint16_t R;
18396 struct {
18397#ifndef USE_FIELD_ALIASES_FR
18398 uint16_t EMC_IF:1; /* ERROR MODE CHANGED INTERRUPT FLAG */
18399#else
18400 uint16_t EMCIF:1; /* deprecated name - please avoid */
18401#endif
18402#ifndef USE_FIELD_ALIASES_FR
18403 uint16_t IPC_IF:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT FLAG */
18404#else
18405 uint16_t IPCIF:1; /* deprecated name - please avoid */
18406#endif
18407#ifndef USE_FIELD_ALIASES_FR
18408 uint16_t PECF_IF:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT FLAG */
18409#else
18410 uint16_t PECFIF:1; /* deprecated name - please avoid */
18411#endif
18412#ifndef USE_FIELD_ALIASES_FR
18413 uint16_t PSC_IF:1; /* PROTOCOL STATE CHANGED INTERRUPT FLAG */
18414#else
18415 uint16_t PSCIF:1; /* deprecated name - please avoid */
18416#endif
18417#ifndef USE_FIELD_ALIASES_FR
18418 uint16_t SSI3_IF:1; /* SLOT STATUS COUNTER 3 INCREMENTED INTERRUPT FLAG */
18419#else
18420 uint16_t SSI3IF:1; /* deprecated name - please avoid */
18421#endif
18422#ifndef USE_FIELD_ALIASES_FR
18423 uint16_t SSI2_IF:1; /* SLOT STATUS COUNTER 2 INCREMENTED INTERRUPT FLAG */
18424#else
18425 uint16_t SSI2IF:1; /* deprecated name - please avoid */
18426#endif
18427#ifndef USE_FIELD_ALIASES_FR
18428 uint16_t SSI1_IF:1; /* SLOT STATUS COUNTER 1 INCREMENTED INTERRUPT FLAG */
18429#else
18430 uint16_t SSI1IF:1; /* deprecated name - please avoid */
18431#endif
18432#ifndef USE_FIELD_ALIASES_FR
18433 uint16_t SSI0_IF:1; /* SLOT STATUS COUNTER 0 INCREMENTED INTERRUPT FLAG */
18434#else
18435 uint16_t SSI0IF:1; /* deprecated name - please avoid */
18436#endif
18437 uint16_t:2;
18438#ifndef USE_FIELD_ALIASES_FR
18439 uint16_t EVT_IF:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT FLAG */
18440#else
18441 uint16_t EVTIF:1; /* deprecated name - please avoid */
18442#endif
18443#ifndef USE_FIELD_ALIASES_FR
18444 uint16_t ODT_IF:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT FLAG */
18445#else
18446 uint16_t ODTIF:1; /* deprecated name - please avoid */
18447#endif
18448 uint16_t:4;
18449 } B;
18450 } FR_PIFR1_16B_tag;
18451
18452 typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */
18453 uint16_t R;
18454 struct {
18455#ifndef USE_FIELD_ALIASES_FR
18456 uint16_t FATL_IE:1; /* FATAL PROTOCOL ERROR INTERRUPT ENABLE */
18457#else
18458 uint16_t FATLIE:1; /* deprecated name - please avoid */
18459#endif
18460#ifndef USE_FIELD_ALIASES_FR
18461 uint16_t INTL_IE:1; /* INTERNAL PROTOCOL ERROR INTERRUPT ENABLE */
18462#else
18463 uint16_t INTLIE:1; /* deprecated name - please avoid */
18464#endif
18465#ifndef USE_FIELD_ALIASES_FR
18466 uint16_t ILCF_IE:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT ENABLE */
18467#else
18468 uint16_t ILCFIE:1; /* deprecated name - please avoid */
18469#endif
18470#ifndef USE_FIELD_ALIASES_FR
18471 uint16_t CSA_IE:1; /* COLDSTART ABORT INTERRUPT ENABLE */
18472#else
18473 uint16_t CSAIE:1; /* deprecated name - please avoid */
18474#endif
18475#ifndef USE_FIELD_ALIASES_FR
18476 uint16_t MRC_IE:1; /* MISSING RATE CORRECTION INTERRUPT ENABLE */
18477#else
18478 uint16_t MRCIE:1; /* deprecated name - please avoid */
18479#endif
18480#ifndef USE_FIELD_ALIASES_FR
18481 uint16_t MOC_IE:1; /* MISSING OFFSET CORRECTION INTERRUPT ENABLE */
18482#else
18483 uint16_t MOCIE:1; /* deprecated name - please avoid */
18484#endif
18485#ifndef USE_FIELD_ALIASES_FR
18486 uint16_t CCL_IE:1; /* CLOCK CORRECTION LIMIT REACHED */
18487#else
18488 uint16_t CCLIE:1; /* deprecated name - please avoid */
18489#endif
18490#ifndef USE_FIELD_ALIASES_FR
18491 uint16_t MXS_IE:1; /* MAX SYNC FRAMES DETECTED INTERRUPT ENABLE */
18492#else
18493 uint16_t MXSIE:1; /* deprecated name - please avoid */
18494#endif
18495#ifndef USE_FIELD_ALIASES_FR
18496 uint16_t MTX_IE:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT ENABLE */
18497#else
18498 uint16_t MTXIE:1; /* deprecated name - please avoid */
18499#endif
18500#ifndef USE_FIELD_ALIASES_FR
18501 uint16_t LTXB_IE:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT ENABLE */
18502#else
18503 uint16_t LTXBIE:1; /* deprecated name - please avoid */
18504#endif
18505#ifndef USE_FIELD_ALIASES_FR
18506 uint16_t LTXA_IE:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT ENABLE */
18507#else
18508 uint16_t LTXAIE:1; /* deprecated name - please avoid */
18509#endif
18510#ifndef USE_FIELD_ALIASES_FR
18511 uint16_t TBVB_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT ENABLE */
18512#else
18513 uint16_t TBVBIE:1; /* deprecated name - please avoid */
18514#endif
18515#ifndef USE_FIELD_ALIASES_FR
18516 uint16_t TBVA_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT ENABLE */
18517#else
18518 uint16_t TBVAIE:1; /* deprecated name - please avoid */
18519#endif
18520#ifndef USE_FIELD_ALIASES_FR
18521 uint16_t TI2_IE:1; /* TIMER 2 EXPIRED INTERRUPT ENABLE */
18522#else
18523 uint16_t TI2IE:1; /* deprecated name - please avoid */
18524#endif
18525#ifndef USE_FIELD_ALIASES_FR
18526 uint16_t TI1_IE:1; /* TIMER 1 EXPIRED INTERRUPT ENABLE */
18527#else
18528 uint16_t TI1IE:1; /* deprecated name - please avoid */
18529#endif
18530#ifndef USE_FIELD_ALIASES_FR
18531 uint16_t CYS_IE:1; /* CYCLE START INTERRUPT ENABLE */
18532#else
18533 uint16_t CYSIE:1; /* deprecated name - please avoid */
18534#endif
18535 } B;
18536 } FR_PIER0_16B_tag;
18537
18538 typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */
18539 uint16_t R;
18540 struct {
18541#ifndef USE_FIELD_ALIASES_FR
18542 uint16_t EMC_IE:1; /* ERROR MODE CHANGED INTERRUPT Enable */
18543#else
18544 uint16_t EMCIE:1; /* deprecated name - please avoid */
18545#endif
18546#ifndef USE_FIELD_ALIASES_FR
18547 uint16_t IPC_IE:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT Enable */
18548#else
18549 uint16_t IPCIE:1; /* deprecated name - please avoid */
18550#endif
18551#ifndef USE_FIELD_ALIASES_FR
18552 uint16_t PECF_IE:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT Enable */
18553#else
18554 uint16_t PECFIE:1; /* deprecated name - please avoid */
18555#endif
18556#ifndef USE_FIELD_ALIASES_FR
18557 uint16_t PSC_IE:1; /* PROTOCOL STATE CHANGED INTERRUPT Enable */
18558#else
18559 uint16_t PSCIE:1; /* deprecated name - please avoid */
18560#endif
18561#ifndef USE_FIELD_ALIASES_FR
18562 uint16_t SSI_3_0_IE:4; /* SLOT STATUS COUNTER INCREMENTED INTERRUPT Enable */
18563#else
18564 uint16_t SSI3IE:1;
18565 uint16_t SSI2IE:1;
18566 uint16_t SSI1IE:1;
18567 uint16_t SSI0IE:1;
18568#endif
18569
18570 uint16_t:2;
18571#ifndef USE_FIELD_ALIASES_FR
18572 uint16_t EVT_IE:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT Enable */
18573#else
18574 uint16_t EVTIE:1; /* deprecated name - please avoid */
18575#endif
18576#ifndef USE_FIELD_ALIASES_FR
18577 uint16_t ODT_IE:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT Enable */
18578#else
18579 uint16_t ODTIE:1; /* deprecated name - please avoid */
18580#endif
18581 uint16_t:4;
18582 } B;
18583 } FR_PIER1_16B_tag;
18584
18585 typedef union { /* CHI ERROR FLAG REGISTER */
18586 uint16_t R;
18587 struct {
18588#ifndef USE_FIELD_ALIASES_FR
18589 uint16_t FRLB_EF:1; /* FRAME LOST CHANNEL B ERROR FLAG */
18590#else
18591 uint16_t FRLBEF:1; /* deprecated name - please avoid */
18592#endif
18593#ifndef USE_FIELD_ALIASES_FR
18594 uint16_t FRLA_EF:1; /* FRAME LOST CHANNEL A ERROR FLAG */
18595#else
18596 uint16_t FRLAEF:1; /* deprecated name - please avoid */
18597#endif
18598#ifndef USE_FIELD_ALIASES_FR
18599 uint16_t PCMI_EF:1; /* PROTOCOL COMMAND IGNORED ERROR FLAG */
18600#else
18601 uint16_t PCMIEF:1; /* deprecated name - please avoid */
18602#endif
18603#ifndef USE_FIELD_ALIASES_FR
18604 uint16_t FOVB_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL B ERROR FLAG */
18605#else
18606 uint16_t FOVBEF:1; /* deprecated name - please avoid */
18607#endif
18608#ifndef USE_FIELD_ALIASES_FR
18609 uint16_t FOVA_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL A ERROR FLAG */
18610#else
18611 uint16_t FOVAEF:1; /* deprecated name - please avoid */
18612#endif
18613#ifndef USE_FIELD_ALIASES_FR
18614 uint16_t MBS_EF:1; /* MESSAGE BUFFER SEARCH ERROR FLAG */
18615#else
18616 uint16_t MSBEF:1; /* deprecated name - please avoid */
18617#endif
18618#ifndef USE_FIELD_ALIASES_FR
18619 uint16_t MBU_EF:1; /* MESSAGE BUFFER UTILIZATION ERROR FLAG */
18620#else
18621 uint16_t MBUEF:1; /* deprecated name - please avoid */
18622#endif
18623#ifndef USE_FIELD_ALIASES_FR
18624 uint16_t LCK_EF:1; /* LOCK ERROR FLAG */
18625#else
18626 uint16_t LCKEF:1; /* deprecated name - please avoid */
18627#endif
18628#ifndef USE_FIELD_ALIASES_FR
18629 uint16_t DBL_EF:1; /* DOUBLE TRANSMIT MESSAGE BUFFER LOCK ERROR FLAG */
18630#else
18631 uint16_t DBLEF:1; /* deprecated name - please avoid */
18632#endif
18633#ifndef USE_FIELD_ALIASES_FR
18634 uint16_t SBCF_EF:1; /* SYSTEM BUS COMMUNICATION FAILURE ERROR FLAG */
18635#else
18636 uint16_t SBCFEF:1; /* deprecated name - please avoid */
18637#endif
18638#ifndef USE_FIELD_ALIASES_FR
18639 uint16_t FID_EF:1; /* FRAME ID ERROR FLAG */
18640#else
18641 uint16_t FIDEF:1; /* deprecated name - please avoid */
18642#endif
18643#ifndef USE_FIELD_ALIASES_FR
18644 uint16_t DPL_EF:1; /* DYNAMIC PAYLOAD LENGTH ERROR FLAG */
18645#else
18646 uint16_t DPLEF:1; /* deprecated name - please avoid */
18647#endif
18648#ifndef USE_FIELD_ALIASES_FR
18649 uint16_t SPL_EF:1; /* STATIC PAYLOAD LENGTH ERROR FLAG */
18650#else
18651 uint16_t SPLEF:1; /* deprecated name - please avoid */
18652#endif
18653#ifndef USE_FIELD_ALIASES_FR
18654 uint16_t NML_EF:1; /* NETWORK MANAGEMENT LENGTH ERROR FLAG */
18655#else
18656 uint16_t NMLEF:1; /* deprecated name - please avoid */
18657#endif
18658#ifndef USE_FIELD_ALIASES_FR
18659 uint16_t NMF_EF:1; /* NETWORK MANAGEMENT FRAME ERROR FLAG */
18660#else
18661 uint16_t NMFEF:1; /* deprecated name - please avoid */
18662#endif
18663#ifndef USE_FIELD_ALIASES_FR
18664 uint16_t ILSA_EF:1; /* ILLEGAL SYSTEM MEMORY ACCESS ERROR FLAG */
18665#else
18666 uint16_t ILSAEF:1; /* deprecated name - please avoid */
18667#endif
18668 } B;
18669 } FR_CHIERFR_16B_tag;
18670
18671 typedef union { /* Message Buffer Interrupt Vector Register */
18672 uint16_t R;
18673 struct {
18674 uint16_t:2;
18675 uint16_t TBIVEC:6; /* Transmit Buffer Interrupt Vector */
18676 uint16_t:2;
18677 uint16_t RBIVEC:6; /* Receive Buffer Interrupt Vector */
18678 } B;
18679 } FR_MBIVEC_16B_tag;
18680
18681 typedef union { /* Channel A Status Error Counter Register */
18682 uint16_t R;
18683 struct {
18684 uint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */
18685 } B;
18686 } FR_CASERCR_16B_tag;
18687
18688 typedef union { /* Channel B Status Error Counter Register */
18689 uint16_t R;
18690 struct {
18691 uint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */
18692 } B;
18693 } FR_CBSERCR_16B_tag;
18694
18695 typedef union { /* Protocol Status Register 0 */
18696 uint16_t R;
18697 struct {
18698 uint16_t ERRMODE:2; /* Error Mode */
18699 uint16_t SLOTMODE:2; /* Slot Mode */
18700 uint16_t:1;
18701 uint16_t PROTSTATE:3; /* Protocol State */
18702#ifndef USE_FIELD_ALIASES_FR
18703 uint16_t STARTUPSTATE:4; /* Startup State */
18704#else
18705 uint16_t SUBSTATE:4; /* deprecated name - please avoid */
18706#endif
18707 uint16_t WAKEUPSTATE:4; /* Wakeup Status */
18708 } B;
18709 } FR_PSR0_16B_tag;
18710
18711 typedef union { /* Protocol Status Register 1 */
18712 uint16_t R;
18713 struct {
18714 uint16_t CSAA:1; /* Coldstart Attempt Aborted Flag */
18715 uint16_t CSP:1; /* Leading Coldstart Path */
18716 uint16_t:1;
18717 uint16_t REMCSAT:5; /* Remaining Coldstart Attempts */
18718 uint16_t CPN:1; /* Leading Coldstart Path Noise */
18719 uint16_t HHR:1; /* Host Halt Request Pending */
18720 uint16_t FRZ:1; /* Freeze Occurred */
18721 uint16_t APTAC:5; /* Allow Passive to Active Counter */
18722 } B;
18723 } FR_PSR1_16B_tag;
18724
18725 typedef union { /* Protocol Status Register 2 */
18726 uint16_t R;
18727 struct {
18728 uint16_t NBVB:1; /* NIT Boundary Violation on Channel B */
18729 uint16_t NSEB:1; /* NIT Syntax Error on Channel B */
18730 uint16_t STCB:1; /* Symbol Window Transmit Conflict on Channel B */
18731#ifndef USE_FIELD_ALIASES_FR
18732 uint16_t SSVB:1; /* Symbol Window Boundary Violation on Channel B */
18733#else
18734 uint16_t SBVB:1; /* deprecated name - please avoid */
18735#endif
18736 uint16_t SSEB:1; /* Symbol Window Syntax Error on Channel B */
18737 uint16_t MTB:1; /* Media Access Test Symbol MTS Received on Channel B */
18738 uint16_t NBVA:1; /* NIT Boundary Violation on Channel A */
18739 uint16_t NSEA:1; /* NIT Syntax Error on Channel A */
18740 uint16_t STCA:1; /* Symbol Window Transmit Conflict on Channel A */
18741 uint16_t SBVA:1; /* Symbol Window Boundary Violation on Channel A */
18742 uint16_t SSEA:1; /* Symbol Window Syntax Error on Channel A */
18743 uint16_t MTA:1; /* Media Access Test Symbol MTS Received on Channel A */
18744 uint16_t CLKCORRFAILCNT:4; /* Clock Correction Failed Counter */
18745 } B;
18746 } FR_PSR2_16B_tag;
18747
18748 typedef union { /* Protocol Status Register 3 */
18749 uint16_t R;
18750 struct {
18751 uint16_t:2;
18752 uint16_t WUB:1; /* Wakeup Symbol Received on Channel B */
18753 uint16_t ABVB:1; /* Aggregated Boundary Violation on Channel B */
18754 uint16_t AACB:1; /* Aggregated Additional Communication on Channel B */
18755 uint16_t ACEB:1; /* Aggregated Content Error on Channel B */
18756 uint16_t ASEB:1; /* Aggregated Syntax Error on Channel B */
18757 uint16_t AVFB:1; /* Aggregated Valid Frame on Channel B */
18758 uint16_t:2;
18759 uint16_t WUA:1; /* Wakeup Symbol Received on Channel A */
18760 uint16_t ABVA:1; /* Aggregated Boundary Violation on Channel A */
18761 uint16_t AACA:1; /* Aggregated Additional Communication on Channel A */
18762 uint16_t ACEA:1; /* Aggregated Content Error on Channel A */
18763 uint16_t ASEA:1; /* Aggregated Syntax Error on Channel A */
18764 uint16_t AVFA:1; /* Aggregated Valid Frame on Channel A */
18765 } B;
18766 } FR_PSR3_16B_tag;
18767
18768 typedef union { /* Macrotick Counter Register */
18769 uint16_t R;
18770 struct {
18771 uint16_t:2;
18772 uint16_t MTCT:14; /* Macrotick Counter */
18773 } B;
18774 } FR_MTCTR_16B_tag;
18775
18776 typedef union { /* Cycle Counter Register */
18777 uint16_t R;
18778 struct {
18779 uint16_t:10;
18780 uint16_t CYCCNT:6; /* Cycle Counter */
18781 } B;
18782 } FR_CYCTR_16B_tag;
18783
18784 typedef union { /* Slot Counter Channel A Register */
18785 uint16_t R;
18786 struct {
18787 uint16_t:5;
18788 uint16_t SLOTCNTA:11; /* Slot Counter Value for Channel A */
18789 } B;
18790 } FR_SLTCTAR_16B_tag;
18791
18792 typedef union { /* Slot Counter Channel B Register */
18793 uint16_t R;
18794 struct {
18795 uint16_t:5;
18796 uint16_t SLOTCNTB:11; /* Slot Counter Value for Channel B */
18797 } B;
18798 } FR_SLTCTBR_16B_tag;
18799
18800 typedef union { /* Rate Correction Value Register */
18801 uint16_t R;
18802 struct {
18803 uint16_t RATECORR:16; /* Rate Correction Value */
18804 } B;
18805 } FR_RTCORVR_16B_tag;
18806
18807 typedef union { /* Offset Correction Value Register */
18808 uint16_t R;
18809 struct {
18810 uint16_t:6;
18811 uint16_t OFFSETCORR:10; /* Offset Correction Value */
18812 } B;
18813 } FR_OFCORVR_16B_tag;
18814
18815 typedef union { /* Combined Interrupt Flag Register */
18816 uint16_t R;
18817 struct {
18818 uint16_t:8;
18819#ifndef USE_FIELD_ALIASES_FR
18820 uint16_t MIF:1; /* Module Interrupt Flag */
18821#else
18822 uint16_t MIFR:1; /* deprecated name - please avoid */
18823#endif
18824#ifndef USE_FIELD_ALIASES_FR
18825 uint16_t PRIF:1; /* Protocol Interrupt Flag */
18826#else
18827 uint16_t PRIFR:1; /* deprecated name - please avoid */
18828#endif
18829#ifndef USE_FIELD_ALIASES_FR
18830 uint16_t CHIF:1; /* CHI Interrupt Flag */
18831#else
18832 uint16_t CHIFR:1; /* deprecated name - please avoid */
18833#endif
18834#ifndef USE_FIELD_ALIASES_FR
18835 uint16_t WUPIF:1; /* Wakeup Interrupt Flag */
18836#else
18837 uint16_t WUPIFR:1; /* deprecated name - please avoid */
18838#endif
18839#ifndef USE_FIELD_ALIASES_FR
18840 uint16_t FAFBIF:1; /* Receive FIFO channel B Almost Full Interrupt Flag */
18841#else
18842 uint16_t FNEBIFR:1; /* deprecated name - please avoid */
18843#endif
18844#ifndef USE_FIELD_ALIASES_FR
18845 uint16_t FAFAIF:1; /* Receive FIFO channel A Almost Full Interrupt Flag */
18846#else
18847 uint16_t FNEAIFR:1; /* deprecated name - please avoid */
18848#endif
18849#ifndef USE_FIELD_ALIASES_FR
18850 uint16_t RBIF:1; /* Receive Message Buffer Interrupt Flag */
18851#else
18852 uint16_t RBIFR:1; /* deprecated name - please avoid */
18853#endif
18854#ifndef USE_FIELD_ALIASES_FR
18855 uint16_t TBIF:1; /* Transmit Message Buffer Interrupt Flag */
18856#else
18857 uint16_t TBIFR:1; /* deprecated name - please avoid */
18858#endif
18859 } B;
18860 } FR_CIFR_16B_tag;
18861
18862 typedef union { /* System Memory Access Time-Out Register */
18863 uint16_t R;
18864 struct {
18865 uint16_t:8;
18866 uint16_t TIMEOUT:8; /* Time-Out */
18867 } B;
18868 } FR_SYMATOR_16B_tag;
18869
18870 typedef union { /* Sync Frame Counter Register */
18871 uint16_t R;
18872 struct {
18873 uint16_t SFEVB:4; /* Sync Frames Channel B, even cycle */
18874 uint16_t SFEVA:4; /* Sync Frames Channel A, even cycle */
18875 uint16_t SFODB:4; /* Sync Frames Channel B, odd cycle */
18876 uint16_t SFODA:4; /* Sync Frames Channel A, odd cycle */
18877 } B;
18878 } FR_SFCNTR_16B_tag;
18879
18880 typedef union { /* Sync Frame Table Offset Register */
18881 uint16_t R;
18882 struct {
18883 uint16_t SFT_OFFSET_15_1:15; /* Sync Frame Table Offset */
18884 uint16_t:1;
18885 } B;
18886 } FR_SFTOR_16B_tag;
18887
18888 typedef union { /* Sync Frame Table Configuration, Control, Status Register */
18889 uint16_t R;
18890 struct {
18891 uint16_t ELKT:1; /* Even Cycle Tables Lock/Unlock Trigger */
18892 uint16_t OLKT:1; /* Odd Cycle Tables Lock/Unlock Trigger */
18893 uint16_t CYCNUM:6; /* Cycle Number */
18894 uint16_t ELKS:1; /* Even Cycle Tables Lock Status */
18895 uint16_t OLKS:1; /* Odd Cycle Tables Lock Status */
18896 uint16_t EVAL:1; /* Even Cycle Tables Valid */
18897 uint16_t OVAL:1; /* Odd Cycle Tables Valid */
18898 uint16_t:1;
18899 uint16_t OPT:1; /* One Pair Trigger */
18900 uint16_t SDVEN:1; /* Sync Frame Deviation Table Enable */
18901#ifndef USE_FIELD_ALIASES_FR
18902 uint16_t SIVEN:1; /* Sync Frame ID Table Enable */
18903#else
18904 uint16_t SIDEN:1; /* deprecated name - please avoid */
18905#endif
18906 } B;
18907 } FR_SFTCCSR_16B_tag;
18908
18909 typedef union { /* Sync Frame ID Rejection Filter */
18910 uint16_t R;
18911 struct {
18912 uint16_t:6;
18913 uint16_t SYNFRID:10; /* Sync Frame Rejection ID */
18914 } B;
18915 } FR_SFIDRFR_16B_tag;
18916
18917 typedef union { /* Sync Frame ID Acceptance Filter Value Register */
18918 uint16_t R;
18919 struct {
18920 uint16_t:6;
18921 uint16_t FVAL:10; /* Filter Value */
18922 } B;
18923 } FR_SFIDAFVR_16B_tag;
18924
18925 typedef union { /* Sync Frame ID Acceptance Filter Mask Register */
18926 uint16_t R;
18927 struct {
18928 uint16_t:6;
18929 uint16_t FMSK:10; /* Filter Mask */
18930 } B;
18931 } FR_SFIDAFMR_16B_tag;
18932
18933 typedef union { /* Network Management Vector Register0 */
18934 uint16_t R;
18935 struct {
18936 uint16_t NMVP_15_8:8; /* Network Management Vector Part */
18937 uint16_t NMVP_7_0:8; /* Network Management Vector Part */
18938 } B;
18939 } FR_NMVR0_16B_tag;
18940
18941 typedef union { /* Network Management Vector Register1 */
18942 uint16_t R;
18943 struct {
18944 uint16_t NMVP_15_8:8; /* Network Management Vector Part */
18945 uint16_t NMVP_7_0:8; /* Network Management Vector Part */
18946 } B;
18947 } FR_NMVR1_16B_tag;
18948
18949 typedef union { /* Network Management Vector Register2 */
18950 uint16_t R;
18951 struct {
18952 uint16_t NMVP_15_8:8; /* Network Management Vector Part */
18953 uint16_t NMVP_7_0:8; /* Network Management Vector Part */
18954 } B;
18955 } FR_NMVR2_16B_tag;
18956
18957 typedef union { /* Network Management Vector Register3 */
18958 uint16_t R;
18959 struct {
18960 uint16_t NMVP_15_8:8; /* Network Management Vector Part */
18961 uint16_t NMVP_7_0:8; /* Network Management Vector Part */
18962 } B;
18963 } FR_NMVR3_16B_tag;
18964
18965 typedef union { /* Network Management Vector Register4 */
18966 uint16_t R;
18967 struct {
18968 uint16_t NMVP_15_8:8; /* Network Management Vector Part */
18969 uint16_t NMVP_7_0:8; /* Network Management Vector Part */
18970 } B;
18971 } FR_NMVR4_16B_tag;
18972
18973 typedef union { /* Network Management Vector Register5 */
18974 uint16_t R;
18975 struct {
18976 uint16_t NMVP_15_8:8; /* Network Management Vector Part */
18977 uint16_t NMVP_7_0:8; /* Network Management Vector Part */
18978 } B;
18979 } FR_NMVR5_16B_tag;
18980
18981 typedef union { /* Network Management Vector Length Register */
18982 uint16_t R;
18983 struct {
18984 uint16_t:12;
18985 uint16_t NMVL:4; /* Network Management Vector Length */
18986 } B;
18987 } FR_NMVLR_16B_tag;
18988
18989 typedef union { /* Timer Configuration and Control Register */
18990 uint16_t R;
18991 struct {
18992 uint16_t:2;
18993#ifndef USE_FIELD_ALIASES_FR
18994 uint16_t T2_CFG:1; /* Timer T2 Configuration */
18995#else
18996 uint16_t T2CFG:1; /* Timer T2 Configuration */
18997#endif
18998#ifndef USE_FIELD_ALIASES_FR
18999 uint16_t T2_REP:1; /* Timer T2 Repetitive Mode */
19000#else
19001 uint16_t T2REP:1; /* Timer T2 Configuration */
19002#endif
19003 uint16_t:1;
19004 uint16_t T2SP:1; /* Timer T2 Stop */
19005 uint16_t T2TR:1; /* Timer T2 Trigger */
19006 uint16_t T2ST:1; /* Timer T2 State */
19007 uint16_t:3;
19008#ifndef USE_FIELD_ALIASES_FR
19009 uint16_t T1_REP:1; /* Timer T1 Repetitive Mode */
19010#else
19011 uint16_t T1REP:1;
19012#endif
19013 uint16_t:1;
19014 uint16_t T1SP:1; /* Timer T1 Stop */
19015 uint16_t T1TR:1; /* Timer T1 Trigger */
19016 uint16_t T1ST:1; /* Timer T1 State */
19017 } B;
19018 } FR_TICCR_16B_tag;
19019
19020 typedef union { /* Timer 1 Cycle Set Register */
19021 uint16_t R;
19022 struct {
19023 uint16_t:2;
19024#ifndef USE_FIELD_ALIASES_FR
19025 uint16_t T1_CYC_VAL:6; /* Timer T1 Cycle Filter Value */
19026#else
19027 uint16_t TI1CYCVAL:1; /* Timer T1 Cycle Filter Value */
19028#endif
19029 uint16_t:2;
19030#ifndef USE_FIELD_ALIASES_FR
19031 uint16_t T1_CYC_MSK:6; /* Timer T1 Cycle Filter Mask */
19032#else
19033 uint16_t TI1CYCMSK:1; /* Timer T1 Cycle Filter Mask */
19034#endif
19035 } B;
19036 } FR_TI1CYSR_16B_tag;
19037
19038 typedef union { /* Timer 1 Macrotick Offset Register */
19039 uint16_t R;
19040 struct {
19041 uint16_t:2;
19042 uint16_t T1_MTOFFSET:14; /* Timer 1 Macrotick Offset */
19043 } B;
19044 } FR_TI1MTOR_16B_tag;
19045
19046 typedef union { /* Timer 2 Configuration Register 0 */
19047 uint16_t R;
19048 struct {
19049 uint16_t:2;
19050 uint16_t T2_CYC_VAL:6; /* Timer T2 Cycle Filter Value */
19051 uint16_t:2;
19052 uint16_t T2_CYC_MSK:6; /* Timer T2 Cycle Filter Mask */
19053 } B;
19054 } FR_TI2CR0_16B_tag;
19055
19056 typedef union { /* Timer 2 Configuration Register 1 */
19057 uint16_t R;
19058 struct {
19059 uint16_t T2_MTCNT:16; /* Timer T2 Macrotick Offset */
19060 } B;
19061 } FR_TI2CR1_16B_tag;
19062
19063 typedef union { /* Slot Status Selection Register */
19064 uint16_t R;
19065 struct {
19066 uint16_t WMD:1; /* Write Mode */
19067 uint16_t:1;
19068 uint16_t SEL:2; /* Selector */
19069 uint16_t:1;
19070 uint16_t SLOTNUMBER:11; /* Slot Number */
19071 } B;
19072 } FR_SSSR_16B_tag;
19073
19074 typedef union { /* Slot Status Counter Condition Register */
19075 uint16_t R;
19076 struct {
19077 uint16_t WMD:1; /* Write Mode */
19078 uint16_t:1;
19079 uint16_t SEL:2; /* Selector */
19080 uint16_t:1;
19081 uint16_t CNTCFG:2; /* Counter Configuration */
19082 uint16_t MCY:1; /* Multi Cycle Selection */
19083 uint16_t VFR:1; /* Valid Frame Restriction */
19084 uint16_t SYF:1; /* Sync Frame Restriction */
19085 uint16_t NUF:1; /* Null Frame Restriction */
19086 uint16_t SUF:1; /* Startup Frame Restriction */
19087 uint16_t STATUSMASK:4; /* Slot Status Mask */
19088 } B;
19089 } FR_SSCCR_16B_tag;
19090
19091 typedef union { /* Slot Status Register0 */
19092 uint16_t R;
19093 struct {
19094 uint16_t VFB:1; /* Valid Frame on Channel B */
19095 uint16_t SYB:1; /* Sync Frame Indicator Channel B */
19096 uint16_t NFB:1; /* Null Frame Indicator Channel B */
19097 uint16_t SUB:1; /* Startup Frame Indicator Channel B */
19098 uint16_t SEB:1; /* Syntax Error on Channel B */
19099 uint16_t CEB:1; /* Content Error on Channel B */
19100 uint16_t BVB:1; /* Boundary Violation on Channel B */
19101 uint16_t TCB:1; /* Transmission Conflict on Channel B */
19102 uint16_t VFA:1; /* Valid Frame on Channel A */
19103 uint16_t SYA:1; /* Sync Frame Indicator Channel A */
19104 uint16_t NFA:1; /* Null Frame Indicator Channel A */
19105 uint16_t SUA:1; /* Startup Frame Indicator Channel A */
19106 uint16_t SEA:1; /* Syntax Error on Channel A */
19107 uint16_t CEA:1; /* Content Error on Channel A */
19108 uint16_t BVA:1; /* Boundary Violation on Channel A */
19109 uint16_t TCA:1; /* Transmission Conflict on Channel A */
19110 } B;
19111 } FR_SSR_16B_tag;
19112
19113
19114
19115 typedef union { /* Slot Status Counter Register0 */
19116 uint16_t R;
19117 struct {
19118 uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */
19119 } B;
19120 } FR_SSCR0_16B_tag;
19121
19122 typedef union { /* Slot Status Counter Register1 */
19123 uint16_t R;
19124 struct {
19125 uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */
19126 } B;
19127 } FR_SSCR1_16B_tag;
19128
19129 typedef union { /* Slot Status Counter Register2 */
19130 uint16_t R;
19131 struct {
19132 uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */
19133 } B;
19134 } FR_SSCR2_16B_tag;
19135
19136 typedef union { /* Slot Status Counter Register3 */
19137 uint16_t R;
19138 struct {
19139 uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */
19140 } B;
19141 } FR_SSCR3_16B_tag;
19142
19143 typedef union { /* MTS A Configuration Register */
19144 uint16_t R;
19145 struct {
19146 uint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */
19147 uint16_t:1;
19148 uint16_t CYCCNTMSK:6; /* Cycle Counter Mask */
19149 uint16_t:2;
19150 uint16_t CYCCNTVAL:6; /* Cycle Counter Value */
19151 } B;
19152 } FR_MTSACFR_16B_tag;
19153
19154 typedef union { /* MTS B Configuration Register */
19155 uint16_t R;
19156 struct {
19157 uint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */
19158 uint16_t:1;
19159 uint16_t CYCCNTMSK:6; /* Cycle Counter Mask */
19160 uint16_t:2;
19161 uint16_t CYCCNTVAL:6; /* Cycle Counter Value */
19162 } B;
19163 } FR_MTSBCFR_16B_tag;
19164
19165 typedef union { /* Receive Shadow Buffer Index Register */
19166 uint16_t R;
19167 struct {
19168 uint16_t WMD:1; /* Write Mode */
19169 uint16_t:1;
19170 uint16_t SEL:2; /* Selector */
19171 uint16_t:5;
19172 uint16_t RSBIDX:7; /* Receive Shadow Buffer Index */
19173 } B;
19174 } FR_RSBIR_16B_tag;
19175
19176 typedef union { /* Receive FIFO Watermark and Selection Register */
19177 uint16_t R;
19178 struct {
19179 uint16_t WM:8; /* Watermark Value */
19180 uint16_t:7;
19181 uint16_t SEL:1; /* Select */
19182 } B;
19183 } FR_RFWMSR_16B_tag;
19184
19185 typedef union { /* Receive FIFO Start Index Register */
19186 uint16_t R;
19187 struct {
19188 uint16_t:6;
19189 uint16_t SIDX:10; /* Start Index */
19190 } B;
19191 } FR_RF_RFSIR_16B_tag;
19192
19193 typedef union { /* Receive FIFO Depth and Size Register */
19194 uint16_t R;
19195 struct {
19196#ifndef USE_FIELD_ALIASES_FR
19197 uint16_t FIFO_DEPTH:8; /* FIFO Depth */
19198#else
19199 uint16_t FIFODEPTH:8; /* deprecated name - please avoid */
19200#endif
19201 uint16_t:1;
19202#ifndef USE_FIELD_ALIASES_FR
19203 uint16_t ENTRY_SIZE:7; /* Entry Size */
19204#else
19205 uint16_t ENTRYSIZE:7; /* deprecated name - please avoid */
19206#endif
19207 } B;
19208 } FR_RFDSR_16B_tag;
19209
19210 typedef union { /* Receive FIFO A Read Index Register */
19211 uint16_t R;
19212 struct {
19213 uint16_t:6;
19214 uint16_t RDIDX:10; /* Read Index */
19215 } B;
19216 } FR_RFARIR_16B_tag;
19217
19218 typedef union { /* Receive FIFO B Read Index Register */
19219 uint16_t R;
19220 struct {
19221 uint16_t:6;
19222 uint16_t RDIDX:10; /* Read Index */
19223 } B;
19224 } FR_RFBRIR_16B_tag;
19225
19226 typedef union { /* Receive FIFO Message ID Acceptance Filter Value Register */
19227 uint16_t R;
19228 struct {
19229 uint16_t MIDAFVAL:16; /* Message ID Acceptance Filter Value */
19230 } B;
19231 } FR_RFMIDAFVR_16B_tag;
19232
19233 typedef union { /* Receive FIFO Message ID Acceptance Filter Mask Register */
19234 uint16_t R;
19235 struct {
19236 uint16_t MIDAFMSK:16; /* Message ID Acceptance Filter Mask */
19237 } B;
19238 } FR_RFMIDAFMR_16B_tag;
19239
19240 typedef union { /* Receive FIFO Frame ID Rejection Filter Value Register */
19241 uint16_t R;
19242 struct {
19243 uint16_t:5;
19244 uint16_t FIDRFVAL:11; /* Frame ID Rejection Filter Value */
19245 } B;
19246 } FR_RFFIDRFVR_16B_tag;
19247
19248 typedef union { /* Receive FIFO Frame ID Rejection Filter Mask Register */
19249 uint16_t R;
19250 struct {
19251 uint16_t:5;
19252 uint16_t FIDRFMSK:11; /* Frame ID Rejection Filter Mask */
19253 } B;
19254 } FR_RFFIDRFMR_16B_tag;
19255
19256 typedef union { /* Receive FIFO Range Filter Configuration Register */
19257 uint16_t R;
19258 struct {
19259 uint16_t WMD:1; /* Write Mode */
19260 uint16_t IBD:1; /* Interval Boundary */
19261 uint16_t SEL:2; /* Filter Selector */
19262 uint16_t:1;
19263 uint16_t SID:11; /* Slot ID */
19264 } B;
19265 } FR_RFRFCFR_16B_tag;
19266
19267 typedef union { /* Receive FIFO Range Filter Control Register */
19268 uint16_t R;
19269 struct {
19270 uint16_t:4;
19271 uint16_t F3MD:1; /* Range Filter 3 Mode */
19272 uint16_t F2MD:1; /* Range Filter 2 Mode */
19273 uint16_t F1MD:1; /* Range Filter 1 Mode */
19274 uint16_t F0MD:1; /* Range Filter 0 Mode */
19275 uint16_t:4;
19276 uint16_t F3EN:1; /* Range Filter 3 Enable */
19277 uint16_t F2EN:1; /* Range Filter 2 Enable */
19278 uint16_t F1EN:1; /* Range Filter 1 Enable */
19279 uint16_t F0EN:1; /* Range Filter 0 Enable */
19280 } B;
19281 } FR_RFRFCTR_16B_tag;
19282
19283 typedef union { /* Last Dynamic Transmit Slot Channel A Register */
19284 uint16_t R;
19285 struct {
19286 uint16_t:5;
19287 uint16_t LASTDYNTXSLOTA:11; /* Last Dynamic Transmission Slot Channel A */
19288 } B;
19289 } FR_LDTXSLAR_16B_tag;
19290
19291 typedef union { /* Last Dynamic Transmit Slot Channel B Register */
19292 uint16_t R;
19293 struct {
19294 uint16_t:5;
19295 uint16_t LASTDYNTXSLOTB:11; /* Last Dynamic Transmission Slot Channel B */
19296 } B;
19297 } FR_LDTXSLBR_16B_tag;
19298
19299 typedef union { /* Protocol Configuration Register 0 */
19300 uint16_t R;
19301 struct {
19302 uint16_t ACTION_POINT_OFFSET:6; /* gdActionPointOffset - 1 */
19303 uint16_t STATIC_SLOT_LENGTH:10; /* gdStaticSlot */
19304 } B;
19305 } FR_PCR0_16B_tag;
19306
19307 typedef union { /* Protocol Configuration Register 1 */
19308 uint16_t R;
19309 struct {
19310 uint16_t:2;
19311 uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; /* gMacroPerCycle - gdStaticSlot */
19312 } B;
19313 } FR_PCR1_16B_tag;
19314
19315 typedef union { /* Protocol Configuration Register 2 */
19316 uint16_t R;
19317 struct {
19318 uint16_t MINISLOT_AFTER_ACTION_POINT:6; /* gdMinislot - gdMinislotActionPointOffset - 1 */
19319 uint16_t NUMBER_OF_STATIC_SLOTS:10; /* gNumberOfStaticSlots */
19320 } B;
19321 } FR_PCR2_16B_tag;
19322
19323 typedef union { /* Protocol Configuration Register 3 */
19324 uint16_t R;
19325 struct {
19326 uint16_t WAKEUP_SYMBOL_RX_LOW:6; /* gdWakeupSymbolRxLow */
19327#ifndef USE_FIELD_ALIASES_FR
19328 uint16_t MINISLOT_ACTION_POINT_OFFSET_4_0:5; /* gdMinislotActionPointOffset - 1 */
19329#else
19330 uint16_t MINISLOT_ACTION_POINT_OFFSET:5; /* deprecated name - please avoid */
19331#endif
19332 uint16_t COLDSTART_ATTEMPTS:5; /* gColdstartAttempts */
19333 } B;
19334 } FR_PCR3_16B_tag;
19335
19336 typedef union { /* Protocol Configuration Register 4 */
19337 uint16_t R;
19338 struct {
19339 uint16_t CAS_RX_LOW_MAX:7; /* gdCASRxLowMax - 1 */
19340 uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; /* gdWakeupSymbolRxWindow */
19341 } B;
19342 } FR_PCR4_16B_tag;
19343
19344 typedef union { /* Protocol Configuration Register 5 */
19345 uint16_t R;
19346 struct {
19347 uint16_t TSS_TRANSMITTER:4; /* gdTSSTransmitter */
19348 uint16_t WAKEUP_SYMBOL_TX_LOW:6; /* gdWakeupSymbolTxLow */
19349 uint16_t WAKEUP_SYMBOL_RX_IDLE:6; /* gdWakeupSymbolRxIdle */
19350 } B;
19351 } FR_PCR5_16B_tag;
19352
19353 typedef union { /* Protocol Configuration Register 6 */
19354 uint16_t R;
19355 struct {
19356 uint16_t:1;
19357 uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; /* gdSymbolWindow - gdActionPointOffset - 1 */
19358 uint16_t MACRO_INITIAL_OFFSET_A:7; /* pMacroInitialOffset[A] */
19359 } B;
19360 } FR_PCR6_16B_tag;
19361
19362 typedef union { /* Protocol Configuration Register 7 */
19363 uint16_t R;
19364 struct {
19365 uint16_t DECODING_CORRECTION_B:9; /* pDecodingCorrection + pDelayCompensation[B] + 2 */
19366 uint16_t MICRO_PER_MACRO_NOM_HALF:7; /* round(pMicroPerMacroNom / 2) */
19367 } B;
19368 } FR_PCR7_16B_tag;
19369
19370 typedef union { /* Protocol Configuration Register 8 */
19371 uint16_t R;
19372 struct {
19373 uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; /* gMaxWithoutClockCorrectionFatal */
19374 uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; /* gMaxWithoutClockCorrectionPassive */
19375 uint16_t WAKEUP_SYMBOL_TX_IDLE:8; /* gdWakeupSymbolTxIdle */
19376 } B;
19377 } FR_PCR8_16B_tag;
19378
19379 typedef union { /* Protocol Configuration Register 9 */
19380 uint16_t R;
19381 struct {
19382 uint16_t MINISLOT_EXISTS:1; /* gNumberOfMinislots!=0 */
19383 uint16_t SYMBOL_WINDOW_EXISTS:1; /* gdSymbolWindow!=0 */
19384 uint16_t OFFSET_CORRECTION_OUT:14; /* pOffsetCorrectionOut */
19385 } B;
19386 } FR_PCR9_16B_tag;
19387
19388 typedef union { /* Protocol Configuration Register 10 */
19389 uint16_t R;
19390 struct {
19391 uint16_t SINGLE_SLOT_ENABLED:1; /* pSingleSlotEnabled */
19392 uint16_t WAKEUP_CHANNEL:1; /* pWakeupChannel */
19393 uint16_t MACRO_PER_CYCLE:14; /* pMicroPerCycle */
19394 } B;
19395 } FR_PCR10_16B_tag;
19396
19397 typedef union { /* Protocol Configuration Register 11 */
19398 uint16_t R;
19399 struct {
19400 uint16_t KEY_SLOT_USED_FOR_STARTUP:1; /* pKeySlotUsedForStartup */
19401 uint16_t KEY_SLOT_USED_FOR_SYNC:1; /* pKeySlotUsedForSync */
19402 uint16_t OFFSET_CORRECTION_START:14; /* gOffsetCorrectionStart */
19403 } B;
19404 } FR_PCR11_16B_tag;
19405
19406 typedef union { /* Protocol Configuration Register 12 */
19407 uint16_t R;
19408 struct {
19409 uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; /* pAllowPassiveToActive */
19410 uint16_t KEY_SLOT_HEADER_CRC:11; /* header CRC for key slot */
19411 } B;
19412 } FR_PCR12_16B_tag;
19413
19414 typedef union { /* Protocol Configuration Register 13 */
19415 uint16_t R;
19416 struct {
19417 uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; /* max(gdActionPointOffset,gdMinislotActionPointOffset) - 1 */
19418 uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; /* gdStaticSlot - gdActionPointOffset - 1 */
19419 } B;
19420 } FR_PCR13_16B_tag;
19421
19422 typedef union { /* Protocol Configuration Register 14 */
19423 uint16_t R;
19424 struct {
19425 uint16_t RATE_CORRECTION_OUT:11; /* pRateCorrectionOut */
19426#ifndef USE_FIELD_ALIASES_FR
19427 uint16_t LISTEN_TIMEOUT_20_16:5; /* pdListenTimeout - 1 */
19428#else
19429 uint16_t LISTEN_TIMEOUT_H:5; /* deprecated name - please avoid */
19430#endif
19431 } B;
19432 } FR_PCR14_16B_tag;
19433
19434 typedef union { /* Protocol Configuration Register 15 */
19435 uint16_t R;
19436 struct {
19437#ifndef USE_FIELD_ALIASES_FR
19438 uint16_t LISTEN_TIMEOUT_15_0:16; /* pdListenTimeout - 1 */
19439#else
19440 uint16_t LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */
19441#endif
19442 } B;
19443 } FR_PCR15_16B_tag;
19444
19445 typedef union { /* Protocol Configuration Register 16 */
19446 uint16_t R;
19447 struct {
19448 uint16_t MACRO_INITIAL_OFFSET_B:7; /* pMacroInitialOffset[B] */
19449#ifndef USE_FIELD_ALIASES_FR
19450 uint16_t NOISE_LISTEN_TIMEOUT_24_16:9; /* (gListenNoise * pdListenTimeout) - 1 */
19451#else
19452 uint16_t NOISE_LISTEN_TIMEOUT_H:9; /* deprecated name - please avoid */
19453#endif
19454 } B;
19455 } FR_PCR16_16B_tag;
19456
19457 typedef union { /* Protocol Configuration Register 17 */
19458 uint16_t R;
19459 struct {
19460#ifndef USE_FIELD_ALIASES_FR
19461 uint16_t NOISE_LISTEN_TIMEOUT_15_0:16; /* (gListenNoise * pdListenTimeout) - 1 */
19462#else
19463 uint16_t NOISE_LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */
19464#endif
19465 } B;
19466 } FR_PCR17_16B_tag;
19467
19468 typedef union { /* Protocol Configuration Register 18 */
19469 uint16_t R;
19470 struct {
19471 uint16_t WAKEUP_PATTERN:6; /* pWakeupPattern */
19472 uint16_t KEY_SLOT_ID:10; /* pKeySlotId */
19473 } B;
19474 } FR_PCR18_16B_tag;
19475
19476 typedef union { /* Protocol Configuration Register 19 */
19477 uint16_t R;
19478 struct {
19479 uint16_t DECODING_CORRECTION_A:9; /* pDecodingCorrection + pDelayCompensation[A] + 2 */
19480 uint16_t PAYLOAD_LENGTH_STATIC:7; /* gPayloadLengthStatic */
19481 } B;
19482 } FR_PCR19_16B_tag;
19483
19484 typedef union { /* Protocol Configuration Register 20 */
19485 uint16_t R;
19486 struct {
19487 uint16_t MICRO_INITIAL_OFFSET_B:8; /* pMicroInitialOffset[B] */
19488 uint16_t MICRO_INITIAL_OFFSET_A:8; /* pMicroInitialOffset[A] */
19489 } B;
19490 } FR_PCR20_16B_tag;
19491
19492 typedef union { /* Protocol Configuration Register 21 */
19493 uint16_t R;
19494 struct {
19495 uint16_t EXTERN_RATE_CORRECTION:3; /* pExternRateCorrection */
19496 uint16_t LATEST_TX:13; /* gNumberOfMinislots - pLatestTx */
19497 } B;
19498 } FR_PCR21_16B_tag;
19499
19500 typedef union { /* Protocol Configuration Register 22 */
19501 uint16_t R;
19502 struct {
19503 uint16_t R:1; /* Reserved bit */
19504#ifndef USE_FIELD_ALIASES_FR
19505 uint16_t COMP_ACCEPTED_STARRUP_RANGE_A:11; /* pdAcceptedStartupRange - pDelayCompensationChA */
19506#else
19507 uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; /* deprecated name - please avoid */
19508#endif
19509#ifndef USE_FIELD_ALIASES_FR
19510 uint16_t MICRO_PER_CYCLE_19_16:4; /* gMicroPerCycle */
19511#else
19512 uint16_t MICRO_PER_CYCLE_H:4; /* deprecated name - please avoid */
19513#endif
19514 } B;
19515 } FR_PCR22_16B_tag;
19516
19517 typedef union { /* Protocol Configuration Register 23 */
19518 uint16_t R;
19519 struct {
19520#ifndef USE_FIELD_ALIASES_FR
19521 uint16_t MICRO_PER_CYCLE_15_0:16; /* pMicroPerCycle */
19522#else
19523 uint16_t micro_per_cycle_l:16; /* deprecated name - please avoid */
19524#endif
19525 } B;
19526 } FR_PCR23_16B_tag;
19527
19528 typedef union { /* Protocol Configuration Register 24 */
19529 uint16_t R;
19530 struct {
19531 uint16_t CLUSTER_DRIFT_DAMPING:5; /* pClusterDriftDamping */
19532 uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; /* pPayloadLengthDynMax */
19533#ifndef USE_FIELD_ALIASES_FR
19534 uint16_t MICRO_PER_CYCLE_MIN_19_16:4; /* pMicroPerCycle - pdMaxDrift */
19535#else
19536 uint16_t MICRO_PER_CYCLE_MIN_H:4; /* deprecated name - please avoid */
19537#endif
19538 } B;
19539 } FR_PCR24_16B_tag;
19540
19541 typedef union { /* Protocol Configuration Register 25 */
19542 uint16_t R;
19543 struct {
19544#ifndef USE_FIELD_ALIASES_FR
19545 uint16_t MICRO_PER_CYCLE_MIN_15_0:16; /* pMicroPerCycle - pdMaxDrift */
19546#else
19547 uint16_t MICRO_PER_CYCLE_MIN_L:16; /* deprecated name - please avoid */
19548#endif
19549 } B;
19550 } FR_PCR25_16B_tag;
19551
19552 typedef union { /* Protocol Configuration Register 26 */
19553 uint16_t R;
19554 struct {
19555 uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; /* pAllowHaltDueToClock */
19556 uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; /* pdAcceptedStartupRange - pDelayCompensationChB */
19557#ifndef USE_FIELD_ALIASES_FR
19558 uint16_t MICRO_PER_CYCLE_MAX_19_16:4; /* pMicroPerCycle + pdMaxDrift */
19559#else
19560 uint16_t MICRO_PER_CYCLE_MAX_H:4; /* deprecated name - please avoid */
19561#endif
19562 } B;
19563 } FR_PCR26_16B_tag;
19564
19565 typedef union { /* Protocol Configuration Register 27 */
19566 uint16_t R;
19567 struct {
19568#ifndef USE_FIELD_ALIASES_FR
19569 uint16_t MICRO_PER_CYCLE_MAX_15_0:16; /* pMicroPerCycle + pdMaxDrift */
19570#else
19571 uint16_t MICRO_PER_CYCLE_MAX_L:16; /* deprecated name - please avoid */
19572#endif
19573 } B;
19574 } FR_PCR27_16B_tag;
19575
19576 typedef union { /* Protocol Configuration Register 28 */
19577 uint16_t R;
19578 struct {
19579 uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; /* gdDynamicSlotIdlePhase */
19580 uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; /* gMacroPerCycle - gOffsetCorrectionStart */
19581 } B;
19582 } FR_PCR28_16B_tag;
19583
19584 typedef union { /* Protocol Configuration Register 29 */
19585 uint16_t R;
19586 struct {
19587 uint16_t EXTERN_OFFSET_CORRECTION:3; /* pExternOffsetCorrection */
19588 uint16_t MINISLOTS_MAX:13; /* gNumberOfMinislots - 1 */
19589 } B;
19590 } FR_PCR29_16B_tag;
19591
19592 typedef union { /* Protocol Configuration Register 30 */
19593 uint16_t R;
19594 struct {
19595 uint16_t:12;
19596 uint16_t SYNC_NODE_MAX:4; /* gSyncNodeMax */
19597 } B;
19598 } FR_PCR30_16B_tag;
19599
19600 typedef union { /* Receive FIFO System Memory Base Address High Register */
19601 uint16_t R;
19602 struct {
19603 uint16_t SMBA_31_16:16; /* System Memory Base Address */
19604 } B;
19605 } FR_RFSYMBHADR_16B_tag;
19606
19607 typedef union { /* Receive FIFO System Memory Base Address Low Register */
19608 uint16_t R;
19609 struct {
19610 uint16_t:4;
19611 uint16_t SMBA_15_4:12; /* System Memory Base Address */
19612 } B;
19613 } FR_RFSYMBLADR_16B_tag;
19614
19615 typedef union { /* Receive FIFO Periodic Timer Register */
19616 uint16_t R;
19617 struct {
19618 uint16_t:2;
19619 uint16_t PTD:14; /* Periodic Timer Duration */
19620 } B;
19621 } FR_RFPTR_16B_tag;
19622
19623 typedef union { /* Receive FIFO Fill Level and Pop Count Register */
19624 uint16_t R;
19625 struct {
19626 uint16_t FLPCB:8; /* Fill Level and Pop Count Channel B */
19627 uint16_t FLPCA:8; /* Fill Level and Pop Count Channel A */
19628 } B;
19629 } FR_RFFLPCR_16B_tag;
19630
19631 typedef union { /* ECC Error Interrupt Flag and Enable Register */
19632 uint16_t R;
19633 struct {
19634 uint16_t LRNE_OF:1; /* LRAM Non-Corrected Error Overflow Flag */
19635 uint16_t LRCE_OF:1; /* LRAM Corrected Error Overflow Flag */
19636 uint16_t DRNE_OF:1; /* DRAM Non-Corrected Error Overflow Flag */
19637 uint16_t DRCE_OF:1; /* DRAM Corrected Error Overflow Flag */
19638 uint16_t LRNE_IF:1; /* LRAM Non-Corrected Error Interrupt Flag */
19639 uint16_t LRCE_IF:1; /* LRAM Corrected Error Interrupt Flag */
19640 uint16_t DRNE_IF:1; /* DRAM Non-Corrected Error Interrupt Flag */
19641 uint16_t DRCE_IF:1; /* DRAM Corrected Error Interrupt Flag */
19642 uint16_t:4;
19643 uint16_t LRNE_IE:1; /* LRAM Non-Corrected Error Interrupt Enable */
19644 uint16_t LRCE_IE:1; /* LRAM Corrected Error Interrupt Enable */
19645 uint16_t DRNE_IE:1; /* DRAM Non-Corrected Error Interrupt Enable */
19646 uint16_t DRCE_IE:1; /* DRAM Corrected Error Interrupt Enable */
19647 } B;
19648 } FR_EEIFER_16B_tag;
19649
19650 typedef union { /* ECC Error Report and Injection Control Register */
19651 uint16_t R;
19652 struct {
19653 uint16_t BSY:1; /* Register Update Busy */
19654 uint16_t:5;
19655 uint16_t ERS:2; /* Error Report Select */
19656 uint16_t:3;
19657 uint16_t ERM:1; /* Error Report Mode */
19658 uint16_t:2;
19659 uint16_t EIM:1; /* Error Injection Mode */
19660 uint16_t EIE:1; /* Error Injection Enable */
19661 } B;
19662 } FR_EERICR_16B_tag;
19663
19664 typedef union { /* ECC Error Report Adress Register */
19665 uint16_t R;
19666 struct {
19667 uint16_t MID:1; /* Memory Identifier */
19668 uint16_t BANK:3; /* Memory Bank */
19669 uint16_t ADDR:12; /* Memory Address */
19670 } B;
19671 } FR_EERAR_16B_tag;
19672
19673 typedef union { /* ECC Error Report Data Register */
19674 uint16_t R;
19675 struct {
19676 uint16_t DATA:16; /* Data */
19677 } B;
19678 } FR_EERDR_16B_tag;
19679
19680 typedef union { /* ECC Error Report Code Register */
19681 uint16_t R;
19682 struct {
19683 uint16_t:11;
19684 uint16_t CODE:5; /* Code */
19685 } B;
19686 } FR_EERCR_16B_tag;
19687
19688 typedef union { /* ECC Error Injection Address Register */
19689 uint16_t R;
19690 struct {
19691 uint16_t MID:1; /* Memory Identifier */
19692 uint16_t BANK:3; /* Memory Bank */
19693 uint16_t ADDR:12; /* Memory Address */
19694 } B;
19695 } FR_EEIAR_16B_tag;
19696
19697 typedef union { /* ECC Error Injection Data Register */
19698 uint16_t R;
19699 struct {
19700 uint16_t DATA:16; /* Data */
19701 } B;
19702 } FR_EEIDR_16B_tag;
19703
19704 typedef union { /* ECC Error Injection Code Register */
19705 uint16_t R;
19706 struct {
19707 uint16_t:11;
19708 uint16_t CODE:5; /* Code */
19709 } B;
19710 } FR_EEICR_16B_tag;
19711
19712
19713 /* Register layout for all registers MBCCSR... */
19714
19715 typedef union { /* Message Buffer Configuration Control Status Register */
19716 uint16_t R;
19717 struct {
19718 uint16_t:1;
19719 uint16_t MCM:1; /* Message Buffer Commit Mode */
19720 uint16_t MBT:1; /* Message Buffer Type */
19721 uint16_t MTD:1; /* Message Buffer Transfer Direction */
19722 uint16_t CMT:1; /* Commit for Transmission */
19723 uint16_t EDT:1; /* Enable/Disable Trigger */
19724 uint16_t LCKT:1; /* Lock/Unlock Trigger */
19725 uint16_t MBIE:1; /* Message Buffer Interrupt Enable */
19726 uint16_t:3;
19727 uint16_t DUP:1; /* Data Updated */
19728 uint16_t DVAL:1; /* DataValid */
19729 uint16_t EDS:1; /* Enable/Disable Status */
19730 uint16_t LCKS:1; /* LockStatus */
19731 uint16_t MBIF:1; /* Message Buffer Interrupt Flag */
19732 } B;
19733 } FR_MBCCSR_16B_tag;
19734
19735
19736 /* Register layout for all registers MBCCFR... */
19737
19738 typedef union { /* Message Buffer Cycle Counter Filter Register */
19739 uint16_t R;
19740 struct {
19741 uint16_t MTM:1; /* Message Buffer Transmission Mode */
19742#ifndef USE_FIELD_ALIASES_FR
19743 uint16_t CHA:1; /* Channel Assignment */
19744#else
19745 uint16_t CHNLA:1; /* deprecated name - please avoid */
19746#endif
19747#ifndef USE_FIELD_ALIASES_FR
19748 uint16_t CHB:1; /* Channel Assignment */
19749#else
19750 uint16_t CHNLB:1; /* deprecated name - please avoid */
19751#endif
19752 uint16_t CCFE:1; /* Cycle Counter Filtering Enable */
19753 uint16_t CCFMSK:6; /* Cycle Counter Filtering Mask */
19754 uint16_t CCFVAL:6; /* Cycle Counter Filtering Value */
19755 } B;
19756 } FR_MBCCFR_16B_tag;
19757
19758
19759 /* Register layout for all registers MBFIDR... */
19760
19761 typedef union { /* Message Buffer Frame ID Register */
19762 uint16_t R;
19763 struct {
19764 uint16_t:5;
19765 uint16_t FID:11; /* Frame ID */
19766 } B;
19767 } FR_MBFIDR_16B_tag;
19768
19769
19770 /* Register layout for all registers MBIDXR... */
19771
19772 typedef union { /* Message Buffer Index Register */
19773 uint16_t R;
19774 struct {
19775 uint16_t:9;
19776 uint16_t MBIDX:7; /* Message Buffer Index */
19777 } B;
19778 } FR_MBIDXR_16B_tag;
19779
19780
19781 /* Register layout for generated register(s) NMVR... */
19782
19783 typedef union { /* */
19784 uint16_t R;
19785 } FR_NMVR_16B_tag;
19786
19787
19788
19789
19790 /* Register layout for generated register(s) SSCR... */
19791
19792 typedef union { /* */
19793 uint16_t R;
19794 } FR_SSCR_16B_tag;
19795
19796
19797 typedef struct FR_MB_struct_tag {
19798
19799 /* Message Buffer Configuration Control Status Register */
19800 FR_MBCCSR_16B_tag MBCCSR; /* relative offset: 0x0000 */
19801 /* Message Buffer Cycle Counter Filter Register */
19802 FR_MBCCFR_16B_tag MBCCFR; /* relative offset: 0x0002 */
19803 /* Message Buffer Frame ID Register */
19804 FR_MBFIDR_16B_tag MBFIDR; /* relative offset: 0x0004 */
19805 /* Message Buffer Index Register */
19806 FR_MBIDXR_16B_tag MBIDXR; /* relative offset: 0x0006 */
19807
19808 } FR_MB_tag;
19809
19810
19811 typedef struct FR_struct_tag { /* start of FR_tag */
19812 /* Module Version Number */
19813 FR_MVR_16B_tag MVR; /* offset: 0x0000 size: 16 bit */
19814 /* Module Configuration Register */
19815 FR_MCR_16B_tag MCR; /* offset: 0x0002 size: 16 bit */
19816 union {
19817 FR_SYMBADHR_16B_tag SYSBADHR; /* deprecated - please avoid */
19818
19819 /* SYSTEM MEMORY BASE ADD HIGH REG */
19820 FR_SYMBADHR_16B_tag SYMBADHR; /* offset: 0x0004 size: 16 bit */
19821
19822 };
19823 union {
19824 FR_SYMBADLR_16B_tag SYSBADLR; /* deprecated - please avoid */
19825
19826 /* SYSTEM MEMORY BASE ADD LOW REG */
19827 FR_SYMBADLR_16B_tag SYMBADLR; /* offset: 0x0006 size: 16 bit */
19828
19829 };
19830 /* STROBE SIGNAL CONTROL REGISTER */
19831 FR_STBSCR_16B_tag STBSCR; /* offset: 0x0008 size: 16 bit */
19832 int8_t FR_reserved_000A[2];
19833 /* MESSAGE BUFFER DATA SIZE REGISTER */
19834 FR_MBDSR_16B_tag MBDSR; /* offset: 0x000C size: 16 bit */
19835 /* MESS. BUFFER SEG. SIZE & UTILISATION REG */
19836 FR_MBSSUTR_16B_tag MBSSUTR; /* offset: 0x000E size: 16 bit */
19837 union {
19838 /* PE DRAM ACCESS REGISTER */
19839 FR_PEDRAR_16B_tag PEDRAR; /* offset: 0x0010 size: 16 bit */
19840
19841 FR_PEDRAR_16B_tag PADR; /* deprecated - please avoid */
19842
19843 };
19844 union {
19845 /* PE DRAM DATA REGISTER */
19846 FR_PEDRDR_16B_tag PEDRDR; /* offset: 0x0012 size: 16 bit */
19847
19848 FR_PEDRDR_16B_tag PDAR; /* deprecated - please avoid */
19849
19850 };
19851 /* PROTOCOL OPERATION CONTROL REG */
19852 FR_POCR_16B_tag POCR; /* offset: 0x0014 size: 16 bit */
19853 /* GLOBAL INTERRUPT FLAG & ENABLE REG */
19854 FR_GIFER_16B_tag GIFER; /* offset: 0x0016 size: 16 bit */
19855 /* PROTOCOL INTERRUPT FLAG REGISTER 0 */
19856 FR_PIFR0_16B_tag PIFR0; /* offset: 0x0018 size: 16 bit */
19857 /* PROTOCOL INTERRUPT FLAG REGISTER 1 */
19858 FR_PIFR1_16B_tag PIFR1; /* offset: 0x001A size: 16 bit */
19859 /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */
19860 FR_PIER0_16B_tag PIER0; /* offset: 0x001C size: 16 bit */
19861 /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */
19862 FR_PIER1_16B_tag PIER1; /* offset: 0x001E size: 16 bit */
19863 /* CHI ERROR FLAG REGISTER */
19864 FR_CHIERFR_16B_tag CHIERFR; /* offset: 0x0020 size: 16 bit */
19865 /* Message Buffer Interrupt Vector Register */
19866 FR_MBIVEC_16B_tag MBIVEC; /* offset: 0x0022 size: 16 bit */
19867 /* Channel A Status Error Counter Register */
19868 FR_CASERCR_16B_tag CASERCR; /* offset: 0x0024 size: 16 bit */
19869 /* Channel B Status Error Counter Register */
19870 FR_CBSERCR_16B_tag CBSERCR; /* offset: 0x0026 size: 16 bit */
19871 /* Protocol Status Register 0 */
19872 FR_PSR0_16B_tag PSR0; /* offset: 0x0028 size: 16 bit */
19873 /* Protocol Status Register 1 */
19874 FR_PSR1_16B_tag PSR1; /* offset: 0x002A size: 16 bit */
19875 /* Protocol Status Register 2 */
19876 FR_PSR2_16B_tag PSR2; /* offset: 0x002C size: 16 bit */
19877 /* Protocol Status Register 3 */
19878 FR_PSR3_16B_tag PSR3; /* offset: 0x002E size: 16 bit */
19879 /* Macrotick Counter Register */
19880 FR_MTCTR_16B_tag MTCTR; /* offset: 0x0030 size: 16 bit */
19881 /* Cycle Counter Register */
19882 FR_CYCTR_16B_tag CYCTR; /* offset: 0x0032 size: 16 bit */
19883 /* Slot Counter Channel A Register */
19884 FR_SLTCTAR_16B_tag SLTCTAR; /* offset: 0x0034 size: 16 bit */
19885 /* Slot Counter Channel B Register */
19886 FR_SLTCTBR_16B_tag SLTCTBR; /* offset: 0x0036 size: 16 bit */
19887 /* Rate Correction Value Register */
19888 FR_RTCORVR_16B_tag RTCORVR; /* offset: 0x0038 size: 16 bit */
19889 /* Offset Correction Value Register */
19890 FR_OFCORVR_16B_tag OFCORVR; /* offset: 0x003A size: 16 bit */
19891 union {
19892 FR_CIFR_16B_tag CIFRR; /* deprecated - please avoid */
19893
19894 /* Combined Interrupt Flag Register */
19895 FR_CIFR_16B_tag CIFR; /* offset: 0x003C size: 16 bit */
19896
19897 };
19898 /* System Memory Access Time-Out Register */
19899 FR_SYMATOR_16B_tag SYMATOR; /* offset: 0x003E size: 16 bit */
19900 /* Sync Frame Counter Register */
19901 FR_SFCNTR_16B_tag SFCNTR; /* offset: 0x0040 size: 16 bit */
19902 /* Sync Frame Table Offset Register */
19903 FR_SFTOR_16B_tag SFTOR; /* offset: 0x0042 size: 16 bit */
19904 /* Sync Frame Table Configuration, Control, Status Register */
19905 FR_SFTCCSR_16B_tag SFTCCSR; /* offset: 0x0044 size: 16 bit */
19906 /* Sync Frame ID Rejection Filter */
19907 FR_SFIDRFR_16B_tag SFIDRFR; /* offset: 0x0046 size: 16 bit */
19908 /* Sync Frame ID Acceptance Filter Value Register */
19909 FR_SFIDAFVR_16B_tag SFIDAFVR; /* offset: 0x0048 size: 16 bit */
19910 /* Sync Frame ID Acceptance Filter Mask Register */
19911 FR_SFIDAFMR_16B_tag SFIDAFMR; /* offset: 0x004A size: 16 bit */
19912 union {
19913 FR_NMVR_16B_tag NMVR[6]; /* offset: 0x004C (0x0002 x 6) */
19914
19915 struct {
19916 /* Network Management Vector Register0 */
19917 FR_NMVR0_16B_tag NMVR0; /* offset: 0x004C size: 16 bit */
19918 /* Network Management Vector Register1 */
19919 FR_NMVR1_16B_tag NMVR1; /* offset: 0x004E size: 16 bit */
19920 /* Network Management Vector Register2 */
19921 FR_NMVR2_16B_tag NMVR2; /* offset: 0x0050 size: 16 bit */
19922 /* Network Management Vector Register3 */
19923 FR_NMVR3_16B_tag NMVR3; /* offset: 0x0052 size: 16 bit */
19924 /* Network Management Vector Register4 */
19925 FR_NMVR4_16B_tag NMVR4; /* offset: 0x0054 size: 16 bit */
19926 /* Network Management Vector Register5 */
19927 FR_NMVR5_16B_tag NMVR5; /* offset: 0x0056 size: 16 bit */
19928 };
19929
19930 };
19931 /* Network Management Vector Length Register */
19932 FR_NMVLR_16B_tag NMVLR; /* offset: 0x0058 size: 16 bit */
19933 /* Timer Configuration and Control Register */
19934 FR_TICCR_16B_tag TICCR; /* offset: 0x005A size: 16 bit */
19935 /* Timer 1 Cycle Set Register */
19936 FR_TI1CYSR_16B_tag TI1CYSR; /* offset: 0x005C size: 16 bit */
19937 union {
19938 /* Timer 1 Macrotick Offset Register */
19939 FR_TI1MTOR_16B_tag TI1MTOR; /* offset: 0x005E size: 16 bit */
19940
19941 FR_TI1MTOR_16B_tag T1MTOR; /* deprecated - please avoid */
19942
19943 };
19944 /* Timer 2 Configuration Register 0 */
19945 FR_TI2CR0_16B_tag TI2CR0; /* offset: 0x0060 size: 16 bit */
19946 /* Timer 2 Configuration Register 1 */
19947 FR_TI2CR1_16B_tag TI2CR1; /* offset: 0x0062 size: 16 bit */
19948 /* Slot Status Selection Register */
19949 FR_SSSR_16B_tag SSSR; /* offset: 0x0064 size: 16 bit */
19950 /* Slot Status Counter Condition Register */
19951 FR_SSCCR_16B_tag SSCCR; /* offset: 0x0066 size: 16 bit */
19952 union {
19953 FR_SSR_16B_tag SSR[8]; /* offset: 0x0068 (0x0002 x 8) */
19954
19955 struct {
19956 /* Slot Status Register0 */
19957 FR_SSR_16B_tag SSR0; /* offset: 0x0068 size: 16 bit */
19958 /* Slot Status Register1 */
19959 FR_SSR_16B_tag SSR1; /* offset: 0x006A size: 16 bit */
19960 /* Slot Status Register2 */
19961 FR_SSR_16B_tag SSR2; /* offset: 0x006C size: 16 bit */
19962 /* Slot Status Register3 */
19963 FR_SSR_16B_tag SSR3; /* offset: 0x006E size: 16 bit */
19964 /* Slot Status Register4 */
19965 FR_SSR_16B_tag SSR4; /* offset: 0x0070 size: 16 bit */
19966 /* Slot Status Register5 */
19967 FR_SSR_16B_tag SSR5; /* offset: 0x0072 size: 16 bit */
19968 /* Slot Status Register6 */
19969 FR_SSR_16B_tag SSR6; /* offset: 0x0074 size: 16 bit */
19970 /* Slot Status Register7 */
19971 FR_SSR_16B_tag SSR7; /* offset: 0x0076 size: 16 bit */
19972 };
19973
19974 };
19975 union {
19976 FR_SSCR_16B_tag SSCR[4]; /* offset: 0x0078 (0x0002 x 4) */
19977
19978 struct {
19979 /* Slot Status Counter Register0 */
19980 FR_SSCR0_16B_tag SSCR0; /* offset: 0x0078 size: 16 bit */
19981 /* Slot Status Counter Register1 */
19982 FR_SSCR1_16B_tag SSCR1; /* offset: 0x007A size: 16 bit */
19983 /* Slot Status Counter Register2 */
19984 FR_SSCR2_16B_tag SSCR2; /* offset: 0x007C size: 16 bit */
19985 /* Slot Status Counter Register3 */
19986 FR_SSCR3_16B_tag SSCR3; /* offset: 0x007E size: 16 bit */
19987 };
19988
19989 };
19990 /* MTS A Configuration Register */
19991 FR_MTSACFR_16B_tag MTSACFR; /* offset: 0x0080 size: 16 bit */
19992 /* MTS B Configuration Register */
19993 FR_MTSBCFR_16B_tag MTSBCFR; /* offset: 0x0082 size: 16 bit */
19994 /* Receive Shadow Buffer Index Register */
19995 FR_RSBIR_16B_tag RSBIR; /* offset: 0x0084 size: 16 bit */
19996 union {
19997 /* Receive FIFO Watermark and Selection Register */
19998 FR_RFWMSR_16B_tag RFWMSR; /* offset: 0x0086 size: 16 bit */
19999
20000 FR_RFWMSR_16B_tag RFSR; /* deprecated - please avoid */
20001
20002 };
20003 union {
20004 FR_RF_RFSIR_16B_tag RFSIR; /* deprecated - please avoid */
20005
20006 /* Receive FIFO Start Index Register */
20007 FR_RF_RFSIR_16B_tag RF_RFSIR; /* offset: 0x0088 size: 16 bit */
20008
20009 };
20010 /* Receive FIFO Depth and Size Register */
20011 FR_RFDSR_16B_tag RFDSR; /* offset: 0x008A size: 16 bit */
20012 /* Receive FIFO A Read Index Register */
20013 FR_RFARIR_16B_tag RFARIR; /* offset: 0x008C size: 16 bit */
20014 /* Receive FIFO B Read Index Register */
20015 FR_RFBRIR_16B_tag RFBRIR; /* offset: 0x008E size: 16 bit */
20016 /* Receive FIFO Message ID Acceptance Filter Value Register */
20017 FR_RFMIDAFVR_16B_tag RFMIDAFVR; /* offset: 0x0090 size: 16 bit */
20018 union {
20019 /* Receive FIFO Message ID Acceptance Filter Mask Register */
20020 FR_RFMIDAFMR_16B_tag RFMIDAFMR; /* offset: 0x0092 size: 16 bit */
20021
20022 FR_RFMIDAFMR_16B_tag RFMIAFMR; /* deprecated - please avoid */
20023
20024 };
20025 /* Receive FIFO Frame ID Rejection Filter Value Register */
20026 FR_RFFIDRFVR_16B_tag RFFIDRFVR; /* offset: 0x0094 size: 16 bit */
20027 /* Receive FIFO Frame ID Rejection Filter Mask Register */
20028 FR_RFFIDRFMR_16B_tag RFFIDRFMR; /* offset: 0x0096 size: 16 bit */
20029 /* Receive FIFO Range Filter Configuration Register */
20030 FR_RFRFCFR_16B_tag RFRFCFR; /* offset: 0x0098 size: 16 bit */
20031 /* Receive FIFO Range Filter Control Register */
20032 FR_RFRFCTR_16B_tag RFRFCTR; /* offset: 0x009A size: 16 bit */
20033 /* Last Dynamic Transmit Slot Channel A Register */
20034 FR_LDTXSLAR_16B_tag LDTXSLAR; /* offset: 0x009C size: 16 bit */
20035 /* Last Dynamic Transmit Slot Channel B Register */
20036 FR_LDTXSLBR_16B_tag LDTXSLBR; /* offset: 0x009E size: 16 bit */
20037 /* Protocol Configuration Register 0 */
20038 FR_PCR0_16B_tag PCR0; /* offset: 0x00A0 size: 16 bit */
20039 /* Protocol Configuration Register 1 */
20040 FR_PCR1_16B_tag PCR1; /* offset: 0x00A2 size: 16 bit */
20041 /* Protocol Configuration Register 2 */
20042 FR_PCR2_16B_tag PCR2; /* offset: 0x00A4 size: 16 bit */
20043 /* Protocol Configuration Register 3 */
20044 FR_PCR3_16B_tag PCR3; /* offset: 0x00A6 size: 16 bit */
20045 /* Protocol Configuration Register 4 */
20046 FR_PCR4_16B_tag PCR4; /* offset: 0x00A8 size: 16 bit */
20047 /* Protocol Configuration Register 5 */
20048 FR_PCR5_16B_tag PCR5; /* offset: 0x00AA size: 16 bit */
20049 /* Protocol Configuration Register 6 */
20050 FR_PCR6_16B_tag PCR6; /* offset: 0x00AC size: 16 bit */
20051 /* Protocol Configuration Register 7 */
20052 FR_PCR7_16B_tag PCR7; /* offset: 0x00AE size: 16 bit */
20053 /* Protocol Configuration Register 8 */
20054 FR_PCR8_16B_tag PCR8; /* offset: 0x00B0 size: 16 bit */
20055 /* Protocol Configuration Register 9 */
20056 FR_PCR9_16B_tag PCR9; /* offset: 0x00B2 size: 16 bit */
20057 /* Protocol Configuration Register 10 */
20058 FR_PCR10_16B_tag PCR10; /* offset: 0x00B4 size: 16 bit */
20059 /* Protocol Configuration Register 11 */
20060 FR_PCR11_16B_tag PCR11; /* offset: 0x00B6 size: 16 bit */
20061 /* Protocol Configuration Register 12 */
20062 FR_PCR12_16B_tag PCR12; /* offset: 0x00B8 size: 16 bit */
20063 /* Protocol Configuration Register 13 */
20064 FR_PCR13_16B_tag PCR13; /* offset: 0x00BA size: 16 bit */
20065 /* Protocol Configuration Register 14 */
20066 FR_PCR14_16B_tag PCR14; /* offset: 0x00BC size: 16 bit */
20067 /* Protocol Configuration Register 15 */
20068 FR_PCR15_16B_tag PCR15; /* offset: 0x00BE size: 16 bit */
20069 /* Protocol Configuration Register 16 */
20070 FR_PCR16_16B_tag PCR16; /* offset: 0x00C0 size: 16 bit */
20071 /* Protocol Configuration Register 17 */
20072 FR_PCR17_16B_tag PCR17; /* offset: 0x00C2 size: 16 bit */
20073 /* Protocol Configuration Register 18 */
20074 FR_PCR18_16B_tag PCR18; /* offset: 0x00C4 size: 16 bit */
20075 /* Protocol Configuration Register 19 */
20076 FR_PCR19_16B_tag PCR19; /* offset: 0x00C6 size: 16 bit */
20077 /* Protocol Configuration Register 20 */
20078 FR_PCR20_16B_tag PCR20; /* offset: 0x00C8 size: 16 bit */
20079 /* Protocol Configuration Register 21 */
20080 FR_PCR21_16B_tag PCR21; /* offset: 0x00CA size: 16 bit */
20081 /* Protocol Configuration Register 22 */
20082 FR_PCR22_16B_tag PCR22; /* offset: 0x00CC size: 16 bit */
20083 /* Protocol Configuration Register 23 */
20084 FR_PCR23_16B_tag PCR23; /* offset: 0x00CE size: 16 bit */
20085 /* Protocol Configuration Register 24 */
20086 FR_PCR24_16B_tag PCR24; /* offset: 0x00D0 size: 16 bit */
20087 /* Protocol Configuration Register 25 */
20088 FR_PCR25_16B_tag PCR25; /* offset: 0x00D2 size: 16 bit */
20089 /* Protocol Configuration Register 26 */
20090 FR_PCR26_16B_tag PCR26; /* offset: 0x00D4 size: 16 bit */
20091 /* Protocol Configuration Register 27 */
20092 FR_PCR27_16B_tag PCR27; /* offset: 0x00D6 size: 16 bit */
20093 /* Protocol Configuration Register 28 */
20094 FR_PCR28_16B_tag PCR28; /* offset: 0x00D8 size: 16 bit */
20095 /* Protocol Configuration Register 29 */
20096 FR_PCR29_16B_tag PCR29; /* offset: 0x00DA size: 16 bit */
20097 /* Protocol Configuration Register 30 */
20098 FR_PCR30_16B_tag PCR30; /* offset: 0x00DC size: 16 bit */
20099 int8_t FR_reserved_00DE[10];
20100 /* Receive FIFO System Memory Base Address High Register */
20101 FR_RFSYMBHADR_16B_tag RFSYMBHADR; /* offset: 0x00E8 size: 16 bit */
20102 /* Receive FIFO System Memory Base Address Low Register */
20103 FR_RFSYMBLADR_16B_tag RFSYMBLADR; /* offset: 0x00EA size: 16 bit */
20104 /* Receive FIFO Periodic Timer Register */
20105 FR_RFPTR_16B_tag RFPTR; /* offset: 0x00EC size: 16 bit */
20106 /* Receive FIFO Fill Level and Pop Count Register */
20107 FR_RFFLPCR_16B_tag RFFLPCR; /* offset: 0x00EE size: 16 bit */
20108 /* ECC Error Interrupt Flag and Enable Register */
20109 FR_EEIFER_16B_tag EEIFER; /* offset: 0x00F0 size: 16 bit */
20110 /* ECC Error Report and Injection Control Register */
20111 FR_EERICR_16B_tag EERICR; /* offset: 0x00F2 size: 16 bit */
20112 /* ECC Error Report Adress Register */
20113 FR_EERAR_16B_tag EERAR; /* offset: 0x00F4 size: 16 bit */
20114 /* ECC Error Report Data Register */
20115 FR_EERDR_16B_tag EERDR; /* offset: 0x00F6 size: 16 bit */
20116 /* ECC Error Report Code Register */
20117 FR_EERCR_16B_tag EERCR; /* offset: 0x00F8 size: 16 bit */
20118 /* ECC Error Injection Address Register */
20119 FR_EEIAR_16B_tag EEIAR; /* offset: 0x00FA size: 16 bit */
20120 /* ECC Error Injection Data Register */
20121 FR_EEIDR_16B_tag EEIDR; /* offset: 0x00FC size: 16 bit */
20122 /* ECC Error Injection Code Register */
20123 FR_EEICR_16B_tag EEICR; /* offset: 0x00FE size: 16 bit */
20124 union {
20125 /* Register set MB */
20126 FR_MB_tag MB[64]; /* offset: 0x0100 (0x0008 x 64) */
20127
20128 FR_MB_tag MBCCS[64]; /* offset: 0x0100 (0x0008 x 64) */
20129
20130 struct {
20131 /* Message Buffer Configuration Control Status Register */
20132 FR_MBCCSR_16B_tag MBCCSR0; /* offset: 0x0100 size: 16 bit */
20133 /* Message Buffer Cycle Counter Filter Register */
20134 FR_MBCCFR_16B_tag MBCCFR0; /* offset: 0x0102 size: 16 bit */
20135 /* Message Buffer Frame ID Register */
20136 FR_MBFIDR_16B_tag MBFIDR0; /* offset: 0x0104 size: 16 bit */
20137 /* Message Buffer Index Register */
20138 FR_MBIDXR_16B_tag MBIDXR0; /* offset: 0x0106 size: 16 bit */
20139 /* Message Buffer Configuration Control Status Register */
20140 FR_MBCCSR_16B_tag MBCCSR1; /* offset: 0x0108 size: 16 bit */
20141 /* Message Buffer Cycle Counter Filter Register */
20142 FR_MBCCFR_16B_tag MBCCFR1; /* offset: 0x010A size: 16 bit */
20143 /* Message Buffer Frame ID Register */
20144 FR_MBFIDR_16B_tag MBFIDR1; /* offset: 0x010C size: 16 bit */
20145 /* Message Buffer Index Register */
20146 FR_MBIDXR_16B_tag MBIDXR1; /* offset: 0x010E size: 16 bit */
20147 /* Message Buffer Configuration Control Status Register */
20148 FR_MBCCSR_16B_tag MBCCSR2; /* offset: 0x0110 size: 16 bit */
20149 /* Message Buffer Cycle Counter Filter Register */
20150 FR_MBCCFR_16B_tag MBCCFR2; /* offset: 0x0112 size: 16 bit */
20151 /* Message Buffer Frame ID Register */
20152 FR_MBFIDR_16B_tag MBFIDR2; /* offset: 0x0114 size: 16 bit */
20153 /* Message Buffer Index Register */
20154 FR_MBIDXR_16B_tag MBIDXR2; /* offset: 0x0116 size: 16 bit */
20155 /* Message Buffer Configuration Control Status Register */
20156 FR_MBCCSR_16B_tag MBCCSR3; /* offset: 0x0118 size: 16 bit */
20157 /* Message Buffer Cycle Counter Filter Register */
20158 FR_MBCCFR_16B_tag MBCCFR3; /* offset: 0x011A size: 16 bit */
20159 /* Message Buffer Frame ID Register */
20160 FR_MBFIDR_16B_tag MBFIDR3; /* offset: 0x011C size: 16 bit */
20161 /* Message Buffer Index Register */
20162 FR_MBIDXR_16B_tag MBIDXR3; /* offset: 0x011E size: 16 bit */
20163 /* Message Buffer Configuration Control Status Register */
20164 FR_MBCCSR_16B_tag MBCCSR4; /* offset: 0x0120 size: 16 bit */
20165 /* Message Buffer Cycle Counter Filter Register */
20166 FR_MBCCFR_16B_tag MBCCFR4; /* offset: 0x0122 size: 16 bit */
20167 /* Message Buffer Frame ID Register */
20168 FR_MBFIDR_16B_tag MBFIDR4; /* offset: 0x0124 size: 16 bit */
20169 /* Message Buffer Index Register */
20170 FR_MBIDXR_16B_tag MBIDXR4; /* offset: 0x0126 size: 16 bit */
20171 /* Message Buffer Configuration Control Status Register */
20172 FR_MBCCSR_16B_tag MBCCSR5; /* offset: 0x0128 size: 16 bit */
20173 /* Message Buffer Cycle Counter Filter Register */
20174 FR_MBCCFR_16B_tag MBCCFR5; /* offset: 0x012A size: 16 bit */
20175 /* Message Buffer Frame ID Register */
20176 FR_MBFIDR_16B_tag MBFIDR5; /* offset: 0x012C size: 16 bit */
20177 /* Message Buffer Index Register */
20178 FR_MBIDXR_16B_tag MBIDXR5; /* offset: 0x012E size: 16 bit */
20179 /* Message Buffer Configuration Control Status Register */
20180 FR_MBCCSR_16B_tag MBCCSR6; /* offset: 0x0130 size: 16 bit */
20181 /* Message Buffer Cycle Counter Filter Register */
20182 FR_MBCCFR_16B_tag MBCCFR6; /* offset: 0x0132 size: 16 bit */
20183 /* Message Buffer Frame ID Register */
20184 FR_MBFIDR_16B_tag MBFIDR6; /* offset: 0x0134 size: 16 bit */
20185 /* Message Buffer Index Register */
20186 FR_MBIDXR_16B_tag MBIDXR6; /* offset: 0x0136 size: 16 bit */
20187 /* Message Buffer Configuration Control Status Register */
20188 FR_MBCCSR_16B_tag MBCCSR7; /* offset: 0x0138 size: 16 bit */
20189 /* Message Buffer Cycle Counter Filter Register */
20190 FR_MBCCFR_16B_tag MBCCFR7; /* offset: 0x013A size: 16 bit */
20191 /* Message Buffer Frame ID Register */
20192 FR_MBFIDR_16B_tag MBFIDR7; /* offset: 0x013C size: 16 bit */
20193 /* Message Buffer Index Register */
20194 FR_MBIDXR_16B_tag MBIDXR7; /* offset: 0x013E size: 16 bit */
20195 /* Message Buffer Configuration Control Status Register */
20196 FR_MBCCSR_16B_tag MBCCSR8; /* offset: 0x0140 size: 16 bit */
20197 /* Message Buffer Cycle Counter Filter Register */
20198 FR_MBCCFR_16B_tag MBCCFR8; /* offset: 0x0142 size: 16 bit */
20199 /* Message Buffer Frame ID Register */
20200 FR_MBFIDR_16B_tag MBFIDR8; /* offset: 0x0144 size: 16 bit */
20201 /* Message Buffer Index Register */
20202 FR_MBIDXR_16B_tag MBIDXR8; /* offset: 0x0146 size: 16 bit */
20203 /* Message Buffer Configuration Control Status Register */
20204 FR_MBCCSR_16B_tag MBCCSR9; /* offset: 0x0148 size: 16 bit */
20205 /* Message Buffer Cycle Counter Filter Register */
20206 FR_MBCCFR_16B_tag MBCCFR9; /* offset: 0x014A size: 16 bit */
20207 /* Message Buffer Frame ID Register */
20208 FR_MBFIDR_16B_tag MBFIDR9; /* offset: 0x014C size: 16 bit */
20209 /* Message Buffer Index Register */
20210 FR_MBIDXR_16B_tag MBIDXR9; /* offset: 0x014E size: 16 bit */
20211 /* Message Buffer Configuration Control Status Register */
20212 FR_MBCCSR_16B_tag MBCCSR10; /* offset: 0x0150 size: 16 bit */
20213 /* Message Buffer Cycle Counter Filter Register */
20214 FR_MBCCFR_16B_tag MBCCFR10; /* offset: 0x0152 size: 16 bit */
20215 /* Message Buffer Frame ID Register */
20216 FR_MBFIDR_16B_tag MBFIDR10; /* offset: 0x0154 size: 16 bit */
20217 /* Message Buffer Index Register */
20218 FR_MBIDXR_16B_tag MBIDXR10; /* offset: 0x0156 size: 16 bit */
20219 /* Message Buffer Configuration Control Status Register */
20220 FR_MBCCSR_16B_tag MBCCSR11; /* offset: 0x0158 size: 16 bit */
20221 /* Message Buffer Cycle Counter Filter Register */
20222 FR_MBCCFR_16B_tag MBCCFR11; /* offset: 0x015A size: 16 bit */
20223 /* Message Buffer Frame ID Register */
20224 FR_MBFIDR_16B_tag MBFIDR11; /* offset: 0x015C size: 16 bit */
20225 /* Message Buffer Index Register */
20226 FR_MBIDXR_16B_tag MBIDXR11; /* offset: 0x015E size: 16 bit */
20227 /* Message Buffer Configuration Control Status Register */
20228 FR_MBCCSR_16B_tag MBCCSR12; /* offset: 0x0160 size: 16 bit */
20229 /* Message Buffer Cycle Counter Filter Register */
20230 FR_MBCCFR_16B_tag MBCCFR12; /* offset: 0x0162 size: 16 bit */
20231 /* Message Buffer Frame ID Register */
20232 FR_MBFIDR_16B_tag MBFIDR12; /* offset: 0x0164 size: 16 bit */
20233 /* Message Buffer Index Register */
20234 FR_MBIDXR_16B_tag MBIDXR12; /* offset: 0x0166 size: 16 bit */
20235 /* Message Buffer Configuration Control Status Register */
20236 FR_MBCCSR_16B_tag MBCCSR13; /* offset: 0x0168 size: 16 bit */
20237 /* Message Buffer Cycle Counter Filter Register */
20238 FR_MBCCFR_16B_tag MBCCFR13; /* offset: 0x016A size: 16 bit */
20239 /* Message Buffer Frame ID Register */
20240 FR_MBFIDR_16B_tag MBFIDR13; /* offset: 0x016C size: 16 bit */
20241 /* Message Buffer Index Register */
20242 FR_MBIDXR_16B_tag MBIDXR13; /* offset: 0x016E size: 16 bit */
20243 /* Message Buffer Configuration Control Status Register */
20244 FR_MBCCSR_16B_tag MBCCSR14; /* offset: 0x0170 size: 16 bit */
20245 /* Message Buffer Cycle Counter Filter Register */
20246 FR_MBCCFR_16B_tag MBCCFR14; /* offset: 0x0172 size: 16 bit */
20247 /* Message Buffer Frame ID Register */
20248 FR_MBFIDR_16B_tag MBFIDR14; /* offset: 0x0174 size: 16 bit */
20249 /* Message Buffer Index Register */
20250 FR_MBIDXR_16B_tag MBIDXR14; /* offset: 0x0176 size: 16 bit */
20251 /* Message Buffer Configuration Control Status Register */
20252 FR_MBCCSR_16B_tag MBCCSR15; /* offset: 0x0178 size: 16 bit */
20253 /* Message Buffer Cycle Counter Filter Register */
20254 FR_MBCCFR_16B_tag MBCCFR15; /* offset: 0x017A size: 16 bit */
20255 /* Message Buffer Frame ID Register */
20256 FR_MBFIDR_16B_tag MBFIDR15; /* offset: 0x017C size: 16 bit */
20257 /* Message Buffer Index Register */
20258 FR_MBIDXR_16B_tag MBIDXR15; /* offset: 0x017E size: 16 bit */
20259 /* Message Buffer Configuration Control Status Register */
20260 FR_MBCCSR_16B_tag MBCCSR16; /* offset: 0x0180 size: 16 bit */
20261 /* Message Buffer Cycle Counter Filter Register */
20262 FR_MBCCFR_16B_tag MBCCFR16; /* offset: 0x0182 size: 16 bit */
20263 /* Message Buffer Frame ID Register */
20264 FR_MBFIDR_16B_tag MBFIDR16; /* offset: 0x0184 size: 16 bit */
20265 /* Message Buffer Index Register */
20266 FR_MBIDXR_16B_tag MBIDXR16; /* offset: 0x0186 size: 16 bit */
20267 /* Message Buffer Configuration Control Status Register */
20268 FR_MBCCSR_16B_tag MBCCSR17; /* offset: 0x0188 size: 16 bit */
20269 /* Message Buffer Cycle Counter Filter Register */
20270 FR_MBCCFR_16B_tag MBCCFR17; /* offset: 0x018A size: 16 bit */
20271 /* Message Buffer Frame ID Register */
20272 FR_MBFIDR_16B_tag MBFIDR17; /* offset: 0x018C size: 16 bit */
20273 /* Message Buffer Index Register */
20274 FR_MBIDXR_16B_tag MBIDXR17; /* offset: 0x018E size: 16 bit */
20275 /* Message Buffer Configuration Control Status Register */
20276 FR_MBCCSR_16B_tag MBCCSR18; /* offset: 0x0190 size: 16 bit */
20277 /* Message Buffer Cycle Counter Filter Register */
20278 FR_MBCCFR_16B_tag MBCCFR18; /* offset: 0x0192 size: 16 bit */
20279 /* Message Buffer Frame ID Register */
20280 FR_MBFIDR_16B_tag MBFIDR18; /* offset: 0x0194 size: 16 bit */
20281 /* Message Buffer Index Register */
20282 FR_MBIDXR_16B_tag MBIDXR18; /* offset: 0x0196 size: 16 bit */
20283 /* Message Buffer Configuration Control Status Register */
20284 FR_MBCCSR_16B_tag MBCCSR19; /* offset: 0x0198 size: 16 bit */
20285 /* Message Buffer Cycle Counter Filter Register */
20286 FR_MBCCFR_16B_tag MBCCFR19; /* offset: 0x019A size: 16 bit */
20287 /* Message Buffer Frame ID Register */
20288 FR_MBFIDR_16B_tag MBFIDR19; /* offset: 0x019C size: 16 bit */
20289 /* Message Buffer Index Register */
20290 FR_MBIDXR_16B_tag MBIDXR19; /* offset: 0x019E size: 16 bit */
20291 /* Message Buffer Configuration Control Status Register */
20292 FR_MBCCSR_16B_tag MBCCSR20; /* offset: 0x01A0 size: 16 bit */
20293 /* Message Buffer Cycle Counter Filter Register */
20294 FR_MBCCFR_16B_tag MBCCFR20; /* offset: 0x01A2 size: 16 bit */
20295 /* Message Buffer Frame ID Register */
20296 FR_MBFIDR_16B_tag MBFIDR20; /* offset: 0x01A4 size: 16 bit */
20297 /* Message Buffer Index Register */
20298 FR_MBIDXR_16B_tag MBIDXR20; /* offset: 0x01A6 size: 16 bit */
20299 /* Message Buffer Configuration Control Status Register */
20300 FR_MBCCSR_16B_tag MBCCSR21; /* offset: 0x01A8 size: 16 bit */
20301 /* Message Buffer Cycle Counter Filter Register */
20302 FR_MBCCFR_16B_tag MBCCFR21; /* offset: 0x01AA size: 16 bit */
20303 /* Message Buffer Frame ID Register */
20304 FR_MBFIDR_16B_tag MBFIDR21; /* offset: 0x01AC size: 16 bit */
20305 /* Message Buffer Index Register */
20306 FR_MBIDXR_16B_tag MBIDXR21; /* offset: 0x01AE size: 16 bit */
20307 /* Message Buffer Configuration Control Status Register */
20308 FR_MBCCSR_16B_tag MBCCSR22; /* offset: 0x01B0 size: 16 bit */
20309 /* Message Buffer Cycle Counter Filter Register */
20310 FR_MBCCFR_16B_tag MBCCFR22; /* offset: 0x01B2 size: 16 bit */
20311 /* Message Buffer Frame ID Register */
20312 FR_MBFIDR_16B_tag MBFIDR22; /* offset: 0x01B4 size: 16 bit */
20313 /* Message Buffer Index Register */
20314 FR_MBIDXR_16B_tag MBIDXR22; /* offset: 0x01B6 size: 16 bit */
20315 /* Message Buffer Configuration Control Status Register */
20316 FR_MBCCSR_16B_tag MBCCSR23; /* offset: 0x01B8 size: 16 bit */
20317 /* Message Buffer Cycle Counter Filter Register */
20318 FR_MBCCFR_16B_tag MBCCFR23; /* offset: 0x01BA size: 16 bit */
20319 /* Message Buffer Frame ID Register */
20320 FR_MBFIDR_16B_tag MBFIDR23; /* offset: 0x01BC size: 16 bit */
20321 /* Message Buffer Index Register */
20322 FR_MBIDXR_16B_tag MBIDXR23; /* offset: 0x01BE size: 16 bit */
20323 /* Message Buffer Configuration Control Status Register */
20324 FR_MBCCSR_16B_tag MBCCSR24; /* offset: 0x01C0 size: 16 bit */
20325 /* Message Buffer Cycle Counter Filter Register */
20326 FR_MBCCFR_16B_tag MBCCFR24; /* offset: 0x01C2 size: 16 bit */
20327 /* Message Buffer Frame ID Register */
20328 FR_MBFIDR_16B_tag MBFIDR24; /* offset: 0x01C4 size: 16 bit */
20329 /* Message Buffer Index Register */
20330 FR_MBIDXR_16B_tag MBIDXR24; /* offset: 0x01C6 size: 16 bit */
20331 /* Message Buffer Configuration Control Status Register */
20332 FR_MBCCSR_16B_tag MBCCSR25; /* offset: 0x01C8 size: 16 bit */
20333 /* Message Buffer Cycle Counter Filter Register */
20334 FR_MBCCFR_16B_tag MBCCFR25; /* offset: 0x01CA size: 16 bit */
20335 /* Message Buffer Frame ID Register */
20336 FR_MBFIDR_16B_tag MBFIDR25; /* offset: 0x01CC size: 16 bit */
20337 /* Message Buffer Index Register */
20338 FR_MBIDXR_16B_tag MBIDXR25; /* offset: 0x01CE size: 16 bit */
20339 /* Message Buffer Configuration Control Status Register */
20340 FR_MBCCSR_16B_tag MBCCSR26; /* offset: 0x01D0 size: 16 bit */
20341 /* Message Buffer Cycle Counter Filter Register */
20342 FR_MBCCFR_16B_tag MBCCFR26; /* offset: 0x01D2 size: 16 bit */
20343 /* Message Buffer Frame ID Register */
20344 FR_MBFIDR_16B_tag MBFIDR26; /* offset: 0x01D4 size: 16 bit */
20345 /* Message Buffer Index Register */
20346 FR_MBIDXR_16B_tag MBIDXR26; /* offset: 0x01D6 size: 16 bit */
20347 /* Message Buffer Configuration Control Status Register */
20348 FR_MBCCSR_16B_tag MBCCSR27; /* offset: 0x01D8 size: 16 bit */
20349 /* Message Buffer Cycle Counter Filter Register */
20350 FR_MBCCFR_16B_tag MBCCFR27; /* offset: 0x01DA size: 16 bit */
20351 /* Message Buffer Frame ID Register */
20352 FR_MBFIDR_16B_tag MBFIDR27; /* offset: 0x01DC size: 16 bit */
20353 /* Message Buffer Index Register */
20354 FR_MBIDXR_16B_tag MBIDXR27; /* offset: 0x01DE size: 16 bit */
20355 /* Message Buffer Configuration Control Status Register */
20356 FR_MBCCSR_16B_tag MBCCSR28; /* offset: 0x01E0 size: 16 bit */
20357 /* Message Buffer Cycle Counter Filter Register */
20358 FR_MBCCFR_16B_tag MBCCFR28; /* offset: 0x01E2 size: 16 bit */
20359 /* Message Buffer Frame ID Register */
20360 FR_MBFIDR_16B_tag MBFIDR28; /* offset: 0x01E4 size: 16 bit */
20361 /* Message Buffer Index Register */
20362 FR_MBIDXR_16B_tag MBIDXR28; /* offset: 0x01E6 size: 16 bit */
20363 /* Message Buffer Configuration Control Status Register */
20364 FR_MBCCSR_16B_tag MBCCSR29; /* offset: 0x01E8 size: 16 bit */
20365 /* Message Buffer Cycle Counter Filter Register */
20366 FR_MBCCFR_16B_tag MBCCFR29; /* offset: 0x01EA size: 16 bit */
20367 /* Message Buffer Frame ID Register */
20368 FR_MBFIDR_16B_tag MBFIDR29; /* offset: 0x01EC size: 16 bit */
20369 /* Message Buffer Index Register */
20370 FR_MBIDXR_16B_tag MBIDXR29; /* offset: 0x01EE size: 16 bit */
20371 /* Message Buffer Configuration Control Status Register */
20372 FR_MBCCSR_16B_tag MBCCSR30; /* offset: 0x01F0 size: 16 bit */
20373 /* Message Buffer Cycle Counter Filter Register */
20374 FR_MBCCFR_16B_tag MBCCFR30; /* offset: 0x01F2 size: 16 bit */
20375 /* Message Buffer Frame ID Register */
20376 FR_MBFIDR_16B_tag MBFIDR30; /* offset: 0x01F4 size: 16 bit */
20377 /* Message Buffer Index Register */
20378 FR_MBIDXR_16B_tag MBIDXR30; /* offset: 0x01F6 size: 16 bit */
20379 /* Message Buffer Configuration Control Status Register */
20380 FR_MBCCSR_16B_tag MBCCSR31; /* offset: 0x01F8 size: 16 bit */
20381 /* Message Buffer Cycle Counter Filter Register */
20382 FR_MBCCFR_16B_tag MBCCFR31; /* offset: 0x01FA size: 16 bit */
20383 /* Message Buffer Frame ID Register */
20384 FR_MBFIDR_16B_tag MBFIDR31; /* offset: 0x01FC size: 16 bit */
20385 /* Message Buffer Index Register */
20386 FR_MBIDXR_16B_tag MBIDXR31; /* offset: 0x01FE size: 16 bit */
20387 /* Message Buffer Configuration Control Status Register */
20388 FR_MBCCSR_16B_tag MBCCSR32; /* offset: 0x0200 size: 16 bit */
20389 /* Message Buffer Cycle Counter Filter Register */
20390 FR_MBCCFR_16B_tag MBCCFR32; /* offset: 0x0202 size: 16 bit */
20391 /* Message Buffer Frame ID Register */
20392 FR_MBFIDR_16B_tag MBFIDR32; /* offset: 0x0204 size: 16 bit */
20393 /* Message Buffer Index Register */
20394 FR_MBIDXR_16B_tag MBIDXR32; /* offset: 0x0206 size: 16 bit */
20395 /* Message Buffer Configuration Control Status Register */
20396 FR_MBCCSR_16B_tag MBCCSR33; /* offset: 0x0208 size: 16 bit */
20397 /* Message Buffer Cycle Counter Filter Register */
20398 FR_MBCCFR_16B_tag MBCCFR33; /* offset: 0x020A size: 16 bit */
20399 /* Message Buffer Frame ID Register */
20400 FR_MBFIDR_16B_tag MBFIDR33; /* offset: 0x020C size: 16 bit */
20401 /* Message Buffer Index Register */
20402 FR_MBIDXR_16B_tag MBIDXR33; /* offset: 0x020E size: 16 bit */
20403 /* Message Buffer Configuration Control Status Register */
20404 FR_MBCCSR_16B_tag MBCCSR34; /* offset: 0x0210 size: 16 bit */
20405 /* Message Buffer Cycle Counter Filter Register */
20406 FR_MBCCFR_16B_tag MBCCFR34; /* offset: 0x0212 size: 16 bit */
20407 /* Message Buffer Frame ID Register */
20408 FR_MBFIDR_16B_tag MBFIDR34; /* offset: 0x0214 size: 16 bit */
20409 /* Message Buffer Index Register */
20410 FR_MBIDXR_16B_tag MBIDXR34; /* offset: 0x0216 size: 16 bit */
20411 /* Message Buffer Configuration Control Status Register */
20412 FR_MBCCSR_16B_tag MBCCSR35; /* offset: 0x0218 size: 16 bit */
20413 /* Message Buffer Cycle Counter Filter Register */
20414 FR_MBCCFR_16B_tag MBCCFR35; /* offset: 0x021A size: 16 bit */
20415 /* Message Buffer Frame ID Register */
20416 FR_MBFIDR_16B_tag MBFIDR35; /* offset: 0x021C size: 16 bit */
20417 /* Message Buffer Index Register */
20418 FR_MBIDXR_16B_tag MBIDXR35; /* offset: 0x021E size: 16 bit */
20419 /* Message Buffer Configuration Control Status Register */
20420 FR_MBCCSR_16B_tag MBCCSR36; /* offset: 0x0220 size: 16 bit */
20421 /* Message Buffer Cycle Counter Filter Register */
20422 FR_MBCCFR_16B_tag MBCCFR36; /* offset: 0x0222 size: 16 bit */
20423 /* Message Buffer Frame ID Register */
20424 FR_MBFIDR_16B_tag MBFIDR36; /* offset: 0x0224 size: 16 bit */
20425 /* Message Buffer Index Register */
20426 FR_MBIDXR_16B_tag MBIDXR36; /* offset: 0x0226 size: 16 bit */
20427 /* Message Buffer Configuration Control Status Register */
20428 FR_MBCCSR_16B_tag MBCCSR37; /* offset: 0x0228 size: 16 bit */
20429 /* Message Buffer Cycle Counter Filter Register */
20430 FR_MBCCFR_16B_tag MBCCFR37; /* offset: 0x022A size: 16 bit */
20431 /* Message Buffer Frame ID Register */
20432 FR_MBFIDR_16B_tag MBFIDR37; /* offset: 0x022C size: 16 bit */
20433 /* Message Buffer Index Register */
20434 FR_MBIDXR_16B_tag MBIDXR37; /* offset: 0x022E size: 16 bit */
20435 /* Message Buffer Configuration Control Status Register */
20436 FR_MBCCSR_16B_tag MBCCSR38; /* offset: 0x0230 size: 16 bit */
20437 /* Message Buffer Cycle Counter Filter Register */
20438 FR_MBCCFR_16B_tag MBCCFR38; /* offset: 0x0232 size: 16 bit */
20439 /* Message Buffer Frame ID Register */
20440 FR_MBFIDR_16B_tag MBFIDR38; /* offset: 0x0234 size: 16 bit */
20441 /* Message Buffer Index Register */
20442 FR_MBIDXR_16B_tag MBIDXR38; /* offset: 0x0236 size: 16 bit */
20443 /* Message Buffer Configuration Control Status Register */
20444 FR_MBCCSR_16B_tag MBCCSR39; /* offset: 0x0238 size: 16 bit */
20445 /* Message Buffer Cycle Counter Filter Register */
20446 FR_MBCCFR_16B_tag MBCCFR39; /* offset: 0x023A size: 16 bit */
20447 /* Message Buffer Frame ID Register */
20448 FR_MBFIDR_16B_tag MBFIDR39; /* offset: 0x023C size: 16 bit */
20449 /* Message Buffer Index Register */
20450 FR_MBIDXR_16B_tag MBIDXR39; /* offset: 0x023E size: 16 bit */
20451 /* Message Buffer Configuration Control Status Register */
20452 FR_MBCCSR_16B_tag MBCCSR40; /* offset: 0x0240 size: 16 bit */
20453 /* Message Buffer Cycle Counter Filter Register */
20454 FR_MBCCFR_16B_tag MBCCFR40; /* offset: 0x0242 size: 16 bit */
20455 /* Message Buffer Frame ID Register */
20456 FR_MBFIDR_16B_tag MBFIDR40; /* offset: 0x0244 size: 16 bit */
20457 /* Message Buffer Index Register */
20458 FR_MBIDXR_16B_tag MBIDXR40; /* offset: 0x0246 size: 16 bit */
20459 /* Message Buffer Configuration Control Status Register */
20460 FR_MBCCSR_16B_tag MBCCSR41; /* offset: 0x0248 size: 16 bit */
20461 /* Message Buffer Cycle Counter Filter Register */
20462 FR_MBCCFR_16B_tag MBCCFR41; /* offset: 0x024A size: 16 bit */
20463 /* Message Buffer Frame ID Register */
20464 FR_MBFIDR_16B_tag MBFIDR41; /* offset: 0x024C size: 16 bit */
20465 /* Message Buffer Index Register */
20466 FR_MBIDXR_16B_tag MBIDXR41; /* offset: 0x024E size: 16 bit */
20467 /* Message Buffer Configuration Control Status Register */
20468 FR_MBCCSR_16B_tag MBCCSR42; /* offset: 0x0250 size: 16 bit */
20469 /* Message Buffer Cycle Counter Filter Register */
20470 FR_MBCCFR_16B_tag MBCCFR42; /* offset: 0x0252 size: 16 bit */
20471 /* Message Buffer Frame ID Register */
20472 FR_MBFIDR_16B_tag MBFIDR42; /* offset: 0x0254 size: 16 bit */
20473 /* Message Buffer Index Register */
20474 FR_MBIDXR_16B_tag MBIDXR42; /* offset: 0x0256 size: 16 bit */
20475 /* Message Buffer Configuration Control Status Register */
20476 FR_MBCCSR_16B_tag MBCCSR43; /* offset: 0x0258 size: 16 bit */
20477 /* Message Buffer Cycle Counter Filter Register */
20478 FR_MBCCFR_16B_tag MBCCFR43; /* offset: 0x025A size: 16 bit */
20479 /* Message Buffer Frame ID Register */
20480 FR_MBFIDR_16B_tag MBFIDR43; /* offset: 0x025C size: 16 bit */
20481 /* Message Buffer Index Register */
20482 FR_MBIDXR_16B_tag MBIDXR43; /* offset: 0x025E size: 16 bit */
20483 /* Message Buffer Configuration Control Status Register */
20484 FR_MBCCSR_16B_tag MBCCSR44; /* offset: 0x0260 size: 16 bit */
20485 /* Message Buffer Cycle Counter Filter Register */
20486 FR_MBCCFR_16B_tag MBCCFR44; /* offset: 0x0262 size: 16 bit */
20487 /* Message Buffer Frame ID Register */
20488 FR_MBFIDR_16B_tag MBFIDR44; /* offset: 0x0264 size: 16 bit */
20489 /* Message Buffer Index Register */
20490 FR_MBIDXR_16B_tag MBIDXR44; /* offset: 0x0266 size: 16 bit */
20491 /* Message Buffer Configuration Control Status Register */
20492 FR_MBCCSR_16B_tag MBCCSR45; /* offset: 0x0268 size: 16 bit */
20493 /* Message Buffer Cycle Counter Filter Register */
20494 FR_MBCCFR_16B_tag MBCCFR45; /* offset: 0x026A size: 16 bit */
20495 /* Message Buffer Frame ID Register */
20496 FR_MBFIDR_16B_tag MBFIDR45; /* offset: 0x026C size: 16 bit */
20497 /* Message Buffer Index Register */
20498 FR_MBIDXR_16B_tag MBIDXR45; /* offset: 0x026E size: 16 bit */
20499 /* Message Buffer Configuration Control Status Register */
20500 FR_MBCCSR_16B_tag MBCCSR46; /* offset: 0x0270 size: 16 bit */
20501 /* Message Buffer Cycle Counter Filter Register */
20502 FR_MBCCFR_16B_tag MBCCFR46; /* offset: 0x0272 size: 16 bit */
20503 /* Message Buffer Frame ID Register */
20504 FR_MBFIDR_16B_tag MBFIDR46; /* offset: 0x0274 size: 16 bit */
20505 /* Message Buffer Index Register */
20506 FR_MBIDXR_16B_tag MBIDXR46; /* offset: 0x0276 size: 16 bit */
20507 /* Message Buffer Configuration Control Status Register */
20508 FR_MBCCSR_16B_tag MBCCSR47; /* offset: 0x0278 size: 16 bit */
20509 /* Message Buffer Cycle Counter Filter Register */
20510 FR_MBCCFR_16B_tag MBCCFR47; /* offset: 0x027A size: 16 bit */
20511 /* Message Buffer Frame ID Register */
20512 FR_MBFIDR_16B_tag MBFIDR47; /* offset: 0x027C size: 16 bit */
20513 /* Message Buffer Index Register */
20514 FR_MBIDXR_16B_tag MBIDXR47; /* offset: 0x027E size: 16 bit */
20515 /* Message Buffer Configuration Control Status Register */
20516 FR_MBCCSR_16B_tag MBCCSR48; /* offset: 0x0280 size: 16 bit */
20517 /* Message Buffer Cycle Counter Filter Register */
20518 FR_MBCCFR_16B_tag MBCCFR48; /* offset: 0x0282 size: 16 bit */
20519 /* Message Buffer Frame ID Register */
20520 FR_MBFIDR_16B_tag MBFIDR48; /* offset: 0x0284 size: 16 bit */
20521 /* Message Buffer Index Register */
20522 FR_MBIDXR_16B_tag MBIDXR48; /* offset: 0x0286 size: 16 bit */
20523 /* Message Buffer Configuration Control Status Register */
20524 FR_MBCCSR_16B_tag MBCCSR49; /* offset: 0x0288 size: 16 bit */
20525 /* Message Buffer Cycle Counter Filter Register */
20526 FR_MBCCFR_16B_tag MBCCFR49; /* offset: 0x028A size: 16 bit */
20527 /* Message Buffer Frame ID Register */
20528 FR_MBFIDR_16B_tag MBFIDR49; /* offset: 0x028C size: 16 bit */
20529 /* Message Buffer Index Register */
20530 FR_MBIDXR_16B_tag MBIDXR49; /* offset: 0x028E size: 16 bit */
20531 /* Message Buffer Configuration Control Status Register */
20532 FR_MBCCSR_16B_tag MBCCSR50; /* offset: 0x0290 size: 16 bit */
20533 /* Message Buffer Cycle Counter Filter Register */
20534 FR_MBCCFR_16B_tag MBCCFR50; /* offset: 0x0292 size: 16 bit */
20535 /* Message Buffer Frame ID Register */
20536 FR_MBFIDR_16B_tag MBFIDR50; /* offset: 0x0294 size: 16 bit */
20537 /* Message Buffer Index Register */
20538 FR_MBIDXR_16B_tag MBIDXR50; /* offset: 0x0296 size: 16 bit */
20539 /* Message Buffer Configuration Control Status Register */
20540 FR_MBCCSR_16B_tag MBCCSR51; /* offset: 0x0298 size: 16 bit */
20541 /* Message Buffer Cycle Counter Filter Register */
20542 FR_MBCCFR_16B_tag MBCCFR51; /* offset: 0x029A size: 16 bit */
20543 /* Message Buffer Frame ID Register */
20544 FR_MBFIDR_16B_tag MBFIDR51; /* offset: 0x029C size: 16 bit */
20545 /* Message Buffer Index Register */
20546 FR_MBIDXR_16B_tag MBIDXR51; /* offset: 0x029E size: 16 bit */
20547 /* Message Buffer Configuration Control Status Register */
20548 FR_MBCCSR_16B_tag MBCCSR52; /* offset: 0x02A0 size: 16 bit */
20549 /* Message Buffer Cycle Counter Filter Register */
20550 FR_MBCCFR_16B_tag MBCCFR52; /* offset: 0x02A2 size: 16 bit */
20551 /* Message Buffer Frame ID Register */
20552 FR_MBFIDR_16B_tag MBFIDR52; /* offset: 0x02A4 size: 16 bit */
20553 /* Message Buffer Index Register */
20554 FR_MBIDXR_16B_tag MBIDXR52; /* offset: 0x02A6 size: 16 bit */
20555 /* Message Buffer Configuration Control Status Register */
20556 FR_MBCCSR_16B_tag MBCCSR53; /* offset: 0x02A8 size: 16 bit */
20557 /* Message Buffer Cycle Counter Filter Register */
20558 FR_MBCCFR_16B_tag MBCCFR53; /* offset: 0x02AA size: 16 bit */
20559 /* Message Buffer Frame ID Register */
20560 FR_MBFIDR_16B_tag MBFIDR53; /* offset: 0x02AC size: 16 bit */
20561 /* Message Buffer Index Register */
20562 FR_MBIDXR_16B_tag MBIDXR53; /* offset: 0x02AE size: 16 bit */
20563 /* Message Buffer Configuration Control Status Register */
20564 FR_MBCCSR_16B_tag MBCCSR54; /* offset: 0x02B0 size: 16 bit */
20565 /* Message Buffer Cycle Counter Filter Register */
20566 FR_MBCCFR_16B_tag MBCCFR54; /* offset: 0x02B2 size: 16 bit */
20567 /* Message Buffer Frame ID Register */
20568 FR_MBFIDR_16B_tag MBFIDR54; /* offset: 0x02B4 size: 16 bit */
20569 /* Message Buffer Index Register */
20570 FR_MBIDXR_16B_tag MBIDXR54; /* offset: 0x02B6 size: 16 bit */
20571 /* Message Buffer Configuration Control Status Register */
20572 FR_MBCCSR_16B_tag MBCCSR55; /* offset: 0x02B8 size: 16 bit */
20573 /* Message Buffer Cycle Counter Filter Register */
20574 FR_MBCCFR_16B_tag MBCCFR55; /* offset: 0x02BA size: 16 bit */
20575 /* Message Buffer Frame ID Register */
20576 FR_MBFIDR_16B_tag MBFIDR55; /* offset: 0x02BC size: 16 bit */
20577 /* Message Buffer Index Register */
20578 FR_MBIDXR_16B_tag MBIDXR55; /* offset: 0x02BE size: 16 bit */
20579 /* Message Buffer Configuration Control Status Register */
20580 FR_MBCCSR_16B_tag MBCCSR56; /* offset: 0x02C0 size: 16 bit */
20581 /* Message Buffer Cycle Counter Filter Register */
20582 FR_MBCCFR_16B_tag MBCCFR56; /* offset: 0x02C2 size: 16 bit */
20583 /* Message Buffer Frame ID Register */
20584 FR_MBFIDR_16B_tag MBFIDR56; /* offset: 0x02C4 size: 16 bit */
20585 /* Message Buffer Index Register */
20586 FR_MBIDXR_16B_tag MBIDXR56; /* offset: 0x02C6 size: 16 bit */
20587 /* Message Buffer Configuration Control Status Register */
20588 FR_MBCCSR_16B_tag MBCCSR57; /* offset: 0x02C8 size: 16 bit */
20589 /* Message Buffer Cycle Counter Filter Register */
20590 FR_MBCCFR_16B_tag MBCCFR57; /* offset: 0x02CA size: 16 bit */
20591 /* Message Buffer Frame ID Register */
20592 FR_MBFIDR_16B_tag MBFIDR57; /* offset: 0x02CC size: 16 bit */
20593 /* Message Buffer Index Register */
20594 FR_MBIDXR_16B_tag MBIDXR57; /* offset: 0x02CE size: 16 bit */
20595 /* Message Buffer Configuration Control Status Register */
20596 FR_MBCCSR_16B_tag MBCCSR58; /* offset: 0x02D0 size: 16 bit */
20597 /* Message Buffer Cycle Counter Filter Register */
20598 FR_MBCCFR_16B_tag MBCCFR58; /* offset: 0x02D2 size: 16 bit */
20599 /* Message Buffer Frame ID Register */
20600 FR_MBFIDR_16B_tag MBFIDR58; /* offset: 0x02D4 size: 16 bit */
20601 /* Message Buffer Index Register */
20602 FR_MBIDXR_16B_tag MBIDXR58; /* offset: 0x02D6 size: 16 bit */
20603 /* Message Buffer Configuration Control Status Register */
20604 FR_MBCCSR_16B_tag MBCCSR59; /* offset: 0x02D8 size: 16 bit */
20605 /* Message Buffer Cycle Counter Filter Register */
20606 FR_MBCCFR_16B_tag MBCCFR59; /* offset: 0x02DA size: 16 bit */
20607 /* Message Buffer Frame ID Register */
20608 FR_MBFIDR_16B_tag MBFIDR59; /* offset: 0x02DC size: 16 bit */
20609 /* Message Buffer Index Register */
20610 FR_MBIDXR_16B_tag MBIDXR59; /* offset: 0x02DE size: 16 bit */
20611 /* Message Buffer Configuration Control Status Register */
20612 FR_MBCCSR_16B_tag MBCCSR60; /* offset: 0x02E0 size: 16 bit */
20613 /* Message Buffer Cycle Counter Filter Register */
20614 FR_MBCCFR_16B_tag MBCCFR60; /* offset: 0x02E2 size: 16 bit */
20615 /* Message Buffer Frame ID Register */
20616 FR_MBFIDR_16B_tag MBFIDR60; /* offset: 0x02E4 size: 16 bit */
20617 /* Message Buffer Index Register */
20618 FR_MBIDXR_16B_tag MBIDXR60; /* offset: 0x02E6 size: 16 bit */
20619 /* Message Buffer Configuration Control Status Register */
20620 FR_MBCCSR_16B_tag MBCCSR61; /* offset: 0x02E8 size: 16 bit */
20621 /* Message Buffer Cycle Counter Filter Register */
20622 FR_MBCCFR_16B_tag MBCCFR61; /* offset: 0x02EA size: 16 bit */
20623 /* Message Buffer Frame ID Register */
20624 FR_MBFIDR_16B_tag MBFIDR61; /* offset: 0x02EC size: 16 bit */
20625 /* Message Buffer Index Register */
20626 FR_MBIDXR_16B_tag MBIDXR61; /* offset: 0x02EE size: 16 bit */
20627 /* Message Buffer Configuration Control Status Register */
20628 FR_MBCCSR_16B_tag MBCCSR62; /* offset: 0x02F0 size: 16 bit */
20629 /* Message Buffer Cycle Counter Filter Register */
20630 FR_MBCCFR_16B_tag MBCCFR62; /* offset: 0x02F2 size: 16 bit */
20631 /* Message Buffer Frame ID Register */
20632 FR_MBFIDR_16B_tag MBFIDR62; /* offset: 0x02F4 size: 16 bit */
20633 /* Message Buffer Index Register */
20634 FR_MBIDXR_16B_tag MBIDXR62; /* offset: 0x02F6 size: 16 bit */
20635 /* Message Buffer Configuration Control Status Register */
20636 FR_MBCCSR_16B_tag MBCCSR63; /* offset: 0x02F8 size: 16 bit */
20637 /* Message Buffer Cycle Counter Filter Register */
20638 FR_MBCCFR_16B_tag MBCCFR63; /* offset: 0x02FA size: 16 bit */
20639 /* Message Buffer Frame ID Register */
20640 FR_MBFIDR_16B_tag MBFIDR63; /* offset: 0x02FC size: 16 bit */
20641 /* Message Buffer Index Register */
20642 FR_MBIDXR_16B_tag MBIDXR63; /* offset: 0x02FE size: 16 bit */
20643 };
20644
20645 };
20646 } FR_tag;
20647
20648
20649#define FR (*(volatile FR_tag *) 0xFFFE0000UL)
20650
20651
20652
20653
20654
20655#ifdef __MWERKS__
20656#pragma pop
20657#endif
20658
20659#ifdef __cplusplus
20660}
20661#endif
20662#endif /* ASM */
20663#endif /* _leopard_H_*/
20664
20665/* End of file */
20666
RESET
#define RESET
Issue a read for reset.
Definition: wd80x3.h:31
FIFO
#define FIFO
Definition: wd80x3.h:55
regs-edma.h
ADC_struct_tag
Definition: fsl-mpc564xL.h:7141
ADC_tag
Definition: fsl-mpc5668.h:73
CFLASH_SHADOW_BIU_DEFAULTS_struct_tag
Definition: fsl-mpc564xL.h:262
CFLASH_SHADOW_struct_tag
Definition: fsl-mpc564xL.h:271
CFLASH_struct_tag
Definition: fsl-mpc564xL.h:639
CGM_AUXCLK_struct_tag
Definition: fsl-mpc564xL.h:4916
CGM_struct_tag
Definition: fsl-mpc564xL.h:4926
CMU_struct_tag
Definition: fsl-mpc564xL.h:4793
CRC_CNTX_struct_tag
Definition: fsl-mpc564xL.h:10389
CRC_struct_tag
Definition: fsl-mpc564xL.h:10403
CTU_struct_tag
Definition: fsl-mpc564xL.h:8225
CTU_tag
Definition: fsl-mpc5668.h:1542
DMA_CH_MUX_struct_tag
Definition: fsl-mpc564xL.h:18122
DSPI_tag
Definition: fsl-mpc551x.h:244
FCCU_struct_tag
Definition: fsl-mpc564xL.h:11948
FLEXCAN_MB_struct_tag
Definition: fsl-mpc564xL.h:17418
FLEXCAN_struct_tag
Definition: fsl-mpc564xL.h:17445
FLEXCAN_tag
Definition: fsl-mpc551x.h:1171
FR_MB_struct_tag
Definition: fsl-mpc564xL.h:19797
FR_struct_tag
Definition: fsl-mpc564xL.h:19811
FR_tag
Definition: fsl-mpc551x.h:3622
INTC_struct_tag
Definition: fsl-mpc564xL.h:15811
INTC_tag
Definition: fsl-mpc551x.h:1603
LINFLEX_struct_tag
Definition: fsl-mpc564xL.h:10261
MAX_MASTER_PORT_struct_tag
Definition: fsl-mpc564xL.h:12988
MAX_SLAVE_PORT_struct_tag
Definition: fsl-mpc564xL.h:12973
MAX_struct_tag
Definition: fsl-mpc564xL.h:12997
ME_struct_tag
Definition: fsl-mpc564xL.h:4299
MPU_REGION_struct_tag
Definition: fsl-mpc564xL.h:13264
MPU_SLAVE_PORT_struct_tag
Definition: fsl-mpc564xL.h:13255
MPU_struct_tag
Definition: fsl-mpc564xL.h:13278
MPU_tag
Definition: fsl-mpc551x.h:1843
OSC_struct_tag
Definition: fsl-mpc564xL.h:4616
PBRIDGE_struct_tag
Definition: fsl-mpc564xL.h:12831
PCU_struct_tag
Definition: fsl-mpc564xL.h:5340
PIT_RTI_CHANNEL_struct_tag
Definition: fsl-mpc564xL.h:5597
PIT_RTI_struct_tag
Definition: fsl-mpc564xL.h:5611
PLLD_struct_tag
Definition: fsl-mpc564xL.h:4702
PMUCTRL_struct_tag
Definition: fsl-mpc564xL.h:5506
RC_struct_tag
Definition: fsl-mpc564xL.h:4647
RGM_struct_tag
Definition: fsl-mpc564xL.h:5261
SEMA4_struct_tag
Definition: fsl-mpc564xL.h:13545
SEMA4_tag
Definition: fsl-mpc551x.h:2087
SGENDIG_struct_tag
Definition: fsl-mpc564xL.h:12165
SIU_tag
Definition: fsl-mpc551x.h:2221
SPP_DMA2_CHANNEL_struct_tag
Definition: fsl-mpc564xL.h:14471
SPP_DMA2_struct_tag
Definition: fsl-mpc564xL.h:14493
SPP_MCM_struct_tag
Definition: fsl-mpc564xL.h:14047
SSCM_struct_tag
Definition: fsl-mpc564xL.h:3757
STAT
Definition: dd.h:66
STM_CHANNEL_struct_tag
Definition: fsl-mpc564xL.h:13747
STM_struct_tag
Definition: fsl-mpc564xL.h:13760
STM_tag
Definition: fsl-mpc5668.h:6467
SWT_struct_tag
Definition: fsl-mpc564xL.h:13674
SWT_tag
Definition: fsl-mpc5668.h:6576
WKPU_struct_tag
Definition: fsl-mpc564xL.h:3601
mcPWM_SUBMOD_struct_tag
Definition: fsl-mpc564xL.h:9564
mcPWM_struct_tag
Definition: fsl-mpc564xL.h:9647
mcTIMER_CHANNEL_struct_tag
Definition: fsl-mpc564xL.h:8740
mcTIMER_struct_tag
Definition: fsl-mpc564xL.h:8781
ADC_AWORR_32B_tag
Definition: fsl-mpc564xL.h:6893
ADC_CDR_32B_tag
Definition: fsl-mpc564xL.h:6715
ADC_CEOCFR0_32B_tag
Definition: fsl-mpc564xL.h:5740
ADC_CEOCFR1_32B_tag
Definition: fsl-mpc564xL.h:5906
ADC_CEOCFR2_32B_tag
Definition: fsl-mpc564xL.h:5944
ADC_CIMR0_32B_tag
Definition: fsl-mpc564xL.h:5996
ADC_CIMR1_32B_tag
Definition: fsl-mpc564xL.h:6034
ADC_CIMR2_32B_tag
Definition: fsl-mpc564xL.h:6072
ADC_CTR_32B_tag
Definition: fsl-mpc564xL.h:6436
ADC_CWENR_32B_tag
Definition: fsl-mpc564xL.h:6867
ADC_CWSELR_32B_tag
Definition: fsl-mpc564xL.h:6850
ADC_DMAE_32B_tag
Definition: fsl-mpc564xL.h:6140
ADC_DMAR0_32B_tag
Definition: fsl-mpc564xL.h:6149
ADC_DMAR1_32B_tag
Definition: fsl-mpc564xL.h:6187
ADC_DMAR2_32B_tag
Definition: fsl-mpc564xL.h:6225
ADC_DSDR_32B_tag
Definition: fsl-mpc564xL.h:6696
ADC_IMR_32B_tag
Definition: fsl-mpc564xL.h:5982
ADC_ISR_32B_tag
Definition: fsl-mpc564xL.h:5726
ADC_JCMR0_32B_tag
Definition: fsl-mpc564xL.h:6568
ADC_JCMR1_32B_tag
Definition: fsl-mpc564xL.h:6606
ADC_JCMR2_32B_tag
Definition: fsl-mpc564xL.h:6644
ADC_MCR_32B_tag
Definition: fsl-mpc564xL.h:5670
ADC_MSR_32B_tag
Definition: fsl-mpc564xL.h:5703
ADC_NCMR0_32B_tag
Definition: fsl-mpc564xL.h:6454
ADC_NCMR1_32B_tag
Definition: fsl-mpc564xL.h:6492
ADC_NCMR2_32B_tag
Definition: fsl-mpc564xL.h:6530
ADC_OFFWR_32B_tag
Definition: fsl-mpc564xL.h:6682
ADC_PDEDR_32B_tag
Definition: fsl-mpc564xL.h:6704
ADC_PSCR_32B_tag
Definition: fsl-mpc564xL.h:6304
ADC_PSR0_32B_tag
Definition: fsl-mpc564xL.h:6319
ADC_PSR1_32B_tag
Definition: fsl-mpc564xL.h:6357
ADC_PSR2_32B_tag
Definition: fsl-mpc564xL.h:6395
ADC_STAW0R_32B_tag
Definition: fsl-mpc564xL.h:7063
ADC_STAW1AR_32B_tag
Definition: fsl-mpc564xL.h:7075
ADC_STAW1BR_32B_tag
Definition: fsl-mpc564xL.h:7086
ADC_STAW2R_32B_tag
Definition: fsl-mpc564xL.h:7096
ADC_STAW3R_32B_tag
Definition: fsl-mpc564xL.h:7105
ADC_STAW4R_32B_tag
Definition: fsl-mpc564xL.h:7117
ADC_STAW5R_32B_tag
Definition: fsl-mpc564xL.h:7129
ADC_STBRR_32B_tag
Definition: fsl-mpc564xL.h:6978
ADC_STCR1_32B_tag
Definition: fsl-mpc564xL.h:6931
ADC_STCR2_32B_tag
Definition: fsl-mpc564xL.h:6943
ADC_STCR3_32B_tag
Definition: fsl-mpc564xL.h:6969
ADC_STDR1_32B_tag
Definition: fsl-mpc564xL.h:7041
ADC_STDR2_32B_tag
Definition: fsl-mpc564xL.h:7052
ADC_STSR1_32B_tag
Definition: fsl-mpc564xL.h:6988
ADC_STSR2_32B_tag
Definition: fsl-mpc564xL.h:7010
ADC_STSR3_32B_tag
Definition: fsl-mpc564xL.h:7021
ADC_STSR4_32B_tag
Definition: fsl-mpc564xL.h:7031
ADC_THRALT_32B_tag
Definition: fsl-mpc564xL.h:6294
ADC_THRHLR10_32B_tag
Definition: fsl-mpc564xL.h:6787
ADC_THRHLR11_32B_tag
Definition: fsl-mpc564xL.h:6797
ADC_THRHLR12_32B_tag
Definition: fsl-mpc564xL.h:6807
ADC_THRHLR13_32B_tag
Definition: fsl-mpc564xL.h:6817
ADC_THRHLR14_32B_tag
Definition: fsl-mpc564xL.h:6827
ADC_THRHLR15_32B_tag
Definition: fsl-mpc564xL.h:6837
ADC_THRHLR4_32B_tag
Definition: fsl-mpc564xL.h:6727
ADC_THRHLR5_32B_tag
Definition: fsl-mpc564xL.h:6737
ADC_THRHLR6_32B_tag
Definition: fsl-mpc564xL.h:6747
ADC_THRHLR7_32B_tag
Definition: fsl-mpc564xL.h:6757
ADC_THRHLR8_32B_tag
Definition: fsl-mpc564xL.h:6767
ADC_THRHLR9_32B_tag
Definition: fsl-mpc564xL.h:6777
ADC_THRHLR_32B_tag
Definition: fsl-mpc564xL.h:6281
ADC_TRC_32B_tag
Definition: fsl-mpc564xL.h:6266
ADC_WTIMR_32B_tag
Definition: fsl-mpc564xL.h:6125
ADC_WTISR_32B_tag
Definition: fsl-mpc564xL.h:6110
CFLASH_ADR_32B_tag
Definition: fsl-mpc564xL.h:428
CFLASH_BIU_32B_tag
Definition: fsl-mpc564xL.h:527
CFLASH_HBL_32B_tag
Definition: fsl-mpc564xL.h:380
CFLASH_HBS_32B_tag
Definition: fsl-mpc564xL.h:420
CFLASH_LML_32B_tag
Definition: fsl-mpc564xL.h:359
CFLASH_LMS_32B_tag
Definition: fsl-mpc564xL.h:410
CFLASH_MCR_32B_tag
Definition: fsl-mpc564xL.h:334
CFLASH_PFAPR_32B_tag
Definition: fsl-mpc564xL.h:560
CFLASH_PFCR0_32B_tag
Definition: fsl-mpc564xL.h:438
CFLASH_PFCR1_32B_tag
Definition: fsl-mpc564xL.h:531
CFLASH_PFCR_32B_tag
Definition: fsl-mpc564xL.h:633
CFLASH_SHADOW_NVBIU_32B_tag
Definition: fsl-mpc564xL.h:247
CFLASH_SHADOW_NVHBL_32B_tag
Definition: fsl-mpc564xL.h:236
CFLASH_SHADOW_NVLML_32B_tag
Definition: fsl-mpc564xL.h:232
CFLASH_SHADOW_NVPWD_32B_tag
Definition: fsl-mpc564xL.h:214
CFLASH_SHADOW_NVSCI_32B_tag
Definition: fsl-mpc564xL.h:224
CFLASH_SHADOW_NVSLL_32B_tag
Definition: fsl-mpc564xL.h:240
CFLASH_SHADOW_NVUSRO_32B_tag
Definition: fsl-mpc564xL.h:254
CFLASH_SLL_32B_tag
Definition: fsl-mpc564xL.h:389
CFLASH_UM_32B_tag
Definition: fsl-mpc564xL.h:612
CFLASH_UT0_32B_tag
Definition: fsl-mpc564xL.h:584
CFLASH_UT1_32B_tag
Definition: fsl-mpc564xL.h:601
CFLASH_UT2_32B_tag
Definition: fsl-mpc564xL.h:605
CFLASH_UT_32B_tag
Definition: fsl-mpc564xL.h:626
CGM_AC_DC0_3_32B_tag
Definition: fsl-mpc564xL.h:4902
CGM_AC_SC_32B_tag
Definition: fsl-mpc564xL.h:4887
CGM_OCDS_SC_32B_tag
Definition: fsl-mpc564xL.h:4834
CGM_OC_EN_32B_tag
Definition: fsl-mpc564xL.h:4823
CGM_SC_DC0_3_32B_tag
Definition: fsl-mpc564xL.h:4859
CGM_SC_DC_8B_tag
Definition: fsl-mpc564xL.h:4875
CGM_SC_SS_32B_tag
Definition: fsl-mpc564xL.h:4847
CMU_CSR_32B_tag
Definition: fsl-mpc564xL.h:4723
CMU_FDR_32B_tag
Definition: fsl-mpc564xL.h:4740
CMU_HFREFR_A_32B_tag
Definition: fsl-mpc564xL.h:4748
CMU_IMR_32B_tag
Definition: fsl-mpc564xL.h:4779
CMU_ISR_32B_tag
Definition: fsl-mpc564xL.h:4764
CMU_LFREFR_A_32B_tag
Definition: fsl-mpc564xL.h:4756
CMU_MDR_32B_tag
Definition: fsl-mpc564xL.h:4783
CRC_CFG_32B_tag
Definition: fsl-mpc564xL.h:10345
CRC_CSTAT_32B_tag
Definition: fsl-mpc564xL.h:10371
CRC_INP_32B_tag
Definition: fsl-mpc564xL.h:10361
CRC_OUTP_32B_tag
Definition: fsl-mpc564xL.h:10381
CTU_CLCR1_32B_tag
Definition: fsl-mpc564xL.h:7608
CTU_CLCR2_32B_tag
Definition: fsl-mpc564xL.h:7622
CTU_CLR_DCM_16B_tag
Definition: fsl-mpc564xL.h:7715
CTU_CLR_SCM_16B_tag
Definition: fsl-mpc564xL.h:7732
CTU_CNT_RANGE_16B_tag
Definition: fsl-mpc564xL.h:8201
CTU_COTR_16B_tag
Definition: fsl-mpc564xL.h:8089
CTU_CR_16B_tag
Definition: fsl-mpc564xL.h:7750
CTU_CTUCR_16B_tag
Definition: fsl-mpc564xL.h:8101
CTU_CTUEFR_16B_tag
Definition: fsl-mpc564xL.h:7929
CTU_CTUIFR_16B_tag
Definition: fsl-mpc564xL.h:7969
CTU_CTUIR_16B_tag
Definition: fsl-mpc564xL.h:8028
CTU_EXPECTED_A_16B_tag
Definition: fsl-mpc564xL.h:8187
CTU_EXPECTED_B_16B_tag
Definition: fsl-mpc564xL.h:8194
CTU_FCR_32B_tag
Definition: fsl-mpc564xL.h:7804
CTU_FILTER_16B_tag
Definition: fsl-mpc564xL.h:8175
CTU_FLA_32B_tag
Definition: fsl-mpc564xL.h:8219
CTU_FL_32B_tag
Definition: fsl-mpc564xL.h:7917
CTU_FRA_32B_tag
Definition: fsl-mpc564xL.h:8212
CTU_FR_32B_tag
Definition: fsl-mpc564xL.h:7903
CTU_STS_32B_tag
Definition: fsl-mpc564xL.h:7862
CTU_TCR_16B_tag
Definition: fsl-mpc564xL.h:7586
CTU_TGSCCR_16B_tag
Definition: fsl-mpc564xL.h:7590
CTU_TGSCRR_16B_tag
Definition: fsl-mpc564xL.h:7599
CTU_TGSCR_16B_tag
Definition: fsl-mpc564xL.h:7563
CTU_TGSISR_32B_tag
Definition: fsl-mpc564xL.h:7525
CTU_TH1_32B_tag
Definition: fsl-mpc564xL.h:7842
CTU_TH2_32B_tag
Definition: fsl-mpc564xL.h:7852
CTU_THCR1_32B_tag
Definition: fsl-mpc564xL.h:7636
CTU_THCR2_32B_tag
Definition: fsl-mpc564xL.h:7674
DMA_CH_MUX_CHCONFIG_8B_tag
Definition: fsl-mpc564xL.h:18111
DSPI_ASDR_32B_tag
Definition: fsl-mpc564xL.h:16773
DSPI_COMPR_32B_tag
Definition: fsl-mpc564xL.h:16781
DSPI_CTAR_tag
Definition: fsl-mpc564xL.h:16586
DSPI_DDR_32B_tag
Definition: fsl-mpc564xL.h:16789
DSPI_DSICR1_32B_tag
Definition: fsl-mpc564xL.h:16797
DSPI_DSICR_32B_tag
Definition: fsl-mpc564xL.h:16740
DSPI_MCR_tag
Definition: fsl-mpc564xL.h:16541
DSPI_POPR_tag
Definition: fsl-mpc564xL.h:16698
DSPI_PUSHR_tag
Definition: fsl-mpc564xL.h:16678
DSPI_RSER_tag
Definition: fsl-mpc564xL.h:16627
DSPI_RXFR_32B_tag
Definition: fsl-mpc564xL.h:16728
DSPI_SDR_32B_tag
Definition: fsl-mpc564xL.h:16765
DSPI_SR_tag
Definition: fsl-mpc564xL.h:16605
DSPI_TCR_32B_tag
Definition: fsl-mpc564xL.h:16571
DSPI_TXFR_32B_tag
Definition: fsl-mpc564xL.h:16709
FCCU_AFFS_32B_tag
Definition: fsl-mpc564xL.h:11792
FCCU_CFF_32B_tag
Definition: fsl-mpc564xL.h:11827
FCCU_CFG_32B_tag
Definition: fsl-mpc564xL.h:10464
FCCU_CFG_TO_32B_tag
Definition: fsl-mpc564xL.h:11756
FCCU_CFK_32B_tag
Definition: fsl-mpc564xL.h:11288
FCCU_CFS0_32B_tag
Definition: fsl-mpc564xL.h:11136
FCCU_CFS1_32B_tag
Definition: fsl-mpc564xL.h:11174
FCCU_CFS2_32B_tag
Definition: fsl-mpc564xL.h:11212
FCCU_CFS3_32B_tag
Definition: fsl-mpc564xL.h:11250
FCCU_CFS_32B_tag
Definition: fsl-mpc564xL.h:11921
FCCU_CFS_CFG0_32B_tag
Definition: fsl-mpc564xL.h:10784
FCCU_CFS_CFG1_32B_tag
Definition: fsl-mpc564xL.h:10806
FCCU_CFS_CFG2_32B_tag
Definition: fsl-mpc564xL.h:10828
FCCU_CFS_CFG3_32B_tag
Definition: fsl-mpc564xL.h:10850
FCCU_CFS_CFG4_32B_tag
Definition: fsl-mpc564xL.h:10872
FCCU_CFS_CFG5_32B_tag
Definition: fsl-mpc564xL.h:10894
FCCU_CFS_CFG6_32B_tag
Definition: fsl-mpc564xL.h:10916
FCCU_CFS_CFG7_32B_tag
Definition: fsl-mpc564xL.h:10938
FCCU_CFS_CFG_32B_tag
Definition: fsl-mpc564xL.h:11907
FCCU_CF_CFG0_32B_tag
Definition: fsl-mpc564xL.h:10480
FCCU_CF_CFG1_32B_tag
Definition: fsl-mpc564xL.h:10518
FCCU_CF_CFG2_32B_tag
Definition: fsl-mpc564xL.h:10556
FCCU_CF_CFG3_32B_tag
Definition: fsl-mpc564xL.h:10594
FCCU_CF_CFG_32B_tag
Definition: fsl-mpc564xL.h:11893
FCCU_CTRLK_32B_tag
Definition: fsl-mpc564xL.h:10460
FCCU_CTRL_32B_tag
Definition: fsl-mpc564xL.h:10449
FCCU_EINOUT_32B_tag
Definition: fsl-mpc564xL.h:11764
FCCU_FAFS_32B_tag
Definition: fsl-mpc564xL.h:11810
FCCU_IRQ_EN_32B_tag
Definition: fsl-mpc564xL.h:11853
FCCU_IRQ_STAT_32B_tag
Definition: fsl-mpc564xL.h:11843
FCCU_MCS_32B_tag
Definition: fsl-mpc564xL.h:11868
FCCU_NAFS_32B_tag
Definition: fsl-mpc564xL.h:11784
FCCU_NCFE0_32B_tag
Definition: fsl-mpc564xL.h:11448
FCCU_NCFE1_32B_tag
Definition: fsl-mpc564xL.h:11486
FCCU_NCFE2_32B_tag
Definition: fsl-mpc564xL.h:11524
FCCU_NCFE3_32B_tag
Definition: fsl-mpc564xL.h:11562
FCCU_NCFE_32B_tag
Definition: fsl-mpc564xL.h:11935
FCCU_NCFF_32B_tag
Definition: fsl-mpc564xL.h:11835
FCCU_NCFK_32B_tag
Definition: fsl-mpc564xL.h:11444
FCCU_NCFS0_32B_tag
Definition: fsl-mpc564xL.h:11292
FCCU_NCFS1_32B_tag
Definition: fsl-mpc564xL.h:11330
FCCU_NCFS2_32B_tag
Definition: fsl-mpc564xL.h:11368
FCCU_NCFS3_32B_tag
Definition: fsl-mpc564xL.h:11406
FCCU_NCFS_32B_tag
Definition: fsl-mpc564xL.h:11928
FCCU_NCFS_CFG0_32B_tag
Definition: fsl-mpc564xL.h:10960
FCCU_NCFS_CFG1_32B_tag
Definition: fsl-mpc564xL.h:10982
FCCU_NCFS_CFG2_32B_tag
Definition: fsl-mpc564xL.h:11004
FCCU_NCFS_CFG3_32B_tag
Definition: fsl-mpc564xL.h:11026
FCCU_NCFS_CFG4_32B_tag
Definition: fsl-mpc564xL.h:11048
FCCU_NCFS_CFG5_32B_tag
Definition: fsl-mpc564xL.h:11070
FCCU_NCFS_CFG6_32B_tag
Definition: fsl-mpc564xL.h:11092
FCCU_NCFS_CFG7_32B_tag
Definition: fsl-mpc564xL.h:11114
FCCU_NCFS_CFG_32B_tag
Definition: fsl-mpc564xL.h:11914
FCCU_NCF_CFG0_32B_tag
Definition: fsl-mpc564xL.h:10632
FCCU_NCF_CFG1_32B_tag
Definition: fsl-mpc564xL.h:10670
FCCU_NCF_CFG2_32B_tag
Definition: fsl-mpc564xL.h:10708
FCCU_NCF_CFG3_32B_tag
Definition: fsl-mpc564xL.h:10746
FCCU_NCF_CFG_32B_tag
Definition: fsl-mpc564xL.h:11900
FCCU_NCF_TOE0_32B_tag
Definition: fsl-mpc564xL.h:11600
FCCU_NCF_TOE1_32B_tag
Definition: fsl-mpc564xL.h:11638
FCCU_NCF_TOE2_32B_tag
Definition: fsl-mpc564xL.h:11676
FCCU_NCF_TOE3_32B_tag
Definition: fsl-mpc564xL.h:11714
FCCU_NCF_TOE_32B_tag
Definition: fsl-mpc564xL.h:11942
FCCU_NCF_TO_32B_tag
Definition: fsl-mpc564xL.h:11752
FCCU_NFFS_32B_tag
Definition: fsl-mpc564xL.h:11801
FCCU_SCFS_32B_tag
Definition: fsl-mpc564xL.h:11818
FCCU_STAT_32B_tag
Definition: fsl-mpc564xL.h:11776
FCCU_XTMR_32B_tag
Definition: fsl-mpc564xL.h:11861
FLEXCAN_CTRL_32B_tag
Definition: fsl-mpc564xL.h:16956
FLEXCAN_ECR_32B_tag
Definition: fsl-mpc564xL.h:17034
FLEXCAN_ESR_32B_tag
Definition: fsl-mpc564xL.h:17051
FLEXCAN_IFLAG1_32B_tag
Definition: fsl-mpc564xL.h:17285
FLEXCAN_IFLAG2_32B_tag
Definition: fsl-mpc564xL.h:17247
FLEXCAN_IMASK1_32B_tag
Definition: fsl-mpc564xL.h:17169
FLEXCAN_IMASK2_32B_tag
Definition: fsl-mpc564xL.h:17131
FLEXCAN_MCR_32B_tag
Definition: fsl-mpc564xL.h:16891
FLEXCAN_MSG_CS_32B_tag
Definition: fsl-mpc564xL.h:17366
FLEXCAN_MSG_DATA2_32B_tag
Definition: fsl-mpc564xL.h:17401
FLEXCAN_MSG_DATA_32B_tag
Definition: fsl-mpc564xL.h:17395
FLEXCAN_MSG_ID_32B_tag
Definition: fsl-mpc564xL.h:17383
FLEXCAN_RX14MASK_32B_tag
Definition: fsl-mpc564xL.h:17016
FLEXCAN_RX15MASK_32B_tag
Definition: fsl-mpc564xL.h:17025
FLEXCAN_RXGMASK_32B_tag
Definition: fsl-mpc564xL.h:17007
FLEXCAN_RXIMR_32B_tag
Definition: fsl-mpc564xL.h:17413
FLEXCAN_TIMER_32B_tag
Definition: fsl-mpc564xL.h:17003
FR_CASERCR_16B_tag
Definition: fsl-mpc564xL.h:18681
FR_CBSERCR_16B_tag
Definition: fsl-mpc564xL.h:18688
FR_CHIERFR_16B_tag
Definition: fsl-mpc564xL.h:18585
FR_CIFR_16B_tag
Definition: fsl-mpc564xL.h:18815
FR_CYCTR_16B_tag
Definition: fsl-mpc564xL.h:18776
FR_EEIAR_16B_tag
Definition: fsl-mpc564xL.h:19688
FR_EEICR_16B_tag
Definition: fsl-mpc564xL.h:19704
FR_EEIDR_16B_tag
Definition: fsl-mpc564xL.h:19697
FR_EEIFER_16B_tag
Definition: fsl-mpc564xL.h:19631
FR_EERAR_16B_tag
Definition: fsl-mpc564xL.h:19664
FR_EERCR_16B_tag
Definition: fsl-mpc564xL.h:19680
FR_EERDR_16B_tag
Definition: fsl-mpc564xL.h:19673
FR_EERICR_16B_tag
Definition: fsl-mpc564xL.h:19650
FR_GIFER_16B_tag
Definition: fsl-mpc564xL.h:18270
FR_LDTXSLAR_16B_tag
Definition: fsl-mpc564xL.h:19283
FR_LDTXSLBR_16B_tag
Definition: fsl-mpc564xL.h:19291
FR_MBCCFR_16B_tag
Definition: fsl-mpc564xL.h:19738
FR_MBCCSR_16B_tag
Definition: fsl-mpc564xL.h:19715
FR_MBDSR_16B_tag
Definition: fsl-mpc564xL.h:18221
FR_MBFIDR_16B_tag
Definition: fsl-mpc564xL.h:19761
FR_MBIDXR_16B_tag
Definition: fsl-mpc564xL.h:19772
FR_MBIVEC_16B_tag
Definition: fsl-mpc564xL.h:18671
FR_MBSSUTR_16B_tag
Definition: fsl-mpc564xL.h:18231
FR_MCR_16B_tag
Definition: fsl-mpc564xL.h:18169
FR_MTCTR_16B_tag
Definition: fsl-mpc564xL.h:18768
FR_MTSACFR_16B_tag
Definition: fsl-mpc564xL.h:19143
FR_MTSBCFR_16B_tag
Definition: fsl-mpc564xL.h:19154
FR_MVR_16B_tag
Definition: fsl-mpc564xL.h:18161
FR_NMVLR_16B_tag
Definition: fsl-mpc564xL.h:18981
FR_NMVR0_16B_tag
Definition: fsl-mpc564xL.h:18933
FR_NMVR1_16B_tag
Definition: fsl-mpc564xL.h:18941
FR_NMVR2_16B_tag
Definition: fsl-mpc564xL.h:18949
FR_NMVR3_16B_tag
Definition: fsl-mpc564xL.h:18957
FR_NMVR4_16B_tag
Definition: fsl-mpc564xL.h:18965
FR_NMVR5_16B_tag
Definition: fsl-mpc564xL.h:18973
FR_NMVR_16B_tag
Definition: fsl-mpc564xL.h:19783
FR_OFCORVR_16B_tag
Definition: fsl-mpc564xL.h:18807
FR_PCR0_16B_tag
Definition: fsl-mpc564xL.h:19299
FR_PCR10_16B_tag
Definition: fsl-mpc564xL.h:19388
FR_PCR11_16B_tag
Definition: fsl-mpc564xL.h:19397
FR_PCR12_16B_tag
Definition: fsl-mpc564xL.h:19406
FR_PCR13_16B_tag
Definition: fsl-mpc564xL.h:19414
FR_PCR14_16B_tag
Definition: fsl-mpc564xL.h:19422
FR_PCR15_16B_tag
Definition: fsl-mpc564xL.h:19434
FR_PCR16_16B_tag
Definition: fsl-mpc564xL.h:19445
FR_PCR17_16B_tag
Definition: fsl-mpc564xL.h:19457
FR_PCR18_16B_tag
Definition: fsl-mpc564xL.h:19468
FR_PCR19_16B_tag
Definition: fsl-mpc564xL.h:19476
FR_PCR1_16B_tag
Definition: fsl-mpc564xL.h:19307
FR_PCR20_16B_tag
Definition: fsl-mpc564xL.h:19484
FR_PCR21_16B_tag
Definition: fsl-mpc564xL.h:19492
FR_PCR22_16B_tag
Definition: fsl-mpc564xL.h:19500
FR_PCR23_16B_tag
Definition: fsl-mpc564xL.h:19517
FR_PCR24_16B_tag
Definition: fsl-mpc564xL.h:19528
FR_PCR25_16B_tag
Definition: fsl-mpc564xL.h:19541
FR_PCR26_16B_tag
Definition: fsl-mpc564xL.h:19552
FR_PCR27_16B_tag
Definition: fsl-mpc564xL.h:19565
FR_PCR28_16B_tag
Definition: fsl-mpc564xL.h:19576
FR_PCR29_16B_tag
Definition: fsl-mpc564xL.h:19584
FR_PCR2_16B_tag
Definition: fsl-mpc564xL.h:19315
FR_PCR30_16B_tag
Definition: fsl-mpc564xL.h:19592
FR_PCR3_16B_tag
Definition: fsl-mpc564xL.h:19323
FR_PCR4_16B_tag
Definition: fsl-mpc564xL.h:19336
FR_PCR5_16B_tag
Definition: fsl-mpc564xL.h:19344
FR_PCR6_16B_tag
Definition: fsl-mpc564xL.h:19353
FR_PCR7_16B_tag
Definition: fsl-mpc564xL.h:19362
FR_PCR8_16B_tag
Definition: fsl-mpc564xL.h:19370
FR_PCR9_16B_tag
Definition: fsl-mpc564xL.h:19379
FR_PEDRAR_16B_tag
Definition: fsl-mpc564xL.h:18241
FR_PEDRDR_16B_tag
Definition: fsl-mpc564xL.h:18250
FR_PIER0_16B_tag
Definition: fsl-mpc564xL.h:18452
FR_PIER1_16B_tag
Definition: fsl-mpc564xL.h:18538
FR_PIFR0_16B_tag
Definition: fsl-mpc564xL.h:18308
FR_PIFR1_16B_tag
Definition: fsl-mpc564xL.h:18394
FR_POCR_16B_tag
Definition: fsl-mpc564xL.h:18257
FR_PSR0_16B_tag
Definition: fsl-mpc564xL.h:18695
FR_PSR1_16B_tag
Definition: fsl-mpc564xL.h:18711
FR_PSR2_16B_tag
Definition: fsl-mpc564xL.h:18725
FR_PSR3_16B_tag
Definition: fsl-mpc564xL.h:18748
FR_RFARIR_16B_tag
Definition: fsl-mpc564xL.h:19210
FR_RFBRIR_16B_tag
Definition: fsl-mpc564xL.h:19218
FR_RFDSR_16B_tag
Definition: fsl-mpc564xL.h:19193
FR_RFFIDRFMR_16B_tag
Definition: fsl-mpc564xL.h:19248
FR_RFFIDRFVR_16B_tag
Definition: fsl-mpc564xL.h:19240
FR_RFFLPCR_16B_tag
Definition: fsl-mpc564xL.h:19623
FR_RFMIDAFMR_16B_tag
Definition: fsl-mpc564xL.h:19233
FR_RFMIDAFVR_16B_tag
Definition: fsl-mpc564xL.h:19226
FR_RFPTR_16B_tag
Definition: fsl-mpc564xL.h:19615
FR_RFRFCFR_16B_tag
Definition: fsl-mpc564xL.h:19256
FR_RFRFCTR_16B_tag
Definition: fsl-mpc564xL.h:19267
FR_RFSYMBHADR_16B_tag
Definition: fsl-mpc564xL.h:19600
FR_RFSYMBLADR_16B_tag
Definition: fsl-mpc564xL.h:19607
FR_RFWMSR_16B_tag
Definition: fsl-mpc564xL.h:19176
FR_RF_RFSIR_16B_tag
Definition: fsl-mpc564xL.h:19185
FR_RSBIR_16B_tag
Definition: fsl-mpc564xL.h:19165
FR_RTCORVR_16B_tag
Definition: fsl-mpc564xL.h:18800
FR_SFCNTR_16B_tag
Definition: fsl-mpc564xL.h:18870
FR_SFIDAFMR_16B_tag
Definition: fsl-mpc564xL.h:18925
FR_SFIDAFVR_16B_tag
Definition: fsl-mpc564xL.h:18917
FR_SFIDRFR_16B_tag
Definition: fsl-mpc564xL.h:18909
FR_SFTCCSR_16B_tag
Definition: fsl-mpc564xL.h:18888
FR_SFTOR_16B_tag
Definition: fsl-mpc564xL.h:18880
FR_SLTCTAR_16B_tag
Definition: fsl-mpc564xL.h:18784
FR_SLTCTBR_16B_tag
Definition: fsl-mpc564xL.h:18792
FR_SSCCR_16B_tag
Definition: fsl-mpc564xL.h:19074
FR_SSCR0_16B_tag
Definition: fsl-mpc564xL.h:19115
FR_SSCR1_16B_tag
Definition: fsl-mpc564xL.h:19122
FR_SSCR2_16B_tag
Definition: fsl-mpc564xL.h:19129
FR_SSCR3_16B_tag
Definition: fsl-mpc564xL.h:19136
FR_SSCR_16B_tag
Definition: fsl-mpc564xL.h:19792
FR_SSR_16B_tag
Definition: fsl-mpc564xL.h:19091
FR_SSSR_16B_tag
Definition: fsl-mpc564xL.h:19063
FR_STBSCR_16B_tag
Definition: fsl-mpc564xL.h:18208
FR_SYMATOR_16B_tag
Definition: fsl-mpc564xL.h:18862
FR_SYMBADHR_16B_tag
Definition: fsl-mpc564xL.h:18193
FR_SYMBADLR_16B_tag
Definition: fsl-mpc564xL.h:18200
FR_TI1CYSR_16B_tag
Definition: fsl-mpc564xL.h:19020
FR_TI1MTOR_16B_tag
Definition: fsl-mpc564xL.h:19038
FR_TI2CR0_16B_tag
Definition: fsl-mpc564xL.h:19046
FR_TI2CR1_16B_tag
Definition: fsl-mpc564xL.h:19056
FR_TICCR_16B_tag
Definition: fsl-mpc564xL.h:18989
INTC_BCR_32B_tag
Definition: fsl-mpc564xL.h:15656
INTC_CPR_PRC0_32B_tag
Definition: fsl-mpc564xL.h:15678
INTC_CPR_PRC1_32B_tag
Definition: fsl-mpc564xL.h:15686
INTC_EOIR_PRC0_32B_tag
Definition: fsl-mpc564xL.h:15720
INTC_EOIR_PRC1_32B_tag
Definition: fsl-mpc564xL.h:15724
INTC_IACKR_PRC0_32B_tag
Definition: fsl-mpc564xL.h:15694
INTC_IACKR_PRC1_32B_tag
Definition: fsl-mpc564xL.h:15711
INTC_PSR_32B_tag
Definition: fsl-mpc564xL.h:15791
INTC_PSR_8B_tag
Definition: fsl-mpc564xL.h:15779
INTC_SSCIR0_3_32B_tag
Definition: fsl-mpc564xL.h:15740
INTC_SSCIR4_7_32B_tag
Definition: fsl-mpc564xL.h:15758
INTC_SSCIR_8B_tag
Definition: fsl-mpc564xL.h:15731
LINFLEX_BDRL_32B_tag
Definition: fsl-mpc564xL.h:10155
LINFLEX_BDRM_32B_tag
Definition: fsl-mpc564xL.h:10165
LINFLEX_BIDR_32B_tag
Definition: fsl-mpc564xL.h:10143
LINFLEX_DMARXE_32B_tag
Definition: fsl-mpc564xL.h:10251
LINFLEX_DMATXE_32B_tag
Definition: fsl-mpc564xL.h:10243
LINFLEX_GCR_32B_tag
Definition: fsl-mpc564xL.h:10214
LINFLEX_IFCR_32B_tag
Definition: fsl-mpc564xL.h:10202
LINFLEX_IFER_32B_tag
Definition: fsl-mpc564xL.h:10175
LINFLEX_IFMI_32B_tag
Definition: fsl-mpc564xL.h:10183
LINFLEX_IFMR_32B_tag
Definition: fsl-mpc564xL.h:10191
LINFLEX_LINCFR_32B_tag
Definition: fsl-mpc564xL.h:10120
LINFLEX_LINCR1_32B_tag
Definition: fsl-mpc564xL.h:9900
LINFLEX_LINCR2_32B_tag
Definition: fsl-mpc564xL.h:10128
LINFLEX_LINESR_32B_tag
Definition: fsl-mpc564xL.h:9985
LINFLEX_LINFBRR_32B_tag
Definition: fsl-mpc564xL.h:10096
LINFLEX_LINIBRR_32B_tag
Definition: fsl-mpc564xL.h:10108
LINFLEX_LINIER_32B_tag
Definition: fsl-mpc564xL.h:9932
LINFLEX_LINOCR_32B_tag
Definition: fsl-mpc564xL.h:10077
LINFLEX_LINSR_32B_tag
Definition: fsl-mpc564xL.h:9958
LINFLEX_LINTCSR_32B_tag
Definition: fsl-mpc564xL.h:10062
LINFLEX_LINTOCR_32B_tag
Definition: fsl-mpc564xL.h:10086
LINFLEX_UARTCR_32B_tag
Definition: fsl-mpc564xL.h:10007
LINFLEX_UARTCTO_32B_tag
Definition: fsl-mpc564xL.h:10235
LINFLEX_UARTPTO_32B_tag
Definition: fsl-mpc564xL.h:10227
LINFLEX_UARTSR_32B_tag
Definition: fsl-mpc564xL.h:10034
MAX_ASGPCR_32B_tag
Definition: fsl-mpc564xL.h:12938
MAX_MGPCR_32B_tag
Definition: fsl-mpc564xL.h:12964
MAX_MPR_32B_tag
Definition: fsl-mpc564xL.h:12884
MAX_SGPCR_32B_tag
Definition: fsl-mpc564xL.h:12912
ME_DMTS_32B_tag
Definition: fsl-mpc564xL.h:3923
ME_DRUN_MC_32B_tag
Definition: fsl-mpc564xL.h:4018
ME_GS_32B_tag
Definition: fsl-mpc564xL.h:3802
ME_HALT0_MC_32B_tag
Definition: fsl-mpc564xL.h:4089
ME_IMTS_32B_tag
Definition: fsl-mpc564xL.h:3911
ME_IM_32B_tag
Definition: fsl-mpc564xL.h:3888
ME_IS_32B_tag
Definition: fsl-mpc564xL.h:3865
ME_LP_PC_32B_tag
Definition: fsl-mpc564xL.h:4261
ME_MCTL_32B_tag
Definition: fsl-mpc564xL.h:3838
ME_MEN_32B_tag
Definition: fsl-mpc564xL.h:3847
ME_PCTL_8B_tag
Definition: fsl-mpc564xL.h:4275
ME_PS0_32B_tag
Definition: fsl-mpc564xL.h:4191
ME_PS1_32B_tag
Definition: fsl-mpc564xL.h:4207
ME_PS2_32B_tag
Definition: fsl-mpc564xL.h:4231
ME_PS_32B_tag
Definition: fsl-mpc564xL.h:4290
ME_RESET_MC_32B_tag
Definition: fsl-mpc564xL.h:3950
ME_RUN_MC_32B_tag
Definition: fsl-mpc564xL.h:4055
ME_RUN_PC_32B_tag
Definition: fsl-mpc564xL.h:4243
ME_SAFE_MC_32B_tag
Definition: fsl-mpc564xL.h:3984
ME_STANDBY0_MC_32B_tag
Definition: fsl-mpc564xL.h:4157
ME_STOP0_MC_32B_tag
Definition: fsl-mpc564xL.h:4123
MPU_CESR_32B_tag
Definition: fsl-mpc564xL.h:13124
MPU_EAR_32B_tag
Definition: fsl-mpc564xL.h:13140
MPU_EDR_32B_tag
Definition: fsl-mpc564xL.h:13150
MPU_RGDAAC_32B_tag
Definition: fsl-mpc564xL.h:13228
MPU_RGD_WORD0_32B_tag
Definition: fsl-mpc564xL.h:13164
MPU_RGD_WORD1_32B_tag
Definition: fsl-mpc564xL.h:13175
MPU_RGD_WORD2_32B_tag
Definition: fsl-mpc564xL.h:13186
MPU_RGD_WORD3_32B_tag
Definition: fsl-mpc564xL.h:13215
OSC_CTL_32B_tag
Definition: fsl-mpc564xL.h:4599
PBRIDGE_MPROT_32B_tag
Definition: fsl-mpc564xL.h:12183
PBRIDGE_OPACR0_7_32B_tag
Definition: fsl-mpc564xL.h:12373
PBRIDGE_OPACR16_23_32B_tag
Definition: fsl-mpc564xL.h:12449
PBRIDGE_OPACR24_31_32B_tag
Definition: fsl-mpc564xL.h:12487
PBRIDGE_OPACR32_39_32B_tag
Definition: fsl-mpc564xL.h:12525
PBRIDGE_OPACR40_47_32B_tag
Definition: fsl-mpc564xL.h:12563
PBRIDGE_OPACR48_55_32B_tag
Definition: fsl-mpc564xL.h:12601
PBRIDGE_OPACR56_63_32B_tag
Definition: fsl-mpc564xL.h:12639
PBRIDGE_OPACR64_71_32B_tag
Definition: fsl-mpc564xL.h:12677
PBRIDGE_OPACR72_79_32B_tag
Definition: fsl-mpc564xL.h:12715
PBRIDGE_OPACR80_87_32B_tag
Definition: fsl-mpc564xL.h:12753
PBRIDGE_OPACR88_95_32B_tag
Definition: fsl-mpc564xL.h:12791
PBRIDGE_OPACR8_15_32B_tag
Definition: fsl-mpc564xL.h:12411
PBRIDGE_PACR0_7_32B_tag
Definition: fsl-mpc564xL.h:12221
PBRIDGE_PACR16_23_32B_tag
Definition: fsl-mpc564xL.h:12297
PBRIDGE_PACR24_31_32B_tag
Definition: fsl-mpc564xL.h:12335
PBRIDGE_PACR8_15_32B_tag
Definition: fsl-mpc564xL.h:12259
PCU_PCONF_32B_tag
Definition: fsl-mpc564xL.h:5295
PCU_PSTAT_32B_tag
Definition: fsl-mpc564xL.h:5315
PIT_RTI_CVAL_32B_tag
Definition: fsl-mpc564xL.h:5566
PIT_RTI_LDVAL_32B_tag
Definition: fsl-mpc564xL.h:5556
PIT_RTI_PITMCR_32B_tag
Definition: fsl-mpc564xL.h:5544
PIT_RTI_TCTRL_32B_tag
Definition: fsl-mpc564xL.h:5576
PIT_RTI_TFLG_32B_tag
Definition: fsl-mpc564xL.h:5588
PLLD_CR_32B_tag
Definition: fsl-mpc564xL.h:4663
PLLD_MR_32B_tag
Definition: fsl-mpc564xL.h:4684
PMUCTRL_CTRL_32B_tag
Definition: fsl-mpc564xL.h:5437
PMUCTRL_FAULT_32B_tag
Definition: fsl-mpc564xL.h:5453
PMUCTRL_IRQE_32B_tag
Definition: fsl-mpc564xL.h:5486
PMUCTRL_IRQS_32B_tag
Definition: fsl-mpc564xL.h:5468
PMUCTRL_MASKF_32B_tag
Definition: fsl-mpc564xL.h:5445
PMUCTRL_STATEREG_32B_tag
Definition: fsl-mpc564xL.h:5415
PMUCTRL_STATHVD_32B_tag
Definition: fsl-mpc564xL.h:5381
PMUCTRL_STATIREG_32B_tag
Definition: fsl-mpc564xL.h:5407
PMUCTRL_STATLVD_32B_tag
Definition: fsl-mpc564xL.h:5394
PMUCTRL_STATUS_32B_tag
Definition: fsl-mpc564xL.h:5423
RC_CTL_32B_tag
Definition: fsl-mpc564xL.h:4632
RGM_DERD_16B_tag
Definition: fsl-mpc564xL.h:5167
RGM_DES_16B_tag
Definition: fsl-mpc564xL.h:5118
RGM_FBRE_16B_tag
Definition: fsl-mpc564xL.h:5233
RGM_FEAR_16B_tag
Definition: fsl-mpc564xL.h:5185
RGM_FERD_16B_tag
Definition: fsl-mpc564xL.h:5141
RGM_FESS_16B_tag
Definition: fsl-mpc564xL.h:5207
RGM_FES_16B_tag
Definition: fsl-mpc564xL.h:5092
SEMA4_CP0INE_16B_tag
Definition: fsl-mpc564xL.h:13493
SEMA4_CP0NTF_16B_tag
Definition: fsl-mpc564xL.h:13507
SEMA4_CP1INE_16B_tag
Definition: fsl-mpc564xL.h:13500
SEMA4_CP1NTF_16B_tag
Definition: fsl-mpc564xL.h:13514
SEMA4_GATE_8B_tag
Definition: fsl-mpc564xL.h:13485
SEMA4_RSTGT_16B_tag
Definition: fsl-mpc564xL.h:13521
SEMA4_RSTNTF_16B_tag
Definition: fsl-mpc564xL.h:13532
SGENDIG_CTRL_32B_tag
Definition: fsl-mpc564xL.h:12138
SGENDIG_IRQE_32B_tag
Definition: fsl-mpc564xL.h:12152
SIUL_GPDI_32B_tag
Definition: fsl-mpc564xL.h:1063
SIUL_GPDI_8B_tag
Definition: fsl-mpc564xL.h:1052
SIUL_GPDO_32B_tag
Definition: fsl-mpc564xL.h:1035
SIUL_GPDO_8B_tag
Definition: fsl-mpc564xL.h:1024
SIUL_IFCPR_32B_tag
Definition: fsl-mpc564xL.h:1113
SIUL_IFEER_32B_tag
Definition: fsl-mpc564xL.h:887
SIUL_IFER_32B_tag
Definition: fsl-mpc564xL.h:925
SIUL_IFMC_32B_tag
Definition: fsl-mpc564xL.h:1105
SIUL_IREER_32B_tag
Definition: fsl-mpc564xL.h:849
SIUL_IRER_32B_tag
Definition: fsl-mpc564xL.h:811
SIUL_ISR_32B_tag
Definition: fsl-mpc564xL.h:773
SIUL_MIDR1_32B_tag
Definition: fsl-mpc564xL.h:733
SIUL_MIDR2_32B_tag
Definition: fsl-mpc564xL.h:753
SIUL_MPGPDO_32B_tag
Definition: fsl-mpc564xL.h:1094
SIUL_PGPDI_16B_tag
Definition: fsl-mpc564xL.h:1087
SIUL_PGPDO_16B_tag
Definition: fsl-mpc564xL.h:1080
SIUL_PSMI_32B_tag
Definition: fsl-mpc564xL.h:1007
SIUL_PSMI_8B_tag
Definition: fsl-mpc564xL.h:996
SIU_PCR_tag
Definition: fsl-mpc564xL.h:966
SPP_DMA2_DCHPRI_8B_tag
Definition: fsl-mpc564xL.h:14354
SPP_DMA2_DMACDNE_8B_tag
Definition: fsl-mpc564xL.h:14294
SPP_DMA2_DMACEEI_8B_tag
Definition: fsl-mpc564xL.h:14262
SPP_DMA2_DMACERQ_8B_tag
Definition: fsl-mpc564xL.h:14246
SPP_DMA2_DMACERR_8B_tag
Definition: fsl-mpc564xL.h:14278
SPP_DMA2_DMACINT_8B_tag
Definition: fsl-mpc564xL.h:14270
SPP_DMA2_DMACR_32B_tag
Definition: fsl-mpc564xL.h:14169
SPP_DMA2_DMAEEIH_32B_tag
Definition: fsl-mpc564xL.h:14224
SPP_DMA2_DMAEEIL_32B_tag
Definition: fsl-mpc564xL.h:14231
SPP_DMA2_DMAERQH_32B_tag
Definition: fsl-mpc564xL.h:14210
SPP_DMA2_DMAERQL_32B_tag
Definition: fsl-mpc564xL.h:14217
SPP_DMA2_DMAERRH_32B_tag
Definition: fsl-mpc564xL.h:14316
SPP_DMA2_DMAERRL_32B_tag
Definition: fsl-mpc564xL.h:14323
SPP_DMA2_DMAES_32B_tag
Definition: fsl-mpc564xL.h:14190
SPP_DMA2_DMAGPOR_32B_tag
Definition: fsl-mpc564xL.h:14344
SPP_DMA2_DMAHRSH_32B_tag
Definition: fsl-mpc564xL.h:14330
SPP_DMA2_DMAHRSL_32B_tag
Definition: fsl-mpc564xL.h:14337
SPP_DMA2_DMAINTH_32B_tag
Definition: fsl-mpc564xL.h:14302
SPP_DMA2_DMAINTL_32B_tag
Definition: fsl-mpc564xL.h:14309
SPP_DMA2_DMASEEI_8B_tag
Definition: fsl-mpc564xL.h:14254
SPP_DMA2_DMASERQ_8B_tag
Definition: fsl-mpc564xL.h:14238
SPP_DMA2_DMASSRT_8B_tag
Definition: fsl-mpc564xL.h:14286
SPP_DMA2_TCDWORD0__32B_tag
Definition: fsl-mpc564xL.h:14367
SPP_DMA2_TCDWORD12__32B_tag
Definition: fsl-mpc564xL.h:14404
SPP_DMA2_TCDWORD16__32B_tag
Definition: fsl-mpc564xL.h:14414
SPP_DMA2_TCDWORD20__32B_tag
Definition: fsl-mpc564xL.h:14424
SPP_DMA2_TCDWORD24__32B_tag
Definition: fsl-mpc564xL.h:14437
SPP_DMA2_TCDWORD28__32B_tag
Definition: fsl-mpc564xL.h:14447
SPP_DMA2_TCDWORD4__32B_tag
Definition: fsl-mpc564xL.h:14377
SPP_DMA2_TCDWORD8__32B_tag
Definition: fsl-mpc564xL.h:14391
SPP_MCM_ECR_8B_tag
Definition: fsl-mpc564xL.h:13888
SPP_MCM_EEGR_16B_tag
Definition: fsl-mpc564xL.h:13944
SPP_MCM_ESR_8B_tag
Definition: fsl-mpc564xL.h:13916
SPP_MCM_IOPMC_32B_tag
Definition: fsl-mpc564xL.h:13839
SPP_MCM_MIR_8B_tag
Definition: fsl-mpc564xL.h:13868
SPP_MCM_MRSR_8B_tag
Definition: fsl-mpc564xL.h:13846
SPP_MCM_MUDCR_32B_tag
Definition: fsl-mpc564xL.h:13881
SPP_MCM_MWCR_8B_tag
Definition: fsl-mpc564xL.h:13859
SPP_MCM_PCT_16B_tag
Definition: fsl-mpc564xL.h:13825
SPP_MCM_PFEAR_32B_tag
Definition: fsl-mpc564xL.h:13959
SPP_MCM_PFEAT_8B_tag
Definition: fsl-mpc564xL.h:13967
SPP_MCM_PFEDRH_32B_tag
Definition: fsl-mpc564xL.h:13988
SPP_MCM_PFEDR_32B_tag
Definition: fsl-mpc564xL.h:13992
SPP_MCM_PFEMR_8B_tag
Definition: fsl-mpc564xL.h:13963
SPP_MCM_PLREV_16B_tag
Definition: fsl-mpc564xL.h:13832
SPP_MCM_PREAR_32B_tag
Definition: fsl-mpc564xL.h:13996
SPP_MCM_PREAT_8B_tag
Definition: fsl-mpc564xL.h:14016
SPP_MCM_PREDRH_32B_tag
Definition: fsl-mpc564xL.h:14037
SPP_MCM_PREDR_32B_tag
Definition: fsl-mpc564xL.h:14041
SPP_MCM_PREMR_8B_tag
Definition: fsl-mpc564xL.h:14004
SPP_MCM_PRESR_8B_tag
Definition: fsl-mpc564xL.h:14000
SSCM_DEBUGPORT_16B_tag
Definition: fsl-mpc564xL.h:3672
SSCM_DPMBOOT_32B_tag
Definition: fsl-mpc564xL.h:3694
SSCM_DPMKEY_32B_tag
Definition: fsl-mpc564xL.h:3703
SSCM_ERROR_16B_tag
Definition: fsl-mpc564xL.h:3663
SSCM_MEMCONFIG_16B_tag
Definition: fsl-mpc564xL.h:3653
SSCM_PWCMPH_32B_tag
Definition: fsl-mpc564xL.h:3680
SSCM_PWCMPL_32B_tag
Definition: fsl-mpc564xL.h:3687
SSCM_SCTR_32B_tag
Definition: fsl-mpc564xL.h:3717
SSCM_STATUS_16B_tag
Definition: fsl-mpc564xL.h:3636
SSCM_TF_INFO0_32B_tag
Definition: fsl-mpc564xL.h:3727
SSCM_TF_INFO1_32B_tag
Definition: fsl-mpc564xL.h:3734
SSCM_TF_INFO2_32B_tag
Definition: fsl-mpc564xL.h:3741
SSCM_TF_INFO3_32B_tag
Definition: fsl-mpc564xL.h:3748
SSCM_UOPS_32B_tag
Definition: fsl-mpc564xL.h:3710
STM_CCR_32B_tag
Definition: fsl-mpc564xL.h:13720
STM_CIR_32B_tag
Definition: fsl-mpc564xL.h:13731
STM_CMP_32B_tag
Definition: fsl-mpc564xL.h:13742
STM_CNT_32B_tag
Definition: fsl-mpc564xL.h:13713
STM_CR_32B_tag
Definition: fsl-mpc564xL.h:13702
SWT_CO_32B_tag
Definition: fsl-mpc564xL.h:13657
SWT_CR_32B_tag
Definition: fsl-mpc564xL.h:13602
SWT_IR_32B_tag
Definition: fsl-mpc564xL.h:13627
SWT_SK_32B_tag
Definition: fsl-mpc564xL.h:13664
SWT_SR_32B_tag
Definition: fsl-mpc564xL.h:13649
SWT_TO_32B_tag
Definition: fsl-mpc564xL.h:13635
SWT_WN_32B_tag
Definition: fsl-mpc564xL.h:13642
WKPU_IRER_32B_tag
Definition: fsl-mpc564xL.h:3557
WKPU_NCR_32B_tag
Definition: fsl-mpc564xL.h:3516
WKPU_NSR_32B_tag
Definition: fsl-mpc564xL.h:3498
WKPU_WIFEER_32B_tag
Definition: fsl-mpc564xL.h:3578
WKPU_WIFER_32B_tag
Definition: fsl-mpc564xL.h:3585
WKPU_WIPUER_32B_tag
Definition: fsl-mpc564xL.h:3592
WKPU_WIREER_32B_tag
Definition: fsl-mpc564xL.h:3571
WKPU_WISR_32B_tag
Definition: fsl-mpc564xL.h:3550
WKPU_WRER_32B_tag
Definition: fsl-mpc564xL.h:3564
mcPWM_CAPTCMPX_16B_tag
Definition: fsl-mpc564xL.h:9286
mcPWM_CAPTCTRLX_16B_tag
Definition: fsl-mpc564xL.h:9260
mcPWM_CNT_16B_tag
Definition: fsl-mpc564xL.h:9030
mcPWM_CTRL1_16B_tag
Definition: fsl-mpc564xL.h:9073
mcPWM_CTRL2_16B_tag
Definition: fsl-mpc564xL.h:9044
mcPWM_CVAL0CYC_16B_tag
Definition: fsl-mpc564xL.h:9307
mcPWM_CVAL0_16B_tag
Definition: fsl-mpc564xL.h:9297
mcPWM_CVAL1CYC_16B_tag
Definition: fsl-mpc564xL.h:9328
mcPWM_CVAL1_16B_tag
Definition: fsl-mpc564xL.h:9318
mcPWM_CVAL3CYC_16B_tag
Definition: fsl-mpc564xL.h:9349
mcPWM_CVAL3_16B_tag
Definition: fsl-mpc564xL.h:9339
mcPWM_CVAL4CYC_16B_tag
Definition: fsl-mpc564xL.h:9370
mcPWM_CVAL4_16B_tag
Definition: fsl-mpc564xL.h:9360
mcPWM_CVAL5CYC_16B_tag
Definition: fsl-mpc564xL.h:9391
mcPWM_CVAL5_16B_tag
Definition: fsl-mpc564xL.h:9381
mcPWM_DISMAP_16B_tag
Definition: fsl-mpc564xL.h:9226
mcPWM_DMAEN_16B_tag
Definition: fsl-mpc564xL.h:9196
mcPWM_DTCNT0_16B_tag
Definition: fsl-mpc564xL.h:9239
mcPWM_DTCNT1_16B_tag
Definition: fsl-mpc564xL.h:9250
mcPWM_DTSRCSEL_16B_tag
Definition: fsl-mpc564xL.h:9466
mcPWM_FCTRL_16B_tag
Definition: fsl-mpc564xL.h:9526
mcPWM_FFILT_16B_tag
Definition: fsl-mpc564xL.h:9547
mcPWM_FSTS_16B_tag
Definition: fsl-mpc564xL.h:9536
mcPWM_INIT_16B_tag
Definition: fsl-mpc564xL.h:9037
mcPWM_INTEN_16B_tag
Definition: fsl-mpc564xL.h:9177
mcPWM_MASK_16B_tag
Definition: fsl-mpc564xL.h:9409
mcPWM_MCTRL_16B_tag
Definition: fsl-mpc564xL.h:9512
mcPWM_OCTRL_16B_tag
Definition: fsl-mpc564xL.h:9137
mcPWM_OUTEN_16B_tag
Definition: fsl-mpc564xL.h:9399
mcPWM_STS_16B_tag
Definition: fsl-mpc564xL.h:9157
mcPWM_SWCOUT_16B_tag
Definition: fsl-mpc564xL.h:9419
mcPWM_TCTRL_16B_tag
Definition: fsl-mpc564xL.h:9215
mcPWM_VAL_0_16B_tag
Definition: fsl-mpc564xL.h:9096
mcPWM_VAL_16B_tag
Definition: fsl-mpc564xL.h:9559
mcPWM_VAL_1_16B_tag
Definition: fsl-mpc564xL.h:9103
mcPWM_VAL_2_16B_tag
Definition: fsl-mpc564xL.h:9110
mcPWM_VAL_3_16B_tag
Definition: fsl-mpc564xL.h:9117
mcPWM_VAL_4_16B_tag
Definition: fsl-mpc564xL.h:9124
mcPWM_VAL_5_16B_tag
Definition: fsl-mpc564xL.h:9131
mcTIMER_CAPT1_16B_tag
Definition: fsl-mpc564xL.h:8440
mcTIMER_CAPT2_16B_tag
Definition: fsl-mpc564xL.h:8450
mcTIMER_CCCTRL_16B_tag
Definition: fsl-mpc564xL.h:8606
mcTIMER_CMPLD1_16B_tag
Definition: fsl-mpc564xL.h:8586
mcTIMER_CMPLD2_16B_tag
Definition: fsl-mpc564xL.h:8596
mcTIMER_CNTR_16B_tag
Definition: fsl-mpc564xL.h:8480
mcTIMER_COMP1_16B_tag
Definition: fsl-mpc564xL.h:8420
mcTIMER_COMP2_16B_tag
Definition: fsl-mpc564xL.h:8430
mcTIMER_CTRL1_16B_tag
Definition: fsl-mpc564xL.h:8490
mcTIMER_CTRL2_16B_tag
Definition: fsl-mpc564xL.h:8505
mcTIMER_CTRL3_16B_tag
Definition: fsl-mpc564xL.h:8526
mcTIMER_DREQ0_16B_tag
Definition: fsl-mpc564xL.h:8700
mcTIMER_DREQ1_16B_tag
Definition: fsl-mpc564xL.h:8708
mcTIMER_DREQ2_16B_tag
Definition: fsl-mpc564xL.h:8716
mcTIMER_DREQ3_16B_tag
Definition: fsl-mpc564xL.h:8724
mcTIMER_DREQ_16B_tag
Definition: fsl-mpc564xL.h:8735
mcTIMER_ENBL_16B_tag
Definition: fsl-mpc564xL.h:8692
mcTIMER_FCTRL_16B_tag
Definition: fsl-mpc564xL.h:8654
mcTIMER_FFILT_16B_tag
Definition: fsl-mpc564xL.h:8675
mcTIMER_FILT_16B_tag
Definition: fsl-mpc564xL.h:8623
mcTIMER_FSTS_16B_tag
Definition: fsl-mpc564xL.h:8665
mcTIMER_HOLD_16B_tag
Definition: fsl-mpc564xL.h:8470
mcTIMER_INTDMA_16B_tag
Definition: fsl-mpc564xL.h:8562
mcTIMER_LOAD_16B_tag
Definition: fsl-mpc564xL.h:8460
mcTIMER_STS_16B_tag
Definition: fsl-mpc564xL.h:8542
mcTIMER_WDTOH_16B_tag
Definition: fsl-mpc564xL.h:8647
mcTIMER_WDTOL_16B_tag
Definition: fsl-mpc564xL.h:8640