RTEMS: bsps/i386/pc386/net/3c509.h Source File

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3c509.h
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1
9/*
10 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are
14 * met: 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer. 2. The name
16 * of the author may not be used to endorse or promote products derived from
17 * this software without specific prior written permission
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
22 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
24 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
25 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
26 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
27 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by:
31 *
32 October 2, 1994
33
34 Modified by: Andres Vega Garcia
35
36 INRIA - Sophia Antipolis, France
37 e-mail: avega@sophia.inria.fr
38 finger: avega@pax.inria.fr
39
40 */
41/*
42 * Promiscuous mode added and interrupt logic slightly changed
43 * to reduce the number of adapter failures. Transceiver select
44 * logic changed to use value from EEPROM. Autoconfiguration
45 * features added.
46 * Done by:
47 * Serge Babkin
48 * Chelindbank (Chelyabinsk, Russia)
49 * babkin@hq.icb.chel.su
50 */
51
52/*
53 * Pccard support for 3C589 by:
54 * HAMADA Naoki
55 * nao@tom-yam.or.jp
56 */
57
66/*
67typedef unsigned short u_short;
68typedef unsigned long u_long;
69typedef unsigned char u_char;
70*/
71
72/*
73 * Some global constants
74 */
75#define F_RX_FIRST 0x1
76#define F_PROMISC 0x8
77#define F_ACCESS_32_BITS 0x100
78
79#define TX_INIT_RATE 16
80#define TX_INIT_MAX_RATE 64
81#define RX_INIT_LATENCY 64
82#define RX_INIT_EARLY_THRESH 208 /* not less than MINCLSIZE */
83#define RX_NEXT_EARLY_THRESH 500
84
85#define EEPROMSIZE 0x40
86#define MAX_EEPROMBUSY 1000
87#define EP_LAST_TAG 0xd7
88#define EP_MAX_BOARDS 16
89/*
90 * This `ID' port is a mere hack. There's currently no chance to register
91 * it with config's idea of the ports that are in use.
92 *
93 * "After the automatic configuration is completed, the IDS is in its initial
94 * state (ID-WAIT), and it monitors all write access to I/O port 01x0h, where
95 * 'x' is any hex digit. If a zero is written to any one of these ports, then
96 * that address is remembered and becomes the ID port. A second zero written
97 * to that port resets the ID sequence to its initial state. The IDS watches
98 * for the ID sequence to be written to the ID port."
99 *
100 * We prefer 0x110 over 0x100 so to not conflict with the Plaque&Pray
101 * ports.
102 */
103#define EP_ID_PORT 0x110
104#define EP_IOSIZE 16 /* 16 bytes of I/O space used. */
105
106/*
107 * some macros to acces long named fields
108 */
109#define IS_BASE (is->id_iobase)
110#define BASE (sc->ep_io_addr)
111
112/*
113 * Commands to read/write EEPROM trough EEPROM command register (Window 0,
114 * Offset 0xa)
115 */
116#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */
117#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */
118#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
119#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */
120
121#define EEPROM_BUSY (1<<15)
122#define EEPROM_TST_MODE (1<<14)
123
124/*
125 * Some short functions, worth to let them be a macro
126 */
127#define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
128#define GO_WINDOW(x) outw(BASE+EP_COMMAND, WINDOW_SELECT|(x))
129
130/**************************************************************************
131 * *
132 * These define the EEPROM data structure. They are used in the probe
133 * function to verify the existence of the adapter after having sent
134 * the ID_Sequence.
135 *
136 * There are others but only the ones we use are defined here.
137 *
138 **************************************************************************/
139
140#define EEPROM_NODE_ADDR_0 0x0 /* Word */
141#define EEPROM_NODE_ADDR_1 0x1 /* Word */
142#define EEPROM_NODE_ADDR_2 0x2 /* Word */
143#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */
144#define EEPROM_MFG_ID 0x7 /* 0x6d50 */
145#define EEPROM_ADDR_CFG 0x8 /* Base addr */
146#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */
147
148/**************************************************************************
149 * *
150 * These are the registers for the 3Com 3c509 and their bit patterns when *
151 * applicable. They have been taken out the the "EtherLink III Parallel *
152 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
153 * from 3com. *
154 * *
155 **************************************************************************/
156
157#define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a
158 * command reg. */
159#define EP_STATUS 0x0e /* Read. BASE+0x0e is always status
160 * reg. */
161#define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window
162 * reg. */
163/*
164 * Window 0 registers. Setup.
165 */
166/* Write */
167#define EP_W0_EEPROM_DATA 0x0c
168#define EP_W0_EEPROM_COMMAND 0x0a
169#define EP_W0_RESOURCE_CFG 0x08
170#define EP_W0_ADDRESS_CFG 0x06
171#define EP_W0_CONFIG_CTRL 0x04
172/* Read */
173#define EP_W0_PRODUCT_ID 0x02
174#define EP_W0_MFG_ID 0x00
175
176/*
177 * Window 1 registers. Operating Set.
178 */
179/* Write */
180#define EP_W1_TX_PIO_WR_2 0x02
181#define EP_W1_TX_PIO_WR_1 0x00
182/* Read */
183#define EP_W1_FREE_TX 0x0c
184#define EP_W1_TX_STATUS 0x0b /* byte */
185#define EP_W1_TIMER 0x0a /* byte */
186#define EP_W1_RX_STATUS 0x08
187#define EP_W1_RX_PIO_RD_2 0x02
188#define EP_W1_RX_PIO_RD_1 0x00
189
190/*
191 * Window 2 registers. Station Address Setup/Read
192 */
193/* Read/Write */
194#define EP_W2_ADDR_5 0x05
195#define EP_W2_ADDR_4 0x04
196#define EP_W2_ADDR_3 0x03
197#define EP_W2_ADDR_2 0x02
198#define EP_W2_ADDR_1 0x01
199#define EP_W2_ADDR_0 0x00
200
201/*
202 * Window 3 registers. FIFO Management.
203 */
204/* Read */
205#define EP_W3_FREE_TX 0x0c
206#define EP_W3_FREE_RX 0x0a
207
208/*
209 * Window 4 registers. Diagnostics.
210 */
211/* Read/Write */
212#define EP_W4_MEDIA_TYPE 0x0a
213#define EP_W4_CTRLR_STATUS 0x08
214#define EP_W4_NET_DIAG 0x06
215#define EP_W4_FIFO_DIAG 0x04
216#define EP_W4_HOST_DIAG 0x02
217#define EP_W4_TX_DIAG 0x00
218
219/*
220 * Window 5 Registers. Results and Internal status.
221 */
222/* Read */
223#define EP_W5_READ_0_MASK 0x0c
224#define EP_W5_INTR_MASK 0x0a
225#define EP_W5_RX_FILTER 0x08
226#define EP_W5_RX_EARLY_THRESH 0x06
227#define EP_W5_TX_AVAIL_THRESH 0x02
228#define EP_W5_TX_START_THRESH 0x00
229
230/*
231 * Window 6 registers. Statistics.
232 */
233/* Read/Write */
234#define TX_TOTAL_OK 0x0c
235#define RX_TOTAL_OK 0x0a
236#define TX_DEFERRALS 0x08
237#define RX_FRAMES_OK 0x07
238#define TX_FRAMES_OK 0x06
239#define RX_OVERRUNS 0x05
240#define TX_COLLISIONS 0x04
241#define TX_AFTER_1_COLLISION 0x03
242#define TX_AFTER_X_COLLISIONS 0x02
243#define TX_NO_SQE 0x01
244#define TX_CD_LOST 0x00
245
246/****************************************
247 *
248 * Register definitions.
249 *
250 ****************************************/
251
252/*
253 * Command register. All windows.
254 *
255 * 16 bit register.
256 * 15-11: 5-bit code for command to be executed.
257 * 10-0: 11-bit arg if any. For commands with no args;
258 * this can be set to anything.
259 */
260#define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms
261 * after issuing */
262#define WINDOW_SELECT (u_short) (0x1<<11)
263#define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to
264 * determine whether
265 * this is needed. If
266 * so; wait 800 uSec
267 * before using trans-
268 * ceiver. */
269#define RX_DISABLE (u_short) (0x3<<11) /* state disabled on
270 * power-up */
271#define RX_ENABLE (u_short) (0x4<<11)
272#define RX_RESET (u_short) (0x5<<11)
273#define RX_DISCARD_TOP_PACK (u_short) (0x8<<11)
274#define TX_ENABLE (u_short) (0x9<<11)
275#define TX_DISABLE (u_short) (0xa<<11)
276#define TX_RESET (u_short) (0xb<<11)
277#define REQ_INTR (u_short) (0xc<<11)
278#define SET_INTR_MASK (u_short) (0xe<<11)
279#define SET_RD_0_MASK (u_short) (0xf<<11)
280#define SET_RX_FILTER (u_short) (0x10<<11)
281#define FIL_INDIVIDUAL (u_short) (0x1)
282#define FIL_GROUP (u_short) (0x2)
283#define FIL_BRDCST (u_short) (0x4)
284#define FIL_ALL (u_short) (0x8)
285#define SET_RX_EARLY_THRESH (u_short) (0x11<<11)
286#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11)
287#define SET_TX_START_THRESH (u_short) (0x13<<11)
288#define STATS_ENABLE (u_short) (0x15<<11)
289#define STATS_DISABLE (u_short) (0x16<<11)
290#define STOP_TRANSCEIVER (u_short) (0x17<<11)
291/*
292 * The following C_* acknowledge the various interrupts. Some of them don't
293 * do anything. See the manual.
294 */
295#define ACK_INTR (u_short) (0x6800)
296#define C_INTR_LATCH (u_short) (ACK_INTR|0x1)
297#define C_CARD_FAILURE (u_short) (ACK_INTR|0x2)
298#define C_TX_COMPLETE (u_short) (ACK_INTR|0x4)
299#define C_TX_AVAIL (u_short) (ACK_INTR|0x8)
300#define C_RX_COMPLETE (u_short) (ACK_INTR|0x10)
301#define C_RX_EARLY (u_short) (ACK_INTR|0x20)
302#define C_INT_RQD (u_short) (ACK_INTR|0x40)
303#define C_UPD_STATS (u_short) (ACK_INTR|0x80)
304#define C_MASK (u_short) 0xFF /* mask of C_* */
305
306/*
307 * Status register. All windows.
308 *
309 * 15-13: Window number(0-7).
310 * 12: Command_in_progress.
311 * 11: reserved.
312 * 10: reserved.
313 * 9: reserved.
314 * 8: reserved.
315 * 7: Update Statistics.
316 * 6: Interrupt Requested.
317 * 5: RX Early.
318 * 4: RX Complete.
319 * 3: TX Available.
320 * 2: TX Complete.
321 * 1: Adapter Failure.
322 * 0: Interrupt Latch.
323 */
324#define S_INTR_LATCH (u_short) (0x1)
325#define S_CARD_FAILURE (u_short) (0x2)
326#define S_TX_COMPLETE (u_short) (0x4)
327#define S_TX_AVAIL (u_short) (0x8)
328#define S_RX_COMPLETE (u_short) (0x10)
329#define S_RX_EARLY (u_short) (0x20)
330#define S_INT_RQD (u_short) (0x40)
331#define S_UPD_STATS (u_short) (0x80)
332#define S_MASK (u_short) 0xFF /* mask of S_* */
333#define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\
334 S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY)
335#define S_COMMAND_IN_PROGRESS (u_short) (0x1000)
336
337/* Address Config. Register.
338 * Window 0/Port 06
339 */
340
341#define ACF_CONNECTOR_BITS 14
342#define ACF_CONNECTOR_UTP 0
343#define ACF_CONNECTOR_AUI 1
344#define ACF_CONNECTOR_BNC 3
345
346/* Resource configuration register.
347 * Window 0/Port 08
348 *
349 */
350
351#define SET_IRQ(base,irq) outw((base) + EP_W0_RESOURCE_CFG, \
352 ((inw((base) + EP_W0_RESOURCE_CFG) & 0x0fff) | \
353 ((u_short)(irq)<<12)) ) /* set IRQ i */
354
355/*
356 * FIFO Registers.
357 * RX Status. Window 1/Port 08
358 *
359 * 15: Incomplete or FIFO empty.
360 * 14: 1: Error in RX Packet 0: Incomplete or no error.
361 * 13-11: Type of error.
362 * 1000 = Overrun.
363 * 1011 = Run Packet Error.
364 * 1100 = Alignment Error.
365 * 1101 = CRC Error.
366 * 1001 = Oversize Packet Error (>1514 bytes)
367 * 0010 = Dribble Bits.
368 * (all other error codes, no errors.)
369 *
370 * 10-0: RX Bytes (0-1514)
371 */
372#define ERR_RX_INCOMPLETE (u_short) (0x1<<15)
373#define ERR_RX (u_short) (0x1<<14)
374#define ERR_RX_OVERRUN (u_short) (0x8<<11)
375#define ERR_RX_RUN_PKT (u_short) (0xb<<11)
376#define ERR_RX_ALIGN (u_short) (0xc<<11)
377#define ERR_RX_CRC (u_short) (0xd<<11)
378#define ERR_RX_OVERSIZE (u_short) (0x9<<11)
379#define ERR_RX_DRIBBLE (u_short) (0x2<<11)
380
381/*
382 * FIFO Registers.
383 * TX Status. Window 1/Port 0B
384 *
385 * Reports the transmit status of a completed transmission. Writing this
386 * register pops the transmit completion stack.
387 *
388 * Window 1/Port 0x0b.
389 *
390 * 7: Complete
391 * 6: Interrupt on successful transmission requested.
392 * 5: Jabber Error (TP Only, TX Reset required. )
393 * 4: Underrun (TX Reset required. )
394 * 3: Maximum Collisions.
395 * 2: TX Status Overflow.
396 * 1-0: Undefined.
397 *
398 */
399#define TXS_COMPLETE 0x80
400#define TXS_SUCCES_INTR_REQ 0x40
401#define TXS_JABBER 0x20
402#define TXS_UNDERRUN 0x10
403#define TXS_MAX_COLLISION 0x8
404#define TXS_STATUS_OVERFLOW 0x4
405
406/*
407 * Configuration control register.
408 * Window 0/Port 04
409 */
410/* Read */
411#define IS_AUI (1<<13)
412#define IS_BNC (1<<12)
413#define IS_UTP (1<<9)
414/* Write */
415#define ENABLE_DRQ_IRQ 0x0001
416#define W0_P4_CMD_RESET_ADAPTER 0x4
417#define W0_P4_CMD_ENABLE_ADAPTER 0x1
418/*
419 * Media type and status.
420 * Window 4/Port 0A
421 */
422#define ENABLE_UTP 0xc0
423#define DISABLE_UTP 0x0
424
425/*
426 * Misc defines for various things.
427 */
428#define ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */
429#define MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */
430#define PROD_ID 0x9150
431
432#define AUI 0x1
433#define BNC 0x2
434#define UTP 0x4
435
436#define RX_BYTES_MASK (u_short) (0x07ff)