RTEMS: Epiphany

| RTEMS 5.4-rc2

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Data Structures | Macros | Typedefs | Functions
Epiphany
Internal » SuperCore » CPU Architecture Support

Epiphany Architecture Support. More...

## Data Structures
struct | Context_Control
| Thread register context. More...
struct | CPU_Exception_frame
| The set of registers that specifies the complete processor state. More...

## Macros
#define | CPU_ISR_PASSES_FRAME_POINTER TRUE
#define | CPU_HARDWARE_FP FALSE
#define | CPU_SOFTWARE_FP FALSE
#define | CPU_ALL_TASKS_ARE_FP FALSE
#define | CPU_IDLE_TASK_IS_FP FALSE
#define | CPU_USE_DEFERRED_FP_SWITCH FALSE
#define | CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
#define | CPU_STACK_GROWS_UP FALSE
#define | CPU_CACHE_LINE_BYTES 64
#define | CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
#define | CPU_MODES_INTERRUPT_MASK 0x00000001
#define | _CPU_Context_Get_SP(_context) (_context)->r[13]
#define | CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
#define | CPU_STACK_MINIMUM_SIZE 4096
#define | CPU_ALIGNMENT 8
#define | CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
#define | CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
#define | CPU_STACK_ALIGNMENT 8
#define | CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
#define | _CPU_Initialize_vectors()
#define | _CPU_ISR_Disable(_level) _level = epiphany_interrupt_disable()
#define | _CPU_ISR_Enable(_level) epiphany_interrupt_enable( _level )
#define | _CPU_ISR_Flash(_level)
#define | EPIPHANY_GCC_RED_ZONE_SIZE 128
| Account for GCC red-zone.
#define | _CPU_Context_Restart_self(_the_context) _CPU_Context_restore( (_the_context) )
#define | _CPU_Fatal_halt(_source, _error)
#define | CPU_USE_GENERIC_BITFIELD_CODE TRUE
#define | CPU_SIZEOF_POINTER 4
#define | CPU_EXCEPTION_FRAME_SIZE 260
#define | CPU_MAXIMUM_PROCESSORS 32
#define | CPU_swap_u16(value) (((value&0xff) << 8) | ((value >> 8)&0xff))
#define | CPU_PER_CPU_CONTROL_SIZE 0

## Typedefs
typedef Context_Control | CPU_Interrupt_frame
typedef uint32_t | CPU_Counter_ticks
typedef uintptr_t | CPU_Uint32ptr

## Functions
RTEMS_INLINE_ROUTINE bool | _CPU_ISR_Is_enabled (uint32_t level)
void | _CPU_ISR_Set_level (uint32_t level)
| Sets the hardware interrupt level by the level value.
uint32_t | _CPU_ISR_Get_level (void)
void | _CPU_Context_Initialize (Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
| Initializes the CPU context.
void | _CPU_Exception_frame_print (const CPU_Exception_frame *frame)
| Prints the exception frame via printk().
void | _CPU_Initialize (void)
| CPU initialization.
void * | _CPU_Thread_Idle_body (uintptr_t ignored)
void | _CPU_Context_switch (Context_Control *run, Context_Control *heir)
| CPU switch context.
void | _CPU_Context_restore (Context_Control *new_context) RTEMS_NO_RETURN
void | _CPU_Context_save_fp (void **fp_context_ptr)
void | _CPU_Context_restore_fp (void **fp_context_ptr)
uint32_t | _CPU_Counter_frequency (void)
CPU_Counter_ticks | _CPU_Counter_read (void)
RTEMS_INLINE_ROUTINE void | _CPU_Context_volatile_clobber (uintptr_t pattern)
RTEMS_INLINE_ROUTINE void | _CPU_Context_validate (uintptr_t pattern)
RTEMS_INLINE_ROUTINE void | _CPU_Instruction_illegal (void)
RTEMS_INLINE_ROUTINE void | _CPU_Instruction_no_operation (void)

## Detailed Description

Epiphany Architecture Support.

## Macro Definition Documentation

## ◆ _CPU_Fatal_halt

#define _CPU_Fatal_halt | ( |  | _source,
|  |  | _error
| ) |  |

Value:
printk("Fatal Error %d.%" PRIu32 " Halted\n",_source, _error); \
asm("trap 3" :: "r" (_error)); \
for(;;)

## ◆ _CPU_ISR_Flash

#define _CPU_ISR_Flash | ( |  | _level | ) |

Value:
do{ \
if ( (_level & 0x2) != 0 ) \
_CPU_ISR_Enable( _level ); \
epiphany_interrupt_disable(); \
} while(0)

## ◆ CPU_SIZEOF_POINTER

#define CPU_SIZEOF_POINTER 4

Size of a pointer.

This must be an integer literal that can be used by the assembler. This value will be used to calculate offsets of structure members. These offsets will be used in assembler code.

## ◆ EPIPHANY_GCC_RED_ZONE_SIZE

#define EPIPHANY_GCC_RED_ZONE_SIZE 128

Account for GCC red-zone.

The following macro is used when initializing task's stack to account for GCC red-zone.

## Typedef Documentation

## ◆ CPU_Uint32ptr

typedef uintptr_t CPU_Uint32ptr

Type that can store a 32-bit integer or a pointer.

## Function Documentation

## ◆ _CPU_Context_Initialize()

void _CPU_Context_Initialize | ( | Context_Control * | context,
|  | void * | stack_area_begin,
|  | size_t | stack_area_size,
|  | uint32_t | new_level,
|  | void(*)(void) | entry_point,
|  | bool | is_fp,
|  | void * | tls_area
| ) |  |

Initializes the CPU context.

The following steps are performed:

- setting a starting address
- preparing the stack
- preparing the stack and frame pointers
- setting the proper interrupt level in the context

Parameters

  [in] | context | points to the context area
  [in] | stack_area_begin | is the low address of the allocated stack area
  [in] | stack_area_size | is the size of the stack area in bytes
  [in] | new_level | is the interrupt level for the task
  [in] | entry_point | is the task's entry point
  [in] | is_fp | is set to `true` if the task is a floating point task
  [in] | tls_area | is the thread-local storage (TLS) area

## ◆ _CPU_Context_restore()

void _CPU_Context_restore | ( | Context_Control * | new_context | ) |

This routine is generally used only to restart self in an efficient manner. It may simply be a label in _CPU_Context_switch.

Parameters

  [in] | new_context | points to the context to be restored.

Note
  May be unnecessary to reload some registers.

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ _CPU_Context_switch()

void _CPU_Context_switch | ( | Context_Control * | run,
|  | Context_Control * | heir
| ) |  |

CPU switch context.

This routine switches from the run context to the heir context.

Parameters

  [in] | run | points to the context of the currently executing task
  [in] | heir | points to the context of the heir task

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ _CPU_Exception_frame_print()

void _CPU_Exception_frame_print | ( | const CPU_Exception_frame * | frame | ) |

Prints the exception frame via printk().

See also
  rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.

## ◆ _CPU_Initialize()

void _CPU_Initialize | ( | void |  | ) |

CPU initialization.

CPU initialize. This routine performs CPU dependent initialization.

CPU initialize. This routine performs CPU dependent initialization.

CPU initialization.

## ◆ _CPU_ISR_Get_level()

uint32_t _CPU_ISR_Get_level | ( | void |  | ) |

Return the current interrupt disable level for this task in the format used by the interrupt level portion of the task mode.

Note
  This routine usually must be implemented as a subroutine.

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ _CPU_ISR_Set_level()

void _CPU_ISR_Set_level | ( | uint32_t | new_level | ) |

Sets the hardware interrupt level by the level value.

Parameters

  [in] | level | for or1k can only range over two values: 0 (enable interrupts) and 1 (disable interrupts). In future implementations if fast context switch is implemented, the level can range from 0 to 15.

See also
  OpenRISC architecture manual.