RTEMS: bsps/sh/gensh4/include/rtems/score/sh4_regs.h Source File

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sh4_regs.h
1/*
2 * Bits on SH-4 registers.
3 * See SH-4 Programming manual for more details.
4 *
5 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
6 * Author: Alexandra Kossovsky <sasha@oktet.ru>
7 *
8 * The license and distribution terms for this file may be
9 * found in the file LICENSE in this distribution or at
10 * http://www.rtems.org/license/LICENSE.
11 */
12
13#ifndef __SH4_REGS_H__
14#define __SH4_REGS_H__
15
16/* SR -- Status Register */
17#define SH4_SR_MD 0x40000000 /* Priveleged mode */
18#define SH4_SR_RB 0x20000000 /* General register bank specifier */
19#define SH4_SR_BL 0x10000000 /* Exeption/interrupt masking bit */
20#define SH4_SR_FD 0x00008000 /* FPU disable bit */
21#define SH4_SR_M 0x00000200 /* For signed division:
22 divisor (module) is negative */
23#define SH4_SR_Q 0x00000100 /* For signed division:
24 dividend (and quotient) is negative */
25#define SH4_SR_IMASK 0x000000f0 /* Interrupt mask level */
26#define SH4_SR_IMASK_S 4
27#define SH4_SR_S 0x00000002 /* Saturation for MAC instruction:
28 if set, data in MACH/L register
29 is restricted to 48/32 bits
30 for MAC.W/L instructions */
31#define SH4_SR_T 0x00000001 /* 1 if last condiyion was true */
32#define SH4_SR_RESERV 0x8fff7d0d /* Reserved bits, read/write as 0 */
33
34/* FPSCR -- FPU Starus/Control Register */
35#define SH4_FPSCR_FR 0x00200000 /* FPU register bank specifier */
36#define SH4_FPSCR_SZ 0x00100000 /* FMOV 64-bit transfer mode */
37#define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point
38 operations flag */
39 /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */
40#define SH4_FPSCR_DN 0x00040000 /* Treat denormalized number as zero */
41#define SH4_FPSCR_CAUSE 0x0003f000 /* FPU exeption cause field */
42#define SH4_FPSCR_CAUSE_S 12
43#define SH4_FPSCR_ENABLE 0x00000f80 /* FPU exeption enable field */
44#define SH4_FPSCR_ENABLE_s 7
45#define SH4_FPSCR_FLAG 0x0000007d /* FPU exeption flag field */
46#define SH4_FPSCR_FLAG_S 2
47#define SH4_FPSCR_RM 0x00000001 /* Rounding mode:
48 1/0 -- round to zero/nearest */
49#define SH4_FPSCR_RESERV 0xffd00000 /* Reserved bits, read/write as 0 */
50
51#endif