RTEMS: bsps/arm/include/bsp/arm-gic-regs.h File Reference

| RTEMS 5.4-rc2

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Data Structures | Macros
arm-gic-regs.h File Reference
Board Support Packages » ARM » Shared » ARM GIC

ARM GIC Register definitions. More...

`#include <bsp/utility.h>`

Go to the source code of this file.

## Data Structures
struct | gic_cpuif
struct | gic_dist
struct | gic_redist
struct | gic_sgi_ppi

## Macros
#define | GIC_CPUIF_ICCICR_CBPR BSP_BIT32(4)
#define | GIC_CPUIF_ICCICR_FIQ_EN BSP_BIT32(3)
#define | GIC_CPUIF_ICCICR_ACK_CTL BSP_BIT32(2)
#define | GIC_CPUIF_ICCICR_ENABLE_GRP_1 BSP_BIT32(1)
#define | GIC_CPUIF_ICCICR_ENABLE BSP_BIT32(0)
#define | GIC_CPUIF_ICCPMR_PRIORITY(val) BSP_FLD32(val, 0, 7)
#define | GIC_CPUIF_ICCPMR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7)
#define | GIC_CPUIF_ICCPMR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
#define | GIC_CPUIF_ICCBPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2)
#define | GIC_CPUIF_ICCBPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2)
#define | GIC_CPUIF_ICCBPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
#define | GIC_CPUIF_ICCIAR_CPUID(val) BSP_FLD32(val, 10, 12)
#define | GIC_CPUIF_ICCIAR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
#define | GIC_CPUIF_ICCIAR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
#define | GIC_CPUIF_ICCIAR_ACKINTID(val) BSP_FLD32(val, 0, 9)
#define | GIC_CPUIF_ICCIAR_ACKINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
#define | GIC_CPUIF_ICCIAR_ACKINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
#define | GIC_CPUIF_ICCEOIR_CPUID(val) BSP_FLD32(val, 10, 12)
#define | GIC_CPUIF_ICCEOIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
#define | GIC_CPUIF_ICCEOIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
#define | GIC_CPUIF_ICCEOIR_EOIINTID(val) BSP_FLD32(val, 0, 9)
#define | GIC_CPUIF_ICCEOIR_EOIINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
#define | GIC_CPUIF_ICCEOIR_EOIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
#define | GIC_CPUIF_ICCRPR_PRIORITY(val) BSP_FLD32(val, 0, 7)
#define | GIC_CPUIF_ICCRPR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7)
#define | GIC_CPUIF_ICCRPR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
#define | GIC_CPUIF_ICCHPIR_CPUID(val) BSP_FLD32(val, 10, 12)
#define | GIC_CPUIF_ICCHPIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
#define | GIC_CPUIF_ICCHPIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
#define | GIC_CPUIF_ICCHPIR_PENDINTID(val) BSP_FLD32(val, 0, 9)
#define | GIC_CPUIF_ICCHPIR_PENDINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
#define | GIC_CPUIF_ICCHPIR_PENDINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
#define | GIC_CPUIF_ICCABPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2)
#define | GIC_CPUIF_ICCABPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2)
#define | GIC_CPUIF_ICCABPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
#define | GIC_CPUIF_ICCIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31)
#define | GIC_CPUIF_ICCIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31)
#define | GIC_CPUIF_ICCIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
#define | GIC_CPUIF_ICCIIDR_ARCH_VERSION(val) BSP_FLD32(val, 16, 19)
#define | GIC_CPUIF_ICCIIDR_ARCH_VERSION_GET(reg) BSP_FLD32GET(reg, 16, 19)
#define | GIC_CPUIF_ICCIIDR_ARCH_VERSION_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
#define | GIC_CPUIF_ICCIIDR_REVISION(val) BSP_FLD32(val, 12, 15)
#define | GIC_CPUIF_ICCIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15)
#define | GIC_CPUIF_ICCIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
#define | GIC_CPUIF_ICCIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11)
#define | GIC_CPUIF_ICCIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11)
#define | GIC_CPUIF_ICCIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
#define | GIC_DIST_ICDDCR_RWP BSP_BIT32(31)
#define | GIC_DIST_ICDDCR_E1NWF BSP_BIT32(7)
#define | GIC_DIST_ICDDCR_DS BSP_BIT32(6)
#define | GIC_DIST_ICDDCR_ARE_NS BSP_BIT32(5)
#define | GIC_DIST_ICDDCR_ARE_S BSP_BIT32(4)
#define | GIC_DIST_ICDDCR_ENABLE_GRP1S BSP_BIT32(2)
#define | GIC_DIST_ICDDCR_ENABLE_GRP1NS BSP_BIT32(1)
#define | GIC_DIST_ICDDCR_ENABLE_GRP0 BSP_BIT32(0)
#define | GIC_DIST_ICDDCR_ENABLE_GRP_1 BSP_BIT32(1)
#define | GIC_DIST_ICDDCR_ENABLE BSP_BIT32(0)
#define | GIC_DIST_ICDICTR_LSPI(val) BSP_FLD32(val, 11, 15)
#define | GIC_DIST_ICDICTR_LSPI_GET(reg) BSP_FLD32GET(reg, 11, 15)
#define | GIC_DIST_ICDICTR_LSPI_SET(reg, val) BSP_FLD32SET(reg, val, 11, 15)
#define | GIC_DIST_ICDICTR_SECURITY_EXTN BSP_BIT32(10)
#define | GIC_DIST_ICDICTR_CPU_NUMBER(val) BSP_FLD32(val, 5, 7)
#define | GIC_DIST_ICDICTR_CPU_NUMBER_GET(reg) BSP_FLD32GET(reg, 5, 7)
#define | GIC_DIST_ICDICTR_CPU_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7)
#define | GIC_DIST_ICDICTR_IT_LINES_NUMBER(val) BSP_FLD32(val, 0, 4)
#define | GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(reg) BSP_FLD32GET(reg, 0, 4)
#define | GIC_DIST_ICDICTR_IT_LINES_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
#define | GIC_DIST_ICDIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31)
#define | GIC_DIST_ICDIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31)
#define | GIC_DIST_ICDIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
#define | GIC_DIST_ICDIIDR_VARIANT(val) BSP_FLD32(val, 16, 19)
#define | GIC_DIST_ICDIIDR_VARIANT_GET(reg) BSP_FLD32GET(reg, 16, 19)
#define | GIC_DIST_ICDIIDR_VARIANT_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
#define | GIC_DIST_ICDIIDR_REVISION(val) BSP_FLD32(val, 12, 15)
#define | GIC_DIST_ICDIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15)
#define | GIC_DIST_ICDIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
#define | GIC_DIST_ICDIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11)
#define | GIC_DIST_ICDIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11)
#define | GIC_DIST_ICDIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
#define | GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(val) BSP_FLD32(val, 24, 25)
#define | GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_GET(reg) BSP_FLD32GET(reg, 24, 25)
#define | GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25)
#define | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(val) BSP_FLD32(val, 16, 23)
#define | GIC_DIST_ICDSGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD32GET(reg, 16, 23)
#define | GIC_DIST_ICDSGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
#define | GIC_DIST_ICDSGIR_NSATT BSP_BIT32(15)
#define | GIC_DIST_ICDSGIR_SGIINTID(val) BSP_FLD32(val, 0, 3)
#define | GIC_DIST_ICDSGIR_SGIINTID_GET(reg) BSP_FLD32GET(reg, 0, 3)
#define | GIC_DIST_ICDSGIR_SGIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
#define | GIC_REDIST_ICRRCR_UWP BSP_BIT32(31)
#define | GIC_REDIST_ICRRCR_DPG1S BSP_BIT32(26)
#define | GIC_REDIST_ICRRCR_DPG1NS BSP_BIT32(25)
#define | GIC_REDIST_ICRRCR_DPG0 BSP_BIT32(24)
#define | GIC_REDIST_ICRRCR_RWP BSP_BIT32(4)
#define | GIC_REDIST_ICRRCR_ENABLE_LPI BSP_BIT32(0)
#define | GIC_REDIST_ICRTYPER_AFFINITY_VALUE(val) BSP_FLD64(val, 32, 63)
#define | GIC_REDIST_ICRTYPER_AFFINITY_VALUE_GET(reg) BSP_FLD64GET(reg, 32, 63)
#define | GIC_REDIST_ICRTYPER_AFFINITY_VALUE_SET(reg, val) BSP_FLD64SET(reg, val, 32, 63)
#define | GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY(val) BSP_FLD64(val, 24, 25)
#define | GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_GET(reg) BSP_FLD64GET(reg, 24, 25)
#define | GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_SET(reg, val) BSP_FLD64SET(reg, val, 24, 25)
#define | GIC_REDIST_ICRTYPER_CPU_NUMBER(val) BSP_FLD64(val, 8, 23)
#define | GIC_REDIST_ICRTYPER_CPU_NUMBER_GET(reg) BSP_FLD64GET(reg, 8, 23)
#define | GIC_REDIST_ICRTYPER_CPU_NUMBER_SET(reg, val) BSP_FLD64SET(reg, val, 8, 23)
#define | GIC_REDIST_ICRTYPER_DPGS BSP_BIT64(5)
#define | GIC_REDIST_ICRTYPER_LAST BSP_BIT64(4)
#define | GIC_REDIST_ICRTYPER_DIRECT_LPI BSP_BIT64(3)
#define | GIC_REDIST_ICRTYPER_VLPIS BSP_BIT64(1)
#define | GIC_REDIST_ICRTYPER_PLPIS BSP_BIT64(0)
#define | GIC_REDIST_ICRWAKER_CHILDREN_ASLEEP BSP_BIT32(2)
#define | GIC_REDIST_ICRWAKER_PROCESSOR_SLEEP BSP_BIT32(1)

## Detailed Description

ARM GIC Register definitions.