RTEMS: Context_Control Struct Reference

| RTEMS 5.4-rc2

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Data Fields
Context_Control Struct Reference
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Thread register context. More...

`#include <cpu.h>`

## Data Fields
void * | register_sp
uint32_t | register_r4
uint32_t | register_r5
uint32_t | register_r6
uint32_t | register_r7
uint32_t | register_p3
uint32_t | register_p4
uint32_t | register_p5
uint32_t | register_fp
uint32_t | register_sp
uint32_t | register_rets
uint32_t | imask
uint32_t | r [64]
uint32_t | status
uint32_t | config
uint32_t | iret
uint32_t | eflags
void * | esp
void * | ebp
uint32_t | ebx
uint32_t | esi
uint32_t | edi
segment_descriptors | gs
uint32_t | isr_dispatch_disable
uint32_t | r11
uint32_t | r12
uint32_t | r13
uint32_t | r14
uint32_t | r15
uint32_t | r16
uint32_t | r17
uint32_t | r18
uint32_t | r19
uint32_t | r20
uint32_t | r21
uint32_t | r22
uint32_t | r23
uint32_t | r24
uint32_t | r25
uint32_t | gp
uint32_t | fp
uint32_t | sp
uint32_t | ra
uint32_t | ie
uint32_t | epc
uint32_t | sr
uint32_t | d2
uint32_t | d3
uint32_t | d4
uint32_t | d5
uint32_t | d6
uint32_t | d7
void * | a2
void * | a3
void * | a4
void * | a5
void * | a6
void * | a7_msp
__MIPS_REGISTER_TYPE | s0
__MIPS_REGISTER_TYPE | s1
__MIPS_REGISTER_TYPE | s2
__MIPS_REGISTER_TYPE | s3
__MIPS_REGISTER_TYPE | s4
__MIPS_REGISTER_TYPE | s5
__MIPS_REGISTER_TYPE | s6
__MIPS_REGISTER_TYPE | s7
__MIPS_REGISTER_TYPE | sp
__MIPS_REGISTER_TYPE | fp
__MIPS_REGISTER_TYPE | ra
__MIPS_REGISTER_TYPE | c0_sr
__MIPS_REGISTER_TYPE | c0_epc
void *fp | nogap
void *sp | nogap
uint32_t r0 | nogap
uint32_t r1 | nogap
uint32_t r2 | nogap
uint32_t r3 | nogap
uint32_t r4 | nogap
uint32_t r5 | nogap
uint32_t r6 | nogap
uint32_t r7 | nogap
uint32_t r8 | nogap
uint32_t r9 | nogap
uint32_t r10 | nogap
uint32_t r11 | nogap
uint32_t r12 | nogap
uint32_t r13 | nogap
uint32_t | thread_dispatch_disabled
uint32_t | stack_mpubase
uint32_t | stack_mpuacc
uint32_t | some_integer_register
uint32_t | some_system_register
uint32_t | stack_pointer
uint32_t | r1
uint32_t | r2
uint32_t | r3
uint32_t | r4
uint32_t | r5
uint32_t | r6
uint32_t | r7
uint32_t | r8
uint32_t | r9
uint32_t | r10
uint32_t | r26
uint32_t | r27
uint32_t | r28
uint32_t | r29
uint32_t | r30
uint32_t | r31
uint32_t | epcr
uint32_t | eear
uint32_t | esr
uint8_t | context [PPC_DEFAULT_CACHE_LINE_SIZE+sizeof(ppc_context)+(sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE==0 ? 0 :PPC_DEFAULT_CACHE_LINE_SIZE - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE)]
uint32_t | reserved
uintptr_t | ra
uintptr_t | sp
uintptr_t | tp
uintptr_t | s0
uintptr_t | s1
uintptr_t | s2
uintptr_t | s3
uintptr_t | s4
uintptr_t | s5
uintptr_t | s6
uintptr_t | s7
uintptr_t | s8
uintptr_t | s9
uintptr_t | s10
uintptr_t | s11
uint32_t * | r15
uint32_t | macl
uint32_t | mach
uint32_t * | pr
uint32_t * | r14
uint32_t * | r7
uint32_t * | r6
uint32_t * | r3
uint32_t * | r2
uint32_t * | r1
uint32_t * | r0
uint32_t | gbr
uint32_t | g5
uint32_t | g7
double | l0_and_l1
uint32_t | l2
uint32_t | l3
uint32_t | l4
uint32_t | l5
uint32_t | l6
uint32_t | l7
uint32_t | i0
uint32_t | i1
uint32_t | i2
uint32_t | i3
uint32_t | i4
uint32_t | i5
uint32_t | i6_fp
uint32_t | i7
uint32_t | o6_sp
uint32_t | o7
uint32_t | psr
uint64_t | g1
uint64_t | g2
uint64_t | g3
uint64_t | g4
uint64_t | g5
uint64_t | g6
uint64_t | g7
uint64_t | l0
uint64_t | l1
uint64_t | l2
uint64_t | l3
uint64_t | l4
uint64_t | l5
uint64_t | l6
uint64_t | l7
uint64_t | i0
uint64_t | i1
uint64_t | i2
uint64_t | i3
uint64_t | i4
uint64_t | i5
uint64_t | i6_fp
uint64_t | i7
uint64_t | o0
uint64_t | o1
uint64_t | o2
uint64_t | o3
uint64_t | o4
uint64_t | o5
uint64_t | o6_sp
uint64_t | o7
uint32_t | pad
uint32_t | r3_stack_pointer
uint32_t | psw
uint64_t | rflags
uint64_t | rbx
void * | rsp
void * | rbp
uint64_t | r12
uint64_t | r13
uint64_t | r14
uint64_t | r15

## Detailed Description

Thread register context.

SPARC basic context.

This defines the minimal set of integer and processor state registers that must be saved during a voluntary context switch from one thread to another.

The thread register context covers the non-volatile registers, the thread stack pointer, the return address, and the processor status.

There is no need to save the global pointer (gp) since it is a system wide constant and set-up with the C runtime environment.

The thread_dispatch_disabled field is used for the external interrupt controller (EIC) support.

See also
  _Nios2_Thread_dispatch_disabled

This structure defines the non-volatile integer and processor state context for the SPARC architecture according to "SYSTEM V APPLICATION BINARY INTERFACE - SPARC Processor Supplement", Third Edition.

The registers g2 through g4 are reserved for applications. GCC uses them as volatile registers by default. So they are treated like volatile registers in RTEMS as well.

The register g6 contains the per-CPU control of the current processor. It is an invariant of the processor context. This register must not be saved and restored during context switches or interrupt services.

## Field Documentation

## ◆ g5

uint32_t Context_Control::g5

This will contain the contents of the g5 register.

## ◆ g7

uint32_t Context_Control::g7

This will contain the contents of the g7 register.

## ◆ i0

uint32_t Context_Control::i0

This will contain the contents of the i0 register.

## ◆ i1

uint32_t Context_Control::i1

This will contain the contents of the i1 register.

## ◆ i2

uint32_t Context_Control::i2

This will contain the contents of the i2 register.

## ◆ i3

uint32_t Context_Control::i3

This will contain the contents of the i3 register.

## ◆ i4

uint32_t Context_Control::i4

This will contain the contents of the i4 register.

## ◆ i5

uint32_t Context_Control::i5

This will contain the contents of the i5 register.

## ◆ i6_fp

uint32_t Context_Control::i6_fp

This will contain the contents of the i6 (e.g. frame pointer) register.

## ◆ i7

uint32_t Context_Control::i7

This will contain the contents of the i7 register.

## ◆ isr_dispatch_disable

uint32_t Context_Control::isr_dispatch_disable

This field is used to prevent heavy nesting of calls to _Thread_Dispatch on an interrupted task's stack. This is problematic on the slower SPARC CPU models at high interrupt rates.

## ◆ l0_and_l1

double Context_Control::l0_and_l1

This will contain the contents of the l0 and l1 registers.

Using a double l0_and_l1 will put everything in this structure on a double word boundary which allows us to use double word loads and stores safely in the context switch.

## ◆ l2

uint32_t Context_Control::l2

This will contain the contents of the l2 register.

## ◆ l3

uint32_t Context_Control::l3

This will contain the contents of the l3 register.

## ◆ l4

uint32_t Context_Control::l4

This will contain the contents of the l4 register.

## ◆ l5

uint32_t Context_Control::l5

This will contain the contents of the l5 registeer.

## ◆ l6

uint32_t Context_Control::l6

This will contain the contents of the l6 register.

## ◆ l7

uint32_t Context_Control::l7

This will contain the contents of the l7 register.

## ◆ o6_sp

uint32_t Context_Control::o6_sp

This will contain the contents of the o6 (e.g. frame pointer) register.

## ◆ o7

uint32_t Context_Control::o7

This will contain the contents of the o7 (e.g. address of CALL instruction) register.

## ◆ psr

uint32_t Context_Control::psr

This will contain the contents of the processor status register.

## ◆ r3_stack_pointer

uint32_t Context_Control::r3_stack_pointer

This field is the stack pointer (e.g. r3).

## ◆ rbx

uint64_t Context_Control::rbx

Callee-saved registers as listed in the SysV ABI document: https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI

## ◆ some_integer_register

uint32_t Context_Control::some_integer_register

This field is a hint that a port will have a number of integer registers that need to be saved at a context switch.

## ◆ some_system_register

uint32_t Context_Control::some_system_register

This field is a hint that a port will have a number of system registers that need to be saved at a context switch.

## ◆ stack_pointer

uint32_t Context_Control::stack_pointer

This field is a hint that a port will have a register that is the stack pointer.

The documentation for this struct was generated from the following files:

- cpukit/score/cpu/arm/include/rtems/score/cpu.h
- cpukit/score/cpu/bfin/include/rtems/score/cpu.h
- cpukit/score/cpu/epiphany/include/rtems/score/cpu.h
- cpukit/score/cpu/i386/include/rtems/score/cpu.h
- cpukit/score/cpu/lm32/include/rtems/score/cpu.h
- cpukit/score/cpu/m68k/include/rtems/score/cpu.h
- cpukit/score/cpu/mips/include/rtems/score/cpu.h
- cpukit/score/cpu/moxie/include/rtems/score/cpu.h
- cpukit/score/cpu/nios2/include/rtems/score/cpu.h
- cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
- cpukit/score/cpu/or1k/include/rtems/score/cpu.h
- cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
- cpukit/score/cpu/riscv/include/rtems/score/cpu.h
- cpukit/score/cpu/sh/include/rtems/score/cpu.h
- cpukit/score/cpu/sparc/include/rtems/score/cpu.h
- cpukit/score/cpu/sparc64/include/rtems/score/cpu.h
- cpukit/score/cpu/v850/include/rtems/score/cpu.h
- cpukit/score/cpu/x86_64/include/rtems/score/cpu.h