RTEMS: bsps/include/libchip/greth.h Source File

| RTEMS 5.4-rc2

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greth.h
1/*
2 * Gaisler Research ethernet MAC driver
3 * adapted from Opencores driver by Marko Isomaki
4 *
5 * The license and distribution terms for this file may be
6 * found in the file LICENSE in this distribution or at
7 * http://www.rtems.org/license/LICENSE.
8 */
9
10
11#ifndef _GR_ETH_
12#define _GR_ETH_
13
14
15/* Configuration Information */
16
17 typedef struct {
18 void *base_address;
19 rtems_vector_number vector;
20 uint32_t txd_count;
21 uint32_t rxd_count;
22} greth_configuration_t;
23
24/* Ethernet configuration registers */
25
26typedef struct _greth_regs {
27 volatile uint32_t ctrl; /* Ctrl Register */
28 volatile uint32_t status; /* Status Register */
29 volatile uint32_t mac_addr_msb; /* Bit 47-32 of MAC address */
30 volatile uint32_t mac_addr_lsb; /* Bit 31-0 of MAC address */
31 volatile uint32_t mdio_ctrl; /* MDIO control and status */
32 volatile uint32_t txdesc; /* Transmit descriptor pointer */
33 volatile uint32_t rxdesc; /* Receive descriptor pointer */
34} greth_regs;
35
36#define GRETH_TOTAL_BD 128
37#define GRETH_MAXBUF_LEN 1520
38
39/* Tx BD */
40#define GRETH_TXD_ENABLE 0x0800 /* Tx BD Enable */
41#define GRETH_TXD_WRAP 0x1000 /* Tx BD Wrap (last BD) */
42#define GRETH_TXD_IRQ 0x2000 /* Tx BD IRQ Enable */
43#define GRETH_TXD_MORE 0x20000 /* Tx BD More (more descs for packet) */
44#define GRETH_TXD_IPCS 0x40000 /* Tx BD insert ip chksum */
45#define GRETH_TXD_TCPCS 0x80000 /* Tx BD insert tcp chksum */
46#define GRETH_TXD_UDPCS 0x100000 /* Tx BD insert udp chksum */
47
48#define GRETH_TXD_UNDERRUN 0x4000 /* Tx BD Underrun Status */
49#define GRETH_TXD_RETLIM 0x8000 /* Tx BD Retransmission Limit Status */
50#define GRETH_TXD_LATECOL 0x10000 /* Tx BD Late Collision */
51
52#define GRETH_TXD_STATS (GRETH_TXD_UNDERRUN | \
53 GRETH_TXD_RETLIM | \
54 GRETH_TXD_LATECOL)
55
56#define GRETH_TXD_CS (GRETH_TXD_IPCS | \
57 GRETH_TXD_TCPCS | \
58 GRETH_TXD_UDPCS)
59
60/* Rx BD */
61#define GRETH_RXD_ENABLE 0x0800 /* Rx BD Enable */
62#define GRETH_RXD_WRAP 0x1000 /* Rx BD Wrap (last BD) */
63#define GRETH_RXD_IRQ 0x2000 /* Rx BD IRQ Enable */
64
65#define GRETH_RXD_DRIBBLE 0x4000 /* Rx BD Dribble Nibble Status */
66#define GRETH_RXD_TOOLONG 0x8000 /* Rx BD Too Long Status */
67#define GRETH_RXD_CRCERR 0x10000 /* Rx BD CRC Error Status */
68#define GRETH_RXD_OVERRUN 0x20000 /* Rx BD Overrun Status */
69#define GRETH_RXD_LENERR 0x40000 /* Rx BD Length Error */
70#define GRETH_RXD_ID 0x40000 /* Rx BD IP Detected */
71#define GRETH_RXD_IR 0x40000 /* Rx BD IP Chksum Error */
72#define GRETH_RXD_UD 0x40000 /* Rx BD UDP Detected*/
73#define GRETH_RXD_UR 0x40000 /* Rx BD UDP Chksum Error */
74#define GRETH_RXD_TD 0x40000 /* Rx BD TCP Detected */
75#define GRETH_RXD_TR 0x40000 /* Rx BD TCP Chksum Error */
76
77
78#define GRETH_RXD_STATS (GRETH_RXD_OVERRUN | \
79 GRETH_RXD_DRIBBLE | \
80 GRETH_RXD_TOOLONG | \
81 GRETH_RXD_CRCERR)
82
83/* CTRL Register */
84#define GRETH_CTRL_TXEN 0x00000001 /* Transmit Enable */
85#define GRETH_CTRL_RXEN 0x00000002 /* Receive Enable */
86#define GRETH_CTRL_TXIRQ 0x00000004 /* Transmit Enable */
87#define GRETH_CTRL_RXIRQ 0x00000008 /* Receive Enable */
88#define GRETH_CTRL_FULLD 0x00000010 /* Full Duplex */
89#define GRETH_CTRL_PRO 0x00000020 /* Promiscuous (receive all) */
90#define GRETH_CTRL_RST 0x00000040 /* Reset MAC */
91
92/* Status Register */
93#define GRETH_STATUS_RXERR 0x00000001 /* Receive Error */
94#define GRETH_STATUS_TXERR 0x00000002 /* Transmit Error IRQ */
95#define GRETH_STATUS_RXIRQ 0x00000004 /* Receive Frame IRQ */
96#define GRETH_STATUS_TXIRQ 0x00000008 /* Transmit Error IRQ */
97#define GRETH_STATUS_RXAHBERR 0x00000010 /* Receiver AHB Error */
98#define GRETH_STATUS_TXAHBERR 0x00000020 /* Transmitter AHB Error */
99
100/* MDIO Control */
101#define GRETH_MDIO_WRITE 0x00000001 /* MDIO Write */
102#define GRETH_MDIO_READ 0x00000002 /* MDIO Read */
103#define GRETH_MDIO_LINKFAIL 0x00000004 /* MDIO Link failed */
104#define GRETH_MDIO_BUSY 0x00000008 /* MDIO Link Busy */
105#define GRETH_MDIO_REGADR 0x000007C0 /* Register Address */
106#define GRETH_MDIO_PHYADR 0x0000F800 /* PHY address */
107#define GRETH_MDIO_DATA 0xFFFF0000 /* MDIO DATA */
108
109
110/* MII registers */
111#define GRETH_MII_EXTADV_1000FD 0x00000200
112#define GRETH_MII_EXTADV_1000HD 0x00000100
113#define GRETH_MII_EXTPRT_1000FD 0x00000800
114#define GRETH_MII_EXTPRT_1000HD 0x00000400
115
116#define GRETH_MII_100T4 0x00000200
117#define GRETH_MII_100TXFD 0x00000100
118#define GRETH_MII_100TXHD 0x00000080
119#define GRETH_MII_10FD 0x00000040
120#define GRETH_MII_10HD 0x00000020
121
122
123
124/* Attach routine */
125
126int rtems_greth_driver_attach (
127 struct rtems_bsdnet_ifconfig *config,
128 greth_configuration_t *chip
129);
130
131/* PHY data */
132struct phy_device_info
133{
134 int vendor;
135 int device;
136 int rev;
137
138 int adv;
139 int part;
140
141 int extadv;
142 int extpart;
143};
144
145/*
146#ifdef CPU_U32_FIX
147void ipalign(struct mbuf *m);
148#endif
149
150*/
151#endif
152
rtems_vector_number
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition: intr.h:47
_greth_regs
Definition: greth.h:19
config_s
Definition: deflate.c:115
device
Definition: rtemscompat1.h:15
greth_configuration_t
Definition: greth.h:17
phy_device_info
Definition: greth.h:134