RTEMS: cpukit/score/cpu/riscv/include/rtems/score/cpu.h File Reference

| RTEMS 5.4-rc2

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Data Structures | Macros | Typedefs | Enumerations | Functions | Variables
cpu.h File Reference
`#include <rtems/score/basedefs.h>`
`#include <rtems/score/riscv.h>`

Go to the source code of this file.

## Data Structures
struct | Context_Control
| Thread register context. More...
struct | RTEMS_ALIGNED
struct | CPU_Exception_frame
| The set of registers that specifies the complete processor state. More...

## Macros
#define | RISCV_MSTATUS_MIE 0x8
#define | CPU_ISR_PASSES_FRAME_POINTER FALSE
#define | CPU_HARDWARE_FP FALSE
#define | CPU_SOFTWARE_FP FALSE
#define | CPU_ALL_TASKS_ARE_FP FALSE
#define | CPU_IDLE_TASK_IS_FP FALSE
#define | CPU_USE_DEFERRED_FP_SWITCH FALSE
#define | CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE
#define | CPU_STACK_GROWS_UP FALSE
#define | CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (64)))
#define | CPU_BIG_ENDIAN FALSE
#define | CPU_LITTLE_ENDIAN TRUE
#define | CPU_MODES_INTERRUPT_MASK 0x0000000000000001
#define | CPU_CACHE_LINE_BYTES 64
#define | CPU_ALIGNMENT 16
#define | CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
#define | CPU_STACK_ALIGNMENT 16
#define | CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
#define | _CPU_Context_Get_SP(_context) (_context)->sp
#define | CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
#define | CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
#define | _CPU_Initialize_vectors()
#define | _CPU_ISR_Disable(_level) _level = riscv_interrupt_disable()
#define | _CPU_ISR_Enable(_level) riscv_interrupt_enable( _level )
#define | _CPU_ISR_Flash(_level)
#define | _CPU_Context_Restart_self(_the_context) _CPU_Context_restore( (_the_context) )
#define | CPU_USE_GENERIC_BITFIELD_CODE TRUE
#define | CPU_USE_GENERIC_BITFIELD_DATA TRUE
#define | CPU_MAXIMUM_PROCESSORS 32
#define | CPU_swap_u16(value) (((value&0xff) << 8) | ((value >> 8)&0xff))

## Typedefs
typedef uint16_t | Priority_bit_map_Word
typedef uint32_t | CPU_Counter_ticks
typedef uintptr_t | CPU_Uint32ptr

## Enumerations
enum | RISCV_Interrupt_code { RISCV_INTERRUPT_SOFTWARE_USER = 0 , RISCV_INTERRUPT_SOFTWARE_SUPERVISOR = 1 , RISCV_INTERRUPT_SOFTWARE_MACHINE = 3 , RISCV_INTERRUPT_TIMER_USER = 4 , RISCV_INTERRUPT_TIMER_SUPERVISOR = 5 , RISCV_INTERRUPT_TIMER_MACHINE = 7 , RISCV_INTERRUPT_EXTERNAL_USER = 8 , RISCV_INTERRUPT_EXTERNAL_SUPERVISOR = 9 , RISCV_INTERRUPT_EXTERNAL_MACHINE = 11 }
enum | RISCV_Exception_code { RISCV_EXCEPTION_INSTRUCTION_ADDRESS_MISALIGNED = 0 , RISCV_EXCEPTION_INSTRUCTION_ACCESS_FAULT = 1 , RISCV_EXCEPTION_ILLEGAL_INSTRUCTION = 2 , RISCV_EXCEPTION_BREAKPOINT = 3 , RISCV_EXCEPTION_LOAD_ADDRESS_MISALIGNED = 4 , RISCV_EXCEPTION_LOAD_ACCESS_FAULT = 5 , RISCV_EXCEPTION_STORE_OR_AMO_ADDRESS_MISALIGNED = 6 , RISCV_EXCEPTION_STORE_OR_AMO_ACCESS_FAULT = 7 , RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_U_MODE = 8 , RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_S_MODE = 9 , RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_M_MODE = 11 , RISCV_EXCEPTION_INSTRUCTION_PAGE_FAULT = 12 , RISCV_EXCEPTION_LOAD_PAGE_FAULT = 13 , RISCV_EXCEPTION_STORE_OR_AMO_PAGE_FAULT = 15 }

## Functions
RTEMS_INLINE_ROUTINE bool | _CPU_ISR_Is_enabled (unsigned long level)
RTEMS_INLINE_ROUTINE void | _CPU_ISR_Set_level (uint32_t level)
| Sets the hardware interrupt level by the level value.
uint32_t | _CPU_ISR_Get_level (void)
| Returns the interrupt level of the executing thread.
void | _CPU_Context_Initialize (Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
| Initializes the CPU context.
void | _CPU_Fatal_halt (uint32_t source, uint32_t error) RTEMS_NO_RETURN
void | _CPU_Exception_frame_print (const CPU_Exception_frame *frame)
| Prints the exception frame via printk().
void | _CPU_Initialize (void)
| CPU initialization.
void * | _CPU_Thread_Idle_body (uintptr_t ignored)
void | _CPU_Context_switch (Context_Control *run, Context_Control *heir)
| CPU switch context.
void | _CPU_Context_restore (Context_Control *new_context) RTEMS_NO_RETURN
uint32_t | _CPU_Counter_frequency (void)
| Returns the current CPU counter frequency in Hz.
CPU_Counter_ticks | _CPU_Counter_read (void)
| Returns the current CPU counter value.

## Variables
volatile uint32_t *const | _RISCV_Counter

## Macro Definition Documentation

## ◆ _CPU_ISR_Flash

#define _CPU_ISR_Flash | ( |  | _level | ) |

Value:
do{ \
_CPU_ISR_Enable( _level ); \
riscv_interrupt_disable(); \
} while(0)

## Typedef Documentation

## ◆ CPU_Uint32ptr

typedef uintptr_t CPU_Uint32ptr

Type that can store a 32-bit integer or a pointer.