RTEMS: cpukit/score/cpu/bfin/include/rtems/score/cpu.h Source File

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cpu.h
Go to the documentation of this file.
1
10/*
11 * COPYRIGHT (c) 1989-2006.
12 * On-Line Applications Research Corporation (OAR).
13 * adapted to Blackfin by Alain Schaefer <alain.schaefer@easc.ch>
14 * and Antonio Giovanini <antonio@atos.com.br>
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 */
20
21#ifndef _RTEMS_SCORE_CPU_H
22#define _RTEMS_SCORE_CPU_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28#include <rtems/score/basedefs.h>
29#include <rtems/score/bfin.h>
30
31/* conditional compilation parameters */
32
33/*
34 * Does the CPU follow the simple vectored interrupt model?
35 *
36 * If TRUE, then RTEMS allocates the vector table it internally manages.
37 * If FALSE, then the BSP is assumed to allocate and manage the vector
38 * table
39 *
40 * BFIN Specific Information:
41 *
42 * XXX document implementation including references if appropriate
43 */
44#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
45
55#define CPU_ISR_PASSES_FRAME_POINTER TRUE
56
57#define CPU_HARDWARE_FP FALSE
58
59#define CPU_SOFTWARE_FP FALSE
60
61#define CPU_ALL_TASKS_ARE_FP FALSE
62
63#define CPU_IDLE_TASK_IS_FP FALSE
64
65#define CPU_USE_DEFERRED_FP_SWITCH FALSE
66
67#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
68
80#define CPU_STACK_GROWS_UP FALSE
81
82/* FIXME: Is this the right value? */
83#define CPU_CACHE_LINE_BYTES 32
84
85#define CPU_STRUCTURE_ALIGNMENT
86
97#define CPU_MODES_INTERRUPT_MASK 0x00000001
98
99#define CPU_MAXIMUM_PROCESSORS 32
100
101/*
102 * Processor defined structures required for cpukit/score.
103 *
104 * Port Specific Information:
105 *
106 * XXX document implementation including references if appropriate
107 */
108
109/* may need to put some structures here. */
110
111#ifndef ASM
112
164/* make sure this stays in sync with the assembly function
165 __CPU_Context_switch in cpu_asm.S */
166typedef struct {
167 uint32_t register_r4;
168 uint32_t register_r5;
169 uint32_t register_r6;
170 uint32_t register_r7;
171
172 uint32_t register_p3;
173 uint32_t register_p4;
174 uint32_t register_p5;
175 uint32_t register_fp;
176 uint32_t register_sp;
177
178 uint32_t register_rets;
179
180 uint32_t imask;
181} Context_Control;
182
183#define _CPU_Context_Get_SP( _context ) \
184 (_context)->register_sp
185
191 typedef struct {
196 /*uint32_t special_interrupt_register;*/
197} CPU_Interrupt_frame;
198
209#endif /* ASM */
210
221#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
222
232#define CPU_INTERRUPT_NUMBER_OF_VECTORS 16
233
238#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
239
245#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
246
256#define CPU_STACK_MINIMUM_SIZE (1024*8)
257
258#define CPU_SIZEOF_POINTER 4
259
268#define CPU_ALIGNMENT 8
269
293#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
294
308#define CPU_STACK_ALIGNMENT 8
309
310#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
311
312#ifndef ASM
313
314/*
315 * ISR handler macros
316 */
317
330#define _CPU_Initialize_vectors()
331
342#define _CPU_ISR_Disable( _level ) \
343 { \
344 __asm__ volatile ("cli %0; csync \n" : "=d" (_level) ); \
345 }
346
347
359#define _CPU_ISR_Enable( _level ) { \
360 __asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) ); \
361 }
362
375#define _CPU_ISR_Flash( _level ) { \
376 __asm__ __volatile__ ("sti %0; csync; cli r0; csync" \
377 : : "d"(_level) : "R0" ); \
378 }
379
380 RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
381{
382 return level != 0;
383}
384
400#define _CPU_ISR_Set_level( _new_level ) \
401 { \
402 __asm__ __volatile__ ( "sti %0; csync" : : "d"(_new_level ? 0 : 0xffff) ); \
403 }
404
415uint32_t _CPU_ISR_Get_level( void );
416
417/* end of ISR handler macros */
418
421/* Context handler macros */
422
455void _CPU_Context_Initialize(
456 Context_Control *the_context,
457 uint32_t *stack_base,
458 uint32_t size,
459 uint32_t new_level,
460 void *entry_point,
461 bool is_fp,
462 void *tls_area
463);
464
480#define _CPU_Context_Restart_self( _the_context ) \
481 _CPU_Context_restore( (_the_context) );
482
483/* end of Context handler macros */
484
485/* Fatal Error manager macros */
486
496#define _CPU_Fatal_halt( _source, _error ) \
497 { \
498 __asm__ volatile ( "cli R1; \
499 R1 = %0; \
500 _halt: \
501 idle; \
502 jump _halt;"\
503 : : "r" (_error) ); \
504 }
505
506/* end of Fatal Error manager macros */
507
508#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
509
510/* functions */
511
520void _CPU_Initialize(void);
521
522typedef void ( *CPU_ISR_raw_handler )( void );
523
524void _CPU_ISR_install_raw_handler(
525 uint32_t vector,
526 CPU_ISR_raw_handler new_handler,
527 CPU_ISR_raw_handler *old_handler
528);
529
530typedef void ( *CPU_ISR_handler )( uint32_t );
531
532void _CPU_ISR_install_vector(
533 uint32_t vector,
534 CPU_ISR_handler new_handler,
535 CPU_ISR_handler *old_handler
536);
537
538void *_CPU_Thread_Idle_body( uintptr_t ignored );
539
555void _CPU_Context_switch(
556 Context_Control *run,
557 Context_Control *heir
558);
559
572void _CPU_Context_restore(
573 Context_Control *new_context
574) RTEMS_NO_RETURN;
575
578/* FIXME */
579typedef CPU_Interrupt_frame CPU_Exception_frame;
580
581void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
582
592/*
593 *
594 * The following routine swaps the endian format of an unsigned int.
595 * It must be static because it is referenced indirectly.
596 *
597 * This version will work on any processor, but if there is a better
598 * way for your CPU PLEASE use it. The most common way to do this is to:
599 *
600 * swap least significant two bytes with 16-bit rotate
601 * swap upper and lower 16-bits
602 * swap most significant two bytes with 16-bit rotate
603 *
604 * Some CPUs have special instructions which swap a 32-bit quantity in
605 * a single instruction (e.g. i486). It is probably best to avoid
606 * an "endian swapping control bit" in the CPU. One good reason is
607 * that interrupts would probably have to be disabled to ensure that
608 * an interrupt does not try to access the same "chunk" with the wrong
609 * endian. Another good reason is that on some CPUs, the endian bit
610 * endianness for ALL fetches -- both code and data -- so the code
611 * will be fetched incorrectly.
612 *
613 * @param[in] value is the value to be swapped
614 * @return the value after being endian swapped
615 *
616 * Port Specific Information:
617 *
618 * XXX document implementation including references if appropriate
619 */
620
621static inline uint32_t CPU_swap_u32(
622 uint32_t value
623)
624{
625 uint32_t byte1, byte2, byte3, byte4, swapped;
626
627 byte4 = (value >> 24) & 0xff;
628 byte3 = (value >> 16) & 0xff;
629 byte2 = (value >> 8) & 0xff;
630 byte1 = value & 0xff;
631
632 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
633 return( swapped );
634}
635
642#define CPU_swap_u16( value ) \
643 (((value&0xff) << 8) | ((value >> 8)&0xff))
644
647typedef uint32_t CPU_Counter_ticks;
648
649uint32_t _CPU_Counter_frequency( void );
650
651CPU_Counter_ticks _CPU_Counter_read( void );
652
653static inline CPU_Counter_ticks _CPU_Counter_difference(
654 CPU_Counter_ticks second,
655 CPU_Counter_ticks first
656)
657{
658 return second - first;
659}
660
662 typedef uintptr_t CPU_Uint32ptr;
663
664#endif /* ASM */
665
666#ifdef __cplusplus
667}
668#endif
669
670#endif
basedefs.h
Basic Definitions.
_CPU_ISR_install_raw_handler
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:103
RTEMS_NO_RETURN
#define RTEMS_NO_RETURN
Definition: basedefs.h:102
RTEMS_INLINE_ROUTINE
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:66
_CPU_Thread_Idle_body
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
_CPU_Initialize
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
CPU_Uint32ptr
uintptr_t CPU_Uint32ptr
Definition: cpu.h:662
_CPU_ISR_install_vector
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
_CPU_Exception_frame_print
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
_CPU_Counter_frequency
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
_CPU_Context_switch
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
_CPU_Counter_read
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
bfin.h
Blackfin Set up Basic CPU Dependency Settings Based on Compiler Settings.
CPU_Exception_frame
The set of registers that specifies the complete processor state.
Definition: cpu.h:629
CPU_Interrupt_frame
Interrupt stack frame (ISF).
Definition: cpu.h:191
Context_Control
Thread register context.
Definition: cpu.h:194