RTEMS: bsps/arm/atsam/include/libchip/include/samv71/component/component_acc.h Source File

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component_acc.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMV71_ACC_COMPONENT_
31#define _SAMV71_ACC_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __O uint32_t ACC_CR;
43 __IO uint32_t ACC_MR;
44 __I uint32_t Reserved1[7];
45 __O uint32_t ACC_IER;
46 __O uint32_t ACC_IDR;
47 __I uint32_t ACC_IMR;
48 __I uint32_t ACC_ISR;
49 __I uint32_t Reserved2[24];
50 __IO uint32_t ACC_ACR;
51 __I uint32_t Reserved3[19];
52 __IO uint32_t ACC_WPMR;
53 __I uint32_t ACC_WPSR;
54 __I uint32_t Reserved4[4];
55 __I uint32_t ACC_VER;
56} Acc;
57#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
58/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */
59#define ACC_CR_SWRST (0x1u << 0)
60/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */
61#define ACC_MR_SELMINUS_Pos 0
62#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos)
63#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos)))
64#define ACC_MR_SELMINUS_TS (0x0u << 0)
65#define ACC_MR_SELMINUS_VREFP (0x1u << 0)
66#define ACC_MR_SELMINUS_DAC0 (0x2u << 0)
67#define ACC_MR_SELMINUS_DAC1 (0x3u << 0)
68#define ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0)
69#define ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0)
70#define ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0)
71#define ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0)
72#define ACC_MR_SELPLUS_Pos 4
73#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos)
74#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos)))
75#define ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4)
76#define ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4)
77#define ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4)
78#define ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4)
79#define ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4)
80#define ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4)
81#define ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4)
82#define ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4)
83#define ACC_MR_ACEN (0x1u << 8)
84#define ACC_MR_ACEN_DIS (0x0u << 8)
85#define ACC_MR_ACEN_EN (0x1u << 8)
86#define ACC_MR_EDGETYP_Pos 9
87#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos)
88#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos)))
89#define ACC_MR_EDGETYP_RISING (0x0u << 9)
90#define ACC_MR_EDGETYP_FALLING (0x1u << 9)
91#define ACC_MR_EDGETYP_ANY (0x2u << 9)
92#define ACC_MR_INV (0x1u << 12)
93#define ACC_MR_INV_DIS (0x0u << 12)
94#define ACC_MR_INV_EN (0x1u << 12)
95#define ACC_MR_SELFS (0x1u << 13)
96#define ACC_MR_SELFS_CE (0x0u << 13)
97#define ACC_MR_SELFS_OUTPUT (0x1u << 13)
98#define ACC_MR_FE (0x1u << 14)
99#define ACC_MR_FE_DIS (0x0u << 14)
100#define ACC_MR_FE_EN (0x1u << 14)
101/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */
102#define ACC_IER_CE (0x1u << 0)
103/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */
104#define ACC_IDR_CE (0x1u << 0)
105/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */
106#define ACC_IMR_CE (0x1u << 0)
107/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */
108#define ACC_ISR_CE (0x1u << 0)
109#define ACC_ISR_SCO (0x1u << 1)
110#define ACC_ISR_MASK (0x1u << 31)
111/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */
112#define ACC_ACR_ISEL (0x1u << 0)
113#define ACC_ACR_ISEL_LOPW (0x0u << 0)
114#define ACC_ACR_ISEL_HISP (0x1u << 0)
115#define ACC_ACR_HYST_Pos 1
116#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos)
117#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))
118/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */
119#define ACC_WPMR_WPEN (0x1u << 0)
120#define ACC_WPMR_WPKEY_Pos 8
121#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos)
122#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))
123#define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8)
124/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */
125#define ACC_WPSR_WPVS (0x1u << 0)
126/* -------- ACC_VER : (ACC Offset: 0xFC) Version Register -------- */
127#define ACC_VER_VERSION_Pos 0
128#define ACC_VER_VERSION_Msk (0xfffu << ACC_VER_VERSION_Pos)
129#define ACC_VER_MFN_Pos 16
130#define ACC_VER_MFN_Msk (0x7u << ACC_VER_MFN_Pos)
133
134
135#endif /* _SAMV71_ACC_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Acc
Acc hardware registers.
Definition: component_acc.h:41
Acc::ACC_VER
__I uint32_t ACC_VER
(Acc Offset: 0xFC) Version Register
Definition: component_acc.h:55