RTEMS: bsps/arm/csb337/include/at91rm9200_dbgu.h File Reference

| RTEMS 5.4-rc2

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Data Structures | Macros
at91rm9200_dbgu.h File Reference
Board Support Packages » ARM » CSB337 » AT91RM9200

Atmel AT91RM9200_DBGU Register definitions. More...

`#include "bits.h"`

Go to the source code of this file.

## Data Structures
struct | at91rm9200_dbgu_regs_t

## Macros
#define | DBGU_CR 0x00 /* Control Register */
#define | DBGU_MR 0x04 /* Mode Register */
#define | DBGU_IER 0x08 /* Interrupt Enable Register */
#define | DBGU_IDR 0x0C /* Interrupt Disable Register */
#define | DBGU_IMR 0x10 /* Interrupt Mask Register */
#define | DBGU_SR 0x14 /* Channel Status Register */
#define | DBGU_RHR 0x18 /* Receiver Holding Register */
#define | DBGU_THR 0x1C /* Transmitter Holding Register */
#define | DBGU_BRGR 0x20 /* Baud Rate Generator Register */
#define | DBGU_C1R 0x40 /* Chip ID1 Register */
#define | DBGU_C2R 0x44 /* Chip ID2 Register */
#define | DBGU_FNTR 0x48 /* Force NTRST Register */
#define | DBGU_CR_RSTRX BIT2 /* 1 = Reset and disable receiver */
#define | DBGU_CR_RSTTX BIT3 /* 1 = Reset and disable transmitter */
#define | DBGU_CR_RXEN BIT4 /* 1 = Receiver enable */
#define | DBGU_CR_RXDIS BIT5 /* 1 = Receiver disable */
#define | DBGU_CR_TXEN BIT6 /* 1 = Transmitter enable */
#define | DBGU_CR_TXDIS BIT7 /* 1 = Transmitter disable */
#define | DBGU_CR_RSTSTA BIT8 /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */
#define | DBGU_MR_PAR_EVEN (0x0 << 9) /* Even Parity */
#define | DBGU_MR_PAR_ODD (0x1 << 9) /* Odd Parity */
#define | DBGU_MR_PAR_SPACE (0x2 << 9) /* Parity forced to 0 (Space) */
#define | DBGU_MR_PAR_MARK (0x3 << 9) /* Parity forced to 1 (Mark) */
#define | DBGU_MR_PAR_NONE (0x4 << 9) /* No Parity */
#define | DBGU_MR_PAR_MDROP (0x6 << 9) /* Multi-drop mode */
#define | DBGU_MR_CHMODE_NORM (0x0 << 14) /* Normal Mode */
#define | DBGU_MR_CHMODE_AUTO (0x1 << 14) /* Auto Echo: RXD drives TXD */
#define | DBGU_MR_CHMODE_LOC (0x2 << 14) /* Local Loopback: TXD drives RXD */
#define | DBGU_MR_CHMODE_REM (0x3 << 14) /* Remote Loopback: RXD pin connected to TXD pin. */
#define | DBGU_INT_RXRDY BIT0 /* RXRDY Interrupt */
#define | DBGU_INT_TXRDY BIT1 /* TXRDY Interrupt */
#define | DBGU_INT_ENDRX BIT3 /* End of Receive Transfer Interrupt */
#define | DBGU_INT_ENDTX BIT4 /* End of Transmit Interrupt */
#define | DBGU_INT_OVRE BIT5 /* Overrun Interrupt */
#define | DBGU_INT_FRAME BIT6 /* Framing Error Interrupt */
#define | DBGU_INT_PARE BIT7 /* Parity Error Interrupt */
#define | DBGU_INT_TXEMPTY BIT9 /* TXEMPTY Interrupt */
#define | DBGU_INT_TXBUFE BIT11 /* TXBUFE Interrupt */
#define | DBGU_INT_RXBUFF BIT12 /* RXBUFF Interrupt */
#define | DBGU_INT_COMM_TX BIT30 /* COMM_TX Interrupt */
#define | DBGU_INT_COMM_RX BIT31 /* COMM_RX Interrupt */
#define | DBGU_INT_ALL 0xC0001AFB /* all assigned bits */
#define | DBGU_FNTR_NTRST BIT0 /* 1 = Force NTRST low in JTAG */

## Detailed Description

Atmel AT91RM9200_DBGU Register definitions.