RTEMS: Reset Control

| RTEMS 5.4-rc2

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Functions
Reset Control
Board Support Packages » ARM » Intel Cyclone V » Contributed Code » The Reset Manager

## Functions
ALT_STATUS_CODE | alt_reset_cold_reset (void)
ALT_STATUS_CODE | alt_reset_warm_reset (uint32_t warm_reset_delay, uint32_t nRST_pin_clk_assertion, bool sdram_refresh, bool fpga_mgr_handshake, bool scan_mgr_handshake, bool fpga_handshake, bool etr_stall)

## Detailed Description

This functional group provides global and selective reset control for the SoC and its constituent modules.

## Function Documentation

## ◆ alt_reset_cold_reset()

ALT_STATUS_CODE alt_reset_cold_reset | ( | void |  | ) |

Initiate a cold reset of the SoC.

If this function is successful, then it should never return.

Return values

  ALT_E_SUCCESS | The operation was succesful.
  ALT_E_ERROR | The operation failed.

## ◆ alt_reset_warm_reset()

ALT_STATUS_CODE alt_reset_warm_reset | ( | uint32_t | warm_reset_delay,
|  | uint32_t | nRST_pin_clk_assertion,
|  | bool | sdram_refresh,
|  | bool | fpga_mgr_handshake,
|  | bool | scan_mgr_handshake,
|  | bool | fpga_handshake,
|  | bool | etr_stall
| ) |  |

Initiate a warm reset of the SoC.

Perform a hardware sequenced warm reset of the SoC. A hardware sequenced reset handshake with certain modules can optionally be requested in an attempt to ensure an orderly reset transition.

Parameters

  warm_reset_delay | Specifies the number of cycles after the Reset Manager releases the Clock Manager reset before releasing any other hardware controlled resets. Value must be greater than 16 and less than 256.
  nRST_pin_clk_assertion | Specifies that number of clock cycles (osc1_clk?) to externally assert the warm reset pin (nRST). 0 <= nRST_pin_clk_assertion <= (2**20 - 1). A value of 0 prevents any assertion of nRST.
  sdram_refresh | Controls whether the contents of SDRAM survive a hardware sequenced warm reset. The reset manager requests the SDRAM controller to put SDRAM devices into self-refresh mode before asserting warm reset signals. An argument value of true enables the option, false disables the option.
  fpga_mgr_handshake | Controls whether a handshake between the reset manager and FPGA manager occurs before a warm reset. The handshake is used to warn the FPGA manager that a warm reset is imminent so it can prepare for it by driving its output clock to a quiescent state to avoid glitches. An argument value of true enables the option, false disables the option.
  scan_mgr_handshake | Controls whether a handshake between the reset manager and scan manager occurs before a warm reset. The handshake is used to warn the scan manager that a warm reset is imminent so it can prepare for it by driving its output clock to a quiescent state to avoid glitches. An argument value of true enables the option, false disables the option.
  fpga_handshake | Controls whether a handshake between the reset manager and the FPGA occurs before a warm reset. The handshake is used to warn the FPGA that a warm reset is imminent so that the FPGA prepare for the reset event in soft IP. An argument value of true enables the option, false disables the option.
  etr_stall | Controls whether the ETR is requested to idle its AXI master interface (i.e. finish outstanding transactions and not initiate any more) to the L3 Interconnect before a warm reset. An argument value of true enables the option, false disables the option.

Return values

  ALT_E_SUCCESS | The operation was succesful.
  ALT_E_ERROR | The operation failed.