RTEMS: bsps/m68k/mvme147s/include/bsp.h Source File

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bsp.h
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1
9/* bsp.h
10 *
11 * This include file contains all MVME147 board IO definitions.
12 *
13 * COPYRIGHT (c) 1989-1999.
14 * On-Line Applications Research Corporation (OAR).
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 *
20 * MVME147 port for TNI - Telecom Bretagne
21 * by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
22 * May 1996
23 */
24
25#ifndef LIBBSP_M68K_MVME147S_BSP_H
26#define LIBBSP_M68K_MVME147S_BSP_H
27
38#include <bspopts.h>
39#include <bsp/default-initial-extension.h>
40
41#include <rtems.h>
42
43#ifdef __cplusplus
44extern "C" {
45#endif
46
47/* Constants */
48
49#define RAM_START 0x00007000
50#define RAM_END 0x003e0000
51#define DRAM_END 0x00400000
52 /* We leave 128k for the shared memory */
53
54 /* MVME 147 Peripheral controller chip
55 see MVME147/D1, 3.4 */
56
57struct pcc_map {
58 /* 32 bit registers */
59 uint32_t dma_table_address; /* 0xfffe1000 */
60 uint32_t dma_data_address; /* 0xfffe1004 */
61 uint32_t dma_bytecount; /* 0xfffe1008 */
62 uint32_t dma_data_holding; /* 0xfffe100c */
63
64 /* 16 bit registers */
65 uint16_t timer1_preload; /* 0xfffe1010 */
66 uint16_t timer1_count; /* 0xfffe1012 */
67 uint16_t timer2_preload; /* 0xfffe1014 */
68 uint16_t timer2_count; /* 0xfffe1016 */
69
70 /* 8 bit registers */
71 uint8_t timer1_int_control; /* 0xfffe1018 */
72 uint8_t timer1_control; /* 0xfffe1019 */
73 uint8_t timer2_int_control; /* 0xfffe101a */
74 uint8_t timer2_control; /* 0xfffe101b */
75
76 uint8_t acfail_int_control; /* 0xfffe101c */
77 uint8_t watchdog_control; /* 0xfffe101d */
78
79 uint8_t printer_int_control; /* 0xfffe101e */
80 uint8_t printer_control; /* 0xfffe102f */
81
82 uint8_t dma_int_control; /* 0xfffe1020 */
83 uint8_t dma_control; /* 0xfffe1021 */
84 uint8_t bus_error_int_control; /* 0xfffe1022 */
85 uint8_t dma_status; /* 0xfffe1023 */
86 uint8_t abort_int_control; /* 0xfffe1024 */
87 uint8_t table_address_function_code; /* 0xfffe1025 */
88 uint8_t serial_port_int_control; /* 0xfffe1026 */
89 uint8_t general_purpose_control; /* 0xfffe1027 */
90 uint8_t lan_int_control; /* 0xfffe1028 */
91 uint8_t general_purpose_status; /* 0xfffe1029 */
92 uint8_t scsi_port_int_control; /* 0xfffe102a */
93 uint8_t slave_base_address; /* 0xfffe102b */
94 uint8_t software_int_1_control; /* 0xfffe102c */
95 uint8_t int_base_vector; /* 0xfffe102d */
96 uint8_t software_int_2_control; /* 0xfffe102e */
97 uint8_t revision_level; /* 0xfffe102f */
98};
99
100#define pcc ((volatile struct pcc_map * const) 0xfffe1000)
101
102/* VME chip configuration registers */
103
104 struct vme_lcsr_map {
105 uint8_t unused_1;
106 uint8_t system_controller; /* 0xfffe2001 */
107 uint8_t unused_2;
108 uint8_t vme_bus_requester; /* 0xfffe2003 */
109 uint8_t unused_3;
110 uint8_t master_configuration; /* 0xfffe2005 */
111 uint8_t unused_4;
112 uint8_t slave_configuration; /* 0xfffe2007 */
113 uint8_t unused_5;
114 uint8_t timer_configuration; /* 0xfffe2009 */
115 uint8_t unused_6;
116 uint8_t slave_address_modifier; /* 0xfffe200b */
117 uint8_t unused_7;
118 uint8_t master_address_modifier; /* 0xfffe200d */
119 uint8_t unused_8;
120 uint8_t interrupt_handler_mask; /* 0xfffe200f */
121 uint8_t unused_9;
122 uint8_t utility_interrupt_mask; /* 0xfffe2011 */
123 uint8_t unused_10;
124 uint8_t utility_interrupt_vector; /* 0xfffe2013 */
125 uint8_t unused_11;
126 uint8_t interrupt_request; /* 0xfffe2015 */
127 uint8_t unused_12;
128 uint8_t vme_bus_status_id; /* 0xfffe2017 */
129 uint8_t unused_13;
130 uint8_t bus_error_status; /* 0xfffe2019 */
131 uint8_t unused_14;
132 uint8_t gcsr_base_address; /* 0xfffe201b */
133};
134
135#define vme_lcsr ((volatile struct vme_lcsr_map * const) 0xfffe2000)
136
137 struct vme_gcsr_map {
138 uint8_t unused_1;
139 uint8_t global_0; /* 0xfffe2021 */
140 uint8_t unused_2;
141 uint8_t global_1; /* 0xfffe2023 */
142 uint8_t unused_3;
143 uint8_t board_identification; /* 0xfffe2025 */
144 uint8_t unused_4;
145 uint8_t general_purpose_0; /* 0xfffe2027 */
146 uint8_t unused_5;
147 uint8_t general_purpose_1; /* 0xfffe2029 */
148 uint8_t unused_6;
149 uint8_t general_purpose_2; /* 0xfffe202b */
150 uint8_t unused_7;
151 uint8_t general_purpose_3; /* 0xfffe202d */
152 uint8_t unused_8;
153 uint8_t general_purpose_4; /* 0xfffe202f */
154};
155
156#define vme_gcsr ((volatile struct vme_gcsr_map * const) 0xfffe2020)
157
158#define z8530 0xfffe3001
159
160/* interrupt vectors - see MVME147/D1 4.14 */
161#define PCC_BASE_VECTOR 0x40 /* First user int */
162#define SCC_VECTOR PCC_BASE_VECTOR+3
163#define TIMER_1_VECTOR PCC_BASE_VECTOR+8
164#define TIMER_2_VECTOR PCC_BASE_VECTOR+9
165#define SOFT_1_VECTOR PCC_BASE_VECTOR+10
166#define SOFT_2_VECTOR PCC_BASE_VECTOR+11
167
168#define VME_BASE_VECTOR 0x50
169#define VME_SIGLP_VECTOR VME_BASE_VECTOR+1
170
171#define USE_CHANNEL_A 1 /* 1 = use channel A for console */
172#define USE_CHANNEL_B 0 /* 1 = use channel B for console */
173
174#if (USE_CHANNEL_A == 1)
175#define CONSOLE_CONTROL 0xfffe3002
176#define CONSOLE_DATA 0xfffe3003
177#elif (USE_CHANNEL_B == 1)
178#define CONSOLE_CONTROL 0xfffe3000
179#define CONSOLE_DATA 0xfffe3001
180#endif
181
182#define FOREVER 1 /* infinite loop */
183
184#ifdef M147_INIT
185#undef EXTERN
186#define EXTERN
187#else
188#undef EXTERN
189#define EXTERN extern
190#endif
191
192extern rtems_isr_entry M68Kvec[]; /* vector table address */
193
194/*
195 * NOTE: Use the standard Clock driver entry
196 */
197
198/* functions */
199
200rtems_isr_entry set_vector(
201 rtems_isr_entry handler,
202 rtems_vector_number vector,
203 int type
204);
205
206#ifdef __cplusplus
207}
208#endif
209
212#endif
default-initial-extension.h
DEFAULT_INITIAL_EXTENSION Support.
rtems_vector_number
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition: intr.h:47
rtems.h
pcc_map
Definition: bsp.h:55
vme_gcsr_map
Definition: bsp.h:137
vme_lcsr_map
Definition: bsp.h:104