RTEMS: cpukit/score/cpu/v850/include/rtems/score/cpu.h Source File

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cpu.h
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1
10/*
11 * COPYRIGHT (c) 1989-2012.
12 * On-Line Applications Research Corporation (OAR).
13 *
14 * The license and distribution terms for this file may be
15 * found in the file LICENSE in this distribution or at
16 * http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/basedefs.h>
27#include <rtems/score/v850.h>
28
29/* conditional compilation parameters */
30
42#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
43
44#define CPU_HARDWARE_FP FALSE
45
46#define CPU_SOFTWARE_FP FALSE
47
48#define CPU_ALL_TASKS_ARE_FP FALSE
49
50#define CPU_IDLE_TASK_IS_FP FALSE
51
52#define CPU_USE_DEFERRED_FP_SWITCH FALSE
53
54#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
55
67#define CPU_STACK_GROWS_UP FALSE
68
69/* FIXME: Is this the right value? */
70#define CPU_CACHE_LINE_BYTES 32
71
72#define CPU_STRUCTURE_ALIGNMENT
73
84#define CPU_MODES_INTERRUPT_MASK 0x00000001
85
86#define CPU_MAXIMUM_PROCESSORS 32
87
139typedef struct {
140 uint32_t r1;
142 uint32_t r3_stack_pointer;
143 uint32_t r20;
144 uint32_t r21;
145 uint32_t r22;
146 uint32_t r23;
147 uint32_t r24;
148 uint32_t r25;
149 uint32_t r26;
150 uint32_t r27;
151 uint32_t r28;
152 uint32_t r29;
153 uint32_t r31;
154 uint32_t psw;
155} Context_Control;
156
164#define _CPU_Context_Get_SP( _context ) \
165 (_context)->r3_stack_pointer
166
172typedef struct {
177 uint32_t special_interrupt_register;
178} CPU_Interrupt_frame;
179
199#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
200
205#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
206
218#define CPU_STACK_MINIMUM_SIZE (1024*4)
219
220#define CPU_SIZEOF_POINTER 4
221
230#define CPU_ALIGNMENT 8
231
255#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
256
271#define CPU_STACK_ALIGNMENT 4
272
273#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
274
275/*
276 * ISR handler macros
277 */
278
294#define _CPU_ISR_Disable( _isr_cookie ) \
295 do { \
296 unsigned int _psw; \
297 \
298 v850_get_psw( _psw ); \
299 __asm__ __volatile__( "di" ); \
300 _isr_cookie = _psw; \
301 } while (0)
302
314#define _CPU_ISR_Enable( _isr_cookie ) \
315 do { \
316 unsigned int _psw = (_isr_cookie); \
317 \
318 v850_set_psw( _psw ); \
319 } while (0)
320
333#define _CPU_ISR_Flash( _isr_cookie ) \
334 do { \
335 unsigned int _psw = (_isr_cookie); \
336 v850_set_psw( _psw ); \
337 __asm__ __volatile__( "di" ); \
338 } while (0)
339
340 RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
341{
342 return ( level & V850_PSW_INTERRUPT_DISABLE_MASK )
343 != V850_PSW_INTERRUPT_DISABLE;
344}
345
361#define _CPU_ISR_Set_level( new_level ) \
362 do { \
363 if ( new_level ) \
364 __asm__ __volatile__( "di" ); \
365 else \
366 __asm__ __volatile__( "ei" ); \
367 } while (0)
368
379uint32_t _CPU_ISR_Get_level( void );
380
381/* end of ISR handler macros */
382
385/* Context handler macros */
386
419void _CPU_Context_Initialize(
420 Context_Control *the_context,
421 uint32_t *stack_base,
422 uint32_t size,
423 uint32_t new_level,
424 void *entry_point,
425 bool is_fp,
426 void *tls_area
427);
428
444#define _CPU_Context_Restart_self( _the_context ) \
445 _CPU_Context_restore( (_the_context) );
446
447/* XXX this should be possible to remove */
448#if 0
467#define _CPU_Context_Initialize_fp( _destination ) \
468 { \
469 }
470#endif
471
472/* end of Context handler macros */
473
474/* Fatal Error manager macros */
475
485#define _CPU_Fatal_halt( _source, _error ) \
486 do { \
487 __asm__ __volatile__ ( "di" ); \
488 __asm__ __volatile__ ( "mov %0, r10; " : "=r" ((_error)) ); \
489 __asm__ __volatile__ ( "halt" ); \
490 } while (0)
491
492/* end of Fatal Error manager macros */
493
494#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
495
496/* functions */
497
508void _CPU_Initialize(void);
509
510void *_CPU_Thread_Idle_body( uintptr_t ignored );
511
527void _CPU_Context_switch(
528 Context_Control *run,
529 Context_Control *heir
530);
531
544void _CPU_Context_restore(
545 Context_Control *new_context
546) RTEMS_NO_RETURN;
547
548/* XXX this should be possible to remove */
549#if 0
563void _CPU_Context_save_fp(
564 Context_Control_fp **fp_context_ptr
565);
566#endif
567
568/* XXX this should be possible to remove */
569#if 0
583void _CPU_Context_restore_fp(
584 Context_Control_fp **fp_context_ptr
585);
586#endif
587
590/* FIXME */
591typedef CPU_Interrupt_frame CPU_Exception_frame;
592
593void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
594
631static inline uint32_t CPU_swap_u32(
632 uint32_t value
633)
634{
635 unsigned int swapped;
636
637 #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1)
638 unsigned int v;
639
640 v = value;
641 __asm__ __volatile__ ("bsw %0, %1" : "=r" (v), "=&r" (swapped) );
642 #else
643 uint32_t byte1, byte2, byte3, byte4;
644
645 byte4 = (value >> 24) & 0xff;
646 byte3 = (value >> 16) & 0xff;
647 byte2 = (value >> 8) & 0xff;
648 byte1 = value & 0xff;
649
650 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
651 #endif
652 return swapped;
653}
654
665static inline uint16_t CPU_swap_u16( uint16_t value )
666{
667 unsigned int swapped;
668
669 #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1)
670 unsigned int v;
671
672 v = value;
673 __asm__ __volatile__ ("bsh %0, %1" : "=r" (v), "=&r" (swapped) );
674 #else
675 swapped = ((value & 0xff) << 8) | ((value >> 8) & 0xff);
676 #endif
677 return swapped;
678}
679
682typedef uint32_t CPU_Counter_ticks;
683
684uint32_t _CPU_Counter_frequency( void );
685
686CPU_Counter_ticks _CPU_Counter_read( void );
687
688static inline CPU_Counter_ticks _CPU_Counter_difference(
689 CPU_Counter_ticks second,
690 CPU_Counter_ticks first
691)
692{
693 return second - first;
694}
695
697 typedef uintptr_t CPU_Uint32ptr;
698
699#ifdef __cplusplus
700}
701#endif
702
703#endif
basedefs.h
Basic Definitions.
RTEMS_NO_RETURN
#define RTEMS_NO_RETURN
Definition: basedefs.h:102
RTEMS_INLINE_ROUTINE
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:66
_CPU_Thread_Idle_body
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
_CPU_Initialize
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
CPU_Uint32ptr
uintptr_t CPU_Uint32ptr
Definition: cpu.h:662
_CPU_Exception_frame_print
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
_CPU_Counter_frequency
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
_CPU_Context_switch
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
_CPU_Counter_read
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
CPU_swap_u16
#define CPU_swap_u16(value)
Definition: cpu.h:642
_CPU_Context_restore_fp
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:904
_CPU_Context_save_fp
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:898
CPU_Exception_frame
The set of registers that specifies the complete processor state.
Definition: cpu.h:629
CPU_Interrupt_frame
Interrupt stack frame (ISF).
Definition: cpu.h:191
Context_Control_fp
SPARC basic context.
Definition: cpu.h:194
Context_Control
Thread register context.
Definition: cpu.h:194
Context_Control::r3_stack_pointer
uint32_t r3_stack_pointer
Definition: cpu.h:142
v850.h
V850 Set up Basic CPU Dependency Settings Based on Compiler Settings.