RTEMS: bsps/m68k/gen68340/include/m68340.h Source File

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m68340.h
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1
9/**********************************************************************
10 * MC68340 C Header File *
11 * *
12 * Developed by : Motorola *
13 * High Performance Embedded Systems Division *
14 * Austin, TX *
15 * Rectified by : Geoffroy Montel
16 * g_montel@yahoo.com *
17 * *
18 **********************************************************************/
19
20typedef volatile unsigned char * portb; /* 8-bit port */
21typedef volatile unsigned short * portw; /* 16-bit port */
22typedef volatile unsigned int * portl; /* 32-bit port */
23
24#define MBASE 0xEFFFF000 /* Module Base Address */
25 /* not EFFFF000 due to a 68349
26 hardware incompatibility */
27
28#define MBAR (*(portb) 0x0003FF00) /* Module Base Addr Reg */
29#define MBAR1 (*(portb) 0x0003FF00) /* Module Base Addr Reg 1 (MSW) */
30#define MBAR2 (*(portb) 0x0003FF02) /* Module Base Addr Reg 2 (LSW) */
31
32/* System Integration Module */
33
34#define SIMMCR (*(portw) (MBASE+0x0000)) /* SIM Module Config Reg */
35#define SIMSYNCR (*(portw) (MBASE+0x0004)) /* SIM Clock Synth Cont Reg */
36#define SIMAVR (*(portb) (MBASE+0x0006)) /* SIM Autovector Reg */
37#define SIMRSR (*(portb) (MBASE+0x0007)) /* SIM Reset Status Reg */
38#define SIMPORTA (*(portb) (MBASE+0x0011)) /* SIM Port A Data Reg */
39#define SIMDDRA (*(portb) (MBASE+0x0013)) /* SIM Port A Data Dir Reg */
40#define SIMPPRA1 (*(portb) (MBASE+0x0015)) /* SIM Port A Pin Asm 1 Reg */
41#define SIMPPRA2 (*(portb) (MBASE+0x0017)) /* SIM Port A Pin Asm 2 Reg */
42#define SIMPORTB (*(portb) (MBASE+0x0019)) /* SIM Port B Data Reg */
43#define SIMPORTB1 (*(portb) (MBASE+0x001B)) /* SIM Port B Data Reg */
44#define SIMDDRB (*(portb) (MBASE+0x001D)) /* SIM Port B Data Dir Reg */
45#define SIMPPARB (*(portb) (MBASE+0x001F)) /* SIM Port B Pin Asm Reg */
46#define SIMSWIV (*(portb) (MBASE+0x0020)) /* SIM SW Interrupt Vector */
47#define SIMSYPCR (*(portb) (MBASE+0x0021)) /* SIM System Prot Cont Reg */
48#define SIMPICR (*(portw) (MBASE+0x0022)) /* SIM Period Intr Cont Reg */
49#define SIMPITR (*(portw) (MBASE+0x0024)) /* SIM Period Intr Tmg Reg */
50#define SIMSWSR (*(portb) (MBASE+0x0027)) /* SIM Software Service Reg */
51
52#define SIMCS0AM (*(portl) (MBASE+0x0040)) /* SIM Chp Sel 0 Addr Msk */
53#define SIMCS0AM1 (*(portw) (MBASE+0x0040)) /* SIM Chp Sel 0 Addr Msk 1 */
54#define SIMCS0AM2 (*(portw) (MBASE+0x0042)) /* SIM Chp Sel 0 Addr Msk 2 */
55#define SIMCS0BA (*(portl) (MBASE+0x0044)) /* SIM Chp Sel 0 Base Addr */
56#define SIMCS0BA1 (*(portw) (MBASE+0x0044)) /* SIM Chp Sel 0 Bas Addr 1 */
57#define SIMCS0BA2 (*(portw) (MBASE+0x0046)) /* SIM Chp Sel 0 Bas Addr 2 */
58#define SIMCS1AM (*(portl) (MBASE+0x0048)) /* SIM Chp Sel 1 Adress Msk */
59#define SIMCS1AM1 (*(portw) (MBASE+0x0048)) /* SIM Chp Sel 1 Addr Msk 1 */
60#define SIMCS1AM2 (*(portw) (MBASE+0x004A)) /* SIM Chp Sel 1 Addr Msk 2 */
61#define SIMCS1BA (*(portl) (MBASE+0x004C)) /* SIM Chp Sel 1 Base Addr */
62#define SIMCS1BA1 (*(portw) (MBASE+0x004C)) /* SIM Chp Sel 1 Bas Addr 1 */
63#define SIMCS1BA2 (*(portw) (MBASE+0x004E)) /* SIM Chp Sel 1 Bas Addr 2 */
64#define SIMCS2AM (*(portl) (MBASE+0x0050)) /* SIM Chp Sel 2 Addr Msk */
65#define SIMCS2AM1 (*(portw) (MBASE+0x0050)) /* SIM Chp Sel 2 Addr Msk 1 */
66#define SIMCS2AM2 (*(portw) (MBASE+0x0052)) /* SIM Chp Sel 2 Addr Msk 2 */
67#define SIMCS2BA (*(portl) (MBASE+0x0054)) /* SIM Chp Sel 2 Base Addr */
68#define SIMCS2BA1 (*(portw) (MBASE+0x0054)) /* SIM Chp Sel 2 Bas Addr 1 */
69#define SIMCS2BA2 (*(portw) (MBASE+0x0056)) /* SIM Chp Sel 2 Bas Addr 2 */
70#define SIMCS3AM (*(portl) (MBASE+0x0058)) /* SIM Chp Sel 3 Addr Msk */
71#define SIMCS3AM1 (*(portw) (MBASE+0x0058)) /* SIM Chp Sel 3 Addr Msk 1 */
72#define SIMCS3AM2 (*(portw) (MBASE+0x005A)) /* SIM Chp Sel 3 Addr Msk 2 */
73#define SIMCS3BA (*(portl) (MBASE+0x005C)) /* SIM Chp Sel 3 Base Addr */
74#define SIMCS3BA1 (*(portw) (MBASE+0x005C)) /* SIM Chp Sel 3 Bas Addr 1 */
75#define SIMCS3BA2 (*(portw) (MBASE+0x005E)) /* SIM Chp Sel 3 Bas Addr 2 */
76
77/* Dynamic Memory Access (DMA) Module */
78
79#define DMAMCR1 (*(portw) (MBASE+0x0780)) /* DMA Module Config Reg 1 */
80#define DMAINTR1 (*(portw) (MBASE+0x0784)) /* DMA Interrupt Reg 1 */
81#define DMACCR1 (*(portw) (MBASE+0x0788)) /* DMA Channel Cont Reg 1 */
82#define DMACSR1 (*(portb) (MBASE+0x078A)) /* DMA Channel Status Reg 1 */
83#define DMAFCR1 (*(portb) (MBASE+0x078B)) /* DMA Function Code Reg 1 */
84#define DMASAR1 (*(portl) (MBASE+0x078C)) /* DMA DMA Src Addr Reg 1 */
85#define DMADAR1 (*(portl) (MBASE+0x0790)) /* DMA Dest Addr Reg 1 */
86#define DMABTC1 (*(portb) (MBASE+0x079l)) /* DMA Byte Trans Cnt Reg 1 */
87
88#define DMAMCR2 (*(portw) (MBASE+0x07A0)) /* DMA Module Config Reg 2 */
89#define DMAINTR2 (*(portw) (MBASE+0x07A4)) /* DMA Interrupt Reg 2 */
90#define DMACCR2 (*(portw) (MBASE+0x07A8)) /* DMA Channel Cont Reg 2 */
91#define DMACSR2 (*(portb) (MBASE+0x07AA)) /* DMA Channel Status Reg 2 */
92#define DMAFCR2 (*(portb) (MBASE+0x07AB)) /* DMA Function Code Reg 1 */
93#define DMASAR2 (*(portl) (MBASE+0x07AC)) /* DMA Source Addr Reg 2 */
94#define DMADAR2 (*(portl) (MBASE+0x07B0)) /* DMA Dest Addr Reg 2 */
95#define DMABTC2 (*(portb) (MBASE+0x07B4)) /* DMA Byte Trans Cnt Reg 2 */
96
97/* Dual Serial Module */
98
99#define DUMCRH (*(portb) (MBASE+0x0700)) /* DUART Module Config Reg */
100#define DUMCRL (*(portb) (MBASE+0x0701)) /* DUART Module Config Reg */
101#define DUILR (*(portb) (MBASE+0x0704)) /* DUART Interrupt Level */
102#define DUIVR (*(portb) (MBASE+0x0705)) /* DUART Interrupt Vector */
103#define DUMR1A (*(portb) (MBASE+0x0710)) /* DUART Mode Reg 1A */
104#define DUSRA (*(portb) (MBASE+0x0711)) /* DUART Status Reg A */
105#define DUCSRA (*(portb) (MBASE+0x0711)) /* DUART Clock Sel Reg A */
106#define DUCRA (*(portb) (MBASE+0x0712)) /* DUART Command Reg A */
107#define DURBA (*(portb) (MBASE+0x0713)) /* DUART Receiver Buffer A */
108#define DUTBA (*(portb) (MBASE+0x0713)) /* DUART Transmitter Buff A */
109#define DUIPCR (*(portb) (MBASE+0x0714)) /* DUART Input Port Chg Reg */
110#define DUACR (*(portb) (MBASE+0x0714)) /* DUART Auxiliary Cont Reg */
111#define DUISR (*(portb) (MBASE+0x0715)) /* DUART Interrupt Stat Reg */
112#define DUIER (*(portb) (MBASE+0x0715)) /* DUART Interrupt Enb Reg */
113
114#define DUMR1B (*(portb) (MBASE+0x0718)) /* DUART Mode Reg 1B */
115#define DUSRB (*(portb) (MBASE+0x0719)) /* DUART Status Reg B */
116#define DUCSRB (*(portb) (MBASE+0x0719)) /* DUART Clock Sel Reg B */
117#define DUCRB (*(portb) (MBASE+0x071A)) /* DUART Command Reg B */
118#define DURBB (*(portb) (MBASE+0x071B)) /* DUART Receiver Buffer B */
119#define DUTBB (*(portb) (MBASE+0x071B)) /* DUART Transmitter Buff B */
120#define DUIP (*(portb) (MBASE+0x071D)) /* DUART Input Port Reg */
121#define DUOPCR (*(portb) (MBASE+0x071D)) /* DUART Outp Port Cnt Reg */
122#define DUOPBS (*(portb) (MBASE+0x071E)) /* DUART Outp Port Bit Set */
123#define DUOPBR (*(portb) (MBASE+0x071F)) /* DUART Outp Port Bit Rst */
124#define DUMR2A (*(portb) (MBASE+0x0720)) /* DUART Mode Reg 2A */
125#define DUMR2B (*(portb) (MBASE+0x0721)) /* DUART Mode Reg 2B */
126
127/* Dual Timer Module */
128
129#define TMCR1 (*(portw) (MBASE+0x0600)) /* Timer Module Config Reg 1 */
130#define TIR1 (*(portw) (MBASE+0x0604)) /* Timer Interrupt Reg 1 */
131#define TCR1 (*(portw) (MBASE+0x0606)) /* Timer Control Reg 1 */
132#define TSR1 (*(portw) (MBASE+0x0608)) /* Timer Status Reg 1 */
133#define TCNTR1 (*(portw) (MBASE+0x060A)) /* Timer Counter Reg 1 */
134#define WPREL11 (*(portw) (MBASE+0x060C)) /* Timer Preload 1 Reg 1 */
135#define WPREL21 (*(portw) (MBASE+0x060E)) /* Timer Preload 2 Reg 1 */
136#define TCOM1 (*(portw) (MBASE+0x0610)) /* Timer Compare Reg 1 */
137
138#define TMCR2 (*(portw) (MBASE+0x0640)) /* Timer Module Config Reg 2 */
139#define TIR2 (*(portw) (MBASE+0x0644)) /* Timer Interrupt Reg 2 */
140#define TCR2 (*(portw) (MBASE+0x0646)) /* Timer Control Reg 2 */
141#define TSR2 (*(portw) (MBASE+0x0648)) /* Timer Status Reg 2 */
142#define TCNTR2 (*(portw) (MBASE+0x064A)) /* Timer Counter Reg 2 */
143#define WPREL12 (*(portw) (MBASE+0x064C)) /* Timer Preload 1 Reg 2 */
144#define WPREL22 (*(portw) (MBASE+0x064E)) /* Timer Preload 2 Reg 2 */
145#define TCOM2 (*(portw) (MBASE+0x0650)) /* Timer Compare Reg 2 */