RTEMS: bsps/arm/atsam/include/libchip/include/samv71/component/component_ssc.h Source File

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component_ssc.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMV71_SSC_COMPONENT_
31#define _SAMV71_SSC_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __O uint32_t SSC_CR;
43 __IO uint32_t SSC_CMR;
44 __I uint32_t Reserved1[2];
45 __IO uint32_t SSC_RCMR;
46 __IO uint32_t SSC_RFMR;
47 __IO uint32_t SSC_TCMR;
48 __IO uint32_t SSC_TFMR;
49 __I uint32_t SSC_RHR;
50 __O uint32_t SSC_THR;
51 __I uint32_t Reserved2[2];
52 __I uint32_t SSC_RSHR;
53 __IO uint32_t SSC_TSHR;
54 __IO uint32_t SSC_RC0R;
55 __IO uint32_t SSC_RC1R;
56 __I uint32_t SSC_SR;
57 __O uint32_t SSC_IER;
58 __O uint32_t SSC_IDR;
59 __I uint32_t SSC_IMR;
60 __I uint32_t Reserved3[37];
61 __IO uint32_t SSC_WPMR;
62 __I uint32_t SSC_WPSR;
63 __I uint32_t Reserved4[4];
64 __I uint32_t SSC_VERSION;
65} Ssc;
66#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
67/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
68#define SSC_CR_RXEN (0x1u << 0)
69#define SSC_CR_RXDIS (0x1u << 1)
70#define SSC_CR_TXEN (0x1u << 8)
71#define SSC_CR_TXDIS (0x1u << 9)
72#define SSC_CR_SWRST (0x1u << 15)
73/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
74#define SSC_CMR_DIV_Pos 0
75#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos)
76#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
77/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
78#define SSC_RCMR_CKS_Pos 0
79#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos)
80#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos)))
81#define SSC_RCMR_CKS_MCK (0x0u << 0)
82#define SSC_RCMR_CKS_TK (0x1u << 0)
83#define SSC_RCMR_CKS_RK (0x2u << 0)
84#define SSC_RCMR_CKO_Pos 2
85#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos)
86#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos)))
87#define SSC_RCMR_CKO_NONE (0x0u << 2)
88#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2)
89#define SSC_RCMR_CKO_TRANSFER (0x2u << 2)
90#define SSC_RCMR_CKI (0x1u << 5)
91#define SSC_RCMR_CKG_Pos 6
92#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos)
93#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos)))
94#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6)
95#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6)
96#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6)
97#define SSC_RCMR_START_Pos 8
98#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos)
99#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos)))
100#define SSC_RCMR_START_CONTINUOUS (0x0u << 8)
101#define SSC_RCMR_START_TRANSMIT (0x1u << 8)
102#define SSC_RCMR_START_RF_LOW (0x2u << 8)
103#define SSC_RCMR_START_RF_HIGH (0x3u << 8)
104#define SSC_RCMR_START_RF_FALLING (0x4u << 8)
105#define SSC_RCMR_START_RF_RISING (0x5u << 8)
106#define SSC_RCMR_START_RF_LEVEL (0x6u << 8)
107#define SSC_RCMR_START_RF_EDGE (0x7u << 8)
108#define SSC_RCMR_START_CMP_0 (0x8u << 8)
109#define SSC_RCMR_STOP (0x1u << 12)
110#define SSC_RCMR_STTDLY_Pos 16
111#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos)
112#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
113#define SSC_RCMR_PERIOD_Pos 24
114#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos)
115#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
116/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
117#define SSC_RFMR_DATLEN_Pos 0
118#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos)
119#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
120#define SSC_RFMR_LOOP (0x1u << 5)
121#define SSC_RFMR_MSBF (0x1u << 7)
122#define SSC_RFMR_DATNB_Pos 8
123#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos)
124#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
125#define SSC_RFMR_FSLEN_Pos 16
126#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos)
127#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
128#define SSC_RFMR_FSOS_Pos 20
129#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos)
130#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos)))
131#define SSC_RFMR_FSOS_NONE (0x0u << 20)
132#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20)
133#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20)
134#define SSC_RFMR_FSOS_LOW (0x3u << 20)
135#define SSC_RFMR_FSOS_HIGH (0x4u << 20)
136#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20)
137#define SSC_RFMR_FSEDGE (0x1u << 24)
138#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24)
139#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24)
140#define SSC_RFMR_FSLEN_EXT_Pos 28
141#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos)
142#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
143/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
144#define SSC_TCMR_CKS_Pos 0
145#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos)
146#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos)))
147#define SSC_TCMR_CKS_MCK (0x0u << 0)
148#define SSC_TCMR_CKS_RK (0x1u << 0)
149#define SSC_TCMR_CKS_TK (0x2u << 0)
150#define SSC_TCMR_CKO_Pos 2
151#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos)
152#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos)))
153#define SSC_TCMR_CKO_NONE (0x0u << 2)
154#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2)
155#define SSC_TCMR_CKO_TRANSFER (0x2u << 2)
156#define SSC_TCMR_CKI (0x1u << 5)
157#define SSC_TCMR_CKG_Pos 6
158#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos)
159#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos)))
160#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6)
161#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6)
162#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6)
163#define SSC_TCMR_START_Pos 8
164#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos)
165#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos)))
166#define SSC_TCMR_START_CONTINUOUS (0x0u << 8)
167#define SSC_TCMR_START_RECEIVE (0x1u << 8)
168#define SSC_TCMR_START_TF_LOW (0x2u << 8)
169#define SSC_TCMR_START_TF_HIGH (0x3u << 8)
170#define SSC_TCMR_START_TF_FALLING (0x4u << 8)
171#define SSC_TCMR_START_TF_RISING (0x5u << 8)
172#define SSC_TCMR_START_TF_LEVEL (0x6u << 8)
173#define SSC_TCMR_START_TF_EDGE (0x7u << 8)
174#define SSC_TCMR_STTDLY_Pos 16
175#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos)
176#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
177#define SSC_TCMR_PERIOD_Pos 24
178#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos)
179#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
180/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
181#define SSC_TFMR_DATLEN_Pos 0
182#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos)
183#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
184#define SSC_TFMR_DATDEF (0x1u << 5)
185#define SSC_TFMR_MSBF (0x1u << 7)
186#define SSC_TFMR_DATNB_Pos 8
187#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos)
188#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
189#define SSC_TFMR_FSLEN_Pos 16
190#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos)
191#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
192#define SSC_TFMR_FSOS_Pos 20
193#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos)
194#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos)))
195#define SSC_TFMR_FSOS_NONE (0x0u << 20)
196#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20)
197#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20)
198#define SSC_TFMR_FSOS_LOW (0x3u << 20)
199#define SSC_TFMR_FSOS_HIGH (0x4u << 20)
200#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20)
201#define SSC_TFMR_FSDEN (0x1u << 23)
202#define SSC_TFMR_FSEDGE (0x1u << 24)
203#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24)
204#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24)
205#define SSC_TFMR_FSLEN_EXT_Pos 28
206#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos)
207#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
208/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
209#define SSC_RHR_RDAT_Pos 0
210#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos)
211/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
212#define SSC_THR_TDAT_Pos 0
213#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos)
214#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
215/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
216#define SSC_RSHR_RSDAT_Pos 0
217#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos)
218/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
219#define SSC_TSHR_TSDAT_Pos 0
220#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos)
221#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
222/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
223#define SSC_RC0R_CP0_Pos 0
224#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos)
225#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
226/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
227#define SSC_RC1R_CP1_Pos 0
228#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos)
229#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
230/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
231#define SSC_SR_TXRDY (0x1u << 0)
232#define SSC_SR_TXEMPTY (0x1u << 1)
233#define SSC_SR_RXRDY (0x1u << 4)
234#define SSC_SR_OVRUN (0x1u << 5)
235#define SSC_SR_CP0 (0x1u << 8)
236#define SSC_SR_CP1 (0x1u << 9)
237#define SSC_SR_TXSYN (0x1u << 10)
238#define SSC_SR_RXSYN (0x1u << 11)
239#define SSC_SR_TXEN (0x1u << 16)
240#define SSC_SR_RXEN (0x1u << 17)
241/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
242#define SSC_IER_TXRDY (0x1u << 0)
243#define SSC_IER_TXEMPTY (0x1u << 1)
244#define SSC_IER_RXRDY (0x1u << 4)
245#define SSC_IER_OVRUN (0x1u << 5)
246#define SSC_IER_CP0 (0x1u << 8)
247#define SSC_IER_CP1 (0x1u << 9)
248#define SSC_IER_TXSYN (0x1u << 10)
249#define SSC_IER_RXSYN (0x1u << 11)
250/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
251#define SSC_IDR_TXRDY (0x1u << 0)
252#define SSC_IDR_TXEMPTY (0x1u << 1)
253#define SSC_IDR_RXRDY (0x1u << 4)
254#define SSC_IDR_OVRUN (0x1u << 5)
255#define SSC_IDR_CP0 (0x1u << 8)
256#define SSC_IDR_CP1 (0x1u << 9)
257#define SSC_IDR_TXSYN (0x1u << 10)
258#define SSC_IDR_RXSYN (0x1u << 11)
259/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
260#define SSC_IMR_TXRDY (0x1u << 0)
261#define SSC_IMR_TXEMPTY (0x1u << 1)
262#define SSC_IMR_RXRDY (0x1u << 4)
263#define SSC_IMR_OVRUN (0x1u << 5)
264#define SSC_IMR_CP0 (0x1u << 8)
265#define SSC_IMR_CP1 (0x1u << 9)
266#define SSC_IMR_TXSYN (0x1u << 10)
267#define SSC_IMR_RXSYN (0x1u << 11)
268/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */
269#define SSC_WPMR_WPEN (0x1u << 0)
270#define SSC_WPMR_WPKEY_Pos 8
271#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos)
272#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
273#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8)
274/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */
275#define SSC_WPSR_WPVS (0x1u << 0)
276#define SSC_WPSR_WPVSRC_Pos 8
277#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos)
278/* -------- SSC_VERSION : (SSC Offset: 0xFC) Version Register -------- */
279#define SSC_VERSION_VERSION_Pos 0
280#define SSC_VERSION_VERSION_Msk (0xffffu << SSC_VERSION_VERSION_Pos)
281#define SSC_VERSION_MFN_Pos 16
282#define SSC_VERSION_MFN_Msk (0x7u << SSC_VERSION_MFN_Pos)
285
286
287#endif /* _SAMV71_SSC_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Ssc
Ssc hardware registers.
Definition: component_ssc.h:41
Ssc::SSC_VERSION
__I uint32_t SSC_VERSION
(Ssc Offset: 0xFC) Version Register
Definition: component_ssc.h:64