RTEMS: bsps/arm/include/bsp/arm-pl111-regs.h Source File

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arm-pl111-regs.h
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1
9/*
10 * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
11 *
12 * embedded brains GmbH
13 * Dornierstr. 4
14 * 82178 Puchheim
15 * Germany
16 * <info@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_SHARED_ARM_PL111_REGS_H
24#define LIBBSP_ARM_SHARED_ARM_PL111_REGS_H
25
26#include <bsp/utility.h>
27
28 typedef struct {
29 uint32_t timing0;
30#define PL111_LCD_TIMING0_PPL(val) BSP_FLD32(val, 2, 7)
31#define PL111_LCD_TIMING0_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7)
32#define PL111_LCD_TIMING0_PPL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 7)
33#define PL111_LCD_TIMING0_HSW(val) BSP_FLD32(val, 8, 15)
34#define PL111_LCD_TIMING0_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15)
35#define PL111_LCD_TIMING0_HSW_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
36#define PL111_LCD_TIMING0_HFP(val) BSP_FLD32(val, 16, 23)
37#define PL111_LCD_TIMING0_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
38#define PL111_LCD_TIMING0_HFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
39#define PL111_LCD_TIMING0_HBP(val) BSP_FLD32(val, 24, 31)
40#define PL111_LCD_TIMING0_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
41#define PL111_LCD_TIMING0_HBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
42 uint32_t timing1;
43#define PL111_LCD_TIMING1_LPP(val) BSP_FLD32(val, 0, 9)
44#define PL111_LCD_TIMING1_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9)
45#define PL111_LCD_TIMING1_LPP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
46#define PL111_LCD_TIMING1_VSW(val) BSP_FLD32(val, 10, 15)
47#define PL111_LCD_TIMING1_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15)
48#define PL111_LCD_TIMING1_VSW_SET(reg, val) BSP_FLD32SET(reg, val, 10, 15)
49#define PL111_LCD_TIMING1_VFP(val) BSP_FLD32(val, 16, 23)
50#define PL111_LCD_TIMING1_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
51#define PL111_LCD_TIMING1_VFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
52#define PL111_LCD_TIMING1_VBP(val) BSP_FLD32(val, 24, 31)
53#define PL111_LCD_TIMING1_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
54#define PL111_LCD_TIMING1_VBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
55 uint32_t timing2;
56#define PL111_LCD_TIMING2_PCD_LO(val) BSP_FLD32(val, 0, 4)
57#define PL111_LCD_TIMING2_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4)
58#define PL111_LCD_TIMING2_PCD_LO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
59#define PL111_LCD_TIMING2_CLKSEL BSP_BIT32(5)
60#define PL111_LCD_TIMING2_ACB(val) BSP_FLD32(val, 6, 10)
61#define PL111_LCD_TIMING2_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10)
62#define PL111_LCD_TIMING2_ACB_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10)
63#define PL111_LCD_TIMING2_IVS BSP_BIT32(11)
64#define PL111_LCD_TIMING2_IHS BSP_BIT32(12)
65#define PL111_LCD_TIMING2_IPC BSP_BIT32(13)
66#define PL111_LCD_TIMING2_IOE BSP_BIT32(14)
67#define PL111_LCD_TIMING2_CPL(val) BSP_FLD32(val, 16, 25)
68#define PL111_LCD_TIMING2_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25)
69#define PL111_LCD_TIMING2_CPL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25)
70#define PL111_LCD_TIMING2_BCD BSP_BIT32(26)
71#define PL111_LCD_TIMING2_PCD_HI(val) BSP_FLD32(val, 27, 31)
72#define PL111_LCD_TIMING2_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31)
73#define PL111_LCD_TIMING2_PCD_HI_SET(reg, val) BSP_FLD32SET(reg, val, 27, 31)
74 uint32_t timing3;
75#define PL111_LCD_TIMING3_LED(val) BSP_FLD32(val, 0, 6)
76#define PL111_LCD_TIMING3_LED_GET(reg) BSP_FLD32GET(reg, 0, 6)
77#define PL111_LCD_TIMING3_LED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6)
78#define PL111_LCD_TIMING3_LEE BSP_BIT32(16)
79 uint32_t upbase;
80 uint32_t lpbase;
81 uint32_t control;
82#define PL111_LCD_CONTROL_LCD_EN BSP_BIT32(0)
83#define PL111_LCD_CONTROL_LCD_BPP(val) BSP_FLD32(val, 1, 3)
84#define PL111_LCD_CONTROL_LCD_BPP_GET(reg) BSP_FLD32GET(reg, 1, 3)
85#define PL111_LCD_CONTROL_LCD_BPP_SET(reg, val) BSP_FLD32SET(reg, val, 1, 3)
86#define PL111_LCD_CONTROL_LCD_BPP_1 0x00U
87#define PL111_LCD_CONTROL_LCD_BPP_2 0x01U
88#define PL111_LCD_CONTROL_LCD_BPP_4 0x02U
89#define PL111_LCD_CONTROL_LCD_BPP_8 0x03U
90#define PL111_LCD_CONTROL_LCD_BPP_16 0x04U
91#define PL111_LCD_CONTROL_LCD_BPP_24 0x05U
92#define PL111_LCD_CONTROL_LCD_BPP_16_5_6_5 0x06U
93#define PL111_LCD_CONTROL_LCD_BPP_12 0x07U
94#define PL111_LCD_CONTROL_LCD_BW BSP_BIT32(4)
95#define PL111_LCD_CONTROL_LCD_TFT BSP_BIT32(5)
96#define PL111_LCD_CONTROL_LCD_MONO8 BSP_BIT32(6)
97#define PL111_LCD_CONTROL_LCD_DUAL BSP_BIT32(7)
98#define PL111_LCD_CONTROL_BGR BSP_BIT32(8)
99#define PL111_LCD_CONTROL_BEBO BSP_BIT32(9)
100#define PL111_LCD_CONTROL_BEPO BSP_BIT32(10)
101#define PL111_LCD_CONTROL_LCD_PWR BSP_BIT32(11)
102#define PL111_LCD_CONTROL_LCD_V_COMP(val) BSP_FLD32(val, 12, 13)
103#define PL111_LCD_CONTROL_LCD_V_COMP_GET(reg) BSP_FLD32GET(reg, 12, 13)
104#define PL111_LCD_CONTROL_LCD_V_COMP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13)
105#define PL111_LCD_CONTROL_WATERMARK BSP_BIT32(16)
106 uint32_t imsc;
107 uint32_t ris;
108 uint32_t mis;
109 uint32_t icr;
110#define PL111_LCD_I_FUF BSP_BIT32(1)
111#define PL111_LCD_I_LNBU BSP_BIT32(2)
112#define PL111_LCD_I_VCOMP BSP_BIT32(3)
113#define PL111_LCD_I_MBERROR BSP_BIT32(4)
114 uint32_t upcurr;
115 uint32_t lpcurr;
116 uint32_t reserved_34[115];
117 uint16_t pal[256];
118#define PL111_LCD_PAL_R(val) BSP_FLD16(val, 0, 4)
119#define PL111_LCD_PAL_R_GET(reg) BSP_FLD16GET(reg, 0, 4)
120#define PL111_LCD_PAL_R_SET(reg, val) BSP_FLD16SET(reg, val, 0, 4)
121#define PL111_LCD_PAL_G(val) BSP_FLD16(val, 5, 9)
122#define PL111_LCD_PAL_G_GET(reg) BSP_FLD16GET(reg, 5, 9)
123#define PL111_LCD_PAL_G_SET(reg, val) BSP_FLD16SET(reg, val, 5, 9)
124#define PL111_LCD_PAL_B(val) BSP_FLD16(val, 10, 14)
125#define PL111_LCD_PAL_B_GET(reg) BSP_FLD16GET(reg, 10, 14)
126#define PL111_LCD_PAL_B_SET(reg, val) BSP_FLD16SET(reg, val, 10, 14)
127#define PL111_LCD_PAL_I BSP_BIT16(15)
128} pl111_lcd;
129
130 typedef struct {
131 uint8_t image[1024];
132 uint32_t ctrl;
133#define PL111_CRSR_CTRL_ON BSP_BIT32(0)
134#define PL111_CRSR_CTRL_NUMBER(val) BSP_FLD32(val, 4, 5)
135#define PL111_CRSR_CTRL_NUMBER_GET(reg) BSP_FLD32GET(reg, 4, 5)
136#define PL111_CRSR_CTRL_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5)
137 uint32_t config;
138#define PL111_CRSR_CONFIG_SIZE BSP_BIT32(0)
139#define PL111_CRSR_CONFIG_FRAME_SYNC BSP_BIT32(1)
140 uint32_t palette0;
141 uint32_t palette1;
142#define PL111_CRSR_PALETTE_RED(val) BSP_FLD32(val, 0, 7)
143#define PL111_CRSR_PALETTE_RED_GET(reg) BSP_FLD32GET(reg, 0, 7)
144#define PL111_CRSR_PALETTE_RED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
145#define PL111_CRSR_PALETTE_GREEN(val) BSP_FLD32(val, 8, 15)
146#define PL111_CRSR_PALETTE_GREEN_GET(reg) BSP_FLD32GET(reg, 8, 15)
147#define PL111_CRSR_PALETTE_GREEN_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
148#define PL111_CRSR_PALETTE_BLUE(val) BSP_FLD32(val, 16, 23)
149#define PL111_CRSR_PALETTE_BLUE_GET(reg) BSP_FLD32GET(reg, 16, 23)
150#define PL111_CRSR_PALETTE_BLUE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
151 uint32_t xy;
152#define PL111_CRSR_XY_X(val) BSP_FLD32(val, 0, 9)
153#define PL111_CRSR_XY_X_GET(reg) BSP_FLD32GET(reg, 0, 9)
154#define PL111_CRSR_XY_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
155#define PL111_CRSR_XY_X_EXP(val) BSP_FLD32(val, 10, 11)
156#define PL111_CRSR_XY_X_EXP_GET(reg) BSP_FLD32GET(reg, 10, 11)
157#define PL111_CRSR_XY_X_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 10, 11)
158#define PL111_CRSR_XY_Y(val) BSP_FLD32(val, 16, 25)
159#define PL111_CRSR_XY_Y_GET(reg) BSP_FLD32GET(reg, 16, 25)
160#define PL111_CRSR_XY_Y_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25)
161#define PL111_CRSR_XY_Y_EXP(val) BSP_FLD32(val, 25, 27)
162#define PL111_CRSR_XY_Y_EXP_GET(reg) BSP_FLD32GET(reg, 25, 27)
163#define PL111_CRSR_XY_Y_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 25, 27)
164 uint32_t clip;
165#define PL111_CRSR_CLIP_X(val) BSP_FLD32(val, 0, 5)
166#define PL111_CRSR_CLIP_X_GET(reg) BSP_FLD32GET(reg, 0, 5)
167#define PL111_CRSR_CLIP_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
168#define PL111_CRSR_CLIP_Y(val) BSP_FLD32(val, 8, 13)
169#define PL111_CRSR_CLIP_Y_GET(reg) BSP_FLD32GET(reg, 8, 13)
170#define PL111_CRSR_CLIP_Y_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13)
171 uint32_t imsc;
172 uint32_t icr;
173 uint32_t ris;
174 uint32_t mis;
175#define PL111_CRSR_I_CRSR BSP_BIT32(0)
176} pl111_crsr;
177
178 typedef struct {
179 pl111_lcd lcd;
180 uint32_t reserved_400[256];
181 pl111_crsr crsr;
182} pl111;
183
184#endif /* LIBBSP_ARM_SHARED_ARM_PL111_REGS_H */
utility.h
Utility macros.
config_s
Definition: deflate.c:115
control
Definition: intercom.c:74
lcd
Definition: 8xx_immap.h:201
pl111_crsr
Definition: arm-pl111-regs.h:130
pl111_lcd
Definition: arm-pl111-regs.h:28
pl111
Definition: arm-pl111-regs.h:178