RTEMS: L2 Cache Management API

| RTEMS 5.4-rc2

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Typedefs | Enumerations | Functions
L2 Cache Management API
Board Support Packages » ARM » Intel Cyclone V » Contributed Code » Cache Management API

## Typedefs
typedef enum ALT_CACHE_L2_INTERRUPT_e | ALT_CACHE_L2_INTERRUPT_t

## Enumerations
enum | ALT_CACHE_L2_INTERRUPT_e { ALT_CACHE_L2_INTERRUPT_DECERR = 1 << 8 , ALT_CACHE_L2_INTERRUPT_SLVERR = 1 << 7 , ALT_CACHE_L2_INTERRUPT_ERRRD = 1 << 6 , ALT_CACHE_L2_INTERRUPT_ERRRT = 1 << 5 , ALT_CACHE_L2_INTERRUPT_ERRWD = 1 << 4 , ALT_CACHE_L2_INTERRUPT_ERRWT = 1 << 3 , ALT_CACHE_L2_INTERRUPT_PARRD = 1 << 2 , ALT_CACHE_L2_INTERRUPT_PARRT = 1 << 1 , ALT_CACHE_L2_INTERRUPT_ECNTR = 1 << 0 }

## Functions
ALT_STATUS_CODE | alt_cache_l2_init (void)
ALT_STATUS_CODE | alt_cache_l2_uninit (void)
ALT_STATUS_CODE | alt_cache_l2_prefetch_enable (void)
ALT_STATUS_CODE | alt_cache_l2_prefetch_disable (void)
bool | alt_cache_l2_prefetch_is_enabled (void)
ALT_STATUS_CODE | alt_cache_l2_parity_enable (void)
ALT_STATUS_CODE | alt_cache_l2_parity_disable (void)
bool | alt_cache_l2_parity_is_enabled (void)
ALT_STATUS_CODE | alt_cache_l2_enable (void)
ALT_STATUS_CODE | alt_cache_l2_disable (void)
bool | alt_cache_l2_is_enabled (void)
ALT_STATUS_CODE | alt_cache_l2_sync (void)
ALT_STATUS_CODE | alt_cache_l2_invalidate (void *paddress, size_t length)
ALT_STATUS_CODE | alt_cache_l2_invalidate_all (void)
ALT_STATUS_CODE | alt_cache_l2_clean (void *paddress, size_t length)
ALT_STATUS_CODE | alt_cache_l2_clean_all (void)
ALT_STATUS_CODE | alt_cache_l2_purge (void *paddress, size_t length)
ALT_STATUS_CODE | alt_cache_l2_purge_all (void)
ALT_STATUS_CODE | alt_cache_l2_int_enable (uint32_t interrupt)
ALT_STATUS_CODE | alt_cache_l2_int_disable (uint32_t interrupt)
uint32_t | alt_cache_l2_int_status_get (void)
ALT_STATUS_CODE | alt_cache_l2_int_status_clear (uint32_t interrupt)

## Detailed Description

This API group provides functions to interact with various features of the L2 cache on the SoCFPGA. This includes the following features:

- L2 cache
- Parity error detection
- Data prefetching
- Interrupt Management

The API within this group affects the L2 cache which is visible to all CPUs on the system.

With respect to bring-up, the L1 and L2 cache controller setups are fully independent. The L2 can be setup at any time, before or after the L1 is setup.

## Enumeration Type Documentation

## ◆ ALT_CACHE_L2_INTERRUPT_e

enum ALT_CACHE_L2_INTERRUPT_e

This type definition enumerates all the interrupt conditions that can be generated by the L2 cache controller as register mask values.

Enumerator
ALT_CACHE_L2_INTERRUPT_DECERR | Decode error received on the master ports from L3.
ALT_CACHE_L2_INTERRUPT_SLVERR | Slave error received on the master ports from L3.
ALT_CACHE_L2_INTERRUPT_ERRRD | Error on the L2 data RAM read.
ALT_CACHE_L2_INTERRUPT_ERRRT | Error on the L2 tag RAM read.
ALT_CACHE_L2_INTERRUPT_ERRWD | Error on the L2 data RAM write.
ALT_CACHE_L2_INTERRUPT_ERRWT | Error on the L2 tag RAM write.
ALT_CACHE_L2_INTERRUPT_PARRD | Parity error on the L2 data RAM read.
ALT_CACHE_L2_INTERRUPT_PARRT | Parity error on the L2 tag RAM read.
ALT_CACHE_L2_INTERRUPT_ECNTR | Event counter overflow or increment.

## Function Documentation

## ◆ alt_cache_l2_clean()

ALT_STATUS_CODE alt_cache_l2_clean | ( | void * | paddress,
|  | size_t | length
| ) |  |

Cleans the specified contents of the L2 cache for the given memory segment.

The memory segment address and length specified must align to the characteristics of the cache line. This means the address and length must be multiples of the cache line size. To determine the cache line size, use the ALT_CACHE_LINE_SIZE macro.

Parameters

  paddress | The physical address of the memory segment to be cleaned.
  length | The length of the memory segment to be cleaned.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.
  ALT_E_BAD_ARG | The memory segment is invalid.
  ALT_E_TMO | The memory operation timed out.

## ◆ alt_cache_l2_clean_all()

ALT_STATUS_CODE alt_cache_l2_clean_all | ( | void |  | ) |

Cleans the entire L2 cache. All L2 cache controller interrupts will be temporarily disabled while the clean operation is in progress and restored once the it is finished.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.
  ALT_E_TMO | The memory operation timed out.

## ◆ alt_cache_l2_disable()

ALT_STATUS_CODE alt_cache_l2_disable | ( | void |  | ) |

Disables the L2 cache.

If the L2 cache is already disabled, nothing is done. Otherwise the entire contents of the cache is first cleaned before being disabled.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.

## ◆ alt_cache_l2_enable()

ALT_STATUS_CODE alt_cache_l2_enable | ( | void |  | ) |

Enables the L2 cache.

If the L2 cache is already enabled, nothing is done. Otherwise the entire contents of the cache is first invalidated before being enabled.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.

## ◆ alt_cache_l2_init()

ALT_STATUS_CODE alt_cache_l2_init | ( | void |  | ) |

Initializes the L2 cache controller.

Return values

  ALT_E_SUCCESS | Successful status.
  ALT_E_ERROR | Details about error status code

## ◆ alt_cache_l2_int_disable()

ALT_STATUS_CODE alt_cache_l2_int_disable | ( | uint32_t | interrupt | ) |

Disables the L2 cache controller interrupts for the specified set of condition(s).

Parameters

  interrupt | A register mask of the selected L2 cache controller interrupting conditions.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.

## ◆ alt_cache_l2_int_enable()

ALT_STATUS_CODE alt_cache_l2_int_enable | ( | uint32_t | interrupt | ) |

Enables the L2 cache controller interrupts for the specified set of condition(s).

Parameters

  interrupt | A register mask of the selected L2 cache controller interrupting conditions.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.

## ◆ alt_cache_l2_int_status_clear()

ALT_STATUS_CODE alt_cache_l2_int_status_clear | ( | uint32_t | interrupt | ) |

Clears the specified conditon(s) causing the L2 cache controller to interrupt as a mask. Condition(s) specified which are not causing an interrupt or condition(s) specified which are not enabled are ignored.

Parameters

  interrupt | A register mask of the selected L2 cache controller interrupting conditions.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.

## ◆ alt_cache_l2_int_status_get()

uint32_t alt_cache_l2_int_status_get | ( | void |  | ) |

Gets the condition(s) causing the L2 cache controller to interrupt as a register mask.

Returns
  A register mask of the currently asserted and enabled conditions resulting in an interrupt being generated.

## ◆ alt_cache_l2_invalidate()

ALT_STATUS_CODE alt_cache_l2_invalidate | ( | void * | paddress,
|  | size_t | length
| ) |  |

Invalidates the specified contents of the L2 cache for the given memory segment.

The memory segment address and length specified must align to the characteristics of the cache line. This means the address and length must be multiples of the cache line size. To determine the cache line size, use the ALT_CACHE_LINE_SIZE macro.

Parameters

  paddress | The physical address of the memory segment to be invalidated.
  length | The length of the memory segment to be invalidated.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.
  ALT_E_BAD_ARG | The memory segment is invalid.
  ALT_E_TMO | The memory operation timed out.

## ◆ alt_cache_l2_invalidate_all()

ALT_STATUS_CODE alt_cache_l2_invalidate_all | ( | void |  | ) |

Invalidates th entire contents of the L2 cache.

Normally this is done automatically as part of alt_cache_l2_enable(), but in certain circumstances it may be necessary to invalidate it manually. An example of this situation is when the address space is remapped and the processor accesses memory from the new memory area.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.
  ALT_E_TMO | The memory operation timed out.

## ◆ alt_cache_l2_is_enabled()

bool alt_cache_l2_is_enabled | ( | void |  | ) |

Returns true when the L2 cache is enabled and false when it is disabled.

Return values

  true | The L2 cache is enabled.
  false | The L2 cache is disabled.

## ◆ alt_cache_l2_parity_disable()

ALT_STATUS_CODE alt_cache_l2_parity_disable | ( | void |  | ) |

Disables parity error detection in the L2 cache.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.

## ◆ alt_cache_l2_parity_enable()

ALT_STATUS_CODE alt_cache_l2_parity_enable | ( | void |  | ) |

Enables parity error detection in the L2 cache.

Ideally parity should be enabled before the L2 cache is enabled. If the cache is already enabled, it will first be cleaned and disabled before parity is enabled in hardware. Afterwards, the cache will be invalidated and enabled.

For a parity error to be reported, the ALT_CACHE_L2_INTERRUPT_PARRD and / or ALT_CACHE_L2_INTERRUPT_PARRT interrupt condition(s) must be enabled. This is done by calling alt_cache_l2_int_enable(). As well, the L2 cache interrupt must be enabled using the interrupt controller API. Refer to the interrupt controller API for more details about programming the interrupt controller.

In the event of a parity error is detected, the appropriate L2 cache parity interrupt will be raised. To clear the parity interrupt(s), the appropriate L2 cache parity interrupt must be cleared by calling alt_cache_l2_int_status_clear().

For ECC support, refer to the ECC related API documentation for more information.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.

## ◆ alt_cache_l2_parity_is_enabled()

bool alt_cache_l2_parity_is_enabled | ( | void |  | ) |

Returns true when parity error detection is enabled and false when it is disabled.

Return values

  true | The L2 cache parity error detection feature is enabled.
  false | The L2 cache parity error detection feature is disabled.

## ◆ alt_cache_l2_prefetch_disable()

ALT_STATUS_CODE alt_cache_l2_prefetch_disable | ( | void |  | ) |

Disables the L2 cache features for data and instruction prefetching.

Prefetching can be enabled or disabled while the L2 cache is enabled.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.

## ◆ alt_cache_l2_prefetch_enable()

ALT_STATUS_CODE alt_cache_l2_prefetch_enable | ( | void |  | ) |

Enables the L2 cache features for data and instruction prefetching.

Prefetching can be enabled or disabled while the L2 cache is enabled.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.

## ◆ alt_cache_l2_prefetch_is_enabled()

bool alt_cache_l2_prefetch_is_enabled | ( | void |  | ) |

Returns true if either L2 cache data or instruction prefetch features are enabled and false if no prefetching features are enabled.

Return values

  true | The L2 data and instruction prefetch features are enabled.
  false | Some L2 data and instruction prefetch features are disabled.

## ◆ alt_cache_l2_purge()

ALT_STATUS_CODE alt_cache_l2_purge | ( | void * | paddress,
|  | size_t | length
| ) |  |

Cleans and invalidates the specified contents of the L2 cache for the given memory segment.

The memory segment address and length specified must align to the characteristics of the cache line. This means the address and length must be multiples of the cache line size. To determine the cache line size, use the ALT_CACHE_LINE_SIZE macro.

Parameters

  paddress | The physical address of the memory segment to be purged.
  length | The length of the memory segment to be purged.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.
  ALT_E_BAD_ARG | The memory segment is invalid.

## ◆ alt_cache_l2_purge_all()

ALT_STATUS_CODE alt_cache_l2_purge_all | ( | void |  | ) |

Cleans and invalidates the entire L2 cache. All L2 cache controller interrupts will be temporarily disabled while the clean and invalidate operation is in progress and restored once the it is finished.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.
  ALT_E_TMO | The memory operation timed out.

## ◆ alt_cache_l2_sync()

ALT_STATUS_CODE alt_cache_l2_sync | ( | void |  | ) |

Flushes the L2 cache controller hardware buffers.

Return values

  ALT_E_SUCCESS | The operation was successful.
  ALT_E_ERROR | The operation failed.
  ALT_E_TMO | The memory operation timed out.

## ◆ alt_cache_l2_uninit()

ALT_STATUS_CODE alt_cache_l2_uninit | ( | void |  | ) |

Uninitializes the L2 cache controller.

Return values

  ALT_E_SUCCESS | Successful status.
  ALT_E_ERROR | Details about error status code