RTEMS: bsps/m68k/include/mvme16x_hw.h Source File

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mvme16x_hw.h
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1
9/* mvme16x_hw.h
10 *
11 * This include file contains all MVME16x board IO definitions
12 * and was derived by combining the common items in the
13 * mvme162 and mvme167 BSPs.
14 *
15 * COPYRIGHT (c) 1989-2000.
16 * On-Line Applications Research Corporation (OAR).
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef __MVME16xHW_h
24#define __MVME16xHW_h
25
26#include <bsp.h>
27
28#ifdef __cplusplus
29extern "C" {
30#endif
31
40struct rtems_bsdnet_ifconfig;
41int uti596_attach(struct rtems_bsdnet_ifconfig * pConfig, int attaching );
42#define RTEMS_BSP_NETWORK_DRIVER_NAME "uti1"
43#define RTEMS_BSP_NETWORK_DRIVER_ATTACH uti596_attach
44
45/*
46 * This is NOT the base address of local RAM!
47 * This is the base local address of the VMEbus short I/O space. A local
48 * access to this space results in a A16 VMEbus I/O cycle. This base address
49 * is NOT configurable on the MVME167, although the types of VMEbus short I/O
50 * cycles generated when a cycle in the local 0xFFFF0000-0xFFFFFFFF address
51 * range is generated is under control of bits 8-15 of LCSR 0xFFF4002C. The
52 * GCSRs of other boards are accessible only through the VMEbus short I/O
53 * space. See pages 2-45 and 2-7.
54 */
55#define BOARD_BASE_ADDRESS 0xFFFF0000
56
57/*
58 * This address must be added to the BOARD_BASE_ADDRESS to access the GCSR of
59 * other MVMEs in the group, i.e. it represents the offset of the GCSRs in the
60 * VMEbus short I/O space. It also should represent the group address of this
61 * MVME167! The group address is configurable, and must match the address
62 * programmed into the MVME167 through the 167Bug monitor. 0xCC is the address
63 * recommended by Motorola. It is arbitrary.
64 * See pages 2-42 and 2-97 to 2-104.
65 */
66#define GROUP_BASE_ADDRESS 0x0000CC00
67
68/*
69 * Representation of the VMEchip2 LCSR.
70 * Could be made more detailed.
71 */
72
73 typedef volatile struct {
74 unsigned long slave_adr[2];
75 unsigned long slave_trn[2];
76 unsigned long slave_ctl;
77 unsigned long mastr_adr[4];
78 unsigned long mastr_trn;
79 unsigned long mastr_att;
80 unsigned long mastr_ctl;
81 unsigned long dma_ctl_1;
82 unsigned long dma_ctl_2;
83 unsigned long dma_loc_cnt;
84 unsigned long dma_vme_cnt;
85 unsigned long dma_byte_cnt;
86 unsigned long dma_adr_cnt;
87 unsigned long dma_status;
88 unsigned long to_ctl;
89 unsigned long timer_cmp_1;
90 unsigned long timer_cnt_1;
91 unsigned long timer_cmp_2;
92 unsigned long timer_cnt_2;
93 unsigned long board_ctl;
94 unsigned long prescaler_cnt;
95 unsigned long intr_stat;
96 unsigned long intr_ena;
97 unsigned long intr_soft_set;
98 unsigned long intr_clear;
99 unsigned long intr_level[4];
100 unsigned long vector_base;
101} lcsr_regs;
102
103/*
104 * Base address of VMEchip2 LCSR
105 * Not configurable on the MVME167.
106 * XXX what about 162?
107 */
108#define lcsr ((lcsr_regs * const) 0xFFF40000)
109
110/*
111 * Vector numbers for the interrupts from the VMEchip2. Use the values
112 * "recommended" by Motorola.
113 * See pages 2-70 to 2-92, and table 2-3.
114 */
115
116/* MIEN (Master Interrupt Enable) bit in LCSR 0xFFF40088. */
117#define MASK_INT 0x00800000
118
119/* The content of VBR0 corresponds to "X" in table 2-3 */
120#define VBR0 0x6
121
122/* The content of VBR1 corresponds to "Y" in table 2-3 */
123#define VBR1 0x7
124
125/*
126 * Representation of the PCCchip2
127 */
128 typedef volatile struct pccchip2_regs_ {
129 unsigned char chip_id; /* 0xFFF42000 */
130 unsigned char chip_revision; /* 0xFFF42001 */
131 unsigned char gen_control; /* 0xFFF42002 */
132 unsigned char vector_base; /* 0xFFF42003 */
133 unsigned long timer_cmp_1; /* 0xFFF42004 */
134 unsigned long timer_cnt_1; /* 0xFFF42008 */
135 unsigned long timer_cmp_2; /* 0xFFF4200C */
136 unsigned long timer_cnt_2; /* 0xFFF42010 */
137 unsigned char LSB_prescaler_count;/* 0xFFF42014 */
138 unsigned char prescaler_clock_adjust; /* 0xFFF42015 */
139 unsigned char timer_ctl_2; /* 0xFFF42016 */
140 unsigned char timer_ctl_1; /* 0xFFF42017 */
141 unsigned char gpi_int_ctl; /* 0xFFF42018 */
142 unsigned char gpio_ctl; /* 0xFFF42019 */
143 unsigned char timer_int_ctl_2; /* 0xFFF4201A */
144 unsigned char timer_int_ctl_1; /* 0xFFF4201B */
145 unsigned char SCC_error; /* 0xFFF4201C */
146 unsigned char SCC_modem_int_ctl; /* 0xFFF4201D */
147 unsigned char SCC_tx_int_ctl; /* 0xFFF4201E */
148 unsigned char SCC_rx_int_ctl; /* 0xFFF4201F */
149 unsigned char reserved1[3];
150 unsigned char modem_piack; /* 0xFFF42023 */
151 unsigned char reserved2;
152 unsigned char tx_piack; /* 0xFFF42025 */
153 unsigned char reserved3;
154 unsigned char rx_piack; /* 0xFFF42027 */
155 unsigned char LANC_error; /* 0xFFF42028 */
156 unsigned char reserved4;
157 unsigned char LANC_int_ctl; /* 0xFFF4202A */
158 unsigned char LANC_berr_ctl; /* 0xFFF4202B */
159 unsigned char SCSI_error; /* 0xFFF4202C */
160 unsigned char reserved5[2];
161 unsigned char SCSI_int_ctl; /* 0xFFF4202F */
162 unsigned char print_ack_int_ctl; /* 0xFFF42030 */
163 unsigned char print_fault_int_ctl;/* 0xFFF42031 */
164 unsigned char print_sel_int_ctl; /* 0xFFF42032 */
165 unsigned char print_pe_int_ctl; /* 0xFFF42033 */
166 unsigned char print_busy_int_ctl; /* 0xFFF42034 */
167 unsigned char reserved6;
168 unsigned char print_input_status; /* 0xFFF42036 */
169 unsigned char print_ctl; /* 0xFFF42037 */
170 unsigned char chip_speed; /* 0xFFF42038 */
171 unsigned char reserved7;
172 unsigned char print_data; /* 0xFFF4203A */
173 unsigned char reserved8[3];
174 unsigned char int_level; /* 0xFFF4203E */
175 unsigned char int_mask; /* 0xFFF4203F */
176} pccchip2_regs;
177
178/*
179 * Base address of the PCCchip2.
180 * This is not configurable in the MVME167.
181 */
182#define pccchip2 ((pccchip2_regs * const) 0xFFF42000)
183
184/*
185 * On the MVME162, we have the mcchip and the pccchip2 on
186 * the 167. They are similar but different enough where
187 * we have to reconcile them later.
188 */
189
190/*
191 * Vector numbers for the interrupts from the PCCchip2. Use the values
192 * "recommended" by Motorola.
193 * See page 3-15.
194 */
195#define PCCCHIP2_VBR 0x5
196
197/*
198 * The following registers are located in the VMEbus short
199 * IO space and respond to address modifier codes $29 and $2D.
200 * On FORCE CPU use address gcsr_vme and device /dev/vme16d32.
201 */
202
203 typedef volatile struct {
204 unsigned char chip_revision;
205 unsigned char chip_id;
206 unsigned char lmsig;
207 unsigned char board_scr;
208 unsigned short gpr[6];
209} gcsr_regs;
210
211#define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
212#define gcsr ((gcsr_regs * const) 0xFFF40100)
213
214/*
215 * Representation of 82596CA LAN controller: Memory Map
216 */
217 typedef volatile struct i82596_regs_ {
218 unsigned short port_lower; /* 0xFFF46000 */
219 unsigned short port_upper; /* 0xFFF46002 */
220 unsigned long chan_attn; /* 0xFFF46004 */
221} i82596_regs;
222
223/*
224 * Base address of the 82596.
225 */
226
227#define i82596 ((i82596_regs * const) 0xFFF46000)
228
229/*
230 * Representation of initialization data in NVRAM
231 */
232
233#if defined(mvme167)
234typedef volatile struct nvram_config_ {
235 unsigned char cache_mode; /* 0xFFFC0000 */
236 unsigned char console_mode; /* 0xFFFC0001 */
237 unsigned char console_printk_port; /* 0xFFFC0002 */
238 unsigned char pad1; /* 0xFFFC0003 */
239 unsigned long ipaddr; /* 0xFFFC0004 */
240 unsigned long netmask; /* 0xFFFC0008 */
241 unsigned char enaddr[6]; /* 0xFFFC000C */
242 unsigned short processor_id; /* 0xFFFC0012 */
243 unsigned long rma_start; /* 0xFFFC0014 */
244 unsigned long vma_start; /* 0xFFFC0018 */
245 unsigned long ramsize; /* 0xFFFC001C */
246} nvram_config;
247
248/*
249 * Pointer to the base of User Area NVRAM
250 */
251
252#define nvram ((nvram_config * const) 0xFFFC0000)
253
254#endif
255
256/*
257 * Flag to indicate if J1-4 is on (and parameters should be
258 * sought in User Area NVRAM)
259 *
260 * NOTE: If NVRAM has bad settings, the you want to disable this
261 * on the MVME167.
262 */
263#if defined(mvme167)
264 #define NVRAM_CONFIGURE \
265 ( !( ( (unsigned char)(lcsr->vector_base & 0xFF) ) & 0x10 ) )
266#else
267 #define NVRAM_CONFIGURE 0
268#endif
269
270#ifdef __cplusplus
271}
272#endif
273
274#endif
gcsr_regs
Definition: mvme16x_hw.h:203
i82596_regs_
Definition: mvme16x_hw.h:217
lcsr_regs
Definition: mvme16x_hw.h:73
pccchip2_regs_
Definition: mvme16x_hw.h:128