RTEMS: bsps/arm/atsam/include/libchip/include/same70/component/component_pio.h Source File

| RTEMS 5.4-rc2

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component_pio.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAME70_PIO_COMPONENT_
31#define _SAME70_PIO_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41 typedef struct {
42 __O uint32_t PIO_PER;
43 __O uint32_t PIO_PDR;
44 __I uint32_t PIO_PSR;
45 __I uint32_t Reserved1[1];
46 __O uint32_t PIO_OER;
47 __O uint32_t PIO_ODR;
48 __I uint32_t PIO_OSR;
49 __I uint32_t Reserved2[1];
50 __O uint32_t PIO_IFER;
51 __O uint32_t PIO_IFDR;
52 __I uint32_t PIO_IFSR;
53 __I uint32_t Reserved3[1];
54 __O uint32_t PIO_SODR;
55 __O uint32_t PIO_CODR;
56 __IO uint32_t PIO_ODSR;
57 __I uint32_t PIO_PDSR;
58 __O uint32_t PIO_IER;
59 __O uint32_t PIO_IDR;
60 __I uint32_t PIO_IMR;
61 __I uint32_t PIO_ISR;
62 __O uint32_t PIO_MDER;
63 __O uint32_t PIO_MDDR;
64 __I uint32_t PIO_MDSR;
65 __I uint32_t Reserved4[1];
66 __O uint32_t PIO_PUDR;
67 __O uint32_t PIO_PUER;
68 __I uint32_t PIO_PUSR;
69 __I uint32_t Reserved5[1];
70 __IO uint32_t PIO_ABCDSR[2];
71 __I uint32_t Reserved6[2];
72 __O uint32_t PIO_IFSCDR;
73 __O uint32_t PIO_IFSCER;
74 __I uint32_t PIO_IFSCSR;
75 __IO uint32_t PIO_SCDR;
76 __O uint32_t PIO_PPDDR;
77 __O uint32_t PIO_PPDER;
78 __I uint32_t PIO_PPDSR;
79 __I uint32_t Reserved7[1];
80 __O uint32_t PIO_OWER;
81 __O uint32_t PIO_OWDR;
82 __I uint32_t PIO_OWSR;
83 __I uint32_t Reserved8[1];
84 __O uint32_t PIO_AIMER;
85 __O uint32_t PIO_AIMDR;
86 __I uint32_t PIO_AIMMR;
87 __I uint32_t Reserved9[1];
88 __O uint32_t PIO_ESR;
89 __O uint32_t PIO_LSR;
90 __I uint32_t PIO_ELSR;
91 __I uint32_t Reserved10[1];
92 __O uint32_t PIO_FELLSR;
93 __O uint32_t PIO_REHLSR;
94 __I uint32_t PIO_FRLHSR;
95 __I uint32_t Reserved11[1];
96 __I uint32_t PIO_LOCKSR;
97 __IO uint32_t PIO_WPMR;
98 __I uint32_t PIO_WPSR;
99 __I uint32_t Reserved12[5];
100 __IO uint32_t PIO_SCHMITT;
101 __I uint32_t Reserved13[5];
102 __IO uint32_t PIO_DRIVER;
103 __I uint32_t Reserved14[13];
104 __IO uint32_t PIO_PCMR;
105 __O uint32_t PIO_PCIER;
106 __O uint32_t PIO_PCIDR;
107 __I uint32_t PIO_PCIMR;
108 __I uint32_t PIO_PCISR;
109 __I uint32_t PIO_PCRHR;
110} Pio;
111#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
112/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
113#define PIO_PER_P0 (0x1u << 0)
114#define PIO_PER_P1 (0x1u << 1)
115#define PIO_PER_P2 (0x1u << 2)
116#define PIO_PER_P3 (0x1u << 3)
117#define PIO_PER_P4 (0x1u << 4)
118#define PIO_PER_P5 (0x1u << 5)
119#define PIO_PER_P6 (0x1u << 6)
120#define PIO_PER_P7 (0x1u << 7)
121#define PIO_PER_P8 (0x1u << 8)
122#define PIO_PER_P9 (0x1u << 9)
123#define PIO_PER_P10 (0x1u << 10)
124#define PIO_PER_P11 (0x1u << 11)
125#define PIO_PER_P12 (0x1u << 12)
126#define PIO_PER_P13 (0x1u << 13)
127#define PIO_PER_P14 (0x1u << 14)
128#define PIO_PER_P15 (0x1u << 15)
129#define PIO_PER_P16 (0x1u << 16)
130#define PIO_PER_P17 (0x1u << 17)
131#define PIO_PER_P18 (0x1u << 18)
132#define PIO_PER_P19 (0x1u << 19)
133#define PIO_PER_P20 (0x1u << 20)
134#define PIO_PER_P21 (0x1u << 21)
135#define PIO_PER_P22 (0x1u << 22)
136#define PIO_PER_P23 (0x1u << 23)
137#define PIO_PER_P24 (0x1u << 24)
138#define PIO_PER_P25 (0x1u << 25)
139#define PIO_PER_P26 (0x1u << 26)
140#define PIO_PER_P27 (0x1u << 27)
141#define PIO_PER_P28 (0x1u << 28)
142#define PIO_PER_P29 (0x1u << 29)
143#define PIO_PER_P30 (0x1u << 30)
144#define PIO_PER_P31 (0x1u << 31)
145/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
146#define PIO_PDR_P0 (0x1u << 0)
147#define PIO_PDR_P1 (0x1u << 1)
148#define PIO_PDR_P2 (0x1u << 2)
149#define PIO_PDR_P3 (0x1u << 3)
150#define PIO_PDR_P4 (0x1u << 4)
151#define PIO_PDR_P5 (0x1u << 5)
152#define PIO_PDR_P6 (0x1u << 6)
153#define PIO_PDR_P7 (0x1u << 7)
154#define PIO_PDR_P8 (0x1u << 8)
155#define PIO_PDR_P9 (0x1u << 9)
156#define PIO_PDR_P10 (0x1u << 10)
157#define PIO_PDR_P11 (0x1u << 11)
158#define PIO_PDR_P12 (0x1u << 12)
159#define PIO_PDR_P13 (0x1u << 13)
160#define PIO_PDR_P14 (0x1u << 14)
161#define PIO_PDR_P15 (0x1u << 15)
162#define PIO_PDR_P16 (0x1u << 16)
163#define PIO_PDR_P17 (0x1u << 17)
164#define PIO_PDR_P18 (0x1u << 18)
165#define PIO_PDR_P19 (0x1u << 19)
166#define PIO_PDR_P20 (0x1u << 20)
167#define PIO_PDR_P21 (0x1u << 21)
168#define PIO_PDR_P22 (0x1u << 22)
169#define PIO_PDR_P23 (0x1u << 23)
170#define PIO_PDR_P24 (0x1u << 24)
171#define PIO_PDR_P25 (0x1u << 25)
172#define PIO_PDR_P26 (0x1u << 26)
173#define PIO_PDR_P27 (0x1u << 27)
174#define PIO_PDR_P28 (0x1u << 28)
175#define PIO_PDR_P29 (0x1u << 29)
176#define PIO_PDR_P30 (0x1u << 30)
177#define PIO_PDR_P31 (0x1u << 31)
178/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
179#define PIO_PSR_P0 (0x1u << 0)
180#define PIO_PSR_P1 (0x1u << 1)
181#define PIO_PSR_P2 (0x1u << 2)
182#define PIO_PSR_P3 (0x1u << 3)
183#define PIO_PSR_P4 (0x1u << 4)
184#define PIO_PSR_P5 (0x1u << 5)
185#define PIO_PSR_P6 (0x1u << 6)
186#define PIO_PSR_P7 (0x1u << 7)
187#define PIO_PSR_P8 (0x1u << 8)
188#define PIO_PSR_P9 (0x1u << 9)
189#define PIO_PSR_P10 (0x1u << 10)
190#define PIO_PSR_P11 (0x1u << 11)
191#define PIO_PSR_P12 (0x1u << 12)
192#define PIO_PSR_P13 (0x1u << 13)
193#define PIO_PSR_P14 (0x1u << 14)
194#define PIO_PSR_P15 (0x1u << 15)
195#define PIO_PSR_P16 (0x1u << 16)
196#define PIO_PSR_P17 (0x1u << 17)
197#define PIO_PSR_P18 (0x1u << 18)
198#define PIO_PSR_P19 (0x1u << 19)
199#define PIO_PSR_P20 (0x1u << 20)
200#define PIO_PSR_P21 (0x1u << 21)
201#define PIO_PSR_P22 (0x1u << 22)
202#define PIO_PSR_P23 (0x1u << 23)
203#define PIO_PSR_P24 (0x1u << 24)
204#define PIO_PSR_P25 (0x1u << 25)
205#define PIO_PSR_P26 (0x1u << 26)
206#define PIO_PSR_P27 (0x1u << 27)
207#define PIO_PSR_P28 (0x1u << 28)
208#define PIO_PSR_P29 (0x1u << 29)
209#define PIO_PSR_P30 (0x1u << 30)
210#define PIO_PSR_P31 (0x1u << 31)
211/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
212#define PIO_OER_P0 (0x1u << 0)
213#define PIO_OER_P1 (0x1u << 1)
214#define PIO_OER_P2 (0x1u << 2)
215#define PIO_OER_P3 (0x1u << 3)
216#define PIO_OER_P4 (0x1u << 4)
217#define PIO_OER_P5 (0x1u << 5)
218#define PIO_OER_P6 (0x1u << 6)
219#define PIO_OER_P7 (0x1u << 7)
220#define PIO_OER_P8 (0x1u << 8)
221#define PIO_OER_P9 (0x1u << 9)
222#define PIO_OER_P10 (0x1u << 10)
223#define PIO_OER_P11 (0x1u << 11)
224#define PIO_OER_P12 (0x1u << 12)
225#define PIO_OER_P13 (0x1u << 13)
226#define PIO_OER_P14 (0x1u << 14)
227#define PIO_OER_P15 (0x1u << 15)
228#define PIO_OER_P16 (0x1u << 16)
229#define PIO_OER_P17 (0x1u << 17)
230#define PIO_OER_P18 (0x1u << 18)
231#define PIO_OER_P19 (0x1u << 19)
232#define PIO_OER_P20 (0x1u << 20)
233#define PIO_OER_P21 (0x1u << 21)
234#define PIO_OER_P22 (0x1u << 22)
235#define PIO_OER_P23 (0x1u << 23)
236#define PIO_OER_P24 (0x1u << 24)
237#define PIO_OER_P25 (0x1u << 25)
238#define PIO_OER_P26 (0x1u << 26)
239#define PIO_OER_P27 (0x1u << 27)
240#define PIO_OER_P28 (0x1u << 28)
241#define PIO_OER_P29 (0x1u << 29)
242#define PIO_OER_P30 (0x1u << 30)
243#define PIO_OER_P31 (0x1u << 31)
244/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
245#define PIO_ODR_P0 (0x1u << 0)
246#define PIO_ODR_P1 (0x1u << 1)
247#define PIO_ODR_P2 (0x1u << 2)
248#define PIO_ODR_P3 (0x1u << 3)
249#define PIO_ODR_P4 (0x1u << 4)
250#define PIO_ODR_P5 (0x1u << 5)
251#define PIO_ODR_P6 (0x1u << 6)
252#define PIO_ODR_P7 (0x1u << 7)
253#define PIO_ODR_P8 (0x1u << 8)
254#define PIO_ODR_P9 (0x1u << 9)
255#define PIO_ODR_P10 (0x1u << 10)
256#define PIO_ODR_P11 (0x1u << 11)
257#define PIO_ODR_P12 (0x1u << 12)
258#define PIO_ODR_P13 (0x1u << 13)
259#define PIO_ODR_P14 (0x1u << 14)
260#define PIO_ODR_P15 (0x1u << 15)
261#define PIO_ODR_P16 (0x1u << 16)
262#define PIO_ODR_P17 (0x1u << 17)
263#define PIO_ODR_P18 (0x1u << 18)
264#define PIO_ODR_P19 (0x1u << 19)
265#define PIO_ODR_P20 (0x1u << 20)
266#define PIO_ODR_P21 (0x1u << 21)
267#define PIO_ODR_P22 (0x1u << 22)
268#define PIO_ODR_P23 (0x1u << 23)
269#define PIO_ODR_P24 (0x1u << 24)
270#define PIO_ODR_P25 (0x1u << 25)
271#define PIO_ODR_P26 (0x1u << 26)
272#define PIO_ODR_P27 (0x1u << 27)
273#define PIO_ODR_P28 (0x1u << 28)
274#define PIO_ODR_P29 (0x1u << 29)
275#define PIO_ODR_P30 (0x1u << 30)
276#define PIO_ODR_P31 (0x1u << 31)
277/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
278#define PIO_OSR_P0 (0x1u << 0)
279#define PIO_OSR_P1 (0x1u << 1)
280#define PIO_OSR_P2 (0x1u << 2)
281#define PIO_OSR_P3 (0x1u << 3)
282#define PIO_OSR_P4 (0x1u << 4)
283#define PIO_OSR_P5 (0x1u << 5)
284#define PIO_OSR_P6 (0x1u << 6)
285#define PIO_OSR_P7 (0x1u << 7)
286#define PIO_OSR_P8 (0x1u << 8)
287#define PIO_OSR_P9 (0x1u << 9)
288#define PIO_OSR_P10 (0x1u << 10)
289#define PIO_OSR_P11 (0x1u << 11)
290#define PIO_OSR_P12 (0x1u << 12)
291#define PIO_OSR_P13 (0x1u << 13)
292#define PIO_OSR_P14 (0x1u << 14)
293#define PIO_OSR_P15 (0x1u << 15)
294#define PIO_OSR_P16 (0x1u << 16)
295#define PIO_OSR_P17 (0x1u << 17)
296#define PIO_OSR_P18 (0x1u << 18)
297#define PIO_OSR_P19 (0x1u << 19)
298#define PIO_OSR_P20 (0x1u << 20)
299#define PIO_OSR_P21 (0x1u << 21)
300#define PIO_OSR_P22 (0x1u << 22)
301#define PIO_OSR_P23 (0x1u << 23)
302#define PIO_OSR_P24 (0x1u << 24)
303#define PIO_OSR_P25 (0x1u << 25)
304#define PIO_OSR_P26 (0x1u << 26)
305#define PIO_OSR_P27 (0x1u << 27)
306#define PIO_OSR_P28 (0x1u << 28)
307#define PIO_OSR_P29 (0x1u << 29)
308#define PIO_OSR_P30 (0x1u << 30)
309#define PIO_OSR_P31 (0x1u << 31)
310/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
311#define PIO_IFER_P0 (0x1u << 0)
312#define PIO_IFER_P1 (0x1u << 1)
313#define PIO_IFER_P2 (0x1u << 2)
314#define PIO_IFER_P3 (0x1u << 3)
315#define PIO_IFER_P4 (0x1u << 4)
316#define PIO_IFER_P5 (0x1u << 5)
317#define PIO_IFER_P6 (0x1u << 6)
318#define PIO_IFER_P7 (0x1u << 7)
319#define PIO_IFER_P8 (0x1u << 8)
320#define PIO_IFER_P9 (0x1u << 9)
321#define PIO_IFER_P10 (0x1u << 10)
322#define PIO_IFER_P11 (0x1u << 11)
323#define PIO_IFER_P12 (0x1u << 12)
324#define PIO_IFER_P13 (0x1u << 13)
325#define PIO_IFER_P14 (0x1u << 14)
326#define PIO_IFER_P15 (0x1u << 15)
327#define PIO_IFER_P16 (0x1u << 16)
328#define PIO_IFER_P17 (0x1u << 17)
329#define PIO_IFER_P18 (0x1u << 18)
330#define PIO_IFER_P19 (0x1u << 19)
331#define PIO_IFER_P20 (0x1u << 20)
332#define PIO_IFER_P21 (0x1u << 21)
333#define PIO_IFER_P22 (0x1u << 22)
334#define PIO_IFER_P23 (0x1u << 23)
335#define PIO_IFER_P24 (0x1u << 24)
336#define PIO_IFER_P25 (0x1u << 25)
337#define PIO_IFER_P26 (0x1u << 26)
338#define PIO_IFER_P27 (0x1u << 27)
339#define PIO_IFER_P28 (0x1u << 28)
340#define PIO_IFER_P29 (0x1u << 29)
341#define PIO_IFER_P30 (0x1u << 30)
342#define PIO_IFER_P31 (0x1u << 31)
343/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
344#define PIO_IFDR_P0 (0x1u << 0)
345#define PIO_IFDR_P1 (0x1u << 1)
346#define PIO_IFDR_P2 (0x1u << 2)
347#define PIO_IFDR_P3 (0x1u << 3)
348#define PIO_IFDR_P4 (0x1u << 4)
349#define PIO_IFDR_P5 (0x1u << 5)
350#define PIO_IFDR_P6 (0x1u << 6)
351#define PIO_IFDR_P7 (0x1u << 7)
352#define PIO_IFDR_P8 (0x1u << 8)
353#define PIO_IFDR_P9 (0x1u << 9)
354#define PIO_IFDR_P10 (0x1u << 10)
355#define PIO_IFDR_P11 (0x1u << 11)
356#define PIO_IFDR_P12 (0x1u << 12)
357#define PIO_IFDR_P13 (0x1u << 13)
358#define PIO_IFDR_P14 (0x1u << 14)
359#define PIO_IFDR_P15 (0x1u << 15)
360#define PIO_IFDR_P16 (0x1u << 16)
361#define PIO_IFDR_P17 (0x1u << 17)
362#define PIO_IFDR_P18 (0x1u << 18)
363#define PIO_IFDR_P19 (0x1u << 19)
364#define PIO_IFDR_P20 (0x1u << 20)
365#define PIO_IFDR_P21 (0x1u << 21)
366#define PIO_IFDR_P22 (0x1u << 22)
367#define PIO_IFDR_P23 (0x1u << 23)
368#define PIO_IFDR_P24 (0x1u << 24)
369#define PIO_IFDR_P25 (0x1u << 25)
370#define PIO_IFDR_P26 (0x1u << 26)
371#define PIO_IFDR_P27 (0x1u << 27)
372#define PIO_IFDR_P28 (0x1u << 28)
373#define PIO_IFDR_P29 (0x1u << 29)
374#define PIO_IFDR_P30 (0x1u << 30)
375#define PIO_IFDR_P31 (0x1u << 31)
376/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
377#define PIO_IFSR_P0 (0x1u << 0)
378#define PIO_IFSR_P1 (0x1u << 1)
379#define PIO_IFSR_P2 (0x1u << 2)
380#define PIO_IFSR_P3 (0x1u << 3)
381#define PIO_IFSR_P4 (0x1u << 4)
382#define PIO_IFSR_P5 (0x1u << 5)
383#define PIO_IFSR_P6 (0x1u << 6)
384#define PIO_IFSR_P7 (0x1u << 7)
385#define PIO_IFSR_P8 (0x1u << 8)
386#define PIO_IFSR_P9 (0x1u << 9)
387#define PIO_IFSR_P10 (0x1u << 10)
388#define PIO_IFSR_P11 (0x1u << 11)
389#define PIO_IFSR_P12 (0x1u << 12)
390#define PIO_IFSR_P13 (0x1u << 13)
391#define PIO_IFSR_P14 (0x1u << 14)
392#define PIO_IFSR_P15 (0x1u << 15)
393#define PIO_IFSR_P16 (0x1u << 16)
394#define PIO_IFSR_P17 (0x1u << 17)
395#define PIO_IFSR_P18 (0x1u << 18)
396#define PIO_IFSR_P19 (0x1u << 19)
397#define PIO_IFSR_P20 (0x1u << 20)
398#define PIO_IFSR_P21 (0x1u << 21)
399#define PIO_IFSR_P22 (0x1u << 22)
400#define PIO_IFSR_P23 (0x1u << 23)
401#define PIO_IFSR_P24 (0x1u << 24)
402#define PIO_IFSR_P25 (0x1u << 25)
403#define PIO_IFSR_P26 (0x1u << 26)
404#define PIO_IFSR_P27 (0x1u << 27)
405#define PIO_IFSR_P28 (0x1u << 28)
406#define PIO_IFSR_P29 (0x1u << 29)
407#define PIO_IFSR_P30 (0x1u << 30)
408#define PIO_IFSR_P31 (0x1u << 31)
409/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
410#define PIO_SODR_P0 (0x1u << 0)
411#define PIO_SODR_P1 (0x1u << 1)
412#define PIO_SODR_P2 (0x1u << 2)
413#define PIO_SODR_P3 (0x1u << 3)
414#define PIO_SODR_P4 (0x1u << 4)
415#define PIO_SODR_P5 (0x1u << 5)
416#define PIO_SODR_P6 (0x1u << 6)
417#define PIO_SODR_P7 (0x1u << 7)
418#define PIO_SODR_P8 (0x1u << 8)
419#define PIO_SODR_P9 (0x1u << 9)
420#define PIO_SODR_P10 (0x1u << 10)
421#define PIO_SODR_P11 (0x1u << 11)
422#define PIO_SODR_P12 (0x1u << 12)
423#define PIO_SODR_P13 (0x1u << 13)
424#define PIO_SODR_P14 (0x1u << 14)
425#define PIO_SODR_P15 (0x1u << 15)
426#define PIO_SODR_P16 (0x1u << 16)
427#define PIO_SODR_P17 (0x1u << 17)
428#define PIO_SODR_P18 (0x1u << 18)
429#define PIO_SODR_P19 (0x1u << 19)
430#define PIO_SODR_P20 (0x1u << 20)
431#define PIO_SODR_P21 (0x1u << 21)
432#define PIO_SODR_P22 (0x1u << 22)
433#define PIO_SODR_P23 (0x1u << 23)
434#define PIO_SODR_P24 (0x1u << 24)
435#define PIO_SODR_P25 (0x1u << 25)
436#define PIO_SODR_P26 (0x1u << 26)
437#define PIO_SODR_P27 (0x1u << 27)
438#define PIO_SODR_P28 (0x1u << 28)
439#define PIO_SODR_P29 (0x1u << 29)
440#define PIO_SODR_P30 (0x1u << 30)
441#define PIO_SODR_P31 (0x1u << 31)
442/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
443#define PIO_CODR_P0 (0x1u << 0)
444#define PIO_CODR_P1 (0x1u << 1)
445#define PIO_CODR_P2 (0x1u << 2)
446#define PIO_CODR_P3 (0x1u << 3)
447#define PIO_CODR_P4 (0x1u << 4)
448#define PIO_CODR_P5 (0x1u << 5)
449#define PIO_CODR_P6 (0x1u << 6)
450#define PIO_CODR_P7 (0x1u << 7)
451#define PIO_CODR_P8 (0x1u << 8)
452#define PIO_CODR_P9 (0x1u << 9)
453#define PIO_CODR_P10 (0x1u << 10)
454#define PIO_CODR_P11 (0x1u << 11)
455#define PIO_CODR_P12 (0x1u << 12)
456#define PIO_CODR_P13 (0x1u << 13)
457#define PIO_CODR_P14 (0x1u << 14)
458#define PIO_CODR_P15 (0x1u << 15)
459#define PIO_CODR_P16 (0x1u << 16)
460#define PIO_CODR_P17 (0x1u << 17)
461#define PIO_CODR_P18 (0x1u << 18)
462#define PIO_CODR_P19 (0x1u << 19)
463#define PIO_CODR_P20 (0x1u << 20)
464#define PIO_CODR_P21 (0x1u << 21)
465#define PIO_CODR_P22 (0x1u << 22)
466#define PIO_CODR_P23 (0x1u << 23)
467#define PIO_CODR_P24 (0x1u << 24)
468#define PIO_CODR_P25 (0x1u << 25)
469#define PIO_CODR_P26 (0x1u << 26)
470#define PIO_CODR_P27 (0x1u << 27)
471#define PIO_CODR_P28 (0x1u << 28)
472#define PIO_CODR_P29 (0x1u << 29)
473#define PIO_CODR_P30 (0x1u << 30)
474#define PIO_CODR_P31 (0x1u << 31)
475/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
476#define PIO_ODSR_P0 (0x1u << 0)
477#define PIO_ODSR_P1 (0x1u << 1)
478#define PIO_ODSR_P2 (0x1u << 2)
479#define PIO_ODSR_P3 (0x1u << 3)
480#define PIO_ODSR_P4 (0x1u << 4)
481#define PIO_ODSR_P5 (0x1u << 5)
482#define PIO_ODSR_P6 (0x1u << 6)
483#define PIO_ODSR_P7 (0x1u << 7)
484#define PIO_ODSR_P8 (0x1u << 8)
485#define PIO_ODSR_P9 (0x1u << 9)
486#define PIO_ODSR_P10 (0x1u << 10)
487#define PIO_ODSR_P11 (0x1u << 11)
488#define PIO_ODSR_P12 (0x1u << 12)
489#define PIO_ODSR_P13 (0x1u << 13)
490#define PIO_ODSR_P14 (0x1u << 14)
491#define PIO_ODSR_P15 (0x1u << 15)
492#define PIO_ODSR_P16 (0x1u << 16)
493#define PIO_ODSR_P17 (0x1u << 17)
494#define PIO_ODSR_P18 (0x1u << 18)
495#define PIO_ODSR_P19 (0x1u << 19)
496#define PIO_ODSR_P20 (0x1u << 20)
497#define PIO_ODSR_P21 (0x1u << 21)
498#define PIO_ODSR_P22 (0x1u << 22)
499#define PIO_ODSR_P23 (0x1u << 23)
500#define PIO_ODSR_P24 (0x1u << 24)
501#define PIO_ODSR_P25 (0x1u << 25)
502#define PIO_ODSR_P26 (0x1u << 26)
503#define PIO_ODSR_P27 (0x1u << 27)
504#define PIO_ODSR_P28 (0x1u << 28)
505#define PIO_ODSR_P29 (0x1u << 29)
506#define PIO_ODSR_P30 (0x1u << 30)
507#define PIO_ODSR_P31 (0x1u << 31)
508/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
509#define PIO_PDSR_P0 (0x1u << 0)
510#define PIO_PDSR_P1 (0x1u << 1)
511#define PIO_PDSR_P2 (0x1u << 2)
512#define PIO_PDSR_P3 (0x1u << 3)
513#define PIO_PDSR_P4 (0x1u << 4)
514#define PIO_PDSR_P5 (0x1u << 5)
515#define PIO_PDSR_P6 (0x1u << 6)
516#define PIO_PDSR_P7 (0x1u << 7)
517#define PIO_PDSR_P8 (0x1u << 8)
518#define PIO_PDSR_P9 (0x1u << 9)
519#define PIO_PDSR_P10 (0x1u << 10)
520#define PIO_PDSR_P11 (0x1u << 11)
521#define PIO_PDSR_P12 (0x1u << 12)
522#define PIO_PDSR_P13 (0x1u << 13)
523#define PIO_PDSR_P14 (0x1u << 14)
524#define PIO_PDSR_P15 (0x1u << 15)
525#define PIO_PDSR_P16 (0x1u << 16)
526#define PIO_PDSR_P17 (0x1u << 17)
527#define PIO_PDSR_P18 (0x1u << 18)
528#define PIO_PDSR_P19 (0x1u << 19)
529#define PIO_PDSR_P20 (0x1u << 20)
530#define PIO_PDSR_P21 (0x1u << 21)
531#define PIO_PDSR_P22 (0x1u << 22)
532#define PIO_PDSR_P23 (0x1u << 23)
533#define PIO_PDSR_P24 (0x1u << 24)
534#define PIO_PDSR_P25 (0x1u << 25)
535#define PIO_PDSR_P26 (0x1u << 26)
536#define PIO_PDSR_P27 (0x1u << 27)
537#define PIO_PDSR_P28 (0x1u << 28)
538#define PIO_PDSR_P29 (0x1u << 29)
539#define PIO_PDSR_P30 (0x1u << 30)
540#define PIO_PDSR_P31 (0x1u << 31)
541/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
542#define PIO_IER_P0 (0x1u << 0)
543#define PIO_IER_P1 (0x1u << 1)
544#define PIO_IER_P2 (0x1u << 2)
545#define PIO_IER_P3 (0x1u << 3)
546#define PIO_IER_P4 (0x1u << 4)
547#define PIO_IER_P5 (0x1u << 5)
548#define PIO_IER_P6 (0x1u << 6)
549#define PIO_IER_P7 (0x1u << 7)
550#define PIO_IER_P8 (0x1u << 8)
551#define PIO_IER_P9 (0x1u << 9)
552#define PIO_IER_P10 (0x1u << 10)
553#define PIO_IER_P11 (0x1u << 11)
554#define PIO_IER_P12 (0x1u << 12)
555#define PIO_IER_P13 (0x1u << 13)
556#define PIO_IER_P14 (0x1u << 14)
557#define PIO_IER_P15 (0x1u << 15)
558#define PIO_IER_P16 (0x1u << 16)
559#define PIO_IER_P17 (0x1u << 17)
560#define PIO_IER_P18 (0x1u << 18)
561#define PIO_IER_P19 (0x1u << 19)
562#define PIO_IER_P20 (0x1u << 20)
563#define PIO_IER_P21 (0x1u << 21)
564#define PIO_IER_P22 (0x1u << 22)
565#define PIO_IER_P23 (0x1u << 23)
566#define PIO_IER_P24 (0x1u << 24)
567#define PIO_IER_P25 (0x1u << 25)
568#define PIO_IER_P26 (0x1u << 26)
569#define PIO_IER_P27 (0x1u << 27)
570#define PIO_IER_P28 (0x1u << 28)
571#define PIO_IER_P29 (0x1u << 29)
572#define PIO_IER_P30 (0x1u << 30)
573#define PIO_IER_P31 (0x1u << 31)
574/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
575#define PIO_IDR_P0 (0x1u << 0)
576#define PIO_IDR_P1 (0x1u << 1)
577#define PIO_IDR_P2 (0x1u << 2)
578#define PIO_IDR_P3 (0x1u << 3)
579#define PIO_IDR_P4 (0x1u << 4)
580#define PIO_IDR_P5 (0x1u << 5)
581#define PIO_IDR_P6 (0x1u << 6)
582#define PIO_IDR_P7 (0x1u << 7)
583#define PIO_IDR_P8 (0x1u << 8)
584#define PIO_IDR_P9 (0x1u << 9)
585#define PIO_IDR_P10 (0x1u << 10)
586#define PIO_IDR_P11 (0x1u << 11)
587#define PIO_IDR_P12 (0x1u << 12)
588#define PIO_IDR_P13 (0x1u << 13)
589#define PIO_IDR_P14 (0x1u << 14)
590#define PIO_IDR_P15 (0x1u << 15)
591#define PIO_IDR_P16 (0x1u << 16)
592#define PIO_IDR_P17 (0x1u << 17)
593#define PIO_IDR_P18 (0x1u << 18)
594#define PIO_IDR_P19 (0x1u << 19)
595#define PIO_IDR_P20 (0x1u << 20)
596#define PIO_IDR_P21 (0x1u << 21)
597#define PIO_IDR_P22 (0x1u << 22)
598#define PIO_IDR_P23 (0x1u << 23)
599#define PIO_IDR_P24 (0x1u << 24)
600#define PIO_IDR_P25 (0x1u << 25)
601#define PIO_IDR_P26 (0x1u << 26)
602#define PIO_IDR_P27 (0x1u << 27)
603#define PIO_IDR_P28 (0x1u << 28)
604#define PIO_IDR_P29 (0x1u << 29)
605#define PIO_IDR_P30 (0x1u << 30)
606#define PIO_IDR_P31 (0x1u << 31)
607/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
608#define PIO_IMR_P0 (0x1u << 0)
609#define PIO_IMR_P1 (0x1u << 1)
610#define PIO_IMR_P2 (0x1u << 2)
611#define PIO_IMR_P3 (0x1u << 3)
612#define PIO_IMR_P4 (0x1u << 4)
613#define PIO_IMR_P5 (0x1u << 5)
614#define PIO_IMR_P6 (0x1u << 6)
615#define PIO_IMR_P7 (0x1u << 7)
616#define PIO_IMR_P8 (0x1u << 8)
617#define PIO_IMR_P9 (0x1u << 9)
618#define PIO_IMR_P10 (0x1u << 10)
619#define PIO_IMR_P11 (0x1u << 11)
620#define PIO_IMR_P12 (0x1u << 12)
621#define PIO_IMR_P13 (0x1u << 13)
622#define PIO_IMR_P14 (0x1u << 14)
623#define PIO_IMR_P15 (0x1u << 15)
624#define PIO_IMR_P16 (0x1u << 16)
625#define PIO_IMR_P17 (0x1u << 17)
626#define PIO_IMR_P18 (0x1u << 18)
627#define PIO_IMR_P19 (0x1u << 19)
628#define PIO_IMR_P20 (0x1u << 20)
629#define PIO_IMR_P21 (0x1u << 21)
630#define PIO_IMR_P22 (0x1u << 22)
631#define PIO_IMR_P23 (0x1u << 23)
632#define PIO_IMR_P24 (0x1u << 24)
633#define PIO_IMR_P25 (0x1u << 25)
634#define PIO_IMR_P26 (0x1u << 26)
635#define PIO_IMR_P27 (0x1u << 27)
636#define PIO_IMR_P28 (0x1u << 28)
637#define PIO_IMR_P29 (0x1u << 29)
638#define PIO_IMR_P30 (0x1u << 30)
639#define PIO_IMR_P31 (0x1u << 31)
640/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
641#define PIO_ISR_P0 (0x1u << 0)
642#define PIO_ISR_P1 (0x1u << 1)
643#define PIO_ISR_P2 (0x1u << 2)
644#define PIO_ISR_P3 (0x1u << 3)
645#define PIO_ISR_P4 (0x1u << 4)
646#define PIO_ISR_P5 (0x1u << 5)
647#define PIO_ISR_P6 (0x1u << 6)
648#define PIO_ISR_P7 (0x1u << 7)
649#define PIO_ISR_P8 (0x1u << 8)
650#define PIO_ISR_P9 (0x1u << 9)
651#define PIO_ISR_P10 (0x1u << 10)
652#define PIO_ISR_P11 (0x1u << 11)
653#define PIO_ISR_P12 (0x1u << 12)
654#define PIO_ISR_P13 (0x1u << 13)
655#define PIO_ISR_P14 (0x1u << 14)
656#define PIO_ISR_P15 (0x1u << 15)
657#define PIO_ISR_P16 (0x1u << 16)
658#define PIO_ISR_P17 (0x1u << 17)
659#define PIO_ISR_P18 (0x1u << 18)
660#define PIO_ISR_P19 (0x1u << 19)
661#define PIO_ISR_P20 (0x1u << 20)
662#define PIO_ISR_P21 (0x1u << 21)
663#define PIO_ISR_P22 (0x1u << 22)
664#define PIO_ISR_P23 (0x1u << 23)
665#define PIO_ISR_P24 (0x1u << 24)
666#define PIO_ISR_P25 (0x1u << 25)
667#define PIO_ISR_P26 (0x1u << 26)
668#define PIO_ISR_P27 (0x1u << 27)
669#define PIO_ISR_P28 (0x1u << 28)
670#define PIO_ISR_P29 (0x1u << 29)
671#define PIO_ISR_P30 (0x1u << 30)
672#define PIO_ISR_P31 (0x1u << 31)
673/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
674#define PIO_MDER_P0 (0x1u << 0)
675#define PIO_MDER_P1 (0x1u << 1)
676#define PIO_MDER_P2 (0x1u << 2)
677#define PIO_MDER_P3 (0x1u << 3)
678#define PIO_MDER_P4 (0x1u << 4)
679#define PIO_MDER_P5 (0x1u << 5)
680#define PIO_MDER_P6 (0x1u << 6)
681#define PIO_MDER_P7 (0x1u << 7)
682#define PIO_MDER_P8 (0x1u << 8)
683#define PIO_MDER_P9 (0x1u << 9)
684#define PIO_MDER_P10 (0x1u << 10)
685#define PIO_MDER_P11 (0x1u << 11)
686#define PIO_MDER_P12 (0x1u << 12)
687#define PIO_MDER_P13 (0x1u << 13)
688#define PIO_MDER_P14 (0x1u << 14)
689#define PIO_MDER_P15 (0x1u << 15)
690#define PIO_MDER_P16 (0x1u << 16)
691#define PIO_MDER_P17 (0x1u << 17)
692#define PIO_MDER_P18 (0x1u << 18)
693#define PIO_MDER_P19 (0x1u << 19)
694#define PIO_MDER_P20 (0x1u << 20)
695#define PIO_MDER_P21 (0x1u << 21)
696#define PIO_MDER_P22 (0x1u << 22)
697#define PIO_MDER_P23 (0x1u << 23)
698#define PIO_MDER_P24 (0x1u << 24)
699#define PIO_MDER_P25 (0x1u << 25)
700#define PIO_MDER_P26 (0x1u << 26)
701#define PIO_MDER_P27 (0x1u << 27)
702#define PIO_MDER_P28 (0x1u << 28)
703#define PIO_MDER_P29 (0x1u << 29)
704#define PIO_MDER_P30 (0x1u << 30)
705#define PIO_MDER_P31 (0x1u << 31)
706/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
707#define PIO_MDDR_P0 (0x1u << 0)
708#define PIO_MDDR_P1 (0x1u << 1)
709#define PIO_MDDR_P2 (0x1u << 2)
710#define PIO_MDDR_P3 (0x1u << 3)
711#define PIO_MDDR_P4 (0x1u << 4)
712#define PIO_MDDR_P5 (0x1u << 5)
713#define PIO_MDDR_P6 (0x1u << 6)
714#define PIO_MDDR_P7 (0x1u << 7)
715#define PIO_MDDR_P8 (0x1u << 8)
716#define PIO_MDDR_P9 (0x1u << 9)
717#define PIO_MDDR_P10 (0x1u << 10)
718#define PIO_MDDR_P11 (0x1u << 11)
719#define PIO_MDDR_P12 (0x1u << 12)
720#define PIO_MDDR_P13 (0x1u << 13)
721#define PIO_MDDR_P14 (0x1u << 14)
722#define PIO_MDDR_P15 (0x1u << 15)
723#define PIO_MDDR_P16 (0x1u << 16)
724#define PIO_MDDR_P17 (0x1u << 17)
725#define PIO_MDDR_P18 (0x1u << 18)
726#define PIO_MDDR_P19 (0x1u << 19)
727#define PIO_MDDR_P20 (0x1u << 20)
728#define PIO_MDDR_P21 (0x1u << 21)
729#define PIO_MDDR_P22 (0x1u << 22)
730#define PIO_MDDR_P23 (0x1u << 23)
731#define PIO_MDDR_P24 (0x1u << 24)
732#define PIO_MDDR_P25 (0x1u << 25)
733#define PIO_MDDR_P26 (0x1u << 26)
734#define PIO_MDDR_P27 (0x1u << 27)
735#define PIO_MDDR_P28 (0x1u << 28)
736#define PIO_MDDR_P29 (0x1u << 29)
737#define PIO_MDDR_P30 (0x1u << 30)
738#define PIO_MDDR_P31 (0x1u << 31)
739/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
740#define PIO_MDSR_P0 (0x1u << 0)
741#define PIO_MDSR_P1 (0x1u << 1)
742#define PIO_MDSR_P2 (0x1u << 2)
743#define PIO_MDSR_P3 (0x1u << 3)
744#define PIO_MDSR_P4 (0x1u << 4)
745#define PIO_MDSR_P5 (0x1u << 5)
746#define PIO_MDSR_P6 (0x1u << 6)
747#define PIO_MDSR_P7 (0x1u << 7)
748#define PIO_MDSR_P8 (0x1u << 8)
749#define PIO_MDSR_P9 (0x1u << 9)
750#define PIO_MDSR_P10 (0x1u << 10)
751#define PIO_MDSR_P11 (0x1u << 11)
752#define PIO_MDSR_P12 (0x1u << 12)
753#define PIO_MDSR_P13 (0x1u << 13)
754#define PIO_MDSR_P14 (0x1u << 14)
755#define PIO_MDSR_P15 (0x1u << 15)
756#define PIO_MDSR_P16 (0x1u << 16)
757#define PIO_MDSR_P17 (0x1u << 17)
758#define PIO_MDSR_P18 (0x1u << 18)
759#define PIO_MDSR_P19 (0x1u << 19)
760#define PIO_MDSR_P20 (0x1u << 20)
761#define PIO_MDSR_P21 (0x1u << 21)
762#define PIO_MDSR_P22 (0x1u << 22)
763#define PIO_MDSR_P23 (0x1u << 23)
764#define PIO_MDSR_P24 (0x1u << 24)
765#define PIO_MDSR_P25 (0x1u << 25)
766#define PIO_MDSR_P26 (0x1u << 26)
767#define PIO_MDSR_P27 (0x1u << 27)
768#define PIO_MDSR_P28 (0x1u << 28)
769#define PIO_MDSR_P29 (0x1u << 29)
770#define PIO_MDSR_P30 (0x1u << 30)
771#define PIO_MDSR_P31 (0x1u << 31)
772/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
773#define PIO_PUDR_P0 (0x1u << 0)
774#define PIO_PUDR_P1 (0x1u << 1)
775#define PIO_PUDR_P2 (0x1u << 2)
776#define PIO_PUDR_P3 (0x1u << 3)
777#define PIO_PUDR_P4 (0x1u << 4)
778#define PIO_PUDR_P5 (0x1u << 5)
779#define PIO_PUDR_P6 (0x1u << 6)
780#define PIO_PUDR_P7 (0x1u << 7)
781#define PIO_PUDR_P8 (0x1u << 8)
782#define PIO_PUDR_P9 (0x1u << 9)
783#define PIO_PUDR_P10 (0x1u << 10)
784#define PIO_PUDR_P11 (0x1u << 11)
785#define PIO_PUDR_P12 (0x1u << 12)
786#define PIO_PUDR_P13 (0x1u << 13)
787#define PIO_PUDR_P14 (0x1u << 14)
788#define PIO_PUDR_P15 (0x1u << 15)
789#define PIO_PUDR_P16 (0x1u << 16)
790#define PIO_PUDR_P17 (0x1u << 17)
791#define PIO_PUDR_P18 (0x1u << 18)
792#define PIO_PUDR_P19 (0x1u << 19)
793#define PIO_PUDR_P20 (0x1u << 20)
794#define PIO_PUDR_P21 (0x1u << 21)
795#define PIO_PUDR_P22 (0x1u << 22)
796#define PIO_PUDR_P23 (0x1u << 23)
797#define PIO_PUDR_P24 (0x1u << 24)
798#define PIO_PUDR_P25 (0x1u << 25)
799#define PIO_PUDR_P26 (0x1u << 26)
800#define PIO_PUDR_P27 (0x1u << 27)
801#define PIO_PUDR_P28 (0x1u << 28)
802#define PIO_PUDR_P29 (0x1u << 29)
803#define PIO_PUDR_P30 (0x1u << 30)
804#define PIO_PUDR_P31 (0x1u << 31)
805/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
806#define PIO_PUER_P0 (0x1u << 0)
807#define PIO_PUER_P1 (0x1u << 1)
808#define PIO_PUER_P2 (0x1u << 2)
809#define PIO_PUER_P3 (0x1u << 3)
810#define PIO_PUER_P4 (0x1u << 4)
811#define PIO_PUER_P5 (0x1u << 5)
812#define PIO_PUER_P6 (0x1u << 6)
813#define PIO_PUER_P7 (0x1u << 7)
814#define PIO_PUER_P8 (0x1u << 8)
815#define PIO_PUER_P9 (0x1u << 9)
816#define PIO_PUER_P10 (0x1u << 10)
817#define PIO_PUER_P11 (0x1u << 11)
818#define PIO_PUER_P12 (0x1u << 12)
819#define PIO_PUER_P13 (0x1u << 13)
820#define PIO_PUER_P14 (0x1u << 14)
821#define PIO_PUER_P15 (0x1u << 15)
822#define PIO_PUER_P16 (0x1u << 16)
823#define PIO_PUER_P17 (0x1u << 17)
824#define PIO_PUER_P18 (0x1u << 18)
825#define PIO_PUER_P19 (0x1u << 19)
826#define PIO_PUER_P20 (0x1u << 20)
827#define PIO_PUER_P21 (0x1u << 21)
828#define PIO_PUER_P22 (0x1u << 22)
829#define PIO_PUER_P23 (0x1u << 23)
830#define PIO_PUER_P24 (0x1u << 24)
831#define PIO_PUER_P25 (0x1u << 25)
832#define PIO_PUER_P26 (0x1u << 26)
833#define PIO_PUER_P27 (0x1u << 27)
834#define PIO_PUER_P28 (0x1u << 28)
835#define PIO_PUER_P29 (0x1u << 29)
836#define PIO_PUER_P30 (0x1u << 30)
837#define PIO_PUER_P31 (0x1u << 31)
838/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
839#define PIO_PUSR_P0 (0x1u << 0)
840#define PIO_PUSR_P1 (0x1u << 1)
841#define PIO_PUSR_P2 (0x1u << 2)
842#define PIO_PUSR_P3 (0x1u << 3)
843#define PIO_PUSR_P4 (0x1u << 4)
844#define PIO_PUSR_P5 (0x1u << 5)
845#define PIO_PUSR_P6 (0x1u << 6)
846#define PIO_PUSR_P7 (0x1u << 7)
847#define PIO_PUSR_P8 (0x1u << 8)
848#define PIO_PUSR_P9 (0x1u << 9)
849#define PIO_PUSR_P10 (0x1u << 10)
850#define PIO_PUSR_P11 (0x1u << 11)
851#define PIO_PUSR_P12 (0x1u << 12)
852#define PIO_PUSR_P13 (0x1u << 13)
853#define PIO_PUSR_P14 (0x1u << 14)
854#define PIO_PUSR_P15 (0x1u << 15)
855#define PIO_PUSR_P16 (0x1u << 16)
856#define PIO_PUSR_P17 (0x1u << 17)
857#define PIO_PUSR_P18 (0x1u << 18)
858#define PIO_PUSR_P19 (0x1u << 19)
859#define PIO_PUSR_P20 (0x1u << 20)
860#define PIO_PUSR_P21 (0x1u << 21)
861#define PIO_PUSR_P22 (0x1u << 22)
862#define PIO_PUSR_P23 (0x1u << 23)
863#define PIO_PUSR_P24 (0x1u << 24)
864#define PIO_PUSR_P25 (0x1u << 25)
865#define PIO_PUSR_P26 (0x1u << 26)
866#define PIO_PUSR_P27 (0x1u << 27)
867#define PIO_PUSR_P28 (0x1u << 28)
868#define PIO_PUSR_P29 (0x1u << 29)
869#define PIO_PUSR_P30 (0x1u << 30)
870#define PIO_PUSR_P31 (0x1u << 31)
871/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */
872#define PIO_ABCDSR_P0 (0x1u << 0)
873#define PIO_ABCDSR_P1 (0x1u << 1)
874#define PIO_ABCDSR_P2 (0x1u << 2)
875#define PIO_ABCDSR_P3 (0x1u << 3)
876#define PIO_ABCDSR_P4 (0x1u << 4)
877#define PIO_ABCDSR_P5 (0x1u << 5)
878#define PIO_ABCDSR_P6 (0x1u << 6)
879#define PIO_ABCDSR_P7 (0x1u << 7)
880#define PIO_ABCDSR_P8 (0x1u << 8)
881#define PIO_ABCDSR_P9 (0x1u << 9)
882#define PIO_ABCDSR_P10 (0x1u << 10)
883#define PIO_ABCDSR_P11 (0x1u << 11)
884#define PIO_ABCDSR_P12 (0x1u << 12)
885#define PIO_ABCDSR_P13 (0x1u << 13)
886#define PIO_ABCDSR_P14 (0x1u << 14)
887#define PIO_ABCDSR_P15 (0x1u << 15)
888#define PIO_ABCDSR_P16 (0x1u << 16)
889#define PIO_ABCDSR_P17 (0x1u << 17)
890#define PIO_ABCDSR_P18 (0x1u << 18)
891#define PIO_ABCDSR_P19 (0x1u << 19)
892#define PIO_ABCDSR_P20 (0x1u << 20)
893#define PIO_ABCDSR_P21 (0x1u << 21)
894#define PIO_ABCDSR_P22 (0x1u << 22)
895#define PIO_ABCDSR_P23 (0x1u << 23)
896#define PIO_ABCDSR_P24 (0x1u << 24)
897#define PIO_ABCDSR_P25 (0x1u << 25)
898#define PIO_ABCDSR_P26 (0x1u << 26)
899#define PIO_ABCDSR_P27 (0x1u << 27)
900#define PIO_ABCDSR_P28 (0x1u << 28)
901#define PIO_ABCDSR_P29 (0x1u << 29)
902#define PIO_ABCDSR_P30 (0x1u << 30)
903#define PIO_ABCDSR_P31 (0x1u << 31)
904/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */
905#define PIO_IFSCDR_P0 (0x1u << 0)
906#define PIO_IFSCDR_P1 (0x1u << 1)
907#define PIO_IFSCDR_P2 (0x1u << 2)
908#define PIO_IFSCDR_P3 (0x1u << 3)
909#define PIO_IFSCDR_P4 (0x1u << 4)
910#define PIO_IFSCDR_P5 (0x1u << 5)
911#define PIO_IFSCDR_P6 (0x1u << 6)
912#define PIO_IFSCDR_P7 (0x1u << 7)
913#define PIO_IFSCDR_P8 (0x1u << 8)
914#define PIO_IFSCDR_P9 (0x1u << 9)
915#define PIO_IFSCDR_P10 (0x1u << 10)
916#define PIO_IFSCDR_P11 (0x1u << 11)
917#define PIO_IFSCDR_P12 (0x1u << 12)
918#define PIO_IFSCDR_P13 (0x1u << 13)
919#define PIO_IFSCDR_P14 (0x1u << 14)
920#define PIO_IFSCDR_P15 (0x1u << 15)
921#define PIO_IFSCDR_P16 (0x1u << 16)
922#define PIO_IFSCDR_P17 (0x1u << 17)
923#define PIO_IFSCDR_P18 (0x1u << 18)
924#define PIO_IFSCDR_P19 (0x1u << 19)
925#define PIO_IFSCDR_P20 (0x1u << 20)
926#define PIO_IFSCDR_P21 (0x1u << 21)
927#define PIO_IFSCDR_P22 (0x1u << 22)
928#define PIO_IFSCDR_P23 (0x1u << 23)
929#define PIO_IFSCDR_P24 (0x1u << 24)
930#define PIO_IFSCDR_P25 (0x1u << 25)
931#define PIO_IFSCDR_P26 (0x1u << 26)
932#define PIO_IFSCDR_P27 (0x1u << 27)
933#define PIO_IFSCDR_P28 (0x1u << 28)
934#define PIO_IFSCDR_P29 (0x1u << 29)
935#define PIO_IFSCDR_P30 (0x1u << 30)
936#define PIO_IFSCDR_P31 (0x1u << 31)
937/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */
938#define PIO_IFSCER_P0 (0x1u << 0)
939#define PIO_IFSCER_P1 (0x1u << 1)
940#define PIO_IFSCER_P2 (0x1u << 2)
941#define PIO_IFSCER_P3 (0x1u << 3)
942#define PIO_IFSCER_P4 (0x1u << 4)
943#define PIO_IFSCER_P5 (0x1u << 5)
944#define PIO_IFSCER_P6 (0x1u << 6)
945#define PIO_IFSCER_P7 (0x1u << 7)
946#define PIO_IFSCER_P8 (0x1u << 8)
947#define PIO_IFSCER_P9 (0x1u << 9)
948#define PIO_IFSCER_P10 (0x1u << 10)
949#define PIO_IFSCER_P11 (0x1u << 11)
950#define PIO_IFSCER_P12 (0x1u << 12)
951#define PIO_IFSCER_P13 (0x1u << 13)
952#define PIO_IFSCER_P14 (0x1u << 14)
953#define PIO_IFSCER_P15 (0x1u << 15)
954#define PIO_IFSCER_P16 (0x1u << 16)
955#define PIO_IFSCER_P17 (0x1u << 17)
956#define PIO_IFSCER_P18 (0x1u << 18)
957#define PIO_IFSCER_P19 (0x1u << 19)
958#define PIO_IFSCER_P20 (0x1u << 20)
959#define PIO_IFSCER_P21 (0x1u << 21)
960#define PIO_IFSCER_P22 (0x1u << 22)
961#define PIO_IFSCER_P23 (0x1u << 23)
962#define PIO_IFSCER_P24 (0x1u << 24)
963#define PIO_IFSCER_P25 (0x1u << 25)
964#define PIO_IFSCER_P26 (0x1u << 26)
965#define PIO_IFSCER_P27 (0x1u << 27)
966#define PIO_IFSCER_P28 (0x1u << 28)
967#define PIO_IFSCER_P29 (0x1u << 29)
968#define PIO_IFSCER_P30 (0x1u << 30)
969#define PIO_IFSCER_P31 (0x1u << 31)
970/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */
971#define PIO_IFSCSR_P0 (0x1u << 0)
972#define PIO_IFSCSR_P1 (0x1u << 1)
973#define PIO_IFSCSR_P2 (0x1u << 2)
974#define PIO_IFSCSR_P3 (0x1u << 3)
975#define PIO_IFSCSR_P4 (0x1u << 4)
976#define PIO_IFSCSR_P5 (0x1u << 5)
977#define PIO_IFSCSR_P6 (0x1u << 6)
978#define PIO_IFSCSR_P7 (0x1u << 7)
979#define PIO_IFSCSR_P8 (0x1u << 8)
980#define PIO_IFSCSR_P9 (0x1u << 9)
981#define PIO_IFSCSR_P10 (0x1u << 10)
982#define PIO_IFSCSR_P11 (0x1u << 11)
983#define PIO_IFSCSR_P12 (0x1u << 12)
984#define PIO_IFSCSR_P13 (0x1u << 13)
985#define PIO_IFSCSR_P14 (0x1u << 14)
986#define PIO_IFSCSR_P15 (0x1u << 15)
987#define PIO_IFSCSR_P16 (0x1u << 16)
988#define PIO_IFSCSR_P17 (0x1u << 17)
989#define PIO_IFSCSR_P18 (0x1u << 18)
990#define PIO_IFSCSR_P19 (0x1u << 19)
991#define PIO_IFSCSR_P20 (0x1u << 20)
992#define PIO_IFSCSR_P21 (0x1u << 21)
993#define PIO_IFSCSR_P22 (0x1u << 22)
994#define PIO_IFSCSR_P23 (0x1u << 23)
995#define PIO_IFSCSR_P24 (0x1u << 24)
996#define PIO_IFSCSR_P25 (0x1u << 25)
997#define PIO_IFSCSR_P26 (0x1u << 26)
998#define PIO_IFSCSR_P27 (0x1u << 27)
999#define PIO_IFSCSR_P28 (0x1u << 28)
1000#define PIO_IFSCSR_P29 (0x1u << 29)
1001#define PIO_IFSCSR_P30 (0x1u << 30)
1002#define PIO_IFSCSR_P31 (0x1u << 31)
1003/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
1004#define PIO_SCDR_DIV_Pos 0
1005#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos)
1006#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
1007/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */
1008#define PIO_PPDDR_P0 (0x1u << 0)
1009#define PIO_PPDDR_P1 (0x1u << 1)
1010#define PIO_PPDDR_P2 (0x1u << 2)
1011#define PIO_PPDDR_P3 (0x1u << 3)
1012#define PIO_PPDDR_P4 (0x1u << 4)
1013#define PIO_PPDDR_P5 (0x1u << 5)
1014#define PIO_PPDDR_P6 (0x1u << 6)
1015#define PIO_PPDDR_P7 (0x1u << 7)
1016#define PIO_PPDDR_P8 (0x1u << 8)
1017#define PIO_PPDDR_P9 (0x1u << 9)
1018#define PIO_PPDDR_P10 (0x1u << 10)
1019#define PIO_PPDDR_P11 (0x1u << 11)
1020#define PIO_PPDDR_P12 (0x1u << 12)
1021#define PIO_PPDDR_P13 (0x1u << 13)
1022#define PIO_PPDDR_P14 (0x1u << 14)
1023#define PIO_PPDDR_P15 (0x1u << 15)
1024#define PIO_PPDDR_P16 (0x1u << 16)
1025#define PIO_PPDDR_P17 (0x1u << 17)
1026#define PIO_PPDDR_P18 (0x1u << 18)
1027#define PIO_PPDDR_P19 (0x1u << 19)
1028#define PIO_PPDDR_P20 (0x1u << 20)
1029#define PIO_PPDDR_P21 (0x1u << 21)
1030#define PIO_PPDDR_P22 (0x1u << 22)
1031#define PIO_PPDDR_P23 (0x1u << 23)
1032#define PIO_PPDDR_P24 (0x1u << 24)
1033#define PIO_PPDDR_P25 (0x1u << 25)
1034#define PIO_PPDDR_P26 (0x1u << 26)
1035#define PIO_PPDDR_P27 (0x1u << 27)
1036#define PIO_PPDDR_P28 (0x1u << 28)
1037#define PIO_PPDDR_P29 (0x1u << 29)
1038#define PIO_PPDDR_P30 (0x1u << 30)
1039#define PIO_PPDDR_P31 (0x1u << 31)
1040/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */
1041#define PIO_PPDER_P0 (0x1u << 0)
1042#define PIO_PPDER_P1 (0x1u << 1)
1043#define PIO_PPDER_P2 (0x1u << 2)
1044#define PIO_PPDER_P3 (0x1u << 3)
1045#define PIO_PPDER_P4 (0x1u << 4)
1046#define PIO_PPDER_P5 (0x1u << 5)
1047#define PIO_PPDER_P6 (0x1u << 6)
1048#define PIO_PPDER_P7 (0x1u << 7)
1049#define PIO_PPDER_P8 (0x1u << 8)
1050#define PIO_PPDER_P9 (0x1u << 9)
1051#define PIO_PPDER_P10 (0x1u << 10)
1052#define PIO_PPDER_P11 (0x1u << 11)
1053#define PIO_PPDER_P12 (0x1u << 12)
1054#define PIO_PPDER_P13 (0x1u << 13)
1055#define PIO_PPDER_P14 (0x1u << 14)
1056#define PIO_PPDER_P15 (0x1u << 15)
1057#define PIO_PPDER_P16 (0x1u << 16)
1058#define PIO_PPDER_P17 (0x1u << 17)
1059#define PIO_PPDER_P18 (0x1u << 18)
1060#define PIO_PPDER_P19 (0x1u << 19)
1061#define PIO_PPDER_P20 (0x1u << 20)
1062#define PIO_PPDER_P21 (0x1u << 21)
1063#define PIO_PPDER_P22 (0x1u << 22)
1064#define PIO_PPDER_P23 (0x1u << 23)
1065#define PIO_PPDER_P24 (0x1u << 24)
1066#define PIO_PPDER_P25 (0x1u << 25)
1067#define PIO_PPDER_P26 (0x1u << 26)
1068#define PIO_PPDER_P27 (0x1u << 27)
1069#define PIO_PPDER_P28 (0x1u << 28)
1070#define PIO_PPDER_P29 (0x1u << 29)
1071#define PIO_PPDER_P30 (0x1u << 30)
1072#define PIO_PPDER_P31 (0x1u << 31)
1073/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */
1074#define PIO_PPDSR_P0 (0x1u << 0)
1075#define PIO_PPDSR_P1 (0x1u << 1)
1076#define PIO_PPDSR_P2 (0x1u << 2)
1077#define PIO_PPDSR_P3 (0x1u << 3)
1078#define PIO_PPDSR_P4 (0x1u << 4)
1079#define PIO_PPDSR_P5 (0x1u << 5)
1080#define PIO_PPDSR_P6 (0x1u << 6)
1081#define PIO_PPDSR_P7 (0x1u << 7)
1082#define PIO_PPDSR_P8 (0x1u << 8)
1083#define PIO_PPDSR_P9 (0x1u << 9)
1084#define PIO_PPDSR_P10 (0x1u << 10)
1085#define PIO_PPDSR_P11 (0x1u << 11)
1086#define PIO_PPDSR_P12 (0x1u << 12)
1087#define PIO_PPDSR_P13 (0x1u << 13)
1088#define PIO_PPDSR_P14 (0x1u << 14)
1089#define PIO_PPDSR_P15 (0x1u << 15)
1090#define PIO_PPDSR_P16 (0x1u << 16)
1091#define PIO_PPDSR_P17 (0x1u << 17)
1092#define PIO_PPDSR_P18 (0x1u << 18)
1093#define PIO_PPDSR_P19 (0x1u << 19)
1094#define PIO_PPDSR_P20 (0x1u << 20)
1095#define PIO_PPDSR_P21 (0x1u << 21)
1096#define PIO_PPDSR_P22 (0x1u << 22)
1097#define PIO_PPDSR_P23 (0x1u << 23)
1098#define PIO_PPDSR_P24 (0x1u << 24)
1099#define PIO_PPDSR_P25 (0x1u << 25)
1100#define PIO_PPDSR_P26 (0x1u << 26)
1101#define PIO_PPDSR_P27 (0x1u << 27)
1102#define PIO_PPDSR_P28 (0x1u << 28)
1103#define PIO_PPDSR_P29 (0x1u << 29)
1104#define PIO_PPDSR_P30 (0x1u << 30)
1105#define PIO_PPDSR_P31 (0x1u << 31)
1106/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
1107#define PIO_OWER_P0 (0x1u << 0)
1108#define PIO_OWER_P1 (0x1u << 1)
1109#define PIO_OWER_P2 (0x1u << 2)
1110#define PIO_OWER_P3 (0x1u << 3)
1111#define PIO_OWER_P4 (0x1u << 4)
1112#define PIO_OWER_P5 (0x1u << 5)
1113#define PIO_OWER_P6 (0x1u << 6)
1114#define PIO_OWER_P7 (0x1u << 7)
1115#define PIO_OWER_P8 (0x1u << 8)
1116#define PIO_OWER_P9 (0x1u << 9)
1117#define PIO_OWER_P10 (0x1u << 10)
1118#define PIO_OWER_P11 (0x1u << 11)
1119#define PIO_OWER_P12 (0x1u << 12)
1120#define PIO_OWER_P13 (0x1u << 13)
1121#define PIO_OWER_P14 (0x1u << 14)
1122#define PIO_OWER_P15 (0x1u << 15)
1123#define PIO_OWER_P16 (0x1u << 16)
1124#define PIO_OWER_P17 (0x1u << 17)
1125#define PIO_OWER_P18 (0x1u << 18)
1126#define PIO_OWER_P19 (0x1u << 19)
1127#define PIO_OWER_P20 (0x1u << 20)
1128#define PIO_OWER_P21 (0x1u << 21)
1129#define PIO_OWER_P22 (0x1u << 22)
1130#define PIO_OWER_P23 (0x1u << 23)
1131#define PIO_OWER_P24 (0x1u << 24)
1132#define PIO_OWER_P25 (0x1u << 25)
1133#define PIO_OWER_P26 (0x1u << 26)
1134#define PIO_OWER_P27 (0x1u << 27)
1135#define PIO_OWER_P28 (0x1u << 28)
1136#define PIO_OWER_P29 (0x1u << 29)
1137#define PIO_OWER_P30 (0x1u << 30)
1138#define PIO_OWER_P31 (0x1u << 31)
1139/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
1140#define PIO_OWDR_P0 (0x1u << 0)
1141#define PIO_OWDR_P1 (0x1u << 1)
1142#define PIO_OWDR_P2 (0x1u << 2)
1143#define PIO_OWDR_P3 (0x1u << 3)
1144#define PIO_OWDR_P4 (0x1u << 4)
1145#define PIO_OWDR_P5 (0x1u << 5)
1146#define PIO_OWDR_P6 (0x1u << 6)
1147#define PIO_OWDR_P7 (0x1u << 7)
1148#define PIO_OWDR_P8 (0x1u << 8)
1149#define PIO_OWDR_P9 (0x1u << 9)
1150#define PIO_OWDR_P10 (0x1u << 10)
1151#define PIO_OWDR_P11 (0x1u << 11)
1152#define PIO_OWDR_P12 (0x1u << 12)
1153#define PIO_OWDR_P13 (0x1u << 13)
1154#define PIO_OWDR_P14 (0x1u << 14)
1155#define PIO_OWDR_P15 (0x1u << 15)
1156#define PIO_OWDR_P16 (0x1u << 16)
1157#define PIO_OWDR_P17 (0x1u << 17)
1158#define PIO_OWDR_P18 (0x1u << 18)
1159#define PIO_OWDR_P19 (0x1u << 19)
1160#define PIO_OWDR_P20 (0x1u << 20)
1161#define PIO_OWDR_P21 (0x1u << 21)
1162#define PIO_OWDR_P22 (0x1u << 22)
1163#define PIO_OWDR_P23 (0x1u << 23)
1164#define PIO_OWDR_P24 (0x1u << 24)
1165#define PIO_OWDR_P25 (0x1u << 25)
1166#define PIO_OWDR_P26 (0x1u << 26)
1167#define PIO_OWDR_P27 (0x1u << 27)
1168#define PIO_OWDR_P28 (0x1u << 28)
1169#define PIO_OWDR_P29 (0x1u << 29)
1170#define PIO_OWDR_P30 (0x1u << 30)
1171#define PIO_OWDR_P31 (0x1u << 31)
1172/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
1173#define PIO_OWSR_P0 (0x1u << 0)
1174#define PIO_OWSR_P1 (0x1u << 1)
1175#define PIO_OWSR_P2 (0x1u << 2)
1176#define PIO_OWSR_P3 (0x1u << 3)
1177#define PIO_OWSR_P4 (0x1u << 4)
1178#define PIO_OWSR_P5 (0x1u << 5)
1179#define PIO_OWSR_P6 (0x1u << 6)
1180#define PIO_OWSR_P7 (0x1u << 7)
1181#define PIO_OWSR_P8 (0x1u << 8)
1182#define PIO_OWSR_P9 (0x1u << 9)
1183#define PIO_OWSR_P10 (0x1u << 10)
1184#define PIO_OWSR_P11 (0x1u << 11)
1185#define PIO_OWSR_P12 (0x1u << 12)
1186#define PIO_OWSR_P13 (0x1u << 13)
1187#define PIO_OWSR_P14 (0x1u << 14)
1188#define PIO_OWSR_P15 (0x1u << 15)
1189#define PIO_OWSR_P16 (0x1u << 16)
1190#define PIO_OWSR_P17 (0x1u << 17)
1191#define PIO_OWSR_P18 (0x1u << 18)
1192#define PIO_OWSR_P19 (0x1u << 19)
1193#define PIO_OWSR_P20 (0x1u << 20)
1194#define PIO_OWSR_P21 (0x1u << 21)
1195#define PIO_OWSR_P22 (0x1u << 22)
1196#define PIO_OWSR_P23 (0x1u << 23)
1197#define PIO_OWSR_P24 (0x1u << 24)
1198#define PIO_OWSR_P25 (0x1u << 25)
1199#define PIO_OWSR_P26 (0x1u << 26)
1200#define PIO_OWSR_P27 (0x1u << 27)
1201#define PIO_OWSR_P28 (0x1u << 28)
1202#define PIO_OWSR_P29 (0x1u << 29)
1203#define PIO_OWSR_P30 (0x1u << 30)
1204#define PIO_OWSR_P31 (0x1u << 31)
1205/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
1206#define PIO_AIMER_P0 (0x1u << 0)
1207#define PIO_AIMER_P1 (0x1u << 1)
1208#define PIO_AIMER_P2 (0x1u << 2)
1209#define PIO_AIMER_P3 (0x1u << 3)
1210#define PIO_AIMER_P4 (0x1u << 4)
1211#define PIO_AIMER_P5 (0x1u << 5)
1212#define PIO_AIMER_P6 (0x1u << 6)
1213#define PIO_AIMER_P7 (0x1u << 7)
1214#define PIO_AIMER_P8 (0x1u << 8)
1215#define PIO_AIMER_P9 (0x1u << 9)
1216#define PIO_AIMER_P10 (0x1u << 10)
1217#define PIO_AIMER_P11 (0x1u << 11)
1218#define PIO_AIMER_P12 (0x1u << 12)
1219#define PIO_AIMER_P13 (0x1u << 13)
1220#define PIO_AIMER_P14 (0x1u << 14)
1221#define PIO_AIMER_P15 (0x1u << 15)
1222#define PIO_AIMER_P16 (0x1u << 16)
1223#define PIO_AIMER_P17 (0x1u << 17)
1224#define PIO_AIMER_P18 (0x1u << 18)
1225#define PIO_AIMER_P19 (0x1u << 19)
1226#define PIO_AIMER_P20 (0x1u << 20)
1227#define PIO_AIMER_P21 (0x1u << 21)
1228#define PIO_AIMER_P22 (0x1u << 22)
1229#define PIO_AIMER_P23 (0x1u << 23)
1230#define PIO_AIMER_P24 (0x1u << 24)
1231#define PIO_AIMER_P25 (0x1u << 25)
1232#define PIO_AIMER_P26 (0x1u << 26)
1233#define PIO_AIMER_P27 (0x1u << 27)
1234#define PIO_AIMER_P28 (0x1u << 28)
1235#define PIO_AIMER_P29 (0x1u << 29)
1236#define PIO_AIMER_P30 (0x1u << 30)
1237#define PIO_AIMER_P31 (0x1u << 31)
1238/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */
1239#define PIO_AIMDR_P0 (0x1u << 0)
1240#define PIO_AIMDR_P1 (0x1u << 1)
1241#define PIO_AIMDR_P2 (0x1u << 2)
1242#define PIO_AIMDR_P3 (0x1u << 3)
1243#define PIO_AIMDR_P4 (0x1u << 4)
1244#define PIO_AIMDR_P5 (0x1u << 5)
1245#define PIO_AIMDR_P6 (0x1u << 6)
1246#define PIO_AIMDR_P7 (0x1u << 7)
1247#define PIO_AIMDR_P8 (0x1u << 8)
1248#define PIO_AIMDR_P9 (0x1u << 9)
1249#define PIO_AIMDR_P10 (0x1u << 10)
1250#define PIO_AIMDR_P11 (0x1u << 11)
1251#define PIO_AIMDR_P12 (0x1u << 12)
1252#define PIO_AIMDR_P13 (0x1u << 13)
1253#define PIO_AIMDR_P14 (0x1u << 14)
1254#define PIO_AIMDR_P15 (0x1u << 15)
1255#define PIO_AIMDR_P16 (0x1u << 16)
1256#define PIO_AIMDR_P17 (0x1u << 17)
1257#define PIO_AIMDR_P18 (0x1u << 18)
1258#define PIO_AIMDR_P19 (0x1u << 19)
1259#define PIO_AIMDR_P20 (0x1u << 20)
1260#define PIO_AIMDR_P21 (0x1u << 21)
1261#define PIO_AIMDR_P22 (0x1u << 22)
1262#define PIO_AIMDR_P23 (0x1u << 23)
1263#define PIO_AIMDR_P24 (0x1u << 24)
1264#define PIO_AIMDR_P25 (0x1u << 25)
1265#define PIO_AIMDR_P26 (0x1u << 26)
1266#define PIO_AIMDR_P27 (0x1u << 27)
1267#define PIO_AIMDR_P28 (0x1u << 28)
1268#define PIO_AIMDR_P29 (0x1u << 29)
1269#define PIO_AIMDR_P30 (0x1u << 30)
1270#define PIO_AIMDR_P31 (0x1u << 31)
1271/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
1272#define PIO_AIMMR_P0 (0x1u << 0)
1273#define PIO_AIMMR_P1 (0x1u << 1)
1274#define PIO_AIMMR_P2 (0x1u << 2)
1275#define PIO_AIMMR_P3 (0x1u << 3)
1276#define PIO_AIMMR_P4 (0x1u << 4)
1277#define PIO_AIMMR_P5 (0x1u << 5)
1278#define PIO_AIMMR_P6 (0x1u << 6)
1279#define PIO_AIMMR_P7 (0x1u << 7)
1280#define PIO_AIMMR_P8 (0x1u << 8)
1281#define PIO_AIMMR_P9 (0x1u << 9)
1282#define PIO_AIMMR_P10 (0x1u << 10)
1283#define PIO_AIMMR_P11 (0x1u << 11)
1284#define PIO_AIMMR_P12 (0x1u << 12)
1285#define PIO_AIMMR_P13 (0x1u << 13)
1286#define PIO_AIMMR_P14 (0x1u << 14)
1287#define PIO_AIMMR_P15 (0x1u << 15)
1288#define PIO_AIMMR_P16 (0x1u << 16)
1289#define PIO_AIMMR_P17 (0x1u << 17)
1290#define PIO_AIMMR_P18 (0x1u << 18)
1291#define PIO_AIMMR_P19 (0x1u << 19)
1292#define PIO_AIMMR_P20 (0x1u << 20)
1293#define PIO_AIMMR_P21 (0x1u << 21)
1294#define PIO_AIMMR_P22 (0x1u << 22)
1295#define PIO_AIMMR_P23 (0x1u << 23)
1296#define PIO_AIMMR_P24 (0x1u << 24)
1297#define PIO_AIMMR_P25 (0x1u << 25)
1298#define PIO_AIMMR_P26 (0x1u << 26)
1299#define PIO_AIMMR_P27 (0x1u << 27)
1300#define PIO_AIMMR_P28 (0x1u << 28)
1301#define PIO_AIMMR_P29 (0x1u << 29)
1302#define PIO_AIMMR_P30 (0x1u << 30)
1303#define PIO_AIMMR_P31 (0x1u << 31)
1304/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
1305#define PIO_ESR_P0 (0x1u << 0)
1306#define PIO_ESR_P1 (0x1u << 1)
1307#define PIO_ESR_P2 (0x1u << 2)
1308#define PIO_ESR_P3 (0x1u << 3)
1309#define PIO_ESR_P4 (0x1u << 4)
1310#define PIO_ESR_P5 (0x1u << 5)
1311#define PIO_ESR_P6 (0x1u << 6)
1312#define PIO_ESR_P7 (0x1u << 7)
1313#define PIO_ESR_P8 (0x1u << 8)
1314#define PIO_ESR_P9 (0x1u << 9)
1315#define PIO_ESR_P10 (0x1u << 10)
1316#define PIO_ESR_P11 (0x1u << 11)
1317#define PIO_ESR_P12 (0x1u << 12)
1318#define PIO_ESR_P13 (0x1u << 13)
1319#define PIO_ESR_P14 (0x1u << 14)
1320#define PIO_ESR_P15 (0x1u << 15)
1321#define PIO_ESR_P16 (0x1u << 16)
1322#define PIO_ESR_P17 (0x1u << 17)
1323#define PIO_ESR_P18 (0x1u << 18)
1324#define PIO_ESR_P19 (0x1u << 19)
1325#define PIO_ESR_P20 (0x1u << 20)
1326#define PIO_ESR_P21 (0x1u << 21)
1327#define PIO_ESR_P22 (0x1u << 22)
1328#define PIO_ESR_P23 (0x1u << 23)
1329#define PIO_ESR_P24 (0x1u << 24)
1330#define PIO_ESR_P25 (0x1u << 25)
1331#define PIO_ESR_P26 (0x1u << 26)
1332#define PIO_ESR_P27 (0x1u << 27)
1333#define PIO_ESR_P28 (0x1u << 28)
1334#define PIO_ESR_P29 (0x1u << 29)
1335#define PIO_ESR_P30 (0x1u << 30)
1336#define PIO_ESR_P31 (0x1u << 31)
1337/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
1338#define PIO_LSR_P0 (0x1u << 0)
1339#define PIO_LSR_P1 (0x1u << 1)
1340#define PIO_LSR_P2 (0x1u << 2)
1341#define PIO_LSR_P3 (0x1u << 3)
1342#define PIO_LSR_P4 (0x1u << 4)
1343#define PIO_LSR_P5 (0x1u << 5)
1344#define PIO_LSR_P6 (0x1u << 6)
1345#define PIO_LSR_P7 (0x1u << 7)
1346#define PIO_LSR_P8 (0x1u << 8)
1347#define PIO_LSR_P9 (0x1u << 9)
1348#define PIO_LSR_P10 (0x1u << 10)
1349#define PIO_LSR_P11 (0x1u << 11)
1350#define PIO_LSR_P12 (0x1u << 12)
1351#define PIO_LSR_P13 (0x1u << 13)
1352#define PIO_LSR_P14 (0x1u << 14)
1353#define PIO_LSR_P15 (0x1u << 15)
1354#define PIO_LSR_P16 (0x1u << 16)
1355#define PIO_LSR_P17 (0x1u << 17)
1356#define PIO_LSR_P18 (0x1u << 18)
1357#define PIO_LSR_P19 (0x1u << 19)
1358#define PIO_LSR_P20 (0x1u << 20)
1359#define PIO_LSR_P21 (0x1u << 21)
1360#define PIO_LSR_P22 (0x1u << 22)
1361#define PIO_LSR_P23 (0x1u << 23)
1362#define PIO_LSR_P24 (0x1u << 24)
1363#define PIO_LSR_P25 (0x1u << 25)
1364#define PIO_LSR_P26 (0x1u << 26)
1365#define PIO_LSR_P27 (0x1u << 27)
1366#define PIO_LSR_P28 (0x1u << 28)
1367#define PIO_LSR_P29 (0x1u << 29)
1368#define PIO_LSR_P30 (0x1u << 30)
1369#define PIO_LSR_P31 (0x1u << 31)
1370/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
1371#define PIO_ELSR_P0 (0x1u << 0)
1372#define PIO_ELSR_P1 (0x1u << 1)
1373#define PIO_ELSR_P2 (0x1u << 2)
1374#define PIO_ELSR_P3 (0x1u << 3)
1375#define PIO_ELSR_P4 (0x1u << 4)
1376#define PIO_ELSR_P5 (0x1u << 5)
1377#define PIO_ELSR_P6 (0x1u << 6)
1378#define PIO_ELSR_P7 (0x1u << 7)
1379#define PIO_ELSR_P8 (0x1u << 8)
1380#define PIO_ELSR_P9 (0x1u << 9)
1381#define PIO_ELSR_P10 (0x1u << 10)
1382#define PIO_ELSR_P11 (0x1u << 11)
1383#define PIO_ELSR_P12 (0x1u << 12)
1384#define PIO_ELSR_P13 (0x1u << 13)
1385#define PIO_ELSR_P14 (0x1u << 14)
1386#define PIO_ELSR_P15 (0x1u << 15)
1387#define PIO_ELSR_P16 (0x1u << 16)
1388#define PIO_ELSR_P17 (0x1u << 17)
1389#define PIO_ELSR_P18 (0x1u << 18)
1390#define PIO_ELSR_P19 (0x1u << 19)
1391#define PIO_ELSR_P20 (0x1u << 20)
1392#define PIO_ELSR_P21 (0x1u << 21)
1393#define PIO_ELSR_P22 (0x1u << 22)
1394#define PIO_ELSR_P23 (0x1u << 23)
1395#define PIO_ELSR_P24 (0x1u << 24)
1396#define PIO_ELSR_P25 (0x1u << 25)
1397#define PIO_ELSR_P26 (0x1u << 26)
1398#define PIO_ELSR_P27 (0x1u << 27)
1399#define PIO_ELSR_P28 (0x1u << 28)
1400#define PIO_ELSR_P29 (0x1u << 29)
1401#define PIO_ELSR_P30 (0x1u << 30)
1402#define PIO_ELSR_P31 (0x1u << 31)
1403/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */
1404#define PIO_FELLSR_P0 (0x1u << 0)
1405#define PIO_FELLSR_P1 (0x1u << 1)
1406#define PIO_FELLSR_P2 (0x1u << 2)
1407#define PIO_FELLSR_P3 (0x1u << 3)
1408#define PIO_FELLSR_P4 (0x1u << 4)
1409#define PIO_FELLSR_P5 (0x1u << 5)
1410#define PIO_FELLSR_P6 (0x1u << 6)
1411#define PIO_FELLSR_P7 (0x1u << 7)
1412#define PIO_FELLSR_P8 (0x1u << 8)
1413#define PIO_FELLSR_P9 (0x1u << 9)
1414#define PIO_FELLSR_P10 (0x1u << 10)
1415#define PIO_FELLSR_P11 (0x1u << 11)
1416#define PIO_FELLSR_P12 (0x1u << 12)
1417#define PIO_FELLSR_P13 (0x1u << 13)
1418#define PIO_FELLSR_P14 (0x1u << 14)
1419#define PIO_FELLSR_P15 (0x1u << 15)
1420#define PIO_FELLSR_P16 (0x1u << 16)
1421#define PIO_FELLSR_P17 (0x1u << 17)
1422#define PIO_FELLSR_P18 (0x1u << 18)
1423#define PIO_FELLSR_P19 (0x1u << 19)
1424#define PIO_FELLSR_P20 (0x1u << 20)
1425#define PIO_FELLSR_P21 (0x1u << 21)
1426#define PIO_FELLSR_P22 (0x1u << 22)
1427#define PIO_FELLSR_P23 (0x1u << 23)
1428#define PIO_FELLSR_P24 (0x1u << 24)
1429#define PIO_FELLSR_P25 (0x1u << 25)
1430#define PIO_FELLSR_P26 (0x1u << 26)
1431#define PIO_FELLSR_P27 (0x1u << 27)
1432#define PIO_FELLSR_P28 (0x1u << 28)
1433#define PIO_FELLSR_P29 (0x1u << 29)
1434#define PIO_FELLSR_P30 (0x1u << 30)
1435#define PIO_FELLSR_P31 (0x1u << 31)
1436/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/High-Level Select Register -------- */
1437#define PIO_REHLSR_P0 (0x1u << 0)
1438#define PIO_REHLSR_P1 (0x1u << 1)
1439#define PIO_REHLSR_P2 (0x1u << 2)
1440#define PIO_REHLSR_P3 (0x1u << 3)
1441#define PIO_REHLSR_P4 (0x1u << 4)
1442#define PIO_REHLSR_P5 (0x1u << 5)
1443#define PIO_REHLSR_P6 (0x1u << 6)
1444#define PIO_REHLSR_P7 (0x1u << 7)
1445#define PIO_REHLSR_P8 (0x1u << 8)
1446#define PIO_REHLSR_P9 (0x1u << 9)
1447#define PIO_REHLSR_P10 (0x1u << 10)
1448#define PIO_REHLSR_P11 (0x1u << 11)
1449#define PIO_REHLSR_P12 (0x1u << 12)
1450#define PIO_REHLSR_P13 (0x1u << 13)
1451#define PIO_REHLSR_P14 (0x1u << 14)
1452#define PIO_REHLSR_P15 (0x1u << 15)
1453#define PIO_REHLSR_P16 (0x1u << 16)
1454#define PIO_REHLSR_P17 (0x1u << 17)
1455#define PIO_REHLSR_P18 (0x1u << 18)
1456#define PIO_REHLSR_P19 (0x1u << 19)
1457#define PIO_REHLSR_P20 (0x1u << 20)
1458#define PIO_REHLSR_P21 (0x1u << 21)
1459#define PIO_REHLSR_P22 (0x1u << 22)
1460#define PIO_REHLSR_P23 (0x1u << 23)
1461#define PIO_REHLSR_P24 (0x1u << 24)
1462#define PIO_REHLSR_P25 (0x1u << 25)
1463#define PIO_REHLSR_P26 (0x1u << 26)
1464#define PIO_REHLSR_P27 (0x1u << 27)
1465#define PIO_REHLSR_P28 (0x1u << 28)
1466#define PIO_REHLSR_P29 (0x1u << 29)
1467#define PIO_REHLSR_P30 (0x1u << 30)
1468#define PIO_REHLSR_P31 (0x1u << 31)
1469/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
1470#define PIO_FRLHSR_P0 (0x1u << 0)
1471#define PIO_FRLHSR_P1 (0x1u << 1)
1472#define PIO_FRLHSR_P2 (0x1u << 2)
1473#define PIO_FRLHSR_P3 (0x1u << 3)
1474#define PIO_FRLHSR_P4 (0x1u << 4)
1475#define PIO_FRLHSR_P5 (0x1u << 5)
1476#define PIO_FRLHSR_P6 (0x1u << 6)
1477#define PIO_FRLHSR_P7 (0x1u << 7)
1478#define PIO_FRLHSR_P8 (0x1u << 8)
1479#define PIO_FRLHSR_P9 (0x1u << 9)
1480#define PIO_FRLHSR_P10 (0x1u << 10)
1481#define PIO_FRLHSR_P11 (0x1u << 11)
1482#define PIO_FRLHSR_P12 (0x1u << 12)
1483#define PIO_FRLHSR_P13 (0x1u << 13)
1484#define PIO_FRLHSR_P14 (0x1u << 14)
1485#define PIO_FRLHSR_P15 (0x1u << 15)
1486#define PIO_FRLHSR_P16 (0x1u << 16)
1487#define PIO_FRLHSR_P17 (0x1u << 17)
1488#define PIO_FRLHSR_P18 (0x1u << 18)
1489#define PIO_FRLHSR_P19 (0x1u << 19)
1490#define PIO_FRLHSR_P20 (0x1u << 20)
1491#define PIO_FRLHSR_P21 (0x1u << 21)
1492#define PIO_FRLHSR_P22 (0x1u << 22)
1493#define PIO_FRLHSR_P23 (0x1u << 23)
1494#define PIO_FRLHSR_P24 (0x1u << 24)
1495#define PIO_FRLHSR_P25 (0x1u << 25)
1496#define PIO_FRLHSR_P26 (0x1u << 26)
1497#define PIO_FRLHSR_P27 (0x1u << 27)
1498#define PIO_FRLHSR_P28 (0x1u << 28)
1499#define PIO_FRLHSR_P29 (0x1u << 29)
1500#define PIO_FRLHSR_P30 (0x1u << 30)
1501#define PIO_FRLHSR_P31 (0x1u << 31)
1502/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
1503#define PIO_LOCKSR_P0 (0x1u << 0)
1504#define PIO_LOCKSR_P1 (0x1u << 1)
1505#define PIO_LOCKSR_P2 (0x1u << 2)
1506#define PIO_LOCKSR_P3 (0x1u << 3)
1507#define PIO_LOCKSR_P4 (0x1u << 4)
1508#define PIO_LOCKSR_P5 (0x1u << 5)
1509#define PIO_LOCKSR_P6 (0x1u << 6)
1510#define PIO_LOCKSR_P7 (0x1u << 7)
1511#define PIO_LOCKSR_P8 (0x1u << 8)
1512#define PIO_LOCKSR_P9 (0x1u << 9)
1513#define PIO_LOCKSR_P10 (0x1u << 10)
1514#define PIO_LOCKSR_P11 (0x1u << 11)
1515#define PIO_LOCKSR_P12 (0x1u << 12)
1516#define PIO_LOCKSR_P13 (0x1u << 13)
1517#define PIO_LOCKSR_P14 (0x1u << 14)
1518#define PIO_LOCKSR_P15 (0x1u << 15)
1519#define PIO_LOCKSR_P16 (0x1u << 16)
1520#define PIO_LOCKSR_P17 (0x1u << 17)
1521#define PIO_LOCKSR_P18 (0x1u << 18)
1522#define PIO_LOCKSR_P19 (0x1u << 19)
1523#define PIO_LOCKSR_P20 (0x1u << 20)
1524#define PIO_LOCKSR_P21 (0x1u << 21)
1525#define PIO_LOCKSR_P22 (0x1u << 22)
1526#define PIO_LOCKSR_P23 (0x1u << 23)
1527#define PIO_LOCKSR_P24 (0x1u << 24)
1528#define PIO_LOCKSR_P25 (0x1u << 25)
1529#define PIO_LOCKSR_P26 (0x1u << 26)
1530#define PIO_LOCKSR_P27 (0x1u << 27)
1531#define PIO_LOCKSR_P28 (0x1u << 28)
1532#define PIO_LOCKSR_P29 (0x1u << 29)
1533#define PIO_LOCKSR_P30 (0x1u << 30)
1534#define PIO_LOCKSR_P31 (0x1u << 31)
1535/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */
1536#define PIO_WPMR_WPEN (0x1u << 0)
1537#define PIO_WPMR_WPKEY_Pos 8
1538#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos)
1539#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
1540#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8)
1541/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */
1542#define PIO_WPSR_WPVS (0x1u << 0)
1543#define PIO_WPSR_WPVSRC_Pos 8
1544#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos)
1545/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */
1546#define PIO_SCHMITT_SCHMITT0 (0x1u << 0)
1547#define PIO_SCHMITT_SCHMITT1 (0x1u << 1)
1548#define PIO_SCHMITT_SCHMITT2 (0x1u << 2)
1549#define PIO_SCHMITT_SCHMITT3 (0x1u << 3)
1550#define PIO_SCHMITT_SCHMITT4 (0x1u << 4)
1551#define PIO_SCHMITT_SCHMITT5 (0x1u << 5)
1552#define PIO_SCHMITT_SCHMITT6 (0x1u << 6)
1553#define PIO_SCHMITT_SCHMITT7 (0x1u << 7)
1554#define PIO_SCHMITT_SCHMITT8 (0x1u << 8)
1555#define PIO_SCHMITT_SCHMITT9 (0x1u << 9)
1556#define PIO_SCHMITT_SCHMITT10 (0x1u << 10)
1557#define PIO_SCHMITT_SCHMITT11 (0x1u << 11)
1558#define PIO_SCHMITT_SCHMITT12 (0x1u << 12)
1559#define PIO_SCHMITT_SCHMITT13 (0x1u << 13)
1560#define PIO_SCHMITT_SCHMITT14 (0x1u << 14)
1561#define PIO_SCHMITT_SCHMITT15 (0x1u << 15)
1562#define PIO_SCHMITT_SCHMITT16 (0x1u << 16)
1563#define PIO_SCHMITT_SCHMITT17 (0x1u << 17)
1564#define PIO_SCHMITT_SCHMITT18 (0x1u << 18)
1565#define PIO_SCHMITT_SCHMITT19 (0x1u << 19)
1566#define PIO_SCHMITT_SCHMITT20 (0x1u << 20)
1567#define PIO_SCHMITT_SCHMITT21 (0x1u << 21)
1568#define PIO_SCHMITT_SCHMITT22 (0x1u << 22)
1569#define PIO_SCHMITT_SCHMITT23 (0x1u << 23)
1570#define PIO_SCHMITT_SCHMITT24 (0x1u << 24)
1571#define PIO_SCHMITT_SCHMITT25 (0x1u << 25)
1572#define PIO_SCHMITT_SCHMITT26 (0x1u << 26)
1573#define PIO_SCHMITT_SCHMITT27 (0x1u << 27)
1574#define PIO_SCHMITT_SCHMITT28 (0x1u << 28)
1575#define PIO_SCHMITT_SCHMITT29 (0x1u << 29)
1576#define PIO_SCHMITT_SCHMITT30 (0x1u << 30)
1577#define PIO_SCHMITT_SCHMITT31 (0x1u << 31)
1578/* -------- PIO_DRIVER : (PIO Offset: 0x0118) I/O Drive Register -------- */
1579#define PIO_DRIVER_LINE0 (0x1u << 0)
1580#define PIO_DRIVER_LINE0_LOW_DRIVE (0x0u << 0)
1581#define PIO_DRIVER_LINE0_HIGH_DRIVE (0x1u << 0)
1582#define PIO_DRIVER_LINE1 (0x1u << 1)
1583#define PIO_DRIVER_LINE1_LOW_DRIVE (0x0u << 1)
1584#define PIO_DRIVER_LINE1_HIGH_DRIVE (0x1u << 1)
1585#define PIO_DRIVER_LINE2 (0x1u << 2)
1586#define PIO_DRIVER_LINE2_LOW_DRIVE (0x0u << 2)
1587#define PIO_DRIVER_LINE2_HIGH_DRIVE (0x1u << 2)
1588#define PIO_DRIVER_LINE3 (0x1u << 3)
1589#define PIO_DRIVER_LINE3_LOW_DRIVE (0x0u << 3)
1590#define PIO_DRIVER_LINE3_HIGH_DRIVE (0x1u << 3)
1591#define PIO_DRIVER_LINE4 (0x1u << 4)
1592#define PIO_DRIVER_LINE4_LOW_DRIVE (0x0u << 4)
1593#define PIO_DRIVER_LINE4_HIGH_DRIVE (0x1u << 4)
1594#define PIO_DRIVER_LINE5 (0x1u << 5)
1595#define PIO_DRIVER_LINE5_LOW_DRIVE (0x0u << 5)
1596#define PIO_DRIVER_LINE5_HIGH_DRIVE (0x1u << 5)
1597#define PIO_DRIVER_LINE6 (0x1u << 6)
1598#define PIO_DRIVER_LINE6_LOW_DRIVE (0x0u << 6)
1599#define PIO_DRIVER_LINE6_HIGH_DRIVE (0x1u << 6)
1600#define PIO_DRIVER_LINE7 (0x1u << 7)
1601#define PIO_DRIVER_LINE7_LOW_DRIVE (0x0u << 7)
1602#define PIO_DRIVER_LINE7_HIGH_DRIVE (0x1u << 7)
1603#define PIO_DRIVER_LINE8 (0x1u << 8)
1604#define PIO_DRIVER_LINE8_LOW_DRIVE (0x0u << 8)
1605#define PIO_DRIVER_LINE8_HIGH_DRIVE (0x1u << 8)
1606#define PIO_DRIVER_LINE9 (0x1u << 9)
1607#define PIO_DRIVER_LINE9_LOW_DRIVE (0x0u << 9)
1608#define PIO_DRIVER_LINE9_HIGH_DRIVE (0x1u << 9)
1609#define PIO_DRIVER_LINE10 (0x1u << 10)
1610#define PIO_DRIVER_LINE10_LOW_DRIVE (0x0u << 10)
1611#define PIO_DRIVER_LINE10_HIGH_DRIVE (0x1u << 10)
1612#define PIO_DRIVER_LINE11 (0x1u << 11)
1613#define PIO_DRIVER_LINE11_LOW_DRIVE (0x0u << 11)
1614#define PIO_DRIVER_LINE11_HIGH_DRIVE (0x1u << 11)
1615#define PIO_DRIVER_LINE12 (0x1u << 12)
1616#define PIO_DRIVER_LINE12_LOW_DRIVE (0x0u << 12)
1617#define PIO_DRIVER_LINE12_HIGH_DRIVE (0x1u << 12)
1618#define PIO_DRIVER_LINE13 (0x1u << 13)
1619#define PIO_DRIVER_LINE13_LOW_DRIVE (0x0u << 13)
1620#define PIO_DRIVER_LINE13_HIGH_DRIVE (0x1u << 13)
1621#define PIO_DRIVER_LINE14 (0x1u << 14)
1622#define PIO_DRIVER_LINE14_LOW_DRIVE (0x0u << 14)
1623#define PIO_DRIVER_LINE14_HIGH_DRIVE (0x1u << 14)
1624#define PIO_DRIVER_LINE15 (0x1u << 15)
1625#define PIO_DRIVER_LINE15_LOW_DRIVE (0x0u << 15)
1626#define PIO_DRIVER_LINE15_HIGH_DRIVE (0x1u << 15)
1627#define PIO_DRIVER_LINE16 (0x1u << 16)
1628#define PIO_DRIVER_LINE16_LOW_DRIVE (0x0u << 16)
1629#define PIO_DRIVER_LINE16_HIGH_DRIVE (0x1u << 16)
1630#define PIO_DRIVER_LINE17 (0x1u << 17)
1631#define PIO_DRIVER_LINE17_LOW_DRIVE (0x0u << 17)
1632#define PIO_DRIVER_LINE17_HIGH_DRIVE (0x1u << 17)
1633#define PIO_DRIVER_LINE18 (0x1u << 18)
1634#define PIO_DRIVER_LINE18_LOW_DRIVE (0x0u << 18)
1635#define PIO_DRIVER_LINE18_HIGH_DRIVE (0x1u << 18)
1636#define PIO_DRIVER_LINE19 (0x1u << 19)
1637#define PIO_DRIVER_LINE19_LOW_DRIVE (0x0u << 19)
1638#define PIO_DRIVER_LINE19_HIGH_DRIVE (0x1u << 19)
1639#define PIO_DRIVER_LINE20 (0x1u << 20)
1640#define PIO_DRIVER_LINE20_LOW_DRIVE (0x0u << 20)
1641#define PIO_DRIVER_LINE20_HIGH_DRIVE (0x1u << 20)
1642#define PIO_DRIVER_LINE21 (0x1u << 21)
1643#define PIO_DRIVER_LINE21_LOW_DRIVE (0x0u << 21)
1644#define PIO_DRIVER_LINE21_HIGH_DRIVE (0x1u << 21)
1645#define PIO_DRIVER_LINE22 (0x1u << 22)
1646#define PIO_DRIVER_LINE22_LOW_DRIVE (0x0u << 22)
1647#define PIO_DRIVER_LINE22_HIGH_DRIVE (0x1u << 22)
1648#define PIO_DRIVER_LINE23 (0x1u << 23)
1649#define PIO_DRIVER_LINE23_LOW_DRIVE (0x0u << 23)
1650#define PIO_DRIVER_LINE23_HIGH_DRIVE (0x1u << 23)
1651#define PIO_DRIVER_LINE24 (0x1u << 24)
1652#define PIO_DRIVER_LINE24_LOW_DRIVE (0x0u << 24)
1653#define PIO_DRIVER_LINE24_HIGH_DRIVE (0x1u << 24)
1654#define PIO_DRIVER_LINE25 (0x1u << 25)
1655#define PIO_DRIVER_LINE25_LOW_DRIVE (0x0u << 25)
1656#define PIO_DRIVER_LINE25_HIGH_DRIVE (0x1u << 25)
1657#define PIO_DRIVER_LINE26 (0x1u << 26)
1658#define PIO_DRIVER_LINE26_LOW_DRIVE (0x0u << 26)
1659#define PIO_DRIVER_LINE26_HIGH_DRIVE (0x1u << 26)
1660#define PIO_DRIVER_LINE27 (0x1u << 27)
1661#define PIO_DRIVER_LINE27_LOW_DRIVE (0x0u << 27)
1662#define PIO_DRIVER_LINE27_HIGH_DRIVE (0x1u << 27)
1663#define PIO_DRIVER_LINE28 (0x1u << 28)
1664#define PIO_DRIVER_LINE28_LOW_DRIVE (0x0u << 28)
1665#define PIO_DRIVER_LINE28_HIGH_DRIVE (0x1u << 28)
1666#define PIO_DRIVER_LINE29 (0x1u << 29)
1667#define PIO_DRIVER_LINE29_LOW_DRIVE (0x0u << 29)
1668#define PIO_DRIVER_LINE29_HIGH_DRIVE (0x1u << 29)
1669#define PIO_DRIVER_LINE30 (0x1u << 30)
1670#define PIO_DRIVER_LINE30_LOW_DRIVE (0x0u << 30)
1671#define PIO_DRIVER_LINE30_HIGH_DRIVE (0x1u << 30)
1672#define PIO_DRIVER_LINE31 (0x1u << 31)
1673#define PIO_DRIVER_LINE31_LOW_DRIVE (0x0u << 31)
1674#define PIO_DRIVER_LINE31_HIGH_DRIVE (0x1u << 31)
1675/* -------- PIO_PCMR : (PIO Offset: 0x0150) Parallel Capture Mode Register -------- */
1676#define PIO_PCMR_PCEN (0x1u << 0)
1677#define PIO_PCMR_DSIZE_Pos 4
1678#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos)
1679#define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos)))
1680#define PIO_PCMR_DSIZE_BYTE (0x0u << 4)
1681#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4)
1682#define PIO_PCMR_DSIZE_WORD (0x2u << 4)
1683#define PIO_PCMR_ALWYS (0x1u << 9)
1684#define PIO_PCMR_HALFS (0x1u << 10)
1685#define PIO_PCMR_FRSTS (0x1u << 11)
1686/* -------- PIO_PCIER : (PIO Offset: 0x0154) Parallel Capture Interrupt Enable Register -------- */
1687#define PIO_PCIER_DRDY (0x1u << 0)
1688#define PIO_PCIER_OVRE (0x1u << 1)
1689#define PIO_PCIER_ENDRX (0x1u << 2)
1690#define PIO_PCIER_RXBUFF (0x1u << 3)
1691/* -------- PIO_PCIDR : (PIO Offset: 0x0158) Parallel Capture Interrupt Disable Register -------- */
1692#define PIO_PCIDR_DRDY (0x1u << 0)
1693#define PIO_PCIDR_OVRE (0x1u << 1)
1694#define PIO_PCIDR_ENDRX (0x1u << 2)
1695#define PIO_PCIDR_RXBUFF (0x1u << 3)
1696/* -------- PIO_PCIMR : (PIO Offset: 0x015C) Parallel Capture Interrupt Mask Register -------- */
1697#define PIO_PCIMR_DRDY (0x1u << 0)
1698#define PIO_PCIMR_OVRE (0x1u << 1)
1699#define PIO_PCIMR_ENDRX (0x1u << 2)
1700#define PIO_PCIMR_RXBUFF (0x1u << 3)
1701/* -------- PIO_PCISR : (PIO Offset: 0x0160) Parallel Capture Interrupt Status Register -------- */
1702#define PIO_PCISR_DRDY (0x1u << 0)
1703#define PIO_PCISR_OVRE (0x1u << 1)
1704/* -------- PIO_PCRHR : (PIO Offset: 0x0164) Parallel Capture Reception Holding Register -------- */
1705#define PIO_PCRHR_RDATA_Pos 0
1706#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos)
1709
1710
1711#endif /* _SAME70_PIO_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Pio
Pio hardware registers.
Definition: component_pio.h:41
Pio::PIO_PCISR
__I uint32_t PIO_PCISR
(Pio Offset: 0x0160) Parallel Capture Interrupt Status Register
Definition: component_pio.h:108
Pio::PIO_ISR
__I uint32_t PIO_ISR
(Pio Offset: 0x004C) Interrupt Status Register
Definition: component_pio.h:61
Pio::PIO_WPMR
__IO uint32_t PIO_WPMR
(Pio Offset: 0x00E4) Write Protection Mode Register
Definition: component_pio.h:97
Pio::PIO_PPDSR
__I uint32_t PIO_PPDSR
(Pio Offset: 0x0098) Pad Pull-down Status Register
Definition: component_pio.h:78
Pio::PIO_ESR
__O uint32_t PIO_ESR
(Pio Offset: 0x00C0) Edge Select Register
Definition: component_pio.h:88
Pio::PIO_PDSR
__I uint32_t PIO_PDSR
(Pio Offset: 0x003C) Pin Data Status Register
Definition: component_pio.h:57
Pio::PIO_OWER
__O uint32_t PIO_OWER
(Pio Offset: 0x00A0) Output Write Enable
Definition: component_pio.h:80
Pio::PIO_PUDR
__O uint32_t PIO_PUDR
(Pio Offset: 0x0060) Pull-up Disable Register
Definition: component_pio.h:66
Pio::PIO_IFDR
__O uint32_t PIO_IFDR
(Pio Offset: 0x0024) Glitch Input Filter Disable Register
Definition: component_pio.h:51
Pio::PIO_SCDR
__IO uint32_t PIO_SCDR
(Pio Offset: 0x008C) Slow Clock Divider Debouncing Register
Definition: component_pio.h:75
Pio::PIO_OWDR
__O uint32_t PIO_OWDR
(Pio Offset: 0x00A4) Output Write Disable
Definition: component_pio.h:81
Pio::PIO_PCMR
__IO uint32_t PIO_PCMR
(Pio Offset: 0x0150) Parallel Capture Mode Register
Definition: component_pio.h:104
Pio::PIO_REHLSR
__O uint32_t PIO_REHLSR
(Pio Offset: 0x00D4) Rising Edge/High-Level Select Register
Definition: component_pio.h:93
Pio::PIO_LOCKSR
__I uint32_t PIO_LOCKSR
(Pio Offset: 0x00E0) Lock Status
Definition: component_pio.h:96
Pio::PIO_MDDR
__O uint32_t PIO_MDDR
(Pio Offset: 0x0054) Multi-driver Disable Register
Definition: component_pio.h:63
Pio::PIO_LSR
__O uint32_t PIO_LSR
(Pio Offset: 0x00C4) Level Select Register
Definition: component_pio.h:89
Pio::PIO_DRIVER
__IO uint32_t PIO_DRIVER
(Pio Offset: 0x0118) I/O Drive Register
Definition: component_pio.h:102
Pio::PIO_AIMER
__O uint32_t PIO_AIMER
(Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register
Definition: component_pio.h:84
Pio::PIO_ELSR
__I uint32_t PIO_ELSR
(Pio Offset: 0x00C8) Edge/Level Status Register
Definition: component_pio.h:90
Pio::PIO_IER
__O uint32_t PIO_IER
(Pio Offset: 0x0040) Interrupt Enable Register
Definition: component_pio.h:58
Pio::PIO_PCRHR
__I uint32_t PIO_PCRHR
(Pio Offset: 0x0164) Parallel Capture Reception Holding Register
Definition: component_pio.h:109
Pio::PIO_CODR
__O uint32_t PIO_CODR
(Pio Offset: 0x0034) Clear Output Data Register
Definition: component_pio.h:55
Pio::PIO_WPSR
__I uint32_t PIO_WPSR
(Pio Offset: 0x00E8) Write Protection Status Register
Definition: component_pio.h:98
Pio::PIO_PCIMR
__I uint32_t PIO_PCIMR
(Pio Offset: 0x015C) Parallel Capture Interrupt Mask Register
Definition: component_pio.h:107
Pio::PIO_ODSR
__IO uint32_t PIO_ODSR
(Pio Offset: 0x0038) Output Data Status Register
Definition: component_pio.h:56
Pio::PIO_PDR
__O uint32_t PIO_PDR
(Pio Offset: 0x0004) PIO Disable Register
Definition: component_pio.h:43
Pio::PIO_ODR
__O uint32_t PIO_ODR
(Pio Offset: 0x0014) Output Disable Register
Definition: component_pio.h:47
Pio::PIO_PCIDR
__O uint32_t PIO_PCIDR
(Pio Offset: 0x0158) Parallel Capture Interrupt Disable Register
Definition: component_pio.h:106
Pio::PIO_AIMDR
__O uint32_t PIO_AIMDR
(Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register
Definition: component_pio.h:85
Pio::PIO_FELLSR
__O uint32_t PIO_FELLSR
(Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register
Definition: component_pio.h:92
Pio::PIO_PER
__O uint32_t PIO_PER
(Pio Offset: 0x0000) PIO Enable Register
Definition: component_pio.h:42
Pio::PIO_IFSCER
__O uint32_t PIO_IFSCER
(Pio Offset: 0x0084) Input Filter Slow Clock Enable Register
Definition: component_pio.h:73
Pio::PIO_IFSCDR
__O uint32_t PIO_IFSCDR
(Pio Offset: 0x0080) Input Filter Slow Clock Disable Register
Definition: component_pio.h:72
Pio::PIO_OER
__O uint32_t PIO_OER
(Pio Offset: 0x0010) Output Enable Register
Definition: component_pio.h:46
Pio::PIO_IFSCSR
__I uint32_t PIO_IFSCSR
(Pio Offset: 0x0088) Input Filter Slow Clock Status Register
Definition: component_pio.h:74
Pio::PIO_PPDDR
__O uint32_t PIO_PPDDR
(Pio Offset: 0x0090) Pad Pull-down Disable Register
Definition: component_pio.h:76
Pio::PIO_IFSR
__I uint32_t PIO_IFSR
(Pio Offset: 0x0028) Glitch Input Filter Status Register
Definition: component_pio.h:52
Pio::PIO_OWSR
__I uint32_t PIO_OWSR
(Pio Offset: 0x00A8) Output Write Status Register
Definition: component_pio.h:82
Pio::PIO_PUER
__O uint32_t PIO_PUER
(Pio Offset: 0x0064) Pull-up Enable Register
Definition: component_pio.h:67
Pio::PIO_OSR
__I uint32_t PIO_OSR
(Pio Offset: 0x0018) Output Status Register
Definition: component_pio.h:48
Pio::PIO_IMR
__I uint32_t PIO_IMR
(Pio Offset: 0x0048) Interrupt Mask Register
Definition: component_pio.h:60
Pio::PIO_SCHMITT
__IO uint32_t PIO_SCHMITT
(Pio Offset: 0x0100) Schmitt Trigger Register
Definition: component_pio.h:100
Pio::PIO_IFER
__O uint32_t PIO_IFER
(Pio Offset: 0x0020) Glitch Input Filter Enable Register
Definition: component_pio.h:50
Pio::PIO_FRLHSR
__I uint32_t PIO_FRLHSR
(Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register
Definition: component_pio.h:94
Pio::PIO_AIMMR
__I uint32_t PIO_AIMMR
(Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register
Definition: component_pio.h:86
Pio::PIO_MDSR
__I uint32_t PIO_MDSR
(Pio Offset: 0x0058) Multi-driver Status Register
Definition: component_pio.h:64
Pio::PIO_PSR
__I uint32_t PIO_PSR
(Pio Offset: 0x0008) PIO Status Register
Definition: component_pio.h:44
Pio::PIO_PCIER
__O uint32_t PIO_PCIER
(Pio Offset: 0x0154) Parallel Capture Interrupt Enable Register
Definition: component_pio.h:105
Pio::PIO_PUSR
__I uint32_t PIO_PUSR
(Pio Offset: 0x0068) Pad Pull-up Status Register
Definition: component_pio.h:68
Pio::PIO_MDER
__O uint32_t PIO_MDER
(Pio Offset: 0x0050) Multi-driver Enable Register
Definition: component_pio.h:62
Pio::PIO_PPDER
__O uint32_t PIO_PPDER
(Pio Offset: 0x0094) Pad Pull-down Enable Register
Definition: component_pio.h:77
Pio::PIO_IDR
__O uint32_t PIO_IDR
(Pio Offset: 0x0044) Interrupt Disable Register
Definition: component_pio.h:59
Pio::PIO_SODR
__O uint32_t PIO_SODR
(Pio Offset: 0x0030) Set Output Data Register
Definition: component_pio.h:54