RTEMS: bsps/arm/lm3s69xx/include/bsp/lm3s69xx.h File Reference

| RTEMS 5.4-rc2

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Data Structures | Macros
lm3s69xx.h File Reference
Board Support Packages » ARM » LM3S69XX » Register Definitions

Register definitions. More...

`#include <bspopts.h>`
`#include <bsp/utility.h>`

Go to the source code of this file.

## Data Structures
struct | lm3s69xx_gpio
struct | lm3s69xx_syscon
struct | lm3s69xx_uart
struct | lm3s69xx_ssi

## Macros
#define | LM3S69XX_SYSCON_BASE 0x400fe000
#define | LM3S69XX_UART_0_BASE 0x4000c000
#define | LM3S69XX_UART_1_BASE 0x4000d000
#define | LM3S69XX_UART_2_BASE 0x4000e000
#define | LM3S69XX_GPIO_A_BASE 0x40004000
#define | LM3S69XX_GPIO_B_BASE 0x40005000
#define | LM3S69XX_GPIO_C_BASE 0x40006000
#define | LM3S69XX_GPIO_D_BASE 0x40007000
#define | LM3S69XX_GPIO_E_BASE 0x40024000
#define | LM3S69XX_GPIO_F_BASE 0x40025000
#define | LM3S69XX_GPIO(port)
#define | LM3S69XX_SSI_0_BASE 0x40008000
#define | LM3S69XX_SYSCON ((volatile lm3s69xx_syscon *)LM3S69XX_SYSCON_BASE)
#define | LM3S69XX_PLL_FREQUENCY 400000000U
#define | SYSCONPBORCTL_BORIOR BSP_BIT32(1)
#define | SYSCONLDOPCTL_VADJ(val) BSP_FLD32(val, 0, 5)
#define | SYSCONLDOPCTL_VADJ_MASK BSP_MSK32(0, 5)
#define | SYSCONRIS_MOSCPUPRIS BSP_BIT32(8)
#define | SYSCONRIS_USBPLLRIS BSP_BIT32(7)
#define | SYSCONRIS_PLLLRIS BSP_BIT32(6)
#define | SYSCONRIS_BORRIS BSP_BIT32(1)
#define | SYSCONIMC_MOSCPUPIM BSP_BIT32(8)
#define | SYSCONIMC_USBPLLLIM BSP_BIT32(7)
#define | SYSCONIMC_PLLLIM BSP_BIT32(6)
#define | SYSCONIMC_BORIM BSP_BIT32(1)
#define | SYSCONMISC_MOSCPUPMIS BSP_BIT32(8)
#define | SYSCONMISC_USBPLLLMIS BSP_BIT32(7)
#define | SYSCONMISC_PLLLMIS BSP_BIT32(6)
#define | SYSCONMISC_BORMIS BSP_BIT32(1)
#define | SYSCONRESC_MOSCFAIL BSP_BIT32(16)
#define | SYSCONRESC_SW BSP_BIT32(4)
#define | SYSCONRESC_WDT BSP_BIT32(3)
#define | SYSCONRESC_BOR BSP_BIT32(2)
#define | SYSCONRESC_POR BSP_BIT32(1)
#define | SYSCONRESC_EXT BSP_BIT32(0)
#define | SYSCONRCC_AGC BSP_BIT32(27)
#define | SYSCONRCC_SYSDIV(val) BSP_FLD32(val, 23, 26)
#define | SYSCONRCC_SYSDIV_MSK BSP_MSK32(23, 26)
#define | SYSCONRCC_USESYSDIV BSP_BIT32(22)
#define | SYSCONRCC_USEPWMDIV BSP_BIT32(20)
#define | SYSCONRCC_PWMDIV(val) BSP_FLD32(val, 17, 19)
#define | SYSCONRCC_PWMDIV_DIV2_VAL 0
#define | SYSCONRCC_PWMDIV_DIV4_VAL 1
#define | SYSCONRCC_PWMDIV_DIV8_VAL 2
#define | SYSCONRCC_PWMDIV_DIV16_VAL 3
#define | SYSCONRCC_PWMDIV_DIV32_VAL 4
#define | SYSCONRCC_PWMDIV_DIV64_VAL 5
#define | SYSCONRCC_PWMDIV_MSK BSP_MSK32(17, 19)
#define | SYSCONRCC_PWRDN BSP_BIT32(13)
#define | SYSCONRCC_BYPASS BSP_BIT32(11)
#define | SYSCONRCC_XTAL(val) BSP_FLD32(val, 6, 10)
#define | SYSCONRCC_XTAL_MSK BSP_MSK32(6, 10)
#define | SYSCONRCC_OSCSRC(val) BSP_FLD32(val, 4, 5)
#define | SYSCONRCC_OSCSRC_MOSC SYSCONRCC_OSCSRC(0x0)
#define | SYSCONRCC_OSCSRC_IOSC SYSCONRCC_OSCSRC(0x1)
#define | SYSCONRCC_OSCSRC_IOSC_DIV_4 SYSCONRCC_OSCSRC(0x2)
#define | SYSCONRCC_OSCSRC_30KHZ SYSCONRCC_OSCSRC(0x3)
#define | SYSCONRCC_OSCSRC_MSK BSP_MSK32(4, 5)
#define | SYSCONRCC_IOSCDIS BSP_BIT32(1)
#define | SYSCONRCC_MOSCDIS BSP_BIT32(0)
#define | SYSCONPLLCFG_F(val) BSP_FLD32(val, 5, 13)
#define | SYSCONPLLCFG_F_MSK BSP_MSK32(5, 13)
#define | SYSCONPLLCFG_R(val) BSP_FLD32(val, 0, 4)
#define | SYSCONPLLCFG_R_MSK BSP_MSK32(0, 4)
#define | SYSCONGPIOHBCTL_PORTH BSP_BIT32(7)
#define | SYSCONGPIOHBCTL_PORTG BSP_BIT32(6)
#define | SYSCONGPIOHBCTL_PORTF BSP_BIT32(5)
#define | SYSCONGPIOHBCTL_PORTE BSP_BIT32(4)
#define | SYSCONGPIOHBCTL_PORTD BSP_BIT32(3)
#define | SYSCONGPIOHBCTL_PORTC BSP_BIT32(2)
#define | SYSCONGPIOHBCTL_PORTB BSP_BIT32(1)
#define | SYSCONGPIOHBCTL_PORTA BSP_BIT32(0)
#define | SYSCONRCC2_USERCC2 BSP_BIT32(31)
#define | SYSCONRCC2_DIV400 BSP_BIT32(30)
#define | SYSCONRCC2_SYSDIV2(val) BSP_FLD32(val, 23, 28)
#define | SYSCONRCC2_SYSDIV2_MSK BSP_MSK32(23, 28)
#define | SYSCONRCC2_SYSDIV2EXT(val) BSP_FLD32(val, 22, 28)
#define | SYSCONRCC2_SYSDIV2EXT_MSK BSP_MSK32(22, 28)
#define | SYSCONRCC2_USBPWRDN BSP_BIT32(14)
#define | SYSCONRCC2_PWRDN2 BSP_BIT32(13)
#define | SYSCONRCC2_BYPASS2 BSP_BIT32(11)
#define | SYSCONRCC2_OSCSRC2(val) BSP_FLD32(val, 4, 6)
#define | SYSCONRCC2_OSCSRC2_MSK BSP_MSK32(4, 6)
#define | SYSCONMOSCCTL_CVAL BSP_BIT32(0)
#define | SYSCONRCGC0_PWM BSP_BIT32(20)
#define | SYSCONRCGC0_ADC BSP_BIT32(16)
#define | SYSCONRCGC0_MAXADCSPD(val) BSP_FLD32(val, 8, 9)
#define | SYSCONRCGC0_MAXADCSPD_MSK BSP_MSK32(8, 9)
#define | SYSCONRCGC0_HIB BSP_BIT32(6)
#define | SYSCONRCGC0_WDT BSP_BIT32(3)
#define | SYSCONRCGC1_COMP1 BSP_BIT32(25)
#define | SYSCONRCGC1_COMP0 BSP_BIT32(24)
#define | SYSCONRCGC1_TIMER3 BSP_BIT32(19)
#define | SYSCONRCGC1_TIMER2 BSP_BIT32(18)
#define | SYSCONRCGC1_TIMER1 BSP_BIT32(17)
#define | SYSCONRCGC1_TIMER0 BSP_BIT32(16)
#define | SYSCONRCGC1_I2C1 BSP_BIT32(14)
#define | SYSCONRCGC1_I2C0 BSP_BIT32(12)
#define | SYSCONRCGC1_QEI0 BSP_BIT32(8)
#define | SYSCONRCGC1_SSI0 BSP_BIT32(4)
#define | SYSCONRCGC1_UART2 BSP_BIT32(2)
#define | SYSCONRCGC1_UART1 BSP_BIT32(1)
#define | SYSCONRCGC1_UART0 BSP_BIT32(0)
#define | SYSCONRCGC2_USB0 BSP_BIT32(16)
#define | SYSCONRCGC2_UDMA BSP_BIT32(13)
#define | SYSCONRCGC2_GPIOG BSP_BIT32(6)
#define | SYSCONRCGC2_GPIOF BSP_BIT32(5)
#define | SYSCONRCGC2_GPIOE BSP_BIT32(4)
#define | SYSCONRCGC2_GPIOD BSP_BIT32(3)
#define | SYSCONRCGC2_GPIOC BSP_BIT32(2)
#define | SYSCONRCGC2_GPIOB BSP_BIT32(1)
#define | SYSCONRCGC2_GPIOA BSP_BIT32(0)
#define | SYSCONDSLPCLKCFG_DSDIVORIDE(val) BSP_FLD32(val, 23, 28)
#define | SYSCONDSLPCLKCFG_DSDIVORIDE_MSK BSP_MSK32(23, 28)
#define | SYSCONDSLPCLKCFG_DSOSCSRC(val) BSP_FLD32(val, 4, 6)
#define | SYSCONDSLPCLKCFG_DSOSCSRC_MSK BSP_MSK32(4, 6)
#define | UARTDR_OE BSP_BIT32(11)
#define | UARTDR_BE BSP_BIT32(10)
#define | UARTDR_PE BSP_BIT32(9)
#define | UARTDR_FE BSP_BIT32(8)
#define | UARTDR_ERROR_MSK BSP_MSK32(8, 11)
#define | UARTDR_DATA(val) BSP_FLD32(val, 0, 7)
#define | UARTDR_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7)
#define | UARTFR_TXFE BSP_BIT32(7)
#define | UARTFR_RXFF BSP_BIT32(6)
#define | UARTFR_TXFF BSP_BIT32(5)
#define | UARTFR_RXFE BSP_BIT32(4)
#define | UARTFR_BUSY BSP_BIT32(3)
#define | UARTLCRH_SPS BSP_BIT32(7)
#define | UARTLCRH_WLEN(val) BSP_FLD32(val, 5, 6)
#define | UARTLCRH_FEN BSP_BIT32(4)
#define | UARTLCRH_STP2 BSP_BIT32(3)
#define | UARTLCRH_EPS BSP_BIT32(2)
#define | UARTLCRH_PEN BSP_BIT32(1)
#define | UARTLCRH_BRK BSP_BIT32(0)
#define | UARTCTL_RXE BSP_BIT32(9)
#define | UARTCTL_TXE BSP_BIT32(8)
#define | UARTCTL_LBE BSP_BIT32(7)
#define | UARTCTL_SIRLP BSP_BIT32(2)
#define | UARTCTL_SIREN BSP_BIT32(1)
#define | UARTCTL_UARTEN BSP_BIT32(0)
#define | UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5)
#define | UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2)
#define | UARTI_OE BSP_BIT32(10)
#define | UARTI_BE BSP_BIT32(9)
#define | UARTI_PE BSP_BIT32(8)
#define | UARTI_FE BSP_BIT32(7)
#define | UARTI_RT BSP_BIT32(6)
#define | UARTI_TX BSP_BIT32(5)
#define | UARTI_RX BSP_BIT32(4)
#define | SSICR0_SCR(val) BSP_FLD32(val, 8, 15)
#define | SSICR0_SPH BSP_BIT32(7)
#define | SSICR0_SPO BSP_BIT32(6)
#define | SSICR0_FRF(val) BSP_FLD32(val, 4, 5)
#define | SSICR0_DSS(val) BSP_FLD32(val, 0, 3)
#define | SSICR1_SOD BSP_BIT32(3)
#define | SSICR1_MS BSP_BIT32(2)
#define | SSICR1_SSE BSP_BIT32(1)
#define | SSICR1_LBM BSP_BIT32(0)
#define | SSISR_BSY BSP_BIT32(4)
#define | SSISR_RFF BSP_BIT32(3)
#define | SSISR_RNE BSP_BIT32(2)
#define | SSISR_TNF BSP_BIT32(1)
#define | SSISR_TFE BSP_BIT32(0)
#define | SSI_CPSRDIV(val) BSP_FLD32(val, 0, 7)
#define | SSII_TX BSP_BIT32(3)
#define | SSII_RX BSP_BIT32(2)
#define | SSII_RT BSP_BIT32(1)
#define | SSII_ROR BSP_BIT32(0)

## Detailed Description

Register definitions.

## Macro Definition Documentation

## ◆ LM3S69XX_GPIO

#define LM3S69XX_GPIO | ( |  | port | ) |

Value:
((volatile lm3s69xx_gpio *)(((port) < 4) ? \
(LM3S69XX_GPIO_A_BASE + (port) * 0x1000) : \
(LM3S69XX_GPIO_E_BASE + ((port) - 4) * 0x1000)))
lm3s69xx_gpio
Definition: lm3s69xx.h:93