RTEMS: bsps/arm/atsam/include/libchip/include/same70/component/component_pmc.h Source File

| RTEMS 5.4-rc2

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component_pmc.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAME70_PMC_COMPONENT_
31#define _SAME70_PMC_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41 typedef struct {
42 __O uint32_t PMC_SCER;
43 __O uint32_t PMC_SCDR;
44 __I uint32_t PMC_SCSR;
45 __I uint32_t Reserved1[1];
46 __O uint32_t PMC_PCER0;
47 __O uint32_t PMC_PCDR0;
48 __I uint32_t PMC_PCSR0;
49 __IO uint32_t CKGR_UCKR;
50 __IO uint32_t CKGR_MOR;
51 __IO uint32_t CKGR_MCFR;
52 __IO uint32_t CKGR_PLLAR;
53 __I uint32_t Reserved2[1];
54 __IO uint32_t PMC_MCKR;
55 __I uint32_t Reserved3[1];
56 __IO uint32_t PMC_USB;
57 __I uint32_t Reserved4[1];
58 __IO uint32_t PMC_PCK[7];
59 __I uint32_t Reserved5[1];
60 __O uint32_t PMC_IER;
61 __O uint32_t PMC_IDR;
62 __I uint32_t PMC_SR;
63 __I uint32_t PMC_IMR;
64 __IO uint32_t PMC_FSMR;
65 __IO uint32_t PMC_FSPR;
66 __O uint32_t PMC_FOCR;
67 __I uint32_t Reserved6[26];
68 __IO uint32_t PMC_WPMR;
69 __I uint32_t PMC_WPSR;
70 __I uint32_t Reserved7[5];
71 __O uint32_t PMC_PCER1;
72 __O uint32_t PMC_PCDR1;
73 __I uint32_t PMC_PCSR1;
74 __IO uint32_t PMC_PCR;
75 __IO uint32_t PMC_OCR;
76 __O uint32_t PMC_SLPWK_ER0;
77 __O uint32_t PMC_SLPWK_DR0;
78 __I uint32_t PMC_SLPWK_SR0;
79 __I uint32_t PMC_SLPWK_ASR0;
80 __I uint32_t Reserved8[3];
81 __IO uint32_t PMC_PMMR;
82 __O uint32_t PMC_SLPWK_ER1;
83 __O uint32_t PMC_SLPWK_DR1;
84 __I uint32_t PMC_SLPWK_SR1;
85 __I uint32_t PMC_SLPWK_ASR1;
86 __I uint32_t PMC_SLPWK_AIPR;
87} Pmc;
88#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
89/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
90#define PMC_SCER_USBCLK (0x1u << 5)
91#define PMC_SCER_PCK0 (0x1u << 8)
92#define PMC_SCER_PCK1 (0x1u << 9)
93#define PMC_SCER_PCK2 (0x1u << 10)
94#define PMC_SCER_PCK3 (0x1u << 11)
95#define PMC_SCER_PCK4 (0x1u << 12)
96#define PMC_SCER_PCK5 (0x1u << 13)
97#define PMC_SCER_PCK6 (0x1u << 14)
98/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
99#define PMC_SCDR_USBCLK (0x1u << 5)
100#define PMC_SCDR_PCK0 (0x1u << 8)
101#define PMC_SCDR_PCK1 (0x1u << 9)
102#define PMC_SCDR_PCK2 (0x1u << 10)
103#define PMC_SCDR_PCK3 (0x1u << 11)
104#define PMC_SCDR_PCK4 (0x1u << 12)
105#define PMC_SCDR_PCK5 (0x1u << 13)
106#define PMC_SCDR_PCK6 (0x1u << 14)
107/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
108#define PMC_SCSR_USBCLK (0x1u << 5)
109#define PMC_SCSR_PCK0 (0x1u << 8)
110#define PMC_SCSR_PCK1 (0x1u << 9)
111#define PMC_SCSR_PCK2 (0x1u << 10)
112#define PMC_SCSR_PCK3 (0x1u << 11)
113#define PMC_SCSR_PCK4 (0x1u << 12)
114#define PMC_SCSR_PCK5 (0x1u << 13)
115#define PMC_SCSR_PCK6 (0x1u << 14)
116/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
117#define PMC_PCER0_PID7 (0x1u << 7)
118#define PMC_PCER0_PID8 (0x1u << 8)
119#define PMC_PCER0_PID9 (0x1u << 9)
120#define PMC_PCER0_PID10 (0x1u << 10)
121#define PMC_PCER0_PID11 (0x1u << 11)
122#define PMC_PCER0_PID12 (0x1u << 12)
123#define PMC_PCER0_PID13 (0x1u << 13)
124#define PMC_PCER0_PID14 (0x1u << 14)
125#define PMC_PCER0_PID15 (0x1u << 15)
126#define PMC_PCER0_PID16 (0x1u << 16)
127#define PMC_PCER0_PID17 (0x1u << 17)
128#define PMC_PCER0_PID18 (0x1u << 18)
129#define PMC_PCER0_PID19 (0x1u << 19)
130#define PMC_PCER0_PID20 (0x1u << 20)
131#define PMC_PCER0_PID21 (0x1u << 21)
132#define PMC_PCER0_PID22 (0x1u << 22)
133#define PMC_PCER0_PID23 (0x1u << 23)
134#define PMC_PCER0_PID24 (0x1u << 24)
135#define PMC_PCER0_PID25 (0x1u << 25)
136#define PMC_PCER0_PID26 (0x1u << 26)
137#define PMC_PCER0_PID27 (0x1u << 27)
138#define PMC_PCER0_PID28 (0x1u << 28)
139#define PMC_PCER0_PID29 (0x1u << 29)
140#define PMC_PCER0_PID30 (0x1u << 30)
141#define PMC_PCER0_PID31 (0x1u << 31)
142/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
143#define PMC_PCDR0_PID7 (0x1u << 7)
144#define PMC_PCDR0_PID8 (0x1u << 8)
145#define PMC_PCDR0_PID9 (0x1u << 9)
146#define PMC_PCDR0_PID10 (0x1u << 10)
147#define PMC_PCDR0_PID11 (0x1u << 11)
148#define PMC_PCDR0_PID12 (0x1u << 12)
149#define PMC_PCDR0_PID13 (0x1u << 13)
150#define PMC_PCDR0_PID14 (0x1u << 14)
151#define PMC_PCDR0_PID15 (0x1u << 15)
152#define PMC_PCDR0_PID16 (0x1u << 16)
153#define PMC_PCDR0_PID17 (0x1u << 17)
154#define PMC_PCDR0_PID18 (0x1u << 18)
155#define PMC_PCDR0_PID19 (0x1u << 19)
156#define PMC_PCDR0_PID20 (0x1u << 20)
157#define PMC_PCDR0_PID21 (0x1u << 21)
158#define PMC_PCDR0_PID22 (0x1u << 22)
159#define PMC_PCDR0_PID23 (0x1u << 23)
160#define PMC_PCDR0_PID24 (0x1u << 24)
161#define PMC_PCDR0_PID25 (0x1u << 25)
162#define PMC_PCDR0_PID26 (0x1u << 26)
163#define PMC_PCDR0_PID27 (0x1u << 27)
164#define PMC_PCDR0_PID28 (0x1u << 28)
165#define PMC_PCDR0_PID29 (0x1u << 29)
166#define PMC_PCDR0_PID30 (0x1u << 30)
167#define PMC_PCDR0_PID31 (0x1u << 31)
168/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
169#define PMC_PCSR0_PID7 (0x1u << 7)
170#define PMC_PCSR0_PID8 (0x1u << 8)
171#define PMC_PCSR0_PID9 (0x1u << 9)
172#define PMC_PCSR0_PID10 (0x1u << 10)
173#define PMC_PCSR0_PID11 (0x1u << 11)
174#define PMC_PCSR0_PID12 (0x1u << 12)
175#define PMC_PCSR0_PID13 (0x1u << 13)
176#define PMC_PCSR0_PID14 (0x1u << 14)
177#define PMC_PCSR0_PID15 (0x1u << 15)
178#define PMC_PCSR0_PID16 (0x1u << 16)
179#define PMC_PCSR0_PID17 (0x1u << 17)
180#define PMC_PCSR0_PID18 (0x1u << 18)
181#define PMC_PCSR0_PID19 (0x1u << 19)
182#define PMC_PCSR0_PID20 (0x1u << 20)
183#define PMC_PCSR0_PID21 (0x1u << 21)
184#define PMC_PCSR0_PID22 (0x1u << 22)
185#define PMC_PCSR0_PID23 (0x1u << 23)
186#define PMC_PCSR0_PID24 (0x1u << 24)
187#define PMC_PCSR0_PID25 (0x1u << 25)
188#define PMC_PCSR0_PID26 (0x1u << 26)
189#define PMC_PCSR0_PID27 (0x1u << 27)
190#define PMC_PCSR0_PID28 (0x1u << 28)
191#define PMC_PCSR0_PID29 (0x1u << 29)
192#define PMC_PCSR0_PID30 (0x1u << 30)
193#define PMC_PCSR0_PID31 (0x1u << 31)
194/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
195#define CKGR_UCKR_UPLLEN (0x1u << 16)
196#define CKGR_UCKR_UPLLCOUNT_Pos 20
197#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos)
198#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
199/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
200#define CKGR_MOR_MOSCXTEN (0x1u << 0)
201#define CKGR_MOR_MOSCXTBY (0x1u << 1)
202#define CKGR_MOR_WAITMODE (0x1u << 2)
203#define CKGR_MOR_MOSCRCEN (0x1u << 3)
204#define CKGR_MOR_MOSCRCF_Pos 4
205#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos)
206#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos)))
207#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4)
208#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4)
209#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4)
210#define CKGR_MOR_MOSCXTST_Pos 8
211#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos)
212#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
213#define CKGR_MOR_KEY_Pos 16
214#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos)
215#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
216#define CKGR_MOR_KEY_PASSWD (0x37u << 16)
217#define CKGR_MOR_MOSCSEL (0x1u << 24)
218#define CKGR_MOR_CFDEN (0x1u << 25)
219#define CKGR_MOR_XT32KFME (0x1u << 26)
220/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
221#define CKGR_MCFR_MAINF_Pos 0
222#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos)
223#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))
224#define CKGR_MCFR_MAINFRDY (0x1u << 16)
225#define CKGR_MCFR_RCMEAS (0x1u << 20)
226#define CKGR_MCFR_CCSS (0x1u << 24)
227/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
228#define CKGR_PLLAR_DIVA_Pos 0
229#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos)
230#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
231#define CKGR_PLLAR_DIVA_0 (0x0u << 0)
232#define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0)
233#define CKGR_PLLAR_PLLACOUNT_Pos 8
234#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos)
235#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
236#define CKGR_PLLAR_MULA_Pos 16
237#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos)
238#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
239#define CKGR_PLLAR_ONE (0x1u << 29)
240/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
241#define PMC_MCKR_CSS_Pos 0
242#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos)
243#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)))
244#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0)
245#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0)
246#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0)
247#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0)
248#define PMC_MCKR_PRES_Pos 4
249#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos)
250#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)))
251#define PMC_MCKR_PRES_CLK_1 (0x0u << 4)
252#define PMC_MCKR_PRES_CLK_2 (0x1u << 4)
253#define PMC_MCKR_PRES_CLK_4 (0x2u << 4)
254#define PMC_MCKR_PRES_CLK_8 (0x3u << 4)
255#define PMC_MCKR_PRES_CLK_16 (0x4u << 4)
256#define PMC_MCKR_PRES_CLK_32 (0x5u << 4)
257#define PMC_MCKR_PRES_CLK_64 (0x6u << 4)
258#define PMC_MCKR_PRES_CLK_3 (0x7u << 4)
259#define PMC_MCKR_MDIV_Pos 8
260#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos)
261#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos)))
262#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8)
263#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8)
264#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8)
265#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8)
266#define PMC_MCKR_UPLLDIV2 (0x1u << 13)
267/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
268#define PMC_USB_USBS (0x1u << 0)
269#define PMC_USB_USBDIV_Pos 8
270#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos)
271#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
272/* -------- PMC_PCK[7] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
273#define PMC_PCK_CSS_Pos 0
274#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos)
275#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)))
276#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0)
277#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0)
278#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0)
279#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0)
280#define PMC_PCK_CSS_MCK (0x4u << 0)
281#define PMC_PCK_PRES_Pos 4
282#define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos)
283#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))
284/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
285#define PMC_IER_MOSCXTS (0x1u << 0)
286#define PMC_IER_LOCKA (0x1u << 1)
287#define PMC_IER_MCKRDY (0x1u << 3)
288#define PMC_IER_LOCKU (0x1u << 6)
289#define PMC_IER_PCKRDY0 (0x1u << 8)
290#define PMC_IER_PCKRDY1 (0x1u << 9)
291#define PMC_IER_PCKRDY2 (0x1u << 10)
292#define PMC_IER_PCKRDY3 (0x1u << 11)
293#define PMC_IER_PCKRDY4 (0x1u << 12)
294#define PMC_IER_PCKRDY5 (0x1u << 13)
295#define PMC_IER_PCKRDY6 (0x1u << 14)
296#define PMC_IER_MOSCSELS (0x1u << 16)
297#define PMC_IER_MOSCRCS (0x1u << 17)
298#define PMC_IER_CFDEV (0x1u << 18)
299#define PMC_IER_XT32KERR (0x1u << 21)
300/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
301#define PMC_IDR_MOSCXTS (0x1u << 0)
302#define PMC_IDR_LOCKA (0x1u << 1)
303#define PMC_IDR_MCKRDY (0x1u << 3)
304#define PMC_IDR_LOCKU (0x1u << 6)
305#define PMC_IDR_PCKRDY0 (0x1u << 8)
306#define PMC_IDR_PCKRDY1 (0x1u << 9)
307#define PMC_IDR_PCKRDY2 (0x1u << 10)
308#define PMC_IDR_PCKRDY3 (0x1u << 11)
309#define PMC_IDR_PCKRDY4 (0x1u << 12)
310#define PMC_IDR_PCKRDY5 (0x1u << 13)
311#define PMC_IDR_PCKRDY6 (0x1u << 14)
312#define PMC_IDR_MOSCSELS (0x1u << 16)
313#define PMC_IDR_MOSCRCS (0x1u << 17)
314#define PMC_IDR_CFDEV (0x1u << 18)
315#define PMC_IDR_XT32KERR (0x1u << 21)
316/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
317#define PMC_SR_MOSCXTS (0x1u << 0)
318#define PMC_SR_LOCKA (0x1u << 1)
319#define PMC_SR_MCKRDY (0x1u << 3)
320#define PMC_SR_LOCKU (0x1u << 6)
321#define PMC_SR_OSCSELS (0x1u << 7)
322#define PMC_SR_PCKRDY0 (0x1u << 8)
323#define PMC_SR_PCKRDY1 (0x1u << 9)
324#define PMC_SR_PCKRDY2 (0x1u << 10)
325#define PMC_SR_PCKRDY3 (0x1u << 11)
326#define PMC_SR_PCKRDY4 (0x1u << 12)
327#define PMC_SR_PCKRDY5 (0x1u << 13)
328#define PMC_SR_PCKRDY6 (0x1u << 14)
329#define PMC_SR_MOSCSELS (0x1u << 16)
330#define PMC_SR_MOSCRCS (0x1u << 17)
331#define PMC_SR_CFDEV (0x1u << 18)
332#define PMC_SR_CFDS (0x1u << 19)
333#define PMC_SR_FOS (0x1u << 20)
334#define PMC_SR_XT32KERR (0x1u << 21)
335/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
336#define PMC_IMR_MOSCXTS (0x1u << 0)
337#define PMC_IMR_LOCKA (0x1u << 1)
338#define PMC_IMR_MCKRDY (0x1u << 3)
339#define PMC_IMR_LOCKU (0x1u << 6)
340#define PMC_IMR_PCKRDY0 (0x1u << 8)
341#define PMC_IMR_PCKRDY1 (0x1u << 9)
342#define PMC_IMR_PCKRDY2 (0x1u << 10)
343#define PMC_IMR_PCKRDY3 (0x1u << 11)
344#define PMC_IMR_PCKRDY4 (0x1u << 12)
345#define PMC_IMR_PCKRDY5 (0x1u << 13)
346#define PMC_IMR_PCKRDY6 (0x1u << 14)
347#define PMC_IMR_MOSCSELS (0x1u << 16)
348#define PMC_IMR_MOSCRCS (0x1u << 17)
349#define PMC_IMR_CFDEV (0x1u << 18)
350#define PMC_IMR_XT32KERR (0x1u << 21)
351/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
352#define PMC_FSMR_FSTT0 (0x1u << 0)
353#define PMC_FSMR_FSTT1 (0x1u << 1)
354#define PMC_FSMR_FSTT2 (0x1u << 2)
355#define PMC_FSMR_FSTT3 (0x1u << 3)
356#define PMC_FSMR_FSTT4 (0x1u << 4)
357#define PMC_FSMR_FSTT5 (0x1u << 5)
358#define PMC_FSMR_FSTT6 (0x1u << 6)
359#define PMC_FSMR_FSTT7 (0x1u << 7)
360#define PMC_FSMR_FSTT8 (0x1u << 8)
361#define PMC_FSMR_FSTT9 (0x1u << 9)
362#define PMC_FSMR_FSTT10 (0x1u << 10)
363#define PMC_FSMR_FSTT11 (0x1u << 11)
364#define PMC_FSMR_FSTT12 (0x1u << 12)
365#define PMC_FSMR_FSTT13 (0x1u << 13)
366#define PMC_FSMR_FSTT14 (0x1u << 14)
367#define PMC_FSMR_FSTT15 (0x1u << 15)
368#define PMC_FSMR_RTTAL (0x1u << 16)
369#define PMC_FSMR_RTCAL (0x1u << 17)
370#define PMC_FSMR_USBAL (0x1u << 18)
371#define PMC_FSMR_LPM (0x1u << 20)
372#define PMC_FSMR_FLPM_Pos 21
373#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos)
374#define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos)))
375#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21)
376#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21)
377#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21)
378#define PMC_FSMR_FFLPM (0x1u << 23)
379/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
380#define PMC_FSPR_FSTP0 (0x1u << 0)
381#define PMC_FSPR_FSTP1 (0x1u << 1)
382#define PMC_FSPR_FSTP2 (0x1u << 2)
383#define PMC_FSPR_FSTP3 (0x1u << 3)
384#define PMC_FSPR_FSTP4 (0x1u << 4)
385#define PMC_FSPR_FSTP5 (0x1u << 5)
386#define PMC_FSPR_FSTP6 (0x1u << 6)
387#define PMC_FSPR_FSTP7 (0x1u << 7)
388#define PMC_FSPR_FSTP8 (0x1u << 8)
389#define PMC_FSPR_FSTP9 (0x1u << 9)
390#define PMC_FSPR_FSTP10 (0x1u << 10)
391#define PMC_FSPR_FSTP11 (0x1u << 11)
392#define PMC_FSPR_FSTP12 (0x1u << 12)
393#define PMC_FSPR_FSTP13 (0x1u << 13)
394#define PMC_FSPR_FSTP14 (0x1u << 14)
395#define PMC_FSPR_FSTP15 (0x1u << 15)
396/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
397#define PMC_FOCR_FOCLR (0x1u << 0)
398/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */
399#define PMC_WPMR_WPEN (0x1u << 0)
400#define PMC_WPMR_WPKEY_Pos 8
401#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos)
402#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
403#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8)
404/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */
405#define PMC_WPSR_WPVS (0x1u << 0)
406#define PMC_WPSR_WPVSRC_Pos 8
407#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos)
408/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
409#define PMC_PCER1_PID32 (0x1u << 0)
410#define PMC_PCER1_PID33 (0x1u << 1)
411#define PMC_PCER1_PID34 (0x1u << 2)
412#define PMC_PCER1_PID35 (0x1u << 3)
413#define PMC_PCER1_PID37 (0x1u << 5)
414#define PMC_PCER1_PID39 (0x1u << 7)
415#define PMC_PCER1_PID40 (0x1u << 8)
416#define PMC_PCER1_PID41 (0x1u << 9)
417#define PMC_PCER1_PID42 (0x1u << 10)
418#define PMC_PCER1_PID43 (0x1u << 11)
419#define PMC_PCER1_PID44 (0x1u << 12)
420#define PMC_PCER1_PID45 (0x1u << 13)
421#define PMC_PCER1_PID46 (0x1u << 14)
422#define PMC_PCER1_PID47 (0x1u << 15)
423#define PMC_PCER1_PID48 (0x1u << 16)
424#define PMC_PCER1_PID49 (0x1u << 17)
425#define PMC_PCER1_PID50 (0x1u << 18)
426#define PMC_PCER1_PID51 (0x1u << 19)
427#define PMC_PCER1_PID52 (0x1u << 20)
428#define PMC_PCER1_PID53 (0x1u << 21)
429#define PMC_PCER1_PID56 (0x1u << 24)
430#define PMC_PCER1_PID57 (0x1u << 25)
431#define PMC_PCER1_PID58 (0x1u << 26)
432#define PMC_PCER1_PID59 (0x1u << 27)
433#define PMC_PCER1_PID60 (0x1u << 28)
434/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
435#define PMC_PCDR1_PID32 (0x1u << 0)
436#define PMC_PCDR1_PID33 (0x1u << 1)
437#define PMC_PCDR1_PID34 (0x1u << 2)
438#define PMC_PCDR1_PID35 (0x1u << 3)
439#define PMC_PCDR1_PID37 (0x1u << 5)
440#define PMC_PCDR1_PID39 (0x1u << 7)
441#define PMC_PCDR1_PID40 (0x1u << 8)
442#define PMC_PCDR1_PID41 (0x1u << 9)
443#define PMC_PCDR1_PID42 (0x1u << 10)
444#define PMC_PCDR1_PID43 (0x1u << 11)
445#define PMC_PCDR1_PID44 (0x1u << 12)
446#define PMC_PCDR1_PID45 (0x1u << 13)
447#define PMC_PCDR1_PID46 (0x1u << 14)
448#define PMC_PCDR1_PID47 (0x1u << 15)
449#define PMC_PCDR1_PID48 (0x1u << 16)
450#define PMC_PCDR1_PID49 (0x1u << 17)
451#define PMC_PCDR1_PID50 (0x1u << 18)
452#define PMC_PCDR1_PID51 (0x1u << 19)
453#define PMC_PCDR1_PID52 (0x1u << 20)
454#define PMC_PCDR1_PID53 (0x1u << 21)
455#define PMC_PCDR1_PID56 (0x1u << 24)
456#define PMC_PCDR1_PID57 (0x1u << 25)
457#define PMC_PCDR1_PID58 (0x1u << 26)
458#define PMC_PCDR1_PID59 (0x1u << 27)
459#define PMC_PCDR1_PID60 (0x1u << 28)
460/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
461#define PMC_PCSR1_PID32 (0x1u << 0)
462#define PMC_PCSR1_PID33 (0x1u << 1)
463#define PMC_PCSR1_PID34 (0x1u << 2)
464#define PMC_PCSR1_PID35 (0x1u << 3)
465#define PMC_PCSR1_PID37 (0x1u << 5)
466#define PMC_PCSR1_PID39 (0x1u << 7)
467#define PMC_PCSR1_PID40 (0x1u << 8)
468#define PMC_PCSR1_PID41 (0x1u << 9)
469#define PMC_PCSR1_PID42 (0x1u << 10)
470#define PMC_PCSR1_PID43 (0x1u << 11)
471#define PMC_PCSR1_PID44 (0x1u << 12)
472#define PMC_PCSR1_PID45 (0x1u << 13)
473#define PMC_PCSR1_PID46 (0x1u << 14)
474#define PMC_PCSR1_PID47 (0x1u << 15)
475#define PMC_PCSR1_PID48 (0x1u << 16)
476#define PMC_PCSR1_PID49 (0x1u << 17)
477#define PMC_PCSR1_PID50 (0x1u << 18)
478#define PMC_PCSR1_PID51 (0x1u << 19)
479#define PMC_PCSR1_PID52 (0x1u << 20)
480#define PMC_PCSR1_PID53 (0x1u << 21)
481#define PMC_PCSR1_PID56 (0x1u << 24)
482#define PMC_PCSR1_PID57 (0x1u << 25)
483#define PMC_PCSR1_PID58 (0x1u << 26)
484#define PMC_PCSR1_PID59 (0x1u << 27)
485#define PMC_PCSR1_PID60 (0x1u << 28)
486/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */
487#define PMC_PCR_PID_Pos 0
488#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos)
489#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))
490#define PMC_PCR_CMD (0x1u << 12)
491#define PMC_PCR_EN (0x1u << 28)
492/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
493#define PMC_OCR_CAL4_Pos 0
494#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos)
495#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))
496#define PMC_OCR_SEL4 (0x1u << 7)
497#define PMC_OCR_CAL8_Pos 8
498#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos)
499#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
500#define PMC_OCR_SEL8 (0x1u << 15)
501#define PMC_OCR_CAL12_Pos 16
502#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos)
503#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))
504#define PMC_OCR_SEL12 (0x1u << 23)
505/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */
506#define PMC_SLPWK_ER0_PID7 (0x1u << 7)
507#define PMC_SLPWK_ER0_PID8 (0x1u << 8)
508#define PMC_SLPWK_ER0_PID9 (0x1u << 9)
509#define PMC_SLPWK_ER0_PID10 (0x1u << 10)
510#define PMC_SLPWK_ER0_PID11 (0x1u << 11)
511#define PMC_SLPWK_ER0_PID12 (0x1u << 12)
512#define PMC_SLPWK_ER0_PID13 (0x1u << 13)
513#define PMC_SLPWK_ER0_PID14 (0x1u << 14)
514#define PMC_SLPWK_ER0_PID15 (0x1u << 15)
515#define PMC_SLPWK_ER0_PID16 (0x1u << 16)
516#define PMC_SLPWK_ER0_PID17 (0x1u << 17)
517#define PMC_SLPWK_ER0_PID18 (0x1u << 18)
518#define PMC_SLPWK_ER0_PID19 (0x1u << 19)
519#define PMC_SLPWK_ER0_PID20 (0x1u << 20)
520#define PMC_SLPWK_ER0_PID21 (0x1u << 21)
521#define PMC_SLPWK_ER0_PID22 (0x1u << 22)
522#define PMC_SLPWK_ER0_PID23 (0x1u << 23)
523#define PMC_SLPWK_ER0_PID24 (0x1u << 24)
524#define PMC_SLPWK_ER0_PID25 (0x1u << 25)
525#define PMC_SLPWK_ER0_PID26 (0x1u << 26)
526#define PMC_SLPWK_ER0_PID27 (0x1u << 27)
527#define PMC_SLPWK_ER0_PID28 (0x1u << 28)
528#define PMC_SLPWK_ER0_PID29 (0x1u << 29)
529#define PMC_SLPWK_ER0_PID30 (0x1u << 30)
530#define PMC_SLPWK_ER0_PID31 (0x1u << 31)
531/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */
532#define PMC_SLPWK_DR0_PID7 (0x1u << 7)
533#define PMC_SLPWK_DR0_PID8 (0x1u << 8)
534#define PMC_SLPWK_DR0_PID9 (0x1u << 9)
535#define PMC_SLPWK_DR0_PID10 (0x1u << 10)
536#define PMC_SLPWK_DR0_PID11 (0x1u << 11)
537#define PMC_SLPWK_DR0_PID12 (0x1u << 12)
538#define PMC_SLPWK_DR0_PID13 (0x1u << 13)
539#define PMC_SLPWK_DR0_PID14 (0x1u << 14)
540#define PMC_SLPWK_DR0_PID15 (0x1u << 15)
541#define PMC_SLPWK_DR0_PID16 (0x1u << 16)
542#define PMC_SLPWK_DR0_PID17 (0x1u << 17)
543#define PMC_SLPWK_DR0_PID18 (0x1u << 18)
544#define PMC_SLPWK_DR0_PID19 (0x1u << 19)
545#define PMC_SLPWK_DR0_PID20 (0x1u << 20)
546#define PMC_SLPWK_DR0_PID21 (0x1u << 21)
547#define PMC_SLPWK_DR0_PID22 (0x1u << 22)
548#define PMC_SLPWK_DR0_PID23 (0x1u << 23)
549#define PMC_SLPWK_DR0_PID24 (0x1u << 24)
550#define PMC_SLPWK_DR0_PID25 (0x1u << 25)
551#define PMC_SLPWK_DR0_PID26 (0x1u << 26)
552#define PMC_SLPWK_DR0_PID27 (0x1u << 27)
553#define PMC_SLPWK_DR0_PID28 (0x1u << 28)
554#define PMC_SLPWK_DR0_PID29 (0x1u << 29)
555#define PMC_SLPWK_DR0_PID30 (0x1u << 30)
556#define PMC_SLPWK_DR0_PID31 (0x1u << 31)
557/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */
558#define PMC_SLPWK_SR0_PID7 (0x1u << 7)
559#define PMC_SLPWK_SR0_PID8 (0x1u << 8)
560#define PMC_SLPWK_SR0_PID9 (0x1u << 9)
561#define PMC_SLPWK_SR0_PID10 (0x1u << 10)
562#define PMC_SLPWK_SR0_PID11 (0x1u << 11)
563#define PMC_SLPWK_SR0_PID12 (0x1u << 12)
564#define PMC_SLPWK_SR0_PID13 (0x1u << 13)
565#define PMC_SLPWK_SR0_PID14 (0x1u << 14)
566#define PMC_SLPWK_SR0_PID15 (0x1u << 15)
567#define PMC_SLPWK_SR0_PID16 (0x1u << 16)
568#define PMC_SLPWK_SR0_PID17 (0x1u << 17)
569#define PMC_SLPWK_SR0_PID18 (0x1u << 18)
570#define PMC_SLPWK_SR0_PID19 (0x1u << 19)
571#define PMC_SLPWK_SR0_PID20 (0x1u << 20)
572#define PMC_SLPWK_SR0_PID21 (0x1u << 21)
573#define PMC_SLPWK_SR0_PID22 (0x1u << 22)
574#define PMC_SLPWK_SR0_PID23 (0x1u << 23)
575#define PMC_SLPWK_SR0_PID24 (0x1u << 24)
576#define PMC_SLPWK_SR0_PID25 (0x1u << 25)
577#define PMC_SLPWK_SR0_PID26 (0x1u << 26)
578#define PMC_SLPWK_SR0_PID27 (0x1u << 27)
579#define PMC_SLPWK_SR0_PID28 (0x1u << 28)
580#define PMC_SLPWK_SR0_PID29 (0x1u << 29)
581#define PMC_SLPWK_SR0_PID30 (0x1u << 30)
582#define PMC_SLPWK_SR0_PID31 (0x1u << 31)
583/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */
584#define PMC_SLPWK_ASR0_PID7 (0x1u << 7)
585#define PMC_SLPWK_ASR0_PID8 (0x1u << 8)
586#define PMC_SLPWK_ASR0_PID9 (0x1u << 9)
587#define PMC_SLPWK_ASR0_PID10 (0x1u << 10)
588#define PMC_SLPWK_ASR0_PID11 (0x1u << 11)
589#define PMC_SLPWK_ASR0_PID12 (0x1u << 12)
590#define PMC_SLPWK_ASR0_PID13 (0x1u << 13)
591#define PMC_SLPWK_ASR0_PID14 (0x1u << 14)
592#define PMC_SLPWK_ASR0_PID15 (0x1u << 15)
593#define PMC_SLPWK_ASR0_PID16 (0x1u << 16)
594#define PMC_SLPWK_ASR0_PID17 (0x1u << 17)
595#define PMC_SLPWK_ASR0_PID18 (0x1u << 18)
596#define PMC_SLPWK_ASR0_PID19 (0x1u << 19)
597#define PMC_SLPWK_ASR0_PID20 (0x1u << 20)
598#define PMC_SLPWK_ASR0_PID21 (0x1u << 21)
599#define PMC_SLPWK_ASR0_PID22 (0x1u << 22)
600#define PMC_SLPWK_ASR0_PID23 (0x1u << 23)
601#define PMC_SLPWK_ASR0_PID24 (0x1u << 24)
602#define PMC_SLPWK_ASR0_PID25 (0x1u << 25)
603#define PMC_SLPWK_ASR0_PID26 (0x1u << 26)
604#define PMC_SLPWK_ASR0_PID27 (0x1u << 27)
605#define PMC_SLPWK_ASR0_PID28 (0x1u << 28)
606#define PMC_SLPWK_ASR0_PID29 (0x1u << 29)
607#define PMC_SLPWK_ASR0_PID30 (0x1u << 30)
608#define PMC_SLPWK_ASR0_PID31 (0x1u << 31)
609/* -------- PMC_PMMR : (PMC Offset: 0x0130) PLL Maximum Multiplier Value Register -------- */
610#define PMC_PMMR_PLLA_MMAX_Pos 0
611#define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos)
612#define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos)))
613/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */
614#define PMC_SLPWK_ER1_PID32 (0x1u << 0)
615#define PMC_SLPWK_ER1_PID33 (0x1u << 1)
616#define PMC_SLPWK_ER1_PID34 (0x1u << 2)
617#define PMC_SLPWK_ER1_PID35 (0x1u << 3)
618#define PMC_SLPWK_ER1_PID37 (0x1u << 5)
619#define PMC_SLPWK_ER1_PID39 (0x1u << 7)
620#define PMC_SLPWK_ER1_PID40 (0x1u << 8)
621#define PMC_SLPWK_ER1_PID41 (0x1u << 9)
622#define PMC_SLPWK_ER1_PID42 (0x1u << 10)
623#define PMC_SLPWK_ER1_PID43 (0x1u << 11)
624#define PMC_SLPWK_ER1_PID44 (0x1u << 12)
625#define PMC_SLPWK_ER1_PID45 (0x1u << 13)
626#define PMC_SLPWK_ER1_PID46 (0x1u << 14)
627#define PMC_SLPWK_ER1_PID47 (0x1u << 15)
628#define PMC_SLPWK_ER1_PID48 (0x1u << 16)
629#define PMC_SLPWK_ER1_PID49 (0x1u << 17)
630#define PMC_SLPWK_ER1_PID50 (0x1u << 18)
631#define PMC_SLPWK_ER1_PID51 (0x1u << 19)
632#define PMC_SLPWK_ER1_PID52 (0x1u << 20)
633#define PMC_SLPWK_ER1_PID53 (0x1u << 21)
634#define PMC_SLPWK_ER1_PID56 (0x1u << 24)
635#define PMC_SLPWK_ER1_PID57 (0x1u << 25)
636#define PMC_SLPWK_ER1_PID58 (0x1u << 26)
637#define PMC_SLPWK_ER1_PID59 (0x1u << 27)
638#define PMC_SLPWK_ER1_PID60 (0x1u << 28)
639/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */
640#define PMC_SLPWK_DR1_PID32 (0x1u << 0)
641#define PMC_SLPWK_DR1_PID33 (0x1u << 1)
642#define PMC_SLPWK_DR1_PID34 (0x1u << 2)
643#define PMC_SLPWK_DR1_PID35 (0x1u << 3)
644#define PMC_SLPWK_DR1_PID37 (0x1u << 5)
645#define PMC_SLPWK_DR1_PID39 (0x1u << 7)
646#define PMC_SLPWK_DR1_PID40 (0x1u << 8)
647#define PMC_SLPWK_DR1_PID41 (0x1u << 9)
648#define PMC_SLPWK_DR1_PID42 (0x1u << 10)
649#define PMC_SLPWK_DR1_PID43 (0x1u << 11)
650#define PMC_SLPWK_DR1_PID44 (0x1u << 12)
651#define PMC_SLPWK_DR1_PID45 (0x1u << 13)
652#define PMC_SLPWK_DR1_PID46 (0x1u << 14)
653#define PMC_SLPWK_DR1_PID47 (0x1u << 15)
654#define PMC_SLPWK_DR1_PID48 (0x1u << 16)
655#define PMC_SLPWK_DR1_PID49 (0x1u << 17)
656#define PMC_SLPWK_DR1_PID50 (0x1u << 18)
657#define PMC_SLPWK_DR1_PID51 (0x1u << 19)
658#define PMC_SLPWK_DR1_PID52 (0x1u << 20)
659#define PMC_SLPWK_DR1_PID53 (0x1u << 21)
660#define PMC_SLPWK_DR1_PID56 (0x1u << 24)
661#define PMC_SLPWK_DR1_PID57 (0x1u << 25)
662#define PMC_SLPWK_DR1_PID58 (0x1u << 26)
663#define PMC_SLPWK_DR1_PID59 (0x1u << 27)
664#define PMC_SLPWK_DR1_PID60 (0x1u << 28)
665/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */
666#define PMC_SLPWK_SR1_PID32 (0x1u << 0)
667#define PMC_SLPWK_SR1_PID33 (0x1u << 1)
668#define PMC_SLPWK_SR1_PID34 (0x1u << 2)
669#define PMC_SLPWK_SR1_PID35 (0x1u << 3)
670#define PMC_SLPWK_SR1_PID37 (0x1u << 5)
671#define PMC_SLPWK_SR1_PID39 (0x1u << 7)
672#define PMC_SLPWK_SR1_PID40 (0x1u << 8)
673#define PMC_SLPWK_SR1_PID41 (0x1u << 9)
674#define PMC_SLPWK_SR1_PID42 (0x1u << 10)
675#define PMC_SLPWK_SR1_PID43 (0x1u << 11)
676#define PMC_SLPWK_SR1_PID44 (0x1u << 12)
677#define PMC_SLPWK_SR1_PID45 (0x1u << 13)
678#define PMC_SLPWK_SR1_PID46 (0x1u << 14)
679#define PMC_SLPWK_SR1_PID47 (0x1u << 15)
680#define PMC_SLPWK_SR1_PID48 (0x1u << 16)
681#define PMC_SLPWK_SR1_PID49 (0x1u << 17)
682#define PMC_SLPWK_SR1_PID50 (0x1u << 18)
683#define PMC_SLPWK_SR1_PID51 (0x1u << 19)
684#define PMC_SLPWK_SR1_PID52 (0x1u << 20)
685#define PMC_SLPWK_SR1_PID53 (0x1u << 21)
686#define PMC_SLPWK_SR1_PID56 (0x1u << 24)
687#define PMC_SLPWK_SR1_PID57 (0x1u << 25)
688#define PMC_SLPWK_SR1_PID58 (0x1u << 26)
689#define PMC_SLPWK_SR1_PID59 (0x1u << 27)
690#define PMC_SLPWK_SR1_PID60 (0x1u << 28)
691/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */
692#define PMC_SLPWK_ASR1_PID32 (0x1u << 0)
693#define PMC_SLPWK_ASR1_PID33 (0x1u << 1)
694#define PMC_SLPWK_ASR1_PID34 (0x1u << 2)
695#define PMC_SLPWK_ASR1_PID35 (0x1u << 3)
696#define PMC_SLPWK_ASR1_PID37 (0x1u << 5)
697#define PMC_SLPWK_ASR1_PID39 (0x1u << 7)
698#define PMC_SLPWK_ASR1_PID40 (0x1u << 8)
699#define PMC_SLPWK_ASR1_PID41 (0x1u << 9)
700#define PMC_SLPWK_ASR1_PID42 (0x1u << 10)
701#define PMC_SLPWK_ASR1_PID43 (0x1u << 11)
702#define PMC_SLPWK_ASR1_PID44 (0x1u << 12)
703#define PMC_SLPWK_ASR1_PID45 (0x1u << 13)
704#define PMC_SLPWK_ASR1_PID46 (0x1u << 14)
705#define PMC_SLPWK_ASR1_PID47 (0x1u << 15)
706#define PMC_SLPWK_ASR1_PID48 (0x1u << 16)
707#define PMC_SLPWK_ASR1_PID49 (0x1u << 17)
708#define PMC_SLPWK_ASR1_PID50 (0x1u << 18)
709#define PMC_SLPWK_ASR1_PID51 (0x1u << 19)
710#define PMC_SLPWK_ASR1_PID52 (0x1u << 20)
711#define PMC_SLPWK_ASR1_PID53 (0x1u << 21)
712#define PMC_SLPWK_ASR1_PID56 (0x1u << 24)
713#define PMC_SLPWK_ASR1_PID57 (0x1u << 25)
714#define PMC_SLPWK_ASR1_PID58 (0x1u << 26)
715#define PMC_SLPWK_ASR1_PID59 (0x1u << 27)
716#define PMC_SLPWK_ASR1_PID60 (0x1u << 28)
717/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */
718#define PMC_SLPWK_AIPR_AIP (0x1u << 0)
721
722
723#endif /* _SAME70_PMC_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Pmc
Pmc hardware registers.
Definition: component_pmc.h:41
Pmc::CKGR_PLLAR
__IO uint32_t CKGR_PLLAR
(Pmc Offset: 0x0028) PLLA Register
Definition: component_pmc.h:52
Pmc::PMC_IER
__O uint32_t PMC_IER
(Pmc Offset: 0x0060) Interrupt Enable Register
Definition: component_pmc.h:60
Pmc::PMC_PMMR
__IO uint32_t PMC_PMMR
(Pmc Offset: 0x0130) PLL Maximum Multiplier Value Register
Definition: component_pmc.h:81
Pmc::CKGR_UCKR
__IO uint32_t CKGR_UCKR
(Pmc Offset: 0x001C) UTMI Clock Register
Definition: component_pmc.h:49
Pmc::PMC_PCSR0
__I uint32_t PMC_PCSR0
(Pmc Offset: 0x0018) Peripheral Clock Status Register 0
Definition: component_pmc.h:48
Pmc::PMC_FSMR
__IO uint32_t PMC_FSMR
(Pmc Offset: 0x0070) Fast Startup Mode Register
Definition: component_pmc.h:64
Pmc::PMC_USB
__IO uint32_t PMC_USB
(Pmc Offset: 0x0038) USB Clock Register
Definition: component_pmc.h:56
Pmc::PMC_SR
__I uint32_t PMC_SR
(Pmc Offset: 0x0068) Status Register
Definition: component_pmc.h:62
Pmc::PMC_SLPWK_SR0
__I uint32_t PMC_SLPWK_SR0
(Pmc Offset: 0x011C) SleepWalking Status Register 0
Definition: component_pmc.h:78
Pmc::PMC_PCER0
__O uint32_t PMC_PCER0
(Pmc Offset: 0x0010) Peripheral Clock Enable Register 0
Definition: component_pmc.h:46
Pmc::PMC_SLPWK_ER1
__O uint32_t PMC_SLPWK_ER1
(Pmc Offset: 0x0134) SleepWalking Enable Register 1
Definition: component_pmc.h:82
Pmc::PMC_SLPWK_ER0
__O uint32_t PMC_SLPWK_ER0
(Pmc Offset: 0x0114) SleepWalking Enable Register 0
Definition: component_pmc.h:76
Pmc::PMC_PCDR0
__O uint32_t PMC_PCDR0
(Pmc Offset: 0x0014) Peripheral Clock Disable Register 0
Definition: component_pmc.h:47
Pmc::PMC_MCKR
__IO uint32_t PMC_MCKR
(Pmc Offset: 0x0030) Master Clock Register
Definition: component_pmc.h:54
Pmc::CKGR_MCFR
__IO uint32_t CKGR_MCFR
(Pmc Offset: 0x0024) Main Clock Frequency Register
Definition: component_pmc.h:51
Pmc::PMC_IMR
__I uint32_t PMC_IMR
(Pmc Offset: 0x006C) Interrupt Mask Register
Definition: component_pmc.h:63
Pmc::PMC_SCER
__O uint32_t PMC_SCER
(Pmc Offset: 0x0000) System Clock Enable Register
Definition: component_pmc.h:42
Pmc::PMC_WPSR
__I uint32_t PMC_WPSR
(Pmc Offset: 0x00E8) Write Protection Status Register
Definition: component_pmc.h:69
Pmc::PMC_SLPWK_SR1
__I uint32_t PMC_SLPWK_SR1
(Pmc Offset: 0x013C) SleepWalking Status Register 1
Definition: component_pmc.h:84
Pmc::PMC_PCSR1
__I uint32_t PMC_PCSR1
(Pmc Offset: 0x0108) Peripheral Clock Status Register 1
Definition: component_pmc.h:73
Pmc::PMC_PCER1
__O uint32_t PMC_PCER1
(Pmc Offset: 0x0100) Peripheral Clock Enable Register 1
Definition: component_pmc.h:71
Pmc::PMC_IDR
__O uint32_t PMC_IDR
(Pmc Offset: 0x0064) Interrupt Disable Register
Definition: component_pmc.h:61
Pmc::PMC_SCSR
__I uint32_t PMC_SCSR
(Pmc Offset: 0x0008) System Clock Status Register
Definition: component_pmc.h:44
Pmc::PMC_FSPR
__IO uint32_t PMC_FSPR
(Pmc Offset: 0x0074) Fast Startup Polarity Register
Definition: component_pmc.h:65
Pmc::PMC_SLPWK_DR1
__O uint32_t PMC_SLPWK_DR1
(Pmc Offset: 0x0138) SleepWalking Disable Register 1
Definition: component_pmc.h:83
Pmc::CKGR_MOR
__IO uint32_t CKGR_MOR
(Pmc Offset: 0x0020) Main Oscillator Register
Definition: component_pmc.h:50
Pmc::PMC_OCR
__IO uint32_t PMC_OCR
(Pmc Offset: 0x0110) Oscillator Calibration Register
Definition: component_pmc.h:75
Pmc::PMC_SLPWK_DR0
__O uint32_t PMC_SLPWK_DR0
(Pmc Offset: 0x0118) SleepWalking Disable Register 0
Definition: component_pmc.h:77
Pmc::PMC_WPMR
__IO uint32_t PMC_WPMR
(Pmc Offset: 0x00E4) Write Protection Mode Register
Definition: component_pmc.h:68
Pmc::PMC_SLPWK_ASR0
__I uint32_t PMC_SLPWK_ASR0
(Pmc Offset: 0x0120) SleepWalking Activity Status Register 0
Definition: component_pmc.h:79
Pmc::PMC_PCDR1
__O uint32_t PMC_PCDR1
(Pmc Offset: 0x0104) Peripheral Clock Disable Register 1
Definition: component_pmc.h:72
Pmc::PMC_SCDR
__O uint32_t PMC_SCDR
(Pmc Offset: 0x0004) System Clock Disable Register
Definition: component_pmc.h:43
Pmc::PMC_SLPWK_AIPR
__I uint32_t PMC_SLPWK_AIPR
(Pmc Offset: 0x0144) SleepWalking Activity In Progress Register
Definition: component_pmc.h:86
Pmc::PMC_SLPWK_ASR1
__I uint32_t PMC_SLPWK_ASR1
(Pmc Offset: 0x0140) SleepWalking Activity Status Register 1
Definition: component_pmc.h:85
Pmc::PMC_FOCR
__O uint32_t PMC_FOCR
(Pmc Offset: 0x0078) Fault Output Clear Register
Definition: component_pmc.h:66
Pmc::PMC_PCR
__IO uint32_t PMC_PCR
(Pmc Offset: 0x010C) Peripheral Control Register
Definition: component_pmc.h:74