RTEMS: bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h Source File

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stm32f4xxxx_rcc.h
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1
7/*
8 * Copyright (c) 2012 Sebastian Huber. All rights reserved.
9 *
10 * embedded brains GmbH
11 * Obere Lagerstr. 30
12 * 82178 Puchheim
13 * Germany
14 * <rtems@embedded-brains.de>
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 */
20
21#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H
22#define LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H
23
24#include <bsp/utility.h>
25
33typedef struct {
34 uint32_t cr;
35#define STM32F4_RCC_CR_PLLI2SRDY BSP_BIT32(27) // PLLI2S clock ready flag
36#define STM32F4_RCC_CR_PLLI2SON BSP_BIT32(26) // PLLI2S enable
37#define STM32F4_RCC_CR_PLLRDY BSP_BIT32(25) // Main PLL clock ready flag
38#define STM32F4_RCC_CR_PLLON BSP_BIT32(24) // Main PLL enable
39#define STM32F4_RCC_CR_CSSON BSP_BIT32(19) // Clock security system enable
40#define STM32F4_RCC_CR_HSEBYP BSP_BIT32(18) // HSE clock bypass
41#define STM32F4_RCC_CR_HSERDY BSP_BIT32(17) // HSE clock ready flag
42#define STM32F4_RCC_CR_HSEON BSP_BIT32(16) // HSE clock enable
43#define STM32F4_RCC_CR_HSIRDY BSP_BIT32(1) // HSI clock ready flag
44#define STM32F4_RCC_CR_HSION BSP_BIT32(0) // HSI clock enable
45
46 uint32_t pllcfgr;
47#define STM32F4_RCC_PLLCFGR_PLLQ(val) BSP_FLD32(val, 24, 27)
48#define STM32F4_RCC_PLLCFGR_PLLQ_GET(reg) BSP_FLD32GET(reg, 24, 27)
49#define STM32F4_RCC_PLLCFGR_PLLQ_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27)
50#define STM32F4_RCC_PLLCFGR_SRC BSP_BIT32(22) // PLL entry clock source
51#define STM32F4_RCC_PLLCFGR_SRC_HSE STM32F4_RCC_PLLCFGR_SRC
52#define STM32F4_RCC_PLLCFGR_SRC_HSI 0
53#define STM32F4_RCC_PLLCFGR_PLLP(val) BSP_FLD32(val, 16, 17)
54#define STM32F4_RCC_PLLCFGR_PLLP_GET(reg) BSP_FLD32GET(reg, 16, 17)
55#define STM32F4_RCC_PLLCFGR_PLLP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17)
56#define STM32F4_RCC_PLLCFGR_PLLP_2 STM32F4_RCC_PLLCFGR_PLLP(0)
57#define STM32F4_RCC_PLLCFGR_PLLP_4 STM32F4_RCC_PLLCFGR_PLLP(1)
58#define STM32F4_RCC_PLLCFGR_PLLP_6 STM32F4_RCC_PLLCFGR_PLLP(2)
59#define STM32F4_RCC_PLLCFGR_PLLP_8 STM32F4_RCC_PLLCFGR_PLLP(3)
60#define STM32F4_RCC_PLLCFGR_PLLN(val) BSP_FLD32(val, 6, 14)
61#define STM32F4_RCC_PLLCFGR_PLLN_GET(reg) BSP_FLD32GET(reg, 6, 14)
62#define STM32F4_RCC_PLLCFGR_PLLN_SET(reg, val) BSP_FLD32SET(reg, val, 6, 14)
63#define STM32F4_RCC_PLLCFGR_PLLM(val) BSP_FLD32(val, 0, 5)
64#define STM32F4_RCC_PLLCFGR_PLLM_GET(reg) BSP_FLD32GET(reg, 0, 5)
65#define STM32F4_RCC_PLLCFGR_PLLM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
66
67 uint32_t cfgr;
68#define STM32F4_RCC_CFGR_MCO2(val) BSP_FLD32(val, 30, 31) // Microcontroller clock output 2
69#define STM32F4_RCC_CFGR_MCO2_GET(reg) BSP_FLD32GET(reg, 30, 31)
70#define STM32F4_RCC_CFGR_MCO2_SET(reg, val) BSP_FLD32SET(reg, val, 30, 31)
71#define STM32F4_RCC_CFGR_MCO2_SYSCLK STM32F4_RCC_CFGR_MCO2(0)
72#define STM32F4_RCC_CFGR_MCO2_PLLI2S STM32F4_RCC_CFGR_MCO2(1)
73#define STM32F4_RCC_CFGR_MCO2_HSE STM32F4_RCC_CFGR_MCO2(2)
74#define STM32F4_RCC_CFGR_MCO2_PLL STM32F4_RCC_CFGR_MCO2(3)
75#define STM32F4_RCC_CFGR_MCO2_PRE(val) BSP_FLD32(val, 27, 29) // MCO2 prescalar
76#define STM32F4_RCC_CFGR_MCO2_PRE_GET(reg) BSP_FLD32GET(reg, 27, 29)
77#define STM32F4_RCC_CFGR_MCO2_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 27, 29)
78#define STM32F4_RCC_CFGR_MCO2_DIV1 STM32F4_RCC_CFGR_MCO2_PRE(0)
79#define STM32F4_RCC_CFGR_MCO2_DIV2 STM32F4_RCC_CFGR_MCO2_PRE(4)
80#define STM32F4_RCC_CFGR_MCO2_DIV3 STM32F4_RCC_CFGR_MCO2_PRE(5)
81#define STM32F4_RCC_CFGR_MCO2_DIV4 STM32F4_RCC_CFGR_MCO2_PRE(6)
82#define STM32F4_RCC_CFGR_MCO2_DIV5 STM32F4_RCC_CFGR_MCO2_PRE(7)
83#define STM32F4_RCC_CFGR_MCO1_PRE(val) BSP_FLD32(val, 24, 26) // MCO1 prescalar
84#define STM32F4_RCC_CFGR_MCO1_PRE_GET(reg) BSP_FLD32GET(reg, 24, 26)
85#define STM32F4_RCC_CFGR_MCO1_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26)
86#define STM32F4_RCC_CFGR_MCO1_DIV1 STM32F4_RCC_CFGR_MCO1_PRE(0)
87#define STM32F4_RCC_CFGR_MCO1_DIV2 STM32F4_RCC_CFGR_MCO1_PRE(4)
88#define STM32F4_RCC_CFGR_MCO1_DIV3 STM32F4_RCC_CFGR_MCO1_PRE(5)
89#define STM32F4_RCC_CFGR_MCO1_DIV4 STM32F4_RCC_CFGR_MCO1_PRE(6)
90#define STM32F4_RCC_CFGR_MCO1_DIV5 STM32F4_RCC_CFGR_MCO1_PRE(7)
91#define STM32F4_RCC_CFGR_I2SSCR BSP_BIT32(23) // I2S clock selection
92#define STM32F4_RCC_CFGR_MCO1(val) BSP_FLD32(val, 21, 22) // Microcontroller clock output 1
93#define STM32F4_RCC_CFGR_MCO1_GET(reg) BSP_FLD32GET(reg, 21, 22)
94#define STM32F4_RCC_CFGR_MCO1_SET(reg, val) BSP_FLD32SET(reg, val, 21, 22)
95#define STM32F4_RCC_CFGR_MCO1_HSI STM32F4_RCC_CFGR_MCO1(0)
96#define STM32F4_RCC_CFGR_MCO1_LSE STM32F4_RCC_CFGR_MCO1(1)
97#define STM32F4_RCC_CFGR_MCO1_HSE STM32F4_RCC_CFGR_MCO1(2)
98#define STM32F4_RCC_CFGR_MCO1_PLL STM32F4_RCC_CFGR_MCO1(3)
99#define STM32F4_RCC_CFGR_RTCPRE(val) BSP_FLD32(val, 16, 20) // HSE division factor for RTC clock
100#define STM32F4_RCC_CFGR_RTCPRE_GET(reg) BSP_FLD32GET(reg, 16, 20)
101#define STM32F4_RCC_CFGR_RTCPRE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20)
102#define STM32F4_RCC_CFGR_PPRE2(val) BSP_FLD32(val, 13, 15) // APB high-speed prescalar (APB2)
103#define STM32F4_RCC_CFGR_PPRE2_GET(reg) BSP_FLD32GET(reg, 13, 15)
104#define STM32F4_RCC_CFGR_PPRE2_SET(reg, val) BSP_FLD32SET(reg, val, 13, 15)
105#define STM32F4_RCC_CFGR_PPRE2_DIV1 STM32F4_RCC_CFGR_PPRE2(0)
106#define STM32F4_RCC_CFGR_PPRE2_DIV2 STM32F4_RCC_CFGR_PPRE2(4)
107#define STM32F4_RCC_CFGR_PPRE2_DIV4 STM32F4_RCC_CFGR_PPRE2(5)
108#define STM32F4_RCC_CFGR_PPRE2_DIV8 STM32F4_RCC_CFGR_PPRE2(6)
109#define STM32F4_RCC_CFGR_PPRE2_DIV16 STM32F4_RCC_CFGR_PPRE2(7)
110#define STM32F4_RCC_CFGR_PPRE1(val) BSP_FLD32(val, 10, 12) // APB low-speed prescalar (APB1)
111#define STM32F4_RCC_CFGR_PPRE1_GET(reg) BSP_FLD32GET(reg, 10, 12)
112#define STM32F4_RCC_CFGR_PPRE1_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
113#define STM32F4_RCC_CFGR_PPRE1_DIV1 STM32F4_RCC_CFGR_PPRE1(0)
114#define STM32F4_RCC_CFGR_PPRE1_DIV2 STM32F4_RCC_CFGR_PPRE1(4)
115#define STM32F4_RCC_CFGR_PPRE1_DIV4 STM32F4_RCC_CFGR_PPRE1(5)
116#define STM32F4_RCC_CFGR_PPRE1_DIV8 STM32F4_RCC_CFGR_PPRE1(6)
117#define STM32F4_RCC_CFGR_PPRE1_DIV16 STM32F4_RCC_CFGR_PPRE1(7)
118#define STM32F4_RCC_CFGR_HPRE(val) BSP_FLD32(val, 4, 15) // AHB prescalar
119#define STM32F4_RCC_CFGR_HPRE_GET(reg) BSP_FLD32GET(reg, 4, 7)
120#define STM32F4_RCC_CFGR_HPRE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
121#define STM32F4_RCC_CFGR_HPRE_DIV1 STM32F4_RCC_CFGR_HPRE(0)
122#define STM32F4_RCC_CFGR_HPRE_DIV2 STM32F4_RCC_CFGR_HPRE(8)
123#define STM32F4_RCC_CFGR_HPRE_DIV4 STM32F4_RCC_CFGR_HPRE(9)
124#define STM32F4_RCC_CFGR_HPRE_DIV8 STM32F4_RCC_CFGR_HPRE(10)
125#define STM32F4_RCC_CFGR_HPRE_DIV16 STM32F4_RCC_CFGR_HPRE(11)
126#define STM32F4_RCC_CFGR_HPRE_DIV64 STM32F4_RCC_CFGR_HPRE(12)
127#define STM32F4_RCC_CFGR_HPRE_DIV128 STM32F4_RCC_CFGR_HPRE(13)
128#define STM32F4_RCC_CFGR_HPRE_DIV256 STM32F4_RCC_CFGR_HPRE(14)
129#define STM32F4_RCC_CFGR_HPRE_DIV512 STM32F4_RCC_CFGR_HPRE(15)
130#define STM32F4_RCC_CFGR_SWS(val) BSP_FLD32(val, 2, 3) // System clock switch status
131#define STM32F4_RCC_CFGR_SWS_GET(reg) BSP_FLD32GET(reg, 2, 3)
132#define STM32F4_RCC_CFGR_SWS_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3)
133#define STM32F4_RCC_CFGR_SWS_HSI STM32F4_RCC_CFGR_SWS(0)
134#define STM32F4_RCC_CFGR_SWS_HSE STM32F4_RCC_CFGR_SWS(1)
135#define STM32F4_RCC_CFGR_SWS_PLL STM32F4_RCC_CFGR_SWS(2)
136#define STM32F4_RCC_CFGR_SW(val) BSP_FLD32(val, 0, 1) // System clock switch
137#define STM32F4_RCC_CFGR_SW_GET(reg) BSP_FLD32GET(reg, 0, 1)
138#define STM32F4_RCC_CFGR_SW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
139#define STM32F4_RCC_CFGR_SW_HSI STM32F4_RCC_CFGR_SW(0)
140#define STM32F4_RCC_CFGR_SW_HSE STM32F4_RCC_CFGR_SW(1)
141#define STM32F4_RCC_CFGR_SW_PLL STM32F4_RCC_CFGR_SW(2)
142
143 uint32_t cir;
144
145 uint32_t ahbrstr [3];
146
147 uint32_t reserved_1c;
148
149 uint32_t apbrstr [2];
150
151 uint32_t reserved_28 [2];
152
153 uint32_t ahbenr [3];
154
155 uint32_t reserved_3c;
156
157 uint32_t apbenr [2];
158
159 uint32_t reserved_48 [2];
160
161 uint32_t ahblpenr [3];
162
163 uint32_t reserved_5c;
164
165 uint32_t apblpenr [2];
166
167 uint32_t reserved_68 [2];
168
169 uint32_t bdcr;
170
171 uint32_t csr;
172
173 uint32_t reserved_78 [2];
174
175 uint32_t sscgr;
176
177 uint32_t plli2scfgr;
178
179} stm32f4_rcc;
180
183#define RCC_CR_HSION BSP_BIT32( 0 )
184#define RCC_CR_HSIRDY BSP_BIT32( 1 )
185#define RCC_CR_HSITRIM( val ) BSP_FLD32( val, 3, 7 )
186#define RCC_CR_HSITRIM_MSK BSP_MSK32( 3, 7 )
187#define RCC_CR_HSICAL( val ) BSP_FLD32( val, 8, 15 )
188#define RCC_CR_HSICAL_MSK BSP_MSK32( 8, 15 )
189#define RCC_CR_HSEON BSP_BIT32( 16 )
190#define RCC_CR_HSERDY BSP_BIT32( 17 )
191#define RCC_CR_HSEBYP BSP_BIT32( 18 )
192#define RCC_CR_CSSON BSP_BIT32( 19 )
193#define RCC_CR_PLLON BSP_BIT32( 24 )
194#define RCC_CR_PLLRDY BSP_BIT32( 25 )
195#define RCC_CR_PLLI2SON BSP_BIT32( 26 )
196#define RCC_CR_PLLI2SRDY BSP_BIT32( 27 )
197
198#define RCC_PLLCFGR_PLLM( val ) BSP_FLD32( val, 0, 5 )
199#define RCC_PLLCFGR_PLLM_MSK BSP_MSK32( 0, 5 )
200#define RCC_PLLCFGR_PLLN( val ) BSP_FLD32( val, 6, 14 )
201#define RCC_PLLCFGR_PLLN_MSK BSP_MSK32( 6, 14 )
202
203#define RCC_PLLCFGR_PLLP 16
204#define RCC_PLLCFGR_PLLP_MSK BSP_MSK32( 16, 17 )
205#define RCC_PLLCFGR_PLLP_BY_2 0
206#define RCC_PLLCFGR_PLLP_BY_4 BSP_FLD32( 1, 16, 17 )
207#define RCC_PLLCFGR_PLLP_BY_6 BSP_FLD32( 2, 16, 17 )
208#define RCC_PLLCFGR_PLLP_BY_8 BSP_FLD32( 3, 16, 17 )
209
210#define RCC_PLLCFGR_PLLSRC_HSE BSP_BIT32( 22 )
211#define RCC_PLLCFGR_PLLSRC_HSI 0
212
213#define RCC_PLLCFGR_PLLQ( val ) BSP_FLD32( val, 24, 27 )
214#define RCC_PLLCFGR_PLLQ_MSK BSP_MSK32( 24, 27 )
215
216#define RCC_CFGR_SW 0
217#define RCC_CFGR_SW_MSK BSP_MSK32( 0, 1 )
218#define RCC_CFGR_SW_HSI 0
219#define RCC_CFGR_SW_HSE 1
220#define RCC_CFGR_SW_PLL 2
221
222#define RCC_CFGR_SWS 2
223#define RCC_CFGR_SWS_MSK BSP_MSK32( 2, 3 )
224#define RCC_CFGR_SWS_HSI 0
225#define RCC_CFGR_SWS_HSE BSP_FLD32( 1, 2, 3 )
226#define RCC_CFGR_SWS_PLL BSP_FLD32( 2, 2, 3 )
227
228#define RCC_CFGR_HPRE 4
229#define RCC_CFGR_HPRE_BY_1 0
230#define RCC_CFGR_HPRE_BY_2 BSP_FLD32( 8, 4, 7 )
231#define RCC_CFGR_HPRE_BY_4 BSP_FLD32( 9, 4, 7 )
232#define RCC_CFGR_HPRE_BY_8 BSP_FLD32( 10, 4, 7 )
233#define RCC_CFGR_HPRE_BY_16 BSP_FLD32( 11, 4, 7 )
234#define RCC_CFGR_HPRE_BY_64 BSP_FLD32( 12, 4, 7 )
235#define RCC_CFGR_HPRE_BY_128 BSP_FLD32( 13, 4, 7 )
236#define RCC_CFGR_HPRE_BY_256 BSP_FLD32( 14, 4, 7 )
237#define RCC_CFGR_HPRE_BY_512 BSP_FLD32( 15, 4, 7 )
238
239#define RCC_CFGR_PPRE1 10
240#define RCC_CFGR_PPRE1_BY_1 0
241#define RCC_CFGR_PPRE1_BY_2 BSP_FLD32( 4, 10, 12 )
242#define RCC_CFGR_PPRE1_BY_4 BSP_FLD32( 5, 10, 12 )
243#define RCC_CFGR_PPRE1_BY_8 BSP_FLD32( 6, 10, 12 )
244#define RCC_CFGR_PPRE1_BY_16 BSP_FLD32( 7, 10, 12 )
245
246#define RCC_CFGR_PPRE2 13
247#define RCC_CFGR_PPRE2 BSP_MSK32( 13, 15 )
248#define RCC_CFGR_PPRE2_BY_1 0
249#define RCC_CFGR_PPRE2_BY_2 BSP_FLD32( 4, 13, 15 )
250#define RCC_CFGR_PPRE2_BY_4 BSP_FLD32( 5, 13, 15 )
251#define RCC_CFGR_PPRE2_BY_8 BSP_FLD32( 6, 13, 15 )
252#define RCC_CFGR_PPRE2_BY_16 BSP_FLD32( 7, 13, 15 )
253
254#define RCC_CFGR_RTCPRE( val ) BSP_FLD32( val, 16, 20 )
255#define RCC_CFGR_RTCPRE_MSK BSP_MSK32( 16, 20 )
256
257#define RCC_CFGR_MCO1 21
258#define RCC_CFGR_MCO1_MSK BSP_MSK32( 21, 22 )
259#define RCC_CFGR_MCO1_HSI 0
260#define RCC_CFGR_MCO1_LSE BSP_FLD32( 1, 21, 22 )
261#define RCC_CFGR_MCO1_HSE BSP_FLD32( 2, 21, 22 )
262#define RCC_CFGR_MCO1_PLL BSP_FLD32( 3, 21, 22 )
263
264#define RCC_CFGR_I2SSRC BSP_BIT32( 23 )
265
266#define RCC_CFGR_MCO1PRE 24
267#define RCC_CFGR_MCO1PRE_MSK BSP_MSK32( 24, 26 )
268#define RCC_CFGR_MCO1PRE_BY_1 0
269#define RCC_CFGR_MCO1PRE_BY_2 BSP_FLD32( 4, 24, 26 )
270#define RCC_CFGR_MCO1PRE_BY_3 BSP_FLD32( 5, 24, 26 )
271#define RCC_CFGR_MCO1PRE_BY_4 BSP_FLD32( 6, 24, 26 )
272#define RCC_CFGR_MCO1PRE_BY_5 BSP_FLD32( 7, 24, 26 )
273
274#define RCC_CFGR_MCO2PRE 27
275#define RCC_CFGR_MCO2PRE_MSK BSP_MSK32( 27, 29 )
276#define RCC_CFGR_MCO2PRE_BY_1 0
277#define RCC_CFGR_MCO2PRE_BY_2 BSP_FLD32( 4, 27, 29 )
278#define RCC_CFGR_MCO2PRE_BY_3 BSP_FLD32( 5, 27, 29 )
279#define RCC_CFGR_MCO2PRE_BY_4 BSP_FLD32( 6, 27, 29 )
280#define RCC_CFGR_MCO2PRE_BY_5 BSP_FLD32( 7, 27, 29 )
281
282#define RCC_CFGR_MCO2 30
283#define RCC_CFGR_MCO2_MSK BSP_MSK32( 30, 31 )
284#define RCC_CFGR_MCO2_SYSCLK 0
285#define RCC_CFGR_MCO2_PLLI2S BSP_FLD32( 1, 30, 31 )
286#define RCC_CFGR_MCO2_HSE BSP_FLD32( 2, 30, 31 )
287#define RCC_CFGR_MCO2_PLL BSP_FLD32( 3, 30, 31 )
288
289#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H */
utility.h
Utility macros.
stm32f4_rcc
Definition: stm32f10xxx_rcc.h:33