RTEMS: bsps/arm/atsam/include/libchip/include/sams70/component/component_xdmac.h Source File

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component_xdmac.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70_XDMAC_COMPONENT_
31#define _SAMS70_XDMAC_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __O uint32_t XDMAC_CIE;
43 __O uint32_t XDMAC_CID;
44 __O uint32_t XDMAC_CIM;
45 __I uint32_t XDMAC_CIS;
46 __IO uint32_t XDMAC_CSA;
47 __IO uint32_t XDMAC_CDA;
48 __IO uint32_t XDMAC_CNDA;
49 __IO uint32_t XDMAC_CNDC;
50 __IO uint32_t XDMAC_CUBC;
51 __IO uint32_t XDMAC_CBC;
52 __IO uint32_t XDMAC_CC;
53 __IO uint32_t XDMAC_CDS_MSP;
54 __IO uint32_t XDMAC_CSUS;
55 __IO uint32_t XDMAC_CDUS;
56 __I uint32_t Reserved1[2];
57} XdmacChid;
59#define XDMACCHID_NUMBER 24
60typedef struct {
61 __IO uint32_t XDMAC_GTYPE;
62 __I uint32_t XDMAC_GCFG;
63 __IO uint32_t XDMAC_GWAC;
64 __O uint32_t XDMAC_GIE;
65 __O uint32_t XDMAC_GID;
66 __I uint32_t XDMAC_GIM;
67 __I uint32_t XDMAC_GIS;
68 __O uint32_t XDMAC_GE;
69 __O uint32_t XDMAC_GD;
70 __I uint32_t XDMAC_GS;
71 __IO uint32_t XDMAC_GRS;
72 __IO uint32_t XDMAC_GWS;
73 __O uint32_t XDMAC_GRWS;
74 __O uint32_t XDMAC_GRWR;
75 __O uint32_t XDMAC_GSWR;
76 __I uint32_t XDMAC_GSWS;
77 __O uint32_t XDMAC_GSWF;
78 __I uint32_t Reserved1[3];
79 XdmacChid XDMAC_CHID[XDMACCHID_NUMBER];
80} Xdmac;
81#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
82/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */
83#define XDMAC_GTYPE_NB_CH_Pos 0
84#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos)
85#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos)))
86#define XDMAC_GTYPE_FIFO_SZ_Pos 5
87#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos)
88#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos)))
89#define XDMAC_GTYPE_NB_REQ_Pos 16
90#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos)
91#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos)))
92/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */
93#define XDMAC_GCFG_CGDISREG (0x1u << 0)
94#define XDMAC_GCFG_CGDISPIPE (0x1u << 1)
95#define XDMAC_GCFG_CGDISFIFO (0x1u << 2)
96#define XDMAC_GCFG_CGDISIF (0x1u << 3)
97#define XDMAC_GCFG_BXKBEN (0x1u << 8)
98/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */
99#define XDMAC_GWAC_PW0_Pos 0
100#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos)
101#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos)))
102#define XDMAC_GWAC_PW1_Pos 4
103#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos)
104#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos)))
105#define XDMAC_GWAC_PW2_Pos 8
106#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos)
107#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos)))
108#define XDMAC_GWAC_PW3_Pos 12
109#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos)
110#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos)))
111/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */
112#define XDMAC_GIE_IE0 (0x1u << 0)
113#define XDMAC_GIE_IE1 (0x1u << 1)
114#define XDMAC_GIE_IE2 (0x1u << 2)
115#define XDMAC_GIE_IE3 (0x1u << 3)
116#define XDMAC_GIE_IE4 (0x1u << 4)
117#define XDMAC_GIE_IE5 (0x1u << 5)
118#define XDMAC_GIE_IE6 (0x1u << 6)
119#define XDMAC_GIE_IE7 (0x1u << 7)
120#define XDMAC_GIE_IE8 (0x1u << 8)
121#define XDMAC_GIE_IE9 (0x1u << 9)
122#define XDMAC_GIE_IE10 (0x1u << 10)
123#define XDMAC_GIE_IE11 (0x1u << 11)
124#define XDMAC_GIE_IE12 (0x1u << 12)
125#define XDMAC_GIE_IE13 (0x1u << 13)
126#define XDMAC_GIE_IE14 (0x1u << 14)
127#define XDMAC_GIE_IE15 (0x1u << 15)
128#define XDMAC_GIE_IE16 (0x1u << 16)
129#define XDMAC_GIE_IE17 (0x1u << 17)
130#define XDMAC_GIE_IE18 (0x1u << 18)
131#define XDMAC_GIE_IE19 (0x1u << 19)
132#define XDMAC_GIE_IE20 (0x1u << 20)
133#define XDMAC_GIE_IE21 (0x1u << 21)
134#define XDMAC_GIE_IE22 (0x1u << 22)
135#define XDMAC_GIE_IE23 (0x1u << 23)
136/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */
137#define XDMAC_GID_ID0 (0x1u << 0)
138#define XDMAC_GID_ID1 (0x1u << 1)
139#define XDMAC_GID_ID2 (0x1u << 2)
140#define XDMAC_GID_ID3 (0x1u << 3)
141#define XDMAC_GID_ID4 (0x1u << 4)
142#define XDMAC_GID_ID5 (0x1u << 5)
143#define XDMAC_GID_ID6 (0x1u << 6)
144#define XDMAC_GID_ID7 (0x1u << 7)
145#define XDMAC_GID_ID8 (0x1u << 8)
146#define XDMAC_GID_ID9 (0x1u << 9)
147#define XDMAC_GID_ID10 (0x1u << 10)
148#define XDMAC_GID_ID11 (0x1u << 11)
149#define XDMAC_GID_ID12 (0x1u << 12)
150#define XDMAC_GID_ID13 (0x1u << 13)
151#define XDMAC_GID_ID14 (0x1u << 14)
152#define XDMAC_GID_ID15 (0x1u << 15)
153#define XDMAC_GID_ID16 (0x1u << 16)
154#define XDMAC_GID_ID17 (0x1u << 17)
155#define XDMAC_GID_ID18 (0x1u << 18)
156#define XDMAC_GID_ID19 (0x1u << 19)
157#define XDMAC_GID_ID20 (0x1u << 20)
158#define XDMAC_GID_ID21 (0x1u << 21)
159#define XDMAC_GID_ID22 (0x1u << 22)
160#define XDMAC_GID_ID23 (0x1u << 23)
161/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */
162#define XDMAC_GIM_IM0 (0x1u << 0)
163#define XDMAC_GIM_IM1 (0x1u << 1)
164#define XDMAC_GIM_IM2 (0x1u << 2)
165#define XDMAC_GIM_IM3 (0x1u << 3)
166#define XDMAC_GIM_IM4 (0x1u << 4)
167#define XDMAC_GIM_IM5 (0x1u << 5)
168#define XDMAC_GIM_IM6 (0x1u << 6)
169#define XDMAC_GIM_IM7 (0x1u << 7)
170#define XDMAC_GIM_IM8 (0x1u << 8)
171#define XDMAC_GIM_IM9 (0x1u << 9)
172#define XDMAC_GIM_IM10 (0x1u << 10)
173#define XDMAC_GIM_IM11 (0x1u << 11)
174#define XDMAC_GIM_IM12 (0x1u << 12)
175#define XDMAC_GIM_IM13 (0x1u << 13)
176#define XDMAC_GIM_IM14 (0x1u << 14)
177#define XDMAC_GIM_IM15 (0x1u << 15)
178#define XDMAC_GIM_IM16 (0x1u << 16)
179#define XDMAC_GIM_IM17 (0x1u << 17)
180#define XDMAC_GIM_IM18 (0x1u << 18)
181#define XDMAC_GIM_IM19 (0x1u << 19)
182#define XDMAC_GIM_IM20 (0x1u << 20)
183#define XDMAC_GIM_IM21 (0x1u << 21)
184#define XDMAC_GIM_IM22 (0x1u << 22)
185#define XDMAC_GIM_IM23 (0x1u << 23)
186/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */
187#define XDMAC_GIS_IS0 (0x1u << 0)
188#define XDMAC_GIS_IS1 (0x1u << 1)
189#define XDMAC_GIS_IS2 (0x1u << 2)
190#define XDMAC_GIS_IS3 (0x1u << 3)
191#define XDMAC_GIS_IS4 (0x1u << 4)
192#define XDMAC_GIS_IS5 (0x1u << 5)
193#define XDMAC_GIS_IS6 (0x1u << 6)
194#define XDMAC_GIS_IS7 (0x1u << 7)
195#define XDMAC_GIS_IS8 (0x1u << 8)
196#define XDMAC_GIS_IS9 (0x1u << 9)
197#define XDMAC_GIS_IS10 (0x1u << 10)
198#define XDMAC_GIS_IS11 (0x1u << 11)
199#define XDMAC_GIS_IS12 (0x1u << 12)
200#define XDMAC_GIS_IS13 (0x1u << 13)
201#define XDMAC_GIS_IS14 (0x1u << 14)
202#define XDMAC_GIS_IS15 (0x1u << 15)
203#define XDMAC_GIS_IS16 (0x1u << 16)
204#define XDMAC_GIS_IS17 (0x1u << 17)
205#define XDMAC_GIS_IS18 (0x1u << 18)
206#define XDMAC_GIS_IS19 (0x1u << 19)
207#define XDMAC_GIS_IS20 (0x1u << 20)
208#define XDMAC_GIS_IS21 (0x1u << 21)
209#define XDMAC_GIS_IS22 (0x1u << 22)
210#define XDMAC_GIS_IS23 (0x1u << 23)
211/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */
212#define XDMAC_GE_EN0 (0x1u << 0)
213#define XDMAC_GE_EN1 (0x1u << 1)
214#define XDMAC_GE_EN2 (0x1u << 2)
215#define XDMAC_GE_EN3 (0x1u << 3)
216#define XDMAC_GE_EN4 (0x1u << 4)
217#define XDMAC_GE_EN5 (0x1u << 5)
218#define XDMAC_GE_EN6 (0x1u << 6)
219#define XDMAC_GE_EN7 (0x1u << 7)
220#define XDMAC_GE_EN8 (0x1u << 8)
221#define XDMAC_GE_EN9 (0x1u << 9)
222#define XDMAC_GE_EN10 (0x1u << 10)
223#define XDMAC_GE_EN11 (0x1u << 11)
224#define XDMAC_GE_EN12 (0x1u << 12)
225#define XDMAC_GE_EN13 (0x1u << 13)
226#define XDMAC_GE_EN14 (0x1u << 14)
227#define XDMAC_GE_EN15 (0x1u << 15)
228#define XDMAC_GE_EN16 (0x1u << 16)
229#define XDMAC_GE_EN17 (0x1u << 17)
230#define XDMAC_GE_EN18 (0x1u << 18)
231#define XDMAC_GE_EN19 (0x1u << 19)
232#define XDMAC_GE_EN20 (0x1u << 20)
233#define XDMAC_GE_EN21 (0x1u << 21)
234#define XDMAC_GE_EN22 (0x1u << 22)
235#define XDMAC_GE_EN23 (0x1u << 23)
236/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */
237#define XDMAC_GD_DI0 (0x1u << 0)
238#define XDMAC_GD_DI1 (0x1u << 1)
239#define XDMAC_GD_DI2 (0x1u << 2)
240#define XDMAC_GD_DI3 (0x1u << 3)
241#define XDMAC_GD_DI4 (0x1u << 4)
242#define XDMAC_GD_DI5 (0x1u << 5)
243#define XDMAC_GD_DI6 (0x1u << 6)
244#define XDMAC_GD_DI7 (0x1u << 7)
245#define XDMAC_GD_DI8 (0x1u << 8)
246#define XDMAC_GD_DI9 (0x1u << 9)
247#define XDMAC_GD_DI10 (0x1u << 10)
248#define XDMAC_GD_DI11 (0x1u << 11)
249#define XDMAC_GD_DI12 (0x1u << 12)
250#define XDMAC_GD_DI13 (0x1u << 13)
251#define XDMAC_GD_DI14 (0x1u << 14)
252#define XDMAC_GD_DI15 (0x1u << 15)
253#define XDMAC_GD_DI16 (0x1u << 16)
254#define XDMAC_GD_DI17 (0x1u << 17)
255#define XDMAC_GD_DI18 (0x1u << 18)
256#define XDMAC_GD_DI19 (0x1u << 19)
257#define XDMAC_GD_DI20 (0x1u << 20)
258#define XDMAC_GD_DI21 (0x1u << 21)
259#define XDMAC_GD_DI22 (0x1u << 22)
260#define XDMAC_GD_DI23 (0x1u << 23)
261/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */
262#define XDMAC_GS_ST0 (0x1u << 0)
263#define XDMAC_GS_ST1 (0x1u << 1)
264#define XDMAC_GS_ST2 (0x1u << 2)
265#define XDMAC_GS_ST3 (0x1u << 3)
266#define XDMAC_GS_ST4 (0x1u << 4)
267#define XDMAC_GS_ST5 (0x1u << 5)
268#define XDMAC_GS_ST6 (0x1u << 6)
269#define XDMAC_GS_ST7 (0x1u << 7)
270#define XDMAC_GS_ST8 (0x1u << 8)
271#define XDMAC_GS_ST9 (0x1u << 9)
272#define XDMAC_GS_ST10 (0x1u << 10)
273#define XDMAC_GS_ST11 (0x1u << 11)
274#define XDMAC_GS_ST12 (0x1u << 12)
275#define XDMAC_GS_ST13 (0x1u << 13)
276#define XDMAC_GS_ST14 (0x1u << 14)
277#define XDMAC_GS_ST15 (0x1u << 15)
278#define XDMAC_GS_ST16 (0x1u << 16)
279#define XDMAC_GS_ST17 (0x1u << 17)
280#define XDMAC_GS_ST18 (0x1u << 18)
281#define XDMAC_GS_ST19 (0x1u << 19)
282#define XDMAC_GS_ST20 (0x1u << 20)
283#define XDMAC_GS_ST21 (0x1u << 21)
284#define XDMAC_GS_ST22 (0x1u << 22)
285#define XDMAC_GS_ST23 (0x1u << 23)
286/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */
287#define XDMAC_GRS_RS0 (0x1u << 0)
288#define XDMAC_GRS_RS1 (0x1u << 1)
289#define XDMAC_GRS_RS2 (0x1u << 2)
290#define XDMAC_GRS_RS3 (0x1u << 3)
291#define XDMAC_GRS_RS4 (0x1u << 4)
292#define XDMAC_GRS_RS5 (0x1u << 5)
293#define XDMAC_GRS_RS6 (0x1u << 6)
294#define XDMAC_GRS_RS7 (0x1u << 7)
295#define XDMAC_GRS_RS8 (0x1u << 8)
296#define XDMAC_GRS_RS9 (0x1u << 9)
297#define XDMAC_GRS_RS10 (0x1u << 10)
298#define XDMAC_GRS_RS11 (0x1u << 11)
299#define XDMAC_GRS_RS12 (0x1u << 12)
300#define XDMAC_GRS_RS13 (0x1u << 13)
301#define XDMAC_GRS_RS14 (0x1u << 14)
302#define XDMAC_GRS_RS15 (0x1u << 15)
303#define XDMAC_GRS_RS16 (0x1u << 16)
304#define XDMAC_GRS_RS17 (0x1u << 17)
305#define XDMAC_GRS_RS18 (0x1u << 18)
306#define XDMAC_GRS_RS19 (0x1u << 19)
307#define XDMAC_GRS_RS20 (0x1u << 20)
308#define XDMAC_GRS_RS21 (0x1u << 21)
309#define XDMAC_GRS_RS22 (0x1u << 22)
310#define XDMAC_GRS_RS23 (0x1u << 23)
311/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */
312#define XDMAC_GWS_WS0 (0x1u << 0)
313#define XDMAC_GWS_WS1 (0x1u << 1)
314#define XDMAC_GWS_WS2 (0x1u << 2)
315#define XDMAC_GWS_WS3 (0x1u << 3)
316#define XDMAC_GWS_WS4 (0x1u << 4)
317#define XDMAC_GWS_WS5 (0x1u << 5)
318#define XDMAC_GWS_WS6 (0x1u << 6)
319#define XDMAC_GWS_WS7 (0x1u << 7)
320#define XDMAC_GWS_WS8 (0x1u << 8)
321#define XDMAC_GWS_WS9 (0x1u << 9)
322#define XDMAC_GWS_WS10 (0x1u << 10)
323#define XDMAC_GWS_WS11 (0x1u << 11)
324#define XDMAC_GWS_WS12 (0x1u << 12)
325#define XDMAC_GWS_WS13 (0x1u << 13)
326#define XDMAC_GWS_WS14 (0x1u << 14)
327#define XDMAC_GWS_WS15 (0x1u << 15)
328#define XDMAC_GWS_WS16 (0x1u << 16)
329#define XDMAC_GWS_WS17 (0x1u << 17)
330#define XDMAC_GWS_WS18 (0x1u << 18)
331#define XDMAC_GWS_WS19 (0x1u << 19)
332#define XDMAC_GWS_WS20 (0x1u << 20)
333#define XDMAC_GWS_WS21 (0x1u << 21)
334#define XDMAC_GWS_WS22 (0x1u << 22)
335#define XDMAC_GWS_WS23 (0x1u << 23)
336/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */
337#define XDMAC_GRWS_RWS0 (0x1u << 0)
338#define XDMAC_GRWS_RWS1 (0x1u << 1)
339#define XDMAC_GRWS_RWS2 (0x1u << 2)
340#define XDMAC_GRWS_RWS3 (0x1u << 3)
341#define XDMAC_GRWS_RWS4 (0x1u << 4)
342#define XDMAC_GRWS_RWS5 (0x1u << 5)
343#define XDMAC_GRWS_RWS6 (0x1u << 6)
344#define XDMAC_GRWS_RWS7 (0x1u << 7)
345#define XDMAC_GRWS_RWS8 (0x1u << 8)
346#define XDMAC_GRWS_RWS9 (0x1u << 9)
347#define XDMAC_GRWS_RWS10 (0x1u << 10)
348#define XDMAC_GRWS_RWS11 (0x1u << 11)
349#define XDMAC_GRWS_RWS12 (0x1u << 12)
350#define XDMAC_GRWS_RWS13 (0x1u << 13)
351#define XDMAC_GRWS_RWS14 (0x1u << 14)
352#define XDMAC_GRWS_RWS15 (0x1u << 15)
353#define XDMAC_GRWS_RWS16 (0x1u << 16)
354#define XDMAC_GRWS_RWS17 (0x1u << 17)
355#define XDMAC_GRWS_RWS18 (0x1u << 18)
356#define XDMAC_GRWS_RWS19 (0x1u << 19)
357#define XDMAC_GRWS_RWS20 (0x1u << 20)
358#define XDMAC_GRWS_RWS21 (0x1u << 21)
359#define XDMAC_GRWS_RWS22 (0x1u << 22)
360#define XDMAC_GRWS_RWS23 (0x1u << 23)
361/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */
362#define XDMAC_GRWR_RWR0 (0x1u << 0)
363#define XDMAC_GRWR_RWR1 (0x1u << 1)
364#define XDMAC_GRWR_RWR2 (0x1u << 2)
365#define XDMAC_GRWR_RWR3 (0x1u << 3)
366#define XDMAC_GRWR_RWR4 (0x1u << 4)
367#define XDMAC_GRWR_RWR5 (0x1u << 5)
368#define XDMAC_GRWR_RWR6 (0x1u << 6)
369#define XDMAC_GRWR_RWR7 (0x1u << 7)
370#define XDMAC_GRWR_RWR8 (0x1u << 8)
371#define XDMAC_GRWR_RWR9 (0x1u << 9)
372#define XDMAC_GRWR_RWR10 (0x1u << 10)
373#define XDMAC_GRWR_RWR11 (0x1u << 11)
374#define XDMAC_GRWR_RWR12 (0x1u << 12)
375#define XDMAC_GRWR_RWR13 (0x1u << 13)
376#define XDMAC_GRWR_RWR14 (0x1u << 14)
377#define XDMAC_GRWR_RWR15 (0x1u << 15)
378#define XDMAC_GRWR_RWR16 (0x1u << 16)
379#define XDMAC_GRWR_RWR17 (0x1u << 17)
380#define XDMAC_GRWR_RWR18 (0x1u << 18)
381#define XDMAC_GRWR_RWR19 (0x1u << 19)
382#define XDMAC_GRWR_RWR20 (0x1u << 20)
383#define XDMAC_GRWR_RWR21 (0x1u << 21)
384#define XDMAC_GRWR_RWR22 (0x1u << 22)
385#define XDMAC_GRWR_RWR23 (0x1u << 23)
386/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */
387#define XDMAC_GSWR_SWREQ0 (0x1u << 0)
388#define XDMAC_GSWR_SWREQ1 (0x1u << 1)
389#define XDMAC_GSWR_SWREQ2 (0x1u << 2)
390#define XDMAC_GSWR_SWREQ3 (0x1u << 3)
391#define XDMAC_GSWR_SWREQ4 (0x1u << 4)
392#define XDMAC_GSWR_SWREQ5 (0x1u << 5)
393#define XDMAC_GSWR_SWREQ6 (0x1u << 6)
394#define XDMAC_GSWR_SWREQ7 (0x1u << 7)
395#define XDMAC_GSWR_SWREQ8 (0x1u << 8)
396#define XDMAC_GSWR_SWREQ9 (0x1u << 9)
397#define XDMAC_GSWR_SWREQ10 (0x1u << 10)
398#define XDMAC_GSWR_SWREQ11 (0x1u << 11)
399#define XDMAC_GSWR_SWREQ12 (0x1u << 12)
400#define XDMAC_GSWR_SWREQ13 (0x1u << 13)
401#define XDMAC_GSWR_SWREQ14 (0x1u << 14)
402#define XDMAC_GSWR_SWREQ15 (0x1u << 15)
403#define XDMAC_GSWR_SWREQ16 (0x1u << 16)
404#define XDMAC_GSWR_SWREQ17 (0x1u << 17)
405#define XDMAC_GSWR_SWREQ18 (0x1u << 18)
406#define XDMAC_GSWR_SWREQ19 (0x1u << 19)
407#define XDMAC_GSWR_SWREQ20 (0x1u << 20)
408#define XDMAC_GSWR_SWREQ21 (0x1u << 21)
409#define XDMAC_GSWR_SWREQ22 (0x1u << 22)
410#define XDMAC_GSWR_SWREQ23 (0x1u << 23)
411/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */
412#define XDMAC_GSWS_SWRS0 (0x1u << 0)
413#define XDMAC_GSWS_SWRS1 (0x1u << 1)
414#define XDMAC_GSWS_SWRS2 (0x1u << 2)
415#define XDMAC_GSWS_SWRS3 (0x1u << 3)
416#define XDMAC_GSWS_SWRS4 (0x1u << 4)
417#define XDMAC_GSWS_SWRS5 (0x1u << 5)
418#define XDMAC_GSWS_SWRS6 (0x1u << 6)
419#define XDMAC_GSWS_SWRS7 (0x1u << 7)
420#define XDMAC_GSWS_SWRS8 (0x1u << 8)
421#define XDMAC_GSWS_SWRS9 (0x1u << 9)
422#define XDMAC_GSWS_SWRS10 (0x1u << 10)
423#define XDMAC_GSWS_SWRS11 (0x1u << 11)
424#define XDMAC_GSWS_SWRS12 (0x1u << 12)
425#define XDMAC_GSWS_SWRS13 (0x1u << 13)
426#define XDMAC_GSWS_SWRS14 (0x1u << 14)
427#define XDMAC_GSWS_SWRS15 (0x1u << 15)
428#define XDMAC_GSWS_SWRS16 (0x1u << 16)
429#define XDMAC_GSWS_SWRS17 (0x1u << 17)
430#define XDMAC_GSWS_SWRS18 (0x1u << 18)
431#define XDMAC_GSWS_SWRS19 (0x1u << 19)
432#define XDMAC_GSWS_SWRS20 (0x1u << 20)
433#define XDMAC_GSWS_SWRS21 (0x1u << 21)
434#define XDMAC_GSWS_SWRS22 (0x1u << 22)
435#define XDMAC_GSWS_SWRS23 (0x1u << 23)
436/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */
437#define XDMAC_GSWF_SWF0 (0x1u << 0)
438#define XDMAC_GSWF_SWF1 (0x1u << 1)
439#define XDMAC_GSWF_SWF2 (0x1u << 2)
440#define XDMAC_GSWF_SWF3 (0x1u << 3)
441#define XDMAC_GSWF_SWF4 (0x1u << 4)
442#define XDMAC_GSWF_SWF5 (0x1u << 5)
443#define XDMAC_GSWF_SWF6 (0x1u << 6)
444#define XDMAC_GSWF_SWF7 (0x1u << 7)
445#define XDMAC_GSWF_SWF8 (0x1u << 8)
446#define XDMAC_GSWF_SWF9 (0x1u << 9)
447#define XDMAC_GSWF_SWF10 (0x1u << 10)
448#define XDMAC_GSWF_SWF11 (0x1u << 11)
449#define XDMAC_GSWF_SWF12 (0x1u << 12)
450#define XDMAC_GSWF_SWF13 (0x1u << 13)
451#define XDMAC_GSWF_SWF14 (0x1u << 14)
452#define XDMAC_GSWF_SWF15 (0x1u << 15)
453#define XDMAC_GSWF_SWF16 (0x1u << 16)
454#define XDMAC_GSWF_SWF17 (0x1u << 17)
455#define XDMAC_GSWF_SWF18 (0x1u << 18)
456#define XDMAC_GSWF_SWF19 (0x1u << 19)
457#define XDMAC_GSWF_SWF20 (0x1u << 20)
458#define XDMAC_GSWF_SWF21 (0x1u << 21)
459#define XDMAC_GSWF_SWF22 (0x1u << 22)
460#define XDMAC_GSWF_SWF23 (0x1u << 23)
461/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */
462#define XDMAC_CIE_BIE (0x1u << 0)
463#define XDMAC_CIE_LIE (0x1u << 1)
464#define XDMAC_CIE_DIE (0x1u << 2)
465#define XDMAC_CIE_FIE (0x1u << 3)
466#define XDMAC_CIE_RBIE (0x1u << 4)
467#define XDMAC_CIE_WBIE (0x1u << 5)
468#define XDMAC_CIE_ROIE (0x1u << 6)
469/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */
470#define XDMAC_CID_BID (0x1u << 0)
471#define XDMAC_CID_LID (0x1u << 1)
472#define XDMAC_CID_DID (0x1u << 2)
473#define XDMAC_CID_FID (0x1u << 3)
474#define XDMAC_CID_RBEID (0x1u << 4)
475#define XDMAC_CID_WBEID (0x1u << 5)
476#define XDMAC_CID_ROID (0x1u << 6)
477/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */
478#define XDMAC_CIM_BIM (0x1u << 0)
479#define XDMAC_CIM_LIM (0x1u << 1)
480#define XDMAC_CIM_DIM (0x1u << 2)
481#define XDMAC_CIM_FIM (0x1u << 3)
482#define XDMAC_CIM_RBEIM (0x1u << 4)
483#define XDMAC_CIM_WBEIM (0x1u << 5)
484#define XDMAC_CIM_ROIM (0x1u << 6)
485/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */
486#define XDMAC_CIS_BIS (0x1u << 0)
487#define XDMAC_CIS_LIS (0x1u << 1)
488#define XDMAC_CIS_DIS (0x1u << 2)
489#define XDMAC_CIS_FIS (0x1u << 3)
490#define XDMAC_CIS_RBEIS (0x1u << 4)
491#define XDMAC_CIS_WBEIS (0x1u << 5)
492#define XDMAC_CIS_ROIS (0x1u << 6)
493/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */
494#define XDMAC_CSA_SA_Pos 0
495#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos)
496#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos)))
497/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */
498#define XDMAC_CDA_DA_Pos 0
499#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos)
500#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos)))
501/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */
502#define XDMAC_CNDA_NDAIF (0x1u << 0)
503#define XDMAC_CNDA_NDA_Pos 2
504#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos)
505#define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos)))
506/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */
507#define XDMAC_CNDC_NDE (0x1u << 0)
508#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0)
509#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0)
510#define XDMAC_CNDC_NDSUP (0x1u << 1)
511#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1)
512#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1)
513#define XDMAC_CNDC_NDDUP (0x1u << 2)
514#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2)
515#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2)
516#define XDMAC_CNDC_NDVIEW_Pos 3
517#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos)
518#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos)))
519#define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3)
520#define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3)
521#define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3)
522#define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3)
523/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */
524#define XDMAC_CUBC_UBLEN_Pos 0
525#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos)
526#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos)))
527/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */
528#define XDMAC_CBC_BLEN_Pos 0
529#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos)
530#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos)))
531/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */
532#define XDMAC_CC_TYPE (0x1u << 0)
533#define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0)
534#define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0)
535#define XDMAC_CC_MBSIZE_Pos 1
536#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos)
537#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos)))
538#define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1)
539#define XDMAC_CC_MBSIZE_FOUR (0x1u << 1)
540#define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1)
541#define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1)
542#define XDMAC_CC_DSYNC (0x1u << 4)
543#define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4)
544#define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4)
545#define XDMAC_CC_SWREQ (0x1u << 6)
546#define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6)
547#define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6)
548#define XDMAC_CC_MEMSET (0x1u << 7)
549#define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7)
550#define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7)
551#define XDMAC_CC_CSIZE_Pos 8
552#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos)
553#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos)))
554#define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8)
555#define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8)
556#define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8)
557#define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8)
558#define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8)
559#define XDMAC_CC_DWIDTH_Pos 11
560#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos)
561#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos)))
562#define XDMAC_CC_DWIDTH_BYTE (0x0u << 11)
563#define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11)
564#define XDMAC_CC_DWIDTH_WORD (0x2u << 11)
565#define XDMAC_CC_SIF (0x1u << 13)
566#define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13)
567#define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13)
568#define XDMAC_CC_DIF (0x1u << 14)
569#define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14)
570#define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14)
571#define XDMAC_CC_SAM_Pos 16
572#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos)
573#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos)))
574#define XDMAC_CC_SAM_FIXED_AM (0x0u << 16)
575#define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16)
576#define XDMAC_CC_SAM_UBS_AM (0x2u << 16)
577#define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16)
578#define XDMAC_CC_DAM_Pos 18
579#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos)
580#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos)))
581#define XDMAC_CC_DAM_FIXED_AM (0x0u << 18)
582#define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18)
583#define XDMAC_CC_DAM_UBS_AM (0x2u << 18)
584#define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18)
585#define XDMAC_CC_INITD (0x1u << 21)
586#define XDMAC_CC_INITD_TERMINATED (0x0u << 21)
587#define XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21)
588#define XDMAC_CC_RDIP (0x1u << 22)
589#define XDMAC_CC_RDIP_DONE (0x0u << 22)
590#define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22)
591#define XDMAC_CC_WRIP (0x1u << 23)
592#define XDMAC_CC_WRIP_DONE (0x0u << 23)
593#define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23)
594#define XDMAC_CC_PERID_Pos 24
595#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos)
596#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos)))
597/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */
598#define XDMAC_CDS_MSP_SDS_MSP_Pos 0
599#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos)
600#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos)))
601#define XDMAC_CDS_MSP_DDS_MSP_Pos 16
602#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos)
603#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos)))
604/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */
605#define XDMAC_CSUS_SUBS_Pos 0
606#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos)
607#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos)))
608/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */
609#define XDMAC_CDUS_DUBS_Pos 0
610#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos)
611#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos)))
612
616#endif /* _SAMS70_XDMAC_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
XdmacChid
XdmacChid hardware registers.
Definition: component_xdmac.h:41
Xdmac
Definition: component_xdmac.h:60