RTEMS: bsps/arm/atsam/include/libchip/include/sams70/component/component_hsmci.h Source File

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component_hsmci.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70_HSMCI_COMPONENT_
31#define _SAMS70_HSMCI_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __O uint32_t HSMCI_CR;
43 __IO uint32_t HSMCI_MR;
44 __IO uint32_t HSMCI_DTOR;
45 __IO uint32_t HSMCI_SDCR;
46 __IO uint32_t HSMCI_ARGR;
47 __O uint32_t HSMCI_CMDR;
48 __IO uint32_t HSMCI_BLKR;
49 __IO uint32_t HSMCI_CSTOR;
50 __I uint32_t HSMCI_RSPR[4];
51 __I uint32_t HSMCI_RDR;
52 __O uint32_t HSMCI_TDR;
53 __I uint32_t Reserved1[2];
54 __I uint32_t HSMCI_SR;
55 __O uint32_t HSMCI_IER;
56 __O uint32_t HSMCI_IDR;
57 __I uint32_t HSMCI_IMR;
58 __IO uint32_t HSMCI_DMA;
59 __IO uint32_t HSMCI_CFG;
60 __I uint32_t Reserved2[35];
61 __IO uint32_t HSMCI_WPMR;
62 __I uint32_t HSMCI_WPSR;
63 __I uint32_t Reserved3[69];
64 __IO uint32_t HSMCI_FIFO[256];
65} Hsmci;
66#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
67/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
68#define HSMCI_CR_MCIEN (0x1u << 0)
69#define HSMCI_CR_MCIDIS (0x1u << 1)
70#define HSMCI_CR_PWSEN (0x1u << 2)
71#define HSMCI_CR_PWSDIS (0x1u << 3)
72#define HSMCI_CR_SWRST (0x1u << 7)
73/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
74#define HSMCI_MR_CLKDIV_Pos 0
75#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos)
76#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
77#define HSMCI_MR_PWSDIV_Pos 8
78#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos)
79#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
80#define HSMCI_MR_RDPROOF (0x1u << 11)
81#define HSMCI_MR_WRPROOF (0x1u << 12)
82#define HSMCI_MR_FBYTE (0x1u << 13)
83#define HSMCI_MR_PADV (0x1u << 14)
84#define HSMCI_MR_CLKODD (0x1u << 16)
85/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
86#define HSMCI_DTOR_DTOCYC_Pos 0
87#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos)
88#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
89#define HSMCI_DTOR_DTOMUL_Pos 4
90#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos)
91#define HSMCI_DTOR_DTOMUL(value) ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos)))
92#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4)
93#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4)
94#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4)
95#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4)
96#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4)
97#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4)
98#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4)
99#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4)
100/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
101#define HSMCI_SDCR_SDCSEL_Pos 0
102#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos)
103#define HSMCI_SDCR_SDCSEL(value) ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos)))
104#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0)
105#define HSMCI_SDCR_SDCBUS_Pos 6
106#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos)
107#define HSMCI_SDCR_SDCBUS(value) ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos)))
108#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6)
109#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6)
110#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6)
111/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
112#define HSMCI_ARGR_ARG_Pos 0
113#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos)
114#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
115/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
116#define HSMCI_CMDR_CMDNB_Pos 0
117#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos)
118#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
119#define HSMCI_CMDR_RSPTYP_Pos 6
120#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos)
121#define HSMCI_CMDR_RSPTYP(value) ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos)))
122#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6)
123#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6)
124#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6)
125#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6)
126#define HSMCI_CMDR_SPCMD_Pos 8
127#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos)
128#define HSMCI_CMDR_SPCMD(value) ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos)))
129#define HSMCI_CMDR_SPCMD_STD (0x0u << 8)
130#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8)
131#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8)
132#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8)
133#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8)
134#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8)
135#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8)
136#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8)
137#define HSMCI_CMDR_OPDCMD (0x1u << 11)
138#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11)
139#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11)
140#define HSMCI_CMDR_MAXLAT (0x1u << 12)
141#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12)
142#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12)
143#define HSMCI_CMDR_TRCMD_Pos 16
144#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos)
145#define HSMCI_CMDR_TRCMD(value) ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos)))
146#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16)
147#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16)
148#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16)
149#define HSMCI_CMDR_TRDIR (0x1u << 18)
150#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18)
151#define HSMCI_CMDR_TRDIR_READ (0x1u << 18)
152#define HSMCI_CMDR_TRTYP_Pos 19
153#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos)
154#define HSMCI_CMDR_TRTYP(value) ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos)))
155#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19)
156#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19)
157#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19)
158#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19)
159#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19)
160#define HSMCI_CMDR_IOSPCMD_Pos 24
161#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos)
162#define HSMCI_CMDR_IOSPCMD(value) ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos)))
163#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24)
164#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24)
165#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24)
166#define HSMCI_CMDR_ATACS (0x1u << 26)
167#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26)
168#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26)
169#define HSMCI_CMDR_BOOT_ACK (0x1u << 27)
170/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
171#define HSMCI_BLKR_BCNT_Pos 0
172#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos)
173#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos)))
174#define HSMCI_BLKR_BLKLEN_Pos 16
175#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos)
176#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
177/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
178#define HSMCI_CSTOR_CSTOCYC_Pos 0
179#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos)
180#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
181#define HSMCI_CSTOR_CSTOMUL_Pos 4
182#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos)
183#define HSMCI_CSTOR_CSTOMUL(value) ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos)))
184#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4)
185#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4)
186#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4)
187#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4)
188#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4)
189#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4)
190#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4)
191#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4)
192/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
193#define HSMCI_RSPR_RSP_Pos 0
194#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos)
195/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
196#define HSMCI_RDR_DATA_Pos 0
197#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos)
198/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
199#define HSMCI_TDR_DATA_Pos 0
200#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos)
201#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
202/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
203#define HSMCI_SR_CMDRDY (0x1u << 0)
204#define HSMCI_SR_RXRDY (0x1u << 1)
205#define HSMCI_SR_TXRDY (0x1u << 2)
206#define HSMCI_SR_BLKE (0x1u << 3)
207#define HSMCI_SR_DTIP (0x1u << 4)
208#define HSMCI_SR_NOTBUSY (0x1u << 5)
209#define HSMCI_SR_SDIOIRQA (0x1u << 8)
210#define HSMCI_SR_SDIOWAIT (0x1u << 12)
211#define HSMCI_SR_CSRCV (0x1u << 13)
212#define HSMCI_SR_RINDE (0x1u << 16)
213#define HSMCI_SR_RDIRE (0x1u << 17)
214#define HSMCI_SR_RCRCE (0x1u << 18)
215#define HSMCI_SR_RENDE (0x1u << 19)
216#define HSMCI_SR_RTOE (0x1u << 20)
217#define HSMCI_SR_DCRCE (0x1u << 21)
218#define HSMCI_SR_DTOE (0x1u << 22)
219#define HSMCI_SR_CSTOE (0x1u << 23)
220#define HSMCI_SR_BLKOVRE (0x1u << 24)
221#define HSMCI_SR_FIFOEMPTY (0x1u << 26)
222#define HSMCI_SR_XFRDONE (0x1u << 27)
223#define HSMCI_SR_ACKRCV (0x1u << 28)
224#define HSMCI_SR_ACKRCVE (0x1u << 29)
225#define HSMCI_SR_OVRE (0x1u << 30)
226#define HSMCI_SR_UNRE (0x1u << 31)
227/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
228#define HSMCI_IER_CMDRDY (0x1u << 0)
229#define HSMCI_IER_RXRDY (0x1u << 1)
230#define HSMCI_IER_TXRDY (0x1u << 2)
231#define HSMCI_IER_BLKE (0x1u << 3)
232#define HSMCI_IER_DTIP (0x1u << 4)
233#define HSMCI_IER_NOTBUSY (0x1u << 5)
234#define HSMCI_IER_SDIOIRQA (0x1u << 8)
235#define HSMCI_IER_SDIOWAIT (0x1u << 12)
236#define HSMCI_IER_CSRCV (0x1u << 13)
237#define HSMCI_IER_RINDE (0x1u << 16)
238#define HSMCI_IER_RDIRE (0x1u << 17)
239#define HSMCI_IER_RCRCE (0x1u << 18)
240#define HSMCI_IER_RENDE (0x1u << 19)
241#define HSMCI_IER_RTOE (0x1u << 20)
242#define HSMCI_IER_DCRCE (0x1u << 21)
243#define HSMCI_IER_DTOE (0x1u << 22)
244#define HSMCI_IER_CSTOE (0x1u << 23)
245#define HSMCI_IER_BLKOVRE (0x1u << 24)
246#define HSMCI_IER_FIFOEMPTY (0x1u << 26)
247#define HSMCI_IER_XFRDONE (0x1u << 27)
248#define HSMCI_IER_ACKRCV (0x1u << 28)
249#define HSMCI_IER_ACKRCVE (0x1u << 29)
250#define HSMCI_IER_OVRE (0x1u << 30)
251#define HSMCI_IER_UNRE (0x1u << 31)
252/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
253#define HSMCI_IDR_CMDRDY (0x1u << 0)
254#define HSMCI_IDR_RXRDY (0x1u << 1)
255#define HSMCI_IDR_TXRDY (0x1u << 2)
256#define HSMCI_IDR_BLKE (0x1u << 3)
257#define HSMCI_IDR_DTIP (0x1u << 4)
258#define HSMCI_IDR_NOTBUSY (0x1u << 5)
259#define HSMCI_IDR_SDIOIRQA (0x1u << 8)
260#define HSMCI_IDR_SDIOWAIT (0x1u << 12)
261#define HSMCI_IDR_CSRCV (0x1u << 13)
262#define HSMCI_IDR_RINDE (0x1u << 16)
263#define HSMCI_IDR_RDIRE (0x1u << 17)
264#define HSMCI_IDR_RCRCE (0x1u << 18)
265#define HSMCI_IDR_RENDE (0x1u << 19)
266#define HSMCI_IDR_RTOE (0x1u << 20)
267#define HSMCI_IDR_DCRCE (0x1u << 21)
268#define HSMCI_IDR_DTOE (0x1u << 22)
269#define HSMCI_IDR_CSTOE (0x1u << 23)
270#define HSMCI_IDR_BLKOVRE (0x1u << 24)
271#define HSMCI_IDR_FIFOEMPTY (0x1u << 26)
272#define HSMCI_IDR_XFRDONE (0x1u << 27)
273#define HSMCI_IDR_ACKRCV (0x1u << 28)
274#define HSMCI_IDR_ACKRCVE (0x1u << 29)
275#define HSMCI_IDR_OVRE (0x1u << 30)
276#define HSMCI_IDR_UNRE (0x1u << 31)
277/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
278#define HSMCI_IMR_CMDRDY (0x1u << 0)
279#define HSMCI_IMR_RXRDY (0x1u << 1)
280#define HSMCI_IMR_TXRDY (0x1u << 2)
281#define HSMCI_IMR_BLKE (0x1u << 3)
282#define HSMCI_IMR_DTIP (0x1u << 4)
283#define HSMCI_IMR_NOTBUSY (0x1u << 5)
284#define HSMCI_IMR_SDIOIRQA (0x1u << 8)
285#define HSMCI_IMR_SDIOWAIT (0x1u << 12)
286#define HSMCI_IMR_CSRCV (0x1u << 13)
287#define HSMCI_IMR_RINDE (0x1u << 16)
288#define HSMCI_IMR_RDIRE (0x1u << 17)
289#define HSMCI_IMR_RCRCE (0x1u << 18)
290#define HSMCI_IMR_RENDE (0x1u << 19)
291#define HSMCI_IMR_RTOE (0x1u << 20)
292#define HSMCI_IMR_DCRCE (0x1u << 21)
293#define HSMCI_IMR_DTOE (0x1u << 22)
294#define HSMCI_IMR_CSTOE (0x1u << 23)
295#define HSMCI_IMR_BLKOVRE (0x1u << 24)
296#define HSMCI_IMR_FIFOEMPTY (0x1u << 26)
297#define HSMCI_IMR_XFRDONE (0x1u << 27)
298#define HSMCI_IMR_ACKRCV (0x1u << 28)
299#define HSMCI_IMR_ACKRCVE (0x1u << 29)
300#define HSMCI_IMR_OVRE (0x1u << 30)
301#define HSMCI_IMR_UNRE (0x1u << 31)
302/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */
303#define HSMCI_DMA_CHKSIZE_Pos 4
304#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos)
305#define HSMCI_DMA_CHKSIZE(value) ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos)))
306#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4)
307#define HSMCI_DMA_CHKSIZE_2 (0x1u << 4)
308#define HSMCI_DMA_CHKSIZE_4 (0x2u << 4)
309#define HSMCI_DMA_CHKSIZE_8 (0x3u << 4)
310#define HSMCI_DMA_CHKSIZE_16 (0x4u << 4)
311#define HSMCI_DMA_DMAEN (0x1u << 8)
312/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
313#define HSMCI_CFG_FIFOMODE (0x1u << 0)
314#define HSMCI_CFG_FERRCTRL (0x1u << 4)
315#define HSMCI_CFG_HSMODE (0x1u << 8)
316#define HSMCI_CFG_LSYNC (0x1u << 12)
317/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
318#define HSMCI_WPMR_WPEN (0x1u << 0)
319#define HSMCI_WPMR_WPKEY_Pos 8
320#define HSMCI_WPMR_WPKEY_Msk (0xffffffu << HSMCI_WPMR_WPKEY_Pos)
321#define HSMCI_WPMR_WPKEY(value) ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos)))
322#define HSMCI_WPMR_WPKEY_PASSWD (0x4D4349u << 8)
323/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
324#define HSMCI_WPSR_WPVS (0x1u << 0)
325#define HSMCI_WPSR_WPVSRC_Pos 8
326#define HSMCI_WPSR_WPVSRC_Msk (0xffffu << HSMCI_WPSR_WPVSRC_Pos)
327/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
328#define HSMCI_FIFO_DATA_Pos 0
329#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos)
330#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))
331
335#endif /* _SAMS70_HSMCI_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Hsmci
Hsmci hardware registers.
Definition: component_hsmci.h:41