RTEMS: bsps/arm/csb337/include/at91rm9200_gpio.h Source File

| RTEMS 5.4-rc2

Loading...
Searching...
No Matches
at91rm9200_gpio.h
Go to the documentation of this file.
1
9/*
10 * AT91RM9200 GPIO definitions
11 *
12 * Copyright (c) 2002 by Cogent Computer Systems
13 * Written by Mike Kelly <mike@cogcomp.com>
14 *
15 * The license and distribution terms for this file may be
16 * found in the file LICENSE in this distribution or at
17 * http://www.rtems.org/license/LICENSE.
18 */
19#ifndef AT91RM9200_GPIO_H
20#define AT91RM9200_GPIO_H
21
22#include <bits.h>
23
24/* Register Offsets */
25#define PIO_PER 0x00 /* PIO Enable Register */
26#define PIO_PDR 0x04 /* PIO Disable Register */
27#define PIO_PSR 0x08 /* PIO Status Register */
28#define PIO_OER 0x10 /* Output Enable Register */
29#define PIO_ODR 0x14 /* Output Disable Registerr */
30#define PIO_OSR 0x18 /* Output Status Register */
31#define PIO_IFER 0x20 /* Input Filter Enable Register */
32#define PIO_IFDR 0x24 /* Input Filter Disable Register */
33#define PIO_IFSR 0x28 /* Input Filter Status Register */
34#define PIO_SODR 0x30 /* Set Output Data Register */
35#define PIO_CODR 0x34 /* Clear Output Data Register */
36#define PIO_ODSR 0x38 /* Output Data Status Register */
37#define PIO_PDSR 0x3c /* Pin Data Status Register */
38#define PIO_IER 0x40 /* Interrupt Enable Register */
39#define PIO_IDR 0x44 /* Interrupt Disable Register */
40#define PIO_IMR 0x48 /* Interrupt Mask Register */
41#define PIO_ISR 0x4c /* Interrupt Status Register */
42#define PIO_MDER 0x50 /* Multi-driver Enable Register */
43#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
44#define PIO_MDSR 0x58 /* Multi-driver Status Register */
45#define PIO_PUDR 0x60 /* Pull-up Disable Register */
46#define PIO_PUER 0x64 /* Pull-up Enable Register */
47#define PIO_PUSR 0x68 /* Pad Pull-up Status Register */
48#define PIO_ASR 0x70 /* Select A Register */
49#define PIO_BSR 0x74 /* Select B Register */
50#define PIO_ABSR 0x78 /* AB Select Status Register */
51#define PIO_OWER 0xA0 /* Output Write Enable Register */
52#define PIO_OWDR 0xA4 /* Output Write Disable Register */
53#define PIO_OWSR 0xA8 /* Output Write Status Register */
54
55
56/*
57 * The AT91RM9200 GPIO's are spread across four 32-bit ports A-D.
58 * To make it easier to interface with them and to eliminate the need
59 * to track which GPIO is in which port, we convert the Port x, Bit y
60 * into a single GPIO number 0 - 127.
61 *
62 * Board specific defines will assign the board level signal to a
63 * virutal GPIO.
64 *
65 * PORT A
66 */
67#define GPIO_0 BIT0
68#define GPIO_1 BIT1
69#define GPIO_2 BIT2
70#define GPIO_3 BIT3
71#define GPIO_4 BIT4
72#define GPIO_5 BIT5
73#define GPIO_6 BIT6
74#define GPIO_7 BIT7
75#define GPIO_8 BIT8
76#define GPIO_9 BIT9
77#define GPIO_10 BIT10
78#define GPIO_11 BIT11
79#define GPIO_12 BIT12
80#define GPIO_13 BIT13
81#define GPIO_14 BIT14
82#define GPIO_15 BIT15
83#define GPIO_16 BIT16
84#define GPIO_17 BIT17
85#define GPIO_18 BIT18
86#define GPIO_19 BIT19
87#define GPIO_20 BIT20
88#define GPIO_21 BIT21
89#define GPIO_22 BIT22
90#define GPIO_23 BIT23
91#define GPIO_24 BIT24
92#define GPIO_25 BIT25
93#define GPIO_26 BIT26
94#define GPIO_27 BIT27
95#define GPIO_28 BIT28
96#define GPIO_29 BIT29
97#define GPIO_30 BIT30
98#define GPIO_31 BIT31
99/* PORT B */
100#define GPIO_32 BIT0
101#define GPIO_33 BIT1
102#define GPIO_34 BIT2
103#define GPIO_35 BIT3
104#define GPIO_36 BIT4
105#define GPIO_37 BIT5
106#define GPIO_38 BIT6
107#define GPIO_39 BIT7
108#define GPIO_40 BIT8
109#define GPIO_41 BIT9
110#define GPIO_42 BIT10
111#define GPIO_43 BIT11
112#define GPIO_44 BIT12
113#define GPIO_45 BIT13
114#define GPIO_46 BIT14
115#define GPIO_47 BIT15
116#define GPIO_48 BIT16
117#define GPIO_49 BIT17
118#define GPIO_50 BIT18
119#define GPIO_51 BIT19
120#define GPIO_52 BIT20
121#define GPIO_53 BIT21
122#define GPIO_54 BIT22
123#define GPIO_55 BIT23
124#define GPIO_56 BIT24
125#define GPIO_57 BIT25
126#define GPIO_58 BIT26
127#define GPIO_59 BIT27
128#define GPIO_60 BIT28
129#define GPIO_61 BIT29
130#define GPIO_62 BIT30
131#define GPIO_63 BIT31
132/* PORT C */
133#define GPIO_64 BIT0
134#define GPIO_65 BIT1
135#define GPIO_66 BIT2
136#define GPIO_67 BIT3
137#define GPIO_68 BIT4
138#define GPIO_69 BIT5
139#define GPIO_70 BIT6
140#define GPIO_71 BIT7
141#define GPIO_72 BIT8
142#define GPIO_73 BIT9
143#define GPIO_74 BIT10
144#define GPIO_75 BIT11
145#define GPIO_76 BIT12
146#define GPIO_77 BIT13
147#define GPIO_78 BIT14
148#define GPIO_79 BIT15
149#define GPIO_80 BIT16
150#define GPIO_81 BIT17
151#define GPIO_82 BIT18
152#define GPIO_83 BIT19
153#define GPIO_84 BIT20
154#define GPIO_85 BIT21
155#define GPIO_86 BIT22
156#define GPIO_87 BIT23
157#define GPIO_88 BIT24
158#define GPIO_89 BIT25
159#define GPIO_90 BIT26
160#define GPIO_91 BIT27
161#define GPIO_92 BIT28
162#define GPIO_93 BIT29
163#define GPIO_94 BIT30
164#define GPIO_95 BIT31
165/* PORT D */
166#define GPIO_96 BIT0
167#define GPIO_97 BIT1
168#define GPIO_98 BIT2
169#define GPIO_99 BIT3
170#define GPIO_100 BIT4
171#define GPIO_101 BIT5
172#define GPIO_102 BIT6
173#define GPIO_103 BIT7
174#define GPIO_104 BIT8
175#define GPIO_105 BIT9
176#define GPIO_106 BIT10
177#define GPIO_107 BIT11
178#define GPIO_108 BIT12
179#define GPIO_109 BIT13
180#define GPIO_110 BIT14
181#define GPIO_111 BIT15
182#define GPIO_112 BIT16
183#define GPIO_113 BIT17
184#define GPIO_114 BIT18
185#define GPIO_115 BIT19
186#define GPIO_116 BIT20
187#define GPIO_117 BIT21
188#define GPIO_118 BIT22
189#define GPIO_119 BIT23
190#define GPIO_120 BIT24
191#define GPIO_121 BIT25
192#define GPIO_122 BIT26
193#define GPIO_123 BIT27
194#define GPIO_124 BIT28
195#define GPIO_125 BIT29
196#define GPIO_126 BIT30
197#define GPIO_127 BIT31
198
199/*
200 * Most of the GPIO pins can have one of two alternate functions
201 * in addition to being GPIO
202 *
203 * Port A, Alternate Function A
204 */
205#define PIOA_ASR_MISO BIT0 /* SPI Master In (RX), Slave out */
206#define PIOA_ASR_MOSI BIT1 /* SPI Master Out (TX), Slave In */
207#define PIOA_ASR_SPCK BIT2 /* SPI Clock */
208#define PIOA_ASR_NPCS0 BIT3 /* SPI Chip Select 0 */
209#define PIOA_ASR_NPCS1 BIT4 /* SPI Chip Select 1 */
210#define PIOA_ASR_NPCS2 BIT5 /* SPI Chip Select 2 */
211#define PIOA_ASR_NPCS3 BIT6 /* SPI Chip Select 3 */
212#define PIOA_ASR_ETXCK BIT7 /* EMAC TX Clock */
213#define PIOA_ASR_ETXEN BIT8 /* EMAC TXEN */
214#define PIOA_ASR_ETX0 BIT9 /* EMAC TXD0 */
215#define PIOA_ASR_ETX1 BIT10 /* EMAC TXD1 */
216#define PIOA_ASR_ECRS BIT11 /* EMAC CRS */
217#define PIOA_ASR_ERX0 BIT12 /* EMAC RXD0 */
218#define PIOA_ASR_ERX1 BIT13 /* EMAC RXD1 */
219#define PIOA_ASR_ERXER BIT14 /* EMAC RXER */
220#define PIOA_ASR_EMDC BIT15 /* EMAC MDC */
221#define PIOA_ASR_EMDIO BIT16 /* EMAC MDIO */
222#define PIOA_ASR_TXD0 BIT17 /* USART 0 Receive */
223#define PIOA_ASR_RXD0 BIT18 /* USART 0 Transmit */
224#define PIOA_ASR_SCK0 BIT19 /* USART 0 Clock */
225#define PIOA_ASR_CTS0 BIT20 /* USART 0 CTS */
226#define PIOA_ASR_RTS0 BIT21 /* USART 0 RTS */
227#define PIOA_ASR_RXD2 BIT22 /* USART 2 Receive */
228#define PIOA_ASR_TXD2 BIT23 /* USART 2 Transmit */
229#define PIOA_ASR_SCK2 BIT24 /* USART 2 Clock */
230#define PIOA_ASR_TWD BIT25 /* Two-Wire (I2C) Data */
231#define PIOA_ASR_TWCK BIT26 /* Two-Wire (I2C) Clock */
232#define PIOA_ASR_MCCK BIT27 /* MMC/SD Card Clock */
233#define PIOA_ASR_MCCDA BIT28 /* MMC/SD Card A Command */
234#define PIOA_ASR_MCDA0 BIT29 /* MMC/SD Card A Data 0 */
235#define PIOA_ASR_DRXD BIT30 /* Debug Uart Receive */
236#define PIOA_ASR_DTXD BIT31 /* Debug Uart Transmit */
237
238/* Port A, Alternate Function B */
239#define PIOA_BSR_PCK3 BIT0 /* Peripheral Clock 3 */
240#define PIOA_BSR_PCK0 BIT1 /* Peripheral Clock 0 */
241#define PIOA_BSR_IRQ4 BIT2 /* IRQ4 */
242#define PIOA_BSR_IRQ5 BIT3 /* IRQ5 */
243/*#define PIOA_BSR_PCK1 BIT4 Peripheral Clock 1 ***DUPLICATED at BIT24 ??? */
244#define PIOA_BSR_TXD3 BIT5 /* USART 3 Transmit */
245#define PIOA_BSR_RXD3 BIT6 /* USART 3 Receive */
246#define PIOA_BSR_PCK2 BIT7 /* Peripheral Clock 2 */
247#define PIOA_BSR_MCCDB BIT8 /* MMC/SD Card B Command */
248#define PIOA_BSR_MCDB0 BIT9 /* MMC/SD Card B Data 0 */
249#define PIOA_BSR_MCDB1 BIT10 /* MMC/SD Card B Data 1 */
250#define PIOA_BSR_MCDB2 BIT11 /* MMC/SD Card B Data 2 */
251#define PIOA_BSR_MCDB3 BIT12 /* MMC/SD C ard B Data 3 */
252#define PIOA_BSR_TCLK0 BIT13 /* Timer 0 Clock */
253#define PIOA_BSR_TCLK1 BIT14 /* Timer 1 Clck */
254#define PIOA_BSR_TCLK2 BIT15 /* Timer 2 Clock */
255#define PIOA_BSR_IRQ6 BIT16 /* IRQ6 */
256#define PIOA_BSR_TIOA0 BIT17 /* Timer 0 I/O A */
257#define PIOA_BSR_TIOB0 BIT18 /* Timer 0 I/O B */
258#define PIOA_BSR_TIOA1 BIT19 /* Timer 1 I/O A */
259#define PIOA_BSR_TIOB1 BIT20 /* Timer 1 I/O B */
260#define PIOA_BSR_TIOA2 BIT21 /* Timer 2 I/O A */
261#define PIOA_BSR_TIOB2 BIT22 /* Timer 2 I/O B */
262#define PIOA_BSR_IRQ3 BIT23 /* IRQ3 */
263#define PIOA_BSR_PCK1 BIT24 /* Peripheral Clock 1 */
264#define PIOA_BSR_IRQ2 BIT25 /* IRQ2 */
265#define PIOA_BSR_IRQ1 BIT26 /* IRQ1 */
266#define PIOA_BSR_TCLK3 BIT27 /* Timer Block Clock 3 (docs only show 0-2?) */
267#define PIOA_BSR_TCLK4 BIT28 /* Timer Block Clock 4 */
268#define PIOA_BSR_TCLK5 BIT29 /* Timer Block Clock 5 */
269#define PIOA_BSR_CTS2 BIT30 /* USART 2 CTS */
270#define PIOA_BSR_RTS2 BIT31 /* USART 2 RTS */
271
272/* Port B, Function A */
273#define PIOB_ASR_TF0 BIT0 /* AC'97/I2S 0 Transmit Frame */
274#define PIOB_ASR_TK0 BIT1 /* AC'97/I2S 0 Transmit Clock */
275#define PIOB_ASR_TD0 BIT2 /* AC'97/I2S 0 Transmit Data */
276#define PIOB_ASR_RD0 BIT3 /* AC'97/I2S 0 Receive Data */
277#define PIOB_ASR_RK0 BIT4 /* AC'97/I2S 0 Receive Clock */
278#define PIOB_ASR_RF0 BIT5 /* AC'97/I2S 0 Receive Frame */
279#define PIOB_ASR_TF1 BIT6 /* AC'97/I2S 1 Transmit Frame */
280#define PIOB_ASR_TK1 BIT7 /* AC'97/I2S 1 Transmit Clock */
281#define PIOB_ASR_TD1 BIT8 /* AC'97/I2S 1 Transmit Data */
282#define PIOB_ASR_RD1 BIT9 /* AC'97/I2S 1 Receive Data */
283#define PIOB_ASR_RK1 BIT10 /* AC'97/I2S 1 Receive Clock */
284#define PIOB_ASR_RF1 BIT11 /* AC'97/I2S 1 Receive Frame */
285#define PIOB_ASR_TF2 BIT12 /* AC'97/I2S 1 Transmit Frame */
286#define PIOB_ASR_TK2 BIT13 /* AC'97/I2S 1 Transmit Clock */
287#define PIOB_ASR_TD2 BIT14 /* AC'97/I2S 1 Transmit Data */
288#define PIOB_ASR_RD2 BIT15 /* AC'97/I2S 1 Receive Data */
289#define PIOB_ASR_RK2 BIT16 /* AC'97/I2S 1 Receive Clock */
290#define PIOB_ASR_RF2 BIT17 /* AC'97/I2S 1 Receive Frame */
291#define PIOB_ASR_RI1 BIT18 /* USART 1 RI */
292#define PIOB_ASR_DTR1 BIT19 /* USART 1 DTR */
293#define PIOB_ASR_TXD1 BIT20 /* USART 1 TXD */
294#define PIOB_ASR_RXD1 BIT21 /* USART 1 RXD */
295#define PIOB_ASR_SCK1 BIT22 /* USART 1 SCK */
296#define PIOB_ASR_DCD1 BIT23 /* USART 1 DCD */
297#define PIOB_ASR_CTS1 BIT24 /* USART 1 CTS */
298#define PIOB_ASR_DSR1 BIT25 /* USART 1 DSR */
299#define PIOB_ASR_RTS1 BIT26 /* USART 1 RTS */
300#define PIOB_ASR_PCK0 BIT27 /* Peripheral Clock 0 */
301#define PIOB_ASR_FIQ BIT28 /* FIQ */
302#define PIOB_ASR_IRQ0 BIT29 /* IRQ0 */
303
304/* Port B, Function B */
305#define PIOB_BSR_RTS3 BIT0 /* USART 3 */
306#define PIOB_BSR_CTS3 BIT1 /* USART 3 */
307#define PIOB_BSR_SCK3 BIT2 /* USART 3 */
308#define PIOB_BSR_MCDA1 BIT3 /* MMC/SD Card A, Data 1 */
309#define PIOB_BSR_MCDA2 BIT4 /* MMC/SD Card A, Data 2 */
310#define PIOB_BSR_MCDA3 BIT5 /* MMC/SD Card A, Data 3 */
311#define PIOB_BSR_TIOA3 BIT6 /* Timer 3 IO A */
312#define PIOB_BSR_TIOB3 BIT7 /* Timer 3 IO B */
313#define PIOB_BSR_TIOA4 BIT8 /* Timer 4 IO A */
314#define PIOB_BSR_TIOB4 BIT9 /* Timer 4 IO B */
315#define PIOB_BSR_TIOA5 BIT10 /* Timer 5 IO A */
316#define PIOB_BSR_TIOB5 BIT11 /* Timer 5 IO B */
317#define PIOB_BSR_ETX2 BIT12 /* EMAC TXD2 */
318#define PIOB_BSR_ETX3 BIT13 /* EMAC TXD3 */
319#define PIOB_BSR_ETXER BIT14 /* EMAC TXER */
320#define PIOB_BSR_ERX2 BIT15 /* EMAC RXD2 */
321#define PIOB_BSR_ERX3 BIT16 /* EMAC RXD3 */
322#define PIOB_BSR_ERXDV BIT17 /* EMAC RXDV */
323#define PIOB_BSR_ECOL BIT18 /* EMAC COL */
324#define PIOB_BSR_ERXCK BIT19 /* EMAC RX Clock */
325#define PIOB_BSR_EF100 BIT25 /* EMAC Speed 100 (RMII Only) */
326
327/* Port C, Alternate Function A */
328#define PIOC_ASR_BFCK BIT0 /* Burst Flash Clock */
329#define PIOC_ASR_BFRDY BIT1 /* Burst Flash Ready or SMC Card OE */
330#define PIOC_ASR_BFAVD BIT2 /* Burst Flash Address Valid */
331#define PIOC_ASR_BFBAA BIT3 /* Burst Flash Address Advance or SMC Card WE */
332#define PIOC_ASR_BFOE BIT4 /* Burst Flash OE */
333#define PIOC_ASR_BFWE BIT5 /* Burst Flash WE */
334#define PIOC_ASR_NWAIT BIT6 /* WAIT Input */
335#define PIOC_ASR_A23 BIT7 /* A23 */
336#define PIOC_ASR_A24 BIT8 /* A24 */
337#define PIOC_ASR_A25 BIT9 /* A25 or Compact Flash R/W */
338#define PIOC_ASR_NCS4 BIT10 /* CS4 or Compact Flash CS */
339#define PIOC_ASR_NCS5 BIT11 /* CS5 or Compact Flash CE1 */
340#define PIOC_ASR_NCS6 BIT12 /* CS6 or Compact Flash CE2 */
341#define PIOC_ASR_NCS7 BIT13 /* CS7 */
342#define PIOC_ASR_D16 BIT16 /* Databus Bit 16 */
343#define PIOC_ASR_D17 BIT17 /* Databus Bit 17 */
344#define PIOC_ASR_D18 BIT18 /* Databus Bit 18 */
345#define PIOC_ASR_D19 BIT19 /* Databus Bit 19 */
346#define PIOC_ASR_D20 BIT20 /* Databus Bit 20 */
347#define PIOC_ASR_D21 BIT21 /* Databus Bit 21 */
348#define PIOC_ASR_D22 BIT22 /* Databus Bit 22 */
349#define PIOC_ASR_D23 BIT23 /* Databus Bit 23 */
350#define PIOC_ASR_D24 BIT24 /* Databus Bit 24 */
351#define PIOC_ASR_D25 BIT25 /* Databus Bit 25 */
352#define PIOC_ASR_D26 BIT26 /* Databus Bit 26 */
353#define PIOC_ASR_D27 BIT27 /* Databus Bit 27 */
354#define PIOC_ASR_D28 BIT28 /* Databus Bit 28 */
355#define PIOC_ASR_D29 BIT29 /* Databus Bit 29 */
356#define PIOC_ASR_D30 BIT30 /* Databus Bit 30 */
357#define PIOC_ASR_D31 BIT31 /* Databus Bit 31 */
358
359/* Port C, Alternate Function B - None */
360
361/* Port D, Alternate Function A */
362#define PIOD_ASR_ETX0 BIT0 /* EMAC TXD0 */
363#define PIOD_ASR_ETX1 BIT1 /* EMAC TXD1 */
364#define PIOD_ASR_ETX2 BIT2 /* EMAC TXD2 */
365#define PIOD_ASR_ETX3 BIT3 /* EMAC TXD3 */
366#define PIOD_ASR_ETXEN BIT4 /* EMAC TXEN */
367#define PIOD_ASR_ETXER BIT5 /* EMAC TXER */
368#define PIOD_ASR_DTXD BIT6 /* Debug UART Transmit */
369#define PIOD_ASR_PCK0 BIT7 /* Peripheral Clock 0 */
370#define PIOD_ASR_PCK1 BIT8 /* Peripheral Clock 1 */
371#define PIOD_ASR_PCK2 BIT9 /* Peripheral Clock 2 */
372#define PIOD_ASR_PCK3 BIT10 /* Peripheral Clock 3 */
373#define PIOD_ASR_TD0 BIT15 /* AC'97/I2S 0 Transmit Data */
374#define PIOD_ASR_TD1 BIT16 /* AC'97/I2S 1 Transmit Data */
375#define PIOD_ASR_TD2 BIT17 /* AC'97/I2S 2 Transmit Data */
376#define PIOD_ASR_NPCS1 BIT18 /* SPI Chip Select 1 */
377#define PIOD_ASR_NPCS2 BIT19 /* SPI Chip Select 2 */
378#define PIOD_ASR_NPCS3 BIT20 /* SPI Chip Select 3 */
379#define PIOD_ASR_RTS0 BIT21 /* USART 0 RTS */
380#define PIOD_ASR_RTS1 BIT22 /* USART 1 RTS */
381#define PIOD_ASR_RTS2 BIT23 /* USART 2 RTS */
382#define PIOD_ASR_RTS3 BIT24 /* USART 3 RTS */
383#define PIOD_ASR_DTR1 BIT25 /* USART 1 DTR */
384
385/* Port D, Alternate Function B */
386
387#define PIOC_ASR_TSYNC BIT7 /* ETM Sync */
388#define PIOC_ASR_TCLK BIT8 /* ETM Clock */
389#define PIOC_ASR_TPS0 BIT9 /* ETM Processor Status 0 */
390#define PIOC_ASR_TPS1 BIT10 /* ETM Processor Status 1 */
391#define PIOC_ASR_TPS2 BIT11 /* ETM Processor Status 2 */
392#define PIOC_ASR_TPK0 BIT12 /* ETM Packet Data 0 */
393#define PIOC_ASR_TPK1 BIT13 /* ETM Packet Data 1 */
394#define PIOC_ASR_TPK2 BIT14 /* ETM Packet Data 2 */
395#define PIOC_ASR_TPK3 BIT15 /* ETM Packet Data 3 */
396#define PIOC_ASR_TPK4 BIT16 /* ETM Packet Data 4 */
397#define PIOC_ASR_TPK5 BIT17 /* ETM Packet Data 5 */
398#define PIOC_ASR_TPK6 BIT18 /* ETM Packet Data 6 */
399#define PIOC_ASR_TPK7 BIT19 /* ETM Packet Data 7 */
400#define PIOC_ASR_TPK8 BIT20 /* ETM Packet Data 8 */
401#define PIOC_ASR_TPK9 BIT21 /* ETM Packet Data 9 */
402#define PIOC_ASR_TPK10 BIT22 /* ETM Packet Data 10 */
403#define PIOC_ASR_TPK11 BIT23 /* ETM Packet Data 11 */
404#define PIOC_ASR_TPK12 BIT24 /* ETM Packet Data 12 */
405#define PIOC_ASR_TPK13 BIT25 /* ETM Packet Data 13 */
406#define PIOC_ASR_TPK14 BIT26 /* ETM Packet Data 14 */
407#define PIOC_ASR_TPK15 BIT27 /* ETM Packet Data 15 */
408
409#endif
bits.h
Contains Defined Bits.