RTEMS: bsps/include/libchip/if_fxpvar.h Source File

| RTEMS 5.4-rc2

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if_fxpvar.h
1/*
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/fxp/if_fxpvar.h,v 1.17.2.3 2001/06/08 20:36:58 jlemon Exp $
28 */
29
30/*
31 * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast
32 * Ethernet driver
33 */
34
35/*
36 * Number of transmit control blocks. This determines the number
37 * of transmit buffers that can be chained in the CB list.
38 * This must be a power of two.
39 */
40#define FXP_NTXCB 128
41
42/*
43 * Number of completed TX commands at which point an interrupt
44 * will be generated to garbage collect the attached buffers.
45 * Must be at least one less than FXP_NTXCB, and should be
46 * enough less so that the transmitter doesn't becomes idle
47 * during the buffer rundown (which would reduce performance).
48 */
49#define FXP_CXINT_THRESH 120
50
51/*
52 * TxCB list index mask. This is used to do list wrap-around.
53 */
54#define FXP_TXCB_MASK (FXP_NTXCB - 1)
55
56/*
57 * Number of receive frame area buffers. These are large so chose
58 * wisely.
59 */
60#if 0
61#define FXP_NRFABUFS 64
62#else
63#define FXP_NRFABUFS 16
64#endif
65/*
66 * Maximum number of seconds that the receiver can be idle before we
67 * assume it's dead and attempt to reset it by reprogramming the
68 * multicast filter. This is part of a work-around for a bug in the
69 * NIC. See fxp_stats_update().
70 */
71#define FXP_MAX_RX_IDLE 15
72
73#if __FreeBSD_version < 500000
74#define FXP_LOCK(_sc)
75#define FXP_UNLOCK(_sc)
76#define mtx_init(a, b, c)
77#define mtx_destroy(a)
78 struct mtx { int dummy; };
79#else
80#define FXP_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
81#define FXP_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
82#endif
83
84#ifdef __alpha__
85#undef vtophys
86#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
87#endif /* __alpha__ */
88
89/*
90 * NOTE: Elements are ordered for optimal cacheline behavior, and NOT
91 * for functional grouping.
92 */
93 struct fxp_softc {
94 struct arpcom arpcom; /* per-interface network data */
95#ifdef NOTUSED
96 struct resource *mem; /* resource descriptor for registers */
97 int rtp; /* register resource type */
98 int rgd; /* register descriptor in use */
99 struct resource *irq; /* resource descriptor for interrupt */
100#endif
101 void *ih; /* interrupt handler cookie */
102 struct mtx sc_mtx;
103#ifdef NOTUSED /* change for RTEMS */
104 bus_space_tag_t sc_st; /* bus space tag */
105 bus_space_handle_t sc_sh; /* bus space handle */
106#else
107 unsigned char pci_bus; /* RTEMS PCI bus number */
108 unsigned char pci_dev; /* RTEMS PCI slot/device number */
109 unsigned char pci_fun; /* RTEMS PCI function number */
110 bool pci_regs_are_io; /* RTEMS dev regs are I/O mapped */
111 u_int32_t pci_regs_base; /* RTEMS i386 register base */
112 rtems_id daemonTid; /* Task ID of deamon */
113 rtems_vector_number irq_num;
114
115#endif
116 struct mbuf *rfa_headm; /* first mbuf in receive frame area */
117 struct mbuf *rfa_tailm; /* last mbuf in receive frame area */
118 struct fxp_cb_tx *cbl_first; /* first active TxCB in list */
119 int tx_queued; /* # of active TxCB's */
120 int need_mcsetup; /* multicast filter needs programming */
121 struct fxp_cb_tx *cbl_last; /* last active TxCB in list */
122 struct fxp_stats *fxp_stats; /* Pointer to interface stats */
123 int rx_idle_secs; /* # of seconds RX has been idle */
124 enum {fxp_timeout_stopped,fxp_timeout_running,fxp_timeout_stop_rq}
125 stat_ch; /* status of status updater */
126 struct fxp_cb_tx *cbl_base; /* base of TxCB list */
127 struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */
128#ifdef NOTUSED
129 struct ifmedia sc_media; /* media information */
130 device_t miibus;
131 device_t dev;
132#endif
133 int eeprom_size; /* size of serial EEPROM */
134 int suspended; /* 0 = normal 1 = suspended (APM) */
135 int cu_resume_bug;
136 int chip;
137 int flags;
138 u_int32_t saved_maps[5]; /* pci data */
139 u_int32_t saved_biosaddr;
140 u_int8_t saved_intline;
141 u_int8_t saved_cachelnsz;
142 u_int8_t saved_lattimer;
143};
144
145#define FXP_CHIP_82557 1 /* 82557 chip type */
146
147#define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */
148#define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */
149#define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */
150#define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */
151#define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */
152#define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */
153#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */
154#define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */
155
156/* Macros to ease CSR access. */
157#if 0
158#define CSR_READ_1(sc, reg) \
159 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
160#define CSR_READ_2(sc, reg) \
161 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
162#define CSR_READ_4(sc, reg) \
163 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
164#define CSR_WRITE_1(sc, reg, val) \
165 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
166#define CSR_WRITE_2(sc, reg, val) \
167 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
168#define CSR_WRITE_4(sc, reg, val) \
169 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
170#else
171#define CSR_READ_1(sc, reg) fxp_csr_read_1(sc,reg)
172#define CSR_READ_2(sc, reg) fxp_csr_read_2(sc,reg)
173#define CSR_READ_4(sc, reg) fxp_csr_read_4(sc,reg)
174
175#define CSR_WRITE_1(sc, reg, val) \
176 do { \
177 if ((sc)->pci_regs_are_io) \
178 outport_byte((sc)->pci_regs_base+(reg),val); \
179 else \
180 *((volatile u_int8_t*)((sc)->pci_regs_base)+(reg)) = val; \
181 }while (0)
182
183#define CSR_WRITE_2(sc, reg, val) \
184 do { \
185 if ((sc)->pci_regs_are_io) \
186 outport_word((sc)->pci_regs_base+(reg),val); \
187 else \
188 *((volatile u_int16_t*)((u_int8_t*)((sc)->pci_regs_base)+(reg))) = val; \
189 }while (0)
190
191#define CSR_WRITE_4(sc, reg, val) \
192 do { \
193 if ((sc)->pci_regs_are_io) \
194 outport_long((sc)->pci_regs_base+(reg),val); \
195 else \
196 *((volatile u_int32_t*)((u_int8_t*)((sc)->pci_regs_base)+(reg))) = val; \
197 }while (0)
198
199#endif
200
201#define sc_if arpcom.ac_if
202
203#define FXP_UNIT(_sc) (_sc)->arpcom.ac_if.if_unit
rtems_vector_number
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition: intr.h:47
rtems_id
Objects_Id rtems_id
Used to manage and manipulate RTEMS object identifiers.
Definition: types.h:83
device
Definition: rtemscompat1.h:15
fxp_cb_mcs
Definition: if_fxpreg.h:214
fxp_cb_tx
Definition: if_fxpreg.h:241
fxp_softc
Definition: if_fxpvar.h:93
fxp_stats
Definition: if_fxpreg.h:313
mtx
Definition: if_fxpvar.h:78
pci_bus
Definition: pci.h:75
pci_dev
Definition: pci.h:41