RTEMS: bsps/sh/gensh4/include/sdram.h Source File

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sdram.h
1/*
2 * SDRAM Mode Register
3 * Based on Fujitsu MB81F643242B data sheet.
4 *
5 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
6 * Author: Victor V. Vengerov <vvv@oktet.ru>
7 *
8 * The license and distribution terms for this file may be
9 * found in the file LICENSE in this distribution or at
10 * http://www.rtems.org/license/LICENSE.
11 */
12
13#ifndef __SDRAM_H__
14#define __SDRAM_H__
15
16/* SDRAM Mode Register */
17#define SDRAM_MODE_BL 0x0007 /* Burst Length: */
18#define SDRAM_MODE_BL_1 0x0000 /* 0 */
19#define SDRAM_MODE_BL_2 0x0001 /* 2 */
20#define SDRAM_MODE_BL_4 0x0002 /* 4 */
21#define SDRAM_MODE_BL_8 0x0003 /* 8 */
22#define SDRAM_MODE_BL_16 0x0004 /* 16 */
23#define SDRAM_MODE_BL_32 0x0005 /* 32 */
24#define SDRAM_MODE_BL_64 0x0006 /* 64 */
25#define SDRAM_MODE_BL_FULL 0x0007 /* Full column */
26
27#define SDRAM_MODE_BT 0x0008 /* Burst Type: */
28#define SDRAM_MODE_BT_SEQ 0x0000 /* Sequential */
29#define SDRAM_MODE_BT_ILV 0x0008 /* Interleave */
30
31#define SDRAM_MODE_CL 0x0070 /* CAS Latency: */
32#define SDRAM_MODE_CL_1 0x0010 /* 1 */
33#define SDRAM_MODE_CL_2 0x0020 /* 2 */
34#define SDRAM_MODE_CL_3 0x0030 /* 3 */
35
36#define SDRAM_MODE_OPC 0x0200 /* Opcode: */
37#define SDRAM_MODE_OPC_BRBW 0x0000 /* Burst read & Burst write */
38#define SDRAM_MODE_OPC_BRSW 0x0200 /* Burst read & Single write */
39
40#endif