RTEMS: bsps/include/libchip/if_dcreg.h Source File

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if_dcreg.h
1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_dcreg.h,v 1.4.2.21 2003/02/12 22:19:34 mbr Exp $
33 */
34
35/*
36 * 21143 and clone common register definitions.
37 */
38
39#define DC_BUSCTL 0x00 /* bus control */
40#define DC_TXSTART 0x08 /* tx start demand */
41#define DC_RXSTART 0x10 /* rx start demand */
42#define DC_RXADDR 0x18 /* rx descriptor list start addr */
43#define DC_TXADDR 0x20 /* tx descriptor list start addr */
44#define DC_ISR 0x28 /* interrupt status register */
45#define DC_NETCFG 0x30 /* network config register */
46#define DC_IMR 0x38 /* interrupt mask */
47#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */
48#define DC_SIO 0x48 /* MII and ROM/EEPROM access */
49#define DC_ROM 0x50 /* ROM programming address */
50#define DC_TIMER 0x58 /* general timer */
51#define DC_10BTSTAT 0x60 /* SIA status */
52#define DC_SIARESET 0x68 /* SIA connectivity */
53#define DC_10BTCTRL 0x70 /* SIA transmit and receive */
54#define DC_WATCHDOG 0x78 /* SIA and general purpose port */
55
56/*
57 * There are two general 'types' of MX chips that we need to be
58 * concerned with. One is the original 98713, which has its internal
59 * NWAY support controlled via the MDIO bits in the serial I/O
60 * register. The other is everything else (from the 98713A on up),
61 * which has its internal NWAY controlled via CSR13, CSR14 and CSR15,
62 * just like the 21143. This type setting also governs which of the
63 * 'magic' numbers we write to CSR16. The PNIC II falls into the
64 * 98713A/98715/98715A/98725 category.
65 */
66#define DC_TYPE_98713 0x1
67#define DC_TYPE_98713A 0x2
68#define DC_TYPE_987x5 0x3
69
70/* Other type of supported chips. */
71#define DC_TYPE_21143 0x4 /* Intel 21143 */
72#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */
73#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */
74#define DC_TYPE_AN985 0x7 /* ADMtek AN985 Centaur */
75#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */
76#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */
77#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */
78#define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */
79
80#define DC_IS_MACRONIX(x) \
81 (x->dc_type == DC_TYPE_98713 || \
82 x->dc_type == DC_TYPE_98713A || \
83 x->dc_type == DC_TYPE_987x5)
84
85#define DC_IS_ADMTEK(x) \
86 (x->dc_type == DC_TYPE_AL981 || \
87 x->dc_type == DC_TYPE_AN985)
88
89#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143)
90#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX)
91#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981)
92#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN985)
93#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102)
94#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII)
95#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC)
96#define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT)
97
98/* MII/symbol mode port types */
99#define DC_PMODE_MII 0x1
100#define DC_PMODE_SYM 0x2
101#define DC_PMODE_SIA 0x3
102
103/*
104 * Bus control bits.
105 */
106#define DC_BUSCTL_RESET 0x00000001
107#define DC_BUSCTL_ARBITRATION 0x00000002
108#define DC_BUSCTL_SKIPLEN 0x0000007C
109#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080
110#define DC_BUSCTL_BURSTLEN 0x00003F00
111#define DC_BUSCTL_CACHEALIGN 0x0000C000
112#define DC_BUSCTL_TXPOLL 0x000E0000
113#define DC_BUSCTL_DBO 0x00100000
114#define DC_BUSCTL_MRME 0x00200000
115#define DC_BUSCTL_MRLE 0x00800000
116#define DC_BUSCTL_MWIE 0x01000000
117#define DC_BUSCTL_ONNOW_ENB 0x04000000
118
119#define DC_SKIPLEN_1LONG 0x00000004
120#define DC_SKIPLEN_2LONG 0x00000008
121#define DC_SKIPLEN_3LONG 0x00000010
122#define DC_SKIPLEN_4LONG 0x00000020
123#define DC_SKIPLEN_5LONG 0x00000040
124
125#define DC_CACHEALIGN_NONE 0x00000000
126#define DC_CACHEALIGN_8LONG 0x00004000
127#define DC_CACHEALIGN_16LONG 0x00008000
128#define DC_CACHEALIGN_32LONG 0x0000C000
129
130#define DC_BURSTLEN_USECA 0x00000000
131#define DC_BURSTLEN_1LONG 0x00000100
132#define DC_BURSTLEN_2LONG 0x00000200
133#define DC_BURSTLEN_4LONG 0x00000400
134#define DC_BURSTLEN_8LONG 0x00000800
135#define DC_BURSTLEN_16LONG 0x00001000
136#define DC_BURSTLEN_32LONG 0x00002000
137
138#define DC_TXPOLL_OFF 0x00000000
139#define DC_TXPOLL_1 0x00020000
140#define DC_TXPOLL_2 0x00040000
141#define DC_TXPOLL_3 0x00060000
142#define DC_TXPOLL_4 0x00080000
143#define DC_TXPOLL_5 0x000A0000
144#define DC_TXPOLL_6 0x000C0000
145#define DC_TXPOLL_7 0x000E0000
146
147/*
148 * Interrupt status bits.
149 */
150#define DC_ISR_TX_OK 0x00000001
151#define DC_ISR_TX_IDLE 0x00000002
152#define DC_ISR_TX_NOBUF 0x00000004
153#define DC_ISR_TX_JABBERTIMEO 0x00000008
154#define DC_ISR_LINKGOOD 0x00000010
155#define DC_ISR_TX_UNDERRUN 0x00000020
156#define DC_ISR_RX_OK 0x00000040
157#define DC_ISR_RX_NOBUF 0x00000080
158#define DC_ISR_RX_READ 0x00000100
159#define DC_ISR_RX_WATDOGTIMEO 0x00000200
160#define DC_ISR_TX_EARLY 0x00000400
161#define DC_ISR_TIMER_EXPIRED 0x00000800
162#define DC_ISR_LINKFAIL 0x00001000
163#define DC_ISR_BUS_ERR 0x00002000
164#define DC_ISR_RX_EARLY 0x00004000
165#define DC_ISR_ABNORMAL 0x00008000
166#define DC_ISR_NORMAL 0x00010000
167#define DC_ISR_RX_STATE 0x000E0000
168#define DC_ISR_TX_STATE 0x00700000
169#define DC_ISR_BUSERRTYPE 0x03800000
170#define DC_ISR_100MBPSLINK 0x08000000
171#define DC_ISR_MAGICKPACK 0x10000000
172
173#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
174#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
175#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
176#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
177#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
178#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
179#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
180#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
181
182#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */
183#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
184#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
185#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
186#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
187#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
188#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
189#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
190
191/*
192 * Network config bits.
193 */
194#define DC_NETCFG_RX_HASHPERF 0x00000001
195#define DC_NETCFG_RX_ON 0x00000002
196#define DC_NETCFG_RX_HASHONLY 0x00000004
197#define DC_NETCFG_RX_BADFRAMES 0x00000008
198#define DC_NETCFG_RX_INVFILT 0x00000010
199#define DC_NETCFG_BACKOFFCNT 0x00000020
200#define DC_NETCFG_RX_PROMISC 0x00000040
201#define DC_NETCFG_RX_ALLMULTI 0x00000080
202#define DC_NETCFG_FULLDUPLEX 0x00000200
203#define DC_NETCFG_LOOPBACK 0x00000C00
204#define DC_NETCFG_FORCECOLL 0x00001000
205#define DC_NETCFG_TX_ON 0x00002000
206#define DC_NETCFG_TX_THRESH 0x0000C000
207#define DC_NETCFG_TX_BACKOFF 0x00020000
208#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */
209#define DC_NETCFG_HEARTBEAT 0x00080000
210#define DC_NETCFG_STORENFWD 0x00200000
211#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
212#define DC_NETCFG_PCS 0x00800000
213#define DC_NETCFG_SCRAMBLER 0x01000000
214#define DC_NETCFG_NO_RXCRC 0x02000000
215#define DC_NETCFG_RX_ALL 0x40000000
216#define DC_NETCFG_CAPEFFECT 0x80000000
217
218#define DC_OPMODE_NORM 0x00000000
219#define DC_OPMODE_INTLOOP 0x00000400
220#define DC_OPMODE_EXTLOOP 0x00000800
221
222#if 0
223#define DC_TXTHRESH_72BYTES 0x00000000
224#define DC_TXTHRESH_96BYTES 0x00004000
225#define DC_TXTHRESH_128BYTES 0x00008000
226#define DC_TXTHRESH_160BYTES 0x0000C000
227#endif
228
229#define DC_TXTHRESH_MIN 0x00000000
230#define DC_TXTHRESH_INC 0x00004000
231#define DC_TXTHRESH_MAX 0x0000C000
232
233
234/*
235 * Interrupt mask bits.
236 */
237#define DC_IMR_TX_OK 0x00000001
238#define DC_IMR_TX_IDLE 0x00000002
239#define DC_IMR_TX_NOBUF 0x00000004
240#define DC_IMR_TX_JABBERTIMEO 0x00000008
241#define DC_IMR_LINKGOOD 0x00000010
242#define DC_IMR_TX_UNDERRUN 0x00000020
243#define DC_IMR_RX_OK 0x00000040
244#define DC_IMR_RX_NOBUF 0x00000080
245#define DC_IMR_RX_READ 0x00000100
246#define DC_IMR_RX_WATDOGTIMEO 0x00000200
247#define DC_IMR_TX_EARLY 0x00000400
248#define DC_IMR_TIMER_EXPIRED 0x00000800
249#define DC_IMR_LINKFAIL 0x00001000
250#define DC_IMR_BUS_ERR 0x00002000
251#define DC_IMR_RX_EARLY 0x00004000
252#define DC_IMR_ABNORMAL 0x00008000
253#define DC_IMR_NORMAL 0x00010000
254#define DC_IMR_100MBPSLINK 0x08000000
255#define DC_IMR_MAGICKPACK 0x10000000
256
257#define DC_INTRS \
258 (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\
259 DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \
260 DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/)
261/*
262 * Serial I/O (EEPROM/ROM) bits.
263 */
264#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */
265#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */
266#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
267#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
268#define DC_SIO_ROMDATA4 0x00000010
269#define DC_SIO_ROMDATA5 0x00000020
270#define DC_SIO_ROMDATA6 0x00000040
271#define DC_SIO_ROMDATA7 0x00000080
272#define DC_SIO_EESEL 0x00000800
273#define DC_SIO_ROMSEL 0x00001000
274#define DC_SIO_ROMCTL_WRITE 0x00002000
275#define DC_SIO_ROMCTL_READ 0x00004000
276#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */
277#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
278#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */
279#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
280
281#define DC_EECMD_WRITE 0x140
282#define DC_EECMD_READ 0x180
283#define DC_EECMD_ERASE 0x1c0
284
285#define DC_EE_NODEADDR_OFFSET 0x70
286#define DC_EE_NODEADDR 10
287
288/*
289 * General purpose timer register
290 */
291#define DC_TIMER_VALUE 0x0000FFFF
292#define DC_TIMER_CONTINUOUS 0x00010000
293
294/*
295 * 10baseT status register
296 */
297#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */
298#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */
299#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */
300#define DC_TSTAT_AUTOPOLARITY 0x00000008
301#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */
302#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */
303#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */
304#define DC_TSTAT_REMFAULT 0x00000800
305#define DC_TSTAT_ANEGSTAT 0x00007000
306#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */
307#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */
308
309#define DC_ASTAT_DISABLE 0x00000000
310#define DC_ASTAT_TXDISABLE 0x00001000
311#define DC_ASTAT_ABDETECT 0x00002000
312#define DC_ASTAT_ACKDETECT 0x00003000
313#define DC_ASTAT_CMPACKDETECT 0x00004000
314#define DC_ASTAT_AUTONEGCMP 0x00005000
315#define DC_ASTAT_LINKCHECK 0x00006000
316
317/*
318 * PHY reset register
319 */
320#define DC_SIA_RESET 0x00000001
321#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */
322
323/*
324 * 10baseT control register
325 */
326#define DC_TCTL_ENCODER_ENB 0x00000001
327#define DC_TCTL_LOOPBACK 0x00000002
328#define DC_TCTL_DRIVER_ENB 0x00000004
329#define DC_TCTL_LNKPULSE_ENB 0x00000008
330#define DC_TCTL_HALFDUPLEX 0x00000040
331#define DC_TCTL_AUTONEGENBL 0x00000080
332#define DC_TCTL_RX_SQUELCH 0x00000100
333#define DC_TCTL_COLL_SQUELCH 0x00000200
334#define DC_TCTL_COLL_DETECT 0x00000400
335#define DC_TCTL_SQE_ENB 0x00000800
336#define DC_TCTL_LINKTEST 0x00001000
337#define DC_TCTL_AUTOPOLARITY 0x00002000
338#define DC_TCTL_SET_POL_PLUS 0x00004000
339#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */
340#define DC_TCTL_100BTXHALF 0x00010000
341#define DC_TCTL_100BTXFULL 0x00020000
342#define DC_TCTL_100BT4 0x00040000
343
344/*
345 * Watchdog timer register
346 */
347#define DC_WDOG_JABBERDIS 0x00000001
348#define DC_WDOG_HOSTUNJAB 0x00000002
349#define DC_WDOG_JABBERCLK 0x00000004
350#define DC_WDOG_RXWDOGDIS 0x00000010
351#define DC_WDOG_RXWDOGCLK 0x00000020
352#define DC_WDOG_MUSTBEZERO 0x00000100
353#define DC_WDOG_AUIBNC 0x00100000
354#define DC_WDOG_ACTIVITY 0x00200000
355#define DC_WDOG_RX_MATCH 0x00400000
356#define DC_WDOG_LINK 0x00800000
357#define DC_WDOG_CTLWREN 0x08000000
358
359/*
360 * Size of a setup frame.
361 */
362#define DC_SFRAME_LEN 192
363
364/*
365 * 21x4x TX/RX list structure.
366 */
367
368 struct dc_desc {
369 u_int32_t dc_status;
370 u_int32_t dc_ctl;
371 u_int32_t dc_ptr1;
372 u_int32_t dc_ptr2;
373};
374
375#define dc_data dc_ptr1
376#define dc_next dc_ptr2
377
378#define DC_RXSTAT_FIFOOFLOW 0x00000001
379#define DC_RXSTAT_CRCERR 0x00000002
380#define DC_RXSTAT_DRIBBLE 0x00000004
381#define DC_RXSTAT_MIIERE 0x00000008
382#define DC_RXSTAT_WATCHDOG 0x00000010
383#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
384#define DC_RXSTAT_COLLSEEN 0x00000040
385#define DC_RXSTAT_GIANT 0x00000080
386#define DC_RXSTAT_LASTFRAG 0x00000100
387#define DC_RXSTAT_FIRSTFRAG 0x00000200
388#define DC_RXSTAT_MULTICAST 0x00000400
389#define DC_RXSTAT_RUNT 0x00000800
390#define DC_RXSTAT_RXTYPE 0x00003000
391#define DC_RXSTAT_DE 0x00004000
392#define DC_RXSTAT_RXERR 0x00008000
393#define DC_RXSTAT_RXLEN 0x3FFF0000
394#define DC_RXSTAT_OWN 0x80000000
395
396#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16)
397#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN)
398
399#define DC_RXCTL_BUFLEN1 0x00000FFF
400#define DC_RXCTL_BUFLEN2 0x00FFF000
401#define DC_RXCTL_RLINK 0x01000000
402#define DC_RXCTL_RLAST 0x02000000
403
404#define DC_TXSTAT_DEFER 0x00000001
405#define DC_TXSTAT_UNDERRUN 0x00000002
406#define DC_TXSTAT_LINKFAIL 0x00000003
407#define DC_TXSTAT_COLLCNT 0x00000078
408#define DC_TXSTAT_SQE 0x00000080
409#define DC_TXSTAT_EXCESSCOLL 0x00000100
410#define DC_TXSTAT_LATECOLL 0x00000200
411#define DC_TXSTAT_NOCARRIER 0x00000400
412#define DC_TXSTAT_CARRLOST 0x00000800
413#define DC_TXSTAT_JABTIMEO 0x00004000
414#define DC_TXSTAT_ERRSUM 0x00008000
415#define DC_TXSTAT_OWN 0x80000000
416
417#define DC_TXCTL_BUFLEN1 0x000007FF
418#define DC_TXCTL_BUFLEN2 0x003FF800
419#define DC_TXCTL_FILTTYPE0 0x00400000
420#define DC_TXCTL_PAD 0x00800000
421#define DC_TXCTL_TLINK 0x01000000
422#define DC_TXCTL_TLAST 0x02000000
423#define DC_TXCTL_NOCRC 0x04000000
424#define DC_TXCTL_SETUP 0x08000000
425#define DC_TXCTL_FILTTYPE1 0x10000000
426#define DC_TXCTL_FIRSTFRAG 0x20000000
427#define DC_TXCTL_LASTFRAG 0x40000000
428#define DC_TXCTL_FINT 0x80000000
429
430#define DC_FILTER_PERFECT 0x00000000
431#define DC_FILTER_HASHPERF 0x00400000
432#define DC_FILTER_INVERSE 0x10000000
433#define DC_FILTER_HASHONLY 0x10400000
434
435#define DC_MAXFRAGS 16
436#ifdef DEVICE_POLLING
437#define DC_RX_LIST_CNT 192
438#else
439#define DC_RX_LIST_CNT 64
440#endif
441#define DC_TX_LIST_CNT 256
442#define DC_MIN_FRAMELEN 60
443#define DC_RXLEN 1536
444
445#define DC_INC(x, y) (x) = (x + 1) % y
446
447 struct dc_list_data {
448 struct dc_desc dc_rx_list[DC_RX_LIST_CNT];
449 struct dc_desc dc_tx_list[DC_TX_LIST_CNT];
450};
451
452 struct dc_chain_data {
453 struct mbuf *dc_rx_chain[DC_RX_LIST_CNT];
454 struct mbuf *dc_tx_chain[DC_TX_LIST_CNT];
455 u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)];
456 u_int8_t dc_pad[DC_MIN_FRAMELEN];
457 int dc_tx_prod;
458 int dc_tx_cons;
459 int dc_tx_cnt;
460 int dc_rx_prod;
461};
462
463 struct dc_mediainfo {
464 int dc_media;
465 u_int8_t *dc_gp_ptr;
466 u_int8_t dc_gp_len;
467 u_int8_t *dc_reset_ptr;
468 u_int8_t dc_reset_len;
469 struct dc_mediainfo *dc_next;
470};
471
472
473 struct dc_type {
474 u_int16_t dc_vid;
475 u_int16_t dc_did;
476 char *dc_name;
477 int dc_devsig;
478 int dc_bus;
479 int dc_dev;
480 int dc_fun;
481};
482
483 struct dc_mii_frame {
484 u_int8_t mii_stdelim;
485 u_int8_t mii_opcode;
486 u_int8_t mii_phyaddr;
487 u_int8_t mii_regaddr;
488 u_int8_t mii_turnaround;
489 u_int16_t mii_data;
490};
491
492/*
493 * MII constants
494 */
495#define DC_MII_STARTDELIM 0x01
496#define DC_MII_READOP 0x02
497#define DC_MII_WRITEOP 0x01
498#define DC_MII_TURNAROUND 0x02
499
500
501/*
502 * Registers specific to clone devices.
503 * This mainly relates to RX filter programming: not all 21x4x clones
504 * use the standard DEC filter programming mechanism.
505 */
506
507/*
508 * ADMtek specific registers and constants for the AL981 and AN985.
509 * The AN985 doesn't use the magic PHY registers.
510 */
511#define DC_AL_CR 0x88 /* command register */
512#define DC_AL_PAR0 0xA4 /* station address */
513#define DC_AL_PAR1 0xA8 /* station address */
514#define DC_AL_MAR0 0xAC /* multicast hash filter */
515#define DC_AL_MAR1 0xB0 /* multicast hash filter */
516#define DC_AL_BMCR 0xB4 /* built in PHY control */
517#define DC_AL_BMSR 0xB8 /* built in PHY status */
518#define DC_AL_VENID 0xBC /* built in PHY ID0 */
519#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */
520#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */
521#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */
522#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */
523
524#define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */
525#define DC_ADMTEK_PHYADDR 0x1
526#define DC_AL_EE_NODEADDR 4
527/* End of ADMtek specific registers */
528
529/*
530 * ASIX specific registers.
531 */
532#define DC_AX_FILTIDX 0x68 /* RX filter index */
533#define DC_AX_FILTDATA 0x70 /* RX filter data */
534
535/*
536 * Special ASIX-specific bits in the ASIX NETCFG register (CSR6).
537 */
538#define DC_AX_NETCFG_RX_BROAD 0x00000100
539
540/*
541 * RX Filter Index Register values
542 */
543#define DC_AX_FILTIDX_PAR0 0x00000000
544#define DC_AX_FILTIDX_PAR1 0x00000001
545#define DC_AX_FILTIDX_MAR0 0x00000002
546#define DC_AX_FILTIDX_MAR1 0x00000003
547/* End of ASIX specific registers */
548
549/*
550 * Macronix specific registers. The Macronix chips have a special
551 * register for reading the NWAY status, which we don't use, plus
552 * a magic packet register, which we need to tweak a bit per the
553 * Macronix application notes.
554 */
555#define DC_MX_MAGICPACKET 0x80
556#define DC_MX_NWAYSTAT 0xA0
557
558/*
559 * Magic packet register
560 */
561#define DC_MX_MPACK_DISABLE 0x00400000
562
563/*
564 * NWAY status register.
565 */
566#define DC_MX_NWAY_10BTHALF 0x08000000
567#define DC_MX_NWAY_10BTFULL 0x10000000
568#define DC_MX_NWAY_100BTHALF 0x20000000
569#define DC_MX_NWAY_100BTFULL 0x40000000
570#define DC_MX_NWAY_100BT4 0x80000000
571
572/*
573 * These are magic values that must be written into CSR16
574 * (DC_MX_MAGICPACKET) in order to put the chip into proper
575 * operating mode. The magic numbers are documented in the
576 * Macronix 98715 application notes.
577 */
578#define DC_MX_MAGIC_98713 0x0F370000
579#define DC_MX_MAGIC_98713A 0x0B3C0000
580#define DC_MX_MAGIC_98715 0x0B3C0000
581#define DC_MX_MAGIC_98725 0x0B3C0000
582/* End of Macronix specific registers */
583
584/*
585 * PNIC 82c168/82c169 specific registers.
586 * The PNIC has its own special NWAY support, which doesn't work,
587 * and shortcut ways of reading the EEPROM and MII bus.
588 */
589#define DC_PN_GPIO 0x60 /* general purpose pins control */
590#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */
591#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */
592#define DC_PN_MII 0xA0 /* MII access register */
593#define DC_PN_NWAY 0xB8 /* Internal NWAY register */
594
595/* Serial I/O EEPROM register */
596#define DC_PN_SIOCTL_DATA 0x0000003F
597#define DC_PN_SIOCTL_OPCODE 0x00000300
598#define DC_PN_SIOCTL_BUSY 0x80000000
599
600#define DC_PN_EEOPCODE_ERASE 0x00000300
601#define DC_PN_EEOPCODE_READ 0x00000600
602#define DC_PN_EEOPCODE_WRITE 0x00000100
603
604/*
605 * The first two general purpose pins control speed selection and
606 * 100Mbps loopback on the 82c168 chip. The control bits should always
607 * be set (to make the data pins outputs) and the speed selction and
608 * loopback bits set accordingly when changing media. Physically, this
609 * will set the state of a relay mounted on the card.
610 */
611#define DC_PN_GPIO_DATA0 0x000000001
612#define DC_PN_GPIO_DATA1 0x000000002
613#define DC_PN_GPIO_DATA2 0x000000004
614#define DC_PN_GPIO_DATA3 0x000000008
615#define DC_PN_GPIO_CTL0 0x000000010
616#define DC_PN_GPIO_CTL1 0x000000020
617#define DC_PN_GPIO_CTL2 0x000000040
618#define DC_PN_GPIO_CTL3 0x000000080
619#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */
620#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */
621#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2
622#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3
623#define DC_PN_GPIO_SETBIT(sc, r) \
624 DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4)))
625#define DC_PN_GPIO_CLRBIT(sc, r) \
626 { \
627 DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \
628 DC_CLRBIT(sc, DC_PN_GPIO, (r)); \
629 }
630
631/* shortcut MII access register */
632#define DC_PN_MII_DATA 0x0000FFFF
633#define DC_PN_MII_RESERVER 0x00020000
634#define DC_PN_MII_REGADDR 0x007C0000
635#define DC_PN_MII_PHYADDR 0x0F800000
636#define DC_PN_MII_OPCODE 0x30000000
637#define DC_PN_MII_BUSY 0x80000000
638
639#define DC_PN_MIIOPCODE_READ 0x60020000
640#define DC_PN_MIIOPCODE_WRITE 0x50020000
641
642/* Internal NWAY bits */
643#define DC_PN_NWAY_RESET 0x00000001 /* reset */
644#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */
645#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */
646#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */
647#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */
648#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */
649#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */
650#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */
651#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */
652#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */
653#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */
654#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */
655#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */
656#define DC_PN_NWAY_CAP10HDX 0x00002000
657#define DC_PN_NWAY_CAP10FDX 0x00004000
658#define DC_PN_NWAY_CAP100FDX 0x00008000
659#define DC_PN_NWAY_CAP100HDX 0x00010000
660#define DC_PN_NWAY_CAP100T4 0x00020000
661#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */
662#define DC_PN_NWAY_REMFAULT 0x04000000
663#define DC_PN_NWAY_LPAR10HDX 0x08000000
664#define DC_PN_NWAY_LPAR10FDX 0x10000000
665#define DC_PN_NWAY_LPAR100FDX 0x20000000
666#define DC_PN_NWAY_LPAR100HDX 0x40000000
667#define DC_PN_NWAY_LPAR100T4 0x80000000
668
669/* End of PNIC specific registers */
670
671/*
672 * CONEXANT specific registers.
673 */
674
675#define DC_CONEXANT_PHYADDR 0x1
676#define DC_CONEXANT_EE_NODEADDR 0x19A
677
678/* End of CONEXANT specific registers */
679
680
681 struct dc_softc {
682 struct arpcom arpcom; /* interface info */
683 rtems_irq_connect_data irqInfo;
684 volatile u_int32_t membase;
685 rtems_id daemontid;
686#if 0
687 bus_space_handle_t dc_bhandle; /* bus space handle */
688 bus_space_tag_t dc_btag; /* bus space tag */
689 void *dc_intrhand;
690 struct resource *dc_irq;
691 struct resource *dc_res;
692#endif
693 struct dc_type *dc_info; /* adapter info */
694/* device_t dc_miibus; */
695 u_int8_t dc_unit; /* interface number */
696 char *dc_name;
697 u_int8_t dc_type;
698 u_int8_t dc_pmode;
699 u_int8_t dc_link;
700 u_int8_t dc_cachesize;
701 int dc_romwidth;
702 int dc_pnic_rx_bug_save;
703 unsigned char *dc_pnic_rx_buf;
704 int dc_if_flags;
705 int dc_if_media;
706 u_int32_t dc_flags;
707 u_int32_t dc_txthresh;
708 u_int8_t *dc_srom;
709 struct dc_mediainfo *dc_mi;
710/*
711 struct callout_handle dc_stat_ch;
712*/
713 struct dc_list_data *dc_ldata;
714 struct dc_chain_data dc_cdata;
715#ifdef __alpha__
716 int dc_srm_media;
717#endif
718#ifdef DEVICE_POLLING
719 int rxcycles; /* ... when polling */
720#endif
721 int suspended; /* 0 = normal 1 = suspended */
722
723 u_int32_t saved_maps[5]; /* pci data */
724 u_int32_t saved_biosaddr;
725 u_int8_t saved_intline;
726 u_int8_t saved_cachelnsz;
727 u_int8_t saved_lattimer;
728};
729
730#define DC_TX_POLL 0x00000001
731#define DC_TX_COALESCE 0x00000002
732#define DC_TX_ADMTEK_WAR 0x00000004
733#define DC_TX_USE_TX_INTR 0x00000008
734#define DC_RX_FILTER_TULIP 0x00000010
735#define DC_TX_INTR_FIRSTFRAG 0x00000020
736#define DC_PNIC_RX_BUG_WAR 0x00000040
737#define DC_TX_FIXED_RING 0x00000080
738#define DC_TX_STORENFWD 0x00000100
739#define DC_REDUCED_MII_POLL 0x00000200
740#define DC_TX_INTR_ALWAYS 0x00000400
741#define DC_21143_NWAY 0x00000800
742#define DC_128BIT_HASH 0x00001000
743#define DC_64BIT_HASH 0x00002000
744#define DC_TULIP_LEDS 0x00004000
745#define DC_TX_ONE 0x00008000
746
747/*
748 * register space access macros
749 */
750#define _readl_(addr) (*(volatile unsigned int *)((void *)(addr)))
751#define _writel_(b, addr) (*(volatile unsigned int *)((void *)(addr)) = (b))
752
753#define CSR_READ_4(sc, reg) _readl_(((sc->membase)+(reg)))
754#define CSR_WRITE_4(sc, reg, val) _writel_(val, ((sc->membase)+(reg)))
755
756
757
758
759
760
761#define DC_TIMEOUT 1000
762#define ETHER_ALIGN 2
763
764/*
765 * General constants that are fun to know.
766 */
767
768/*
769 * DEC PCI vendor ID
770 */
771#define DC_VENDORID_DEC 0x1011
772
773/*
774 * DEC/Intel 21143 PCI device ID
775 */
776#define DC_DEVICEID_21143 0x0019
777
778/*
779 * Macronix PCI vendor ID
780 */
781#define DC_VENDORID_MX 0x10D9
782
783/*
784 * Macronix PMAC device IDs.
785 */
786#define DC_DEVICEID_98713 0x0512
787#define DC_DEVICEID_987x5 0x0531
788#define DC_DEVICEID_98727 0x0532
789#define DC_DEVICEID_98732 0x0532
790
791/* Macronix PCI revision codes. */
792#define DC_REVISION_98713 0x00
793#define DC_REVISION_98713A 0x10
794#define DC_REVISION_98715 0x20
795#define DC_REVISION_98715AEC_C 0x25
796#define DC_REVISION_98725 0x30
797
798/*
799 * Compex PCI vendor ID.
800 */
801#define DC_VENDORID_CP 0x11F6
802
803/*
804 * Compex PMAC PCI device IDs.
805 */
806#define DC_DEVICEID_98713_CP 0x9881
807
808/*
809 * Lite-On PNIC PCI vendor ID
810 */
811#define DC_VENDORID_LO 0x11AD
812
813/*
814 * 82c168/82c169 PNIC device IDs. Both chips have the same device
815 * ID but different revisions. Revision 0x10 is the 82c168, and
816 * 0x20 is the 82c169.
817 */
818#define DC_DEVICEID_82C168 0x0002
819
820#define DC_REVISION_82C168 0x10
821#define DC_REVISION_82C169 0x20
822
823/*
824 * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A
825 * with wake on lan/magic packet support.
826 */
827#define DC_DEVICEID_82C115 0xc115
828
829/*
830 * Davicom vendor ID.
831 */
832#define DC_VENDORID_DAVICOM 0x1282
833
834/*
835 * Davicom device IDs.
836 */
837#define DC_DEVICEID_DM9009 0x9009
838#define DC_DEVICEID_DM9100 0x9100
839#define DC_DEVICEID_DM9102 0x9102
840
841/*
842 * The DM9102A has the same PCI device ID as the DM9102,
843 * but a higher revision code.
844 */
845#define DC_REVISION_DM9102 0x10
846#define DC_REVISION_DM9102A 0x30
847
848/*
849 * ADMtek vendor ID.
850 */
851#define DC_VENDORID_ADMTEK 0x1317
852
853/*
854 * ADMtek device IDs.
855 */
856#define DC_DEVICEID_AL981 0x0981
857#define DC_DEVICEID_AN985 0x0985
858
859/*
860 * ASIX vendor ID.
861 */
862#define DC_VENDORID_ASIX 0x125B
863
864/*
865 * ASIX device IDs.
866 */
867#define DC_DEVICEID_AX88140A 0x1400
868
869/*
870 * The ASIX AX88140 and ASIX AX88141 have the same vendor and
871 * device IDs but different revision values.
872 */
873#define DC_REVISION_88140 0x00
874#define DC_REVISION_88141 0x10
875
876/*
877 * Accton vendor ID.
878 */
879#define DC_VENDORID_ACCTON 0x1113
880
881/*
882 * Accton device IDs.
883 */
884#define DC_DEVICEID_EN1217 0x1217
885#define DC_DEVICEID_EN2242 0x1216
886
887/*
888 * Conexant vendor ID.
889 */
890#define DC_VENDORID_CONEXANT 0x14f1
891
892/*
893 * Conexant device IDs.
894 */
895#define DC_DEVICEID_RS7112 0x1803
896
897/*
898 * PCI low memory base and low I/O base register, and
899 * other PCI registers.
900 */
901
902#define DC_PCI_CFID 0x00 /* Id */
903#define DC_PCI_CFCS 0x04 /* Command and status */
904#define DC_PCI_CFRV 0x08 /* Revision */
905#define DC_PCI_CFLT 0x0C /* Latency timer */
906#define DC_PCI_CFBIO 0x10 /* Base I/O address */
907#define DC_PCI_CFBMA 0x14 /* Base memory address */
908#define DC_PCI_CCIS 0x28 /* Card info struct */
909#define DC_PCI_CSID 0x2C /* Subsystem ID */
910#define DC_PCI_CBER 0x30 /* Expansion ROM base address */
911#define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */
912#define DC_PCI_CFIT 0x3C /* Interrupt */
913#define DC_PCI_CFDD 0x40 /* Device and driver area */
914#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */
915#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */
916#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */
917#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */
918#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */
919#define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */
920#define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */
921
922/* PCI ID register */
923#define DC_CFID_VENDOR 0x0000FFFF
924#define DC_CFID_DEVICE 0xFFFF0000
925
926/* PCI command/status register */
927#define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */
928#define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */
929#define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */
930#define DC_CFCS_MWI_ENB 0x00000010 /* mem write and inval enable */
931#define DC_CFCS_PARITYERR_ENB 0x00000040 /* parity error enable */
932#define DC_CFCS_SYSERR_ENB 0x00000100 /* system error enable */
933#define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */
934#define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */
935#define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */
936#define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */
937#define DC_CFCS_TGTABRT 0x10000000 /* received target abort */
938#define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */
939#define DC_CFCS_SYSERR 0x40000000 /* asserted system error */
940#define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */
941
942/* PCI revision register */
943#define DC_CFRV_STEPPING 0x0000000F
944#define DC_CFRV_REVISION 0x000000F0
945#define DC_CFRV_SUBCLASS 0x00FF0000
946#define DC_CFRV_BASECLASS 0xFF000000
947
948#define DC_21143_PB_REV 0x00000030
949#define DC_21143_TB_REV 0x00000030
950#define DC_21143_PC_REV 0x00000030
951#define DC_21143_TC_REV 0x00000030
952#define DC_21143_PD_REV 0x00000041
953#define DC_21143_TD_REV 0x00000041
954
955/* PCI latency timer register */
956#define DC_CFLT_CACHELINESIZE 0x000000FF
957#define DC_CFLT_LATENCYTIMER 0x0000FF00
958
959/* PCI subsystem ID register */
960#define DC_CSID_VENDOR 0x0000FFFF
961#define DC_CSID_DEVICE 0xFFFF0000
962
963/* PCI cababilities pointer */
964#define DC_CCAP_OFFSET 0x000000FF
965
966/* PCI interrupt config register */
967#define DC_CFIT_INTLINE 0x000000FF
968#define DC_CFIT_INTPIN 0x0000FF00
969#define DC_CFIT_MIN_GNT 0x00FF0000
970#define DC_CFIT_MAX_LAT 0xFF000000
971
972/* PCI capability register */
973#define DC_CCID_CAPID 0x000000FF
974#define DC_CCID_NEXTPTR 0x0000FF00
975#define DC_CCID_PM_VERS 0x00070000
976#define DC_CCID_PME_CLK 0x00080000
977#define DC_CCID_DVSPEC_INT 0x00200000
978#define DC_CCID_STATE_D1 0x02000000
979#define DC_CCID_STATE_D2 0x04000000
980#define DC_CCID_PME_D0 0x08000000
981#define DC_CCID_PME_D1 0x10000000
982#define DC_CCID_PME_D2 0x20000000
983#define DC_CCID_PME_D3HOT 0x40000000
984#define DC_CCID_PME_D3COLD 0x80000000
985
986/* PCI power management control/status register */
987#define DC_CPMC_STATE 0x00000003
988#define DC_CPMC_PME_ENB 0x00000100
989#define DC_CPMC_PME_STS 0x00008000
990
991#define DC_PSTATE_D0 0x0
992#define DC_PSTATE_D1 0x1
993#define DC_PSTATE_D2 0x2
994#define DC_PSTATE_D3 0x3
995
996/* Device specific region */
997/* Configuration and driver area */
998#define DC_CFDD_DRVUSE 0x0000FFFF
999#define DC_CFDD_SNOOZE_MODE 0x40000000
1000#define DC_CFDD_SLEEP_MODE 0x80000000
1001
1002/* Configuration wake-up command register */
1003#define DC_CWUC_MUST_BE_ZERO 0x00000001
1004#define DC_CWUC_SECUREON_ENB 0x00000002
1005#define DC_CWUC_FORCE_WUL 0x00000004
1006#define DC_CWUC_BNC_ABILITY 0x00000008
1007#define DC_CWUC_AUI_ABILITY 0x00000010
1008#define DC_CWUC_TP10_ABILITY 0x00000020
1009#define DC_CWUC_MII_ABILITY 0x00000040
1010#define DC_CWUC_SYM_ABILITY 0x00000080
1011#define DC_CWUC_LOCK 0x00000100
1012
1013/*
1014 * SROM nonsense.
1015 */
1016
1017#define DC_IB_CTLRCNT 0x13
1018#define DC_IB_LEAF0_CNUM 0x1A
1019#define DC_IB_LEAF0_OFFSET 0x1B
1020
1021 struct dc_info_leaf {
1022 u_int16_t dc_conntype;
1023 u_int8_t dc_blkcnt;
1024 u_int8_t dc_rsvd;
1025 u_int16_t dc_infoblk;
1026};
1027
1028#define DC_CTYPE_10BT 0x0000
1029#define DC_CTYPE_10BT_NWAY 0x0100
1030#define DC_CTYPE_10BT_FDX 0x0204
1031#define DC_CTYPE_10B2 0x0001
1032#define DC_CTYPE_10B5 0x0002
1033#define DC_CTYPE_100BT 0x0003
1034#define DC_CTYPE_100BT_FDX 0x0205
1035#define DC_CTYPE_100T4 0x0006
1036#define DC_CTYPE_100FX 0x0007
1037#define DC_CTYPE_100FX_FDX 0x0208
1038#define DC_CTYPE_MII_10BT 0x0009
1039#define DC_CTYPE_MII_10BT_FDX 0x020A
1040#define DC_CTYPE_MII_100BT 0x000D
1041#define DC_CTYPE_MII_100BT_FDX 0x020E
1042#define DC_CTYPE_MII_100T4 0x000F
1043#define DC_CTYPE_MII_100FX 0x0010
1044#define DC_CTYPE_MII_100FX_FDX 0x0211
1045#define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800
1046#define DC_CTYPE_PUP_AUTOSENSE 0x8800
1047#define DC_CTYPE_NOMEDIA 0xFFFF
1048
1049#define DC_EBLOCK_SIA 0x0002
1050#define DC_EBLOCK_MII 0x0003
1051#define DC_EBLOCK_SYM 0x0004
1052#define DC_EBLOCK_RESET 0x0005
1053#define DC_EBLOCK_PHY_SHUTDOWN 0x0006
1054
1055 struct dc_leaf_hdr {
1056 u_int16_t dc_mtype;
1057 u_int8_t dc_mcnt;
1058 u_int8_t dc_rsvd;
1059};
1060
1061 struct dc_eblock_hdr {
1062 u_int8_t dc_len;
1063 u_int8_t dc_type;
1064};
1065
1066 struct dc_eblock_sia {
1067 struct dc_eblock_hdr dc_sia_hdr;
1068 u_int8_t dc_sia_code;
1069 u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */
1070 u_int8_t dc_sia_gpio_ctl[2];
1071 u_int8_t dc_sia_gpio_dat[2];
1072};
1073
1074#define DC_SIA_CODE_10BT 0x00
1075#define DC_SIA_CODE_10B2 0x01
1076#define DC_SIA_CODE_10B5 0x02
1077#define DC_SIA_CODE_10BT_FDX 0x04
1078#define DC_SIA_CODE_EXT 0x40
1079
1080/*
1081 * Note that the first word in the gpr and reset
1082 * sequences is always a control word.
1083 */
1084 struct dc_eblock_mii {
1085 struct dc_eblock_hdr dc_mii_hdr;
1086 u_int8_t dc_mii_phynum;
1087 u_int8_t dc_gpr_len;
1088/* u_int16_t dc_gpr_dat[n]; */
1089/* u_int8_t dc_reset_len; */
1090/* u_int16_t dc_reset_dat[n]; */
1091/* There are other fields after these, but we don't
1092 * care about them since they can be determined by looking
1093 * at the PHY.
1094 */
1095};
1096
1097 struct dc_eblock_sym {
1098 struct dc_eblock_hdr dc_sym_hdr;
1099 u_int8_t dc_sym_code;
1100 u_int8_t dc_sym_gpio_ctl[2];
1101 u_int8_t dc_sym_gpio_dat[2];
1102 u_int8_t dc_sym_cmd[2];
1103};
1104
1105#define DC_SYM_CODE_100BT 0x03
1106#define DC_SYM_CODE_100BT_FDX 0x05
1107#define DC_SYM_CODE_100T4 0x06
1108#define DC_SYM_CODE_100FX 0x07
1109#define DC_SYM_CODE_100FX_FDX 0x08
1110
1111 struct dc_eblock_reset {
1112 struct dc_eblock_hdr dc_reset_hdr;
1113 u_int8_t dc_reset_len;
1114/* u_int16_t dc_reset_dat[n]; */
1115};
1116
1117#ifdef __alpha__
1118#undef vtophys
1119#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
1120#endif
rtems_id
Objects_Id rtems_id
Used to manage and manipulate RTEMS object identifiers.
Definition: types.h:83
__rtems_irq_connect_data__
Definition: irq.h:45
dc_chain_data
Definition: if_dcreg.h:452
dc_desc
Definition: if_dcreg.h:368
dc_eblock_hdr
Definition: if_dcreg.h:1061
dc_eblock_mii
Definition: if_dcreg.h:1084
dc_eblock_reset
Definition: if_dcreg.h:1111
dc_eblock_sia
Definition: if_dcreg.h:1066
dc_eblock_sym
Definition: if_dcreg.h:1097
dc_info_leaf
Definition: if_dcreg.h:1021
dc_leaf_hdr
Definition: if_dcreg.h:1055
dc_list_data
Definition: if_dcreg.h:447
dc_mediainfo
Definition: if_dcreg.h:463
dc_mii_frame
Definition: if_dcreg.h:483
dc_softc
Definition: if_dcreg.h:681
dc_type
Definition: if_dcreg.h:473