RTEMS: bsps/powerpc/gen83xx/include/bsp/hwreg_vals.h Source File

| RTEMS 5.4-rc2

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hwreg_vals.h
1/*===============================================================*\
2| Project: RTEMS generic MPC83xx BSP |
3+-----------------------------------------------------------------+
4| Copyright (c) 2007 |
5| Embedded Brains GmbH |
6| Obere Lagerstr. 30 |
7| D-82178 Puchheim |
8| Germany |
9| rtems@embedded-brains.de |
10+-----------------------------------------------------------------+
11| The license and distribution terms for this file may be |
12| found in the file LICENSE in this distribution or at |
13| |
14| http://www.rtems.org/license/LICENSE. |
15| |
16+-----------------------------------------------------------------+
17| this file contains board specific definitions |
18\*===============================================================*/
19
20
21#ifndef __GEN83xx_HWREG_VALS_h
22#define __GEN83xx_HWREG_VALS_h
23
24#include <mpc83xx/mpc83xx.h>
25#include <bsp.h>
26
27#ifdef MPC83XX_HAS_NAND_LP_FLASH_ON_CS0
28 #define MPC83XX_RCWHR_BOOT_DEVICE (RCWHR_ROMLOC_LB08 | RCWHR_RLEXT_NAND)
29#else
30 #define MPC83XX_RCWHR_BOOT_DEVICE (RCWHR_ROMLOC_LB16 | RCWHR_RLEXT_LGCY)
31#endif
32
33/*
34 * distinguish board characteristics
35 */
36#if defined(MPC83XX_BOARD_MPC8349EAMDS)
37/*
38 * for Freescale MPC8349 EAMDS
39 */
40/*
41 * two DUART channels supported
42 */
43#define GEN83xx_DUART_AVAIL_MASK 0x03
44
45/* we need the low level initialization in start.S*/
46#define NEED_LOW_LEVEL_INIT
47/*
48 * clocking infos
49 */
50#define BSP_CLKIN_FRQ 66000000L
51#define RCFG_SYSPLL_MF 4
52#define RCFG_COREPLL_MF 4
53
54/*
55 * Reset configuration words
56 */
57#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \
58 RCWLR_DDRCM_1_1 | \
59 RCWLR_SPMF(RCFG_SYSPLL_MF) | \
60 RCWLR_COREPLL(RCFG_COREPLL_MF))
61
62#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \
63 RCWHR_PCI_32 | \
64 RCWHR_PCI1ARB_EN | \
65 RCWHR_PCI2ARB_EN | \
66 RCWHR_CORE_EN | \
67 RCWHR_BMS_LOW | \
68 RCWHR_BOOTSEQ_NONE | \
69 RCWHR_SW_DIS | \
70 MPC83XX_RCWHR_BOOT_DEVICE | \
71 RCWHR_TSEC1M_GMII | \
72 RCWHR_TSEC2M_GMII | \
73 RCWHR_ENDIAN_BIG | \
74 RCWHR_LALE_NORM | \
75 RCWHR_LDP_PAR)
76#elif defined(MPC83XX_BOARD_HSC_CM01)
77/*
78 * for JPK HSC_CM01
79 */
80/*
81 * one DUART channel (UART1) supported
82 */
83#define GEN83xx_DUART_AVAIL_MASK 0x01
84
85/* we need the low level initialization in start.S*/
86#define NEED_LOW_LEVEL_INIT
87/*
88 * clocking infos
89 */
90#define BSP_CLKIN_FRQ 30000000L
91#define RCFG_SYSPLL_MF 11
92#define RCFG_COREPLL_MF 4
93/*
94 * Reset configuration words
95 */
96#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \
97 RCWLR_DDRCM_1_1 | \
98 RCWLR_SPMF(RCFG_SYSPLL_MF) | \
99 RCWLR_COREPLL(RCFG_COREPLL_MF))
100
101#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \
102 RCWHR_PCI_32 | \
103 RCWHR_PCI1ARB_DIS | \
104 RCWHR_PCI2ARB_DIS | \
105 RCWHR_CORE_EN | \
106 RCWHR_BMS_LOW | \
107 RCWHR_BOOTSEQ_NONE | \
108 RCWHR_SW_DIS | \
109 MPC83XX_RCWHR_BOOT_DEVICE | \
110 RCWHR_TSEC1M_RGMII | \
111 RCWHR_TSEC2M_GMII | \
112 RCWHR_ENDIAN_BIG | \
113 RCWHR_LALE_EARLY | \
114 RCWHR_LDP_SPC)
115
116#elif defined(MPC83XX_BOARD_BR_UID)
117/*
118 * for BR UID
119 */
120/*
121 * one DUART channel (UART1) supported
122 */
123#define GEN83xx_DUART_AVAIL_MASK 0x01
124
125/* we need the low level initialization in start.S*/
126#define NEED_LOW_LEVEL_INIT
127/*
128 * clocking infos
129 */
130#define BSP_CLKIN_FRQ 25000000L
131#define RCFG_SYSPLL_MF 5
132#define RCFG_COREPLL_MF 5
133/*
134 * Reset configuration words
135 */
136#define RESET_CONF_WRD_L \
137 (RCWLR_LBIUCM_1_1 \
138 | RCWLR_DDRCM_2_1 \
139 | RCWLR_SPMF(RCFG_SYSPLL_MF) \
140 | RCWLR_COREPLL(RCFG_COREPLL_MF) \
141 | RCWLR_CEVCOD_1_2 \
142 | RCWLR_CEPMF(8) \
143 )
144
145#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \
146 RCWHR_PCI_32 | \
147 RCWHR_PCI1ARB_DIS | \
148 RCWHR_CORE_EN | \
149 RCWHR_BMS_LOW | \
150 RCWHR_BOOTSEQ_NONE | \
151 RCWHR_SW_DIS | \
152 MPC83XX_RCWHR_BOOT_DEVICE | \
153 RCWHR_ENDIAN_BIG)
154
155#elif defined( HAS_UBOOT)
156
157/* TODO */
158
159#else
160
161#error "board type not defined"
162
163#endif
164
165#if defined(MPC83XX_BOARD_MPC8349EAMDS)
166/**************************
167 * for Freescale MPC83XX_BOARD_MPC8349EAMDS
168 */
169
170/*
171 * working values for various registers, used in start/start.S
172 */
173
174/*
175 * Local Access Windows
176 * FIXME: decode bit settings
177 */
178#define LBLAWBAR0_VAL 0xFE000000
179#define LBLAWAR0_VAL 0x80000016
180#define LBLAWBAR1_VAL 0xF8000000
181#define LBLAWAR1_VAL 0x8000000E
182#define LBLAWBAR2_VAL 0xF0000000
183#define LBLAWAR2_VAL 0x80000019
184#define DDRLAWBAR0_VAL 0x00000000
185#define DDRLAWAR0_VAL 0x8000001B
186/*
187 * Local Bus (Memory) Controller
188 * FIXME: decode bit settings
189 */
190#define BR0_VAL 0xFE001001
191#define OR0_VAL 0xFF806FF7
192#define BR1_VAL 0xF8000801
193#define OR1_VAL 0xFFFFE8F0
194#define BR2_VAL 0xF0001861
195#define OR2_VAL 0xFC006901
196/*
197 * SDRAM registers
198 * FIXME: decode bit settings
199 */
200#define MRPTR_VAL 0x20000000
201#define LSRT_VAL 0x32000000
202#define LSDMR_VAL 0x4062D733
203#define LCRR_VAL 0x80000004
204
205/*
206 * DDR-SDRAM registers
207 * FIXME: decode bit settings
208 */
209#define CS2_BNDS_VAL 0x00000007
210#define CS3_BNDS_VAL 0x0008000F
211#define CS2_CONFIG_VAL 0x80000101
212#define CS3_CONFIG_VAL 0x80000101
213#define TIMING_CFG_1_VAL 0x36333321
214#define TIMING_CFG_2_VAL 0x00000800
215#define DDR_SDRAM_CFG_VAL 0xC2000000
216#define DDR_SDRAM_MODE_VAL 0x00000022
217#define DDR_SDRAM_INTTVL_VAL 0x045B0100
218#define DDR_SDRAM_CLK_CNTL_VAL 0x00000000
219
220#elif defined(MPC83XX_BOARD_HSC_CM01)
221/**************************
222 * for JPK HSC_CM01
223 */
224
225/*
226 * working values for various registers, used in start/start.S
227 */
228
229/* fpga config 16 MB size */
230#define FPGA_CONFIG_START 0xF8000000
231#define FPGA_CONFIG_SIZE 0x01000000
232/* fpga register 8 MB size */
233#define FPGA_REGISTER_START 0xF9000000
234#define FPGA_REGISTER_SIZE 0x00800000
235/* fpga fifo 8 MB size */
236#define FPGA_FIFO_START 0xF9800000
237#define FPGA_FIFO_SIZE 0x00800000
238
239#define FPGA_START (FPGA_CONFIG_START)
240// fpga window size 32 MByte
241#define FPGA_SIZE (0x02000000)
242#define FPGA_END (FPGA_START+FPGA_SIZE-1)
243
244/*
245 * Local Access Windows
246 * FIXME: decode bit settings
247 */
248
249#define LBLAWBAR0_VAL bsp_rom_start
250#define LBLAWAR0_VAL 0x80000018
251#define LBLAWBAR1_VAL (FPGA_CONFIG_START)
252#define LBLAWAR1_VAL 0x80000018
253#define DDRLAWBAR0_VAL bsp_ram_start
254#define DDRLAWAR0_VAL 0x8000001B
255/*
256 * Local Bus (Memory) Controller
257 * FIXME: decode bit settings
258 */
259#define BR0_VAL (0xFE000000 | 0x01001)
260#define OR0_VAL 0xFE000E54
261// fpga config access range (UPM_A) (32 kByte)
262#define BR2_VAL (FPGA_CONFIG_START | 0x01881)
263#define OR2_VAL 0xFFFF9100
264
265// fpga register access range (UPM_B) (8 MByte)
266#define BR3_VAL (FPGA_REGISTER_START | 0x018A1)
267#define OR3_VAL 0xFF801100
268
269// fpga fifo access range (UPM_C) (8 MByte)
270#define BR4_VAL (FPGA_FIFO_START | 0x018C1)
271#define OR4_VAL 0xFF801100
272
273/*
274 * SDRAM registers
275 */
276#define MRPTR_VAL 0x20000000
277#define LSRT_VAL 0x32000000
278#define LSDMR_VAL 0x4062D733
279#define LCRR_VAL 0x80010004
280
281/*
282 * DDR-SDRAM registers
283 * FIXME: decode bit settings
284 */
285#define DDRCDR_VAL 0x00000001
286#define CS0_BNDS_VAL 0x0000000F
287#define CS0_CONFIG_VAL 0x80810102
288#define TIMING_CFG_0_VAL 0x00420802
289#define TIMING_CFG_1_VAL 0x3735A322
290#define TIMING_CFG_2_VAL 0x2F9044C7
291#define DDR_SDRAM_CFG_2_VAL 0x00401000
292#define DDR_SDRAM_MODE_VAL 0x44521632
293#define DDR_SDRAM_CLK_CNTL_VAL 0x01800000
294#define DDR_SDRAM_CFG_VAL 0x63000008
295
296#define DDR_ERR_DISABLE_VAL 0x0000008D
297#define DDR_ERR_DISABLE_VAL2 0x00000089
298#define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE
299#define DDR_SDRAM_INIT_ADDR_VAL 0
300#define DDR_SDRAM_INTERVAL_VAL 0x05080000
301
302#elif defined(MPC83XX_BOARD_BR_UID)
303/**************************
304 * for BR UID
305 */
306
307/*
308 * working values for various registers, used in start/start.S
309 */
310
311/*
312 * Local Access Windows
313 * FIXME: decode bit settings
314 */
315
316#define LBLAWBAR0_VAL bsp_rom_start
317#define LBLAWAR0_VAL 0x80000018
318#define DDRLAWBAR0_VAL bsp_ram_start
319#define DDRLAWAR0_VAL 0x8000001B
320
321
322/*
323 * clocking for local bus:
324 * ALE active for 1 clock
325 * local bus clock = 1/2 csb clock
326 */
327#define LCRR_VAL 0x80010002
328
329/*
330 * DDR-SDRAM registers
331 * FIXME: decode bit settings
332 */
333#define DDRCDR_VAL 0x00000001
334#define CS0_BNDS_VAL 0x0000000F
335#define CS0_CONFIG_VAL 0x80014202
336#define TIMING_CFG_0_VAL 0x00220802
337#define TIMING_CFG_1_VAL 0x26259222
338#define TIMING_CFG_2_VAL 0x111048C7
339#define DDR_SDRAM_CFG_2_VAL 0x00401000
340#define DDR_SDRAM_MODE_VAL 0x200F1632
341#define DDR_SDRAM_MODE_2_VAL 0x40006000
342#define DDR_SDRAM_CLK_CNTL_VAL 0x01800000
343#define DDR_SDRAM_CFG_VAL 0x43100008
344
345#define DDR_ERR_DISABLE_VAL 0x0000008D
346#define DDR_ERR_DISABLE_VAL2 0x00000089
347#define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE
348#define DDR_SDRAM_INIT_ADDR_VAL 0
349#define DDR_SDRAM_INTERVAL_VAL 0x01E8222E
350
351#elif defined( HAS_UBOOT)
352
353/* TODO */
354
355#else
356
357#error "board type not defined"
358
359#endif
360
361/**************************
362 * derived values for all boards
363 */
364/* value of input clock divider (derived from pll mode reg) */
365#if MPC83XX_CHIP_TYPE != 8309
366 #define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1)
367#else
368 /* On the MPC8309 this bit is reserved */
369 #define BSP_SYSPLL_CKID 1
370#endif
371/* value of system pll (derived from pll mode reg) */
372#define BSP_SYSPLL_MF ((mpc83xx.clk.spmr>>(31-7))&0x0f)
373/* value of system pll (derived from pll mode reg) */
374#define BSP_COREPLL_MF ((mpc83xx.clk.spmr>>(31-15))&0x7f)
375
376#endif /* __GEN83xx_HWREG_VALS_h */