RTEMS: PLL Bypass Control

| RTEMS 5.4-rc2

Loading...
Searching...
No Matches
Functions
PLL Bypass Control
Board Support Packages » ARM » Intel Cyclone V » Contributed Code » The Clock Manager API

## Functions
ALT_STATUS_CODE | alt_clk_pll_bypass_disable (ALT_CLK_t pll)
ALT_STATUS_CODE | alt_clk_pll_bypass_enable (ALT_CLK_t pll, bool use_input_mux)
ALT_STATUS_CODE | alt_clk_pll_is_bypassed (ALT_CLK_t pll)

## Detailed Description

When a PLL is in bypass, the PLL clock logic is kept in reset. In this manner, the PLL clock can be free running while it stabilizes and achieves lock. The bypass logic isolates PLL configuration registers from the clock while changes are made to the PLL settings.

The bypass controls are used by software to change the source clock input reference (for Peripheral and SDRAM PLLs) and is recommended when changing settings that may affect the ability of the VCO to maintain lock. When a PLL is taken in or out of bypass the PLL output clocks will pause momentarily while the clocks are in transition, There will be no glitches or clocks shorter than the either the old or the new clock period.

In summary, the PLL bypass controls permit:

- Each PLL to be individually bypassed.
- Bypass of all PLL clock outputs to osc1_clk or alternatively the PLLs reference clock input source reference clock selection.
- Isolation of a the PLL VCO frequency registers (multiplier and divider), phase shift registers (negative phase) , and post scale counters.
- Glitch free clock transitions.

## Function Documentation

## ◆ alt_clk_pll_bypass_disable()

ALT_STATUS_CODE alt_clk_pll_bypass_disable | ( | ALT_CLK_t | pll | ) |

Disable bypass mode for the specified PLL. This operation takes the PLL out of bypass mode.

Parameters

  pll | The PLL to take out of bypass mode.

Return values

  ALT_E_SUCCESS | The operation was succesful.
  ALT_E_ERROR | The operation failed.
  ALT_E_BAD_ARG | The pll argument specified a non PLL clock value.

## ◆ alt_clk_pll_bypass_enable()

ALT_STATUS_CODE alt_clk_pll_bypass_enable | ( | ALT_CLK_t | pll,
|  | bool | use_input_mux
| ) |  |

Enable bypass mode for the specified PLL.

Parameters

  pll | The PLL to put into bypass mode.
  use_input_mux | If TRUE then use the PLLs reference clock input source selection to directly drive the bypass clock. If FALSE then use bypass clock directly driven by the osc1_clk.

Return values

  ALT_E_SUCCESS | The operation was succesful.
  ALT_E_ERROR | The operation failed.
  ALT_E_BAD_ARG | The pll argument specified a non PLL clock value.
  ALT_E_INV_OPTION | TRUE is an invalid option for use_input_mux with the pll selection.

## ◆ alt_clk_pll_is_bypassed()

ALT_STATUS_CODE alt_clk_pll_is_bypassed | ( | ALT_CLK_t | pll | ) |

Return whether the specified PLL is in bypass or not.

Parameters

  pll | The PLL to check whether in bypass mode or not.

Return values

  ALT_E_TRUE | The PLL is in bypass mode.
  ALT_E_FALSE | The PLL is not in bypass mode.
  ALT_E_BAD_ARG | The pll argument designates a non PLL clock value.