RTEMS: bsps/i386/pc386/net/3c509.h File Reference

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3c509.h File Reference
Board Support Packages » i386 » 3C509 Support

3C509 PC card support. More...

Go to the source code of this file.

## Macros
#define | F_RX_FIRST 0x1
#define | F_PROMISC 0x8
#define | F_ACCESS_32_BITS 0x100
#define | TX_INIT_RATE 16
#define | TX_INIT_MAX_RATE 64
#define | RX_INIT_LATENCY 64
#define | RX_INIT_EARLY_THRESH 208 /* not less than MINCLSIZE */
#define | RX_NEXT_EARLY_THRESH 500
#define | EEPROMSIZE 0x40
#define | MAX_EEPROMBUSY 1000
#define | EP_LAST_TAG 0xd7
#define | EP_MAX_BOARDS 16
#define | EP_ID_PORT 0x110
#define | EP_IOSIZE 16 /* 16 bytes of I/O space used. */
#define | IS_BASE (is->id_iobase)
#define | BASE (sc->ep_io_addr)
#define | EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */
#define | EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */
#define | EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
#define | EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */
#define | EEPROM_BUSY (1<<15)
#define | EEPROM_TST_MODE (1<<14)
#define | is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
#define | GO_WINDOW(x) outw(BASE+EP_COMMAND, WINDOW_SELECT|(x))
#define | EEPROM_NODE_ADDR_0 0x0 /* Word */
#define | EEPROM_NODE_ADDR_1 0x1 /* Word */
#define | EEPROM_NODE_ADDR_2 0x2 /* Word */
#define | EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */
#define | EEPROM_MFG_ID 0x7 /* 0x6d50 */
#define | EEPROM_ADDR_CFG 0x8 /* Base addr */
#define | EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */
#define | EP_COMMAND
#define | EP_STATUS
#define | EP_WINDOW
#define | EP_W0_EEPROM_DATA 0x0c
#define | EP_W0_EEPROM_COMMAND 0x0a
#define | EP_W0_RESOURCE_CFG 0x08
#define | EP_W0_ADDRESS_CFG 0x06
#define | EP_W0_CONFIG_CTRL 0x04
#define | EP_W0_PRODUCT_ID 0x02
#define | EP_W0_MFG_ID 0x00
#define | EP_W1_TX_PIO_WR_2 0x02
#define | EP_W1_TX_PIO_WR_1 0x00
#define | EP_W1_FREE_TX 0x0c
#define | EP_W1_TX_STATUS 0x0b /* byte */
#define | EP_W1_TIMER 0x0a /* byte */
#define | EP_W1_RX_STATUS 0x08
#define | EP_W1_RX_PIO_RD_2 0x02
#define | EP_W1_RX_PIO_RD_1 0x00
#define | EP_W2_ADDR_5 0x05
#define | EP_W2_ADDR_4 0x04
#define | EP_W2_ADDR_3 0x03
#define | EP_W2_ADDR_2 0x02
#define | EP_W2_ADDR_1 0x01
#define | EP_W2_ADDR_0 0x00
#define | EP_W3_FREE_TX 0x0c
#define | EP_W3_FREE_RX 0x0a
#define | EP_W4_MEDIA_TYPE 0x0a
#define | EP_W4_CTRLR_STATUS 0x08
#define | EP_W4_NET_DIAG 0x06
#define | EP_W4_FIFO_DIAG 0x04
#define | EP_W4_HOST_DIAG 0x02
#define | EP_W4_TX_DIAG 0x00
#define | EP_W5_READ_0_MASK 0x0c
#define | EP_W5_INTR_MASK 0x0a
#define | EP_W5_RX_FILTER 0x08
#define | EP_W5_RX_EARLY_THRESH 0x06
#define | EP_W5_TX_AVAIL_THRESH 0x02
#define | EP_W5_TX_START_THRESH 0x00
#define | TX_TOTAL_OK 0x0c
#define | RX_TOTAL_OK 0x0a
#define | TX_DEFERRALS 0x08
#define | RX_FRAMES_OK 0x07
#define | TX_FRAMES_OK 0x06
#define | RX_OVERRUNS 0x05
#define | TX_COLLISIONS 0x04
#define | TX_AFTER_1_COLLISION 0x03
#define | TX_AFTER_X_COLLISIONS 0x02
#define | TX_NO_SQE 0x01
#define | TX_CD_LOST 0x00
#define | GLOBAL_RESET
#define | WINDOW_SELECT (u_short) (0x1<<11)
#define | START_TRANSCEIVER
#define | RX_DISABLE
#define | RX_ENABLE (u_short) (0x4<<11)
#define | RX_RESET (u_short) (0x5<<11)
#define | RX_DISCARD_TOP_PACK (u_short) (0x8<<11)
#define | TX_ENABLE (u_short) (0x9<<11)
#define | TX_DISABLE (u_short) (0xa<<11)
#define | TX_RESET (u_short) (0xb<<11)
#define | REQ_INTR (u_short) (0xc<<11)
#define | SET_INTR_MASK (u_short) (0xe<<11)
#define | SET_RD_0_MASK (u_short) (0xf<<11)
#define | SET_RX_FILTER (u_short) (0x10<<11)
#define | FIL_INDIVIDUAL (u_short) (0x1)
#define | FIL_GROUP (u_short) (0x2)
#define | FIL_BRDCST (u_short) (0x4)
#define | FIL_ALL (u_short) (0x8)
#define | SET_RX_EARLY_THRESH (u_short) (0x11<<11)
#define | SET_TX_AVAIL_THRESH (u_short) (0x12<<11)
#define | SET_TX_START_THRESH (u_short) (0x13<<11)
#define | STATS_ENABLE (u_short) (0x15<<11)
#define | STATS_DISABLE (u_short) (0x16<<11)
#define | STOP_TRANSCEIVER (u_short) (0x17<<11)
#define | ACK_INTR (u_short) (0x6800)
#define | C_INTR_LATCH (u_short) (ACK_INTR|0x1)
#define | C_CARD_FAILURE (u_short) (ACK_INTR|0x2)
#define | C_TX_COMPLETE (u_short) (ACK_INTR|0x4)
#define | C_TX_AVAIL (u_short) (ACK_INTR|0x8)
#define | C_RX_COMPLETE (u_short) (ACK_INTR|0x10)
#define | C_RX_EARLY (u_short) (ACK_INTR|0x20)
#define | C_INT_RQD (u_short) (ACK_INTR|0x40)
#define | C_UPD_STATS (u_short) (ACK_INTR|0x80)
#define | C_MASK (u_short) 0xFF /* mask of C_* */
#define | S_INTR_LATCH (u_short) (0x1)
#define | S_CARD_FAILURE (u_short) (0x2)
#define | S_TX_COMPLETE (u_short) (0x4)
#define | S_TX_AVAIL (u_short) (0x8)
#define | S_RX_COMPLETE (u_short) (0x10)
#define | S_RX_EARLY (u_short) (0x20)
#define | S_INT_RQD (u_short) (0x40)
#define | S_UPD_STATS (u_short) (0x80)
#define | S_MASK (u_short) 0xFF /* mask of S_* */
#define | S_5_INTS
#define | S_COMMAND_IN_PROGRESS (u_short) (0x1000)
#define | ACF_CONNECTOR_BITS 14
#define | ACF_CONNECTOR_UTP 0
#define | ACF_CONNECTOR_AUI 1
#define | ACF_CONNECTOR_BNC 3
#define | SET_IRQ(base, irq)
#define | ERR_RX_INCOMPLETE (u_short) (0x1<<15)
#define | ERR_RX (u_short) (0x1<<14)
#define | ERR_RX_OVERRUN (u_short) (0x8<<11)
#define | ERR_RX_RUN_PKT (u_short) (0xb<<11)
#define | ERR_RX_ALIGN (u_short) (0xc<<11)
#define | ERR_RX_CRC (u_short) (0xd<<11)
#define | ERR_RX_OVERSIZE (u_short) (0x9<<11)
#define | ERR_RX_DRIBBLE (u_short) (0x2<<11)
#define | TXS_COMPLETE 0x80
#define | TXS_SUCCES_INTR_REQ 0x40
#define | TXS_JABBER 0x20
#define | TXS_UNDERRUN 0x10
#define | TXS_MAX_COLLISION 0x8
#define | TXS_STATUS_OVERFLOW 0x4
#define | IS_AUI (1<<13)
#define | IS_BNC (1<<12)
#define | IS_UTP (1<<9)
#define | ENABLE_DRQ_IRQ 0x0001
#define | W0_P4_CMD_RESET_ADAPTER 0x4
#define | W0_P4_CMD_ENABLE_ADAPTER 0x1
#define | ENABLE_UTP 0xc0
#define | DISABLE_UTP 0x0
#define | ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */
#define | MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */
#define | PROD_ID 0x9150
#define | AUI 0x1
#define | BNC 0x2
#define | UTP 0x4
#define | RX_BYTES_MASK (u_short) (0x07ff)

## Detailed Description

3C509 PC card support.

## Macro Definition Documentation

## ◆ EP_COMMAND

#define EP_COMMAND

Value:
0x0e /* Write. BASE+0x0e is always a
* command reg. */

## ◆ EP_STATUS

#define EP_STATUS

Value:
0x0e /* Read. BASE+0x0e is always status
* reg. */

## ◆ EP_WINDOW

#define EP_WINDOW

Value:
0x0f /* Read. BASE+0x0f is always window
* reg. */

## ◆ GLOBAL_RESET

#define GLOBAL_RESET

Value:
(u_short) 0x0000 /* Wait at least 1ms
* after issuing */

## ◆ RX_DISABLE

#define RX_DISABLE

Value:
(u_short) (0x3<<11) /* state disabled on
* power-up */

## ◆ S_5_INTS

#define S_5_INTS

Value:
(S_CARD_FAILURE|S_TX_COMPLETE|\
S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY)

## ◆ SET_IRQ

#define SET_IRQ | ( |  | base,
|  |  | irq
| ) |  |

Value:
outw((base) + EP_W0_RESOURCE_CFG, \
((inw((base) + EP_W0_RESOURCE_CFG) & 0x0fff) | \
((u_short)(irq)<<12)) ) /* set IRQ i */

## ◆ START_TRANSCEIVER

#define START_TRANSCEIVER

Value:
(u_short) (0x2<<11) /* Read ADDR_CFG reg to
* determine whether
* this is needed. If
* so; wait 800 uSec
* before using trans-
* ceiver. */