RTEMS: bsps/x86_64/amd64/include/clock.h Source File

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clock.h
1/*
2 * Copyright (c) 2018.
3 * Amaan Cheval <amaan.cheval@gmail.com>
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#ifndef _AMD64_CLOCK_H
28#define _AMD64_CLOCK_H
29
30#include <rtems/score/basedefs.h>
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
36#ifndef ASM
37 extern volatile uint32_t *amd64_apic_base;
38 bool has_apic_support(void);
39 void apic_initialize(void);
40 void apic_timer_install_handler(void);
41 uint32_t apic_timer_calibrate(void);
42 void apic_timer_initialize(uint64_t desired_freq_hz);
43 void amd64_clock_driver_initialize(void);
44#endif
45
46/* Number of times to calibrate the APIC timer to average it out */
47#define APIC_TIMER_NUM_CALIBRATIONS 5
48/* Default divide value used by APIC timer */
49#define APIC_TIMER_DIVIDE_VALUE 16
50/* Value to set in register to pick the divide value above */
51#define APIC_TIMER_SELECT_DIVIDER 3
52
53#define PIT_FREQUENCY 1193180
54/*
55 * The PIT_FREQUENCY determines how many times the PIT counter is decremented
56 * per second - therefore, we can calculate how many ticks we set based on what
57 * fraction of a second we're okay with spending on calibration
58 */
59#define PIT_CALIBRATE_DIVIDER 20
60#define PIT_CALIBRATE_TICKS (PIT_FREQUENCY/PIT_CALIBRATE_DIVIDER)
61/* Since the PIT only has 2 one-byte registers, the maximum tick value is
62 * limited to 16-bits. We can set the PIT to use a frequency divider if
63 * needed. */
64RTEMS_STATIC_ASSERT(
65 PIT_CALIBRATE_TICKS <= 0xffff,
66 PIT_CALIBRATE_DIVIDER
67);
68
69/* I/O ports for the PIT */
70#define PIT_PORT_CHAN0 0x40
71#define PIT_PORT_CHAN1 0x41
72#define PIT_PORT_CHAN2 0x42
73/*
74 * The input to channel 2 can be gated through software, using bit 0 of port
75 * 0x61.
76 */
77#define PIT_PORT_CHAN2_GATE 0x61
78#define PIT_CHAN2_TIMER_BIT 1
79#define PIT_CHAN2_SPEAKER_BIT 2
80/* The PIT mode/command register */
81#define PIT_PORT_MCR 0x43
82
83/* PIT values to select channels, access, and operating modes */
84#define PIT_SELECT_CHAN0 0b00000000
85#define PIT_SELECT_CHAN1 0b01000000
86#define PIT_SELECT_CHAN2 0b10000000
87/*
88 * In the lo/hi mode, the low-byte is sent to the data port, followed by the
89 * high-byte; this makes it important that this be an atomic operation.
90 */
91#define PIT_SELECT_ACCESS_LOHI 0b00110000
92#define PIT_SELECT_ONE_SHOT_MODE 0b00000010
93#define PIT_SELECT_BINARY_MODE 0
94
95#ifdef __cplusplus
96}
97#endif
98
99#endif /* _AMD64_CLOCK_H */
basedefs.h
Basic Definitions.