RTEMS: bsps/m68k/mvme167/include/bsp.h Source File

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bsp.h
Go to the documentation of this file.
1
9/*
10 * COPYRIGHT (c) 1989-2012.
11 * On-Line Applications Research Corporation (OAR).
12 *
13 * The license and distribution terms for this file may be
14 * found in the file LICENSE in this distribution or at
15 * http://www.rtems.org/license/LICENSE.
16 *
17 * Modifications of respective RTEMS file:
18 * Copyright (c) 1998, National Research Council of Canada
19 */
20
21#ifndef LIBBSP_M68K_MVME167_BSP_H
22#define LIBBSP_M68K_MVME167_BSP_H
23
34#include <bspopts.h>
35#include <bsp/default-initial-extension.h>
36
37#include <rtems.h>
38#include <rtems/bspIo.h>
39
40#include <mvme16x_hw.h>
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
46/* GCSR is in mvme16x_hw.h */
47/* LCSR is in mvme16x_hw.h */
48/* i82596 is in mvme16x_hw.h */
49/* NVRAM is in mvme16x_hw.h */
50
51#if 0
52/*
53 * Representation of the PCCchip2
54 */
55typedef volatile struct pccchip2_regs_ {
56 unsigned char chip_id; /* 0xFFF42000 */
57 unsigned char chip_revision; /* 0xFFF42001 */
58 unsigned char gen_control; /* 0xFFF42002 */
59 unsigned char vector_base; /* 0xFFF42003 */
60 unsigned long timer_cmp_1; /* 0xFFF42004 */
61 unsigned long timer_cnt_1; /* 0xFFF42008 */
62 unsigned long timer_cmp_2; /* 0xFFF4200C */
63 unsigned long timer_cnt_2; /* 0xFFF42010 */
64 unsigned char LSB_prescaler_count;/* 0xFFF42014 */
65 unsigned char prescaler_clock_adjust; /* 0xFFF42015 */
66 unsigned char timer_ctl_2; /* 0xFFF42016 */
67 unsigned char timer_ctl_1; /* 0xFFF42017 */
68 unsigned char gpi_int_ctl; /* 0xFFF42018 */
69 unsigned char gpio_ctl; /* 0xFFF42019 */
70 unsigned char timer_int_ctl_2; /* 0xFFF4201A */
71 unsigned char timer_int_ctl_1; /* 0xFFF4201B */
72 unsigned char SCC_error; /* 0xFFF4201C */
73 unsigned char SCC_modem_int_ctl; /* 0xFFF4201D */
74 unsigned char SCC_tx_int_ctl; /* 0xFFF4201E */
75 unsigned char SCC_rx_int_ctl; /* 0xFFF4201F */
76 unsigned char reserved1[3];
77 unsigned char modem_piack; /* 0xFFF42023 */
78 unsigned char reserved2;
79 unsigned char tx_piack; /* 0xFFF42025 */
80 unsigned char reserved3;
81 unsigned char rx_piack; /* 0xFFF42027 */
82 unsigned char LANC_error; /* 0xFFF42028 */
83 unsigned char reserved4;
84 unsigned char LANC_int_ctl; /* 0xFFF4202A */
85 unsigned char LANC_berr_ctl; /* 0xFFF4202B */
86 unsigned char SCSI_error; /* 0xFFF4202C */
87 unsigned char reserved5[2];
88 unsigned char SCSI_int_ctl; /* 0xFFF4202F */
89 unsigned char print_ack_int_ctl; /* 0xFFF42030 */
90 unsigned char print_fault_int_ctl;/* 0xFFF42031 */
91 unsigned char print_sel_int_ctl; /* 0xFFF42032 */
92 unsigned char print_pe_int_ctl; /* 0xFFF42033 */
93 unsigned char print_busy_int_ctl; /* 0xFFF42034 */
94 unsigned char reserved6;
95 unsigned char print_input_status; /* 0xFFF42036 */
96 unsigned char print_ctl; /* 0xFFF42037 */
97 unsigned char chip_speed; /* 0xFFF42038 */
98 unsigned char reserved7;
99 unsigned char print_data; /* 0xFFF4203A */
100 unsigned char reserved8[3];
101 unsigned char int_level; /* 0xFFF4203E */
102 unsigned char int_mask; /* 0xFFF4203F */
103} pccchip2_regs;
104
105/*
106 * Base address of the PCCchip2.
107 * This is not configurable in the MVME167.
108 */
109#define pccchip2 ((pccchip2_regs * const) 0xFFF42000)
110
111#endif
112/*
113 * The MVME167 is equiped with one or two MEMC040 memory controllers at
114 * 0xFFF43000 and 0xFFF43100. This port assumes that the controllers
115 * were initialized by 167Bug.
116 */
117 typedef volatile struct memc040_regs_ {
118 unsigned char chip_id; /* 0xFFF43000/0xFFF43100 */
119 unsigned char reserved1[3];
120 unsigned char chip_revision; /* 0xFFF43004/0xFFF43104 */
121 unsigned char reserved2[3];
122 unsigned char mem_config; /* 0xFFF43008/0xFFF43108 */
123 unsigned char reserved3[3];
124 unsigned char alt_status; /* 0xFFF4300C/0xFFF4310C */
125 unsigned char reserved4[3];
126 unsigned char alt_ctl; /* 0xFFF43010/0xFFF43110 */
127 unsigned char reserved5[3];
128 unsigned char base_addr; /* 0xFFF43014/0xFFF43114 */
129 unsigned char reserved6[3];
130 unsigned char ram_ctl; /* 0xFFF43018/0xFFF43118 */
131 unsigned char reserved7[3];
132 unsigned char bus_clk; /* 0xFFF4301C/0xFFF4311C */
133} memc040_regs;
134
135/*
136 * Base address of the MEMC040s.
137 * This is not configurable in the MVME167.
138 */
139#define memc040_1 ((memc040_regs * const) 0xFFF43000)
140#define memc040_2 ((memc040_regs * const) 0xFFF43100)
141
142/*
143 * The MVME167 may be equiped with error-correcting RAM cards. In this case,
144 * each MEMC040 is replaced by two MCECC ECC DRAM controllers. This port
145 * assumes that these controllers, if present, are initialized by 167Bug.
146 * They do not appear to hold information of interest at this time, so they
147 * are not described. However, each MCECC pair lives at the same address as
148 * the MEMC040 is replaces. The first eight registers of the MCECC are
149 * nearly identical to the ones of the MEMC040, and the memc040_X structures
150 * can be used to read those first eight registers.
151 */
152
153/*
154 * Representation of the Cirrus Logic CL-CD2401 Multi-Protocol Controller
155 */
156 typedef volatile struct cd2401_regs_ {
157 unsigned char reserved1[7];
158 unsigned char cor7; /* 0xFFF45007 - Channel Option 7 */
159 unsigned char reserved2;
160 unsigned char livr; /* 0xFFF45009 - Local Interrupt Vector */
161 unsigned char reserved3[6];
162 unsigned char cor1; /* 0xFFF45010 - Channel Option 1 */
163 unsigned char ier; /* 0xFFF45011 - Interrupt Enable */
164 unsigned char stcr; /* 0xFFF45012 - Special Transmit Command */
165 unsigned char ccr; /* 0xFFF45013 - Channel Command */
166 unsigned char cor5; /* 0xFFF45014 - Channel Option 5 */
167 unsigned char cor4; /* 0xFFF45015 - Channel Option 4 */
168 unsigned char cor3; /* 0xFFF45016 - Channel Option 3 */
169 unsigned char cor2; /* 0xFFF45017 - Channel Option 2 */
170 unsigned char cor6; /* 0xFFF45018 - Channel Option 6 */
171 unsigned char dmabsts; /* 0xFFF45019 - DMA Buffer Status */
172 unsigned char csr; /* 0xFFF4501A - Channel Status */
173 unsigned char cmr; /* 0xFFF4501B - Channel Mode */
174 union {
175 struct {
176 unsigned char schr4; /* 0xFFF4501C - Special Character 4 */
177 unsigned char schr3; /* 0xFFF4501D - Special Character 3 */
178 unsigned char schr2; /* 0xFFF4501E - Special Character 2 */
179 unsigned char schr1; /* 0xFFF4501F - Special Character 1 */
180 } async;
181 struct {
182 unsigned char rfar4; /* 0xFFF4501C - Receive Frame Address 4 */
183 unsigned char rfar3; /* 0xFFF4501D - Receive Frame Address 3 */
184 unsigned char rfar2; /* 0xFFF4501E - Receive Frame Address 2 */
185 unsigned char rfar1; /* 0xFFF4501F - Receive Frame Address 1 */
186 } sync;
187 } u1;
188 unsigned char reserved4[2];
189 unsigned char scrh; /* 0xFFF45022 - Special Character Range High */
190 unsigned char scrl; /* 0xFFF45023 - Special Character Range Low */
191 union {
192 struct {
193 unsigned short rtpr; /* 0xFFF45024 - Receive Timeout Period */
194 } w;
195 struct {
196 unsigned char rtprh; /* 0xFFF45024 - Receive Timeout Period High */
197 unsigned char rtprl; /* 0xFFF45025 - Receive Timeout Period Low */
198 } b;
199 } u2;
200 unsigned char licr; /* 0xFFF45026 - Local Interrupt Channel */
201 unsigned char reserved5[2];
202 union {
203 struct {
204 unsigned char ttr; /* 0xFFF45029 - Transmit Timer */
205 } async;
206 struct {
207 unsigned char gt2; /* 0xFFF45029 - General Timer 2 */
208 } sync;
209 } u3;
210 union {
211 struct {
212 unsigned short gt1; /* 0xFFF4502A - General Timer 1 */
213 } w;
214 struct {
215 unsigned char gt1h; /* 0xFFF4502A - General Timer 2 High */
216 unsigned char gt1l; /* 0xFFF4502B - General Timer 1 Low */
217 } b;
218 } u4;
219 unsigned char reserved6[2];
220 unsigned char lnxt; /* 0xFF4502E - LNext Character */
221 unsigned char reserved7;
222 unsigned char rfoc; /* 0xFFF45030 - Receive FIFO Output Count */
223 unsigned char reserved8[7];
224 unsigned short tcbadru; /* 0xFF45038 - Transmit Current Buffer Address Upper */
225 unsigned short tcbadrl; /* 0xFF4503A - Transmit Current Buffer Address Lower */
226 unsigned short rcbadru; /* 0xFF4503C - Receive Current Buffer Address Upper */
227 unsigned short rcbadrl; /* 0xFF4503E - Receive Current Buffer Address Lower */
228 unsigned short arbadru; /* 0xFF45040 - A Receive Buffer Address Upper */
229 unsigned short arbardl; /* 0xFF45042 - A Receive Buffer Address Lower */
230 unsigned short brbadru; /* 0xFF45044 - B Receive Buffer Address Upper */
231 unsigned short brbadrl; /* 0xFF45046 - B Receive Buffer Address Lower */
232 unsigned short brbcnt; /* 0xFF45048 - B Receive Buffer Byte Count */
233 unsigned short arbcnt; /* 0xFF4504A - A Receive Buffer Byte Count */
234 unsigned short reserved9;
235 unsigned char brbsts; /* 0xFF4504E - B Receive Buffer Status */
236 unsigned char arbsts; /* 0xFF4504F - A Receive Buffer Status */
237 unsigned short atbadru; /* 0xFF45050 - A Transmit Buffer Address Upper */
238 unsigned short atbadrl; /* 0xFF45052 - A Transmit Buffer Address Lower */
239 unsigned short btbadru; /* 0xFF45054 - B Transmit Buffer Address Upper */
240 unsigned short btbadrl; /* 0xFF45056 - B Transmit Buffer Address Lower */
241 unsigned short btbcnt; /* 0xFF45058 - B Transmit Buffer Byte Count */
242 unsigned short atbcnt; /* 0xFF4505A - A Transmit Buffer Byte Count */
243 unsigned short reserved10;
244 unsigned char btbsts; /* 0xFF4505E - B Transmit Buffer Status */
245 unsigned char atbsts; /* 0xFF4505F - A Transmit Buffer Status */
246 unsigned char reserved11[32];
247 unsigned char tftc; /* 0xFFF45080 - Transmit FIFO Transfer Count */
248 unsigned char gfrcr; /* 0xFFF45081 - Global Firmware Revision Code */
249 unsigned char reserved12[2];
250 unsigned char reoir; /* 0xFFF45084 - Receive End Of Interrupt */
251 unsigned char teoir; /* 0xFFF45085 - Transmit End Of Interrupt */
252 unsigned char meoir; /* 0xFFF45086 - Modem End Of Interrupt */
253 union {
254 struct {
255 unsigned short risr; /* 0xFFF45088 - Receive Interrupt Status */
256 } w;
257 struct {
258 unsigned char risrh; /* 0xFFF45088 - Receive Interrupt Status High */
259 unsigned char risrl; /* 0xFFF45089 - Receive Interrupt Status Low */
260 } b;
261 } u5;
262 unsigned char tisr; /* 0xFFF4508A - Transmit Interrupt Status */
263 unsigned char misr; /* 0xFFF4508B - Modem/Timer Interrupt Status */
264 unsigned char reserved13[2];
265 unsigned char bercnt; /* 0xFFF4508E - Bus Error Retry Count */
266 unsigned char reserved14[49];
267 unsigned char tcor; /* 0xFFF450C0 - Transmit Clock Option */
268 unsigned char reserved15[2];
269 unsigned char tbpr; /* 0xFFF450C3 - Transmit Baud Rate Period */
270 unsigned char reserved16[4];
271 unsigned char rcor; /* 0xFFF450C8 - Receive Clock Option */
272 unsigned char reserved17[2];
273 unsigned char rbpr; /* 0xFFF450CB - Receive Baud Rate Period */
274 unsigned char reserved18[10];
275 unsigned char cpsr; /* 0xFFF450D6 - CRC Polynomial Select */
276 unsigned char reserved19[3];
277 unsigned char tpr; /* 0xFFF450DA - Timer Period */
278 unsigned char reserved20[3];
279 unsigned char msvr_rts; /* 0xFFF450DE - Modem Signal Value - RTS */
280 unsigned char msvr_dtr; /* 0xFFF450DF - Modem Signal Value - DTR */
281 unsigned char tpilr; /* 0xFFF450E0 - Transmit Priority Interrupt Level */
282 unsigned char rpilr; /* 0xFFF450E1 - Receive Priority Interrupt Level */
283 unsigned char stk; /* 0xFFF450E2 - Stack */
284 unsigned char mpilr; /* 0xFFF450E3 - Modem Priority Interrupt Level */
285 unsigned char reserved21[8];
286 unsigned char tir; /* 0xFFF450EC - Transmit Interrupt */
287 unsigned char rir; /* 0xFFF450ED - Receive Interrupt */
288 unsigned char car; /* 0xFFF450EE - Channel Access */
289 unsigned char mir; /* 0xFFF450EF - Model Interrupt */
290 unsigned char reserved22[6];
291 unsigned char dmr; /* 0xFFF450F6 - DMA Mode */
292 unsigned char reserved23;
293 unsigned char dr; /* 0xFFF450F8 - Receive/Transmit Data */
294} cd2401_regs;
295
296/*
297 * Base address of the CD2401.
298 * This is not configurable in the MVME167.
299 */
300#define cd2401 ((cd2401_regs * const) 0xFFF45000)
301
302/* CD2401 is clocked at 20 MHz */
303#define CD2401_CLK_RATE 20000000
304
305/* BSP-wide functions */
306
307rtems_isr_entry set_vector(
308 rtems_isr_entry handler,
309 rtems_vector_number vector,
310 int type
311);
312
313#ifdef M167_INIT
314#undef EXTERN
315#define EXTERN
316#else
317#undef EXTERN
318#define EXTERN extern
319#endif
320
321extern void *M68Kvec[]; /* vector table address */
322
323#ifdef __cplusplus
324}
325#endif
326
329#endif
bspIo.h
Interface to Kernel Print Methods.
default-initial-extension.h
DEFAULT_INITIAL_EXTENSION Support.
rtems_vector_number
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition: intr.h:47
mvme16x_hw.h
MVME16x IO definitions.
rtems.h
cd2401_regs_
Definition: bsp.h:156
memc040_regs_
Definition: bsp.h:117
pccchip2_regs_
Definition: mvme16x_hw.h:128