RTEMS: cpukit/score/cpu/sparc64/include/rtems/score/sparc64.h File Reference

| RTEMS 5.4-rc2

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Macros | Functions
sparc64.h File Reference

Information Required to Build RTEMS for a Particular Member of the SPARC Family. More...

Go to the source code of this file.

## Macros
#define | SPARC_HAS_BITSCAN 0
#define | SPARC_NUMBER_OF_REGISTER_WINDOWS 8
#define | SPARC_HAS_FPU 1
#define | CPU_MODEL_NAME "w/FPU"
#define | CPU_NAME "SPARC"
#define | SPARC_PSTATE_AG_MASK 0x00000001 /* bit 0 */
#define | SPARC_PSTATE_IE_MASK 0x00000002 /* bit 1 */
#define | SPARC_PSTATE_PRIV_MASK 0x00000004 /* bit 2 */
#define | SPARC_PSTATE_AM_MASK 0x00000008 /* bit 3 */
#define | SPARC_PSTATE_PEF_MASK 0x00000010 /* bit 4 */
#define | SPARC_PSTATE_MM_MASK 0x00000040 /* bit 6 */
#define | SPARC_PSTATE_TLE_MASK 0x00000100 /* bit 8 */
#define | SPARC_PSTATE_CLE_MASK 0x00000200 /* bit 9 */
#define | SPARC_PSTATE_AG_BIT_POSITION 0 /* bit 0 */
#define | SPARC_PSTATE_IE_BIT_POSITION 1 /* bit 1 */
#define | SPARC_PSTATE_PRIV_BIT_POSITION 2 /* bit 2 */
#define | SPARC_PSTATE_AM_BIT_POSITION 3 /* bit 3 */
#define | SPARC_PSTATE_PEF_BIT_POSITION 4 /* bit 4 */
#define | SPARC_PSTATE_MM_BIT_POSITION 6 /* bit 6 */
#define | SPARC_PSTATE_TLE_BIT_POSITION 8 /* bit 8 */
#define | SPARC_PSTATE_CLE_BIT_POSITION 9 /* bit 9 */
#define | SPARC_FPRS_FEF_MASK 0x0100 /* bit 2 */
#define | SPARC_FPRS_FEF_BIT_POSITION 2 /* bit 2 */
#define | SPARC_TSTATE_IE_MASK 0x00000200 /* bit 9 */
#define | SPARC_SOFTINT_TM_MASK 0x00000001 /* bit 0 */
#define | SPARC_SOFTINT_SM_MASK 0x00010000 /* bit 16 */
#define | SPARC_SOFTINT_TM_BIT_POSITION 1 /* bit 0 */
#define | SPARC_SOFTINT_SM_BIT_POSITION 17 /* bit 16 */
#define | STACK_BIAS (2047)
#define | nop()
#define | sparc64_get_pstate(_pstate)
#define | sparc64_set_pstate(_pstate)
#define | sparc64_get_pil(_pil)
#define | sparc64_set_pil(_pil)
#define | sparc64_get_tba(_tba)
#define | sparc64_set_tba(_tba)
#define | sparc64_get_tl(_tl)
#define | sparc64_set_tl(_tl)
#define | sparc64_read_stick(_stick)
#define | sparc64_write_stick_cmpr(_stick_cmpr)
#define | sparc64_read_tick(_tick)
#define | sparc64_write_tick_cmpr(_tick_cmpr)
#define | sparc64_clear_interrupt_bits(_bit_mask)
#define | sparc_get_y(_y)
#define | sparc_set_y(_y)
#define | sparc_flash_interrupts(_level)
#define | sparc64_get_interrupt_level(_level)

## Functions
uint32_t | sparc_disable_interrupts (void)
void | sparc_enable_interrupts (uint32_t)

## Detailed Description

Information Required to Build RTEMS for a Particular Member of the SPARC Family.

This include file contains information pertaining to the SPARC processor family.

## Macro Definition Documentation

## ◆ nop

#define nop | ( |  | ) |

Value:
do { \
__asm__ volatile ( "nop" ); \
} while ( 0 )

## ◆ sparc64_clear_interrupt_bits

#define sparc64_clear_interrupt_bits | ( |  | _bit_mask | ) |

Value:
do { \
__asm__ volatile( "wr %%g0, %0, %%clear_softint" : "=r" (_bit_mask) \
: "0" (_bit_mask)); \
} while ( 0 )

## ◆ sparc64_get_interrupt_level

#define sparc64_get_interrupt_level | ( |  | _level | ) |

Value:
do { \
_level = 0; \
sparc64_get_pil( _level ); \
} while ( 0 )

## ◆ sparc64_get_pil

#define sparc64_get_pil | ( |  | _pil | ) |

Value:
do { \
(_pil) = 0; \
__asm__ volatile( "rdpr %%pil, %0" : "=r" (_pil) : "0" (_pil) ); \
} while ( 0 )

## ◆ sparc64_get_pstate

#define sparc64_get_pstate | ( |  | _pstate | ) |

Value:
do { \
(_pstate) = 0; \
__asm__ volatile( "rdpr %%pstate, %0" : "=r" (_pstate) : "0" (_pstate) ); \
} while ( 0 )

## ◆ sparc64_get_tba

#define sparc64_get_tba | ( |  | _tba | ) |

Value:
do { \
(_tba) = 0; /* to avoid unitialized warnings */ \
__asm__ volatile( "rdpr %%tba, %0" : "=r" (_tba) : "0" (_tba) ); \
} while ( 0 )

## ◆ sparc64_get_tl

#define sparc64_get_tl | ( |  | _tl | ) |

Value:
do { \
(_tl) = 0; /* to avoid unitialized warnings */ \
__asm__ volatile( "rdpr %%tl, %0" : "=r" (_tl) : "0" (_tl) ); \
} while ( 0 )

## ◆ sparc64_read_stick

#define sparc64_read_stick | ( |  | _stick | ) |

Value:
do { \
(_stick) = 0; \
__asm__ volatile( "rd %%stick, %0" : "=r" (_stick) : "0" (_stick) ); \
} while ( 0 )

## ◆ sparc64_read_tick

#define sparc64_read_tick | ( |  | _tick | ) |

Value:
do { \
(_tick) = 0; \
__asm__ volatile( "rd %%tick, %0" : "=r" (_tick) : "0" (_tick) ); \
} while ( 0 )

## ◆ sparc64_set_pil

#define sparc64_set_pil | ( |  | _pil | ) |

Value:
do { \
__asm__ volatile ( "wrpr %%g0, %0, %%pil " : "=r" ((_pil)) : "0" ((_pil)) ); \
} while ( 0 )

## ◆ sparc64_set_pstate

#define sparc64_set_pstate | ( |  | _pstate | ) |

Value:
do { \
__asm__ volatile ( \
"wrpr %%g0, %0, %%pstate " : "=r" ((_pstate)) : "0" ((_pstate)) ); \
} while ( 0 )

## ◆ sparc64_set_tba

#define sparc64_set_tba | ( |  | _tba | ) |

Value:
do { \
__asm__ volatile( "wrpr %%g0, %0, %%tba" : "=r" (_tba) : "0" (_tba) ); \
} while ( 0 )

## ◆ sparc64_set_tl

#define sparc64_set_tl | ( |  | _tl | ) |

Value:
do { \
__asm__ volatile( "wrpr %%g0, %0, %%tl" : "=r" (_tl) : "0" (_tl) ); \
} while ( 0 )

## ◆ sparc64_write_stick_cmpr

#define sparc64_write_stick_cmpr | ( |  | _stick_cmpr | ) |

Value:
do { \
__asm__ volatile( "wr %%g0, %0, %%stick_cmpr" : "=r" (_stick_cmpr) \
: "0" (_stick_cmpr) ); \
} while ( 0 )

## ◆ sparc64_write_tick_cmpr

#define sparc64_write_tick_cmpr | ( |  | _tick_cmpr | ) |

Value:
do { \
__asm__ volatile( "wr %%g0, %0, %%tick_cmpr" : "=r" (_tick_cmpr) \
: "0" (_tick_cmpr) ); \
} while ( 0 )

## ◆ sparc_flash_interrupts

#define sparc_flash_interrupts | ( |  | _level | ) |

Value:
do { \
uint32_t _ignored; \
\
sparc_enable_interrupts( (_level) ); \
_ignored = sparc_disable_interrupts(); \
(void) _ignored; \
} while ( 0 )

## ◆ sparc_get_y

#define sparc_get_y | ( |  | _y | ) |

Value:
do { \
__asm__ volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \
} while ( 0 )

## ◆ sparc_set_y

#define sparc_set_y | ( |  | _y | ) |

Value:
do { \
__asm__ volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \
} while ( 0 )