RTEMS: bsps/include/grlib/grspw_pkt.h Source File

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grspw_pkt.h
1/*
2 * GRSPW/GRSPW2 SpaceWire Kernel Library Interface
3 *
4 * COPYRIGHT (c) 2011
5 * Cobham Gaisler AB
6 *
7 * The license and distribution terms for this file may be
8 * found in the file LICENSE in this distribution or at
9 * http://www.rtems.org/license/LICENSE.
10 */
11
12#ifndef __GRSPW_PKT_H__
13#define __GRSPW_PKT_H__
14
15struct grspw_pkt;
16
17/* Maximum number of GRSPW devices supported by driver */
18#define GRSPW_MAX 32
19
20/* Weak overridable variable the user can use to define the worker-task
21 * priority (0..255) or to disable (-1) the creation of the worker-task
22 * and the message queue to save space */
23extern int grspw_work_task_priority;
24
25#ifndef GRSPW_PKT_FLAGS
26#define GRSPW_PKT_FLAGS
27/*** TX Packet flags ***/
28
29/* Enable IRQ generation */
30#define TXPKT_FLAG_IE 0x0040
31
32/* Enable Header CRC generation (if CRC is available in HW)
33 * Header CRC will be appended (one byte at end of header)
34 */
35#define TXPKT_FLAG_HCRC 0x0100
36
37/* Enable Data CRC generation (if CRC is available in HW)
38 * Data CRC will be appended (one or two byte at end of packet, depending on
39 * Data CRC type)
40 */
41#define TXPKT_FLAG_DCRC 0x0200
42
43/* Data CRC type */
44#define TXPKT_FLAG_DCRCT_MASK 0x0c00
45/* RMAP CRC. 1 byte */
46#define TXPKT_FLAG_DCRCT_RMAP 0x0000
47/* CCSDS/CCITT CRC-16. 2 byte */
48#define TXPKT_FLAG_DCRCT_CCSDS 0x0400
49/* 16-bit ISO-checksum (J.G. Fletcher, ISO 8473-1:1998). 2 byte */
50#define TXPKT_FLAG_DCRCT_ISO16 0x0800
51
52/* Control how many bytes the beginning of the Header
53 * the CRC should not be calculated for */
54#define TXPKT_FLAG_NOCRC_MASK 0x0000000f
55#define TXPKT_FLAG_NOCRC_LEN0 0x00000000
56#define TXPKT_FLAG_NOCRC_LEN1 0x00000001
57#define TXPKT_FLAG_NOCRC_LEN2 0x00000002
58#define TXPKT_FLAG_NOCRC_LEN3 0x00000003
59#define TXPKT_FLAG_NOCRC_LEN4 0x00000004
60#define TXPKT_FLAG_NOCRC_LEN5 0x00000005
61#define TXPKT_FLAG_NOCRC_LEN6 0x00000006
62#define TXPKT_FLAG_NOCRC_LEN7 0x00000007
63#define TXPKT_FLAG_NOCRC_LEN8 0x00000008
64#define TXPKT_FLAG_NOCRC_LEN9 0x00000009
65#define TXPKT_FLAG_NOCRC_LENa 0x0000000a
66#define TXPKT_FLAG_NOCRC_LENb 0x0000000b
67#define TXPKT_FLAG_NOCRC_LENc 0x0000000c
68#define TXPKT_FLAG_NOCRC_LENd 0x0000000d
69#define TXPKT_FLAG_NOCRC_LENe 0x0000000e
70#define TXPKT_FLAG_NOCRC_LENf 0x0000000f
71
72#define TXPKT_FLAG_INPUT_MASK (TXPKT_FLAG_NOCRC_MASK | TXPKT_FLAG_IE | \
73 TXPKT_FLAG_HCRC | TXPKT_FLAG_DCRC | \
74 TXPKT_FLAG_DCRCT_MASK)
75
76/* Marks if packet was transmitted or not */
77#define TXPKT_FLAG_TX 0x4000
78
79/* Link Error */
80#define TXPKT_FLAG_LINKERR 0x8000
81
82#define TXPKT_FLAG_OUTPUT_MASK (TXPKT_FLAG_TX | TXPKT_FLAG_LINKERR)
83
84/*** RX Packet Flags ***/
85
86/* Enable IRQ generation */
87#define RXPKT_FLAG_IE 0x0010
88
89#define RXPKT_FLAG_INPUT_MASK (RXPKT_FLAG_IE)
90
91/* Packet was truncated */
92#define RXPKT_FLAG_TRUNK 0x0800
93/* Data CRC error (only valid if RMAP CRC is enabled) */
94#define RXPKT_FLAG_DCRC 0x0400
95/* Header CRC error (only valid if RMAP CRC is enabled) */
96#define RXPKT_FLAG_HCRC 0x0200
97/* Error in End-of-Packet */
98#define RXPKT_FLAG_EEOP 0x0100
99/* Marks if packet was recevied or not */
100#define RXPKT_FLAG_RX 0x8000
101
102#define RXPKT_FLAG_OUTPUT_MASK (RXPKT_FLAG_TRUNK | RXPKT_FLAG_DCRC | \
103 RXPKT_FLAG_HCRC | RXPKT_FLAG_EEOP)
104
105/*** General packet flag options ***/
106
107/* Translate Hdr and/or Payload address */
108#define PKT_FLAG_TR_DATA 0x1000
109#define PKT_FLAG_TR_HDR 0x2000
110/* All General options */
111#define PKT_FLAG_MASK 0x3000
112
113#endif
114/* GRSPW RX/TX Packet structure.
115 *
116 * - For RX the 'hdr' and 'hlen' fields are not used, they are not written
117 * by driver.
118 *
119 * - The 'pkt_id' field is untouched by driver, it is intended for packet
120 * numbering or user-custom data.
121 *
122 * - The last packet in a list must have 'next' set to NULL.
123 *
124 * - data and hdr pointers are written without modification to hardware,
125 * this means that caller must do address translation to hardware
126 * address itself.
127 *
128 * - the 'flags' field are interpreted differently depending on transfer
129 * type (RX/TX). See XXPKT_FLAG_* options above.
130 */
131 struct grspw_pkt {
132 struct grspw_pkt *next; /* Next packet in list. NULL if last packet */
133 unsigned int pkt_id; /* User assigned ID (not touched by driver) */
134 unsigned short flags; /* RX/TX Options and status */
135 unsigned char reserved; /* Reserved, must be zero */
136 unsigned char hlen; /* Length of Header Buffer (only TX) */
137 unsigned int dlen; /* Length of Data Buffer */
138 void *data; /* 4-byte or byte aligned depends on HW */
139 void *hdr; /* 4-byte or byte aligned depends on HW (only TX) */
140};
141
142/* GRSPW SpaceWire Packet List */
143 struct grspw_list {
144 struct grspw_pkt *head;
145 struct grspw_pkt *tail;
146};
147
148/* SpaceWire Link State */
149typedef enum {
150 SPW_LS_ERRRST = 0,
151 SPW_LS_ERRWAIT = 1,
152 SPW_LS_READY = 2,
153 SPW_LS_STARTED = 3,
154 SPW_LS_CONNECTING = 4,
155 SPW_LS_RUN = 5
156} spw_link_state_t;
157
158/* Address Configuration */
159 struct grspw_addr_config {
160 /* Ignore address field and put all received packets to first
161 * DMA channel.
162 */
163 int promiscuous;
164
165 /* Default Node Address and Mask */
166 unsigned char def_addr;
167 unsigned char def_mask;
168 /* DMA Channel custom Node Address and Mask */
169 struct {
170 char node_en; /* Enable Separate Addr */
171 unsigned char node_addr; /* Node address */
172 unsigned char node_mask; /* Node address mask */
173 } dma_nacfg[4];
174};
175
176/* Hardware Support in GRSPW Core */
177 struct grspw_hw_sup {
178 char rmap; /* If RMAP in HW is available */
179 char rmap_crc; /* If RMAP CRC is available */
180 char rx_unalign; /* RX unaligned (byte boundary) access allowed*/
181 char nports; /* Number of Ports (1 or 2) */
182 char ndma_chans; /* Number of DMA Channels (1..4) */
183 char strip_adr; /* Hardware can strip ADR from packet data */
184 char strip_pid; /* Hardware can strip PID from packet data */
185 int hw_version; /* GRSPW Hardware Version */
186 char reserved[2];
187 char irq; /* SpW Distributed Interrupt available if 1 */
188 char irq_num; /* Number of interrupts that can be generated */
189 char itmr_width; /* SpW Intr. ISR timers bit width. 0=no timer */
190 char ccsds_crc; /* CCSDS CRC-16 and 16-bit ISO is available */
191};
192
193 struct grspw_core_stats {
194 int irq_cnt;
195 int err_credit;
196 int err_eeop;
197 int err_addr;
198 int err_parity;
199 int err_disconnect;
200 int err_escape;
201 int err_wsync; /* only in GRSPW1 */
202};
203
204/* grspw_link_ctrl() options */
205#define LINKOPTS_ENABLE 0x0000
206#define LINKOPTS_DISABLE 0x0001
207#define LINKOPTS_START 0x0002
208#define LINKOPTS_AUTOSTART 0x0004
209#define LINKOPTS_DIS_ONERR 0x0008 /* Disable DMA transmitter on link error
210 * Controls LE bit in DMACTRL register.
211 */
212#define LINKOPTS_DIS_ON_CE 0x0020000/* Disable Link on Credit error */
213#define LINKOPTS_DIS_ON_ER 0x0040000/* Disable Link on Escape error */
214#define LINKOPTS_DIS_ON_DE 0x0080000/* Disable Link on Disconnect error */
215#define LINKOPTS_DIS_ON_PE 0x0100000/* Disable Link on Parity error */
216#define LINKOPTS_DIS_ON_WE 0x0400000/* Disable Link on write synchonization
217 * error (GRSPW1 only)
218 */
219#define LINKOPTS_DIS_ON_EE 0x1000000/* Disable Link on Early EOP/EEP error*/
220
221/*#define LINKOPTS_TICK_OUT_IRQ 0x0100*//* Enable Tick-out IRQ */
222#define LINKOPTS_EIRQ 0x0200 /* Enable Error Link IRQ */
223
224#define LINKOPTS_MASK 0x15e020f/* All above options */
225#define LINKOPTS_MASK_DIS_ON 0x15e0000/* All disable link on error options
226 * On a certain error the link disable
227 * bit will be written and the work
228 * task will call dma_stop() for all
229 * channels.
230 */
231
232#define LINKSTS_CE 0x002 /* Credit error */
233#define LINKSTS_ER 0x004 /* Escape error */
234#define LINKSTS_DE 0x008 /* Disconnect error */
235#define LINKSTS_PE 0x010 /* Parity error */
236#define LINKSTS_WE 0x040 /* Write synchonization error (GRSPW1 only) */
237#define LINKSTS_IA 0x080 /* Invalid address */
238#define LINKSTS_EE 0x100 /* Early EOP/EEP */
239#define LINKSTS_MASK 0x1de
240
241/* grspw_tc_ctrl() options */
242#define TCOPTS_EN_RXIRQ 0x0001 /* Tick-Out IRQ */
243#define TCOPTS_EN_TX 0x0004
244#define TCOPTS_EN_RX 0x0008
245
246/* grspw_ic_ctrl() options:
247 * Corresponds code duplicatingly to GRSPW_CTRL_XX_BIT defines
248 */
249#define ICOPTS_INTNUM (0x1f << 27)
250#define ICOPTS_EN_SPWIRQ_ON_EE (1 << 24)
251#define ICOPTS_EN_SPWIRQ_ON_IA (1 << 23)
252#define ICOPTS_EN_PRIO (1 << 22)
253#define ICOPTS_EN_TIMEOUTIRQ (1 << 20)
254#define ICOPTS_EN_ACKIRQ (1 << 19)
255#define ICOPTS_EN_TICKOUTIRQ (1 << 18)
256#define ICOPTS_EN_RX (1 << 17)
257#define ICOPTS_EN_TX (1 << 16)
258#define ICOPTS_BASEIRQ (0x1f << 8)
259#define ICOPTS_EN_FLAGFILTER (1 << 0) /* NOTE: Not in icctrl. CTRL.bit12 */
260
261/* grspw_ic_rlisr() and grspw_ic_rlintack() */
262#define ICRELOAD_EN (1 << 31)
263#define ICRELOAD_MASK 0x7fffffff
264
265/* grspw_rmap_ctrl() options */
266#define RMAPOPTS_EN_RMAP 0x0001
267#define RMAPOPTS_EN_BUF 0x0002
268
269/* grspw_dma_config.flags options */
270#define DMAFLAG_NO_SPILL 0x0001 /* See HW doc DMA-CTRL NS bit */
271#define DMAFLAG_RESV1 0x0002 /* HAS NO EFFECT */
272#define DMAFLAG_STRIP_ADR 0x0004 /* See HW doc DMA-CTRL SA bit */
273#define DMAFLAG_STRIP_PID 0x0008 /* See HW doc DMA-CTRL SP bit */
274#define DMAFLAG_RESV2 0x0010 /* HAS NO EFFECT */
275#define DMAFLAG_MASK (DMAFLAG_NO_SPILL|DMAFLAG_STRIP_ADR|DMAFLAG_STRIP_PID)
276/* grspw_dma_config.flags misc options (not shifted internally) */
277#define DMAFLAG2_TXIE 0x00100000 /* See HW doc DMA-CTRL TI bit.
278 * Used to enable TX DMA interrupt
279 * when tx_irq_en_cnt=0.
280 */
281#define DMAFLAG2_RXIE 0x00200000 /* See HW doc DMA-CTRL RI bit.
282 * Used to enable RX DMA interrupt
283 * when rx_irq_en_cnt=0.
284 */
285/* Defines how the ISR will disable RX/TX DMA interrupt source when a DMA RX/TX
286 * interrupt has happended. DMA Error Interrupt always disables both RX/TX DMA
287 * interrupt. By default both RX/TX IRQs are disabled when either a RX, TX or
288 * both RX/TX DMA interrupt has been requested. The work-task, custom
289 * application handler or custom ISR handler is responsible to re-enable
290 * DMA interrupts.
291 */
292#define DMAFLAG2_IRQD_SRC 0x01000000 /* Disable triggering RX/TX source */
293#define DMAFLAG2_IRQD_NONE 0x00c00000 /* Never disable RX/TX IRQ in ISR */
294#define DMAFLAG2_IRQD_BOTH 0x00000000 /* Always disable both RX/TX sources */
295#define DMAFLAG2_IRQD_MASK 0x01c00000 /* Mask of options */
296#define DMAFLAG2_IRQD_BIT 22
297
298#define DMAFLAG2_MASK (DMAFLAG2_TXIE | DMAFLAG2_RXIE | DMAFLAG2_IRQD_MASK)
299
300struct grspw_dma_config {
301 int flags; /* DMA config flags, see DMAFLAG1&2_* options */
302 int rxmaxlen; /* RX Max Packet Length */
303 int rx_irq_en_cnt; /* Enable RX IRQ every cnt descriptors */
304 int tx_irq_en_cnt; /* Enable TX IRQ every cnt descriptors */
305};
306
307/* Statistics per DMA channel */
308struct grspw_dma_stats {
309 /* IRQ Statistics */
310 int irq_cnt; /* Number of DMA IRQs generated by channel */
311
312 /* Descriptor Statistics */
313 int tx_pkts; /* Number of Transmitted packets */
314 int tx_err_link; /* Number of Transmitted packets with Link Error*/
315 int rx_pkts; /* Number of Received packets */
316 int rx_err_trunk; /* Number of Received Truncated packets */
317 int rx_err_endpkt; /* Number of Received packets with bad ending */
318
319 /* Diagnostics to help developers sizing their number buffers to avoid
320 * out-of-buffers or other phenomenons.
321 */
322 int send_cnt_min; /* Minimum number of packets in TX SEND Q */
323 int send_cnt_max; /* Maximum number of packets in TX SEND Q */
324 int tx_sched_cnt_min; /* Minimum number of packets in TX SCHED Q */
325 int tx_sched_cnt_max; /* Maximum number of packets in TX SCHED Q */
326 int sent_cnt_max; /* Maximum number of packets in TX SENT Q */
327 int tx_work_cnt; /* Times the work thread processed TX BDs */
328 int tx_work_enabled; /* No. RX BDs enabled by work thread */
329
330 int ready_cnt_min; /* Minimum number of packets in RX READY Q */
331 int ready_cnt_max; /* Maximum number of packets in RX READY Q */
332 int rx_sched_cnt_min; /* Minimum number of packets in RX SCHED Q */
333 int rx_sched_cnt_max; /* Maximum number of packets in RX SCHED Q */
334 int recv_cnt_max; /* Maximum number of packets in RX RECV Q */
335 int rx_work_cnt; /* Times the work thread processed RX BDs */
336 int rx_work_enabled; /* No. RX BDs enabled by work thread */
337};
338
339/* ISR message sending call back. Compatible with rtems_message_queue_send().
340 * The 'buf' parameter has a pointer to a WORK-TASK message defined by the
341 * WORK_* macros below. The message indicates what GRSPW device operations
342 * are pending, thus what caused the interrupt.
343 *
344 * \param data defined by grspw_work_config.msgisr_arg, default a rtems_id.
345 * \param buf Pointer to a 32-bit message word
346 * \param n Always 4 (byte size of buf).
347 */
348typedef int (*grspw_msgqisr_t)(void *data, unsigned int *buf, unsigned int n);
349
350/* Work message definitions, the int sent to *buf
351 * Bits 31..24: reserved.
352 * Bits 23..16: GRSPW device number message is associated with.
353 * Bit 15: reserved.
354 * Bit 14: work-task shall delete message queue on exit.
355 * Bit 13: work-task shall exit and delete itself.
356 * Bit 12: link error - shut down all DMA operations (stop DMA channels).
357 * Bit 11..8: Indicats DMA error on DMA channel 3..0.
358 * Bit 7..0: Indicats RX and/or TX packets completed on channel 3..0.
359 */
360#define WORK_NONE 0
361#define WORK_SHUTDOWN 0x1000 /* Signal shut down */
362#define WORK_QUIT_TASK 0x2000 /* Work task shall exit (delete itself) */
363#define WORK_FREE_MSGQ 0x4000 /* Delete MsgQ (valid when WORK_QUIT_TASK) */
364#define WORK_DMA(chan, rxtx) (((rxtx) & 0x3) << ((chan) * 2))
365#define WORK_DMA_TX(chan) WORK_DMA(chan, 1)
366#define WORK_DMA_RX(chan) WORK_DMA(chan, 2)
367#define WORK_DMA_ER(chan) (0x1 << ((chan) + 8))
368#define WORK_DMA_MASK 0xfff /* max 4 channels all work */
369#define WORK_DMA_TX_MASK 0x055 /* max 4 channels TX work */
370#define WORK_DMA_RX_MASK 0x0aa /* max 4 channels RX work */
371#define WORK_DMA_ER_MASK 0xf00 /* max 4 channels Error work */
372#define WORK_DMA_CHAN_MASK(chan) (WORK_DMA_ER(chan) | WORK_DMA(chan, 0x3))
373#define WORK_CORE_BIT 16
374#define WORK_CORE_MASK 0x00ff0000
375#define WORK_CORE(device) ((device) << WORK_CORE_BIT)
376
377/* Message Q used to send messages to work task */
378struct grspw_work_config {
379 grspw_msgqisr_t msgisr;
380 void *msgisr_arg; /* example: rtems_id to Msg Q */
381};
382
383extern void grspw_initialize_user(
384 /* Callback every time a GRSPW device is found. Args: DeviceIndex */
385 void *(*devfound)(int),
386 /* Callback every time a GRSPW device is removed. Args:
387 * int = DeviceIndex
388 * void* = Return Value from devfound()
389 */
390 void (*devremove)(int,void*)
391 );
392
393/* Creates a MsgQ (optional) and spawns a worker task associated with the
394 * message Q. The task can also be associated with a custom msgQ if *msgQ.
395 * is non-zero.
396 *
397 * \param prio Task priority, set to -1 for default.
398 * \param stack Task stack size, set to 0 for default.
399 * \param msgQ pMsgQ=NULL: illegal,
400 * pMsqQ==0: create new MsgQ with task and place in *pMsgQ,
401 * *pmsqQ!=0: pointer to MsgQ used for task.
402 * \param msgMax Maximum number of messages, set to 0 for default.
403 * \return 0 on failure, task id on success.
404 */
405extern rtems_id grspw_work_spawn(int prio, int stack, rtems_id *pMsgQ, int msgMax);
406
407/* Free task associated with message queue and optionally also the message
408 * queue itself. The message queue is deleted by the work task and is therefore
409 * delayed until it the work task resumes its execution.
410 */
411extern rtems_status_code grspw_work_free(rtems_id msgQ, int freeMsgQ);
412
413/* Configure a GRSPW device Work task and Message Q set up.
414 * This affects messages to:
415 * - DMA AHB error interrupt handling (mandatory)
416 * - Link status interrupt handling (optional)
417 * - RX DMA, defaults to common msgQ (configured per DMA channel)
418 */
419extern void grspw_work_cfg(void *d, struct grspw_work_config *wc);
420
421/* Work-task function, called only from the work task. The function is provided
422 * as a way for the user to create its own work tasks.
423 * The argument determines which message queue the task shall read its
424 * work jobs from.
425 *
426 * The messages are always 32-bit words and follows the format defined by the
427 * WORK_* macros above.
428 */
429extern void grspw_work_func(rtems_id msgQ);
430
431enum grspw_worktask_ev {
432 WORKTASK_EV_NONE = 0,
433 WORKTASK_EV_QUIT = 1,
434 WORKTASK_EV_SHUTDOWN = 2,
435 WORKTASK_EV_DMA_STOP = 3,
436};
437
438/* Weak function to let user override. Function called every time one of the
439 * events above is handled by the work-task. The message 'msg' is the current
440 * message being processed by the work-task.
441 * The user can for example add custom code to invoke on a DMA error, link
442 * error or monitor when the work-task exits after a call to grspw_work_free().
443 */
444extern void grspw_work_event(enum grspw_worktask_ev ev, unsigned int msg);
445
446#ifdef RTEMS_SMP
447/* Set ISR interrupt affinity. The LEON IRQCtrl requires that the cpumask shall
448 * always have one bit set.
449 */
450extern int grspw_isr_affinity(void *d, const cpu_set_t *cpus);
451#endif
452
453extern int grspw_dev_count(void);
454extern void *grspw_open(int dev_no);
455extern int grspw_close(void *d);
456extern void grspw_hw_support(void *d, struct grspw_hw_sup *hw);
457extern void grspw_stats_read(void *d, struct grspw_core_stats *sts);
458extern void grspw_stats_clr(void *d);
459
460/* Set and Read current node address configuration. The dma_nacfg[N] field
461 * represents the configuration for DMA Channel N.
462 *
463 * Set cfg->promiscous to -1 in order to only read current configuration.
464 */
465extern void grspw_addr_ctrl(void *d, struct grspw_addr_config *cfg);
466
467/*** Link Control interface ***/
468/* Read Link State */
469extern spw_link_state_t grspw_link_state(void *d);
470/* options [in/out]: set to -1 to only read current config
471 *
472 * CLKDIV register contain:
473 * bits 7..0 : Clock Div RUN (only run-state)
474 * bits 15..8 : Clock Div During Startup (all link states except run-state)
475 */
476extern void grspw_link_ctrl(void *d, int *options, int *stscfg, int *clkdiv);
477/* Read the current value of the status register */
478extern unsigned int grspw_link_status(void *d);
479/* Clear bits in the status register */
480extern void grspw_link_status_clr(void *d, unsigned int clearmask);
481
482/*** Time Code Interface ***/
483/* Generate Tick-In (increment Time Counter, Send Time Code) */
484extern void grspw_tc_tx(void *d);
485/* Control Timcode settings of core */
486extern void grspw_tc_ctrl(void *d, int *options);
487/* Assign ISR Function to TimeCode RX IRQ */
488extern void grspw_tc_isr(void *d, void (*tcisr)(void *data, int tc), void *data);
489/* Read/Write TCTRL and TIMECNT. Write if not -1, always read current value
490 * TCTRL = bits 7 and 6
491 * TIMECNT = bits 5 to 0
492 */
493extern void grspw_tc_time(void *d, int *time);
494
495/*** Interrupt-code Interface ***/
496struct spwpkt_ic_config {
497 unsigned int tomask;
498 unsigned int aamask;
499 unsigned int scaler;
500 unsigned int isr_reload;
501 unsigned int ack_reload;
502};
503/* Function Interrupt-Code ISR callback prototype. Called when respective
504 * interrupt handling option has been enabled by grspw_ic_ctrl(), the
505 * arguments rxirq, rxack and intto are read from the registers of the
506 * GRSPW core read by the GRSPW ISR, they are individually valid only when
507 * repective handling been turned on.
508 *
509 * data - Custom data provided by user
510 * rxirq - Interrupt-Code Recevie register of the GRSPW core read by ISR
511 * (only defined if IQ bit enabled through grspw_ic_ctrl())
512 * rxack - Interrupt-Ack-Code Recevie register of the GRSPW core read by ISR
513 * (only defined if AQ bit enabled through grspw_ic_ctrl())
514 * intto - Interrupt Tick-out Recevie register of the GRSPW core read by ISR
515 * (only defined if TQ bit enabled through grspw_ic_ctrl())
516 */
517typedef void (*spwpkt_ic_isr_t)(void *data, unsigned int rxirq,
518 unsigned int rxack, unsigned int intto);
519/* Control Interrupt-code settings of core
520 * Write if 'options' not pointing to -1, always read current value
521 */
522extern void grspw_ic_ctrl(void *d, unsigned int *options);
523/* Write (rw&1 == 1) configuration parameters to registers and/or,
524 * Read (rw&2 == 1) configuration parameters from registers, in that sequence.
525 */
526extern void grspw_ic_config(void *d, int rw, struct spwpkt_ic_config *cfg);
527/* Read or Write Interrupt-code status registers.
528 * If pointer argument *ptr == 0 then only read, if *ptr != 0 then only write.
529 * If *ptr is NULL no operation.
530 */
531extern void grspw_ic_sts(void *d, unsigned int *rxirq, unsigned int *rxack,
532 unsigned int *intto);
533/* Generate Tick-In for the given Interrupt-code
534 * Returns zero on success and non-zero on failure
535 *
536 * Interrupt code bits (ic):
537 * Bit 5 - ACK if 1
538 * Bits 4-0 Interrupt-code number
539 */
540extern int grspw_ic_tickin(void *d, int ic);
541/* Assign handler function to Interrupt-code timeout IRQ */
542extern void grspw_ic_isr(void *d, spwpkt_ic_isr_t handler, void *data);
543
544/*** RMAP Control Interface ***/
545/* Set (not -1) and/or read RMAP options. */
546extern int grspw_rmap_ctrl(void *d, int *options, int *dstkey);
547extern void grspw_rmap_support(void *d, char *rmap, char *rmap_crc);
548
549/*** SpW Port Control Interface ***/
550
551/* Select port, if
552 * -1=The current selected port is returned
553 * 0=Port 0
554 * 1=Port 1
555 * Other positive values=Both Port0 and Port1
556 */
557extern int grspw_port_ctrl(void *d, int *port);
558/* Returns Number ports available in hardware */
559extern int grspw_port_count(void *d);
560/* Returns the current active port */
561extern int grspw_port_active(void *d);
562
563/*** DMA Interface ***/
564extern void *grspw_dma_open(void *d, int chan_no);
565extern int grspw_dma_close(void *c);
566
567extern int grspw_dma_start(void *c);
568extern void grspw_dma_stop(void *c);
569
570/* Enable interrupt manually */
571extern unsigned int grspw_dma_enable_int(void *c, int rxtx, int force);
572
573/* Return Current DMA Control & Status Register */
574extern unsigned int grspw_dma_ctrlsts(void *c);
575
576/* Schedule List of packets for transmission at some point in
577 * future.
578 *
579 * 1. Move transmitted packets to SENT List (SCHED->SENT)
580 * 2. Add the requested packets to the SEND List (USER->SEND)
581 * 3. Schedule as many packets as possible for transmission (SEND->SCHED)
582 *
583 * Call this function with pkts=NULL to just do step 1 and 3. This may be
584 * required in Polling-mode.
585 *
586 * The above steps 1 and 3 may be skipped by setting 'opts':
587 * bit0 = 1: Skip Step 1.
588 * bit1 = 1: Skip Step 3.
589 * Skipping both step 1 and 3 may be usefull when IRQ is enabled, then
590 * the work queue will be totaly responsible for handling descriptors.
591 *
592 * The fastest solution in retreiving sent TX packets and sending new frames
593 * is to call:
594 * A. grspw_dma_tx_reclaim(opts=0)
595 * B. grspw_dma_tx_send(opts=1)
596 *
597 * NOTE: the TXPKT_FLAG_TX flag must not be set.
598 *
599 * Return Code
600 * -1 Error
601 * 0 Successfully added pkts to send/sched list
602 * 1 DMA stopped. No operation.
603 */
604extern int grspw_dma_tx_send(void *c, int opts, struct grspw_list *pkts, int count);
605
606/* Reclaim TX packet buffers that has previously been scheduled for transmission
607 * with grspw_dma_tx_send().
608 *
609 * 1. Move transmitted packets to SENT List (SCHED->SENT)
610 * 2. Move all SENT List to pkts list (SENT->USER)
611 * 3. Schedule as many packets as possible for transmission (SEND->SCHED)
612 *
613 * The above steps 1 may be skipped by setting 'opts':
614 * bit0 = 1: Skip Step 1.
615 * bit1 = 1: Skip Step 3.
616 *
617 * The fastest solution in retreiving sent TX packets and sending new frames
618 * is to call:
619 * A. grspw_dma_tx_reclaim(opts=2) (Skip step 3)
620 * B. grspw_dma_tx_send(opts=1) (Skip step 1)
621 *
622 * Return Code
623 * -1 Error
624 * 0 Successful. pkts list filled with all packets from sent list
625 * 1 Same as 0, but indicates that DMA stopped
626 */
627extern int grspw_dma_tx_reclaim(void *c, int opts, struct grspw_list *pkts, int *count);
628
629/* Get current number of Packets in respective TX Queue. */
630extern void grspw_dma_tx_count(void *c, int *send, int *sched, int *sent, int *hw);
631
632#define GRSPW_OP_AND 0
633#define GRSPW_OP_OR 1
634/* Block until send_cnt or fewer packets are Queued in "Send and Scheduled" Q,
635 * op (AND or OR), sent_cnt or more packet "have been sent" (Sent Q) condition
636 * is met.
637 * If a link error occurs and the Stop on Link error is defined, this function
638 * will also return to caller.
639 * The timeout argument is used to return after timeout ticks, regardless of
640 * the other conditions. If timeout is zero, the function will wait forever
641 * until the condition is satisfied.
642 *
643 * NOTE: if IRQ of TX descriptors are not enabled conditions are never
644 * checked, this may hang infinitely unless a timeout has been specified
645 *
646 * Return Code
647 * -1 Error
648 * 0 Returing to caller because specified conditions are now fullfilled
649 * 1 DMA stopped
650 * 2 Timeout, conditions are not met
651 * 3 Another task is already waiting. Service is Busy.
652 */
653extern int grspw_dma_tx_wait(void *c, int send_cnt, int op, int sent_cnt, int timeout);
654
655/* Get received RX packet buffers that has previously been scheduled for
656 * reception with grspw_dma_rx_prepare().
657 *
658 * 1. Move Scheduled packets to RECV List (SCHED->RECV)
659 * 2. Move all RECV packet to the callers list (RECV->USER)
660 * 3. Schedule as many free packet buffers as possible (READY->SCHED)
661 *
662 * The above steps 1 may be skipped by setting 'opts':
663 * bit0 = 1: Skip Step 1.
664 * bit1 = 1: Skip Step 3.
665 *
666 * The fastest solution in retreiving received RX packets and preparing new
667 * packet buffers for future receive, is to call:
668 * A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3)
669 * B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1)
670 *
671 * Return Code
672 * -1 Error
673 * 0 Successfully filled pkts list with packets from recv list.
674 * 1 DMA stopped
675 */
676extern int grspw_dma_rx_recv(void *c, int opts, struct grspw_list *pkts, int *count);
677
678/* Add more RX packet buffers for future for reception. The received packets
679 * can later be read out with grspw_dma_rx_recv().
680 *
681 * 1. Move Received packets to RECV List (SCHED->RECV)
682 * 2. Add the "free/ready" packet buffers to the READY List (USER->READY)
683 * 3. Schedule as many packets as possible (READY->SCHED)
684 *
685 * The above steps 1 may be skipped by setting 'opts':
686 * bit0 = 1: Skip Step 1.
687 * bit1 = 1: Skip Step 3.
688 *
689 * The fastest solution in retreiving received RX packets and preparing new
690 * packet buffers for future receive, is to call:
691 * A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3)
692 * B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1)
693 *
694 * Return Code
695 * -1 Error
696 * 0 Successfully added packet buffers from pkt list into the ready queue
697 * 1 DMA stopped
698 */
699extern int grspw_dma_rx_prepare(void *c, int opts, struct grspw_list *pkts, int count);
700
701/* Get current number of Packets in respective RX Queue. */
702extern void grspw_dma_rx_count(void *c, int *ready, int *sched, int *recv, int *hw);
703
704/* Block until recv_cnt or more packets are Queued in RECV Q, op (AND or OR),
705 * ready_cnt or fewer packet buffers are available in the "READY and Scheduled" Q,
706 * condition is met.
707 * If a link error occurs and the Stop on Link error is defined, this function
708 * will also return to caller, however with an error.
709 * The timeout argument is used to return after timeout ticks, regardless of
710 * the other conditions. If timeout is zero, the function will wait forever
711 * until the condition is satisfied.
712 *
713 * NOTE: if IRQ of RX descriptors are not enabled conditions are never
714 * checked, this may hang infinitely unless a timeout has been specified
715 *
716 * Return Code
717 * -1 Error
718 * 0 Returing to caller because specified conditions are now fullfilled
719 * 1 DMA stopped
720 * 2 Timeout, conditions are not met
721 * 3 Another task is already waiting. Service is Busy.
722 */
723extern int grspw_dma_rx_wait(void *c, int recv_cnt, int op, int ready_cnt, int timeout);
724
725extern int grspw_dma_config(void *c, struct grspw_dma_config *cfg);
726extern void grspw_dma_config_read(void *c, struct grspw_dma_config *cfg);
727
728extern void grspw_dma_stats_read(void *c, struct grspw_dma_stats *sts);
729extern void grspw_dma_stats_clr(void *c);
730
731/* Register GRSPW packet driver to Driver Manager */
732void grspw2_register_drv (void);
733
734/*** GRSPW SpaceWire Packet List Handling Routines ***/
735
736static inline void grspw_list_clr(struct grspw_list *list)
737{
738 list->head = NULL;
739 list->tail = NULL;
740}
741
742static inline int grspw_list_is_empty(struct grspw_list *list)
743{
744 return (list->head == NULL);
745}
746
747/* Return Number of entries in list */
748static inline int grspw_list_cnt(struct grspw_list *list)
749{
750 struct grspw_pkt *lastpkt = NULL, *pkt = list->head;
751 int cnt = 0;
752 while ( pkt ) {
753 cnt++;
754 lastpkt = pkt;
755 pkt = pkt->next;
756 }
757 if ( lastpkt && (list->tail != lastpkt) )
758 return -1;
759 return cnt;
760}
761
762static inline void
763grspw_list_append(struct grspw_list *list, struct grspw_pkt *pkt)
764{
765 pkt->next = NULL;
766 if ( list->tail == NULL ) {
767 list->head = pkt;
768 } else {
769 list->tail->next = pkt;
770 }
771 list->tail = pkt;
772}
773
774static inline void
775grspw_list_prepend(struct grspw_list *list, struct grspw_pkt *pkt)
776{
777 pkt->next = list->head;
778 if ( list->head == NULL ) {
779 list->tail = pkt;
780 }
781 list->head = pkt;
782}
783
784static inline void
785grspw_list_append_list(struct grspw_list *list, struct grspw_list *alist)
786{
787 if (grspw_list_is_empty(alist)) {
788 return;
789 }
790 alist->tail->next = NULL;
791 if ( list->tail == NULL ) {
792 list->head = alist->head;
793 } else {
794 list->tail->next = alist->head;
795 }
796 list->tail = alist->tail;
797}
798
799static inline void
800grspw_list_prepend_list(struct grspw_list *list, struct grspw_list *alist)
801{
802 if (grspw_list_is_empty(alist)) {
803 return;
804 }
805 if ( list->head == NULL ) {
806 list->tail = alist->tail;
807 alist->tail->next = NULL;
808 } else {
809 alist->tail->next = list->head;
810 }
811 list->head = alist->head;
812}
813
814/* Remove dlist (delete-list) from head of list */
815static inline void
816grspw_list_remove_head_list(struct grspw_list *list, struct grspw_list *dlist)
817{
818 if (grspw_list_is_empty(dlist)) {
819 return;
820 }
821 list->head = dlist->tail->next;
822 if ( list->head == NULL ) {
823 list->tail = NULL;
824 }
825 dlist->tail->next = NULL;
826}
827
828/* Take A number of entries from head of list 'list' and put the entires
829 * to rlist (result list).
830 */
831static inline int
832grspw_list_take_head_list(struct grspw_list *list, struct grspw_list *rlist, int max)
833{
834 int cnt;
835 struct grspw_pkt *pkt, *last;
836
837 pkt = list->head;
838
839 if ( (max < 1) || (pkt == NULL) ) {
840 grspw_list_clr(rlist);
841 return 0;
842 }
843
844 cnt = 0;
845 rlist->head = pkt;
846 last = pkt;
847 while ((cnt < max) && pkt) {
848 last = pkt;
849 pkt = pkt->next;
850 cnt++;
851 }
852 rlist->tail = last;
853 grspw_list_remove_head_list(list, rlist);
854 return cnt;
855}
856
857#endif
NULL
#define NULL
Requests a GPIO pin group configuration.
Definition: bestcomm_api.h:77
rtems_status_code
rtems_status_code
Classic API Status.
Definition: status.h:43
rtems_id
Objects_Id rtems_id
Used to manage and manipulate RTEMS object identifiers.
Definition: types.h:83
grspw_addr_config
Definition: grspw_pkt.h:159
grspw_core_stats
Definition: grspw_pkt.h:193
grspw_dma_config
Definition: grspw_pkt.h:285
grspw_dma_stats
Definition: grspw_pkt.h:293
grspw_hw_sup
Definition: grspw_pkt.h:177
grspw_list
Definition: grspw_pkt.h:143
grspw_pkt
Definition: grspw_pkt.h:131
grspw_work_config
Definition: grspw_pkt.h:363
msg
Definition: b1553brm.c:75
spwpkt_ic_config
Definition: grspw_pkt.h:481