RTEMS: bsps/arm/csb337/include/at91rm9200_dbgu.h Source File

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at91rm9200_dbgu.h
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1
9/*
10 * Atmel AT91RM9200_DBGU Register definitions
11 *
12 * Copyright (c) 2003 by Cogent Computer Systems
13 * Written by Mike Kelly <mike@cogcomp.com>
14 *
15 * The license and distribution terms for this file may be
16 * found in the file LICENSE in this distribution or at
17 * http://www.rtems.org/license/LICENSE.
18 */
19#ifndef __AT91RM9200_DBGU_H__
20#define __AT91RM9200_DBGU_H__
21
22#include "bits.h"
23
24/* Register Offsets */
25#define DBGU_CR 0x00 /* Control Register */
26#define DBGU_MR 0x04 /* Mode Register */
27#define DBGU_IER 0x08 /* Interrupt Enable Register */
28#define DBGU_IDR 0x0C /* Interrupt Disable Register */
29#define DBGU_IMR 0x10 /* Interrupt Mask Register */
30#define DBGU_SR 0x14 /* Channel Status Register */
31#define DBGU_RHR 0x18 /* Receiver Holding Register */
32#define DBGU_THR 0x1C /* Transmitter Holding Register */
33#define DBGU_BRGR 0x20 /* Baud Rate Generator Register */
34#define DBGU_C1R 0x40 /* Chip ID1 Register */
35#define DBGU_C2R 0x44 /* Chip ID2 Register */
36#define DBGU_FNTR 0x48 /* Force NTRST Register */
37
38/* Bit Defines */
39/* Control Register, DBGU_CR, Offset 0x00 */
40#define DBGU_CR_RSTRX BIT2 /* 1 = Reset and disable receiver */
41#define DBGU_CR_RSTTX BIT3 /* 1 = Reset and disable transmitter */
42#define DBGU_CR_RXEN BIT4 /* 1 = Receiver enable */
43#define DBGU_CR_RXDIS BIT5 /* 1 = Receiver disable */
44#define DBGU_CR_TXEN BIT6 /* 1 = Transmitter enable */
45#define DBGU_CR_TXDIS BIT7 /* 1 = Transmitter disable */
46#define DBGU_CR_RSTSTA BIT8 /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */
47
48/* Mode Register. DBGU_MR. Offset 0x04 */
49#define DBGU_MR_PAR_EVEN (0x0 << 9) /* Even Parity */
50#define DBGU_MR_PAR_ODD (0x1 << 9) /* Odd Parity */
51#define DBGU_MR_PAR_SPACE (0x2 << 9) /* Parity forced to 0 (Space) */
52#define DBGU_MR_PAR_MARK (0x3 << 9) /* Parity forced to 1 (Mark) */
53#define DBGU_MR_PAR_NONE (0x4 << 9) /* No Parity */
54#define DBGU_MR_PAR_MDROP (0x6 << 9) /* Multi-drop mode */
55#define DBGU_MR_CHMODE_NORM (0x0 << 14) /* Normal Mode */
56#define DBGU_MR_CHMODE_AUTO (0x1 << 14) /* Auto Echo: RXD drives TXD */
57#define DBGU_MR_CHMODE_LOC (0x2 << 14) /* Local Loopback: TXD drives RXD */
58#define DBGU_MR_CHMODE_REM (0x3 << 14) /* Remote Loopback: RXD pin connected to TXD pin. */
59
60/* Interrupt Enable Register, DBGU_IER, Offset 0x08 */
61/* Interrupt Disable Register, DBGU_IDR, Offset 0x0C */
62/* Interrupt Mask Register, DBGU_IMR, Offset 0x10 */
63/* Channel Status Register, DBGU_SR, Offset 0x14 */
64#define DBGU_INT_RXRDY BIT0 /* RXRDY Interrupt */
65#define DBGU_INT_TXRDY BIT1 /* TXRDY Interrupt */
66#define DBGU_INT_ENDRX BIT3 /* End of Receive Transfer Interrupt */
67#define DBGU_INT_ENDTX BIT4 /* End of Transmit Interrupt */
68#define DBGU_INT_OVRE BIT5 /* Overrun Interrupt */
69#define DBGU_INT_FRAME BIT6 /* Framing Error Interrupt */
70#define DBGU_INT_PARE BIT7 /* Parity Error Interrupt */
71#define DBGU_INT_TXEMPTY BIT9 /* TXEMPTY Interrupt */
72#define DBGU_INT_TXBUFE BIT11 /* TXBUFE Interrupt */
73#define DBGU_INT_RXBUFF BIT12 /* RXBUFF Interrupt */
74#define DBGU_INT_COMM_TX BIT30 /* COMM_TX Interrupt */
75#define DBGU_INT_COMM_RX BIT31 /* COMM_RX Interrupt */
76#define DBGU_INT_ALL 0xC0001AFB /* all assigned bits */
77
78/* FORCE_NTRST Register, DBGU_FNTR, Offset 0x48 */
79#define DBGU_FNTR_NTRST BIT0 /* 1 = Force NTRST low in JTAG */
80
81 typedef struct {
82 volatile uint32_t cr;
83 volatile uint32_t mr;
84 volatile uint32_t ier;
85 volatile uint32_t idr;
86 volatile uint32_t imr;
87 volatile uint32_t sr;
88 volatile uint32_t rhr;
89 volatile uint32_t thr;
90 volatile uint32_t brgr;
91 volatile uint32_t _res0[7];
92 volatile uint32_t cidr;
93 volatile uint32_t exid;
94 volatile uint32_t fnr;
95} at91rm9200_dbgu_regs_t;
96
97#endif /* __AT91RM9200_DBGU_H__ */
bits.h
Contains Defined Bits.
at91rm9200_dbgu_regs_t
Definition: at91rm9200_dbgu.h:81