RTEMS: bsps/arm/atsam/include/libchip/include/same70/component/component_supc.h Source File

| RTEMS 5.4-rc2

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component_supc.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAME70_SUPC_COMPONENT_
31#define _SAME70_SUPC_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41 typedef struct {
42 __O uint32_t SUPC_CR;
43 __IO uint32_t SUPC_SMMR;
44 __IO uint32_t SUPC_MR;
45 __IO uint32_t SUPC_WUMR;
46 __IO uint32_t SUPC_WUIR;
47 __I uint32_t SUPC_SR;
48} Supc;
49#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
50/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
51#define SUPC_CR_VROFF (0x1u << 2)
52#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2)
53#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2)
54#define SUPC_CR_XTALSEL (0x1u << 3)
55#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3)
56#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3)
57#define SUPC_CR_KEY_Pos 24
58#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos)
59#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
60#define SUPC_CR_KEY_PASSWD (0xA5u << 24)
61/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
62#define SUPC_SMMR_SMTH_Pos 0
63#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos)
64#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos)))
65#define SUPC_SMMR_SMSMPL_Pos 8
66#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos)
67#define SUPC_SMMR_SMSMPL(value) ((SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos)))
68#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8)
69#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8)
70#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8)
71#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8)
72#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8)
73#define SUPC_SMMR_SMRSTEN (0x1u << 12)
74#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12)
75#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12)
76#define SUPC_SMMR_SMIEN (0x1u << 13)
77#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13)
78#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13)
79/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
80#define SUPC_MR_BODRSTEN (0x1u << 12)
81#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12)
82#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12)
83#define SUPC_MR_BODDIS (0x1u << 13)
84#define SUPC_MR_BODDIS_ENABLE (0x0u << 13)
85#define SUPC_MR_BODDIS_DISABLE (0x1u << 13)
86#define SUPC_MR_ONREG (0x1u << 14)
87#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14)
88#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14)
89#define SUPC_MR_BKUPRETON (0x1u << 17)
90#define SUPC_MR_OSCBYPASS (0x1u << 20)
91#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20)
92#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20)
93#define SUPC_MR_KEY_Pos 24
94#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos)
95#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
96#define SUPC_MR_KEY_PASSWD (0xA5u << 24)
97/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */
98#define SUPC_WUMR_SMEN (0x1u << 1)
99#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1)
100#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1)
101#define SUPC_WUMR_RTTEN (0x1u << 2)
102#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2)
103#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2)
104#define SUPC_WUMR_RTCEN (0x1u << 3)
105#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3)
106#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3)
107#define SUPC_WUMR_LPDBCEN0 (0x1u << 5)
108#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5)
109#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5)
110#define SUPC_WUMR_LPDBCEN1 (0x1u << 6)
111#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6)
112#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6)
113#define SUPC_WUMR_LPDBCCLR (0x1u << 7)
114#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7)
115#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7)
116#define SUPC_WUMR_WKUPDBC_Pos 12
117#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos)
118#define SUPC_WUMR_WKUPDBC(value) ((SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos)))
119#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12)
120#define SUPC_WUMR_WKUPDBC_3_SLCK (0x1u << 12)
121#define SUPC_WUMR_WKUPDBC_32_SLCK (0x2u << 12)
122#define SUPC_WUMR_WKUPDBC_512_SLCK (0x3u << 12)
123#define SUPC_WUMR_WKUPDBC_4096_SLCK (0x4u << 12)
124#define SUPC_WUMR_WKUPDBC_32768_SLCK (0x5u << 12)
125#define SUPC_WUMR_LPDBC_Pos 16
126#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos)
127#define SUPC_WUMR_LPDBC(value) ((SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos)))
128#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16)
129#define SUPC_WUMR_LPDBC_2_RTCOUT (0x1u << 16)
130#define SUPC_WUMR_LPDBC_3_RTCOUT (0x2u << 16)
131#define SUPC_WUMR_LPDBC_4_RTCOUT (0x3u << 16)
132#define SUPC_WUMR_LPDBC_5_RTCOUT (0x4u << 16)
133#define SUPC_WUMR_LPDBC_6_RTCOUT (0x5u << 16)
134#define SUPC_WUMR_LPDBC_7_RTCOUT (0x6u << 16)
135#define SUPC_WUMR_LPDBC_8_RTCOUT (0x7u << 16)
136/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */
137#define SUPC_WUIR_WKUPEN0 (0x1u << 0)
138#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0)
139#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0)
140#define SUPC_WUIR_WKUPEN1 (0x1u << 1)
141#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1)
142#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1)
143#define SUPC_WUIR_WKUPEN2 (0x1u << 2)
144#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2)
145#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2)
146#define SUPC_WUIR_WKUPEN3 (0x1u << 3)
147#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3)
148#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3)
149#define SUPC_WUIR_WKUPEN4 (0x1u << 4)
150#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4)
151#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4)
152#define SUPC_WUIR_WKUPEN5 (0x1u << 5)
153#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5)
154#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5)
155#define SUPC_WUIR_WKUPEN6 (0x1u << 6)
156#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6)
157#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6)
158#define SUPC_WUIR_WKUPEN7 (0x1u << 7)
159#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7)
160#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7)
161#define SUPC_WUIR_WKUPEN8 (0x1u << 8)
162#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8)
163#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8)
164#define SUPC_WUIR_WKUPEN9 (0x1u << 9)
165#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9)
166#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9)
167#define SUPC_WUIR_WKUPEN10 (0x1u << 10)
168#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10)
169#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10)
170#define SUPC_WUIR_WKUPEN11 (0x1u << 11)
171#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11)
172#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11)
173#define SUPC_WUIR_WKUPEN12 (0x1u << 12)
174#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12)
175#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12)
176#define SUPC_WUIR_WKUPEN13 (0x1u << 13)
177#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13)
178#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13)
179#define SUPC_WUIR_WKUPT0 (0x1u << 16)
180#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16)
181#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16)
182#define SUPC_WUIR_WKUPT1 (0x1u << 17)
183#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17)
184#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17)
185#define SUPC_WUIR_WKUPT2 (0x1u << 18)
186#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18)
187#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18)
188#define SUPC_WUIR_WKUPT3 (0x1u << 19)
189#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19)
190#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19)
191#define SUPC_WUIR_WKUPT4 (0x1u << 20)
192#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20)
193#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20)
194#define SUPC_WUIR_WKUPT5 (0x1u << 21)
195#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21)
196#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21)
197#define SUPC_WUIR_WKUPT6 (0x1u << 22)
198#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22)
199#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22)
200#define SUPC_WUIR_WKUPT7 (0x1u << 23)
201#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23)
202#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23)
203#define SUPC_WUIR_WKUPT8 (0x1u << 24)
204#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24)
205#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24)
206#define SUPC_WUIR_WKUPT9 (0x1u << 25)
207#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25)
208#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25)
209#define SUPC_WUIR_WKUPT10 (0x1u << 26)
210#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26)
211#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26)
212#define SUPC_WUIR_WKUPT11 (0x1u << 27)
213#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27)
214#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27)
215#define SUPC_WUIR_WKUPT12 (0x1u << 28)
216#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28)
217#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28)
218#define SUPC_WUIR_WKUPT13 (0x1u << 29)
219#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29)
220#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29)
221/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
222#define SUPC_SR_WKUPS (0x1u << 1)
223#define SUPC_SR_WKUPS_NO (0x0u << 1)
224#define SUPC_SR_WKUPS_PRESENT (0x1u << 1)
225#define SUPC_SR_SMWS (0x1u << 2)
226#define SUPC_SR_SMWS_NO (0x0u << 2)
227#define SUPC_SR_SMWS_PRESENT (0x1u << 2)
228#define SUPC_SR_BODRSTS (0x1u << 3)
229#define SUPC_SR_BODRSTS_NO (0x0u << 3)
230#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3)
231#define SUPC_SR_SMRSTS (0x1u << 4)
232#define SUPC_SR_SMRSTS_NO (0x0u << 4)
233#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4)
234#define SUPC_SR_SMS (0x1u << 5)
235#define SUPC_SR_SMS_NO (0x0u << 5)
236#define SUPC_SR_SMS_PRESENT (0x1u << 5)
237#define SUPC_SR_SMOS (0x1u << 6)
238#define SUPC_SR_SMOS_HIGH (0x0u << 6)
239#define SUPC_SR_SMOS_LOW (0x1u << 6)
240#define SUPC_SR_OSCSEL (0x1u << 7)
241#define SUPC_SR_OSCSEL_RC (0x0u << 7)
242#define SUPC_SR_OSCSEL_CRYST (0x1u << 7)
243#define SUPC_SR_LPDBCS0 (0x1u << 13)
244#define SUPC_SR_LPDBCS0_NO (0x0u << 13)
245#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13)
246#define SUPC_SR_LPDBCS1 (0x1u << 14)
247#define SUPC_SR_LPDBCS1_NO (0x0u << 14)
248#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14)
249#define SUPC_SR_WKUPIS0 (0x1u << 16)
250#define SUPC_SR_WKUPIS0_DIS (0x0u << 16)
251#define SUPC_SR_WKUPIS0_EN (0x1u << 16)
252#define SUPC_SR_WKUPIS1 (0x1u << 17)
253#define SUPC_SR_WKUPIS1_DIS (0x0u << 17)
254#define SUPC_SR_WKUPIS1_EN (0x1u << 17)
255#define SUPC_SR_WKUPIS2 (0x1u << 18)
256#define SUPC_SR_WKUPIS2_DIS (0x0u << 18)
257#define SUPC_SR_WKUPIS2_EN (0x1u << 18)
258#define SUPC_SR_WKUPIS3 (0x1u << 19)
259#define SUPC_SR_WKUPIS3_DIS (0x0u << 19)
260#define SUPC_SR_WKUPIS3_EN (0x1u << 19)
261#define SUPC_SR_WKUPIS4 (0x1u << 20)
262#define SUPC_SR_WKUPIS4_DIS (0x0u << 20)
263#define SUPC_SR_WKUPIS4_EN (0x1u << 20)
264#define SUPC_SR_WKUPIS5 (0x1u << 21)
265#define SUPC_SR_WKUPIS5_DIS (0x0u << 21)
266#define SUPC_SR_WKUPIS5_EN (0x1u << 21)
267#define SUPC_SR_WKUPIS6 (0x1u << 22)
268#define SUPC_SR_WKUPIS6_DIS (0x0u << 22)
269#define SUPC_SR_WKUPIS6_EN (0x1u << 22)
270#define SUPC_SR_WKUPIS7 (0x1u << 23)
271#define SUPC_SR_WKUPIS7_DIS (0x0u << 23)
272#define SUPC_SR_WKUPIS7_EN (0x1u << 23)
273#define SUPC_SR_WKUPIS8 (0x1u << 24)
274#define SUPC_SR_WKUPIS8_DIS (0x0u << 24)
275#define SUPC_SR_WKUPIS8_EN (0x1u << 24)
276#define SUPC_SR_WKUPIS9 (0x1u << 25)
277#define SUPC_SR_WKUPIS9_DIS (0x0u << 25)
278#define SUPC_SR_WKUPIS9_EN (0x1u << 25)
279#define SUPC_SR_WKUPIS10 (0x1u << 26)
280#define SUPC_SR_WKUPIS10_DIS (0x0u << 26)
281#define SUPC_SR_WKUPIS10_EN (0x1u << 26)
282#define SUPC_SR_WKUPIS11 (0x1u << 27)
283#define SUPC_SR_WKUPIS11_DIS (0x0u << 27)
284#define SUPC_SR_WKUPIS11_EN (0x1u << 27)
285#define SUPC_SR_WKUPIS12 (0x1u << 28)
286#define SUPC_SR_WKUPIS12_DIS (0x0u << 28)
287#define SUPC_SR_WKUPIS12_EN (0x1u << 28)
288#define SUPC_SR_WKUPIS13 (0x1u << 29)
289#define SUPC_SR_WKUPIS13_DIS (0x0u << 29)
290#define SUPC_SR_WKUPIS13_EN (0x1u << 29)
293
294
295#endif /* _SAME70_SUPC_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Supc
Supc hardware registers.
Definition: component_supc.h:41
Supc::SUPC_CR
__O uint32_t SUPC_CR
(Supc Offset: 0x00) Supply Controller Control Register
Definition: component_supc.h:42
Supc::SUPC_SMMR
__IO uint32_t SUPC_SMMR
(Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register
Definition: component_supc.h:43
Supc::SUPC_MR
__IO uint32_t SUPC_MR
(Supc Offset: 0x08) Supply Controller Mode Register
Definition: component_supc.h:44
Supc::SUPC_WUIR
__IO uint32_t SUPC_WUIR
(Supc Offset: 0x10) Supply Controller Wake-up Inputs Register
Definition: component_supc.h:46
Supc::SUPC_SR
__I uint32_t SUPC_SR
(Supc Offset: 0x14) Supply Controller Status Register
Definition: component_supc.h:47
Supc::SUPC_WUMR
__IO uint32_t SUPC_WUMR
(Supc Offset: 0x0C) Supply Controller Wake-up Mode Register
Definition: component_supc.h:45