RTEMS: I2C Support

| RTEMS 5.4-rc2

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Files | Functions
I2C Support
Board Support Packages » ARM » NXP LPC32XX

I2C Support. More...

## Files
file | i2c.c
| I2C support implementation.
file | i2c.h
| I2C support API.

## Functions
rtems_status_code | lpc32xx_i2c_init (volatile lpc32xx_i2c *i2c, unsigned clock_in_hz)
| Initializes the I2C module i2c.
void | lpc32xx_i2c_reset (volatile lpc32xx_i2c *i2c)
| Resets the I2C module i2c.
rtems_status_code | lpc32xx_i2c_clock (volatile lpc32xx_i2c *i2c, unsigned clock_in_hz)
| Sets the I2C module i2c clock.
rtems_status_code | lpc32xx_i2c_write_start (volatile lpc32xx_i2c *i2c, unsigned addr)
| Starts a write transaction on the I2C module i2c.
rtems_status_code | lpc32xx_i2c_write_with_optional_stop (volatile lpc32xx_i2c *i2c, const uint8_t *out, size_t n, bool stop)
| Writes data via the I2C module i2c with optional stop.
rtems_status_code | lpc32xx_i2c_read_start (volatile lpc32xx_i2c *i2c, unsigned addr)
| Starts a read transaction on the I2C module i2c.
rtems_status_code | lpc32xx_i2c_read_with_optional_stop (volatile lpc32xx_i2c *i2c, uint8_t *in, size_t n, bool stop)
| Reads data via the I2C module i2c with optional stop.
rtems_status_code | lpc32xx_i2c_write_and_read (volatile lpc32xx_i2c *i2c, unsigned addr, const uint8_t *out, size_t out_size, uint8_t *in, size_t in_size)
| Writes and reads data via the I2C module i2c.

## I2C Clock Control Register (I2CCLK_CTRL)
#define | I2CCLK_1_EN BSP_BIT32(0)
#define | I2CCLK_2_EN BSP_BIT32(1)
#define | I2CCLK_1_HIGH_DRIVE BSP_BIT32(2)
#define | I2CCLK_2_HIGH_DRIVE BSP_BIT32(3)
#define | I2CCLK_USB_HIGH_DRIVE BSP_BIT32(4)

## I2C TX Data FIFO Register (I2Cn_TX)
#define | I2C_TX_READ BSP_BIT32(0)
#define | I2C_TX_ADDR(val) BSP_FLD32(val, 1, 7)
#define | I2C_TX_START BSP_BIT32(8)
#define | I2C_TX_STOP BSP_BIT32(9)

## I2C Status Register (I2Cn_STAT)
#define | I2C_STAT_TDI BSP_BIT32(0)
#define | I2C_STAT_AFI BSP_BIT32(1)
#define | I2C_STAT_NAI BSP_BIT32(2)
#define | I2C_STAT_DRMI BSP_BIT32(3)
#define | I2C_STAT_DRSI BSP_BIT32(4)
#define | I2C_STAT_ACTIVE BSP_BIT32(5)
#define | I2C_STAT_SCL BSP_BIT32(6)
#define | I2C_STAT_SDA BSP_BIT32(7)
#define | I2C_STAT_RFF BSP_BIT32(8)
#define | I2C_STAT_RFE BSP_BIT32(9)
#define | I2C_STAT_TFF BSP_BIT32(10)
#define | I2C_STAT_TFE BSP_BIT32(11)
#define | I2C_STAT_TFFS BSP_BIT32(12)
#define | I2C_STAT_TFES BSP_BIT32(13)

## I2C Control Register (I2Cn_CTRL)
#define | I2C_CTRL_TDIE BSP_BIT32(0)
#define | I2C_CTRL_AFIE BSP_BIT32(1)
#define | I2C_CTRL_NAIE BSP_BIT32(2)
#define | I2C_CTRL_DRMIE BSP_BIT32(3)
#define | I2C_CTRL_DRSIE BSP_BIT32(4)
#define | I2C_CTRL_RFFIE BSP_BIT32(5)
#define | I2C_CTRL_RFDAIE BSP_BIT32(6)
#define | I2C_CTRL_TFFIO BSP_BIT32(7)
#define | I2C_CTRL_RESET BSP_BIT32(8)
#define | I2C_CTRL_SEVEN BSP_BIT32(9)
#define | I2C_CTRL_TFFSIE BSP_BIT32(10)

## Detailed Description

I2C Support.

All writes and reads will be performed in master mode. Exclusive bus access will be assumed.

## Function Documentation

## ◆ lpc32xx_i2c_clock()

rtems_status_code lpc32xx_i2c_clock | ( | volatile lpc32xx_i2c * | i2c,
|  | unsigned | clock_in_hz
| ) |  |

Sets the I2C module i2c clock.

Valid clock_in_hz values are 100000 and 400000.

Return values

  RTEMS_SUCCESSFUL | Successful operation.
  RTEMS_INVALID_CLOCK | Invalid clock_in_hz value.

## ◆ lpc32xx_i2c_init()

rtems_status_code lpc32xx_i2c_init | ( | volatile lpc32xx_i2c * | i2c,
|  | unsigned | clock_in_hz
| ) |  |

Initializes the I2C module i2c.

Valid clock_in_hz values are 100000 and 400000.

Return values

  RTEMS_SUCCESSFUL | Successful operation.
  RTEMS_INVALID_ID | Invalid i2c value.
  RTEMS_INVALID_CLOCK | Invalid clock_in_hz value.

## ◆ lpc32xx_i2c_read_start()

rtems_status_code lpc32xx_i2c_read_start | ( | volatile lpc32xx_i2c * | i2c,
|  | unsigned | addr
| ) |  |

Starts a read transaction on the I2C module i2c.

The address parameter addr must not contain the read/write bit.

The error status may be delayed to the next lpc32xx_i2c_read_with_optional_stop() due to controller flaws.

Return values

  RTEMS_SUCCESSFUL | Successful operation.
  RTEMS_IO_ERROR | Received a NACK from the slave.

## ◆ lpc32xx_i2c_read_with_optional_stop()

rtems_status_code lpc32xx_i2c_read_with_optional_stop | ( | volatile lpc32xx_i2c * | i2c,
|  | uint8_t * | in,
|  | size_t | n,
|  | bool | stop
| ) |  |

Reads data via the I2C module i2c with optional stop.

Return values

  RTEMS_SUCCESSFUL | Successful operation.
  RTEMS_IO_ERROR | Received a NACK from the slave.
  RTEMS_NOT_IMPLEMENTED | Stop is false.

## ◆ lpc32xx_i2c_write_and_read()

rtems_status_code lpc32xx_i2c_write_and_read | ( | volatile lpc32xx_i2c * | i2c,
|  | unsigned | addr,
|  | const uint8_t * | out,
|  | size_t | out_size,
|  | uint8_t * | in,
|  | size_t | in_size
| ) |  |

Writes and reads data via the I2C module i2c.

This will be one bus transaction.

Return values

  RTEMS_SUCCESSFUL | Successful operation.
  RTEMS_IO_ERROR | Received a NACK from the slave.

## ◆ lpc32xx_i2c_write_start()

rtems_status_code lpc32xx_i2c_write_start | ( | volatile lpc32xx_i2c * | i2c,
|  | unsigned | addr
| ) |  |

Starts a write transaction on the I2C module i2c.

The address parameter addr must not contain the read/write bit.

The error status may be delayed to the next lpc32xx_i2c_write_with_optional_stop() due to controller flaws.

Return values

  RTEMS_SUCCESSFUL | Successful operation.
  RTEMS_IO_ERROR | Received a NACK from the slave.

## ◆ lpc32xx_i2c_write_with_optional_stop()

rtems_status_code lpc32xx_i2c_write_with_optional_stop | ( | volatile lpc32xx_i2c * | i2c,
|  | const uint8_t * | out,
|  | size_t | n,
|  | bool | stop
| ) |  |

Writes data via the I2C module i2c with optional stop.

The error status may be delayed to the next lpc32xx_i2c_write_with_optional_stop() due to controller flaws.

Return values

  RTEMS_SUCCESSFUL | Successful operation.
  RTEMS_IO_ERROR | Received a NACK from the slave.