RTEMS: bsps/arm/include/core_cm7.h File Reference

| RTEMS 5.4-rc2

Loading...
Searching...
No Matches
Data Structures | Macros
core_cm7.h File Reference

CMSIS Cortex-M7 Core Peripheral Access Layer Header File. More...

`#include <stdint.h>`
`#include "core_cmInstr.h"`
`#include "core_cmFunc.h"`
`#include "core_cmSimd.h"`

Go to the source code of this file.

## Data Structures
union | APSR_Type
| Union type to access the Application Program Status Register (APSR). More...
union | IPSR_Type
| Union type to access the Interrupt Program Status Register (IPSR). More...
union | xPSR_Type
| Union type to access the Special-Purpose Program Status Registers (xPSR). More...
union | CONTROL_Type
| Union type to access the Control Registers (CONTROL). More...
struct | NVIC_Type
| Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...
struct | SCB_Type
| Structure type to access the System Control Block (SCB). More...
struct | SCnSCB_Type
| Structure type to access the System Control and ID Register not in the SCB. More...
struct | SysTick_Type
| Structure type to access the System Timer (SysTick). More...
struct | ITM_Type
| Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
struct | DWT_Type
| Structure type to access the Data Watchpoint and Trace Register (DWT). More...
struct | TPI_Type
| Structure type to access the Trace Port Interface Register (TPI). More...
struct | CoreDebug_Type
| Structure type to access the Core Debug Register (CoreDebug). More...
#define | __CM7_CMSIS_VERSION_MAIN (0x04U)
#define | __CM7_CMSIS_VERSION_SUB (0x1EU)
#define | __CM7_CMSIS_VERSION
#define | __CORTEX_M (0x07U)
#define | __CORE_CM7_H_DEPENDANT
#define | __I volatile const
#define | __O volatile
#define | __IO volatile
#define | __IM volatile const /*! Defines 'read only' structure member permissions */
#define | __OM volatile /*! Defines 'write only' structure member permissions */
#define | __IOM volatile /*! Defines 'read / write' structure member permissions */
#define | APSR_N_Pos 31U
#define | APSR_N_Msk (1UL << APSR_N_Pos)
#define | APSR_Z_Pos 30U
#define | APSR_Z_Msk (1UL << APSR_Z_Pos)
#define | APSR_C_Pos 29U
#define | APSR_C_Msk (1UL << APSR_C_Pos)
#define | APSR_V_Pos 28U
#define | APSR_V_Msk (1UL << APSR_V_Pos)
#define | APSR_Q_Pos 27U
#define | APSR_Q_Msk (1UL << APSR_Q_Pos)
#define | APSR_GE_Pos 16U
#define | APSR_GE_Msk (0xFUL << APSR_GE_Pos)
#define | IPSR_ISR_Pos 0U
#define | IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
#define | xPSR_N_Pos 31U
#define | xPSR_N_Msk (1UL << xPSR_N_Pos)
#define | xPSR_Z_Pos 30U
#define | xPSR_Z_Msk (1UL << xPSR_Z_Pos)
#define | xPSR_C_Pos 29U
#define | xPSR_C_Msk (1UL << xPSR_C_Pos)
#define | xPSR_V_Pos 28U
#define | xPSR_V_Msk (1UL << xPSR_V_Pos)
#define | xPSR_Q_Pos 27U
#define | xPSR_Q_Msk (1UL << xPSR_Q_Pos)
#define | xPSR_IT_Pos 25U
#define | xPSR_IT_Msk (3UL << xPSR_IT_Pos)
#define | xPSR_T_Pos 24U
#define | xPSR_T_Msk (1UL << xPSR_T_Pos)
#define | xPSR_GE_Pos 16U
#define | xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
#define | xPSR_ISR_Pos 0U
#define | xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
#define | CONTROL_FPCA_Pos 2U
#define | CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
#define | CONTROL_SPSEL_Pos 1U
#define | CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
#define | CONTROL_nPRIV_Pos 0U
#define | CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
#define | NVIC_STIR_INTID_Pos 0U
#define | NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
#define | SCB_CPUID_IMPLEMENTER_Pos 24U
#define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
#define | SCB_CPUID_VARIANT_Pos 20U
#define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
#define | SCB_CPUID_ARCHITECTURE_Pos 16U
#define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
#define | SCB_CPUID_PARTNO_Pos 4U
#define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
#define | SCB_CPUID_REVISION_Pos 0U
#define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
#define | SCB_ICSR_NMIPENDSET_Pos 31U
#define | SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
#define | SCB_ICSR_PENDSVSET_Pos 28U
#define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
#define | SCB_ICSR_PENDSVCLR_Pos 27U
#define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
#define | SCB_ICSR_PENDSTSET_Pos 26U
#define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
#define | SCB_ICSR_PENDSTCLR_Pos 25U
#define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
#define | SCB_ICSR_ISRPREEMPT_Pos 23U
#define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
#define | SCB_ICSR_ISRPENDING_Pos 22U
#define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
#define | SCB_ICSR_VECTPENDING_Pos 12U
#define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
#define | SCB_ICSR_RETTOBASE_Pos 11U
#define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
#define | SCB_ICSR_VECTACTIVE_Pos 0U
#define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
#define | SCB_VTOR_TBLOFF_Pos 7U
#define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
#define | SCB_AIRCR_VECTKEY_Pos 16U
#define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
#define | SCB_AIRCR_VECTKEYSTAT_Pos 16U
#define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
#define | SCB_AIRCR_ENDIANESS_Pos 15U
#define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
#define | SCB_AIRCR_PRIGROUP_Pos 8U
#define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
#define | SCB_AIRCR_SYSRESETREQ_Pos 2U
#define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
#define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U
#define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
#define | SCB_AIRCR_VECTRESET_Pos 0U
#define | SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
#define | SCB_SCR_SEVONPEND_Pos 4U
#define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
#define | SCB_SCR_SLEEPDEEP_Pos 2U
#define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
#define | SCB_SCR_SLEEPONEXIT_Pos 1U
#define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
#define | SCB_CCR_BP_Pos 18U
#define | SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
#define | SCB_CCR_IC_Pos 17U
#define | SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
#define | SCB_CCR_DC_Pos 16U
#define | SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
#define | SCB_CCR_STKALIGN_Pos 9U
#define | SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
#define | SCB_CCR_BFHFNMIGN_Pos 8U
#define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
#define | SCB_CCR_DIV_0_TRP_Pos 4U
#define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
#define | SCB_CCR_UNALIGN_TRP_Pos 3U
#define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
#define | SCB_CCR_USERSETMPEND_Pos 1U
#define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
#define | SCB_CCR_NONBASETHRDENA_Pos 0U
#define | SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
#define | SCB_SHCSR_USGFAULTENA_Pos 18U
#define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
#define | SCB_SHCSR_BUSFAULTENA_Pos 17U
#define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
#define | SCB_SHCSR_MEMFAULTENA_Pos 16U
#define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
#define | SCB_SHCSR_SVCALLPENDED_Pos 15U
#define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
#define | SCB_SHCSR_BUSFAULTPENDED_Pos 14U
#define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
#define | SCB_SHCSR_MEMFAULTPENDED_Pos 13U
#define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
#define | SCB_SHCSR_USGFAULTPENDED_Pos 12U
#define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
#define | SCB_SHCSR_SYSTICKACT_Pos 11U
#define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
#define | SCB_SHCSR_PENDSVACT_Pos 10U
#define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
#define | SCB_SHCSR_MONITORACT_Pos 8U
#define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
#define | SCB_SHCSR_SVCALLACT_Pos 7U
#define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
#define | SCB_SHCSR_USGFAULTACT_Pos 3U
#define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
#define | SCB_SHCSR_BUSFAULTACT_Pos 1U
#define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
#define | SCB_SHCSR_MEMFAULTACT_Pos 0U
#define | SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
#define | SCB_CFSR_USGFAULTSR_Pos 16U
#define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
#define | SCB_CFSR_BUSFAULTSR_Pos 8U
#define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
#define | SCB_CFSR_MEMFAULTSR_Pos 0U
#define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
#define | SCB_HFSR_DEBUGEVT_Pos 31U
#define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
#define | SCB_HFSR_FORCED_Pos 30U
#define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
#define | SCB_HFSR_VECTTBL_Pos 1U
#define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
#define | SCB_DFSR_EXTERNAL_Pos 4U
#define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
#define | SCB_DFSR_VCATCH_Pos 3U
#define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
#define | SCB_DFSR_DWTTRAP_Pos 2U
#define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
#define | SCB_DFSR_BKPT_Pos 1U
#define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
#define | SCB_DFSR_HALTED_Pos 0U
#define | SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
#define | SCB_CLIDR_LOUU_Pos 27U
#define | SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
#define | SCB_CLIDR_LOC_Pos 24U
#define | SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
#define | SCB_CTR_FORMAT_Pos 29U
#define | SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
#define | SCB_CTR_CWG_Pos 24U
#define | SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
#define | SCB_CTR_ERG_Pos 20U
#define | SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
#define | SCB_CTR_DMINLINE_Pos 16U
#define | SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
#define | SCB_CTR_IMINLINE_Pos 0U
#define | SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
#define | SCB_CCSIDR_WT_Pos 31U
#define | SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
#define | SCB_CCSIDR_WB_Pos 30U
#define | SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
#define | SCB_CCSIDR_RA_Pos 29U
#define | SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
#define | SCB_CCSIDR_WA_Pos 28U
#define | SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
#define | SCB_CCSIDR_NUMSETS_Pos 13U
#define | SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
#define | SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
#define | SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define | SCB_CCSIDR_LINESIZE_Pos 0U
#define | SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
#define | SCB_CSSELR_LEVEL_Pos 1U
#define | SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
#define | SCB_CSSELR_IND_Pos 0U
#define | SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
#define | SCB_STIR_INTID_Pos 0U
#define | SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
#define | SCB_DCISW_WAY_Pos 30U
#define | SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
#define | SCB_DCISW_SET_Pos 5U
#define | SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
#define | SCB_DCCSW_WAY_Pos 30U
#define | SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
#define | SCB_DCCSW_SET_Pos 5U
#define | SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
#define | SCB_DCCISW_WAY_Pos 30U
#define | SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
#define | SCB_DCCISW_SET_Pos 5U
#define | SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
#define | SCB_ITCMCR_SZ_Pos 3U
#define | SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)
#define | SCB_ITCMCR_RETEN_Pos 2U
#define | SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)
#define | SCB_ITCMCR_RMW_Pos 1U
#define | SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)
#define | SCB_ITCMCR_EN_Pos 0U
#define | SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)
#define | SCB_DTCMCR_SZ_Pos 3U
#define | SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)
#define | SCB_DTCMCR_RETEN_Pos 2U
#define | SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)
#define | SCB_DTCMCR_RMW_Pos 1U
#define | SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)
#define | SCB_DTCMCR_EN_Pos 0U
#define | SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)
#define | SCB_AHBPCR_SZ_Pos 1U
#define | SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)
#define | SCB_AHBPCR_EN_Pos 0U
#define | SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)
#define | SCB_CACR_FORCEWT_Pos 2U
#define | SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)
#define | SCB_CACR_ECCEN_Pos 1U
#define | SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)
#define | SCB_CACR_SIWT_Pos 0U
#define | SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)
#define | SCB_AHBSCR_INITCOUNT_Pos 11U
#define | SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
#define | SCB_AHBSCR_TPRI_Pos 2U
#define | SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
#define | SCB_AHBSCR_CTL_Pos 0U
#define | SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
#define | SCB_ABFSR_AXIMTYPE_Pos 8U
#define | SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)
#define | SCB_ABFSR_EPPB_Pos 4U
#define | SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)
#define | SCB_ABFSR_AXIM_Pos 3U
#define | SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)
#define | SCB_ABFSR_AHBP_Pos 2U
#define | SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)
#define | SCB_ABFSR_DTCM_Pos 1U
#define | SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)
#define | SCB_ABFSR_ITCM_Pos 0U
#define | SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
#define | SCnSCB_ICTR_INTLINESNUM_Pos 0U
#define | SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
#define | SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U
#define | SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)
#define | SCnSCB_ACTLR_DISRAMODE_Pos 11U
#define | SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)
#define | SCnSCB_ACTLR_FPEXCODIS_Pos 10U
#define | SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)
#define | SCnSCB_ACTLR_DISFOLD_Pos 2U
#define | SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
#define | SCnSCB_ACTLR_DISMCYCINT_Pos 0U
#define | SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
#define | SysTick_CTRL_COUNTFLAG_Pos 16U
#define | SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
#define | SysTick_CTRL_CLKSOURCE_Pos 2U
#define | SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
#define | SysTick_CTRL_TICKINT_Pos 1U
#define | SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
#define | SysTick_CTRL_ENABLE_Pos 0U
#define | SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
#define | SysTick_LOAD_RELOAD_Pos 0U
#define | SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
#define | SysTick_VAL_CURRENT_Pos 0U
#define | SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
#define | SysTick_CALIB_NOREF_Pos 31U
#define | SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
#define | SysTick_CALIB_SKEW_Pos 30U
#define | SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
#define | SysTick_CALIB_TENMS_Pos 0U
#define | SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
#define | ITM_TPR_PRIVMASK_Pos 0U
#define | ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
#define | ITM_TCR_BUSY_Pos 23U
#define | ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
#define | ITM_TCR_TraceBusID_Pos 16U
#define | ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
#define | ITM_TCR_GTSFREQ_Pos 10U
#define | ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
#define | ITM_TCR_TSPrescale_Pos 8U
#define | ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
#define | ITM_TCR_SWOENA_Pos 4U
#define | ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
#define | ITM_TCR_DWTENA_Pos 3U
#define | ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
#define | ITM_TCR_SYNCENA_Pos 2U
#define | ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
#define | ITM_TCR_TSENA_Pos 1U
#define | ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
#define | ITM_TCR_ITMENA_Pos 0U
#define | ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
#define | ITM_IWR_ATVALIDM_Pos 0U
#define | ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
#define | ITM_IRR_ATREADYM_Pos 0U
#define | ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
#define | ITM_IMCR_INTEGRATION_Pos 0U
#define | ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
#define | ITM_LSR_ByteAcc_Pos 2U
#define | ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
#define | ITM_LSR_Access_Pos 1U
#define | ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
#define | ITM_LSR_Present_Pos 0U
#define | ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
#define | DWT_CTRL_NUMCOMP_Pos 28U
#define | DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
#define | DWT_CTRL_NOTRCPKT_Pos 27U
#define | DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
#define | DWT_CTRL_NOEXTTRIG_Pos 26U
#define | DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
#define | DWT_CTRL_NOCYCCNT_Pos 25U
#define | DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
#define | DWT_CTRL_NOPRFCNT_Pos 24U
#define | DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
#define | DWT_CTRL_CYCEVTENA_Pos 22U
#define | DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
#define | DWT_CTRL_FOLDEVTENA_Pos 21U
#define | DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
#define | DWT_CTRL_LSUEVTENA_Pos 20U
#define | DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
#define | DWT_CTRL_SLEEPEVTENA_Pos 19U
#define | DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
#define | DWT_CTRL_EXCEVTENA_Pos 18U
#define | DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
#define | DWT_CTRL_CPIEVTENA_Pos 17U
#define | DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
#define | DWT_CTRL_EXCTRCENA_Pos 16U
#define | DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
#define | DWT_CTRL_PCSAMPLENA_Pos 12U
#define | DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
#define | DWT_CTRL_SYNCTAP_Pos 10U
#define | DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
#define | DWT_CTRL_CYCTAP_Pos 9U
#define | DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
#define | DWT_CTRL_POSTINIT_Pos 5U
#define | DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
#define | DWT_CTRL_POSTPRESET_Pos 1U
#define | DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
#define | DWT_CTRL_CYCCNTENA_Pos 0U
#define | DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
#define | DWT_CPICNT_CPICNT_Pos 0U
#define | DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
#define | DWT_EXCCNT_EXCCNT_Pos 0U
#define | DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
#define | DWT_SLEEPCNT_SLEEPCNT_Pos 0U
#define | DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
#define | DWT_LSUCNT_LSUCNT_Pos 0U
#define | DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
#define | DWT_FOLDCNT_FOLDCNT_Pos 0U
#define | DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
#define | DWT_MASK_MASK_Pos 0U
#define | DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
#define | DWT_FUNCTION_MATCHED_Pos 24U
#define | DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
#define | DWT_FUNCTION_DATAVADDR1_Pos 16U
#define | DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
#define | DWT_FUNCTION_DATAVADDR0_Pos 12U
#define | DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
#define | DWT_FUNCTION_DATAVSIZE_Pos 10U
#define | DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
#define | DWT_FUNCTION_LNK1ENA_Pos 9U
#define | DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
#define | DWT_FUNCTION_DATAVMATCH_Pos 8U
#define | DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
#define | DWT_FUNCTION_CYCMATCH_Pos 7U
#define | DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
#define | DWT_FUNCTION_EMITRANGE_Pos 5U
#define | DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
#define | DWT_FUNCTION_FUNCTION_Pos 0U
#define | DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
#define | TPI_ACPR_PRESCALER_Pos 0U
#define | TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
#define | TPI_SPPR_TXMODE_Pos 0U
#define | TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define | TPI_FFSR_FtNonStop_Pos 3U
#define | TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define | TPI_FFSR_TCPresent_Pos 2U
#define | TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
#define | TPI_FFSR_FtStopped_Pos 1U
#define | TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
#define | TPI_FFSR_FlInProg_Pos 0U
#define | TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define | TPI_FFCR_TrigIn_Pos 8U
#define | TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
#define | TPI_FFCR_EnFCont_Pos 1U
#define | TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
#define | TPI_TRIGGER_TRIGGER_Pos 0U
#define | TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
#define | TPI_FIFO0_ITM_ATVALID_Pos 29U
#define | TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
#define | TPI_FIFO0_ITM_bytecount_Pos 27U
#define | TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
#define | TPI_FIFO0_ETM_ATVALID_Pos 26U
#define | TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
#define | TPI_FIFO0_ETM_bytecount_Pos 24U
#define | TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
#define | TPI_FIFO0_ETM2_Pos 16U
#define | TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
#define | TPI_FIFO0_ETM1_Pos 8U
#define | TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
#define | TPI_FIFO0_ETM0_Pos 0U
#define | TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
#define | TPI_ITATBCTR2_ATREADY_Pos 0U
#define | TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)
#define | TPI_FIFO1_ITM_ATVALID_Pos 29U
#define | TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
#define | TPI_FIFO1_ITM_bytecount_Pos 27U
#define | TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
#define | TPI_FIFO1_ETM_ATVALID_Pos 26U
#define | TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
#define | TPI_FIFO1_ETM_bytecount_Pos 24U
#define | TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
#define | TPI_FIFO1_ITM2_Pos 16U
#define | TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
#define | TPI_FIFO1_ITM1_Pos 8U
#define | TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
#define | TPI_FIFO1_ITM0_Pos 0U
#define | TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
#define | TPI_ITATBCTR0_ATREADY_Pos 0U
#define | TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)
#define | TPI_ITCTRL_Mode_Pos 0U
#define | TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)
#define | TPI_DEVID_NRZVALID_Pos 11U
#define | TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define | TPI_DEVID_MANCVALID_Pos 10U
#define | TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define | TPI_DEVID_PTINVALID_Pos 9U
#define | TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define | TPI_DEVID_MinBufSz_Pos 6U
#define | TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
#define | TPI_DEVID_AsynClkIn_Pos 5U
#define | TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
#define | TPI_DEVID_NrTraceInput_Pos 0U
#define | TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
#define | TPI_DEVTYPE_MajorType_Pos 4U
#define | TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define | TPI_DEVTYPE_SubType_Pos 0U
#define | TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define | CoreDebug_DHCSR_DBGKEY_Pos 16U
#define | CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
#define | CoreDebug_DHCSR_S_RESET_ST_Pos 25U
#define | CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
#define | CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
#define | CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
#define | CoreDebug_DHCSR_S_LOCKUP_Pos 19U
#define | CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
#define | CoreDebug_DHCSR_S_SLEEP_Pos 18U
#define | CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
#define | CoreDebug_DHCSR_S_HALT_Pos 17U
#define | CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
#define | CoreDebug_DHCSR_S_REGRDY_Pos 16U
#define | CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
#define | CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
#define | CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
#define | CoreDebug_DHCSR_C_MASKINTS_Pos 3U
#define | CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
#define | CoreDebug_DHCSR_C_STEP_Pos 2U
#define | CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
#define | CoreDebug_DHCSR_C_HALT_Pos 1U
#define | CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
#define | CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
#define | CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
#define | CoreDebug_DCRSR_REGWnR_Pos 16U
#define | CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
#define | CoreDebug_DCRSR_REGSEL_Pos 0U
#define | CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
#define | CoreDebug_DEMCR_TRCENA_Pos 24U
#define | CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
#define | CoreDebug_DEMCR_MON_REQ_Pos 19U
#define | CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
#define | CoreDebug_DEMCR_MON_STEP_Pos 18U
#define | CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
#define | CoreDebug_DEMCR_MON_PEND_Pos 17U
#define | CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
#define | CoreDebug_DEMCR_MON_EN_Pos 16U
#define | CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
#define | CoreDebug_DEMCR_VC_HARDERR_Pos 10U
#define | CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
#define | CoreDebug_DEMCR_VC_INTERR_Pos 9U
#define | CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
#define | CoreDebug_DEMCR_VC_BUSERR_Pos 8U
#define | CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
#define | CoreDebug_DEMCR_VC_STATERR_Pos 7U
#define | CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
#define | CoreDebug_DEMCR_VC_CHKERR_Pos 6U
#define | CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
#define | CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
#define | CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
#define | CoreDebug_DEMCR_VC_MMERR_Pos 4U
#define | CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
#define | CoreDebug_DEMCR_VC_CORERESET_Pos 0U
#define | CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
#define | _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
| Mask and shift a bit field value for use in a register bit range.
#define | _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
| Mask and shift a register value to extract a bit filed value.
#define | SCS_BASE (0xE000E000UL)
#define | ITM_BASE (0xE0000000UL)
#define | DWT_BASE (0xE0001000UL)
#define | TPI_BASE (0xE0040000UL)
#define | CoreDebug_BASE (0xE000EDF0UL)
#define | SysTick_BASE (SCS_BASE + 0x0010UL)
#define | NVIC_BASE (SCS_BASE + 0x0100UL)
#define | SCB_BASE (SCS_BASE + 0x0D00UL)
#define | SCnSCB ((SCnSCB_Type *) SCS_BASE )
#define | SCB ((SCB_Type *) SCB_BASE )
#define | SysTick ((SysTick_Type *) SysTick_BASE )
#define | NVIC ((NVIC_Type *) NVIC_BASE )
#define | ITM ((ITM_Type *) ITM_BASE )
#define | DWT ((DWT_Type *) DWT_BASE )
#define | TPI ((TPI_Type *) TPI_BASE )
#define | CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
#define | CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define | CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
#define | ITM_RXBUFFER_EMPTY 0x5AA55AA5U
volatile int32_t | ITM_RxBuffer
__STATIC_INLINE void | NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
| Set Priority Grouping.
__STATIC_INLINE uint32_t | NVIC_GetPriorityGrouping (void)
| Get Priority Grouping.
__STATIC_INLINE void | NVIC_EnableIRQ (IRQn_Type IRQn)
| Enable External Interrupt.
__STATIC_INLINE void | NVIC_DisableIRQ (IRQn_Type IRQn)
| Disable External Interrupt.
__STATIC_INLINE uint32_t | NVIC_GetPendingIRQ (IRQn_Type IRQn)
| Get Pending Interrupt.
__STATIC_INLINE void | NVIC_SetPendingIRQ (IRQn_Type IRQn)
| Set Pending Interrupt.
__STATIC_INLINE void | NVIC_ClearPendingIRQ (IRQn_Type IRQn)
| Clear Pending Interrupt.
__STATIC_INLINE uint32_t | NVIC_GetActive (IRQn_Type IRQn)
| Get Active Interrupt.
__STATIC_INLINE void | NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
| Set Interrupt Priority.
__STATIC_INLINE uint32_t | NVIC_GetPriority (IRQn_Type IRQn)
| Get Interrupt Priority.
__STATIC_INLINE uint32_t | NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
| Encode Priority.
__STATIC_INLINE void | NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
| Decode Priority.
__STATIC_INLINE void | NVIC_SystemReset (void)
| System Reset.
__STATIC_INLINE uint32_t | SCB_GetFPUType (void)
| get FPU type
__STATIC_INLINE void | SCB_EnableICache (void)
| Enable I-Cache.
__STATIC_INLINE void | SCB_DisableICache (void)
| Disable I-Cache.
__STATIC_INLINE void | SCB_InvalidateICache (void)
| Invalidate I-Cache.
__STATIC_INLINE void | SCB_EnableDCache (void)
| Enable D-Cache.
__STATIC_INLINE void | SCB_DisableDCache (void)
| Disable D-Cache.
__STATIC_INLINE void | SCB_InvalidateDCache (void)
| Invalidate D-Cache.
__STATIC_INLINE void | SCB_CleanDCache (void)
| Clean D-Cache.
__STATIC_INLINE void | SCB_CleanInvalidateDCache (void)
| Clean & Invalidate D-Cache.
__STATIC_INLINE void | SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
| D-Cache Invalidate by address.
__STATIC_INLINE void | SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
| D-Cache Clean by address.
__STATIC_INLINE void | SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
| D-Cache Clean and Invalidate by address.
__STATIC_INLINE uint32_t | SysTick_Config (uint32_t ticks)
| System Tick Configuration.
__STATIC_INLINE uint32_t | ITM_SendChar (uint32_t ch)
| ITM Send Character.
__STATIC_INLINE int32_t | ITM_ReceiveChar (void)
| ITM Receive Character.
__STATIC_INLINE int32_t | ITM_CheckChar (void)
| ITM Check Character.

## Detailed Description

CMSIS Cortex-M7 Core Peripheral Access Layer Header File.

Version
  V4.30

Date
  20. October 2015

## Macro Definition Documentation

## ◆ __CM7_CMSIS_VERSION

#define __CM7_CMSIS_VERSION

Value:
((__CM7_CMSIS_VERSION_MAIN << 16U) | \
__CM7_CMSIS_VERSION_SUB )
__CM7_CMSIS_VERSION_MAIN
#define __CM7_CMSIS_VERSION_MAIN
Definition: core_cm7.h:74
__CM7_CMSIS_VERSION_SUB
#define __CM7_CMSIS_VERSION_SUB
Definition: core_cm7.h:75

CMSIS HAL version number

## ◆ __CM7_CMSIS_VERSION_MAIN

#define __CM7_CMSIS_VERSION_MAIN (0x04U)

[31:16] CMSIS HAL main version

## ◆ __CM7_CMSIS_VERSION_SUB

#define __CM7_CMSIS_VERSION_SUB (0x1EU)

[15:0] CMSIS HAL sub version

## ◆ __CORE_CM7_H_DEPENDANT

#define __CORE_CM7_H_DEPENDANT

__FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.

## ◆ __CORTEX_M

#define __CORTEX_M (0x07U)

Cortex-M Core

## ◆ __I

#define __I volatile const

Defines 'read only' permissions

## ◆ __IO

#define __IO volatile

Defines 'read / write' permissions

## ◆ __O

#define __O volatile

Defines 'write only' permissions