RTEMS: bsps/powerpc/haleakala/include/bsp/irq.h Source File

| RTEMS 5.4-rc2

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irq.h
1/*===============================================================*\
2| Project: RTEMS Haleakala BSP |
3| by Michael Hamel ADInstruments Ltd 2008 |
4+-----------------------------------------------------------------+
5| The license and distribution terms for this file may be |
6| found in the file LICENSE in this distribution or at |
7| |
8| http://www.rtems.org/license/LICENSE. |
9| |
10\*===============================================================*/
11
12
13#ifndef Haleakala_IRQ_IRQ_H
14#define Haleakala_IRQ_IRQ_H
15
16/* Implemented for us in bsp_irq_dispatch_list */
17#define BSP_SHARED_HANDLER_SUPPORT 1
18
19#include <rtems/irq.h>
20
21#ifndef ASM
22
23#include <bsp/irq-default.h>
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29 /* Define UIC interrupt numbers; IRQs that cause an external interrupt that needs further decode.
30 These are arbitrary but it makes things easier if they match the CPU interrupt numbers */
31
32 /*
33
34 #define BSP_UIC_UART0_GP (BSP_UIC_IRQ_LOWEST_OFFSET + 0)
35 #define BSP_UIC_UART1 (BSP_UIC_IRQ_LOWEST_OFFSET + 1)
36 #define BSP_UIC_IIC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 2)
37 #define BSP_UIC_ExtMaster (BSP_UIC_IRQ_LOWEST_OFFSET + 3)
38 #define BSP_UIC_PCI (BSP_UIC_IRQ_LOWEST_OFFSET + 4)
39 #define BSP_UIC_DMA0 (BSP_UIC_IRQ_LOWEST_OFFSET + 5)
40 #define BSP_UIC_DMA1 (BSP_UIC_IRQ_LOWEST_OFFSET + 6)
41 #define BSP_UIC_DMA2 (BSP_UIC_IRQ_LOWEST_OFFSET + 7)
42 #define BSP_UIC_DMA3 (BSP_UIC_IRQ_LOWEST_OFFSET + 8)
43 #define BSP_UIC_ENetWU (BSP_UIC_IRQ_LOWEST_OFFSET + 9)
44 #define BSP_UIC_MALSERR (BSP_UIC_IRQ_LOWEST_OFFSET + 10)
45 #define BSP_UIC_MALTXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 11)
46 #define BSP_UIC_MALRXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 12)
47 #define BSP_UIC_MALTXDE (BSP_UIC_IRQ_LOWEST_OFFSET + 13)
48 #define BSP_UIC_MALRXDE (BSP_UIC_IRQ_LOWEST_OFFSET + 14)
49 #define BSP_UIC_ENet (BSP_UIC_IRQ_LOWEST_OFFSET + 15)
50 #define BSP_UIC_PCISERR (BSP_UIC_IRQ_LOWEST_OFFSET + 16)
51 #define BSP_UIC_ECCERR (BSP_UIC_IRQ_LOWEST_OFFSET + 17)
52 #define BSP_UIC_PCIPower (BSP_UIC_IRQ_LOWEST_OFFSET + 18)
53 #define BSP_UIC_IRQ0 (BSP_UIC_IRQ_LOWEST_OFFSET + 25)
54 #define BSP_UIC_IRQ1 (BSP_UIC_IRQ_LOWEST_OFFSET + 26)
55 #define BSP_UIC_IRQ2 (BSP_UIC_IRQ_LOWEST_OFFSET + 27)
56 #define BSP_UIC_IRQ3 (BSP_UIC_IRQ_LOWEST_OFFSET + 28)
57 #define BSP_UIC_IRQ4 (BSP_UIC_IRQ_LOWEST_OFFSET + 29)
58 #define BSP_UIC_IRQ5 (BSP_UIC_IRQ_LOWEST_OFFSET + 30)
59 #define BSP_UIC_IRQ6 (BSP_UIC_IRQ_LOWEST_OFFSET + 31)
60
61 #define BSP_UIC_IRQ_NUMBER (32)
62
63 */
64 /* PPC405EX interrupt vectors */
65 #define BSP_UIC_UART1 (BSP_UIC_IRQ_LOWEST_OFFSET + 1)
66 #define BSP_UIC_IIC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 2)
67 #define BSP_UIC_EIPPKP_READY (BSP_UIC_IRQ_LOWEST_OFFSET + 3)
68 #define BSP_UIC_EIPPKP_TRNG (BSP_UIC_IRQ_LOWEST_OFFSET + 4)
69 #define BSP_UIC_EBM (BSP_UIC_IRQ_LOWEST_OFFSET + 5)
70 #define BSP_UIC_OPBtoPLB (BSP_UIC_IRQ_LOWEST_OFFSET + 6)
71 #define BSP_UIC_IIC1 (BSP_UIC_IRQ_LOWEST_OFFSET + 7)
72 #define BSP_UIC_SPI (BSP_UIC_IRQ_LOWEST_OFFSET + 8)
73 #define BSP_UIC_IRQ0 (BSP_UIC_IRQ_LOWEST_OFFSET + 9)
74 #define BSP_UIC_MALTXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 10)
75 #define BSP_UIC_MALRXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 11)
76 #define BSP_UIC_DMA0 (BSP_UIC_IRQ_LOWEST_OFFSET + 12)
77 #define BSP_UIC_DMA1 (BSP_UIC_IRQ_LOWEST_OFFSET + 13)
78 #define BSP_UIC_DMA2 (BSP_UIC_IRQ_LOWEST_OFFSET + 14)
79 #define BSP_UIC_DMA3 (BSP_UIC_IRQ_LOWEST_OFFSET + 15)
80 #define BSP_UIC_PCIe0AL (BSP_UIC_IRQ_LOWEST_OFFSET + 16)
81 #define BSP_UIC_PCIe0VPD (BSP_UIC_IRQ_LOWEST_OFFSET + 17)
82 #define BSP_UIC_PCIe0HRst (BSP_UIC_IRQ_LOWEST_OFFSET + 18)
83 #define BSP_UIC_EIPPKP_PKA (BSP_UIC_IRQ_LOWEST_OFFSET + 19)
84 #define BSP_UIC_PCIe0TCR (BSP_UIC_IRQ_LOWEST_OFFSET + 20)
85 #define BSP_UIC_PCIe0VCO (BSP_UIC_IRQ_LOWEST_OFFSET + 21)
86 #define BSP_UIC_EIPPKP_TRNG_AL (BSP_UIC_IRQ_LOWEST_OFFSET + 22)
87 #define BSP_UIC_EIP94 (BSP_UIC_IRQ_LOWEST_OFFSET + 23)
88 #define BSP_UIC_EMAC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 24)
89 #define BSP_UIC_EMAC1 (BSP_UIC_IRQ_LOWEST_OFFSET + 25)
90 #define BSP_UIC_UART0 (BSP_UIC_IRQ_LOWEST_OFFSET + 26)
91 #define BSP_UIC_IRQ4 (BSP_UIC_IRQ_LOWEST_OFFSET + 27)
92 #define BSP_UIC_UIC2_STD (BSP_UIC_IRQ_LOWEST_OFFSET + 28)
93 #define BSP_UIC_UIC2_CRIT (BSP_UIC_IRQ_LOWEST_OFFSET + 29)
94 #define BSP_UIC_UIC1_STD (BSP_UIC_IRQ_LOWEST_OFFSET + 30)
95 #define BSP_UIC_UIC1_CRIT (BSP_UIC_IRQ_LOWEST_OFFSET + 31)
96
97 #define BSP_UIC1_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + 32)
98 #define BSP_UIC_MALSERR (BSP_UIC1_IRQ_LOWEST_OFFSET + 0)
99 #define BSP_UIC_MALTXDE (BSP_UIC1_IRQ_LOWEST_OFFSET + 1)
100 #define BSP_UIC_MALRXDE (BSP_UIC1_IRQ_LOWEST_OFFSET + 2)
101 #define BSP_UIC_PCIe0DCRErr (BSP_UIC1_IRQ_LOWEST_OFFSET + 3)
102 #define BSP_UIC_PCIe1DCRErr (BSP_UIC1_IRQ_LOWEST_OFFSET + 4)
103 #define BSP_UIC_ExtBus (BSP_UIC1_IRQ_LOWEST_OFFSET + 5)
104 #define BSP_UIC_NDFC (BSP_UIC1_IRQ_LOWEST_OFFSET + 6)
105 #define BSP_UIC_EIPKP_SLAVE (BSP_UIC1_IRQ_LOWEST_OFFSET + 7)
106 #define BSP_UIC_GPT_TIMER5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 8)
107 #define BSP_UIC_GPT_TIMER6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 9)
108
109 #define BSP_UIC_GPT_TIMER0 (BSP_UIC1_IRQ_LOWEST_OFFSET + 16)
110 #define BSP_UIC_GPT_TIMER1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 17)
111 #define BSP_UIC_IRQ7 (BSP_UIC1_IRQ_LOWEST_OFFSET + 18)
112 #define BSP_UIC_IRQ8 (BSP_UIC1_IRQ_LOWEST_OFFSET + 19)
113 #define BSP_UIC_IRQ9 (BSP_UIC1_IRQ_LOWEST_OFFSET + 20)
114 #define BSP_UIC_GPT_TIMER2 (BSP_UIC1_IRQ_LOWEST_OFFSET + 21)
115 #define BSP_UIC_GPT_TIMER3 (BSP_UIC1_IRQ_LOWEST_OFFSET + 22)
116 #define BSP_UIC_GPT_TIMER4 (BSP_UIC1_IRQ_LOWEST_OFFSET + 23)
117 #define BSP_UIC_SERIAL_ROM (BSP_UIC1_IRQ_LOWEST_OFFSET + 24)
118 #define BSP_UIC_GPT_DEC (BSP_UIC1_IRQ_LOWEST_OFFSET + 25)
119 #define BSP_UIC_IRQ2 (BSP_UIC1_IRQ_LOWEST_OFFSET + 26)
120 #define BSP_UIC_IRQ5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 27)
121 #define BSP_UIC_IRQ6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 28)
122 #define BSP_UIC_EMAC0WU (BSP_UIC1_IRQ_LOWEST_OFFSET + 29)
123 #define BSP_UIC_IRQ1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 30)
124 #define BSP_UIC_EMAC1WU (BSP_UIC1_IRQ_LOWEST_OFFSET + 31)
125
126 #define BSP_UIC2_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + 64)
127 #define BSP_UIC_PCIe0INTA (BSP_UIC2_IRQ_LOWEST_OFFSET + 0)
128 #define BSP_UIC_PCIe0INTB (BSP_UIC2_IRQ_LOWEST_OFFSET + 1)
129 #define BSP_UIC_PCIe0INTC (BSP_UIC2_IRQ_LOWEST_OFFSET + 2)
130 #define BSP_UIC_PCIe0INTD (BSP_UIC2_IRQ_LOWEST_OFFSET + 3)
131 #define BSP_UIC_IRQ3 (BSP_UIC2_IRQ_LOWEST_OFFSET + 4)
132
133 #define BSP_UIC_USBOTG (BSP_UIC2_IRQ_LOWEST_OFFSET + 30)
134
135 #define BSP_UIC_IRQ_NUMBER (95)
136
137
138 #define BSP_UIC_IRQ_LOWEST_OFFSET 0
139 #define BSP_UIC_IRQ_MAX_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + BSP_UIC_IRQ_NUMBER - 1)
140
141 #define BSP_UART_COM1_IRQ BSP_UIC_UART0 /* Required by shared/console/uart.c */
142 #define BSP_UART_COM2_IRQ BSP_UIC_UART1
143
144 /* Define processor IRQ numbers; IRQs that are handled by the exception vectors */
145
146 #define BSP_PIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET /* Required by ppc403/clock.c */
147 #define BSP_FIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1
148 #define BSP_WDOG BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2
149
150 #define BSP_PROCESSOR_IRQ_NUMBER (3)
151 #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_MAX_OFFSET + 1)
152 #define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
153
154 /* Summary and totals */
155
156 #define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
157 #define BSP_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET)
158 #define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1)
159
160 extern void BSP_rtems_irq_mng_init(unsigned cpuId); // Implemented in irq_init.c
161 #include <bsp/irq_supp.h>
162
163 #ifdef __cplusplus
164 }
165 #endif
166#endif /* ASM */
167
168#endif /* Haleakala_IRQ_IRQ_H */
irq.h
irq-default.h