RTEMS: bsps/powerpc/include/bsp/uart.h Source File

| RTEMS 5.4-rc2

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uart.h
1
2/*
3 * This software is Copyright (C) 1998 by T.sqware - all rights limited
4 * It is provided in to the public domain "as is", can be freely modified
5 * as far as this copyight notice is kept unchanged, but does not imply
6 * an endorsement by T.sqware of the product in which it is included.
7 */
8
9#ifndef _BSPUART_H
10#define _BSPUART_H
11
12#include <bsp/irq.h>
13
14#include <sys/ioctl.h>
15#include <rtems/libio.h>
16
17void BSP_uart_init(int uart, int baud, int hwFlow);
18void BSP_uart_set_baud(int uart, int baud);
19void BSP_uart_intr_ctrl(int uart, int cmd);
20void BSP_uart_throttle(int uart);
21void BSP_uart_unthrottle(int uart);
22int BSP_uart_polled_status(int uart);
23void BSP_uart_polled_write(int uart, int val);
24int BSP_uart_polled_read(int uart);
25void BSP_uart_termios_set(int uart, void *ttyp);
26ssize_t BSP_uart_termios_write_com(int minor, const char *buf, size_t len);
27int BSP_uart_termios_read_com (int minor);
28void BSP_uart_termios_isr_com1(void *unused);
29void BSP_uart_termios_isr_com2(void *unused);
30void BSP_uart_dbgisr_com1(void);
31void BSP_uart_dbgisr_com2(void);
32int BSP_uart_install_isr(int uart, rtems_irq_hdl handler);
33int BSP_uart_remove_isr(int uart, rtems_irq_hdl handler);
34ssize_t BSP_uart_termios_write_polled(int minor, const char *buf, size_t len);
35int BSP_uart_get_break_cb(int uart, rtems_libio_ioctl_args_t *arg);
36int BSP_uart_set_break_cb(int uart, rtems_libio_ioctl_args_t *arg);
37
38extern unsigned BSP_poll_char_via_serial(void);
39extern void BSP_output_char_via_serial(const char val);
40extern int BSPConsolePort;
41extern int BSPBaseBaud;
42
43/* Special IOCTLS to install a lowlevel 'BREAK' handler */
44
45/* pass a BSP_UartBreakCb pointer to ioctl when retrieving
46 * or installing break callback
47 */
48typedef void (*BSP_UartBreakCbProc)(
49 int uartMinor,
50 unsigned uartRBRLSRStatus,
51 void *termiosPrivatePtr,
52 void *private
53);
54
55 typedef struct BSP_UartBreakCbRec_ {
56 BSP_UartBreakCbProc handler; /* NOTE: handler runs in INTERRUPT CONTEXT */
57 void *private; /* closure pointer which is passed to the callback */
58} BSP_UartBreakCbRec, *BSP_UartBreakCb;
59
60#define BIOCGETBREAKCB _IOR('b',1,sizeof(BSP_UartBreakCbRec))
61#define BIOCSETBREAKCB _IOW('b',2,sizeof(BSP_UartBreakCbRec))
62
63/*
64 * Command values for BSP_uart_intr_ctrl(),
65 * values are strange in order to catch errors
66 * with assert
67 */
68#define BSP_UART_INTR_CTRL_DISABLE (0)
69#define BSP_UART_INTR_CTRL_GDB (0xaa) /* RX only */
70#define BSP_UART_INTR_CTRL_ENABLE (0xbb) /* Normal operations */
71#define BSP_UART_INTR_CTRL_TERMIOS (0xcc) /* RX & line status */
72
73/* Return values for uart_polled_status() */
74#define BSP_UART_STATUS_ERROR (-1) /* No character */
75#define BSP_UART_STATUS_NOCHAR (0) /* No character */
76#define BSP_UART_STATUS_CHAR (1) /* Character present */
77#define BSP_UART_STATUS_BREAK (2) /* Break point is detected */
78
79/* PC UART definitions */
80#define BSP_UART_COM1 (0)
81#define BSP_UART_COM2 (1)
82
83/*
84 * Offsets from base
85 */
86
87/* DLAB 0 */
88#define RBR (0) /* Rx Buffer Register (read) */
89#define THR (0) /* Tx Buffer Register (write) */
90#define IER (1) /* Interrupt Enable Register */
91
92/* DLAB X */
93#define IIR (2) /* Interrupt Ident Register (read) */
94#define FCR (2) /* FIFO Control Register (write) */
95#define LCR (3) /* Line Control Register */
96#define MCR (4) /* Modem Control Register */
97#define LSR (5) /* Line Status Register */
98#define MSR (6) /* Modem Status Register */
99#define SCR (7) /* Scratch register */
100
101/* DLAB 1 */
102#define DLL (0) /* Divisor Latch, LSB */
103#define DLM (1) /* Divisor Latch, MSB */
104#define AFR (2) /* Alternate Function register */
105
106/*
107 * Interrupt source definition via IIR
108 */
109#define MODEM_STATUS 0
110#define NO_MORE_INTR 1
111#define TRANSMITTER_HODING_REGISTER_EMPTY 2
112#define RECEIVER_DATA_AVAIL 4
113#define RECEIVER_ERROR 6
114#define CHARACTER_TIMEOUT_INDICATION 12
115
116/*
117 * Bits definition of IER
118 */
119#define RECEIVE_ENABLE 0x1
120#define TRANSMIT_ENABLE 0x2
121#define RECEIVER_LINE_ST_ENABLE 0x4
122#define MODEM_ENABLE 0x8
123#define INTERRUPT_DISABLE 0x0
124
125/*
126 * Bits definition of the Line Status Register (LSR)
127 */
128#define DR 0x01 /* Data Ready */
129#define OE 0x02 /* Overrun Error */
130#define PE 0x04 /* Parity Error */
131#define FE 0x08 /* Framing Error */
132#define BI 0x10 /* Break Interrupt */
133#define THRE 0x20 /* Transmitter Holding Register Empty */
134#define TEMT 0x40 /* Transmitter Empty */
135#define ERFIFO 0x80 /* Error receive Fifo */
136
137/*
138 * Bits definition of the MODEM Control Register (MCR)
139 */
140#define DTR 0x01 /* Data Terminal Ready */
141#define RTS 0x02 /* Request To Send */
142#define OUT_1 0x04 /* Output 1, (reserved on COMPAQ I/O Board) */
143#define OUT_2 0x08 /* Output 2, Enable Asynchronous Port Interrupts */
144#define LB 0x10 /* Enable Internal Loop Back */
145
146/*
147 * Bits definition of the Line Control Register (LCR)
148 */
149#define CHR_5_BITS 0
150#define CHR_6_BITS 1
151#define CHR_7_BITS 2
152#define CHR_8_BITS 3
153
154#define WL 0x03 /* Word length mask */
155#define STB 0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */
156#define PEN 0x08 /* Parity Enabled */
157#define EPS 0x10 /* Even Parity Select, otherwise Odd */
158#define SP 0x20 /* Stick Parity */
159#define BCB 0x40 /* Break Control Bit */
160#define DLAB 0x80 /* Enable Divisor Latch Access */
161
162/*
163 * Bits definition of the MODEM Status Register (MSR)
164 */
165#define DCTS 0x01 /* Delta Clear To Send */
166#define DDSR 0x02 /* Delta Data Set Ready */
167#define TERI 0x04 /* Trailing Edge Ring Indicator */
168#define DDCD 0x08 /* Delta Carrier Detect Indicator */
169#define CTS 0x10 /* Clear To Send (when loop back is active) */
170#define DSR 0x20 /* Data Set Ready (when loop back is active) */
171#define RI 0x40 /* Ring Indicator (when loop back is active) */
172#define DCD 0x80 /* Data Carrier Detect (when loop back is active) */
173
174/*
175 * Bits definition of the FIFO Control Register : WD16C552 or NS16550
176 */
177
178#define FIFO_CTRL 0x01 /* Set to 1 permit access to other bits */
179#define FIFO_EN 0x01 /* Enable the FIFO */
180#define XMIT_RESET 0x02 /* Transmit FIFO Reset */
181#define RCV_RESET 0x04 /* Receive FIFO Reset */
182#define FCR3 0x08 /* do not understand manual! */
183
184#define RECEIVE_FIFO_TRIGGER1 0x00 /* trigger RX interrupt after 1 byte */
185#define RECEIVE_FIFO_TRIGGER4 0x40 /* trigger RX interrupt after 4 bytes */
186#define RECEIVE_FIFO_TRIGGER8 0x80 /* trigger RX interrupt after 8 bytes */
187#define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger RX interrupt after 12 bytes */
188#define TRIG_LEVEL 0xc0 /* Mask for the trigger level */
189
190#endif /* _BSPUART_H */
libio.h
Basic IO API.
BSP_UartBreakCbRec_
Definition: uart.h:55
rtems_libio_ioctl_args_t
Parameter block for ioctl.
Definition: libio.h:1355