RTEMS: bsps/powerpc/include/ppc4xx/ppc405gp.h Source File

| RTEMS 5.4-rc2

Loading...
Searching...
No Matches
ppc405gp.h
1
2/* SDRAM DCRs */
3enum {
4 SDRAM0_BESR0 = 0,
5 SDRAM0_BESR1 = 8,
6 SDRAM0_BEAR = 0x10,
7 SDRAM0_CFG = 0x20,
8 SDRAM0_STATUS = 0x24,
9 SDRAM0_RTR = 0x30,
10 SDRAM0_PMIT = 0x34,
11 SDRAM0_TR = 0x80
12};
13
14
15/* EBC DCRs */
16enum {
17 EBC0_B0CR = 0,
18 EBC0_B1CR = 1,
19 EBC0_B2CR = 2,
20 EBC0_B3CR = 3,
21 EBC0_B4CR = 4,
22 EBC0_B5CR = 5,
23 EBC0_B6CR = 6,
24 EBC0_B7CR = 7,
25 EBC0_B0AP = 0x10,
26 EBC0_B1AP = 0x11,
27 EBC0_B2AP = 0x12,
28 EBC0_B3AP = 0x13,
29 EBC0_B4AP = 0x14,
30 EBC0_B5AP = 0x15,
31 EBC0_B6AP = 0x16,
32 EBC0_B7AP = 0x17,
33 EBC0_BEAR = 0x20,
34 EBC0_BESR0 = 0x21,
35 EBC0_BESR1 = 0x22,
36 EBC0_CFG = 0x23
37};
38
39/* MAL DCRs, have to be #defines */
40#define MAL0_CFG 0x180
41#define MAL0_ESR 0x181
42#define MAL0_IER 0x182
43#define MAL0_TXCASR 0x184
44#define MAL0_TXCARR 0x185
45#define MAL0_TXEOBISR 0x186
46#define MAL0_TXDEIR 0x187
47#define MAL0_RXCASR 0x190
48#define MAL0_RXCARR 0x191
49#define MAL0_RXEOBISR 0x192
50#define MAL0_RXDEIR 0x193
51#define MAL0_TXCTP0R 0x1A0
52#define MAL0_TXCTP1R 0x1A1
53#define MAL0_RXCTP0R 0x1C0
54#define MAL0_RXCTP1R 0x1C1
55#define MAL0_RCBS0 0x1E0
56#define MAL0_RCBS1 0x1E1
57
58/* Memory-mapped registers */
59
60 typedef struct EthernetRegisters_GP {
61 uint32_t mode0;
62 uint32_t mode1;
63 uint32_t xmtMode0;
64 uint32_t xmtMode1;
65 uint32_t rcvMode;
66 uint32_t intStatus;
67 uint32_t intEnable;
68 uint32_t addrHi;
69 uint32_t addrLo;
70 uint32_t VLANTPID;
71 uint32_t VLANTCI;
72 uint32_t pauseTimer;
73 uint32_t g_indivHash[4]; /* EX non-IP multicast addr/mask */
74 uint32_t g_groupHash[4];
75 uint32_t lastSrcLo;
76 uint32_t lastSrcHi;
77 uint32_t IPGap;
78 uint32_t STAcontrol;
79 uint32_t xmtReqThreshold;
80 uint32_t rcvWatermarks;
81 uint32_t bytesXmtd;
82 uint32_t bytesRcvd;
83 uint32_t e_unused2;
84 uint32_t e_revID;
85 uint32_t e_unused3[2];
86 uint32_t e_indivHash[8];
87 uint32_t e_groupHash[8];
88 uint32_t e_xmtPause;
89} EthernetRegisters_GP;
90
91typedef struct EthernetRegisters_GP EthernetRegisters_EX;
92
93enum { EMACAddress = 0xEF600800 };
94enum { EMAC0GPAddress = 0xEF600800 };
95
96enum {
97 // Mode 0 bits
98 kEMACRxIdle = 0x80000000,
99 kEMACTxIdle = 0x40000000,
100 kEMACSoftRst = 0x20000000,
101 kEMACTxEnable = 0x10000000,
102 kEMACRxEnable = 0x08000000,
103
104 // Mode 1 bits
105 kEMACFullDuplex = 0x80000000,
106 kEMACDoFlowControl = 0x10000000,
107 kEMACIgnoreSQE = 0x01000000,
108 kEMAC100MBbps = 0x00400000,
109 kEMAC4KRxFIFO = 0x00300000,
110 kEMAC2KTxFIFO = 0x00080000,
111 kEMACTx0Multi = 0x00008000,
112 kEMACTxDependent= 0x00014000,
113 kEMAC100Mbps = 0x00400000,
114 kgEMAC4KRxFIFO = 0x00300000,
115 kgEMAC2KTxFIFO = 0x00080000,
116 kgEMACTx0Multi = 0x00008000,
117 kgEMACTxDependent= 0x00014000,
118
119
120 // Tx mode bits
121 kEMACNewPacket0 = 0x80000000,
122 kEMACNewPacket1 = 0x40000000,
123
124 // Receive mode bits
125 kEMACStripPadding = 0x80000000,
126 kEMACStripFCS = 0x40000000,
127 kEMACRcvRunts = 0x20000000,
128 kEMACRcvFCSErrs = 0x10000000,
129 kEMACRcvOversize = 0x08000000,
130 kEMACPromiscRcv = 0x01000000,
131 kEMACPromMultRcv = 0x00800000,
132 kEMACIndivRcv = 0x00400000,
133 kEMACHashRcv = 0x00200000,
134 kEMACBrcastRcv = 0x00100000,
135 kEMACMultcastRcv = 0x00080000,
136 keEMACNonIPMultcast = 0x00040000,
137 keEMACRxFIFOAFMax = 7,
138
139 // EMAC_STACR bits
140 kgSTAComplete = 0x8000,
141 kSTAErr = 0x4000,
142
143 // Interrupt status bits
144 kEMACIOverrun = 0x02000000,
145 kEMACIPause = 0x01000000,
146 kEMACIBadPkt = 0x00800000,
147 kEMACIRuntPkt = 0x00400000,
148 kEMACIShortEvt= 0x00200000,
149 kEMACIAlignErr= 0x00100000,
150 kEMACIBadFCS = 0x00080000,
151 kEMACIOverSize= 0x00040000,
152 kEMACILLCRange= 0x00020000,
153 kEMACISQEErr = 0x00000080,
154 kEMACITxErr = 0x00000040,
155
156 // Buffer descriptor control bits
157 kMALTxReady = 0x8000,
158 kMALRxEmpty = 0x8000,
159 kMALWrap = 0x4000,
160 kMALContinuous = 0x2000,
161 kMALLast = 0x1000,
162 kMALRxFirst = 0x0800,
163 kMALInterrupt = 0x0400,
164
165 kMALReset = 0x80000000,
166 kMALLowPriority = 0,
167 kMALMedLowPriority = 0x00400000,
168 kMALMedHiPriority = 0x00800000,
169 kMALHighPriority = 0x00C00000,
170 kMALLatency8 = 0x00040000,
171 kMALLockErr = 0x8000,
172 kMALCanBurst = 0x4000,
173 kMALLocksOPB = 0x80,
174 kMALLocksErrs = 0x2,
175
176 // MAL channel masks
177 kMALChannel0 = 0x80000000,
178 kMALChannel1 = 0x40000000,
179
180 // EMAC Tx descriptor bits sent
181 kEMACGenFCS = 0x200,
182 kEMACGenPad = 0x100,
183 kEMACInsSrcAddr = 0x080,
184 kEMACRepSrcAddr = 0x040,
185 kEMACInsVLAN = 0x020,
186 kEMACRepVLAN = 0x010,
187
188 // EMAC TX descriptor bits returned
189 kEMACErrMask = 0x3FF,
190 kEMACFCSWrong = 0x200,
191 kEMACBadPrev = 0x100,
192 kEMACLostCarrier = 0x080,
193 kEMACDeferred = 0x040,
194 kEMACCollFail = 0x020,
195 kEMACLateColl = 0x010,
196 kEMACMultColl = 0x008,
197 kEMACOneColl = 0x004,
198 kEMACUnderrun = 0x002,
199 kEMACSQEFail = 0x001,
200
201 // EMAC Rx descriptor bits returned
202 kEMACOverrun = 0x200,
203 kEMACPausePkt = 0x100,
204 kEMACBadPkt = 0x080,
205 kEMACRuntPkt = 0x040,
206 kEMACShortEvt = 0x020,
207 kEMACAlignErr = 0x010,
208 kEMACBadFCS = 0x008,
209 kEMACPktLong = 0x004,
210 kEMACPktOOR = 0x002,
211 kEMACPktIRL = 0x001
212};
213
214
EthernetRegisters_GP
Definition: ppc405gp.h:60