RTEMS: cpukit/score/cpu/lm32/include/rtems/score/cpu.h File Reference

| RTEMS 5.4-rc2

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Data Structures | Macros | Typedefs | Functions | Variables
cpu.h File Reference

LM32 CPU Department Source. More...

`#include <rtems/score/basedefs.h>`
`#include <rtems/score/lm32.h>`

Go to the source code of this file.

## Data Structures
struct | Context_Control
| Thread register context. More...
struct | CPU_Interrupt_frame
| Interrupt stack frame (ISF). More...

## Macros
#define | CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
#define | CPU_ISR_PASSES_FRAME_POINTER TRUE
#define | CPU_HARDWARE_FP FALSE
#define | CPU_SOFTWARE_FP FALSE
#define | CPU_ALL_TASKS_ARE_FP FALSE
#define | CPU_IDLE_TASK_IS_FP FALSE
#define | CPU_USE_DEFERRED_FP_SWITCH TRUE
#define | CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
#define | CPU_STACK_GROWS_UP FALSE
#define | CPU_CACHE_LINE_BYTES 32
#define | CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
#define | CPU_MODES_INTERRUPT_MASK 0x00000001
#define | CPU_MAXIMUM_PROCESSORS 32
#define | _CPU_Context_Get_SP(_context) (_context)->sp
#define | CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
#define | CPU_INTERRUPT_NUMBER_OF_VECTORS 32
#define | CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
#define | CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
#define | CPU_STACK_MINIMUM_SIZE (1024*4)
#define | CPU_SIZEOF_POINTER 4
#define | CPU_ALIGNMENT 4
#define | CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
#define | CPU_STACK_ALIGNMENT CPU_ALIGNMENT
#define | CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
#define | _CPU_Initialize_vectors()
#define | _CPU_ISR_Disable(_isr_cookie) lm32_disable_interrupts( _isr_cookie );
#define | _CPU_ISR_Enable(_isr_cookie) lm32_enable_interrupts( _isr_cookie );
#define | _CPU_ISR_Flash(_isr_cookie) lm32_flash_interrupts( _isr_cookie );
#define | _CPU_ISR_Set_level(new_level)
#define | _CPU_Context_Initialize(_the_context, _stack_base, _size, _isr, _entry_point, _is_fp, _tls_area)
#define | _CPU_Context_Restart_self(_the_context) _CPU_Context_restore( (_the_context) );
#define | _CPU_Context_Initialize_fp(_destination)
#define | _CPU_Fatal_halt(_source, _error)
#define | CPU_USE_GENERIC_BITFIELD_CODE TRUE

## Typedefs
typedef void(* | CPU_ISR_raw_handler) (void)
typedef void(* | CPU_ISR_handler) (uint32_t)
typedef CPU_Interrupt_frame | CPU_Exception_frame
typedef uint32_t | CPU_Counter_ticks
typedef uintptr_t | CPU_Uint32ptr

## Functions
RTEMS_INLINE_ROUTINE bool | _CPU_ISR_Is_enabled (uint32_t level)
uint32_t | _CPU_ISR_Get_level (void)
void | _CPU_Initialize (void)
| CPU initialization.
RTEMS_INLINE_ROUTINE void | _CPU_ISR_install_raw_handler (uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
| SPARC specific raw ISR installer.
void | _CPU_ISR_install_vector (uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
void * | _CPU_Thread_Idle_body (uintptr_t ignored)
void | _CPU_Context_switch (Context_Control *run, Context_Control *heir)
| CPU switch context.
void | _CPU_Context_restore (Context_Control *new_context) RTEMS_NO_RETURN
void | _CPU_Exception_frame_print (const CPU_Exception_frame *frame)
| Prints the exception frame via printk().
uint32_t | _CPU_Counter_frequency (void)
CPU_Counter_ticks | _CPU_Counter_read (void)

## Variables
char | _gp []

## Detailed Description

LM32 CPU Department Source.

This include file contains information pertaining to the LM32 processor.

## Macro Definition Documentation

## ◆ _CPU_Context_Initialize

#define _CPU_Context_Initialize | ( |  | _the_context,
|  |  | _stack_base,
|  |  | _size,
|  |  | _isr,
|  |  | _entry_point,
|  |  | _is_fp,
|  |  | _tls_area
| ) |  |

Value:
do { \
uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \
\
(void) _is_fp; /* avoid warning for being unused */ \
(void) _isr; /* avoid warning for being unused */ \
(_the_context)->gp = (uint32_t)_gp; \
(_the_context)->fp = (uint32_t)_stack; \
(_the_context)->sp = (uint32_t)_stack; \
(_the_context)->ra = (uint32_t)(_entry_point); \
} while ( 0 )
ra
#define ra
return address *‍/
Definition: regs.h:66
sp
#define sp
stack-pointer *‍/
Definition: regs.h:64
fp
#define fp
frame-pointer *‍/
Definition: regs.h:65
gp
#define gp
global data pointer *‍/
Definition: regs.h:63

## ◆ _CPU_Context_Initialize_fp

#define _CPU_Context_Initialize_fp | ( |  | _destination | ) |

This routine initializes the FP context area passed to it to. There are a few standard ways in which to initialize the floating point context. The code included for this macro assumes that this is a CPU in which a "initial" FP context was saved into _CPU_Null_fp_context and it simply copies it to the destination context passed to it.

Other floating point context save/restore models include:

1. not doing anything, and
2. putting a "null FP status word" in the correct place in the FP context.

Parameters

  [in] | _destination | is the floating point context area

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ _CPU_Context_Restart_self

#define _CPU_Context_Restart_self | ( |  | _the_context | ) | _CPU_Context_restore( (_the_context) );

This routine is responsible for somehow restarting the currently executing task. If you are lucky, then all that is necessary is restoring the context. Otherwise, there will need to be a special assembly routine which does something special in this case. For many ports, simply adding a label to the restore path of _CPU_Context_switch will work. On other ports, it may be possibly to load a few arguments and jump to the restore path. It will not work if restarting self conflicts with the stack frame assumptions of restoring a context.

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ _CPU_Fatal_halt

#define _CPU_Fatal_halt | ( |  | _source,
|  |  | _error
| ) |  |

Value:
{ \
}

This routine copies _error into a known place – typically a stack location or a register, optionally disables interrupts, and halts/stops the CPU.

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ CPU_ALIGNMENT

#define CPU_ALIGNMENT 4

CPU's worst alignment requirement for data types on a byte boundary. This alignment does not take into account the requirements for the stack.

Port Specific Information: The LM32 architecture manual simply states: "All memory accesses must be aligned to the size of the access", and there is no hardware support whatsoever for 64-bit numbers. (lm32_archman.pdf, July 2009, p. 15)

## ◆ CPU_ALL_TASKS_ARE_FP

#define CPU_ALL_TASKS_ARE_FP FALSE

Are all tasks RTEMS_FLOATING_POINT tasks implicitly?

If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.

So far, the only CPUs in which this option has been used are the HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and gcc both implicitly used the floating point registers to perform integer multiplies. Similarly, the PowerPC port of gcc has been seen to allocate floating point local variables and touch the FPU even when the flow through a subroutine (like vfprintf()) might not use floating point formats.

If a function which you would not think utilize the FP unit DOES, then one can not easily predict which tasks will use the FP hardware. In this case, this option should be TRUE.

If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ CPU_HEAP_ALIGNMENT

#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT

This number corresponds to the byte alignment requirement for the heap handler. This alignment requirement may be stricter than that for the data types alignment specified by CPU_ALIGNMENT. It is common for the heap to follow the same alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, then this should be set to CPU_ALIGNMENT.

NOTE: This does not have to be a power of 2 although it should be a multiple of 2 greater than or equal to 2. The requirement to be a multiple of 2 is because the heap uses the least significant field of the front and back flags to indicate that a block is in use or free. So you do not want any odd length blocks really putting length data in that bit.

On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will have to be greater or equal to than CPU_ALIGNMENT to ensure that elements allocated from the heap meet all restrictions.

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ CPU_IDLE_TASK_IS_FP

#define CPU_IDLE_TASK_IS_FP FALSE

Should the IDLE task have a floating point context?

If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task and it has a floating point context which is switched in and out. If FALSE, then the IDLE task does not have a floating point context.

Setting this to TRUE negatively impacts the time required to preempt the IDLE task from an interrupt because the floating point context must be saved as part of the preemption.

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ CPU_ISR_PASSES_FRAME_POINTER

#define CPU_ISR_PASSES_FRAME_POINTER TRUE

Does the RTEMS invoke the user's ISR with the vector number and a pointer to the saved interrupt frame (1) or just the vector number (0)?

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ CPU_SIMPLE_VECTORED_INTERRUPTS

#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE

Does the CPU follow the simple vectored interrupt model?

If TRUE, then RTEMS allocates the vector table it internally manages. If FALSE, then the BSP is assumed to allocate and manage the vector table

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ CPU_STACK_ALIGNMENT

#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT

This number corresponds to the byte alignment requirement for the stack. This alignment requirement may be stricter than that for the data types alignment specified by CPU_ALIGNMENT.

Port Specific Information:

Stack is software-managed

## ◆ CPU_STACK_GROWS_UP

#define CPU_STACK_GROWS_UP FALSE

Does the stack grow up (toward higher addresses) or down (toward lower addresses)?

If TRUE, then the grows upward. If FALSE, then the grows toward smaller addresses.

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ CPU_USE_DEFERRED_FP_SWITCH

#define CPU_USE_DEFERRED_FP_SWITCH TRUE

Should the saving of the floating point registers be deferred until a context switch is made to another different floating point task?

If TRUE, then the floating point context will not be stored until necessary. It will remain in the floating point registers and not disturned until another floating point task is switched to.

If FALSE, then the floating point context is saved when a floating point task is switched out and restored when the next floating point task is restored. The state of the floating point registers between those two operations is not specified.

If the floating point context does NOT have to be saved as part of interrupt dispatching, then it should be safe to set this to TRUE.

Setting this flag to TRUE results in using a different algorithm for deciding when to save and restore the floating point context. The deferred FP switch algorithm minimizes the number of times the FP context is saved and restored. The FP context is not saved until a context switch is made to another, different FP task. Thus in a system with only one FP task, the FP context will never be saved or restored.

Port Specific Information:

XXX document implementation including references if appropriate

## Typedef Documentation

## ◆ CPU_Uint32ptr

typedef uintptr_t CPU_Uint32ptr

Type that can store a 32-bit integer or a pointer.