RTEMS: bsps/shared/dev/serial/mc68681_p.h Source File

| RTEMS 5.4-rc2

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mc68681_p.h
1/*
2 *
3 * COPYRIGHT (c) 1989-1999.
4 * On-Line Applications Research Corporation (OAR).
5 *
6 * The license and distribution terms for this file may be
7 * found in the file LICENSE in this distribution or at
8 * http://www.rtems.org/license/LICENSE.
9 */
10
11#ifndef _MC68681_P_H_
12#define _MC68681_P_H_
13
14#ifdef __cplusplus
15extern "C" {
16#endif
17
18/*
19 * Define MC68681_STATIC to nothing while debugging so the entry points
20 * will show up in the symbol table.
21 */
22
23#define MC68681_STATIC
24
25/* #define MC68681_STATIC static */
26
27/*
28 * mc68681 register offsets Read/Write Addresses
29 */
30
31#define MC68681_MODE_REG_1A 0 /* MR1A-MR Prior to Read */
32#define MC68681_MODE_REG_2A 0 /* MR2A-MR After Read */
33
34#define MC68681_COUNT_MODE_CURRENT_MSB 6 /* CTU */
35#define MC68681_COUNTER_TIMER_UPPER_REG 6 /* CTU */
36#define MC68681_COUNT_MODE_CURRENT_LSB 7 /* CTL */
37#define MC68681_COUNTER_TIMER_LOWER_REG 7 /* CTL */
38#define MC68681_INTERRUPT_VECTOR_REG 12 /* IVR */
39
40#define MC68681_MODE_REG_1B 8 /* MR1B-MR Prior to Read */
41#define MC68681_MODE_REG_2B 8 /* MR2BA-MR After Read */
42
43/*
44 * mc68681 register offsets Read Only Addresses
45 */
46
47#define MC68681_STATUS_REG_A 1 /* SRA */
48#define MC68681_MASK_ISR_REG 2 /* MISR */
49#define MC68681_RECEIVE_BUFFER_A 3 /* RHRA */
50#define MC68681_INPUT_PORT_CHANGE_REG 4 /* IPCR */
51#define MC68681_INTERRUPT_STATUS_REG 5 /* ISR */
52#define MC68681_STATUS_REG_B 9 /* SRB */
53#define MC68681_RECEIVE_BUFFER_B 11 /* RHRB */
54#define MC68681_INPUT_PORT 13 /* IP */
55#define MC68681_START_COUNT_CMD 14 /* SCC */
56#define MC68681_STOP_COUNT_CMD 15 /* STC */
57
58/*
59 * mc68681 register offsets Write Only Addresses
60 */
61
62#define MC68681_CLOCK_SELECT_REG_A 1 /* CSRA */
63#define MC68681_COMMAND_REG_A 2 /* CRA */
64#define MC68681_TRANSMIT_BUFFER_A 3 /* THRA */
65#define MC68681_AUX_CTRL_REG 4 /* ACR */
66#define MC68681_INTERRUPT_MASK_REG 5 /* IMR */
67#define MC68681_CLOCK_SELECT_REG_B 9 /* CSRB */
68#define MC68681_COMMAND_REG_B 10 /* CRB */
69#define MC68681_TRANSMIT_BUFFER_B 11 /* THRB */
70#define MC68681_OUTPUT_PORT_CONFIG_REG 13 /* OPCR */
71#define MC68681_OUTPUT_PORT_SET_REG 14 /* SOPBC */
72#define MC68681_OUTPUT_PORT_RESET_BITS 15 /* COPBC */
73
74/*
75 * DUART Command Register Definitions:
76 *
77 * MC68681_COMMAND_REG_A,MC68681_COMMAND_REG_B
78 */
79
80#define MC68681_MODE_REG_ENABLE_RX 0x01
81#define MC68681_MODE_REG_DISABLE_RX 0x02
82#define MC68681_MODE_REG_ENABLE_TX 0x04
83#define MC68681_MODE_REG_DISABLE_TX 0x08
84#define MC68681_MODE_REG_RESET_MR_PTR 0x10
85#define MC68681_MODE_REG_RESET_RX 0x20
86#define MC68681_MODE_REG_RESET_TX 0x30
87#define MC68681_MODE_REG_RESET_ERROR 0x40
88#define MC68681_MODE_REG_RESET_BREAK 0x50
89#define MC68681_MODE_REG_START_BREAK 0x60
90#define MC68681_MODE_REG_STOP_BREAK 0x70
91#define MC68681_MODE_REG_SET_RX_BRG 0x80
92#define MC68681_MODE_REG_CLEAR_RX_BRG 0x90
93#define MC68681_MODE_REG_SET_TX_BRG 0xa0
94#define MC68681_MODE_REG_CLEAR_TX_BRG 0xb0
95#define MC68681_MODE_REG_SET_STANDBY 0xc0
96#define MC68681_MODE_REG_SET_ACTIVE 0xd0
97
98/*
99 * Mode Register Definitions
100 *
101 * MC68681_MODE_REG_1A
102 * MC68681_MODE_REG_1B
103 */
104
105#define MC68681_5BIT_CHARS 0x00
106#define MC68681_6BIT_CHARS 0x01
107#define MC68681_7BIT_CHARS 0x02
108#define MC68681_8BIT_CHARS 0x03
109
110#define MC68681_ODD_PARITY 0x00
111#define MC68681_EVEN_PARITY 0x04
112
113#define MC68681_WITH_PARITY 0x00
114#define MC68681_FORCE_PARITY 0x08
115#define MC68681_NO_PARITY 0x10
116#define MC68681_MULTI_DROP 0x18
117
118#define MC68681_ERR_MODE_CHAR 0x00
119#define MC68681_ERR_MODE_BLOCK 0x20
120
121#define MC68681_RX_INTR_RX_READY 0x00
122#define MC68681_RX_INTR_FFULL 0x40
123
124#define MC68681_NO_RX_RTS_CTL 0x00
125#define MC68681_RX_RTS_CTRL 0x80
126
127/*
128 * Mode Register Definitions
129 *
130 * MC68681_MODE_REG_2A
131 * MC68681_MODE_REG_2B
132 */
133
134#define MC68681_STOP_BIT_LENGTH__563 0x00
135#define MC68681_STOP_BIT_LENGTH__625 0x01
136#define MC68681_STOP_BIT_LENGTH__688 0x02
137#define MC68681_STOP_BIT_LENGTH__75 0x03
138#define MC68681_STOP_BIT_LENGTH__813 0x04
139#define MC68681_STOP_BIT_LENGTH__875 0x05
140#define MC68681_STOP_BIT_LENGTH__938 0x06
141#define MC68681_STOP_BIT_LENGTH_1 0x07
142#define MC68681_STOP_BIT_LENGTH_1_563 0x08
143#define MC68681_STOP_BIT_LENGTH_1_625 0x09
144#define MC68681_STOP_BIT_LENGTH_1_688 0x0a
145#define MC68681_STOP_BIT_LENGTH_1_75 0x0b
146#define MC68681_STOP_BIT_LENGTH_1_813 0x0c
147#define MC68681_STOP_BIT_LENGTH_1_875 0x0d
148#define MC68681_STOP_BIT_LENGTH_1_938 0x0e
149#define MC68681_STOP_BIT_LENGTH_2 0x0f
150
151#define MC68681_CTS_ENABLE_TX 0x10
152#define MC68681_TX_RTS_CTRL 0x20
153
154#define MC68681_CHANNEL_MODE_NORMAL 0x00
155#define MC68681_CHANNEL_MODE_ECHO 0x40
156#define MC68681_CHANNEL_MODE_LOCAL_LOOP 0x80
157#define MC68681_CHANNEL_MODE_REMOTE_LOOP 0xc0
158
159/*
160 * Status Register Definitions
161 *
162 * MC68681_STATUS_REG_A, MC68681_STATUS_REG_B
163 */
164
165#define MC68681_RX_READY 0x01
166#define MC68681_FFULL 0x02
167#define MC68681_TX_READY 0x04
168#define MC68681_TX_EMPTY 0x08
169#define MC68681_OVERRUN_ERROR 0x10
170#define MC68681_PARITY_ERROR 0x20
171#define MC68681_FRAMING_ERROR 0x40
172#define MC68681_RECEIVED_BREAK 0x80
173
174#define MC68681_RX_ERRORS \
175 (MC68681_OVERRUN_ERROR|MC68681_PARITY_ERROR| \
176 MC68681_FRAMING_ERROR|MC68681_RECEIVED_BREAK)
177
178/*
179 * Interupt Status Register Definitions.
180 *
181 * MC68681_INTERRUPT_STATUS_REG
182 */
183
184/*
185 * Interupt Mask Register Definitions
186 *
187 * MC68681_INTERRUPT_MASK_REG
188 */
189
190/* These are passed to mc68681_build_imr */
191#define MC68681_IR_TX_READY 0x01
192#define MC68681_IR_RX_READY 0x02
193#define MC68681_IR_BREAK 0x04
194#define MC68681_IMR_ENABLE_ALL 0x07
195#define MC68681_IMR_DISABLE_ALL 0x00
196#define MC68681_IMR_ENABLE_ALL_EXCEPT_TX 0x06
197
198#define MC68681_IR_TX_READY_A 0x01
199#define MC68681_IR_RX_READY_A 0x02
200#define MC68681_IR_BREAK_A 0x04
201#define MC68681_IR_COUNTER_READY 0x08
202#define MC68681_IR_TX_READY_B 0x10
203#define MC68681_IR_RX_READY_B 0x20
204#define MC68681_IR_BREAK_B 0x40
205#define MC68681_IR_INPUT_PORT_CHANGE 0x80
206
207/*
208 * Status Register Definitions.
209 *
210 * MC68681_STATUS_REG_A,MC68681_STATUS_REG_B
211 */
212
213#define MC68681_STATUS_RXRDY 0x01
214#define MC68681_STATUS_FFULL 0x02
215#define MC68681_STATUS_TXRDY 0x04
216#define MC68681_STATUS_TXEMT 0x08
217#define MC68681_STATUS_OVERRUN_ERROR 0x10
218#define MC68681_STATUS_PARITY_ERROR 0x20
219#define MC68681_STATUS_FRAMING_ERROR 0x40
220#define MC68681_STATUS_RECEIVED_BREAK 0x80
221
222/*
223 * Definitions for the Interrupt Vector Register:
224 *
225 * MC68681_INTERRUPT_VECTOR_REG
226 */
227
228#define MC68681_INTERRUPT_VECTOR_INIT 0x0f
229
230/*
231 * Definitions for the Auxiliary Control Register
232 *
233 * MC68681_AUX_CTRL_REG
234 */
235
236#define MC68681_AUX_BRG_SET1 0x00
237#define MC68681_AUX_BRG_SET2 0x80
238
239/*
240 * Per chip context control
241 */
242
243 typedef struct _mc68681_context
244{
245 int mate;
246 unsigned char imr;
247} mc68681_context;
248
249/*
250 * Driver functions
251 */
252MC68681_STATIC void mc68681_initialize_context(
253 int minor,
254 mc68681_context *pmc68681Context
255);
256
257MC68681_STATIC bool mc68681_probe(int minor);
258
259MC68681_STATIC int mc68681_set_attributes(
260 int minor,
261 const struct termios *t
262);
263
264MC68681_STATIC void mc68681_init(int minor);
265
266MC68681_STATIC int mc68681_open(
267 int major,
268 int minor,
269 void * arg
270);
271
272MC68681_STATIC int mc68681_close(
273 int major,
274 int minor,
275 void * arg
276);
277
278MC68681_STATIC void mc68681_write_polled(
279 int minor,
280 char cChar
281);
282
283MC68681_STATIC void mc68681_initialize_interrupts(int minor);
284
285MC68681_STATIC ssize_t mc68681_write_support_int(
286 int minor,
287 const char *buf,
288 size_t len
289);
290
291MC68681_STATIC ssize_t mc68681_write_support_polled(
292 int minor,
293 const char *buf,
294 size_t len
295 );
296
297MC68681_STATIC int mc68681_inbyte_nonblocking_polled(
298 int minor
299);
300
301MC68681_STATIC unsigned int mc68681_build_imr(
302 int minor,
303 int enable_flag
304);
305
306MC68681_STATIC void mc68681_process(
307 int minor
308);
309
310MC68681_STATIC void mc68681_enable_interrupts(
311 int minor,
312 int imr_mask
313);
314
315MC68681_STATIC rtems_isr mc68681_isr(
316 rtems_vector_number vector
317);
318
319#ifdef __cplusplus
320}
321#endif
322
323#endif /* _MC68681_P_H_ */
rtems_isr
ISR_Handler rtems_isr
Return type for interrupt handler.
Definition: intr.h:52
rtems_vector_number
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition: intr.h:47
_mc68681_context
Definition: mc68681_p.h:244