RTEMS: bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h Source File

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reg_vim.h
1/* The header file is generated by make_header.py from VIM.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 * list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 * this list of conditions and the following disclaimer in the documentation
22 * and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_TMS570_VIM
40#define LIBBSP_ARM_TMS570_VIM
41
42#include <bsp/utility.h>
43
44 typedef struct{
45 uint32_t PARFLG; /*Interrupt Vector Table Parity Flag Register*/
46 uint32_t PARCTL; /*Interrupt Vector Table Parity Control Register*/
47 uint32_t ADDERR; /*Address Parity Error Register*/
48 uint32_t FBPARERR; /*Fall-Back Address Parity Error Register*/
49 uint8_t reserved1 [4];
50 uint32_t IRQINDEX; /*IRQ Index Offset Vector Register*/
51 uint32_t FIQINDEX; /*FIQ Index Offset Vector Register*/
52 uint8_t reserved2 [8];
53 uint32_t FIRQPR[3]; /*FIQ/IRQ Program Control Register*/
54 uint8_t reserved3 [4];
55 uint32_t INTREQ[3]; /*Pending Interrupt Read Location Register*/
56 uint8_t reserved4 [4];
57 uint32_t REQENASET[3]; /*Interrupt Enable Set Register */
58 uint8_t reserved5 [4];
59 uint32_t REQENACLR[3]; /*Interrupt Enable Clear Register */
60 uint8_t reserved6 [4];
61 uint32_t WAKEENASET[3]; /*Wake-Up Enable Set Register*/
62 uint8_t reserved7 [4];
63 uint32_t WAKEENACLR[3]; /*Wake-Up Enable Clear Registers*/
64 uint8_t reserved8 [4];
65 uint32_t IRQVECREG; /*IRQ Interrupt Vector Register*/
66 uint32_t FIQVECREG; /*FIQ Interrupt Vector Register*/
67 uint32_t CAPEVT; /*Capture Event Register*/
68 uint8_t reserved9 [4];
69 uint32_t CHANCTRL[24]; /*VIM Interrupt Control Register*/
70} tms570_vim_t;
71
72
73/*---------------------TMS570_VIM_PARFLG---------------------*/
74/* field: PARFLG - The PARFLG indicates that a parity error has been found and that theInterrupt Vector Table is */
75#define TMS570_VIM_PARFLG_PARFLG BSP_BIT32(0)
76
77
78/*---------------------TMS570_VIM_PARCTL---------------------*/
79/* field: TEST - This bit maps the parity bits into the Interrupt Vector Table frame to make them accessible by the */
80#define TMS570_VIM_PARCTL_TEST BSP_BIT32(8)
81
82/* field: PARENA - VIM parity enable. */
83#define TMS570_VIM_PARCTL_PARENA(val) BSP_FLD32(val,0, 3)
84#define TMS570_VIM_PARCTL_PARENA_GET(reg) BSP_FLD32GET(reg,0, 3)
85#define TMS570_VIM_PARCTL_PARENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
86
87
88/*---------------------TMS570_VIM_ADDERR---------------------*/
89/* field: Interrupt_Vector_Table - Interrupt Vector Table offset. */
90#define TMS570_VIM_ADDERR_Interrupt_Vector_Table(val) BSP_FLD32(val,9, 31)
91#define TMS570_VIM_ADDERR_Interrupt_Vector_Table_GET(reg) BSP_FLD32GET(reg,9, 31)
92#define TMS570_VIM_ADDERR_Interrupt_Vector_Table_SET(reg,val) BSP_FLD32SET(reg, val,9, 31)
93
94/* field: ADDERR - Address parity error register. */
95#define TMS570_VIM_ADDERR_ADDERR(val) BSP_FLD32(val,2, 8)
96#define TMS570_VIM_ADDERR_ADDERR_GET(reg) BSP_FLD32GET(reg,2, 8)
97#define TMS570_VIM_ADDERR_ADDERR_SET(reg,val) BSP_FLD32SET(reg, val,2, 8)
98
99/* field: Word_offset - Word offset. Reads are always 0; writes have no effect. */
100#define TMS570_VIM_ADDERR_Word_offset(val) BSP_FLD32(val,0, 1)
101#define TMS570_VIM_ADDERR_Word_offset_GET(reg) BSP_FLD32GET(reg,0, 1)
102#define TMS570_VIM_ADDERR_Word_offset_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
103
104
105/*--------------------TMS570_VIM_FBPARERR--------------------*/
106/* field: FBPARERR - Fall back address parity error. */
107/* Whole 32 bits */
108
109/*--------------------TMS570_VIM_IRQINDEX--------------------*/
110/* field: IRQINDEX - IRQ index vector. */
111#define TMS570_VIM_IRQINDEX_IRQINDEX(val) BSP_FLD32(val,0, 7)
112#define TMS570_VIM_IRQINDEX_IRQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
113#define TMS570_VIM_IRQINDEX_IRQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
114
115
116/*--------------------TMS570_VIM_FIQINDEX--------------------*/
117/* field: FIQINDEX - FIQ index offset vector. */
118#define TMS570_VIM_FIQINDEX_FIQINDEX(val) BSP_FLD32(val,0, 7)
119#define TMS570_VIM_FIQINDEX_FIQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
120#define TMS570_VIM_FIQINDEX_FIQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
121
122
123/*---------------------TMS570_VIM_FIRQPR---------------------*/
124/* field: FIRQPRx - FIQ/IRQ program control bits. 96 bit register. 0-1 bits reserved. */
125/* Whole 32 bits */
126
127/*---------------------TMS570_VIM_INTREQ---------------------*/
128/* field: INTREQx - Pending interrupt bits. 96 bit register. */
129/* Whole 32 bits */
130
131/*--------------------TMS570_VIM_REQENASET--------------------*/
132/* field: REQENASETx - Request enable set bits. 96 bit register. 0-1 bits reserved. */
133/* Whole 32 bits */
134
135/*--------------------TMS570_VIM_REQENACLR--------------------*/
136/* field: REQENACLRx - Request enable clear bits. 96 bit register. 0-1 bits reserved. */
137/* Whole 32 bits */
138
139/*-------------------TMS570_VIM_WAKEENASET-------------------*/
140/* field: WAKEENASETx - Wake-up enable set bits. This vector determines whether the wake-up interrupt line is enabled. */
141/* Whole 32 bits */
142
143/*-------------------TMS570_VIM_WAKEENACLR-------------------*/
144/* field: WAKEENACLRx - Wake-up enable clear bits. This vector determines whether the wake-up interrupt line is enabled. */
145/* Whole 32 bits */
146
147/*--------------------TMS570_VIM_IRQVECREG--------------------*/
148/* field: IRQVECREG - IRQ interrupt vector register. */
149/* Whole 32 bits */
150
151/*--------------------TMS570_VIM_FIQVECREG--------------------*/
152/* field: FIQVECREG - FIQ interrupt vector register. */
153/* Whole 32 bits */
154
155/*---------------------TMS570_VIM_CAPEVT---------------------*/
156/* field: CAPEVTSRC1 - Capture event source 1 mapping control. */
157#define TMS570_VIM_CAPEVT_CAPEVTSRC1(val) BSP_FLD32(val,16, 22)
158#define TMS570_VIM_CAPEVT_CAPEVTSRC1_GET(reg) BSP_FLD32GET(reg,16, 22)
159#define TMS570_VIM_CAPEVT_CAPEVTSRC1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22)
160
161/* field: CAPEVTSRC0 - the capture event source 0 of the RTI: */
162#define TMS570_VIM_CAPEVT_CAPEVTSRC0(val) BSP_FLD32(val,0, 6)
163#define TMS570_VIM_CAPEVT_CAPEVTSRC0_GET(reg) BSP_FLD32GET(reg,0, 6)
164#define TMS570_VIM_CAPEVT_CAPEVTSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
165
166
167/*--------------------TMS570_VIM_CHANCTRL--------------------*/
168/* field: CHANMAPx0 - CHANMAPx 0(6-0). Interrupt CHANx 0 mapping control. */
169#define TMS570_VIM_CHANCTRL_CHANMAPx0(val) BSP_FLD32(val,24, 30)
170#define TMS570_VIM_CHANCTRL_CHANMAPx0_GET(reg) BSP_FLD32GET(reg,24, 30)
171#define TMS570_VIM_CHANCTRL_CHANMAPx0_SET(reg,val) BSP_FLD32SET(reg, val,24, 30)
172
173/* field: CHANMAPx1 - CHANMAPx 1(6-0). Interrupt CHANx 1 mapping control. */
174#define TMS570_VIM_CHANCTRL_CHANMAPx1(val) BSP_FLD32(val,16, 22)
175#define TMS570_VIM_CHANCTRL_CHANMAPx1_GET(reg) BSP_FLD32GET(reg,16, 22)
176#define TMS570_VIM_CHANCTRL_CHANMAPx1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22)
177
178/* field: CHANMAPx2 - CHANMAPx 2(6-0). Interrupt CHANx 2 mapping control. */
179#define TMS570_VIM_CHANCTRL_CHANMAPx2(val) BSP_FLD32(val,8, 14)
180#define TMS570_VIM_CHANCTRL_CHANMAPx2_GET(reg) BSP_FLD32GET(reg,8, 14)
181#define TMS570_VIM_CHANCTRL_CHANMAPx2_SET(reg,val) BSP_FLD32SET(reg, val,8, 14)
182
183/* field: CHANMAPx3 - CHANMAPx 3(6-0). Interrupt CHANx 3 mapping control. */
184#define TMS570_VIM_CHANCTRL_CHANMAPx3(val) BSP_FLD32(val,0, 6)
185#define TMS570_VIM_CHANCTRL_CHANMAPx3_GET(reg) BSP_FLD32GET(reg,0, 6)
186#define TMS570_VIM_CHANCTRL_CHANMAPx3_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
187
188
189
190#endif /* LIBBSP_ARM_TMS570_VIM */
utility.h
Utility macros.
tms570_vim_t
Definition: reg_vim.h:44