RTEMS: bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h Source File

| RTEMS 5.4-rc2

Loading...
Searching...
No Matches
alt_qspi.h
Go to the documentation of this file.
1
7/*******************************************************************************
8* *
9* Copyright 2013 Altera Corporation. All Rights Reserved. *
10* *
11* Redistribution and use in source and binary forms, with or without *
12* modification, are permitted provided that the following conditions are met: *
13* *
14* 1. Redistributions of source code must retain the above copyright notice, *
15* this list of conditions and the following disclaimer. *
16* *
17* 2. Redistributions in binary form must reproduce the above copyright notice, *
18* this list of conditions and the following disclaimer in the documentation *
19* and/or other materials provided with the distribution. *
20* *
21* 3. The name of the author may not be used to endorse or promote products *
22* derived from this software without specific prior written permission. *
23* *
24* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
25* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
26* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
27* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
28* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
29* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
30* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
31* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
32* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
33* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
34* *
35*******************************************************************************/
36
37/* Altera - ALT_QSPI */
38
39#ifndef __ALTERA_ALT_QSPI_H__
40#define __ALTERA_ALT_QSPI_H__
41
42#ifdef __cplusplus
43extern "C"
44{
45#endif /* __cplusplus */
46
47/*
48 * Component : QSPI Flash Controller Module Registers - ALT_QSPI
49 * QSPI Flash Controller Module Registers
50 *
51 * Registers in the QSPI Flash Controller module accessible via its APB slave
52 *
53 */
54/*
55 * Register : QSPI Configuration Register - cfg
56 *
57 * Register Layout
58 *
59 * Bits | Access | Reset | Description
60 * :--------|:-------|:------|:-------------------------------------------
61 * [0] | RW | 0x0 | QSPI Enable
62 * [1] | RW | 0x0 | Clock Polarity
63 * [2] | RW | 0x0 | Select Clock Phase
64 * [6:3] | ??? | 0x0 | *UNDEFINED*
65 * [7] | RW | 0x0 | Enable Direct Access Controller
66 * [8] | RW | 0x0 | Legacy IP Mode Enable
67 * [9] | RW | 0x0 | Peripheral select decode
68 * [13:10] | RW | 0x0 | Peripheral Chip Select Lines
69 * [14] | RW | 0x0 | Write Protect Flash Pin
70 * [15] | RW | 0x0 | Enable DMA Peripheral Interface
71 * [16] | RW | 0x0 | Enable AHB Address Re-mapping
72 * [17] | RW | 0x0 | Enter XIP Mode on next READ
73 * [18] | RW | 0x0 | Enter XIP Mode Immediately
74 * [22:19] | RW | 0xf | Master Mode Baud Rate Divisor
75 * [30:23] | ??? | 0x0 | *UNDEFINED*
76 * [31] | R | 0x0 | Serial interface and QSPI pipeline is IDLE
77 *
78 */
79/*
80 * Field : QSPI Enable - en
81 *
82 * If this bit is disabled, the QSPI will finish the current transfer of the data
83 * word (FF_W) and stop sending. When Enabled, and qspi_n_mo_en = 0, all output
84 * enables are inactive and all pins are set to input mode.
85 *
86 * Field Enumeration Values:
87 *
88 * Enum | Value | Description
89 * :----------------------|:------|:-----------------
90 * ALT_QSPI_CFG_EN_E_DIS | 0x0 | Disable the QSPI
91 * ALT_QSPI_CFG_EN_E_EN | 0x1 | Enable the QSPI
92 *
93 * Field Access Macros:
94 *
95 */
96/*
97 * Enumerated value for register field ALT_QSPI_CFG_EN
98 *
99 * Disable the QSPI
100 */
101#define ALT_QSPI_CFG_EN_E_DIS 0x0
102/*
103 * Enumerated value for register field ALT_QSPI_CFG_EN
104 *
105 * Enable the QSPI
106 */
107#define ALT_QSPI_CFG_EN_E_EN 0x1
108
109/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_EN register field. */
110#define ALT_QSPI_CFG_EN_LSB 0
111/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_EN register field. */
112#define ALT_QSPI_CFG_EN_MSB 0
113/* The width in bits of the ALT_QSPI_CFG_EN register field. */
114#define ALT_QSPI_CFG_EN_WIDTH 1
115/* The mask used to set the ALT_QSPI_CFG_EN register field value. */
116#define ALT_QSPI_CFG_EN_SET_MSK 0x00000001
117/* The mask used to clear the ALT_QSPI_CFG_EN register field value. */
118#define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe
119/* The reset value of the ALT_QSPI_CFG_EN register field. */
120#define ALT_QSPI_CFG_EN_RESET 0x0
121/* Extracts the ALT_QSPI_CFG_EN field value from a register. */
122#define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0)
123/* Produces a ALT_QSPI_CFG_EN register field value suitable for setting the register. */
124#define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001)
125
126/*
127 * Field : Clock Polarity - selclkpol
128 *
129 * Controls spiclk modes of operation.
130 *
131 * Field Enumeration Values:
132 *
133 * Enum | Value | Description
134 * :------------------------------|:------|:----------------------------
135 * ALT_QSPI_CFG_SELCLKPOL_E_LOW | 0x1 | SPI clock is quiescent low
136 * ALT_QSPI_CFG_SELCLKPOL_E_HIGH | 0x0 | SPI clock is quiescent high
137 *
138 * Field Access Macros:
139 *
140 */
141/*
142 * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL
143 *
144 * SPI clock is quiescent low
145 */
146#define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1
147/*
148 * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL
149 *
150 * SPI clock is quiescent high
151 */
152#define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0
153
154/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */
155#define ALT_QSPI_CFG_SELCLKPOL_LSB 1
156/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */
157#define ALT_QSPI_CFG_SELCLKPOL_MSB 1
158/* The width in bits of the ALT_QSPI_CFG_SELCLKPOL register field. */
159#define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1
160/* The mask used to set the ALT_QSPI_CFG_SELCLKPOL register field value. */
161#define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002
162/* The mask used to clear the ALT_QSPI_CFG_SELCLKPOL register field value. */
163#define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd
164/* The reset value of the ALT_QSPI_CFG_SELCLKPOL register field. */
165#define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0
166/* Extracts the ALT_QSPI_CFG_SELCLKPOL field value from a register. */
167#define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1)
168/* Produces a ALT_QSPI_CFG_SELCLKPOL register field value suitable for setting the register. */
169#define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002)
170
171/*
172 * Field : Select Clock Phase - selclkphase
173 *
174 * Selects whether the clock is in an active or inactive phase outside the SPI
175 * word.
176 *
177 * Field Enumeration Values:
178 *
179 * Enum | Value | Description
180 * :---------------------------------|:------|:---------------------------
181 * ALT_QSPI_CFG_SELCLKPHASE_E_ACT | 0x0 | SPI clock is quiescent low
182 * ALT_QSPI_CFG_SELCLKPHASE_E_INACT | 0x1 | Clock Inactive
183 *
184 * Field Access Macros:
185 *
186 */
187/*
188 * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE
189 *
190 * SPI clock is quiescent low
191 */
192#define ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0
193/*
194 * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE
195 *
196 * Clock Inactive
197 */
198#define ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1
199
200/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */
201#define ALT_QSPI_CFG_SELCLKPHASE_LSB 2
202/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */
203#define ALT_QSPI_CFG_SELCLKPHASE_MSB 2
204/* The width in bits of the ALT_QSPI_CFG_SELCLKPHASE register field. */
205#define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1
206/* The mask used to set the ALT_QSPI_CFG_SELCLKPHASE register field value. */
207#define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004
208/* The mask used to clear the ALT_QSPI_CFG_SELCLKPHASE register field value. */
209#define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb
210/* The reset value of the ALT_QSPI_CFG_SELCLKPHASE register field. */
211#define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0
212/* Extracts the ALT_QSPI_CFG_SELCLKPHASE field value from a register. */
213#define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2)
214/* Produces a ALT_QSPI_CFG_SELCLKPHASE register field value suitable for setting the register. */
215#define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004)
216
217/*
218 * Field : Enable Direct Access Controller - endiracc
219 *
220 * If disabled, the Direct Access Controller becomes inactive once the current
221 * transfer of the data word (FF_W) is complete. When the Direct Access Controller
222 * and Indirect Access Controller are both disabled, all AHB requests are completed
223 * with an error response.
224 *
225 * Field Enumeration Values:
226 *
227 * Enum | Value | Description
228 * :----------------------------|:------|:---------------------------
229 * ALT_QSPI_CFG_ENDIRACC_E_DIS | 0x0 | Disable Direct Access Ctrl
230 * ALT_QSPI_CFG_ENDIRACC_E_EN | 0x1 | Enable Direct Access Ctrl
231 *
232 * Field Access Macros:
233 *
234 */
235/*
236 * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC
237 *
238 * Disable Direct Access Ctrl
239 */
240#define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0
241/*
242 * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC
243 *
244 * Enable Direct Access Ctrl
245 */
246#define ALT_QSPI_CFG_ENDIRACC_E_EN 0x1
247
248/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */
249#define ALT_QSPI_CFG_ENDIRACC_LSB 7
250/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */
251#define ALT_QSPI_CFG_ENDIRACC_MSB 7
252/* The width in bits of the ALT_QSPI_CFG_ENDIRACC register field. */
253#define ALT_QSPI_CFG_ENDIRACC_WIDTH 1
254/* The mask used to set the ALT_QSPI_CFG_ENDIRACC register field value. */
255#define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080
256/* The mask used to clear the ALT_QSPI_CFG_ENDIRACC register field value. */
257#define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f
258/* The reset value of the ALT_QSPI_CFG_ENDIRACC register field. */
259#define ALT_QSPI_CFG_ENDIRACC_RESET 0x0
260/* Extracts the ALT_QSPI_CFG_ENDIRACC field value from a register. */
261#define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7)
262/* Produces a ALT_QSPI_CFG_ENDIRACC register field value suitable for setting the register. */
263#define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080)
264
265/*
266 * Field : Legacy IP Mode Enable - enlegacyip
267 *
268 * This bit can select the Direct Access Controller/Indirect Access Controller or
269 * legacy mode.If legacy mode is selected, any write to the controller via the AHB
270 * interface is serialized and sent to the FLASH device. Any valid AHB read will
271 * pop the internal RX-FIFO, retrieving data that was forwarded by the external
272 * FLASH device on the SPI lines, byte transfers of 4, 2 or 1 are permitted and
273 * controlled via the HSIZE input.
274 *
275 * Field Enumeration Values:
276 *
277 * Enum | Value | Description
278 * :---------------------------------|:------|:--------------------------------------
279 * ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD | 0x1 | Legacy Mode
280 * ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD | 0x0 | Use Direct/Indirect Access Controller
281 *
282 * Field Access Macros:
283 *
284 */
285/*
286 * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP
287 *
288 * Legacy Mode
289 */
290#define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1
291/*
292 * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP
293 *
294 * Use Direct/Indirect Access Controller
295 */
296#define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0
297
298/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */
299#define ALT_QSPI_CFG_ENLEGACYIP_LSB 8
300/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */
301#define ALT_QSPI_CFG_ENLEGACYIP_MSB 8
302/* The width in bits of the ALT_QSPI_CFG_ENLEGACYIP register field. */
303#define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1
304/* The mask used to set the ALT_QSPI_CFG_ENLEGACYIP register field value. */
305#define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100
306/* The mask used to clear the ALT_QSPI_CFG_ENLEGACYIP register field value. */
307#define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff
308/* The reset value of the ALT_QSPI_CFG_ENLEGACYIP register field. */
309#define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0
310/* Extracts the ALT_QSPI_CFG_ENLEGACYIP field value from a register. */
311#define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8)
312/* Produces a ALT_QSPI_CFG_ENLEGACYIP register field value suitable for setting the register. */
313#define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100)
314
315/*
316 * Field : Peripheral select decode - perseldec
317 *
318 * Select between '1 of 4 selects' or 'external 4-to-16 decode'. The
319 * qspi_n_ss_out[3:0] output signals are controlled.
320 *
321 * Field Enumeration Values:
322 *
323 * Enum | Value | Description
324 * :----------------------------------|:------|:----------------------------------
325 * ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 | 0x1 | Select external 4-to-16 decode
326 * ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 | 0x0 | Selects 1 of 4 qspi_n_ss_out[3:0]
327 *
328 * Field Access Macros:
329 *
330 */
331/*
332 * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC
333 *
334 * Select external 4-to-16 decode
335 */
336#define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1
337/*
338 * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC
339 *
340 * Selects 1 of 4 qspi_n_ss_out[3:0]
341 */
342#define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0
343
344/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */
345#define ALT_QSPI_CFG_PERSELDEC_LSB 9
346/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */
347#define ALT_QSPI_CFG_PERSELDEC_MSB 9
348/* The width in bits of the ALT_QSPI_CFG_PERSELDEC register field. */
349#define ALT_QSPI_CFG_PERSELDEC_WIDTH 1
350/* The mask used to set the ALT_QSPI_CFG_PERSELDEC register field value. */
351#define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200
352/* The mask used to clear the ALT_QSPI_CFG_PERSELDEC register field value. */
353#define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff
354/* The reset value of the ALT_QSPI_CFG_PERSELDEC register field. */
355#define ALT_QSPI_CFG_PERSELDEC_RESET 0x0
356/* Extracts the ALT_QSPI_CFG_PERSELDEC field value from a register. */
357#define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9)
358/* Produces a ALT_QSPI_CFG_PERSELDEC register field value suitable for setting the register. */
359#define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200)
360
361/*
362 * Field : Peripheral Chip Select Lines - percslines
363 *
364 * Peripheral chip select line output decode type. As per perseldec, if perseldec =
365 * 0, the decode is select 1 of 4 decoding on signals, qspi_n_ss_out[3:0], The
366 * asserted decode line goes to 0. If perseldec = 1, the signals qspi_n_ss_out[3:0]
367 * require an external 4 to 16 decoder.
368 *
369 * Field Access Macros:
370 *
371 */
372/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */
373#define ALT_QSPI_CFG_PERCSLINES_LSB 10
374/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */
375#define ALT_QSPI_CFG_PERCSLINES_MSB 13
376/* The width in bits of the ALT_QSPI_CFG_PERCSLINES register field. */
377#define ALT_QSPI_CFG_PERCSLINES_WIDTH 4
378/* The mask used to set the ALT_QSPI_CFG_PERCSLINES register field value. */
379#define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00
380/* The mask used to clear the ALT_QSPI_CFG_PERCSLINES register field value. */
381#define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff
382/* The reset value of the ALT_QSPI_CFG_PERCSLINES register field. */
383#define ALT_QSPI_CFG_PERCSLINES_RESET 0x0
384/* Extracts the ALT_QSPI_CFG_PERCSLINES field value from a register. */
385#define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10)
386/* Produces a ALT_QSPI_CFG_PERCSLINES register field value suitable for setting the register. */
387#define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00)
388
389/*
390 * Field : Write Protect Flash Pin - wp
391 *
392 * This bit controls the write protect pin of the flash devices. The signal
393 * qspi_mo2_wpn needs to be resynchronized to the generated memory clock as
394 * necessary.
395 *
396 * Field Enumeration Values:
397 *
398 * Enum | Value | Description
399 * :-----------------------------|:------|:----------------------
400 * ALT_QSPI_CFG_WP_E_WRPROTON | 0x1 | Enable Write Protect
401 * ALT_QSPI_CFG_WP_E_WRTPROTOFF | 0x0 | Disable Write Protect
402 *
403 * Field Access Macros:
404 *
405 */
406/*
407 * Enumerated value for register field ALT_QSPI_CFG_WP
408 *
409 * Enable Write Protect
410 */
411#define ALT_QSPI_CFG_WP_E_WRPROTON 0x1
412/*
413 * Enumerated value for register field ALT_QSPI_CFG_WP
414 *
415 * Disable Write Protect
416 */
417#define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0
418
419/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_WP register field. */
420#define ALT_QSPI_CFG_WP_LSB 14
421/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_WP register field. */
422#define ALT_QSPI_CFG_WP_MSB 14
423/* The width in bits of the ALT_QSPI_CFG_WP register field. */
424#define ALT_QSPI_CFG_WP_WIDTH 1
425/* The mask used to set the ALT_QSPI_CFG_WP register field value. */
426#define ALT_QSPI_CFG_WP_SET_MSK 0x00004000
427/* The mask used to clear the ALT_QSPI_CFG_WP register field value. */
428#define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff
429/* The reset value of the ALT_QSPI_CFG_WP register field. */
430#define ALT_QSPI_CFG_WP_RESET 0x0
431/* Extracts the ALT_QSPI_CFG_WP field value from a register. */
432#define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14)
433/* Produces a ALT_QSPI_CFG_WP register field value suitable for setting the register. */
434#define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000)
435
436/*
437 * Field : Enable DMA Peripheral Interface - endma
438 *
439 * Allows DMA handshaking mode. When enabled the QSPI will trigger DMA transfer
440 * requests via the DMA peripheral interface.
441 *
442 * Field Enumeration Values:
443 *
444 * Enum | Value | Description
445 * :-------------------------|:------|:-----------------
446 * ALT_QSPI_CFG_ENDMA_E_EN | 0x1 | Enable DMA Mode
447 * ALT_QSPI_CFG_ENDMA_E_DIS | 0x0 | Disable DMA Mode
448 *
449 * Field Access Macros:
450 *
451 */
452/*
453 * Enumerated value for register field ALT_QSPI_CFG_ENDMA
454 *
455 * Enable DMA Mode
456 */
457#define ALT_QSPI_CFG_ENDMA_E_EN 0x1
458/*
459 * Enumerated value for register field ALT_QSPI_CFG_ENDMA
460 *
461 * Disable DMA Mode
462 */
463#define ALT_QSPI_CFG_ENDMA_E_DIS 0x0
464
465/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDMA register field. */
466#define ALT_QSPI_CFG_ENDMA_LSB 15
467/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDMA register field. */
468#define ALT_QSPI_CFG_ENDMA_MSB 15
469/* The width in bits of the ALT_QSPI_CFG_ENDMA register field. */
470#define ALT_QSPI_CFG_ENDMA_WIDTH 1
471/* The mask used to set the ALT_QSPI_CFG_ENDMA register field value. */
472#define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000
473/* The mask used to clear the ALT_QSPI_CFG_ENDMA register field value. */
474#define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff
475/* The reset value of the ALT_QSPI_CFG_ENDMA register field. */
476#define ALT_QSPI_CFG_ENDMA_RESET 0x0
477/* Extracts the ALT_QSPI_CFG_ENDMA field value from a register. */
478#define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15)
479/* Produces a ALT_QSPI_CFG_ENDMA register field value suitable for setting the register. */
480#define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000)
481
482/*
483 * Field : Enable AHB Address Re-mapping - enahbremap
484 *
485 * (Direct Access Mode Only) When enabled, the incoming AHB address will be adapted
486 * and sent to the FLASH device as (address + N), where N is the value stored in
487 * the remap address register.
488 *
489 * Field Enumeration Values:
490 *
491 * Enum | Value | Description
492 * :------------------------------|:------|:-----------------------
493 * ALT_QSPI_CFG_ENAHBREMAP_E_EN | 0x1 | Enable AHB Re-mapping
494 * ALT_QSPI_CFG_ENAHBREMAP_E_DIS | 0x0 | Disable AHB Re-mapping
495 *
496 * Field Access Macros:
497 *
498 */
499/*
500 * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP
501 *
502 * Enable AHB Re-mapping
503 */
504#define ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1
505/*
506 * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP
507 *
508 * Disable AHB Re-mapping
509 */
510#define ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0
511
512/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */
513#define ALT_QSPI_CFG_ENAHBREMAP_LSB 16
514/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */
515#define ALT_QSPI_CFG_ENAHBREMAP_MSB 16
516/* The width in bits of the ALT_QSPI_CFG_ENAHBREMAP register field. */
517#define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1
518/* The mask used to set the ALT_QSPI_CFG_ENAHBREMAP register field value. */
519#define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000
520/* The mask used to clear the ALT_QSPI_CFG_ENAHBREMAP register field value. */
521#define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff
522/* The reset value of the ALT_QSPI_CFG_ENAHBREMAP register field. */
523#define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0
524/* Extracts the ALT_QSPI_CFG_ENAHBREMAP field value from a register. */
525#define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16)
526/* Produces a ALT_QSPI_CFG_ENAHBREMAP register field value suitable for setting the register. */
527#define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000)
528
529/*
530 * Field : Enter XIP Mode on next READ - enterxipnextrd
531 *
532 * If XIP is enabled, then setting to disabled will cause the controller to exit
533 * XIP mode on the next READ instruction. If XIP is disabled, then setting to
534 * enabled will inform the controller that the device is ready to enter XIP on the
535 * next READ instruction. The controller will therefore send the appropriate
536 * command sequence, including mode bits to cause the device to enter XIP mode. Use
537 * this register after the controller has ensured the FLASH device has been
538 * configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit
539 * should be set to 0. This will take effect in the attached device only AFTER the
540 * next READ instruction is executed. Software should therefore ensure that at
541 * least one READ instruction is requested after resetting this bit before it can
542 * be sure XIP mode in the device is exited.
543 *
544 * Field Enumeration Values:
545 *
546 * Enum | Value | Description
547 * :----------------------------------|:------|:----------------------------------------
548 * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN | 0x1 | Enter XIP Mode on next READ instruction
549 * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS | 0x0 | Exit XIP Mode on next READ instruction
550 *
551 * Field Access Macros:
552 *
553 */
554/*
555 * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD
556 *
557 * Enter XIP Mode on next READ instruction
558 */
559#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1
560/*
561 * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD
562 *
563 * Exit XIP Mode on next READ instruction
564 */
565#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0
566
567/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
568#define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17
569/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
570#define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17
571/* The width in bits of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
572#define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1
573/* The mask used to set the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */
574#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000
575/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */
576#define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff
577/* The reset value of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
578#define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0
579/* Extracts the ALT_QSPI_CFG_ENTERXIPNEXTRD field value from a register. */
580#define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17)
581/* Produces a ALT_QSPI_CFG_ENTERXIPNEXTRD register field value suitable for setting the register. */
582#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000)
583
584/*
585 * Field : Enter XIP Mode Immediately - enterxipimm
586 *
587 * If XIP is enabled, then setting to disabled will cause the controller to exit
588 * XIP mode on the next READ instruction. If XIP is disabled, then setting enable
589 * will operate the device in XIP mode immediately. Use this register when the
590 * external device wakes up in XIP mode (as per the contents of its non- volatile
591 * configuration register). The controller will assume the next READ instruction
592 * will be passed to the device as an XIP instruction, and therefore will not
593 * require the READ opcode to be transferred. Note: To exit XIP mode, this bit
594 * should be set to 0. This will take effect in the attached device only after the
595 * next READ instruction is executed. Software therefore should ensure that at
596 * least one READ instruction is requested after resetting this bit in order to be
597 * sure that XIP mode is exited.
598 *
599 * Field Enumeration Values:
600 *
601 * Enum | Value | Description
602 * :-------------------------------|:------|:---------------------------------------
603 * ALT_QSPI_CFG_ENTERXIPIMM_E_EN | 0x1 | Enter XIP Mode immediately
604 * ALT_QSPI_CFG_ENTERXIPIMM_E_DIS | 0x0 | Exit XIP Mode on next READ instruction
605 *
606 * Field Access Macros:
607 *
608 */
609/*
610 * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM
611 *
612 * Enter XIP Mode immediately
613 */
614#define ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1
615/*
616 * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM
617 *
618 * Exit XIP Mode on next READ instruction
619 */
620#define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0
621
622/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
623#define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18
624/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
625#define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18
626/* The width in bits of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
627#define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1
628/* The mask used to set the ALT_QSPI_CFG_ENTERXIPIMM register field value. */
629#define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000
630/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPIMM register field value. */
631#define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff
632/* The reset value of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
633#define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0
634/* Extracts the ALT_QSPI_CFG_ENTERXIPIMM field value from a register. */
635#define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18)
636/* Produces a ALT_QSPI_CFG_ENTERXIPIMM register field value suitable for setting the register. */
637#define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000)
638
639/*
640 * Field : Master Mode Baud Rate Divisor - bauddiv
641 *
642 * SPI baud rate = ref_clk / (2 * baud_rate_divisor)
643 *
644 * Field Enumeration Values:
645 *
646 * Enum | Value | Description
647 * :------------------------------|:------|:-----------------
648 * ALT_QSPI_CFG_BAUDDIV_E_BAUD2 | 0x0 | Baud Rate Div/2
649 * ALT_QSPI_CFG_BAUDDIV_E_BAUD4 | 0x1 | Baud Rate Div/4
650 * ALT_QSPI_CFG_BAUDDIV_E_BAUD6 | 0x2 | Baud Rate Div/6
651 * ALT_QSPI_CFG_BAUDDIV_E_BAUD8 | 0x3 | Baud Rate Div/8
652 * ALT_QSPI_CFG_BAUDDIV_E_BAUD10 | 0x4 | Baud Rate Div/10
653 * ALT_QSPI_CFG_BAUDDIV_E_BAUD12 | 0x5 | Baud Rate Div/12
654 * ALT_QSPI_CFG_BAUDDIV_E_BAUD14 | 0x6 | Baud Rate Div/14
655 * ALT_QSPI_CFG_BAUDDIV_E_BAUD16 | 0x7 | Baud Rate Div/16
656 * ALT_QSPI_CFG_BAUDDIV_E_BAUD18 | 0x8 | Baud Rate Div/18
657 * ALT_QSPI_CFG_BAUDDIV_E_BAUD20 | 0x9 | Baud Rate Div/20
658 * ALT_QSPI_CFG_BAUDDIV_E_BAUD22 | 0xa | Baud Rate Div/22
659 * ALT_QSPI_CFG_BAUDDIV_E_BAUD24 | 0xb | Baud Rate Div/24
660 * ALT_QSPI_CFG_BAUDDIV_E_BAUD26 | 0xc | Baud Rate Div/26
661 * ALT_QSPI_CFG_BAUDDIV_E_BAUD28 | 0xd | Baud Rate Div/28
662 * ALT_QSPI_CFG_BAUDDIV_E_BAUD30 | 0xe | Baud Rate Div/30
663 * ALT_QSPI_CFG_BAUDDIV_E_BAUD32 | 0xf | Baud Rate Div/32
664 *
665 * Field Access Macros:
666 *
667 */
668/*
669 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
670 *
671 * Baud Rate Div/2
672 */
673#define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0
674/*
675 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
676 *
677 * Baud Rate Div/4
678 */
679#define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1
680/*
681 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
682 *
683 * Baud Rate Div/6
684 */
685#define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2
686/*
687 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
688 *
689 * Baud Rate Div/8
690 */
691#define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3
692/*
693 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
694 *
695 * Baud Rate Div/10
696 */
697#define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4
698/*
699 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
700 *
701 * Baud Rate Div/12
702 */
703#define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5
704/*
705 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
706 *
707 * Baud Rate Div/14
708 */
709#define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6
710/*
711 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
712 *
713 * Baud Rate Div/16
714 */
715#define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7
716/*
717 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
718 *
719 * Baud Rate Div/18
720 */
721#define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8
722/*
723 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
724 *
725 * Baud Rate Div/20
726 */
727#define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9
728/*
729 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
730 *
731 * Baud Rate Div/22
732 */
733#define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa
734/*
735 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
736 *
737 * Baud Rate Div/24
738 */
739#define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb
740/*
741 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
742 *
743 * Baud Rate Div/26
744 */
745#define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc
746/*
747 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
748 *
749 * Baud Rate Div/28
750 */
751#define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd
752/*
753 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
754 *
755 * Baud Rate Div/30
756 */
757#define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe
758/*
759 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
760 *
761 * Baud Rate Div/32
762 */
763#define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf
764
765/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */
766#define ALT_QSPI_CFG_BAUDDIV_LSB 19
767/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */
768#define ALT_QSPI_CFG_BAUDDIV_MSB 22
769/* The width in bits of the ALT_QSPI_CFG_BAUDDIV register field. */
770#define ALT_QSPI_CFG_BAUDDIV_WIDTH 4
771/* The mask used to set the ALT_QSPI_CFG_BAUDDIV register field value. */
772#define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000
773/* The mask used to clear the ALT_QSPI_CFG_BAUDDIV register field value. */
774#define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff
775/* The reset value of the ALT_QSPI_CFG_BAUDDIV register field. */
776#define ALT_QSPI_CFG_BAUDDIV_RESET 0xf
777/* Extracts the ALT_QSPI_CFG_BAUDDIV field value from a register. */
778#define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19)
779/* Produces a ALT_QSPI_CFG_BAUDDIV register field value suitable for setting the register. */
780#define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000)
781
782/*
783 * Field : Serial interface and QSPI pipeline is IDLE - idle
784 *
785 * This is a STATUS read-only bit. Note this is a retimed signal, so there will be
786 * some inherent delay on the generation of this status signal.
787 *
788 * Field Enumeration Values:
789 *
790 * Enum | Value | Description
791 * :---------------------------|:------|:--------------
792 * ALT_QSPI_CFG_IDLE_E_SET | 0x1 | Idle Mode
793 * ALT_QSPI_CFG_IDLE_E_NOTSET | 0x0 | Non-Idle Mode
794 *
795 * Field Access Macros:
796 *
797 */
798/*
799 * Enumerated value for register field ALT_QSPI_CFG_IDLE
800 *
801 * Idle Mode
802 */
803#define ALT_QSPI_CFG_IDLE_E_SET 0x1
804/*
805 * Enumerated value for register field ALT_QSPI_CFG_IDLE
806 *
807 * Non-Idle Mode
808 */
809#define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0
810
811/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_IDLE register field. */
812#define ALT_QSPI_CFG_IDLE_LSB 31
813/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_IDLE register field. */
814#define ALT_QSPI_CFG_IDLE_MSB 31
815/* The width in bits of the ALT_QSPI_CFG_IDLE register field. */
816#define ALT_QSPI_CFG_IDLE_WIDTH 1
817/* The mask used to set the ALT_QSPI_CFG_IDLE register field value. */
818#define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000
819/* The mask used to clear the ALT_QSPI_CFG_IDLE register field value. */
820#define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff
821/* The reset value of the ALT_QSPI_CFG_IDLE register field. */
822#define ALT_QSPI_CFG_IDLE_RESET 0x0
823/* Extracts the ALT_QSPI_CFG_IDLE field value from a register. */
824#define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31)
825/* Produces a ALT_QSPI_CFG_IDLE register field value suitable for setting the register. */
826#define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000)
827
828#ifndef __ASSEMBLY__
829/*
830 * WARNING: The C register and register group struct declarations are provided for
831 * convenience and illustrative purposes. They should, however, be used with
832 * caution as the C language standard provides no guarantees about the alignment or
833 * atomicity of device memory accesses. The recommended practice for writing
834 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
835 * alt_write_word() functions.
836 *
837 * The struct declaration for register ALT_QSPI_CFG.
838 */
839 struct ALT_QSPI_CFG_s
840{
841 uint32_t en : 1; /* QSPI Enable */
842 uint32_t selclkpol : 1; /* Clock Polarity */
843 uint32_t selclkphase : 1; /* Select Clock Phase */
844 uint32_t : 4; /* *UNDEFINED* */
845 uint32_t endiracc : 1; /* Enable Direct Access Controller */
846 uint32_t enlegacyip : 1; /* Legacy IP Mode Enable */
847 uint32_t perseldec : 1; /* Peripheral select decode */
848 uint32_t percslines : 4; /* Peripheral Chip Select Lines */
849 uint32_t wp : 1; /* Write Protect Flash Pin */
850 uint32_t endma : 1; /* Enable DMA Peripheral Interface */
851 uint32_t enahbremap : 1; /* Enable AHB Address Re-mapping */
852 uint32_t enterxipnextrd : 1; /* Enter XIP Mode on next READ */
853 uint32_t enterxipimm : 1; /* Enter XIP Mode Immediately */
854 uint32_t bauddiv : 4; /* Master Mode Baud Rate Divisor */
855 uint32_t : 8; /* *UNDEFINED* */
856 const uint32_t idle : 1; /* Serial interface and QSPI pipeline is IDLE */
857};
858
859/* The typedef declaration for register ALT_QSPI_CFG. */
860typedef volatile struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t;
861#endif /* __ASSEMBLY__ */
862
863/* The byte offset of the ALT_QSPI_CFG register from the beginning of the component. */
864#define ALT_QSPI_CFG_OFST 0x0
865
866/*
867 * Register : Device Read Instruction Register - devrd
868 *
869 * Register Layout
870 *
871 * Bits | Access | Reset | Description
872 * :--------|:-------|:------|:----------------------------
873 * [7:0] | RW | 0x3 | Read Opcode in non-XIP mode
874 * [9:8] | RW | 0x0 | Instruction Transfer Width
875 * [11:10] | ??? | 0x0 | *UNDEFINED*
876 * [13:12] | RW | 0x0 | Address Transfer Width
877 * [15:14] | ??? | 0x0 | *UNDEFINED*
878 * [17:16] | RW | 0x0 | Data Transfer Width
879 * [19:18] | ??? | 0x0 | *UNDEFINED*
880 * [20] | RW | 0x0 | Mode Bit Enable
881 * [23:21] | ??? | 0x0 | *UNDEFINED*
882 * [28:24] | RW | 0x0 | Dummy Read Clock Cycles
883 * [31:29] | ??? | 0x0 | *UNDEFINED*
884 *
885 */
886/*
887 * Field : Read Opcode in non-XIP mode - rdopcode
888 *
889 * Read Opcode to use when not in XIP mode
890 *
891 * Field Enumeration Values:
892 *
893 * Enum | Value | Description
894 * :---------------------------------|:------|:----------------------------
895 * ALT_QSPI_DEVRD_RDOPCODE_E_RD | 0x3 | Read Opcode in Non-XIP mode
896 * ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD | 0xb | Fast Read in Non-XIP mode
897 *
898 * Field Access Macros:
899 *
900 */
901/*
902 * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE
903 *
904 * Read Opcode in Non-XIP mode
905 */
906#define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3
907/*
908 * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE
909 *
910 * Fast Read in Non-XIP mode
911 */
912#define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb
913
914/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */
915#define ALT_QSPI_DEVRD_RDOPCODE_LSB 0
916/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */
917#define ALT_QSPI_DEVRD_RDOPCODE_MSB 7
918/* The width in bits of the ALT_QSPI_DEVRD_RDOPCODE register field. */
919#define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8
920/* The mask used to set the ALT_QSPI_DEVRD_RDOPCODE register field value. */
921#define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff
922/* The mask used to clear the ALT_QSPI_DEVRD_RDOPCODE register field value. */
923#define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00
924/* The reset value of the ALT_QSPI_DEVRD_RDOPCODE register field. */
925#define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3
926/* Extracts the ALT_QSPI_DEVRD_RDOPCODE field value from a register. */
927#define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0)
928/* Produces a ALT_QSPI_DEVRD_RDOPCODE register field value suitable for setting the register. */
929#define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff)
930
931/*
932 * Field : Instruction Transfer Width - instwidth
933 *
934 * Sets instruction transfer width (1, 2, or 4 bits). Applies to all instructions
935 * sent to SPI flash device (not just read instructions).
936 *
937 * Field Enumeration Values:
938 *
939 * Enum | Value | Description
940 * :----------------------------------|:------|:-------------------------------------------------
941 * ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE | 0x0 | Instruction transferred on DQ0. Supported by all
942 * : | | SPI flash devices.
943 * ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL | 0x1 | Instruction transferred on DQ0 and DQ1.
944 * : | | Supported by all SPI flash devices that support
945 * : | | the Dual SP (DIO-SPI) Protocol.
946 * ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD | 0x2 | Instruction transferred on DQ0, DQ1, DQ2, and
947 * : | | DQ3. Supported by all SPI flash devices that
948 * : | | support the Quad SP (QIO-SPI) Protocol.
949 *
950 * Field Access Macros:
951 *
952 */
953/*
954 * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
955 *
956 * Instruction transferred on DQ0. Supported by all SPI flash devices.
957 */
958#define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0
959/*
960 * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
961 *
962 * Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that
963 * support the Dual SP (DIO-SPI) Protocol.
964 */
965#define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1
966/*
967 * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
968 *
969 * Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash
970 * devices that support the Quad SP (QIO-SPI) Protocol.
971 */
972#define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2
973
974/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
975#define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8
976/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
977#define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9
978/* The width in bits of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
979#define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2
980/* The mask used to set the ALT_QSPI_DEVRD_INSTWIDTH register field value. */
981#define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300
982/* The mask used to clear the ALT_QSPI_DEVRD_INSTWIDTH register field value. */
983#define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff
984/* The reset value of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
985#define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0
986/* Extracts the ALT_QSPI_DEVRD_INSTWIDTH field value from a register. */
987#define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8)
988/* Produces a ALT_QSPI_DEVRD_INSTWIDTH register field value suitable for setting the register. */
989#define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300)
990
991/*
992 * Field : Address Transfer Width - addrwidth
993 *
994 * Sets read address transfer width (1, 2, or 4 bits).
995 *
996 * Field Enumeration Values:
997 *
998 * Enum | Value | Description
999 * :----------------------------------|:------|:-------------------------------------------------
1000 * ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE | 0x0 | Read address transferred on DQ0. Supported by
1001 * : | | all SPI flash devices
1002 * ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1.
1003 * : | | Supported by some SPI flash devices that support
1004 * : | | the Extended SPI Protocol and by all SPI flash
1005 * : | | devices that support the Dual SP (DIO-SPI)
1006 * : | | Protocol.
1007 * ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and
1008 * : | | DQ3. Supported by some SPI flash devices that
1009 * : | | support the Extended SPI Protocol and by all SPI
1010 * : | | flash devices that support the Quad SP (QIO-SPI)
1011 * : | | Protocol.
1012 *
1013 * Field Access Macros:
1014 *
1015 */
1016/*
1017 * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
1018 *
1019 * Read address transferred on DQ0. Supported by all SPI flash devices
1020 */
1021#define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0
1022/*
1023 * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
1024 *
1025 * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices
1026 * that support the Extended SPI Protocol and by all SPI flash devices that support
1027 * the Dual SP (DIO-SPI) Protocol.
1028 */
1029#define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1
1030/*
1031 * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
1032 *
1033 * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1034 * devices that support the Extended SPI Protocol and by all SPI flash devices that
1035 * support the Quad SP (QIO-SPI) Protocol.
1036 */
1037#define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2
1038
1039/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1040#define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12
1041/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1042#define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13
1043/* The width in bits of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1044#define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2
1045/* The mask used to set the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */
1046#define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000
1047/* The mask used to clear the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */
1048#define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff
1049/* The reset value of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1050#define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0
1051/* Extracts the ALT_QSPI_DEVRD_ADDRWIDTH field value from a register. */
1052#define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1053/* Produces a ALT_QSPI_DEVRD_ADDRWIDTH register field value suitable for setting the register. */
1054#define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1055
1056/*
1057 * Field : Data Transfer Width - datawidth
1058 *
1059 * Sets read data transfer width (1, 2, or 4 bits).
1060 *
1061 * Field Enumeration Values:
1062 *
1063 * Enum | Value | Description
1064 * :----------------------------------|:------|:-------------------------------------------------
1065 * ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE | 0x0 | Read data transferred on DQ0. Supported by all
1066 * : | | SPI flash devices
1067 * ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported
1068 * : | | by some SPI flash devices that support the
1069 * : | | Extended SPI Protocol and by all SPI flash
1070 * : | | devices that support the Dual SP (DIO-SPI)
1071 * : | | Protocol.
1072 * ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3.
1073 * : | | Supported by some SPI flash devices that support
1074 * : | | the Extended SPI Protocol and by all SPI flash
1075 * : | | devices that support the Quad SP (QIO-SPI)
1076 * : | | Protocol.
1077 *
1078 * Field Access Macros:
1079 *
1080 */
1081/*
1082 * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
1083 *
1084 * Read data transferred on DQ0. Supported by all SPI flash devices
1085 */
1086#define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0
1087/*
1088 * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
1089 *
1090 * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that
1091 * support the Extended SPI Protocol and by all SPI flash devices that support the
1092 * Dual SP (DIO-SPI) Protocol.
1093 */
1094#define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1
1095/*
1096 * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
1097 *
1098 * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1099 * devices that support the Extended SPI Protocol and by all SPI flash devices that
1100 * support the Quad SP (QIO-SPI) Protocol.
1101 */
1102#define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2
1103
1104/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1105#define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16
1106/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1107#define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17
1108/* The width in bits of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1109#define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2
1110/* The mask used to set the ALT_QSPI_DEVRD_DATAWIDTH register field value. */
1111#define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000
1112/* The mask used to clear the ALT_QSPI_DEVRD_DATAWIDTH register field value. */
1113#define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff
1114/* The reset value of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1115#define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0
1116/* Extracts the ALT_QSPI_DEVRD_DATAWIDTH field value from a register. */
1117#define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1118/* Produces a ALT_QSPI_DEVRD_DATAWIDTH register field value suitable for setting the register. */
1119#define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1120
1121/*
1122 * Field : Mode Bit Enable - enmodebits
1123 *
1124 * If this bit is set, the mode bits as defined in the Mode Bit Configuration
1125 * register are sent following the address bytes.
1126 *
1127 * Field Enumeration Values:
1128 *
1129 * Enum | Value | Description
1130 * :-----------------------------------|:------|:-------------------------------
1131 * ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER | 0x0 | No Order
1132 * ALT_QSPI_DEVRD_ENMODBITS_E_ORDER | 0x1 | Mode Bits follow address bytes
1133 *
1134 * Field Access Macros:
1135 *
1136 */
1137/*
1138 * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS
1139 *
1140 * No Order
1141 */
1142#define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0
1143/*
1144 * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS
1145 *
1146 * Mode Bits follow address bytes
1147 */
1148#define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1
1149
1150/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */
1151#define ALT_QSPI_DEVRD_ENMODBITS_LSB 20
1152/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */
1153#define ALT_QSPI_DEVRD_ENMODBITS_MSB 20
1154/* The width in bits of the ALT_QSPI_DEVRD_ENMODBITS register field. */
1155#define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1
1156/* The mask used to set the ALT_QSPI_DEVRD_ENMODBITS register field value. */
1157#define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000
1158/* The mask used to clear the ALT_QSPI_DEVRD_ENMODBITS register field value. */
1159#define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff
1160/* The reset value of the ALT_QSPI_DEVRD_ENMODBITS register field. */
1161#define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0
1162/* Extracts the ALT_QSPI_DEVRD_ENMODBITS field value from a register. */
1163#define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20)
1164/* Produces a ALT_QSPI_DEVRD_ENMODBITS register field value suitable for setting the register. */
1165#define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000)
1166
1167/*
1168 * Field : Dummy Read Clock Cycles - dummyrdclks
1169 *
1170 * Number of dummy clock cycles required by device for read instruction.
1171 *
1172 * Field Access Macros:
1173 *
1174 */
1175/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1176#define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24
1177/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1178#define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28
1179/* The width in bits of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1180#define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5
1181/* The mask used to set the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */
1182#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000
1183/* The mask used to clear the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */
1184#define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff
1185/* The reset value of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1186#define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0
1187/* Extracts the ALT_QSPI_DEVRD_DUMMYRDCLKS field value from a register. */
1188#define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1189/* Produces a ALT_QSPI_DEVRD_DUMMYRDCLKS register field value suitable for setting the register. */
1190#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000)
1191
1192#ifndef __ASSEMBLY__
1193/*
1194 * WARNING: The C register and register group struct declarations are provided for
1195 * convenience and illustrative purposes. They should, however, be used with
1196 * caution as the C language standard provides no guarantees about the alignment or
1197 * atomicity of device memory accesses. The recommended practice for writing
1198 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1199 * alt_write_word() functions.
1200 *
1201 * The struct declaration for register ALT_QSPI_DEVRD.
1202 */
1203 struct ALT_QSPI_DEVRD_s
1204{
1205 uint32_t rdopcode : 8; /* Read Opcode in non-XIP mode */
1206 uint32_t instwidth : 2; /* Instruction Transfer Width */
1207 uint32_t : 2; /* *UNDEFINED* */
1208 uint32_t addrwidth : 2; /* Address Transfer Width */
1209 uint32_t : 2; /* *UNDEFINED* */
1210 uint32_t datawidth : 2; /* Data Transfer Width */
1211 uint32_t : 2; /* *UNDEFINED* */
1212 uint32_t enmodebits : 1; /* Mode Bit Enable */
1213 uint32_t : 3; /* *UNDEFINED* */
1214 uint32_t dummyrdclks : 5; /* Dummy Read Clock Cycles */
1215 uint32_t : 3; /* *UNDEFINED* */
1216};
1217
1218/* The typedef declaration for register ALT_QSPI_DEVRD. */
1219typedef volatile struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t;
1220#endif /* __ASSEMBLY__ */
1221
1222/* The byte offset of the ALT_QSPI_DEVRD register from the beginning of the component. */
1223#define ALT_QSPI_DEVRD_OFST 0x4
1224
1225/*
1226 * Register : Device Write Instruction Register - devwr
1227 *
1228 * Register Layout
1229 *
1230 * Bits | Access | Reset | Description
1231 * :--------|:-------|:------|:-------------------------
1232 * [7:0] | RW | 0x2 | Write Opcode
1233 * [11:8] | ??? | 0x0 | *UNDEFINED*
1234 * [13:12] | RW | 0x0 | Address Transfer Width
1235 * [15:14] | ??? | 0x0 | *UNDEFINED*
1236 * [17:16] | RW | 0x0 | Data Transfer Width
1237 * [23:18] | ??? | 0x0 | *UNDEFINED*
1238 * [28:24] | RW | 0x0 | Dummy Write Clock Cycles
1239 * [31:29] | ??? | 0x0 | *UNDEFINED*
1240 *
1241 */
1242/*
1243 * Field : Write Opcode - wropcode
1244 *
1245 * Write Opcode
1246 *
1247 * Field Access Macros:
1248 *
1249 */
1250/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */
1251#define ALT_QSPI_DEVWR_WROPCODE_LSB 0
1252/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */
1253#define ALT_QSPI_DEVWR_WROPCODE_MSB 7
1254/* The width in bits of the ALT_QSPI_DEVWR_WROPCODE register field. */
1255#define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8
1256/* The mask used to set the ALT_QSPI_DEVWR_WROPCODE register field value. */
1257#define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff
1258/* The mask used to clear the ALT_QSPI_DEVWR_WROPCODE register field value. */
1259#define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00
1260/* The reset value of the ALT_QSPI_DEVWR_WROPCODE register field. */
1261#define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2
1262/* Extracts the ALT_QSPI_DEVWR_WROPCODE field value from a register. */
1263#define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0)
1264/* Produces a ALT_QSPI_DEVWR_WROPCODE register field value suitable for setting the register. */
1265#define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff)
1266
1267/*
1268 * Field : Address Transfer Width - addrwidth
1269 *
1270 * Sets write address transfer width (1, 2, or 4 bits).
1271 *
1272 * Field Enumeration Values:
1273 *
1274 * Enum | Value | Description
1275 * :----------------------------------|:------|:-------------------------------------------------
1276 * ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE | 0x0 | Write address transferred on DQ0. Supported by
1277 * : | | all SPI flash devices
1278 * ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1.
1279 * : | | Supported by some SPI flash devices that support
1280 * : | | the Extended SPI Protocol and by all SPI flash
1281 * : | | devices that support the Dual SP (DIO-SPI)
1282 * : | | Protocol.
1283 * ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and
1284 * : | | DQ3. Supported by some SPI flash devices that
1285 * : | | support the Extended SPI Protocol and by all SPI
1286 * : | | flash devices that support the Quad SP (QIO-SPI)
1287 * : | | Protocol.
1288 *
1289 * Field Access Macros:
1290 *
1291 */
1292/*
1293 * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
1294 *
1295 * Write address transferred on DQ0. Supported by all SPI flash devices
1296 */
1297#define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0
1298/*
1299 * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
1300 *
1301 * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices
1302 * that support the Extended SPI Protocol and by all SPI flash devices that support
1303 * the Dual SP (DIO-SPI) Protocol.
1304 */
1305#define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1
1306/*
1307 * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
1308 *
1309 * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1310 * devices that support the Extended SPI Protocol and by all SPI flash devices that
1311 * support the Quad SP (QIO-SPI) Protocol.
1312 */
1313#define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2
1314
1315/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1316#define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12
1317/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1318#define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13
1319/* The width in bits of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1320#define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2
1321/* The mask used to set the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */
1322#define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000
1323/* The mask used to clear the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */
1324#define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff
1325/* The reset value of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1326#define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0
1327/* Extracts the ALT_QSPI_DEVWR_ADDRWIDTH field value from a register. */
1328#define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1329/* Produces a ALT_QSPI_DEVWR_ADDRWIDTH register field value suitable for setting the register. */
1330#define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1331
1332/*
1333 * Field : Data Transfer Width - datawidth
1334 *
1335 * Sets write data transfer width (1, 2, or 4 bits).
1336 *
1337 * Field Enumeration Values:
1338 *
1339 * Enum | Value | Description
1340 * :----------------------------------|:------|:-------------------------------------------------
1341 * ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE | 0x0 | Write data transferred on DQ0. Supported by all
1342 * : | | SPI flash devices
1343 * ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported
1344 * : | | by some SPI flash devices that support the
1345 * : | | Extended SPI Protocol and by all SPI flash
1346 * : | | devices that support the Dual SP (DIO-SPI)
1347 * : | | Protocol.
1348 * ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3.
1349 * : | | Supported by some SPI flash devices that support
1350 * : | | the Extended SPI Protocol and by all SPI flash
1351 * : | | devices that support the Quad SP (QIO-SPI)
1352 * : | | Protocol.
1353 *
1354 * Field Access Macros:
1355 *
1356 */
1357/*
1358 * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
1359 *
1360 * Write data transferred on DQ0. Supported by all SPI flash devices
1361 */
1362#define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0
1363/*
1364 * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
1365 *
1366 * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that
1367 * support the Extended SPI Protocol and by all SPI flash devices that support the
1368 * Dual SP (DIO-SPI) Protocol.
1369 */
1370#define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1
1371/*
1372 * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
1373 *
1374 * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1375 * devices that support the Extended SPI Protocol and by all SPI flash devices that
1376 * support the Quad SP (QIO-SPI) Protocol.
1377 */
1378#define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2
1379
1380/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1381#define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16
1382/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1383#define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17
1384/* The width in bits of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1385#define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2
1386/* The mask used to set the ALT_QSPI_DEVWR_DATAWIDTH register field value. */
1387#define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000
1388/* The mask used to clear the ALT_QSPI_DEVWR_DATAWIDTH register field value. */
1389#define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff
1390/* The reset value of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1391#define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0
1392/* Extracts the ALT_QSPI_DEVWR_DATAWIDTH field value from a register. */
1393#define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1394/* Produces a ALT_QSPI_DEVWR_DATAWIDTH register field value suitable for setting the register. */
1395#define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1396
1397/*
1398 * Field : Dummy Write Clock Cycles - dummywrclks
1399 *
1400 * Number of dummy clock cycles required by device for write instruction.
1401 *
1402 * Field Access Macros:
1403 *
1404 */
1405/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1406#define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24
1407/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1408#define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28
1409/* The width in bits of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1410#define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5
1411/* The mask used to set the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */
1412#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000
1413/* The mask used to clear the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */
1414#define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff
1415/* The reset value of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1416#define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0
1417/* Extracts the ALT_QSPI_DEVWR_DUMMYWRCLKS field value from a register. */
1418#define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1419/* Produces a ALT_QSPI_DEVWR_DUMMYWRCLKS register field value suitable for setting the register. */
1420#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000)
1421
1422#ifndef __ASSEMBLY__
1423/*
1424 * WARNING: The C register and register group struct declarations are provided for
1425 * convenience and illustrative purposes. They should, however, be used with
1426 * caution as the C language standard provides no guarantees about the alignment or
1427 * atomicity of device memory accesses. The recommended practice for writing
1428 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1429 * alt_write_word() functions.
1430 *
1431 * The struct declaration for register ALT_QSPI_DEVWR.
1432 */
1433 struct ALT_QSPI_DEVWR_s
1434{
1435 uint32_t wropcode : 8; /* Write Opcode */
1436 uint32_t : 4; /* *UNDEFINED* */
1437 uint32_t addrwidth : 2; /* Address Transfer Width */
1438 uint32_t : 2; /* *UNDEFINED* */
1439 uint32_t datawidth : 2; /* Data Transfer Width */
1440 uint32_t : 6; /* *UNDEFINED* */
1441 uint32_t dummywrclks : 5; /* Dummy Write Clock Cycles */
1442 uint32_t : 3; /* *UNDEFINED* */
1443};
1444
1445/* The typedef declaration for register ALT_QSPI_DEVWR. */
1446typedef volatile struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t;
1447#endif /* __ASSEMBLY__ */
1448
1449/* The byte offset of the ALT_QSPI_DEVWR register from the beginning of the component. */
1450#define ALT_QSPI_DEVWR_OFST 0x8
1451
1452/*
1453 * Register : QSPI Device Delay Register - delay
1454 *
1455 * This register is used to introduce relative delays into the generation of the
1456 * master output signals. All timings are defined in cycles of the qspi_clk.
1457 *
1458 * Register Layout
1459 *
1460 * Bits | Access | Reset | Description
1461 * :--------|:-------|:------|:-----------------------------------------
1462 * [7:0] | RW | 0x0 | Clock Delay with qspi_n_ss_out
1463 * [15:8] | RW | 0x0 | Clock Delay for Last Transaction Bit
1464 * [23:16] | RW | 0x0 | Clock Delay for Chip Select Deactivation
1465 * [31:24] | RW | 0x0 | Clock Delay for Chip Select Deassert
1466 *
1467 */
1468/*
1469 * Field : Clock Delay with qspi_n_ss_out - init
1470 *
1471 * Delay in master reference clocks between setting qspi_n_ss_out low and first bit
1472 * transfer.
1473 *
1474 * Field Access Macros:
1475 *
1476 */
1477/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_INIT register field. */
1478#define ALT_QSPI_DELAY_INIT_LSB 0
1479/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_INIT register field. */
1480#define ALT_QSPI_DELAY_INIT_MSB 7
1481/* The width in bits of the ALT_QSPI_DELAY_INIT register field. */
1482#define ALT_QSPI_DELAY_INIT_WIDTH 8
1483/* The mask used to set the ALT_QSPI_DELAY_INIT register field value. */
1484#define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff
1485/* The mask used to clear the ALT_QSPI_DELAY_INIT register field value. */
1486#define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00
1487/* The reset value of the ALT_QSPI_DELAY_INIT register field. */
1488#define ALT_QSPI_DELAY_INIT_RESET 0x0
1489/* Extracts the ALT_QSPI_DELAY_INIT field value from a register. */
1490#define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0)
1491/* Produces a ALT_QSPI_DELAY_INIT register field value suitable for setting the register. */
1492#define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff)
1493
1494/*
1495 * Field : Clock Delay for Last Transaction Bit - after
1496 *
1497 * Delay in master reference clocks between last bit of current transaction and
1498 * deasserting the device chip select (qspi_n_ss_out). By default, the chip select
1499 * will be deasserted on the cycle following the completion of the current
1500 * transaction.
1501 *
1502 * Field Access Macros:
1503 *
1504 */
1505/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_AFTER register field. */
1506#define ALT_QSPI_DELAY_AFTER_LSB 8
1507/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_AFTER register field. */
1508#define ALT_QSPI_DELAY_AFTER_MSB 15
1509/* The width in bits of the ALT_QSPI_DELAY_AFTER register field. */
1510#define ALT_QSPI_DELAY_AFTER_WIDTH 8
1511/* The mask used to set the ALT_QSPI_DELAY_AFTER register field value. */
1512#define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00
1513/* The mask used to clear the ALT_QSPI_DELAY_AFTER register field value. */
1514#define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff
1515/* The reset value of the ALT_QSPI_DELAY_AFTER register field. */
1516#define ALT_QSPI_DELAY_AFTER_RESET 0x0
1517/* Extracts the ALT_QSPI_DELAY_AFTER field value from a register. */
1518#define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8)
1519/* Produces a ALT_QSPI_DELAY_AFTER register field value suitable for setting the register. */
1520#define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00)
1521
1522/*
1523 * Field : Clock Delay for Chip Select Deactivation - btwn
1524 *
1525 * Delay in master reference clocks between one chip select being de-activated and
1526 * the activation of another. This is used to ensure a quiet period between the
1527 * selection of two different slaves and requires the transmit FIFO to be empty.
1528 *
1529 * Field Access Macros:
1530 *
1531 */
1532/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_BTWN register field. */
1533#define ALT_QSPI_DELAY_BTWN_LSB 16
1534/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_BTWN register field. */
1535#define ALT_QSPI_DELAY_BTWN_MSB 23
1536/* The width in bits of the ALT_QSPI_DELAY_BTWN register field. */
1537#define ALT_QSPI_DELAY_BTWN_WIDTH 8
1538/* The mask used to set the ALT_QSPI_DELAY_BTWN register field value. */
1539#define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000
1540/* The mask used to clear the ALT_QSPI_DELAY_BTWN register field value. */
1541#define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff
1542/* The reset value of the ALT_QSPI_DELAY_BTWN register field. */
1543#define ALT_QSPI_DELAY_BTWN_RESET 0x0
1544/* Extracts the ALT_QSPI_DELAY_BTWN field value from a register. */
1545#define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16)
1546/* Produces a ALT_QSPI_DELAY_BTWN register field value suitable for setting the register. */
1547#define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000)
1548
1549/*
1550 * Field : Clock Delay for Chip Select Deassert - nss
1551 *
1552 * Delay in master reference clocks for the length that the master mode chip select
1553 * outputs are de-asserted between transactions. The minimum delay is always
1554 * qspi_sck_out period to ensure the chip select is never re-asserted within an
1555 * qspi_sck_out period.
1556 *
1557 * Field Access Macros:
1558 *
1559 */
1560/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_NSS register field. */
1561#define ALT_QSPI_DELAY_NSS_LSB 24
1562/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_NSS register field. */
1563#define ALT_QSPI_DELAY_NSS_MSB 31
1564/* The width in bits of the ALT_QSPI_DELAY_NSS register field. */
1565#define ALT_QSPI_DELAY_NSS_WIDTH 8
1566/* The mask used to set the ALT_QSPI_DELAY_NSS register field value. */
1567#define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000
1568/* The mask used to clear the ALT_QSPI_DELAY_NSS register field value. */
1569#define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff
1570/* The reset value of the ALT_QSPI_DELAY_NSS register field. */
1571#define ALT_QSPI_DELAY_NSS_RESET 0x0
1572/* Extracts the ALT_QSPI_DELAY_NSS field value from a register. */
1573#define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24)
1574/* Produces a ALT_QSPI_DELAY_NSS register field value suitable for setting the register. */
1575#define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000)
1576
1577#ifndef __ASSEMBLY__
1578/*
1579 * WARNING: The C register and register group struct declarations are provided for
1580 * convenience and illustrative purposes. They should, however, be used with
1581 * caution as the C language standard provides no guarantees about the alignment or
1582 * atomicity of device memory accesses. The recommended practice for writing
1583 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1584 * alt_write_word() functions.
1585 *
1586 * The struct declaration for register ALT_QSPI_DELAY.
1587 */
1588 struct ALT_QSPI_DELAY_s
1589{
1590 uint32_t init : 8; /* Clock Delay with qspi_n_ss_out */
1591 uint32_t after : 8; /* Clock Delay for Last Transaction Bit */
1592 uint32_t btwn : 8; /* Clock Delay for Chip Select Deactivation */
1593 uint32_t nss : 8; /* Clock Delay for Chip Select Deassert */
1594};
1595
1596/* The typedef declaration for register ALT_QSPI_DELAY. */
1597typedef volatile struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t;
1598#endif /* __ASSEMBLY__ */
1599
1600/* The byte offset of the ALT_QSPI_DELAY register from the beginning of the component. */
1601#define ALT_QSPI_DELAY_OFST 0xc
1602
1603/*
1604 * Register : Read Data Capture Register - rddatacap
1605 *
1606 * Register Layout
1607 *
1608 * Bits | Access | Reset | Description
1609 * :-------|:-------|:------|:------------
1610 * [0] | RW | 0x1 | Bypass
1611 * [4:1] | RW | 0x0 | Read Delay
1612 * [31:5] | ??? | 0x0 | *UNDEFINED*
1613 *
1614 */
1615/*
1616 * Field : Bypass - byp
1617 *
1618 * Controls bypass of the adapted loopback clock circuit
1619 *
1620 * Field Enumeration Values:
1621 *
1622 * Enum | Value | Description
1623 * :----------------------------------|:------|:------------------------------
1624 * ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS | 0x0 | No Bypass
1625 * ALT_QSPI_RDDATACAP_BYP_E_BYPASS | 0x1 | Bypass loopback clock circuit
1626 *
1627 * Field Access Macros:
1628 *
1629 */
1630/*
1631 * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP
1632 *
1633 * No Bypass
1634 */
1635#define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x0
1636/*
1637 * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP
1638 *
1639 * Bypass loopback clock circuit
1640 */
1641#define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x1
1642
1643/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */
1644#define ALT_QSPI_RDDATACAP_BYP_LSB 0
1645/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */
1646#define ALT_QSPI_RDDATACAP_BYP_MSB 0
1647/* The width in bits of the ALT_QSPI_RDDATACAP_BYP register field. */
1648#define ALT_QSPI_RDDATACAP_BYP_WIDTH 1
1649/* The mask used to set the ALT_QSPI_RDDATACAP_BYP register field value. */
1650#define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001
1651/* The mask used to clear the ALT_QSPI_RDDATACAP_BYP register field value. */
1652#define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe
1653/* The reset value of the ALT_QSPI_RDDATACAP_BYP register field. */
1654#define ALT_QSPI_RDDATACAP_BYP_RESET 0x1
1655/* Extracts the ALT_QSPI_RDDATACAP_BYP field value from a register. */
1656#define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0)
1657/* Produces a ALT_QSPI_RDDATACAP_BYP register field value suitable for setting the register. */
1658#define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001)
1659
1660/*
1661 * Field : Read Delay - delay
1662 *
1663 * Delay the read data capturing logic by the programmed number of qspi_clk cycles
1664 *
1665 * Field Access Macros:
1666 *
1667 */
1668/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */
1669#define ALT_QSPI_RDDATACAP_DELAY_LSB 1
1670/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */
1671#define ALT_QSPI_RDDATACAP_DELAY_MSB 4
1672/* The width in bits of the ALT_QSPI_RDDATACAP_DELAY register field. */
1673#define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4
1674/* The mask used to set the ALT_QSPI_RDDATACAP_DELAY register field value. */
1675#define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e
1676/* The mask used to clear the ALT_QSPI_RDDATACAP_DELAY register field value. */
1677#define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1
1678/* The reset value of the ALT_QSPI_RDDATACAP_DELAY register field. */
1679#define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0
1680/* Extracts the ALT_QSPI_RDDATACAP_DELAY field value from a register. */
1681#define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1)
1682/* Produces a ALT_QSPI_RDDATACAP_DELAY register field value suitable for setting the register. */
1683#define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e)
1684
1685#ifndef __ASSEMBLY__
1686/*
1687 * WARNING: The C register and register group struct declarations are provided for
1688 * convenience and illustrative purposes. They should, however, be used with
1689 * caution as the C language standard provides no guarantees about the alignment or
1690 * atomicity of device memory accesses. The recommended practice for writing
1691 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1692 * alt_write_word() functions.
1693 *
1694 * The struct declaration for register ALT_QSPI_RDDATACAP.
1695 */
1696 struct ALT_QSPI_RDDATACAP_s
1697{
1698 uint32_t byp : 1; /* Bypass */
1699 uint32_t delay : 4; /* Read Delay */
1700 uint32_t : 27; /* *UNDEFINED* */
1701};
1702
1703/* The typedef declaration for register ALT_QSPI_RDDATACAP. */
1704typedef volatile struct ALT_QSPI_RDDATACAP_s ALT_QSPI_RDDATACAP_t;
1705#endif /* __ASSEMBLY__ */
1706
1707/* The byte offset of the ALT_QSPI_RDDATACAP register from the beginning of the component. */
1708#define ALT_QSPI_RDDATACAP_OFST 0x10
1709
1710/*
1711 * Register : Device Size Register - devsz
1712 *
1713 * Register Layout
1714 *
1715 * Bits | Access | Reset | Description
1716 * :--------|:-------|:------|:--------------------------------
1717 * [3:0] | RW | 0x2 | Number of address Bytes
1718 * [15:4] | RW | 0x100 | Number of Bytes per Device Page
1719 * [20:16] | RW | 0x10 | Number of Bytes per Block
1720 * [31:21] | ??? | 0x0 | *UNDEFINED*
1721 *
1722 */
1723/*
1724 * Field : Number of address Bytes - numaddrbytes
1725 *
1726 * Number of address bytes. A value of 0 indicates 1 byte.
1727 *
1728 * Field Access Macros:
1729 *
1730 */
1731/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
1732#define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0
1733/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
1734#define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3
1735/* The width in bits of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
1736#define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4
1737/* The mask used to set the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */
1738#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f
1739/* The mask used to clear the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */
1740#define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0
1741/* The reset value of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
1742#define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2
1743/* Extracts the ALT_QSPI_DEVSZ_NUMADDRBYTES field value from a register. */
1744#define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0)
1745/* Produces a ALT_QSPI_DEVSZ_NUMADDRBYTES register field value suitable for setting the register. */
1746#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f)
1747
1748/*
1749 * Field : Number of Bytes per Device Page - bytesperdevicepage
1750 *
1751 * Number of bytes per device page. This is required by the controller for
1752 * performing FLASH writes up to and across page boundaries.
1753 *
1754 * Field Access Macros:
1755 *
1756 */
1757/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
1758#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4
1759/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
1760#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15
1761/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
1762#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12
1763/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */
1764#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0
1765/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */
1766#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f
1767/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
1768#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100
1769/* Extracts the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE field value from a register. */
1770#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4)
1771/* Produces a ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value suitable for setting the register. */
1772#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0)
1773
1774/*
1775 * Field : Number of Bytes per Block - bytespersubsector
1776 *
1777 * Number of bytes per Block. This is required by the controller for performing the
1778 * write protection logic. The number of bytes per block must be a power of 2
1779 * number.
1780 *
1781 * Field Access Macros:
1782 *
1783 */
1784/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
1785#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16
1786/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
1787#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20
1788/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
1789#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5
1790/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */
1791#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000
1792/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */
1793#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff
1794/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
1795#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10
1796/* Extracts the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR field value from a register. */
1797#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16)
1798/* Produces a ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value suitable for setting the register. */
1799#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000)
1800
1801#ifndef __ASSEMBLY__
1802/*
1803 * WARNING: The C register and register group struct declarations are provided for
1804 * convenience and illustrative purposes. They should, however, be used with
1805 * caution as the C language standard provides no guarantees about the alignment or
1806 * atomicity of device memory accesses. The recommended practice for writing
1807 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1808 * alt_write_word() functions.
1809 *
1810 * The struct declaration for register ALT_QSPI_DEVSZ.
1811 */
1812 struct ALT_QSPI_DEVSZ_s
1813{
1814 uint32_t numaddrbytes : 4; /* Number of address Bytes */
1815 uint32_t bytesperdevicepage : 12; /* Number of Bytes per Device Page */
1816 uint32_t bytespersubsector : 5; /* Number of Bytes per Block */
1817 uint32_t : 11; /* *UNDEFINED* */
1818};
1819
1820/* The typedef declaration for register ALT_QSPI_DEVSZ. */
1821typedef volatile struct ALT_QSPI_DEVSZ_s ALT_QSPI_DEVSZ_t;
1822#endif /* __ASSEMBLY__ */
1823
1824/* The byte offset of the ALT_QSPI_DEVSZ register from the beginning of the component. */
1825#define ALT_QSPI_DEVSZ_OFST 0x14
1826
1827/*
1828 * Register : SRAM Partition Register - srampart
1829 *
1830 * Register Layout
1831 *
1832 * Bits | Access | Reset | Description
1833 * :-------|:-------|:------|:-----------------------------
1834 * [6:0] | RW | 0x40 | Indirect Read Partition Size
1835 * [31:7] | ??? | 0x0 | *UNDEFINED*
1836 *
1837 */
1838/*
1839 * Field : Indirect Read Partition Size - addr
1840 *
1841 * Defines the size of the indirect read partition in the SRAM, in units of SRAM
1842 * locations. By default, half of the SRAM is reserved for indirect read operations
1843 * and half for indirect write operations.
1844 *
1845 * Field Access Macros:
1846 *
1847 */
1848/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */
1849#define ALT_QSPI_SRAMPART_ADDR_LSB 0
1850/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */
1851#define ALT_QSPI_SRAMPART_ADDR_MSB 6
1852/* The width in bits of the ALT_QSPI_SRAMPART_ADDR register field. */
1853#define ALT_QSPI_SRAMPART_ADDR_WIDTH 7
1854/* The mask used to set the ALT_QSPI_SRAMPART_ADDR register field value. */
1855#define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x0000007f
1856/* The mask used to clear the ALT_QSPI_SRAMPART_ADDR register field value. */
1857#define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff80
1858/* The reset value of the ALT_QSPI_SRAMPART_ADDR register field. */
1859#define ALT_QSPI_SRAMPART_ADDR_RESET 0x40
1860/* Extracts the ALT_QSPI_SRAMPART_ADDR field value from a register. */
1861#define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x0000007f) >> 0)
1862/* Produces a ALT_QSPI_SRAMPART_ADDR register field value suitable for setting the register. */
1863#define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x0000007f)
1864
1865#ifndef __ASSEMBLY__
1866/*
1867 * WARNING: The C register and register group struct declarations are provided for
1868 * convenience and illustrative purposes. They should, however, be used with
1869 * caution as the C language standard provides no guarantees about the alignment or
1870 * atomicity of device memory accesses. The recommended practice for writing
1871 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1872 * alt_write_word() functions.
1873 *
1874 * The struct declaration for register ALT_QSPI_SRAMPART.
1875 */
1876 struct ALT_QSPI_SRAMPART_s
1877{
1878 uint32_t addr : 7; /* Indirect Read Partition Size */
1879 uint32_t : 25; /* *UNDEFINED* */
1880};
1881
1882/* The typedef declaration for register ALT_QSPI_SRAMPART. */
1883typedef volatile struct ALT_QSPI_SRAMPART_s ALT_QSPI_SRAMPART_t;
1884#endif /* __ASSEMBLY__ */
1885
1886/* The byte offset of the ALT_QSPI_SRAMPART register from the beginning of the component. */
1887#define ALT_QSPI_SRAMPART_OFST 0x18
1888
1889/*
1890 * Register : Indirect AHB Address Trigger Register - indaddrtrig
1891 *
1892 * Register Layout
1893 *
1894 * Bits | Access | Reset | Description
1895 * :-------|:-------|:------|:----------------
1896 * [31:0] | RW | 0x0 | Trigger Address
1897 *
1898 */
1899/*
1900 * Field : Trigger Address - addr
1901 *
1902 * This is the base address that will be used by the AHB controller. When the
1903 * incoming AHB read access address matches a range of addresses from this trigger
1904 * address to the trigger address + 15, then the AHB request will be completed by
1905 * fetching data from the Indirect Controllers SRAM.
1906 *
1907 * Field Access Macros:
1908 *
1909 */
1910/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
1911#define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0
1912/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
1913#define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31
1914/* The width in bits of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
1915#define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32
1916/* The mask used to set the ALT_QSPI_INDADDRTRIG_ADDR register field value. */
1917#define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff
1918/* The mask used to clear the ALT_QSPI_INDADDRTRIG_ADDR register field value. */
1919#define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000
1920/* The reset value of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
1921#define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0
1922/* Extracts the ALT_QSPI_INDADDRTRIG_ADDR field value from a register. */
1923#define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
1924/* Produces a ALT_QSPI_INDADDRTRIG_ADDR register field value suitable for setting the register. */
1925#define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff)
1926
1927#ifndef __ASSEMBLY__
1928/*
1929 * WARNING: The C register and register group struct declarations are provided for
1930 * convenience and illustrative purposes. They should, however, be used with
1931 * caution as the C language standard provides no guarantees about the alignment or
1932 * atomicity of device memory accesses. The recommended practice for writing
1933 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1934 * alt_write_word() functions.
1935 *
1936 * The struct declaration for register ALT_QSPI_INDADDRTRIG.
1937 */
1938 struct ALT_QSPI_INDADDRTRIG_s
1939{
1940 uint32_t addr : 32; /* Trigger Address */
1941};
1942
1943/* The typedef declaration for register ALT_QSPI_INDADDRTRIG. */
1944typedef volatile struct ALT_QSPI_INDADDRTRIG_s ALT_QSPI_INDADDRTRIG_t;
1945#endif /* __ASSEMBLY__ */
1946
1947/* The byte offset of the ALT_QSPI_INDADDRTRIG register from the beginning of the component. */
1948#define ALT_QSPI_INDADDRTRIG_OFST 0x1c
1949
1950/*
1951 * Register : DMA Peripheral Register - dmaper
1952 *
1953 * Register Layout
1954 *
1955 * Bits | Access | Reset | Description
1956 * :--------|:-------|:------|:-----------------------
1957 * [3:0] | RW | 0x0 | Number of Single Bytes
1958 * [7:4] | ??? | 0x0 | *UNDEFINED*
1959 * [11:8] | RW | 0x0 | Number of Burst Bytes
1960 * [31:12] | ??? | 0x0 | *UNDEFINED*
1961 *
1962 */
1963/*
1964 * Field : Number of Single Bytes - numsglreqbytes
1965 *
1966 * Number of bytes in a single type request on the DMA peripheral request. A
1967 * programmed value of 0 represents a single byte. This should be setup before
1968 * starting the indirect read or write operation. The actual number of bytes used
1969 * is 2**(value in this register) which will simplify implementation.
1970 *
1971 * Field Access Macros:
1972 *
1973 */
1974/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
1975#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0
1976/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
1977#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3
1978/* The width in bits of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
1979#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4
1980/* The mask used to set the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */
1981#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f
1982/* The mask used to clear the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */
1983#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0
1984/* The reset value of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
1985#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0
1986/* Extracts the ALT_QSPI_DMAPER_NUMSGLREQBYTES field value from a register. */
1987#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0)
1988/* Produces a ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value suitable for setting the register. */
1989#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f)
1990
1991/*
1992 * Field : Number of Burst Bytes - numburstreqbytes
1993 *
1994 * Number of bytes in a burst type request on the DMA peripheral request. A
1995 * programmed value of 0 represents a single byte. This should be setup before
1996 * starting the indirect read or write operation. The actual number of bytes used
1997 * is 2**(value in this register) which will simplify implementation.
1998 *
1999 * Field Access Macros:
2000 *
2001 */
2002/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
2003#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8
2004/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
2005#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11
2006/* The width in bits of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
2007#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4
2008/* The mask used to set the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */
2009#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00
2010/* The mask used to clear the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */
2011#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff
2012/* The reset value of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
2013#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0
2014/* Extracts the ALT_QSPI_DMAPER_NUMBURSTREQBYTES field value from a register. */
2015#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8)
2016/* Produces a ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value suitable for setting the register. */
2017#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00)
2018
2019#ifndef __ASSEMBLY__
2020/*
2021 * WARNING: The C register and register group struct declarations are provided for
2022 * convenience and illustrative purposes. They should, however, be used with
2023 * caution as the C language standard provides no guarantees about the alignment or
2024 * atomicity of device memory accesses. The recommended practice for writing
2025 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2026 * alt_write_word() functions.
2027 *
2028 * The struct declaration for register ALT_QSPI_DMAPER.
2029 */
2030 struct ALT_QSPI_DMAPER_s
2031{
2032 uint32_t numsglreqbytes : 4; /* Number of Single Bytes */
2033 uint32_t : 4; /* *UNDEFINED* */
2034 uint32_t numburstreqbytes : 4; /* Number of Burst Bytes */
2035 uint32_t : 20; /* *UNDEFINED* */
2036};
2037
2038/* The typedef declaration for register ALT_QSPI_DMAPER. */
2039typedef volatile struct ALT_QSPI_DMAPER_s ALT_QSPI_DMAPER_t;
2040#endif /* __ASSEMBLY__ */
2041
2042/* The byte offset of the ALT_QSPI_DMAPER register from the beginning of the component. */
2043#define ALT_QSPI_DMAPER_OFST 0x20
2044
2045/*
2046 * Register : Remap Address Register - remapaddr
2047 *
2048 * This register is used to remap an incoming AHB address to a different address
2049 * used by the FLASH device.
2050 *
2051 * Register Layout
2052 *
2053 * Bits | Access | Reset | Description
2054 * :-------|:-------|:------|:---------------------
2055 * [31:0] | RW | 0x0 | Remap Address Offset
2056 *
2057 */
2058/*
2059 * Field : Remap Address Offset - value
2060 *
2061 * This offset is added to the incoming AHB address to determine the address used
2062 * by the FLASH device.
2063 *
2064 * Field Access Macros:
2065 *
2066 */
2067/* The Least Significant Bit (LSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */
2068#define ALT_QSPI_REMAPADDR_VALUE_LSB 0
2069/* The Most Significant Bit (MSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */
2070#define ALT_QSPI_REMAPADDR_VALUE_MSB 31
2071/* The width in bits of the ALT_QSPI_REMAPADDR_VALUE register field. */
2072#define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32
2073/* The mask used to set the ALT_QSPI_REMAPADDR_VALUE register field value. */
2074#define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff
2075/* The mask used to clear the ALT_QSPI_REMAPADDR_VALUE register field value. */
2076#define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000
2077/* The reset value of the ALT_QSPI_REMAPADDR_VALUE register field. */
2078#define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0
2079/* Extracts the ALT_QSPI_REMAPADDR_VALUE field value from a register. */
2080#define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
2081/* Produces a ALT_QSPI_REMAPADDR_VALUE register field value suitable for setting the register. */
2082#define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
2083
2084#ifndef __ASSEMBLY__
2085/*
2086 * WARNING: The C register and register group struct declarations are provided for
2087 * convenience and illustrative purposes. They should, however, be used with
2088 * caution as the C language standard provides no guarantees about the alignment or
2089 * atomicity of device memory accesses. The recommended practice for writing
2090 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2091 * alt_write_word() functions.
2092 *
2093 * The struct declaration for register ALT_QSPI_REMAPADDR.
2094 */
2095 struct ALT_QSPI_REMAPADDR_s
2096{
2097 uint32_t value : 32; /* Remap Address Offset */
2098};
2099
2100/* The typedef declaration for register ALT_QSPI_REMAPADDR. */
2101typedef volatile struct ALT_QSPI_REMAPADDR_s ALT_QSPI_REMAPADDR_t;
2102#endif /* __ASSEMBLY__ */
2103
2104/* The byte offset of the ALT_QSPI_REMAPADDR register from the beginning of the component. */
2105#define ALT_QSPI_REMAPADDR_OFST 0x24
2106
2107/*
2108 * Register : Mode Bit Register - modebit
2109 *
2110 * Register Layout
2111 *
2112 * Bits | Access | Reset | Description
2113 * :-------|:-------|:------|:------------
2114 * [7:0] | RW | 0x0 | Mode
2115 * [31:8] | ??? | 0x0 | *UNDEFINED*
2116 *
2117 */
2118/*
2119 * Field : Mode - mode
2120 *
2121 * These are the 8 mode bits that are sent to the device following the address
2122 * bytes if mode bit transmission has been enabled.
2123 *
2124 * Field Access Macros:
2125 *
2126 */
2127/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODBIT_MOD register field. */
2128#define ALT_QSPI_MODBIT_MOD_LSB 0
2129/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODBIT_MOD register field. */
2130#define ALT_QSPI_MODBIT_MOD_MSB 7
2131/* The width in bits of the ALT_QSPI_MODBIT_MOD register field. */
2132#define ALT_QSPI_MODBIT_MOD_WIDTH 8
2133/* The mask used to set the ALT_QSPI_MODBIT_MOD register field value. */
2134#define ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff
2135/* The mask used to clear the ALT_QSPI_MODBIT_MOD register field value. */
2136#define ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00
2137/* The reset value of the ALT_QSPI_MODBIT_MOD register field. */
2138#define ALT_QSPI_MODBIT_MOD_RESET 0x0
2139/* Extracts the ALT_QSPI_MODBIT_MOD field value from a register. */
2140#define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0)
2141/* Produces a ALT_QSPI_MODBIT_MOD register field value suitable for setting the register. */
2142#define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff)
2143
2144#ifndef __ASSEMBLY__
2145/*
2146 * WARNING: The C register and register group struct declarations are provided for
2147 * convenience and illustrative purposes. They should, however, be used with
2148 * caution as the C language standard provides no guarantees about the alignment or
2149 * atomicity of device memory accesses. The recommended practice for writing
2150 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2151 * alt_write_word() functions.
2152 *
2153 * The struct declaration for register ALT_QSPI_MODBIT.
2154 */
2155 struct ALT_QSPI_MODBIT_s
2156{
2157 uint32_t mode : 8; /* Mode */
2158 uint32_t : 24; /* *UNDEFINED* */
2159};
2160
2161/* The typedef declaration for register ALT_QSPI_MODBIT. */
2162typedef volatile struct ALT_QSPI_MODBIT_s ALT_QSPI_MODBIT_t;
2163#endif /* __ASSEMBLY__ */
2164
2165/* The byte offset of the ALT_QSPI_MODBIT register from the beginning of the component. */
2166#define ALT_QSPI_MODBIT_OFST 0x28
2167
2168/*
2169 * Register : SRAM Fill Register - sramfill
2170 *
2171 * Register Layout
2172 *
2173 * Bits | Access | Reset | Description
2174 * :--------|:-------|:------|:-------------------------------------------------------------------
2175 * [15:0] | R | 0x0 | SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS
2176 * [31:16] | R | 0x0 | SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS
2177 *
2178 */
2179/*
2180 * Field : SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS - indrdpart
2181 *
2182 * Field Access Macros:
2183 *
2184 */
2185/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2186#define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0
2187/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2188#define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15
2189/* The width in bits of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2190#define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16
2191/* The mask used to set the ALT_QSPI_SRAMFILL_INDRDPART register field value. */
2192#define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff
2193/* The mask used to clear the ALT_QSPI_SRAMFILL_INDRDPART register field value. */
2194#define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000
2195/* The reset value of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2196#define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0
2197/* Extracts the ALT_QSPI_SRAMFILL_INDRDPART field value from a register. */
2198#define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0)
2199/* Produces a ALT_QSPI_SRAMFILL_INDRDPART register field value suitable for setting the register. */
2200#define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff)
2201
2202/*
2203 * Field : SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS - indwrpart
2204 *
2205 * Field Access Macros:
2206 *
2207 */
2208/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2209#define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16
2210/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2211#define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31
2212/* The width in bits of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2213#define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16
2214/* The mask used to set the ALT_QSPI_SRAMFILL_INDWRPART register field value. */
2215#define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000
2216/* The mask used to clear the ALT_QSPI_SRAMFILL_INDWRPART register field value. */
2217#define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff
2218/* The reset value of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2219#define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0
2220/* Extracts the ALT_QSPI_SRAMFILL_INDWRPART field value from a register. */
2221#define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16)
2222/* Produces a ALT_QSPI_SRAMFILL_INDWRPART register field value suitable for setting the register. */
2223#define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000)
2224
2225#ifndef __ASSEMBLY__
2226/*
2227 * WARNING: The C register and register group struct declarations are provided for
2228 * convenience and illustrative purposes. They should, however, be used with
2229 * caution as the C language standard provides no guarantees about the alignment or
2230 * atomicity of device memory accesses. The recommended practice for writing
2231 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2232 * alt_write_word() functions.
2233 *
2234 * The struct declaration for register ALT_QSPI_SRAMFILL.
2235 */
2236 struct ALT_QSPI_SRAMFILL_s
2237{
2238 const uint32_t indrdpart : 16; /* SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS */
2239 const uint32_t indwrpart : 16; /* SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS */
2240};
2241
2242/* The typedef declaration for register ALT_QSPI_SRAMFILL. */
2243typedef volatile struct ALT_QSPI_SRAMFILL_s ALT_QSPI_SRAMFILL_t;
2244#endif /* __ASSEMBLY__ */
2245
2246/* The byte offset of the ALT_QSPI_SRAMFILL register from the beginning of the component. */
2247#define ALT_QSPI_SRAMFILL_OFST 0x2c
2248
2249/*
2250 * Register : TX Threshold Register - txthresh
2251 *
2252 * Register Layout
2253 *
2254 * Bits | Access | Reset | Description
2255 * :-------|:-------|:------|:------------
2256 * [3:0] | RW | 0x1 | Level
2257 * [31:4] | ??? | 0x0 | *UNDEFINED*
2258 *
2259 */
2260/*
2261 * Field : Level - level
2262 *
2263 * Defines the level at which the transmit FIFO not full interrupt is generated
2264 *
2265 * Field Access Macros:
2266 *
2267 */
2268/* The Least Significant Bit (LSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2269#define ALT_QSPI_TXTHRESH_LEVEL_LSB 0
2270/* The Most Significant Bit (MSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2271#define ALT_QSPI_TXTHRESH_LEVEL_MSB 3
2272/* The width in bits of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2273#define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4
2274/* The mask used to set the ALT_QSPI_TXTHRESH_LEVEL register field value. */
2275#define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f
2276/* The mask used to clear the ALT_QSPI_TXTHRESH_LEVEL register field value. */
2277#define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2278/* The reset value of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2279#define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1
2280/* Extracts the ALT_QSPI_TXTHRESH_LEVEL field value from a register. */
2281#define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2282/* Produces a ALT_QSPI_TXTHRESH_LEVEL register field value suitable for setting the register. */
2283#define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2284
2285#ifndef __ASSEMBLY__
2286/*
2287 * WARNING: The C register and register group struct declarations are provided for
2288 * convenience and illustrative purposes. They should, however, be used with
2289 * caution as the C language standard provides no guarantees about the alignment or
2290 * atomicity of device memory accesses. The recommended practice for writing
2291 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2292 * alt_write_word() functions.
2293 *
2294 * The struct declaration for register ALT_QSPI_TXTHRESH.
2295 */
2296 struct ALT_QSPI_TXTHRESH_s
2297{
2298 uint32_t level : 4; /* Level */
2299 uint32_t : 28; /* *UNDEFINED* */
2300};
2301
2302/* The typedef declaration for register ALT_QSPI_TXTHRESH. */
2303typedef volatile struct ALT_QSPI_TXTHRESH_s ALT_QSPI_TXTHRESH_t;
2304#endif /* __ASSEMBLY__ */
2305
2306/* The byte offset of the ALT_QSPI_TXTHRESH register from the beginning of the component. */
2307#define ALT_QSPI_TXTHRESH_OFST 0x30
2308
2309/*
2310 * Register : RX Threshold Register - rxthresh
2311 *
2312 * Device Instruction Register
2313 *
2314 * Register Layout
2315 *
2316 * Bits | Access | Reset | Description
2317 * :-------|:-------|:------|:------------
2318 * [3:0] | RW | 0x1 | Level
2319 * [31:4] | ??? | 0x0 | *UNDEFINED*
2320 *
2321 */
2322/*
2323 * Field : Level - level
2324 *
2325 * Defines the level at which the receive FIFO not empty interrupt is generated
2326 *
2327 * Field Access Macros:
2328 *
2329 */
2330/* The Least Significant Bit (LSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2331#define ALT_QSPI_RXTHRESH_LEVEL_LSB 0
2332/* The Most Significant Bit (MSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2333#define ALT_QSPI_RXTHRESH_LEVEL_MSB 3
2334/* The width in bits of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2335#define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4
2336/* The mask used to set the ALT_QSPI_RXTHRESH_LEVEL register field value. */
2337#define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f
2338/* The mask used to clear the ALT_QSPI_RXTHRESH_LEVEL register field value. */
2339#define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2340/* The reset value of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2341#define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1
2342/* Extracts the ALT_QSPI_RXTHRESH_LEVEL field value from a register. */
2343#define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2344/* Produces a ALT_QSPI_RXTHRESH_LEVEL register field value suitable for setting the register. */
2345#define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2346
2347#ifndef __ASSEMBLY__
2348/*
2349 * WARNING: The C register and register group struct declarations are provided for
2350 * convenience and illustrative purposes. They should, however, be used with
2351 * caution as the C language standard provides no guarantees about the alignment or
2352 * atomicity of device memory accesses. The recommended practice for writing
2353 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2354 * alt_write_word() functions.
2355 *
2356 * The struct declaration for register ALT_QSPI_RXTHRESH.
2357 */
2358 struct ALT_QSPI_RXTHRESH_s
2359{
2360 uint32_t level : 4; /* Level */
2361 uint32_t : 28; /* *UNDEFINED* */
2362};
2363
2364/* The typedef declaration for register ALT_QSPI_RXTHRESH. */
2365typedef volatile struct ALT_QSPI_RXTHRESH_s ALT_QSPI_RXTHRESH_t;
2366#endif /* __ASSEMBLY__ */
2367
2368/* The byte offset of the ALT_QSPI_RXTHRESH register from the beginning of the component. */
2369#define ALT_QSPI_RXTHRESH_OFST 0x34
2370
2371/*
2372 * Register : Interrupt Status Register - irqstat
2373 *
2374 * The status fields in this register are set when the described event occurs and
2375 * the interrupt is enabled in the mask register. When any of these bit fields are
2376 * set, the interrupt output is asserted high. The fields are each cleared by
2377 * writing a 1 to the field. Note that bit fields 7 thru 11 are only valid when
2378 * legacy SPI mode is active.
2379 *
2380 * Register Layout
2381 *
2382 * Bits | Access | Reset | Description
2383 * :--------|:-------|:------|:------------------------------------
2384 * [0] | ??? | 0x0 | *UNDEFINED*
2385 * [1] | RW | 0x0 | Underflow Detected
2386 * [2] | RW | 0x0 | Indirect Operation Complete
2387 * [3] | RW | 0x0 | Indirect Read Reject
2388 * [4] | RW | 0x0 | Protected Area Write Attempt
2389 * [5] | RW | 0x0 | Illegal AHB Access Detected
2390 * [6] | RW | 0x0 | Transfer Watermark Reached
2391 * [7] | RW | 0x0 | Receive Overflow
2392 * [8] | RW | 0x1 | Transmit FIFO Compared to Threshold
2393 * [9] | RW | 0x0 | Transmit FIFO Full
2394 * [10] | RW | 0x0 | Receive FIFO Compared to Threshold
2395 * [11] | RW | 0x0 | Receive FIFO Full
2396 * [12] | RW | 0x0 | Indirect Read Partition overflow
2397 * [31:13] | ??? | 0x0 | *UNDEFINED*
2398 *
2399 */
2400/*
2401 * Field : Underflow Detected - underflowdet
2402 *
2403 * An underflow is detected when an attempt to transfer data is made when the
2404 * transmit FIFO is empty. This may occur when the AHB write data is being supplied
2405 * too slowly to keep up with the requested write operation. This bit is reset only
2406 * by a system reset and cleared only when the register is read.
2407 *
2408 * Field Enumeration Values:
2409 *
2410 * Enum | Value | Description
2411 * :--------------------------------------------|:------|:-------------
2412 * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW | 0x1 | Underflow
2413 * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW | 0x0 | No Underflow
2414 *
2415 * Field Access Macros:
2416 *
2417 */
2418/*
2419 * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET
2420 *
2421 * Underflow
2422 */
2423#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1
2424/*
2425 * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET
2426 *
2427 * No Underflow
2428 */
2429#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0
2430
2431/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2432#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1
2433/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2434#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1
2435/* The width in bits of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2436#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1
2437/* The mask used to set the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */
2438#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002
2439/* The mask used to clear the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */
2440#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd
2441/* The reset value of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2442#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0
2443/* Extracts the ALT_QSPI_IRQSTAT_UNDERFLOWDET field value from a register. */
2444#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
2445/* Produces a ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value suitable for setting the register. */
2446#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
2447
2448/*
2449 * Field : Indirect Operation Complete - indopdone
2450 *
2451 * Controller has completed last triggered indirect operation
2452 *
2453 * Field Enumeration Values:
2454 *
2455 * Enum | Value | Description
2456 * :------------------------------------------|:------|:-----------------------------
2457 * ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP | 0x1 | Completed Indirect Operation
2458 * ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP | 0x0 | No Indirect Operation
2459 *
2460 * Field Access Macros:
2461 *
2462 */
2463/*
2464 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE
2465 *
2466 * Completed Indirect Operation
2467 */
2468#define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1
2469/*
2470 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE
2471 *
2472 * No Indirect Operation
2473 */
2474#define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0
2475
2476/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
2477#define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2
2478/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
2479#define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2
2480/* The width in bits of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
2481#define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1
2482/* The mask used to set the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */
2483#define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004
2484/* The mask used to clear the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */
2485#define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb
2486/* The reset value of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
2487#define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0
2488/* Extracts the ALT_QSPI_IRQSTAT_INDOPDONE field value from a register. */
2489#define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
2490/* Produces a ALT_QSPI_IRQSTAT_INDOPDONE register field value suitable for setting the register. */
2491#define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
2492
2493/*
2494 * Field : Indirect Read Reject - indrdreject
2495 *
2496 * Indirect operation was requested but could not be accepted. Two indirect
2497 * operations already in storage.
2498 *
2499 * Field Enumeration Values:
2500 *
2501 * Enum | Value | Description
2502 * :---------------------------------------------|:------|:-----------------------------
2503 * ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ | 0x1 | Indirect Operation Requested
2504 * ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ | 0x0 | No Indirect Operation
2505 *
2506 * Field Access Macros:
2507 *
2508 */
2509/*
2510 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT
2511 *
2512 * Indirect Operation Requested
2513 */
2514#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1
2515/*
2516 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT
2517 *
2518 * No Indirect Operation
2519 */
2520#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0
2521
2522/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
2523#define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3
2524/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
2525#define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3
2526/* The width in bits of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
2527#define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1
2528/* The mask used to set the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */
2529#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008
2530/* The mask used to clear the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */
2531#define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7
2532/* The reset value of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
2533#define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0
2534/* Extracts the ALT_QSPI_IRQSTAT_INDRDREJECT field value from a register. */
2535#define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
2536/* Produces a ALT_QSPI_IRQSTAT_INDRDREJECT register field value suitable for setting the register. */
2537#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
2538
2539/*
2540 * Field : Protected Area Write Attempt - protwrattempt
2541 *
2542 * Write to protected area was attempted and rejected.
2543 *
2544 * Field Enumeration Values:
2545 *
2546 * Enum | Value | Description
2547 * :------------------------------------------|:------|:--------------------------------
2548 * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT | 0x1 | Write Attempt to protected area
2549 * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT | 0x0 | No Write Attempt
2550 *
2551 * Field Access Macros:
2552 *
2553 */
2554/*
2555 * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT
2556 *
2557 * Write Attempt to protected area
2558 */
2559#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1
2560/*
2561 * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT
2562 *
2563 * No Write Attempt
2564 */
2565#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0
2566
2567/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
2568#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4
2569/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
2570#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4
2571/* The width in bits of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
2572#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1
2573/* The mask used to set the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */
2574#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010
2575/* The mask used to clear the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */
2576#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef
2577/* The reset value of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
2578#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0
2579/* Extracts the ALT_QSPI_IRQSTAT_PROTWRATTEMPT field value from a register. */
2580#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
2581/* Produces a ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value suitable for setting the register. */
2582#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
2583
2584/*
2585 * Field : Illegal AHB Access Detected - illegalacc
2586 *
2587 * Illegal AHB access has been detected. AHB wrapping bursts and the use of
2588 * SPLIT/RETRY accesses will cause this error interrupt to trigger.
2589 *
2590 * Field Enumeration Values:
2591 *
2592 * Enum | Value | Description
2593 * :-------------------------------------------|:------|:-----------------------
2594 * ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB | 0x1 | Illegal AHB attempt
2595 * ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB | 0x0 | No Illegal AHB attempt
2596 *
2597 * Field Access Macros:
2598 *
2599 */
2600/*
2601 * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC
2602 *
2603 * Illegal AHB attempt
2604 */
2605#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1
2606/*
2607 * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC
2608 *
2609 * No Illegal AHB attempt
2610 */
2611#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0
2612
2613/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
2614#define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5
2615/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
2616#define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5
2617/* The width in bits of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
2618#define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1
2619/* The mask used to set the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */
2620#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020
2621/* The mask used to clear the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */
2622#define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf
2623/* The reset value of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
2624#define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0
2625/* Extracts the ALT_QSPI_IRQSTAT_ILLEGALACC field value from a register. */
2626#define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
2627/* Produces a ALT_QSPI_IRQSTAT_ILLEGALACC register field value suitable for setting the register. */
2628#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
2629
2630/*
2631 * Field : Transfer Watermark Reached - indxfrlvl
2632 *
2633 * Indirect Transfer Watermark Level Reached
2634 *
2635 * Field Enumeration Values:
2636 *
2637 * Enum | Value | Description
2638 * :----------------------------------------|:------|:-----------------------
2639 * ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL | 0x1 | Water level reached
2640 * ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL | 0x0 | No water level reached
2641 *
2642 * Field Access Macros:
2643 *
2644 */
2645/*
2646 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL
2647 *
2648 * Water level reached
2649 */
2650#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1
2651/*
2652 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL
2653 *
2654 * No water level reached
2655 */
2656#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0
2657
2658/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
2659#define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6
2660/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
2661#define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6
2662/* The width in bits of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
2663#define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1
2664/* The mask used to set the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */
2665#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040
2666/* The mask used to clear the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */
2667#define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf
2668/* The reset value of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
2669#define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0
2670/* Extracts the ALT_QSPI_IRQSTAT_INDXFRLVL field value from a register. */
2671#define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
2672/* Produces a ALT_QSPI_IRQSTAT_INDXFRLVL register field value suitable for setting the register. */
2673#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
2674
2675/*
2676 * Field : Receive Overflow - rxover
2677 *
2678 * This should only occur in Legacy SPI mode. Set if an attempt is made to push the
2679 * RX FIFO when it is full. This bit is reset only by a system reset and cleared
2680 * only when this register is read. If a new push to the RX FIFO occurs coincident
2681 * with a register read this flag will remain set. 0 : no overflow has been
2682 * detected. 1 : an overflow has occurred.
2683 *
2684 * Field Enumeration Values:
2685 *
2686 * Enum | Value | Description
2687 * :------------------------------------|:------|:--------------------
2688 * ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER | 0x1 | Receive Overflow
2689 * ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER | 0x0 | No Receive Overflow
2690 *
2691 * Field Access Macros:
2692 *
2693 */
2694/*
2695 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER
2696 *
2697 * Receive Overflow
2698 */
2699#define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1
2700/*
2701 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER
2702 *
2703 * No Receive Overflow
2704 */
2705#define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0
2706
2707/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */
2708#define ALT_QSPI_IRQSTAT_RXOVER_LSB 7
2709/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */
2710#define ALT_QSPI_IRQSTAT_RXOVER_MSB 7
2711/* The width in bits of the ALT_QSPI_IRQSTAT_RXOVER register field. */
2712#define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1
2713/* The mask used to set the ALT_QSPI_IRQSTAT_RXOVER register field value. */
2714#define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080
2715/* The mask used to clear the ALT_QSPI_IRQSTAT_RXOVER register field value. */
2716#define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f
2717/* The reset value of the ALT_QSPI_IRQSTAT_RXOVER register field. */
2718#define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0
2719/* Extracts the ALT_QSPI_IRQSTAT_RXOVER field value from a register. */
2720#define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
2721/* Produces a ALT_QSPI_IRQSTAT_RXOVER register field value suitable for setting the register. */
2722#define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080)
2723
2724/*
2725 * Field : Transmit FIFO Compared to Threshold - txthreshcmp
2726 *
2727 * Indicates the number of entries in the transmit FIFO with respect to the
2728 * threshold specified in the TXTHRESH register. Only relevant in SPI legacy mode.
2729 *
2730 * Field Enumeration Values:
2731 *
2732 * Enum | Value | Description
2733 * :----------------------------------|:------|:-----------------------------
2734 * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT | 0x0 | FIFO has > TXTHRESH entries
2735 * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE | 0x1 | FIFO has <= TXTHRESH entries
2736 *
2737 * Field Access Macros:
2738 *
2739 */
2740/*
2741 * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP
2742 *
2743 * FIFO has > TXTHRESH entries
2744 */
2745#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0
2746/*
2747 * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP
2748 *
2749 * FIFO has <= TXTHRESH entries
2750 */
2751#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1
2752
2753/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
2754#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8
2755/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
2756#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8
2757/* The width in bits of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
2758#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1
2759/* The mask used to set the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */
2760#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100
2761/* The mask used to clear the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */
2762#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff
2763/* The reset value of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
2764#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1
2765/* Extracts the ALT_QSPI_IRQSTAT_TXTHRESHCMP field value from a register. */
2766#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
2767/* Produces a ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value suitable for setting the register. */
2768#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
2769
2770/*
2771 * Field : Transmit FIFO Full - txfull
2772 *
2773 * Indicates that the transmit FIFO is full or not. Only relevant in SPI legacy
2774 * mode.
2775 *
2776 * Field Enumeration Values:
2777 *
2778 * Enum | Value | Description
2779 * :----------------------------------|:------|:-----------------------
2780 * ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL | 0x0 | Transmit FIFO Not Full
2781 * ALT_QSPI_IRQSTAT_TXFULL_E_FULL | 0x1 | Transmit FIFO Full
2782 *
2783 * Field Access Macros:
2784 *
2785 */
2786/*
2787 * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL
2788 *
2789 * Transmit FIFO Not Full
2790 */
2791#define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0
2792/*
2793 * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL
2794 *
2795 * Transmit FIFO Full
2796 */
2797#define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1
2798
2799/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */
2800#define ALT_QSPI_IRQSTAT_TXFULL_LSB 9
2801/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */
2802#define ALT_QSPI_IRQSTAT_TXFULL_MSB 9
2803/* The width in bits of the ALT_QSPI_IRQSTAT_TXFULL register field. */
2804#define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1
2805/* The mask used to set the ALT_QSPI_IRQSTAT_TXFULL register field value. */
2806#define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200
2807/* The mask used to clear the ALT_QSPI_IRQSTAT_TXFULL register field value. */
2808#define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff
2809/* The reset value of the ALT_QSPI_IRQSTAT_TXFULL register field. */
2810#define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0
2811/* Extracts the ALT_QSPI_IRQSTAT_TXFULL field value from a register. */
2812#define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
2813/* Produces a ALT_QSPI_IRQSTAT_TXFULL register field value suitable for setting the register. */
2814#define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200)
2815
2816/*
2817 * Field : Receive FIFO Compared to Threshold - rxthreshcmp
2818 *
2819 * Indicates the number of entries in the receive FIFO with respect to the
2820 * threshold specified in the RXTHRESH register. Only relevant in SPI legacy mode.
2821 *
2822 * Field Enumeration Values:
2823 *
2824 * Enum | Value | Description
2825 * :----------------------------------|:------|:-----------------------------
2826 * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE | 0x0 | FIFO has <= RXTHRESH entries
2827 * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT | 0x1 | FIFO has > RXTHRESH entries
2828 *
2829 * Field Access Macros:
2830 *
2831 */
2832/*
2833 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP
2834 *
2835 * FIFO has <= RXTHRESH entries
2836 */
2837#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0
2838/*
2839 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP
2840 *
2841 * FIFO has > RXTHRESH entries
2842 */
2843#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1
2844
2845/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
2846#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10
2847/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
2848#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10
2849/* The width in bits of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
2850#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1
2851/* The mask used to set the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */
2852#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400
2853/* The mask used to clear the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */
2854#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff
2855/* The reset value of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
2856#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0
2857/* Extracts the ALT_QSPI_IRQSTAT_RXTHRESHCMP field value from a register. */
2858#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
2859/* Produces a ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value suitable for setting the register. */
2860#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
2861
2862/*
2863 * Field : Receive FIFO Full - rxfull
2864 *
2865 * Indicates that the receive FIFO is full or not. Only relevant in SPI legacy
2866 * mode.
2867 *
2868 * Field Enumeration Values:
2869 *
2870 * Enum | Value | Description
2871 * :----------------------------------|:------|:----------------------
2872 * ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL | 0x0 | Receive FIFO Not Full
2873 * ALT_QSPI_IRQSTAT_RXFULL_E_FULL | 0x1 | Receive FIFO Full
2874 *
2875 * Field Access Macros:
2876 *
2877 */
2878/*
2879 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL
2880 *
2881 * Receive FIFO Not Full
2882 */
2883#define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0
2884/*
2885 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL
2886 *
2887 * Receive FIFO Full
2888 */
2889#define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1
2890
2891/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */
2892#define ALT_QSPI_IRQSTAT_RXFULL_LSB 11
2893/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */
2894#define ALT_QSPI_IRQSTAT_RXFULL_MSB 11
2895/* The width in bits of the ALT_QSPI_IRQSTAT_RXFULL register field. */
2896#define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1
2897/* The mask used to set the ALT_QSPI_IRQSTAT_RXFULL register field value. */
2898#define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800
2899/* The mask used to clear the ALT_QSPI_IRQSTAT_RXFULL register field value. */
2900#define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff
2901/* The reset value of the ALT_QSPI_IRQSTAT_RXFULL register field. */
2902#define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0
2903/* Extracts the ALT_QSPI_IRQSTAT_RXFULL field value from a register. */
2904#define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
2905/* Produces a ALT_QSPI_IRQSTAT_RXFULL register field value suitable for setting the register. */
2906#define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800)
2907
2908/*
2909 * Field : Indirect Read Partition overflow - indsramfull
2910 *
2911 * Indirect Read Partition of SRAM is full and unable to immediately complete
2912 * indirect operation
2913 *
2914 * Field Enumeration Values:
2915 *
2916 * Enum | Value | Description
2917 * :---------------------------------------------|:------|:-----------------
2918 * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL | 0x1 | SRAM is full
2919 * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL | 0x0 | SRAM is not full
2920 *
2921 * Field Access Macros:
2922 *
2923 */
2924/*
2925 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL
2926 *
2927 * SRAM is full
2928 */
2929#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1
2930/*
2931 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL
2932 *
2933 * SRAM is not full
2934 */
2935#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0
2936
2937/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
2938#define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12
2939/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
2940#define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12
2941/* The width in bits of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
2942#define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1
2943/* The mask used to set the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */
2944#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000
2945/* The mask used to clear the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */
2946#define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff
2947/* The reset value of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
2948#define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0
2949/* Extracts the ALT_QSPI_IRQSTAT_INDSRAMFULL field value from a register. */
2950#define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
2951/* Produces a ALT_QSPI_IRQSTAT_INDSRAMFULL register field value suitable for setting the register. */
2952#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
2953
2954#ifndef __ASSEMBLY__
2955/*
2956 * WARNING: The C register and register group struct declarations are provided for
2957 * convenience and illustrative purposes. They should, however, be used with
2958 * caution as the C language standard provides no guarantees about the alignment or
2959 * atomicity of device memory accesses. The recommended practice for writing
2960 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2961 * alt_write_word() functions.
2962 *
2963 * The struct declaration for register ALT_QSPI_IRQSTAT.
2964 */
2965 struct ALT_QSPI_IRQSTAT_s
2966{
2967 uint32_t : 1; /* *UNDEFINED* */
2968 uint32_t underflowdet : 1; /* Underflow Detected */
2969 uint32_t indopdone : 1; /* Indirect Operation Complete */
2970 uint32_t indrdreject : 1; /* Indirect Read Reject */
2971 uint32_t protwrattempt : 1; /* Protected Area Write Attempt */
2972 uint32_t illegalacc : 1; /* Illegal AHB Access Detected */
2973 uint32_t indxfrlvl : 1; /* Transfer Watermark Reached */
2974 uint32_t rxover : 1; /* Receive Overflow */
2975 uint32_t txthreshcmp : 1; /* Transmit FIFO Compared to Threshold */
2976 uint32_t txfull : 1; /* Transmit FIFO Full */
2977 uint32_t rxthreshcmp : 1; /* Receive FIFO Compared to Threshold */
2978 uint32_t rxfull : 1; /* Receive FIFO Full */
2979 uint32_t indsramfull : 1; /* Indirect Read Partition overflow */
2980 uint32_t : 19; /* *UNDEFINED* */
2981};
2982
2983/* The typedef declaration for register ALT_QSPI_IRQSTAT. */
2984typedef volatile struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t;
2985#endif /* __ASSEMBLY__ */
2986
2987/* The byte offset of the ALT_QSPI_IRQSTAT register from the beginning of the component. */
2988#define ALT_QSPI_IRQSTAT_OFST 0x40
2989
2990/*
2991 * Register : Interrupt Mask - irqmask
2992 *
2993 * If disabled, the interrupt for the corresponding interrupt status register bit
2994 * is disabled. If enabled, the interrupt for the corresponding interrupt status
2995 * register bit is enabled.
2996 *
2997 * Register Layout
2998 *
2999 * Bits | Access | Reset | Description
3000 * :--------|:-------|:------|:--------------------------------------
3001 * [0] | ??? | 0x0 | *UNDEFINED*
3002 * [1] | RW | 0x0 | Underflow Detected Mask
3003 * [2] | RW | 0x0 | Mask
3004 * [3] | RW | 0x0 | Indirect Read Reject Mask
3005 * [4] | RW | 0x0 | Protected Area Write Attempt Mask
3006 * [5] | RW | 0x0 | Illegal Access Detected Mask
3007 * [6] | RW | 0x0 | Transfer Watermark Breach Mask
3008 * [7] | RW | 0x0 | Receive Overflow Mask
3009 * [8] | RW | 0x0 | Transmit FIFO Threshold Compare Mask
3010 * [9] | RW | 0x0 | Transmit FIFO Full Mask
3011 * [10] | RW | 0x0 | Receive FIFO Threshold Compare Mask
3012 * [11] | RW | 0x0 | Receive FIFO full Mask
3013 * [12] | RW | 0x0 | Indirect Read Partition overflow mask
3014 * [31:13] | ??? | 0x0 | *UNDEFINED*
3015 *
3016 */
3017/*
3018 * Field : Underflow Detected Mask - underflowdet
3019 *
3020 * Field Enumeration Values:
3021 *
3022 * Enum | Value | Description
3023 * :------------------------------------|:------|:-----------------------------
3024 * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD | 0x0 | Disable Interrupt by Masking
3025 * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END | 0x1 | Enable Interrupt
3026 *
3027 * Field Access Macros:
3028 *
3029 */
3030/*
3031 * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET
3032 *
3033 * Disable Interrupt by Masking
3034 */
3035#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0
3036/*
3037 * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET
3038 *
3039 * Enable Interrupt
3040 */
3041#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1
3042
3043/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
3044#define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1
3045/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
3046#define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1
3047/* The width in bits of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
3048#define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1
3049/* The mask used to set the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */
3050#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002
3051/* The mask used to clear the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */
3052#define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd
3053/* The reset value of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
3054#define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0
3055/* Extracts the ALT_QSPI_IRQMSK_UNDERFLOWDET field value from a register. */
3056#define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
3057/* Produces a ALT_QSPI_IRQMSK_UNDERFLOWDET register field value suitable for setting the register. */
3058#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
3059
3060/*
3061 * Field : Mask - indopdone
3062 *
3063 * Field Enumeration Values:
3064 *
3065 * Enum | Value | Description
3066 * :---------------------------------|:------|:-----------------------------
3067 * ALT_QSPI_IRQMSK_INDOPDONE_E_DISD | 0x0 | Disable Interrupt by Masking
3068 * ALT_QSPI_IRQMSK_INDOPDONE_E_END | 0x1 | Enable Interrupt
3069 *
3070 * Field Access Macros:
3071 *
3072 */
3073/*
3074 * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE
3075 *
3076 * Disable Interrupt by Masking
3077 */
3078#define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0
3079/*
3080 * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE
3081 *
3082 * Enable Interrupt
3083 */
3084#define ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1
3085
3086/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
3087#define ALT_QSPI_IRQMSK_INDOPDONE_LSB 2
3088/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
3089#define ALT_QSPI_IRQMSK_INDOPDONE_MSB 2
3090/* The width in bits of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
3091#define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1
3092/* The mask used to set the ALT_QSPI_IRQMSK_INDOPDONE register field value. */
3093#define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004
3094/* The mask used to clear the ALT_QSPI_IRQMSK_INDOPDONE register field value. */
3095#define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb
3096/* The reset value of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
3097#define ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0
3098/* Extracts the ALT_QSPI_IRQMSK_INDOPDONE field value from a register. */
3099#define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
3100/* Produces a ALT_QSPI_IRQMSK_INDOPDONE register field value suitable for setting the register. */
3101#define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
3102
3103/*
3104 * Field : Indirect Read Reject Mask - indrdreject
3105 *
3106 * Field Enumeration Values:
3107 *
3108 * Enum | Value | Description
3109 * :-----------------------------------|:------|:-----------------------------
3110 * ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD | 0x0 | Disable Interrupt by Masking
3111 * ALT_QSPI_IRQMSK_INDRDREJECT_E_END | 0x1 | Enable Interrupt
3112 *
3113 * Field Access Macros:
3114 *
3115 */
3116/*
3117 * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT
3118 *
3119 * Disable Interrupt by Masking
3120 */
3121#define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0
3122/*
3123 * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT
3124 *
3125 * Enable Interrupt
3126 */
3127#define ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1
3128
3129/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
3130#define ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3
3131/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
3132#define ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3
3133/* The width in bits of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
3134#define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1
3135/* The mask used to set the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */
3136#define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008
3137/* The mask used to clear the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */
3138#define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7
3139/* The reset value of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
3140#define ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0
3141/* Extracts the ALT_QSPI_IRQMSK_INDRDREJECT field value from a register. */
3142#define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
3143/* Produces a ALT_QSPI_IRQMSK_INDRDREJECT register field value suitable for setting the register. */
3144#define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
3145
3146/*
3147 * Field : Protected Area Write Attempt Mask - protwrattempt
3148 *
3149 * Field Enumeration Values:
3150 *
3151 * Enum | Value | Description
3152 * :-------------------------------------|:------|:-----------------------------
3153 * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD | 0x0 | Disable Interrupt by Masking
3154 * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END | 0x1 | Enable Interrupt
3155 *
3156 * Field Access Macros:
3157 *
3158 */
3159/*
3160 * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT
3161 *
3162 * Disable Interrupt by Masking
3163 */
3164#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0
3165/*
3166 * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT
3167 *
3168 * Enable Interrupt
3169 */
3170#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1
3171
3172/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
3173#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4
3174/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
3175#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4
3176/* The width in bits of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
3177#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1
3178/* The mask used to set the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */
3179#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010
3180/* The mask used to clear the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */
3181#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef
3182/* The reset value of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
3183#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0
3184/* Extracts the ALT_QSPI_IRQMSK_PROTWRATTEMPT field value from a register. */
3185#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
3186/* Produces a ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value suitable for setting the register. */
3187#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
3188
3189/*
3190 * Field : Illegal Access Detected Mask - illegalacc
3191 *
3192 * Field Enumeration Values:
3193 *
3194 * Enum | Value | Description
3195 * :----------------------------------|:------|:-----------------------------
3196 * ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD | 0x0 | Disable Interrupt by Masking
3197 * ALT_QSPI_IRQMSK_ILLEGALACC_E_END | 0x1 | Enable Interrupt
3198 *
3199 * Field Access Macros:
3200 *
3201 */
3202/*
3203 * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC
3204 *
3205 * Disable Interrupt by Masking
3206 */
3207#define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0
3208/*
3209 * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC
3210 *
3211 * Enable Interrupt
3212 */
3213#define ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1
3214
3215/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
3216#define ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5
3217/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
3218#define ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5
3219/* The width in bits of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
3220#define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1
3221/* The mask used to set the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */
3222#define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020
3223/* The mask used to clear the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */
3224#define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf
3225/* The reset value of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
3226#define ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0
3227/* Extracts the ALT_QSPI_IRQMSK_ILLEGALACC field value from a register. */
3228#define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
3229/* Produces a ALT_QSPI_IRQMSK_ILLEGALACC register field value suitable for setting the register. */
3230#define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
3231
3232/*
3233 * Field : Transfer Watermark Breach Mask - indxfrlvl
3234 *
3235 * Field Enumeration Values:
3236 *
3237 * Enum | Value | Description
3238 * :---------------------------------|:------|:-----------------------------
3239 * ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD | 0x0 | Disable Interrupt by Masking
3240 * ALT_QSPI_IRQMSK_INDXFRLVL_E_END | 0x1 | Enable Interrupt
3241 *
3242 * Field Access Macros:
3243 *
3244 */
3245/*
3246 * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL
3247 *
3248 * Disable Interrupt by Masking
3249 */
3250#define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0
3251/*
3252 * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL
3253 *
3254 * Enable Interrupt
3255 */
3256#define ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1
3257
3258/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
3259#define ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6
3260/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
3261#define ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6
3262/* The width in bits of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
3263#define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1
3264/* The mask used to set the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */
3265#define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040
3266/* The mask used to clear the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */
3267#define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf
3268/* The reset value of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
3269#define ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0
3270/* Extracts the ALT_QSPI_IRQMSK_INDXFRLVL field value from a register. */
3271#define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
3272/* Produces a ALT_QSPI_IRQMSK_INDXFRLVL register field value suitable for setting the register. */
3273#define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
3274
3275/*
3276 * Field : Receive Overflow Mask - rxover
3277 *
3278 * Field Enumeration Values:
3279 *
3280 * Enum | Value | Description
3281 * :------------------------------|:------|:-----------------------------
3282 * ALT_QSPI_IRQMSK_RXOVER_E_DISD | 0x0 | Disable Interrupt by Masking
3283 * ALT_QSPI_IRQMSK_RXOVER_E_END | 0x1 | Enable Interrupt
3284 *
3285 * Field Access Macros:
3286 *
3287 */
3288/*
3289 * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER
3290 *
3291 * Disable Interrupt by Masking
3292 */
3293#define ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0
3294/*
3295 * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER
3296 *
3297 * Enable Interrupt
3298 */
3299#define ALT_QSPI_IRQMSK_RXOVER_E_END 0x1
3300
3301/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */
3302#define ALT_QSPI_IRQMSK_RXOVER_LSB 7
3303/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */
3304#define ALT_QSPI_IRQMSK_RXOVER_MSB 7
3305/* The width in bits of the ALT_QSPI_IRQMSK_RXOVER register field. */
3306#define ALT_QSPI_IRQMSK_RXOVER_WIDTH 1
3307/* The mask used to set the ALT_QSPI_IRQMSK_RXOVER register field value. */
3308#define ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080
3309/* The mask used to clear the ALT_QSPI_IRQMSK_RXOVER register field value. */
3310#define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f
3311/* The reset value of the ALT_QSPI_IRQMSK_RXOVER register field. */
3312#define ALT_QSPI_IRQMSK_RXOVER_RESET 0x0
3313/* Extracts the ALT_QSPI_IRQMSK_RXOVER field value from a register. */
3314#define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
3315/* Produces a ALT_QSPI_IRQMSK_RXOVER register field value suitable for setting the register. */
3316#define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080)
3317
3318/*
3319 * Field : Transmit FIFO Threshold Compare Mask - txthreshcmp
3320 *
3321 * Field Enumeration Values:
3322 *
3323 * Enum | Value | Description
3324 * :-----------------------------------|:------|:-----------------------------
3325 * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking
3326 * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END | 0x1 | Enable Interrupt
3327 *
3328 * Field Access Macros:
3329 *
3330 */
3331/*
3332 * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP
3333 *
3334 * Disable Interrupt by Masking
3335 */
3336#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0
3337/*
3338 * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP
3339 *
3340 * Enable Interrupt
3341 */
3342#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1
3343
3344/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
3345#define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8
3346/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
3347#define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8
3348/* The width in bits of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
3349#define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1
3350/* The mask used to set the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */
3351#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100
3352/* The mask used to clear the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */
3353#define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff
3354/* The reset value of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
3355#define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0
3356/* Extracts the ALT_QSPI_IRQMSK_TXTHRESHCMP field value from a register. */
3357#define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
3358/* Produces a ALT_QSPI_IRQMSK_TXTHRESHCMP register field value suitable for setting the register. */
3359#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
3360
3361/*
3362 * Field : Transmit FIFO Full Mask - txfull
3363 *
3364 * Field Enumeration Values:
3365 *
3366 * Enum | Value | Description
3367 * :------------------------------|:------|:-----------------------------
3368 * ALT_QSPI_IRQMSK_TXFULL_E_DISD | 0x0 | Disable Interrupt by Masking
3369 * ALT_QSPI_IRQMSK_TXFULL_E_END | 0x1 | Enable Interrupt
3370 *
3371 * Field Access Macros:
3372 *
3373 */
3374/*
3375 * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL
3376 *
3377 * Disable Interrupt by Masking
3378 */
3379#define ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0
3380/*
3381 * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL
3382 *
3383 * Enable Interrupt
3384 */
3385#define ALT_QSPI_IRQMSK_TXFULL_E_END 0x1
3386
3387/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */
3388#define ALT_QSPI_IRQMSK_TXFULL_LSB 9
3389/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */
3390#define ALT_QSPI_IRQMSK_TXFULL_MSB 9
3391/* The width in bits of the ALT_QSPI_IRQMSK_TXFULL register field. */
3392#define ALT_QSPI_IRQMSK_TXFULL_WIDTH 1
3393/* The mask used to set the ALT_QSPI_IRQMSK_TXFULL register field value. */
3394#define ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200
3395/* The mask used to clear the ALT_QSPI_IRQMSK_TXFULL register field value. */
3396#define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff
3397/* The reset value of the ALT_QSPI_IRQMSK_TXFULL register field. */
3398#define ALT_QSPI_IRQMSK_TXFULL_RESET 0x0
3399/* Extracts the ALT_QSPI_IRQMSK_TXFULL field value from a register. */
3400#define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
3401/* Produces a ALT_QSPI_IRQMSK_TXFULL register field value suitable for setting the register. */
3402#define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200)
3403
3404/*
3405 * Field : Receive FIFO Threshold Compare Mask - rxthreshcmp
3406 *
3407 * Field Enumeration Values:
3408 *
3409 * Enum | Value | Description
3410 * :-----------------------------------|:------|:-----------------------------
3411 * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking
3412 * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END | 0x1 | Enable Interrupt
3413 *
3414 * Field Access Macros:
3415 *
3416 */
3417/*
3418 * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP
3419 *
3420 * Disable Interrupt by Masking
3421 */
3422#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0
3423/*
3424 * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP
3425 *
3426 * Enable Interrupt
3427 */
3428#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1
3429
3430/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
3431#define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10
3432/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
3433#define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10
3434/* The width in bits of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
3435#define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1
3436/* The mask used to set the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */
3437#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400
3438/* The mask used to clear the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */
3439#define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff
3440/* The reset value of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
3441#define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0
3442/* Extracts the ALT_QSPI_IRQMSK_RXTHRESHCMP field value from a register. */
3443#define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
3444/* Produces a ALT_QSPI_IRQMSK_RXTHRESHCMP register field value suitable for setting the register. */
3445#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
3446
3447/*
3448 * Field : Receive FIFO full Mask - rxfull
3449 *
3450 * Field Enumeration Values:
3451 *
3452 * Enum | Value | Description
3453 * :------------------------------|:------|:-----------------------------
3454 * ALT_QSPI_IRQMSK_RXFULL_E_DISD | 0x0 | Disable Interrupt by Masking
3455 * ALT_QSPI_IRQMSK_RXFULL_E_END | 0x1 | Enable Interrupt
3456 *
3457 * Field Access Macros:
3458 *
3459 */
3460/*
3461 * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL
3462 *
3463 * Disable Interrupt by Masking
3464 */
3465#define ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0
3466/*
3467 * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL
3468 *
3469 * Enable Interrupt
3470 */
3471#define ALT_QSPI_IRQMSK_RXFULL_E_END 0x1
3472
3473/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */
3474#define ALT_QSPI_IRQMSK_RXFULL_LSB 11
3475/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */
3476#define ALT_QSPI_IRQMSK_RXFULL_MSB 11
3477/* The width in bits of the ALT_QSPI_IRQMSK_RXFULL register field. */
3478#define ALT_QSPI_IRQMSK_RXFULL_WIDTH 1
3479/* The mask used to set the ALT_QSPI_IRQMSK_RXFULL register field value. */
3480#define ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800
3481/* The mask used to clear the ALT_QSPI_IRQMSK_RXFULL register field value. */
3482#define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff
3483/* The reset value of the ALT_QSPI_IRQMSK_RXFULL register field. */
3484#define ALT_QSPI_IRQMSK_RXFULL_RESET 0x0
3485/* Extracts the ALT_QSPI_IRQMSK_RXFULL field value from a register. */
3486#define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
3487/* Produces a ALT_QSPI_IRQMSK_RXFULL register field value suitable for setting the register. */
3488#define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800)
3489
3490/*
3491 * Field : Indirect Read Partition overflow mask - indsramfull
3492 *
3493 * Field Enumeration Values:
3494 *
3495 * Enum | Value | Description
3496 * :-----------------------------------|:------|:-----------------------------
3497 * ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD | 0x0 | Disable Interrupt by Masking
3498 * ALT_QSPI_IRQMSK_INDSRAMFULL_E_END | 0x1 | Enable Interrupt
3499 *
3500 * Field Access Macros:
3501 *
3502 */
3503/*
3504 * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL
3505 *
3506 * Disable Interrupt by Masking
3507 */
3508#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0
3509/*
3510 * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL
3511 *
3512 * Enable Interrupt
3513 */
3514#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1
3515
3516/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
3517#define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12
3518/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
3519#define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12
3520/* The width in bits of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
3521#define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1
3522/* The mask used to set the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */
3523#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000
3524/* The mask used to clear the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */
3525#define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff
3526/* The reset value of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
3527#define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0
3528/* Extracts the ALT_QSPI_IRQMSK_INDSRAMFULL field value from a register. */
3529#define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
3530/* Produces a ALT_QSPI_IRQMSK_INDSRAMFULL register field value suitable for setting the register. */
3531#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
3532
3533#ifndef __ASSEMBLY__
3534/*
3535 * WARNING: The C register and register group struct declarations are provided for
3536 * convenience and illustrative purposes. They should, however, be used with
3537 * caution as the C language standard provides no guarantees about the alignment or
3538 * atomicity of device memory accesses. The recommended practice for writing
3539 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3540 * alt_write_word() functions.
3541 *
3542 * The struct declaration for register ALT_QSPI_IRQMSK.
3543 */
3544 struct ALT_QSPI_IRQMSK_s
3545{
3546 uint32_t : 1; /* *UNDEFINED* */
3547 uint32_t underflowdet : 1; /* Underflow Detected Mask */
3548 uint32_t indopdone : 1; /* Mask */
3549 uint32_t indrdreject : 1; /* Indirect Read Reject Mask */
3550 uint32_t protwrattempt : 1; /* Protected Area Write Attempt Mask */
3551 uint32_t illegalacc : 1; /* Illegal Access Detected Mask */
3552 uint32_t indxfrlvl : 1; /* Transfer Watermark Breach Mask */
3553 uint32_t rxover : 1; /* Receive Overflow Mask */
3554 uint32_t txthreshcmp : 1; /* Transmit FIFO Threshold Compare Mask */
3555 uint32_t txfull : 1; /* Transmit FIFO Full Mask */
3556 uint32_t rxthreshcmp : 1; /* Receive FIFO Threshold Compare Mask */
3557 uint32_t rxfull : 1; /* Receive FIFO full Mask */
3558 uint32_t indsramfull : 1; /* Indirect Read Partition overflow mask */
3559 uint32_t : 19; /* *UNDEFINED* */
3560};
3561
3562/* The typedef declaration for register ALT_QSPI_IRQMSK. */
3563typedef volatile struct ALT_QSPI_IRQMSK_s ALT_QSPI_IRQMSK_t;
3564#endif /* __ASSEMBLY__ */
3565
3566/* The byte offset of the ALT_QSPI_IRQMSK register from the beginning of the component. */
3567#define ALT_QSPI_IRQMSK_OFST 0x44
3568
3569/*
3570 * Register : Lower Write Protection Register - lowwrprot
3571 *
3572 * Register Layout
3573 *
3574 * Bits | Access | Reset | Description
3575 * :-------|:-------|:------|:-------------
3576 * [31:0] | RW | 0x0 | Block Number
3577 *
3578 */
3579/*
3580 * Field : Block Number - subsector
3581 *
3582 * The block number that defines the lower block in the range of blocks that is to
3583 * be locked from writing. The definition of a block in terms of number of bytes is
3584 * programmable via the Device Size Configuration register.
3585 *
3586 * Field Access Macros:
3587 *
3588 */
3589/* The Least Significant Bit (LSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
3590#define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0
3591/* The Most Significant Bit (MSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
3592#define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31
3593/* The width in bits of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
3594#define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32
3595/* The mask used to set the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */
3596#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff
3597/* The mask used to clear the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */
3598#define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000
3599/* The reset value of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
3600#define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0
3601/* Extracts the ALT_QSPI_LOWWRPROT_SUBSECTOR field value from a register. */
3602#define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
3603/* Produces a ALT_QSPI_LOWWRPROT_SUBSECTOR register field value suitable for setting the register. */
3604#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
3605
3606#ifndef __ASSEMBLY__
3607/*
3608 * WARNING: The C register and register group struct declarations are provided for
3609 * convenience and illustrative purposes. They should, however, be used with
3610 * caution as the C language standard provides no guarantees about the alignment or
3611 * atomicity of device memory accesses. The recommended practice for writing
3612 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3613 * alt_write_word() functions.
3614 *
3615 * The struct declaration for register ALT_QSPI_LOWWRPROT.
3616 */
3617 struct ALT_QSPI_LOWWRPROT_s
3618{
3619 uint32_t subsector : 32; /* Block Number */
3620};
3621
3622/* The typedef declaration for register ALT_QSPI_LOWWRPROT. */
3623typedef volatile struct ALT_QSPI_LOWWRPROT_s ALT_QSPI_LOWWRPROT_t;
3624#endif /* __ASSEMBLY__ */
3625
3626/* The byte offset of the ALT_QSPI_LOWWRPROT register from the beginning of the component. */
3627#define ALT_QSPI_LOWWRPROT_OFST 0x50
3628
3629/*
3630 * Register : Upper Write Protection Register - uppwrprot
3631 *
3632 * Register Layout
3633 *
3634 * Bits | Access | Reset | Description
3635 * :-------|:-------|:------|:-------------
3636 * [31:0] | RW | 0x0 | Block Number
3637 *
3638 */
3639/*
3640 * Field : Block Number - subsector
3641 *
3642 * The block number that defines the upper block in the range of blocks that is to
3643 * be locked from writing. The definition of a block in terms of number of bytes is
3644 * programmable via the Device Size Configuration register.
3645 *
3646 * Field Access Macros:
3647 *
3648 */
3649/* The Least Significant Bit (LSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
3650#define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0
3651/* The Most Significant Bit (MSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
3652#define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31
3653/* The width in bits of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
3654#define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32
3655/* The mask used to set the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */
3656#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff
3657/* The mask used to clear the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */
3658#define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000
3659/* The reset value of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
3660#define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0
3661/* Extracts the ALT_QSPI_UPPWRPROT_SUBSECTOR field value from a register. */
3662#define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
3663/* Produces a ALT_QSPI_UPPWRPROT_SUBSECTOR register field value suitable for setting the register. */
3664#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
3665
3666#ifndef __ASSEMBLY__
3667/*
3668 * WARNING: The C register and register group struct declarations are provided for
3669 * convenience and illustrative purposes. They should, however, be used with
3670 * caution as the C language standard provides no guarantees about the alignment or
3671 * atomicity of device memory accesses. The recommended practice for writing
3672 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3673 * alt_write_word() functions.
3674 *
3675 * The struct declaration for register ALT_QSPI_UPPWRPROT.
3676 */
3677 struct ALT_QSPI_UPPWRPROT_s
3678{
3679 uint32_t subsector : 32; /* Block Number */
3680};
3681
3682/* The typedef declaration for register ALT_QSPI_UPPWRPROT. */
3683typedef volatile struct ALT_QSPI_UPPWRPROT_s ALT_QSPI_UPPWRPROT_t;
3684#endif /* __ASSEMBLY__ */
3685
3686/* The byte offset of the ALT_QSPI_UPPWRPROT register from the beginning of the component. */
3687#define ALT_QSPI_UPPWRPROT_OFST 0x54
3688
3689/*
3690 * Register : Write Protection Register - wrprot
3691 *
3692 * Register Layout
3693 *
3694 * Bits | Access | Reset | Description
3695 * :-------|:-------|:------|:-------------------------------
3696 * [0] | RW | 0x0 | Write Protection Inversion Bit
3697 * [1] | RW | 0x0 | Write Protection Enable Bit
3698 * [31:2] | ??? | 0x0 | *UNDEFINED*
3699 *
3700 */
3701/*
3702 * Field : Write Protection Inversion Bit - inv
3703 *
3704 * When enabled, the protection region defined in the lower and upper write
3705 * protection registers is inverted meaning it is the region that the system is
3706 * permitted to write to. When disabled, the protection region defined in the lower
3707 * and upper write protection registers is the region that the system is not
3708 * permitted to write to.
3709 *
3710 * Field Enumeration Values:
3711 *
3712 * Enum | Value | Description
3713 * :--------------------------|:------|:-------------------------
3714 * ALT_QSPI_WRPROT_INV_E_EN | 0x1 | Write Region allowed
3715 * ALT_QSPI_WRPROT_INV_E_DIS | 0x0 | Write Region not allowed
3716 *
3717 * Field Access Macros:
3718 *
3719 */
3720/*
3721 * Enumerated value for register field ALT_QSPI_WRPROT_INV
3722 *
3723 * Write Region allowed
3724 */
3725#define ALT_QSPI_WRPROT_INV_E_EN 0x1
3726/*
3727 * Enumerated value for register field ALT_QSPI_WRPROT_INV
3728 *
3729 * Write Region not allowed
3730 */
3731#define ALT_QSPI_WRPROT_INV_E_DIS 0x0
3732
3733/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_INV register field. */
3734#define ALT_QSPI_WRPROT_INV_LSB 0
3735/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_INV register field. */
3736#define ALT_QSPI_WRPROT_INV_MSB 0
3737/* The width in bits of the ALT_QSPI_WRPROT_INV register field. */
3738#define ALT_QSPI_WRPROT_INV_WIDTH 1
3739/* The mask used to set the ALT_QSPI_WRPROT_INV register field value. */
3740#define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001
3741/* The mask used to clear the ALT_QSPI_WRPROT_INV register field value. */
3742#define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe
3743/* The reset value of the ALT_QSPI_WRPROT_INV register field. */
3744#define ALT_QSPI_WRPROT_INV_RESET 0x0
3745/* Extracts the ALT_QSPI_WRPROT_INV field value from a register. */
3746#define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0)
3747/* Produces a ALT_QSPI_WRPROT_INV register field value suitable for setting the register. */
3748#define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001)
3749
3750/*
3751 * Field : Write Protection Enable Bit - en
3752 *
3753 * When enabled, any AHB write access with an address within the protection region
3754 * defined in the lower and upper write protection registers is rejected. An AHB
3755 * error response is generated and an interrupt source triggered. When disabled,
3756 * the protection region is disabled.
3757 *
3758 * Field Enumeration Values:
3759 *
3760 * Enum | Value | Description
3761 * :-------------------------|:------|:---------------------------
3762 * ALT_QSPI_WRPROT_EN_E_EN | 0x1 | AHB Write Access rejected
3763 * ALT_QSPI_WRPROT_EN_E_DIS | 0x0 | Protection Region Disabled
3764 *
3765 * Field Access Macros:
3766 *
3767 */
3768/*
3769 * Enumerated value for register field ALT_QSPI_WRPROT_EN
3770 *
3771 * AHB Write Access rejected
3772 */
3773#define ALT_QSPI_WRPROT_EN_E_EN 0x1
3774/*
3775 * Enumerated value for register field ALT_QSPI_WRPROT_EN
3776 *
3777 * Protection Region Disabled
3778 */
3779#define ALT_QSPI_WRPROT_EN_E_DIS 0x0
3780
3781/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_EN register field. */
3782#define ALT_QSPI_WRPROT_EN_LSB 1
3783/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_EN register field. */
3784#define ALT_QSPI_WRPROT_EN_MSB 1
3785/* The width in bits of the ALT_QSPI_WRPROT_EN register field. */
3786#define ALT_QSPI_WRPROT_EN_WIDTH 1
3787/* The mask used to set the ALT_QSPI_WRPROT_EN register field value. */
3788#define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002
3789/* The mask used to clear the ALT_QSPI_WRPROT_EN register field value. */
3790#define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd
3791/* The reset value of the ALT_QSPI_WRPROT_EN register field. */
3792#define ALT_QSPI_WRPROT_EN_RESET 0x0
3793/* Extracts the ALT_QSPI_WRPROT_EN field value from a register. */
3794#define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1)
3795/* Produces a ALT_QSPI_WRPROT_EN register field value suitable for setting the register. */
3796#define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002)
3797
3798#ifndef __ASSEMBLY__
3799/*
3800 * WARNING: The C register and register group struct declarations are provided for
3801 * convenience and illustrative purposes. They should, however, be used with
3802 * caution as the C language standard provides no guarantees about the alignment or
3803 * atomicity of device memory accesses. The recommended practice for writing
3804 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3805 * alt_write_word() functions.
3806 *
3807 * The struct declaration for register ALT_QSPI_WRPROT.
3808 */
3809 struct ALT_QSPI_WRPROT_s
3810{
3811 uint32_t inv : 1; /* Write Protection Inversion Bit */
3812 uint32_t en : 1; /* Write Protection Enable Bit */
3813 uint32_t : 30; /* *UNDEFINED* */
3814};
3815
3816/* The typedef declaration for register ALT_QSPI_WRPROT. */
3817typedef volatile struct ALT_QSPI_WRPROT_s ALT_QSPI_WRPROT_t;
3818#endif /* __ASSEMBLY__ */
3819
3820/* The byte offset of the ALT_QSPI_WRPROT register from the beginning of the component. */
3821#define ALT_QSPI_WRPROT_OFST 0x58
3822
3823/*
3824 * Register : Indirect Read Transfer Register - indrd
3825 *
3826 * Register Layout
3827 *
3828 * Bits | Access | Reset | Description
3829 * :-------|:-------|:--------|:--------------------------------
3830 * [0] | RW | 0x0 | Start Indirect Read
3831 * [1] | RW | 0x0 | Cancel Indirect Read
3832 * [2] | R | Unknown | Indirect Read Status
3833 * [3] | RW | Unknown | SRAM Full
3834 * [4] | R | Unknown | Queued Indirect Read Operations
3835 * [5] | RW | Unknown | Indirect Completion Status
3836 * [7:6] | R | Unknown | Completed Indirect Operations
3837 * [31:8] | ??? | 0x0 | *UNDEFINED*
3838 *
3839 */
3840/*
3841 * Field : Start Indirect Read - start
3842 *
3843 * When this bit is enabled, it will trigger an indirect read operation. The
3844 * assumption is that the indirect start address and the indirect number of bytes
3845 * register is setup before triggering the indirect read operation.
3846 *
3847 * Field Enumeration Values:
3848 *
3849 * Enum | Value | Description
3850 * :----------------------------|:------|:----------------------
3851 * ALT_QSPI_INDRD_START_E_END | 0x1 | Trigger Indirect Read
3852 * ALT_QSPI_INDRD_START_E_DISD | 0x0 | No Indirect Read
3853 *
3854 * Field Access Macros:
3855 *
3856 */
3857/*
3858 * Enumerated value for register field ALT_QSPI_INDRD_START
3859 *
3860 * Trigger Indirect Read
3861 */
3862#define ALT_QSPI_INDRD_START_E_END 0x1
3863/*
3864 * Enumerated value for register field ALT_QSPI_INDRD_START
3865 *
3866 * No Indirect Read
3867 */
3868#define ALT_QSPI_INDRD_START_E_DISD 0x0
3869
3870/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_START register field. */
3871#define ALT_QSPI_INDRD_START_LSB 0
3872/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_START register field. */
3873#define ALT_QSPI_INDRD_START_MSB 0
3874/* The width in bits of the ALT_QSPI_INDRD_START register field. */
3875#define ALT_QSPI_INDRD_START_WIDTH 1
3876/* The mask used to set the ALT_QSPI_INDRD_START register field value. */
3877#define ALT_QSPI_INDRD_START_SET_MSK 0x00000001
3878/* The mask used to clear the ALT_QSPI_INDRD_START register field value. */
3879#define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe
3880/* The reset value of the ALT_QSPI_INDRD_START register field. */
3881#define ALT_QSPI_INDRD_START_RESET 0x0
3882/* Extracts the ALT_QSPI_INDRD_START field value from a register. */
3883#define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0)
3884/* Produces a ALT_QSPI_INDRD_START register field value suitable for setting the register. */
3885#define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001)
3886
3887/*
3888 * Field : Cancel Indirect Read - cancel
3889 *
3890 * This bit will cancel all ongoing indirect read operations.
3891 *
3892 * Field Enumeration Values:
3893 *
3894 * Enum | Value | Description
3895 * :---------------------------------|:------|:----------------------------
3896 * ALT_QSPI_INDRD_CANCEL_E_CANCEL | 0x1 | Cancel Indirect Read
3897 * ALT_QSPI_INDRD_CANCEL_E_NOACTION | 0x0 | Do Not Cancel Indirect Read
3898 *
3899 * Field Access Macros:
3900 *
3901 */
3902/*
3903 * Enumerated value for register field ALT_QSPI_INDRD_CANCEL
3904 *
3905 * Cancel Indirect Read
3906 */
3907#define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1
3908/*
3909 * Enumerated value for register field ALT_QSPI_INDRD_CANCEL
3910 *
3911 * Do Not Cancel Indirect Read
3912 */
3913#define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0
3914
3915/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_CANCEL register field. */
3916#define ALT_QSPI_INDRD_CANCEL_LSB 1
3917/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_CANCEL register field. */
3918#define ALT_QSPI_INDRD_CANCEL_MSB 1
3919/* The width in bits of the ALT_QSPI_INDRD_CANCEL register field. */
3920#define ALT_QSPI_INDRD_CANCEL_WIDTH 1
3921/* The mask used to set the ALT_QSPI_INDRD_CANCEL register field value. */
3922#define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002
3923/* The mask used to clear the ALT_QSPI_INDRD_CANCEL register field value. */
3924#define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd
3925/* The reset value of the ALT_QSPI_INDRD_CANCEL register field. */
3926#define ALT_QSPI_INDRD_CANCEL_RESET 0x0
3927/* Extracts the ALT_QSPI_INDRD_CANCEL field value from a register. */
3928#define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
3929/* Produces a ALT_QSPI_INDRD_CANCEL register field value suitable for setting the register. */
3930#define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002)
3931
3932/*
3933 * Field : Indirect Read Status - rd_status
3934 *
3935 * Indirect read operation in progress (status)
3936 *
3937 * Field Enumeration Values:
3938 *
3939 * Enum | Value | Description
3940 * :----------------------------------|:------|:------------------------------
3941 * ALT_QSPI_INDRD_RD_STAT_E_RDOP | 0x1 | Read Operation in progress
3942 * ALT_QSPI_INDRD_RD_STAT_E_NOACTION | 0x0 | No read operation in progress
3943 *
3944 * Field Access Macros:
3945 *
3946 */
3947/*
3948 * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT
3949 *
3950 * Read Operation in progress
3951 */
3952#define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1
3953/*
3954 * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT
3955 *
3956 * No read operation in progress
3957 */
3958#define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0
3959
3960/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */
3961#define ALT_QSPI_INDRD_RD_STAT_LSB 2
3962/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */
3963#define ALT_QSPI_INDRD_RD_STAT_MSB 2
3964/* The width in bits of the ALT_QSPI_INDRD_RD_STAT register field. */
3965#define ALT_QSPI_INDRD_RD_STAT_WIDTH 1
3966/* The mask used to set the ALT_QSPI_INDRD_RD_STAT register field value. */
3967#define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004
3968/* The mask used to clear the ALT_QSPI_INDRD_RD_STAT register field value. */
3969#define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb
3970/* The reset value of the ALT_QSPI_INDRD_RD_STAT register field is UNKNOWN. */
3971#define ALT_QSPI_INDRD_RD_STAT_RESET 0x0
3972/* Extracts the ALT_QSPI_INDRD_RD_STAT field value from a register. */
3973#define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2)
3974/* Produces a ALT_QSPI_INDRD_RD_STAT register field value suitable for setting the register. */
3975#define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004)
3976
3977/*
3978 * Field : SRAM Full - sram_full
3979 *
3980 * SRAM full and unable to immediately complete an indirect operation. Write a 1 to
3981 * this field to clear it. ; indirect operation (status)
3982 *
3983 * Field Enumeration Values:
3984 *
3985 * Enum | Value | Description
3986 * :------------------------------------|:------|:-----------------------------------
3987 * ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL | 0x1 | Sram Full- Cant complete operation
3988 * ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION | 0x0 | SRram Not Full
3989 *
3990 * Field Access Macros:
3991 *
3992 */
3993/*
3994 * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL
3995 *
3996 * Sram Full- Cant complete operation
3997 */
3998#define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1
3999/*
4000 * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL
4001 *
4002 * SRram Not Full
4003 */
4004#define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0
4005
4006/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */
4007#define ALT_QSPI_INDRD_SRAM_FULL_LSB 3
4008/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */
4009#define ALT_QSPI_INDRD_SRAM_FULL_MSB 3
4010/* The width in bits of the ALT_QSPI_INDRD_SRAM_FULL register field. */
4011#define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1
4012/* The mask used to set the ALT_QSPI_INDRD_SRAM_FULL register field value. */
4013#define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008
4014/* The mask used to clear the ALT_QSPI_INDRD_SRAM_FULL register field value. */
4015#define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7
4016/* The reset value of the ALT_QSPI_INDRD_SRAM_FULL register field is UNKNOWN. */
4017#define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0
4018/* Extracts the ALT_QSPI_INDRD_SRAM_FULL field value from a register. */
4019#define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3)
4020/* Produces a ALT_QSPI_INDRD_SRAM_FULL register field value suitable for setting the register. */
4021#define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008)
4022
4023/*
4024 * Field : Queued Indirect Read Operations - rd_queued
4025 *
4026 * Two indirect read operations have been queued
4027 *
4028 * Field Enumeration Values:
4029 *
4030 * Enum | Value | Description
4031 * :----------------------------------------|:------|:---------------------
4032 * ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD | 0x1 | Queued Indirect Read
4033 * ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION | 0x0 | No Queued Read
4034 *
4035 * Field Access Macros:
4036 *
4037 */
4038/*
4039 * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED
4040 *
4041 * Queued Indirect Read
4042 */
4043#define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1
4044/*
4045 * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED
4046 *
4047 * No Queued Read
4048 */
4049#define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0
4050
4051/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */
4052#define ALT_QSPI_INDRD_RD_QUEUED_LSB 4
4053/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */
4054#define ALT_QSPI_INDRD_RD_QUEUED_MSB 4
4055/* The width in bits of the ALT_QSPI_INDRD_RD_QUEUED register field. */
4056#define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1
4057/* The mask used to set the ALT_QSPI_INDRD_RD_QUEUED register field value. */
4058#define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010
4059/* The mask used to clear the ALT_QSPI_INDRD_RD_QUEUED register field value. */
4060#define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef
4061/* The reset value of the ALT_QSPI_INDRD_RD_QUEUED register field is UNKNOWN. */
4062#define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0
4063/* Extracts the ALT_QSPI_INDRD_RD_QUEUED field value from a register. */
4064#define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4)
4065/* Produces a ALT_QSPI_INDRD_RD_QUEUED register field value suitable for setting the register. */
4066#define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010)
4067
4068/*
4069 * Field : Indirect Completion Status - ind_ops_done_status
4070 *
4071 * This field is set to 1 when an indirect operation has completed. Write a 1 to
4072 * this field to clear it.
4073 *
4074 * Field Enumeration Values:
4075 *
4076 * Enum | Value | Description
4077 * :--------------------------------------------|:------|:-------------------------------
4078 * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP | 0x1 | Indirect Op Complete operation
4079 * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION | 0x0 | Indirect Op Not Complete
4080 *
4081 * Field Access Macros:
4082 *
4083 */
4084/*
4085 * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT
4086 *
4087 * Indirect Op Complete operation
4088 */
4089#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1
4090/*
4091 * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT
4092 *
4093 * Indirect Op Not Complete
4094 */
4095#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0
4096
4097/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */
4098#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5
4099/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */
4100#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5
4101/* The width in bits of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */
4102#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1
4103/* The mask used to set the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */
4104#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020
4105/* The mask used to clear the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */
4106#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf
4107/* The reset value of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field is UNKNOWN. */
4108#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0
4109/* Extracts the ALT_QSPI_INDRD_IND_OPS_DONE_STAT field value from a register. */
4110#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5)
4111/* Produces a ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value suitable for setting the register. */
4112#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020)
4113
4114/*
4115 * Field : Completed Indirect Operations - num_ind_ops_done
4116 *
4117 * This field contains the number of indirect operations which have been completed.
4118 * This is used in conjunction with the indirect completion status field (bit 5).
4119 *
4120 * Field Access Macros:
4121 *
4122 */
4123/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
4124#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6
4125/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
4126#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7
4127/* The width in bits of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
4128#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2
4129/* The mask used to set the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */
4130#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0
4131/* The mask used to clear the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */
4132#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f
4133/* The reset value of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field is UNKNOWN. */
4134#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0
4135/* Extracts the ALT_QSPI_INDRD_NUM_IND_OPS_DONE field value from a register. */
4136#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6)
4137/* Produces a ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value suitable for setting the register. */
4138#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0)
4139
4140#ifndef __ASSEMBLY__
4141/*
4142 * WARNING: The C register and register group struct declarations are provided for
4143 * convenience and illustrative purposes. They should, however, be used with
4144 * caution as the C language standard provides no guarantees about the alignment or
4145 * atomicity of device memory accesses. The recommended practice for writing
4146 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4147 * alt_write_word() functions.
4148 *
4149 * The struct declaration for register ALT_QSPI_INDRD.
4150 */
4151 struct ALT_QSPI_INDRD_s
4152{
4153 uint32_t start : 1; /* Start Indirect Read */
4154 uint32_t cancel : 1; /* Cancel Indirect Read */
4155 const uint32_t rd_status : 1; /* Indirect Read Status */
4156 uint32_t sram_full : 1; /* SRAM Full */
4157 const uint32_t rd_queued : 1; /* Queued Indirect Read Operations */
4158 uint32_t ind_ops_done_status : 1; /* Indirect Completion Status */
4159 const uint32_t num_ind_ops_done : 2; /* Completed Indirect Operations */
4160 uint32_t : 24; /* *UNDEFINED* */
4161};
4162
4163/* The typedef declaration for register ALT_QSPI_INDRD. */
4164typedef volatile struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t;
4165#endif /* __ASSEMBLY__ */
4166
4167/* The byte offset of the ALT_QSPI_INDRD register from the beginning of the component. */
4168#define ALT_QSPI_INDRD_OFST 0x60
4169
4170/*
4171 * Register : Indirect Read Transfer Watermark Register - indrdwater
4172 *
4173 * Register Layout
4174 *
4175 * Bits | Access | Reset | Description
4176 * :-------|:-------|:------|:----------------
4177 * [31:0] | RW | 0x0 | Watermark Value
4178 *
4179 */
4180/*
4181 * Field : Watermark Value - level
4182 *
4183 * This represents the minimum fill level of the SRAM before a DMA peripheral
4184 * access is permitted. When the SRAM fill level passes the watermark, an interrupt
4185 * is also generated. This field can be disabled by writing a value of all zeroes.
4186 * The units of this register are BYTES
4187 *
4188 * Field Access Macros:
4189 *
4190 */
4191/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4192#define ALT_QSPI_INDRDWATER_LEVEL_LSB 0
4193/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4194#define ALT_QSPI_INDRDWATER_LEVEL_MSB 31
4195/* The width in bits of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4196#define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32
4197/* The mask used to set the ALT_QSPI_INDRDWATER_LEVEL register field value. */
4198#define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff
4199/* The mask used to clear the ALT_QSPI_INDRDWATER_LEVEL register field value. */
4200#define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000
4201/* The reset value of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4202#define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0
4203/* Extracts the ALT_QSPI_INDRDWATER_LEVEL field value from a register. */
4204#define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
4205/* Produces a ALT_QSPI_INDRDWATER_LEVEL register field value suitable for setting the register. */
4206#define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
4207
4208#ifndef __ASSEMBLY__
4209/*
4210 * WARNING: The C register and register group struct declarations are provided for
4211 * convenience and illustrative purposes. They should, however, be used with
4212 * caution as the C language standard provides no guarantees about the alignment or
4213 * atomicity of device memory accesses. The recommended practice for writing
4214 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4215 * alt_write_word() functions.
4216 *
4217 * The struct declaration for register ALT_QSPI_INDRDWATER.
4218 */
4219 struct ALT_QSPI_INDRDWATER_s
4220{
4221 uint32_t level : 32; /* Watermark Value */
4222};
4223
4224/* The typedef declaration for register ALT_QSPI_INDRDWATER. */
4225typedef volatile struct ALT_QSPI_INDRDWATER_s ALT_QSPI_INDRDWATER_t;
4226#endif /* __ASSEMBLY__ */
4227
4228/* The byte offset of the ALT_QSPI_INDRDWATER register from the beginning of the component. */
4229#define ALT_QSPI_INDRDWATER_OFST 0x64
4230
4231/*
4232 * Register : Indirect Read Transfer Start Address Register - indrdstaddr
4233 *
4234 * Register Layout
4235 *
4236 * Bits | Access | Reset | Description
4237 * :-------|:-------|:------|:---------------------------------
4238 * [31:0] | RW | 0x0 | Start Address of Indirect Access
4239 *
4240 */
4241/*
4242 * Field : Start Address of Indirect Access - addr
4243 *
4244 * This is the start address from which the indirect access will commence its READ
4245 * operation.
4246 *
4247 * Field Access Macros:
4248 *
4249 */
4250/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4251#define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0
4252/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4253#define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31
4254/* The width in bits of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4255#define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32
4256/* The mask used to set the ALT_QSPI_INDRDSTADDR_ADDR register field value. */
4257#define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff
4258/* The mask used to clear the ALT_QSPI_INDRDSTADDR_ADDR register field value. */
4259#define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000
4260/* The reset value of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4261#define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0
4262/* Extracts the ALT_QSPI_INDRDSTADDR_ADDR field value from a register. */
4263#define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4264/* Produces a ALT_QSPI_INDRDSTADDR_ADDR register field value suitable for setting the register. */
4265#define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4266
4267#ifndef __ASSEMBLY__
4268/*
4269 * WARNING: The C register and register group struct declarations are provided for
4270 * convenience and illustrative purposes. They should, however, be used with
4271 * caution as the C language standard provides no guarantees about the alignment or
4272 * atomicity of device memory accesses. The recommended practice for writing
4273 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4274 * alt_write_word() functions.
4275 *
4276 * The struct declaration for register ALT_QSPI_INDRDSTADDR.
4277 */
4278 struct ALT_QSPI_INDRDSTADDR_s
4279{
4280 uint32_t addr : 32; /* Start Address of Indirect Access */
4281};
4282
4283/* The typedef declaration for register ALT_QSPI_INDRDSTADDR. */
4284typedef volatile struct ALT_QSPI_INDRDSTADDR_s ALT_QSPI_INDRDSTADDR_t;
4285#endif /* __ASSEMBLY__ */
4286
4287/* The byte offset of the ALT_QSPI_INDRDSTADDR register from the beginning of the component. */
4288#define ALT_QSPI_INDRDSTADDR_OFST 0x68
4289
4290/*
4291 * Register : Indirect Read Transfer Number Bytes Register - indrdcnt
4292 *
4293 * Register Layout
4294 *
4295 * Bits | Access | Reset | Description
4296 * :-------|:-------|:------|:---------------
4297 * [31:0] | RW | 0x0 | Indirect Count
4298 *
4299 */
4300/*
4301 * Field : Indirect Count - value
4302 *
4303 * This is the number of bytes that the indirect access will consume. This can be
4304 * bigger than the configured size of SRAM.
4305 *
4306 * Field Access Macros:
4307 *
4308 */
4309/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */
4310#define ALT_QSPI_INDRDCNT_VALUE_LSB 0
4311/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */
4312#define ALT_QSPI_INDRDCNT_VALUE_MSB 31
4313/* The width in bits of the ALT_QSPI_INDRDCNT_VALUE register field. */
4314#define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32
4315/* The mask used to set the ALT_QSPI_INDRDCNT_VALUE register field value. */
4316#define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff
4317/* The mask used to clear the ALT_QSPI_INDRDCNT_VALUE register field value. */
4318#define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000
4319/* The reset value of the ALT_QSPI_INDRDCNT_VALUE register field. */
4320#define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0
4321/* Extracts the ALT_QSPI_INDRDCNT_VALUE field value from a register. */
4322#define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4323/* Produces a ALT_QSPI_INDRDCNT_VALUE register field value suitable for setting the register. */
4324#define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4325
4326#ifndef __ASSEMBLY__
4327/*
4328 * WARNING: The C register and register group struct declarations are provided for
4329 * convenience and illustrative purposes. They should, however, be used with
4330 * caution as the C language standard provides no guarantees about the alignment or
4331 * atomicity of device memory accesses. The recommended practice for writing
4332 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4333 * alt_write_word() functions.
4334 *
4335 * The struct declaration for register ALT_QSPI_INDRDCNT.
4336 */
4337 struct ALT_QSPI_INDRDCNT_s
4338{
4339 uint32_t value : 32; /* Indirect Count */
4340};
4341
4342/* The typedef declaration for register ALT_QSPI_INDRDCNT. */
4343typedef volatile struct ALT_QSPI_INDRDCNT_s ALT_QSPI_INDRDCNT_t;
4344#endif /* __ASSEMBLY__ */
4345
4346/* The byte offset of the ALT_QSPI_INDRDCNT register from the beginning of the component. */
4347#define ALT_QSPI_INDRDCNT_OFST 0x6c
4348
4349/*
4350 * Register : Indirect Write Transfer Register - indwr
4351 *
4352 * Register Layout
4353 *
4354 * Bits | Access | Reset | Description
4355 * :-------|:-------|:--------|:---------------------------------
4356 * [0] | RW | 0x0 | Start Indirect Write
4357 * [1] | RW | 0x0 | Cancel Indirect Write
4358 * [2] | R | Unknown | Indirect Write Status
4359 * [3] | R | 0x0 | Reserved
4360 * [4] | R | Unknown | Queued Indirect Write Operations
4361 * [5] | RW | Unknown | Indirect Completion Status
4362 * [7:6] | R | Unknown | Completed Indirect Operations
4363 * [31:8] | ??? | 0x0 | *UNDEFINED*
4364 *
4365 */
4366/*
4367 * Field : Start Indirect Write - start
4368 *
4369 * Writing a 1 to this bit will trigger an indirect write operation. The assumption
4370 * is that the indirect start address and the indirect number of bytes register is
4371 * setup before triggering the indirect write operation.
4372 *
4373 * Field Enumeration Values:
4374 *
4375 * Enum | Value | Description
4376 * :----------------------------|:------|:---------------------------------
4377 * ALT_QSPI_INDWR_START_E_END | 0x1 | Trigger indirect write operation
4378 * ALT_QSPI_INDWR_START_E_DISD | 0x0 | No Action
4379 *
4380 * Field Access Macros:
4381 *
4382 */
4383/*
4384 * Enumerated value for register field ALT_QSPI_INDWR_START
4385 *
4386 * Trigger indirect write operation
4387 */
4388#define ALT_QSPI_INDWR_START_E_END 0x1
4389/*
4390 * Enumerated value for register field ALT_QSPI_INDWR_START
4391 *
4392 * No Action
4393 */
4394#define ALT_QSPI_INDWR_START_E_DISD 0x0
4395
4396/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_START register field. */
4397#define ALT_QSPI_INDWR_START_LSB 0
4398/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_START register field. */
4399#define ALT_QSPI_INDWR_START_MSB 0
4400/* The width in bits of the ALT_QSPI_INDWR_START register field. */
4401#define ALT_QSPI_INDWR_START_WIDTH 1
4402/* The mask used to set the ALT_QSPI_INDWR_START register field value. */
4403#define ALT_QSPI_INDWR_START_SET_MSK 0x00000001
4404/* The mask used to clear the ALT_QSPI_INDWR_START register field value. */
4405#define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe
4406/* The reset value of the ALT_QSPI_INDWR_START register field. */
4407#define ALT_QSPI_INDWR_START_RESET 0x0
4408/* Extracts the ALT_QSPI_INDWR_START field value from a register. */
4409#define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0)
4410/* Produces a ALT_QSPI_INDWR_START register field value suitable for setting the register. */
4411#define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001)
4412
4413/*
4414 * Field : Cancel Indirect Write - cancel
4415 *
4416 * Writing a 1 to this bit will cancel all ongoing indirect write operations.
4417 *
4418 * Field Enumeration Values:
4419 *
4420 * Enum | Value | Description
4421 * :-----------------------------------|:------|:--------------------------------
4422 * ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR | 0x1 | Cancel Indirect write operation
4423 * ALT_QSPI_INDWR_CANCEL_E_NOACTION | 0x0 | No Action
4424 *
4425 * Field Access Macros:
4426 *
4427 */
4428/*
4429 * Enumerated value for register field ALT_QSPI_INDWR_CANCEL
4430 *
4431 * Cancel Indirect write operation
4432 */
4433#define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1
4434/*
4435 * Enumerated value for register field ALT_QSPI_INDWR_CANCEL
4436 *
4437 * No Action
4438 */
4439#define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0
4440
4441/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_CANCEL register field. */
4442#define ALT_QSPI_INDWR_CANCEL_LSB 1
4443/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_CANCEL register field. */
4444#define ALT_QSPI_INDWR_CANCEL_MSB 1
4445/* The width in bits of the ALT_QSPI_INDWR_CANCEL register field. */
4446#define ALT_QSPI_INDWR_CANCEL_WIDTH 1
4447/* The mask used to set the ALT_QSPI_INDWR_CANCEL register field value. */
4448#define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002
4449/* The mask used to clear the ALT_QSPI_INDWR_CANCEL register field value. */
4450#define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd
4451/* The reset value of the ALT_QSPI_INDWR_CANCEL register field. */
4452#define ALT_QSPI_INDWR_CANCEL_RESET 0x0
4453/* Extracts the ALT_QSPI_INDWR_CANCEL field value from a register. */
4454#define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
4455/* Produces a ALT_QSPI_INDWR_CANCEL register field value suitable for setting the register. */
4456#define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002)
4457
4458/*
4459 * Field : Indirect Write Status - rdstat
4460 *
4461 * Indirect write operation in progress (status)
4462 *
4463 * Field Enumeration Values:
4464 *
4465 * Enum | Value | Description
4466 * :----------------------------------|:------|:-------------------------
4467 * ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT | 0x1 | Indirect write operation
4468 * ALT_QSPI_INDWR_RDSTAT_E_NOACTION | 0x0 | No Action
4469 *
4470 * Field Access Macros:
4471 *
4472 */
4473/*
4474 * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT
4475 *
4476 * Indirect write operation
4477 */
4478#define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1
4479/*
4480 * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT
4481 *
4482 * No Action
4483 */
4484#define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0
4485
4486/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */
4487#define ALT_QSPI_INDWR_RDSTAT_LSB 2
4488/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */
4489#define ALT_QSPI_INDWR_RDSTAT_MSB 2
4490/* The width in bits of the ALT_QSPI_INDWR_RDSTAT register field. */
4491#define ALT_QSPI_INDWR_RDSTAT_WIDTH 1
4492/* The mask used to set the ALT_QSPI_INDWR_RDSTAT register field value. */
4493#define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004
4494/* The mask used to clear the ALT_QSPI_INDWR_RDSTAT register field value. */
4495#define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb
4496/* The reset value of the ALT_QSPI_INDWR_RDSTAT register field is UNKNOWN. */
4497#define ALT_QSPI_INDWR_RDSTAT_RESET 0x0
4498/* Extracts the ALT_QSPI_INDWR_RDSTAT field value from a register. */
4499#define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2)
4500/* Produces a ALT_QSPI_INDWR_RDSTAT register field value suitable for setting the register. */
4501#define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004)
4502
4503/*
4504 * Field : Reserved - sramfull
4505 *
4506 * Field Access Macros:
4507 *
4508 */
4509/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */
4510#define ALT_QSPI_INDWR_SRAMFULL_LSB 3
4511/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */
4512#define ALT_QSPI_INDWR_SRAMFULL_MSB 3
4513/* The width in bits of the ALT_QSPI_INDWR_SRAMFULL register field. */
4514#define ALT_QSPI_INDWR_SRAMFULL_WIDTH 1
4515/* The mask used to set the ALT_QSPI_INDWR_SRAMFULL register field value. */
4516#define ALT_QSPI_INDWR_SRAMFULL_SET_MSK 0x00000008
4517/* The mask used to clear the ALT_QSPI_INDWR_SRAMFULL register field value. */
4518#define ALT_QSPI_INDWR_SRAMFULL_CLR_MSK 0xfffffff7
4519/* The reset value of the ALT_QSPI_INDWR_SRAMFULL register field. */
4520#define ALT_QSPI_INDWR_SRAMFULL_RESET 0x0
4521/* Extracts the ALT_QSPI_INDWR_SRAMFULL field value from a register. */
4522#define ALT_QSPI_INDWR_SRAMFULL_GET(value) (((value) & 0x00000008) >> 3)
4523/* Produces a ALT_QSPI_INDWR_SRAMFULL register field value suitable for setting the register. */
4524#define ALT_QSPI_INDWR_SRAMFULL_SET(value) (((value) << 3) & 0x00000008)
4525
4526/*
4527 * Field : Queued Indirect Write Operations - rdqueued
4528 *
4529 * Two indirect write operations have been queued
4530 *
4531 * Field Enumeration Values:
4532 *
4533 * Enum | Value | Description
4534 * :-----------------------------------|:------|:-----------------------------
4535 * ALT_QSPI_INDWR_RDQUEUED_E_INDWROP | 0x1 | Two Indirect write operation
4536 * ALT_QSPI_INDWR_RDQUEUED_E_NOACTION | 0x0 | No Action
4537 *
4538 * Field Access Macros:
4539 *
4540 */
4541/*
4542 * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED
4543 *
4544 * Two Indirect write operation
4545 */
4546#define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1
4547/*
4548 * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED
4549 *
4550 * No Action
4551 */
4552#define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0
4553
4554/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */
4555#define ALT_QSPI_INDWR_RDQUEUED_LSB 4
4556/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */
4557#define ALT_QSPI_INDWR_RDQUEUED_MSB 4
4558/* The width in bits of the ALT_QSPI_INDWR_RDQUEUED register field. */
4559#define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1
4560/* The mask used to set the ALT_QSPI_INDWR_RDQUEUED register field value. */
4561#define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010
4562/* The mask used to clear the ALT_QSPI_INDWR_RDQUEUED register field value. */
4563#define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef
4564/* The reset value of the ALT_QSPI_INDWR_RDQUEUED register field is UNKNOWN. */
4565#define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0
4566/* Extracts the ALT_QSPI_INDWR_RDQUEUED field value from a register. */
4567#define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4)
4568/* Produces a ALT_QSPI_INDWR_RDQUEUED register field value suitable for setting the register. */
4569#define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010)
4570
4571/*
4572 * Field : Indirect Completion Status - inddone
4573 *
4574 * This field is set to 1 when an indirect operation has completed. Write a 1 to
4575 * this field to clear it.
4576 *
4577 * Field Enumeration Values:
4578 *
4579 * Enum | Value | Description
4580 * :-----------------------------------|:------|:-----------------------------
4581 * ALT_QSPI_INDWR_INDDONE_E_INDCOMPST | 0x1 | Indirect operation completed
4582 * ALT_QSPI_INDWR_INDDONE_E_NOACTION | 0x0 | No Action
4583 *
4584 * Field Access Macros:
4585 *
4586 */
4587/*
4588 * Enumerated value for register field ALT_QSPI_INDWR_INDDONE
4589 *
4590 * Indirect operation completed
4591 */
4592#define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1
4593/*
4594 * Enumerated value for register field ALT_QSPI_INDWR_INDDONE
4595 *
4596 * No Action
4597 */
4598#define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0
4599
4600/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDDONE register field. */
4601#define ALT_QSPI_INDWR_INDDONE_LSB 5
4602/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDDONE register field. */
4603#define ALT_QSPI_INDWR_INDDONE_MSB 5
4604/* The width in bits of the ALT_QSPI_INDWR_INDDONE register field. */
4605#define ALT_QSPI_INDWR_INDDONE_WIDTH 1
4606/* The mask used to set the ALT_QSPI_INDWR_INDDONE register field value. */
4607#define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020
4608/* The mask used to clear the ALT_QSPI_INDWR_INDDONE register field value. */
4609#define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf
4610/* The reset value of the ALT_QSPI_INDWR_INDDONE register field is UNKNOWN. */
4611#define ALT_QSPI_INDWR_INDDONE_RESET 0x0
4612/* Extracts the ALT_QSPI_INDWR_INDDONE field value from a register. */
4613#define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5)
4614/* Produces a ALT_QSPI_INDWR_INDDONE register field value suitable for setting the register. */
4615#define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020)
4616
4617/*
4618 * Field : Completed Indirect Operations - indcnt
4619 *
4620 * This field contains the count of indirect operations which have been completed.
4621 * This is used in conjunction with the indirect completion status field (bit 5).
4622 *
4623 * Field Access Macros:
4624 *
4625 */
4626/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDCNT register field. */
4627#define ALT_QSPI_INDWR_INDCNT_LSB 6
4628/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDCNT register field. */
4629#define ALT_QSPI_INDWR_INDCNT_MSB 7
4630/* The width in bits of the ALT_QSPI_INDWR_INDCNT register field. */
4631#define ALT_QSPI_INDWR_INDCNT_WIDTH 2
4632/* The mask used to set the ALT_QSPI_INDWR_INDCNT register field value. */
4633#define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0
4634/* The mask used to clear the ALT_QSPI_INDWR_INDCNT register field value. */
4635#define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f
4636/* The reset value of the ALT_QSPI_INDWR_INDCNT register field is UNKNOWN. */
4637#define ALT_QSPI_INDWR_INDCNT_RESET 0x0
4638/* Extracts the ALT_QSPI_INDWR_INDCNT field value from a register. */
4639#define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6)
4640/* Produces a ALT_QSPI_INDWR_INDCNT register field value suitable for setting the register. */
4641#define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0)
4642
4643#ifndef __ASSEMBLY__
4644/*
4645 * WARNING: The C register and register group struct declarations are provided for
4646 * convenience and illustrative purposes. They should, however, be used with
4647 * caution as the C language standard provides no guarantees about the alignment or
4648 * atomicity of device memory accesses. The recommended practice for writing
4649 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4650 * alt_write_word() functions.
4651 *
4652 * The struct declaration for register ALT_QSPI_INDWR.
4653 */
4654 struct ALT_QSPI_INDWR_s
4655{
4656 uint32_t start : 1; /* Start Indirect Write */
4657 uint32_t cancel : 1; /* Cancel Indirect Write */
4658 const uint32_t rdstat : 1; /* Indirect Write Status */
4659 const uint32_t sramfull : 1; /* Reserved */
4660 const uint32_t rdqueued : 1; /* Queued Indirect Write Operations */
4661 uint32_t inddone : 1; /* Indirect Completion Status */
4662 const uint32_t indcnt : 2; /* Completed Indirect Operations */
4663 uint32_t : 24; /* *UNDEFINED* */
4664};
4665
4666/* The typedef declaration for register ALT_QSPI_INDWR. */
4667typedef volatile struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t;
4668#endif /* __ASSEMBLY__ */
4669
4670/* The byte offset of the ALT_QSPI_INDWR register from the beginning of the component. */
4671#define ALT_QSPI_INDWR_OFST 0x70
4672
4673/*
4674 * Register : Indirect Write Transfer Watermark Register - indwrwater
4675 *
4676 * Register Layout
4677 *
4678 * Bits | Access | Reset | Description
4679 * :-------|:-------|:-----------|:----------------
4680 * [31:0] | RW | 0xffffffff | Watermark Value
4681 *
4682 */
4683/*
4684 * Field : Watermark Value - level
4685 *
4686 * This represents the maximum fill level of the SRAM before a DMA peripheral
4687 * access is permitted. When the SRAM fill level falls below the watermark, an
4688 * interrupt is also generated. This field can be disabled by writing a value of
4689 * all ones. The units of this register are bytes.
4690 *
4691 * Field Access Macros:
4692 *
4693 */
4694/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */
4695#define ALT_QSPI_INDWRWATER_LEVEL_LSB 0
4696/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */
4697#define ALT_QSPI_INDWRWATER_LEVEL_MSB 31
4698/* The width in bits of the ALT_QSPI_INDWRWATER_LEVEL register field. */
4699#define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32
4700/* The mask used to set the ALT_QSPI_INDWRWATER_LEVEL register field value. */
4701#define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff
4702/* The mask used to clear the ALT_QSPI_INDWRWATER_LEVEL register field value. */
4703#define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000
4704/* The reset value of the ALT_QSPI_INDWRWATER_LEVEL register field. */
4705#define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff
4706/* Extracts the ALT_QSPI_INDWRWATER_LEVEL field value from a register. */
4707#define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
4708/* Produces a ALT_QSPI_INDWRWATER_LEVEL register field value suitable for setting the register. */
4709#define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
4710
4711#ifndef __ASSEMBLY__
4712/*
4713 * WARNING: The C register and register group struct declarations are provided for
4714 * convenience and illustrative purposes. They should, however, be used with
4715 * caution as the C language standard provides no guarantees about the alignment or
4716 * atomicity of device memory accesses. The recommended practice for writing
4717 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4718 * alt_write_word() functions.
4719 *
4720 * The struct declaration for register ALT_QSPI_INDWRWATER.
4721 */
4722 struct ALT_QSPI_INDWRWATER_s
4723{
4724 uint32_t level : 32; /* Watermark Value */
4725};
4726
4727/* The typedef declaration for register ALT_QSPI_INDWRWATER. */
4728typedef volatile struct ALT_QSPI_INDWRWATER_s ALT_QSPI_INDWRWATER_t;
4729#endif /* __ASSEMBLY__ */
4730
4731/* The byte offset of the ALT_QSPI_INDWRWATER register from the beginning of the component. */
4732#define ALT_QSPI_INDWRWATER_OFST 0x74
4733
4734/*
4735 * Register : Indirect Write Transfer Start Address Register - indwrstaddr
4736 *
4737 * Register Layout
4738 *
4739 * Bits | Access | Reset | Description
4740 * :-------|:-------|:------|:-------------------------
4741 * [31:0] | RW | 0x0 | Start of Indirect Access
4742 *
4743 */
4744/*
4745 * Field : Start of Indirect Access - addr
4746 *
4747 * This is the start address from which the indirect access will commence its write
4748 * operation.
4749 *
4750 * Field Access Macros:
4751 *
4752 */
4753/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
4754#define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0
4755/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
4756#define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31
4757/* The width in bits of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
4758#define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32
4759/* The mask used to set the ALT_QSPI_INDWRSTADDR_ADDR register field value. */
4760#define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff
4761/* The mask used to clear the ALT_QSPI_INDWRSTADDR_ADDR register field value. */
4762#define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000
4763/* The reset value of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
4764#define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0
4765/* Extracts the ALT_QSPI_INDWRSTADDR_ADDR field value from a register. */
4766#define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4767/* Produces a ALT_QSPI_INDWRSTADDR_ADDR register field value suitable for setting the register. */
4768#define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4769
4770#ifndef __ASSEMBLY__
4771/*
4772 * WARNING: The C register and register group struct declarations are provided for
4773 * convenience and illustrative purposes. They should, however, be used with
4774 * caution as the C language standard provides no guarantees about the alignment or
4775 * atomicity of device memory accesses. The recommended practice for writing
4776 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4777 * alt_write_word() functions.
4778 *
4779 * The struct declaration for register ALT_QSPI_INDWRSTADDR.
4780 */
4781 struct ALT_QSPI_INDWRSTADDR_s
4782{
4783 uint32_t addr : 32; /* Start of Indirect Access */
4784};
4785
4786/* The typedef declaration for register ALT_QSPI_INDWRSTADDR. */
4787typedef volatile struct ALT_QSPI_INDWRSTADDR_s ALT_QSPI_INDWRSTADDR_t;
4788#endif /* __ASSEMBLY__ */
4789
4790/* The byte offset of the ALT_QSPI_INDWRSTADDR register from the beginning of the component. */
4791#define ALT_QSPI_INDWRSTADDR_OFST 0x78
4792
4793/*
4794 * Register : Indirect Write Transfer Count Register - indwrcnt
4795 *
4796 * Register Layout
4797 *
4798 * Bits | Access | Reset | Description
4799 * :-------|:-------|:------|:-------------------------
4800 * [31:0] | RW | 0x0 | Indirect Number of Bytes
4801 *
4802 */
4803/*
4804 * Field : Indirect Number of Bytes - value
4805 *
4806 * This is the number of bytes that the indirect access will consume. This can be
4807 * bigger than the configured size of SRAM.
4808 *
4809 * Field Access Macros:
4810 *
4811 */
4812/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */
4813#define ALT_QSPI_INDWRCNT_VALUE_LSB 0
4814/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */
4815#define ALT_QSPI_INDWRCNT_VALUE_MSB 31
4816/* The width in bits of the ALT_QSPI_INDWRCNT_VALUE register field. */
4817#define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32
4818/* The mask used to set the ALT_QSPI_INDWRCNT_VALUE register field value. */
4819#define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff
4820/* The mask used to clear the ALT_QSPI_INDWRCNT_VALUE register field value. */
4821#define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000
4822/* The reset value of the ALT_QSPI_INDWRCNT_VALUE register field. */
4823#define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0
4824/* Extracts the ALT_QSPI_INDWRCNT_VALUE field value from a register. */
4825#define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4826/* Produces a ALT_QSPI_INDWRCNT_VALUE register field value suitable for setting the register. */
4827#define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4828
4829#ifndef __ASSEMBLY__
4830/*
4831 * WARNING: The C register and register group struct declarations are provided for
4832 * convenience and illustrative purposes. They should, however, be used with
4833 * caution as the C language standard provides no guarantees about the alignment or
4834 * atomicity of device memory accesses. The recommended practice for writing
4835 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4836 * alt_write_word() functions.
4837 *
4838 * The struct declaration for register ALT_QSPI_INDWRCNT.
4839 */
4840 struct ALT_QSPI_INDWRCNT_s
4841{
4842 uint32_t value : 32; /* Indirect Number of Bytes */
4843};
4844
4845/* The typedef declaration for register ALT_QSPI_INDWRCNT. */
4846typedef volatile struct ALT_QSPI_INDWRCNT_s ALT_QSPI_INDWRCNT_t;
4847#endif /* __ASSEMBLY__ */
4848
4849/* The byte offset of the ALT_QSPI_INDWRCNT register from the beginning of the component. */
4850#define ALT_QSPI_INDWRCNT_OFST 0x7c
4851
4852/*
4853 * Register : Flash Command Register - flashcmd
4854 *
4855 * Register Layout
4856 *
4857 * Bits | Access | Reset | Description
4858 * :--------|:-------|:------|:---------------------------
4859 * [0] | RW | 0x0 | Execute Command
4860 * [1] | R | 0x0 | Command Execution Status
4861 * [6:2] | ??? | 0x0 | *UNDEFINED*
4862 * [11:7] | RW | 0x0 | Number of Dummy Bytes
4863 * [14:12] | RW | 0x0 | Number of Write Data Bytes
4864 * [15] | RW | 0x0 | Write Data Enable
4865 * [17:16] | RW | 0x0 | Number of Address Bytes
4866 * [18] | RW | 0x0 | Mode Bit Enable
4867 * [19] | RW | 0x0 | Command Address Enable
4868 * [22:20] | RW | 0x0 | Number of Read Data Bytes
4869 * [23] | RW | 0x0 | Read Data Enable
4870 * [31:24] | RW | 0x0 | Command Opcode
4871 *
4872 */
4873/*
4874 * Field : Execute Command - execcmd
4875 *
4876 * Execute the command.
4877 *
4878 * Field Enumeration Values:
4879 *
4880 * Enum | Value | Description
4881 * :------------------------------------|:------|:----------------
4882 * ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE | 0x1 | Execute Command
4883 * ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION | 0x0 | No Action
4884 *
4885 * Field Access Macros:
4886 *
4887 */
4888/*
4889 * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD
4890 *
4891 * Execute Command
4892 */
4893#define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1
4894/*
4895 * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD
4896 *
4897 * No Action
4898 */
4899#define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0
4900
4901/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
4902#define ALT_QSPI_FLSHCMD_EXECCMD_LSB 0
4903/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
4904#define ALT_QSPI_FLSHCMD_EXECCMD_MSB 0
4905/* The width in bits of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
4906#define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1
4907/* The mask used to set the ALT_QSPI_FLSHCMD_EXECCMD register field value. */
4908#define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001
4909/* The mask used to clear the ALT_QSPI_FLSHCMD_EXECCMD register field value. */
4910#define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe
4911/* The reset value of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
4912#define ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0
4913/* Extracts the ALT_QSPI_FLSHCMD_EXECCMD field value from a register. */
4914#define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0)
4915/* Produces a ALT_QSPI_FLSHCMD_EXECCMD register field value suitable for setting the register. */
4916#define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001)
4917
4918/*
4919 * Field : Command Execution Status - cmdexecstat
4920 *
4921 * Command execution in progress.
4922 *
4923 * Field Enumeration Values:
4924 *
4925 * Enum | Value | Description
4926 * :-------------------------------------------|:------|:-------------------------
4927 * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT | 0x1 | Command Execution Status
4928 * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION | 0x0 | No Action
4929 *
4930 * Field Access Macros:
4931 *
4932 */
4933/*
4934 * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT
4935 *
4936 * Command Execution Status
4937 */
4938#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1
4939/*
4940 * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT
4941 *
4942 * No Action
4943 */
4944#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0
4945
4946/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
4947#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1
4948/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
4949#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1
4950/* The width in bits of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
4951#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1
4952/* The mask used to set the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */
4953#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002
4954/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */
4955#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd
4956/* The reset value of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
4957#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0
4958/* Extracts the ALT_QSPI_FLSHCMD_CMDEXECSTAT field value from a register. */
4959#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1)
4960/* Produces a ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value suitable for setting the register. */
4961#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002)
4962
4963/*
4964 * Field : Number of Dummy Bytes - numdummybytes
4965 *
4966 * Set to the number of dummy bytes required This should be setup before triggering
4967 * the command via the execute field of this register.
4968 *
4969 * Field Access Macros:
4970 *
4971 */
4972/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
4973#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7
4974/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
4975#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11
4976/* The width in bits of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
4977#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5
4978/* The mask used to set the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */
4979#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80
4980/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */
4981#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f
4982/* The reset value of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
4983#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0
4984/* Extracts the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES field value from a register. */
4985#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7)
4986/* Produces a ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value suitable for setting the register. */
4987#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80)
4988
4989/*
4990 * Field : Number of Write Data Bytes - numwrdatabytes
4991 *
4992 * Up to 8 Data bytes may be written using this command.
4993 *
4994 * Field Enumeration Values:
4995 *
4996 * Enum | Value | Description
4997 * :------------------------------------------|:------|:-------------
4998 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 | 0x0 | Write 1 Byte
4999 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 | 0x1 | Write 2 Byte
5000 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 | 0x2 | Write 3 Byte
5001 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 | 0x3 | Write 4 Byte
5002 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 | 0x4 | Write 5 Byte
5003 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 | 0x5 | Write 6 Byte
5004 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 | 0x6 | Write 7 Byte
5005 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 | 0x7 | Write 8 Byte
5006 *
5007 * Field Access Macros:
5008 *
5009 */
5010/*
5011 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5012 *
5013 * Write 1 Byte
5014 */
5015#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0
5016/*
5017 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5018 *
5019 * Write 2 Byte
5020 */
5021#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1
5022/*
5023 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5024 *
5025 * Write 3 Byte
5026 */
5027#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2
5028/*
5029 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5030 *
5031 * Write 4 Byte
5032 */
5033#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3
5034/*
5035 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5036 *
5037 * Write 5 Byte
5038 */
5039#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4
5040/*
5041 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5042 *
5043 * Write 6 Byte
5044 */
5045#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5
5046/*
5047 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5048 *
5049 * Write 7 Byte
5050 */
5051#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6
5052/*
5053 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5054 *
5055 * Write 8 Byte
5056 */
5057#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7
5058
5059/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
5060#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12
5061/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
5062#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14
5063/* The width in bits of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
5064#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3
5065/* The mask used to set the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */
5066#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000
5067/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */
5068#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff
5069/* The reset value of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
5070#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0
5071/* Extracts the ALT_QSPI_FLSHCMD_NUMWRDATABYTES field value from a register. */
5072#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12)
5073/* Produces a ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value suitable for setting the register. */
5074#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000)
5075
5076/*
5077 * Field : Write Data Enable - enwrdata
5078 *
5079 * Set to 1 if the command specified in the command opcode field requires write
5080 * data bytes to be sent to the device.
5081 *
5082 * Field Enumeration Values:
5083 *
5084 * Enum | Value | Description
5085 * :----------------------------------------|:------|:----------------------------------
5086 * ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES | 0x1 | Command requires write data bytes
5087 * ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION | 0x0 | No Action
5088 *
5089 * Field Access Macros:
5090 *
5091 */
5092/*
5093 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA
5094 *
5095 * Command requires write data bytes
5096 */
5097#define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1
5098/*
5099 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA
5100 *
5101 * No Action
5102 */
5103#define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0
5104
5105/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
5106#define ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15
5107/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
5108#define ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15
5109/* The width in bits of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
5110#define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1
5111/* The mask used to set the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */
5112#define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000
5113/* The mask used to clear the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */
5114#define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff
5115/* The reset value of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
5116#define ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0
5117/* Extracts the ALT_QSPI_FLSHCMD_ENWRDATA field value from a register. */
5118#define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15)
5119/* Produces a ALT_QSPI_FLSHCMD_ENWRDATA register field value suitable for setting the register. */
5120#define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000)
5121
5122/*
5123 * Field : Number of Address Bytes - numaddrbytes
5124 *
5125 * Set to the number of address bytes required (the address itself is programmed in
5126 * the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the
5127 * command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address
5128 * bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes
5129 *
5130 * Field Enumeration Values:
5131 *
5132 * Enum | Value | Description
5133 * :------------------------------------------|:------|:----------------------
5134 * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 | 0x0 | Write 1 Address Byte
5135 * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 | 0x1 | Write 2 Address Bytes
5136 * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 | 0x2 | Write 3 Address Bytes
5137 * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 | 0x3 | Write 4 Address Bytes
5138 *
5139 * Field Access Macros:
5140 *
5141 */
5142/*
5143 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
5144 *
5145 * Write 1 Address Byte
5146 */
5147#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0
5148/*
5149 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
5150 *
5151 * Write 2 Address Bytes
5152 */
5153#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1
5154/*
5155 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
5156 *
5157 * Write 3 Address Bytes
5158 */
5159#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2
5160/*
5161 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
5162 *
5163 * Write 4 Address Bytes
5164 */
5165#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3
5166
5167/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
5168#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16
5169/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
5170#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17
5171/* The width in bits of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
5172#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2
5173/* The mask used to set the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */
5174#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000
5175/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */
5176#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff
5177/* The reset value of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
5178#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0
5179/* Extracts the ALT_QSPI_FLSHCMD_NUMADDRBYTES field value from a register. */
5180#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16)
5181/* Produces a ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value suitable for setting the register. */
5182#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000)
5183
5184/*
5185 * Field : Mode Bit Enable - enmodebit
5186 *
5187 * Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration
5188 * register are sent following the address bytes.
5189 *
5190 * Field Enumeration Values:
5191 *
5192 * Enum | Value | Description
5193 * :---------------------------------|:------|:-------------------------------
5194 * ALT_QSPI_FLSHCMD_ENMODBIT_E_END | 0x1 | Mode Bit follows address bytes
5195 * ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD | 0x0 | No Action
5196 *
5197 * Field Access Macros:
5198 *
5199 */
5200/*
5201 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT
5202 *
5203 * Mode Bit follows address bytes
5204 */
5205#define ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1
5206/*
5207 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT
5208 *
5209 * No Action
5210 */
5211#define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0
5212
5213/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
5214#define ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18
5215/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
5216#define ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18
5217/* The width in bits of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
5218#define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1
5219/* The mask used to set the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */
5220#define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000
5221/* The mask used to clear the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */
5222#define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff
5223/* The reset value of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
5224#define ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0
5225/* Extracts the ALT_QSPI_FLSHCMD_ENMODBIT field value from a register. */
5226#define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18)
5227/* Produces a ALT_QSPI_FLSHCMD_ENMODBIT register field value suitable for setting the register. */
5228#define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000)
5229
5230/*
5231 * Field : Command Address Enable - encmdaddr
5232 *
5233 * If enabled, the command specified in bits 31:24 requires an address. This should
5234 * be setup before triggering the command via writing a 1 to the execute field.
5235 *
5236 * Field Enumeration Values:
5237 *
5238 * Enum | Value | Description
5239 * :----------------------------------|:------|:---------------------------------------
5240 * ALT_QSPI_FLSHCMD_ENCMDADDR_E_END | 0x1 | Command in bits 31:24 requires address
5241 * ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD | 0x0 | No Action
5242 *
5243 * Field Access Macros:
5244 *
5245 */
5246/*
5247 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR
5248 *
5249 * Command in bits 31:24 requires address
5250 */
5251#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1
5252/*
5253 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR
5254 *
5255 * No Action
5256 */
5257#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0
5258
5259/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
5260#define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19
5261/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
5262#define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19
5263/* The width in bits of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
5264#define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1
5265/* The mask used to set the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */
5266#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000
5267/* The mask used to clear the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */
5268#define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff
5269/* The reset value of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
5270#define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0
5271/* Extracts the ALT_QSPI_FLSHCMD_ENCMDADDR field value from a register. */
5272#define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19)
5273/* Produces a ALT_QSPI_FLSHCMD_ENCMDADDR register field value suitable for setting the register. */
5274#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000)
5275
5276/*
5277 * Field : Number of Read Data Bytes - numrddatabytes
5278 *
5279 * Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for
5280 * 8 bytes.
5281 *
5282 * Field Enumeration Values:
5283 *
5284 * Enum | Value | Description
5285 * :------------------------------------------|:------|:------------
5286 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 | 0x0 | Read 1 Byte
5287 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 | 0x1 | Read 2 Byte
5288 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 | 0x2 | Read 3 Byte
5289 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 | 0x3 | Read 4 Byte
5290 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 | 0x4 | Read 5 Byte
5291 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 | 0x5 | Read 6 Byte
5292 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 | 0x6 | Read 7 Byte
5293 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 | 0x7 | Read 8 Byte
5294 *
5295 * Field Access Macros:
5296 *
5297 */
5298/*
5299 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5300 *
5301 * Read 1 Byte
5302 */
5303#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0
5304/*
5305 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5306 *
5307 * Read 2 Byte
5308 */
5309#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1
5310/*
5311 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5312 *
5313 * Read 3 Byte
5314 */
5315#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2
5316/*
5317 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5318 *
5319 * Read 4 Byte
5320 */
5321#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3
5322/*
5323 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5324 *
5325 * Read 5 Byte
5326 */
5327#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4
5328/*
5329 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5330 *
5331 * Read 6 Byte
5332 */
5333#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5
5334/*
5335 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5336 *
5337 * Read 7 Byte
5338 */
5339#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6
5340/*
5341 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5342 *
5343 * Read 8 Byte
5344 */
5345#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7
5346
5347/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
5348#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20
5349/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
5350#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22
5351/* The width in bits of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
5352#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3
5353/* The mask used to set the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */
5354#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000
5355/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */
5356#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff
5357/* The reset value of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
5358#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0
5359/* Extracts the ALT_QSPI_FLSHCMD_NUMRDDATABYTES field value from a register. */
5360#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20)
5361/* Produces a ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value suitable for setting the register. */
5362#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000)
5363
5364/*
5365 * Field : Read Data Enable - enrddata
5366 *
5367 * If enabled, the command specified in the command opcode field (bits 31:24)
5368 * requires read data bytes to be received from the device.
5369 *
5370 * Field Enumeration Values:
5371 *
5372 * Enum | Value | Description
5373 * :-------------------------------------|:------|:---------------------------
5374 * ALT_QSPI_FLSHCMD_ENRDDATA_E_EN | 0x1 | Command Requires read data
5375 * ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION | 0x0 | No Action
5376 *
5377 * Field Access Macros:
5378 *
5379 */
5380/*
5381 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA
5382 *
5383 * Command Requires read data
5384 */
5385#define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1
5386/*
5387 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA
5388 *
5389 * No Action
5390 */
5391#define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0
5392
5393/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
5394#define ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23
5395/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
5396#define ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23
5397/* The width in bits of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
5398#define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1
5399/* The mask used to set the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */
5400#define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000
5401/* The mask used to clear the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */
5402#define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff
5403/* The reset value of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
5404#define ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0
5405/* Extracts the ALT_QSPI_FLSHCMD_ENRDDATA field value from a register. */
5406#define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23)
5407/* Produces a ALT_QSPI_FLSHCMD_ENRDDATA register field value suitable for setting the register. */
5408#define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000)
5409
5410/*
5411 * Field : Command Opcode - cmdopcode
5412 *
5413 * The command opcode field should be setup before triggering the command. For
5414 * example, 0x20 maps to SubSector Erase. Writeing to the execute field (bit 0) of
5415 * this register launches the command. NOTE : Using this approach to issue commands
5416 * to the device will make use of the instruction type of the device instruction
5417 * configuration register. If this field is set to 2'b00, then the command opcode,
5418 * command address, command dummy bytes and command data will all be transferred in
5419 * a serial fashion. If this field is set to 2'b01, then the command opcode,
5420 * command address, command dummy bytes and command data will all be transferred in
5421 * parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command
5422 * opcode, command address, command dummy bytes and command data will all be
5423 * transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins.
5424 *
5425 * Field Access Macros:
5426 *
5427 */
5428/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
5429#define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24
5430/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
5431#define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31
5432/* The width in bits of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
5433#define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8
5434/* The mask used to set the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */
5435#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000
5436/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */
5437#define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff
5438/* The reset value of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
5439#define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0
5440/* Extracts the ALT_QSPI_FLSHCMD_CMDOPCODE field value from a register. */
5441#define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24)
5442/* Produces a ALT_QSPI_FLSHCMD_CMDOPCODE register field value suitable for setting the register. */
5443#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000)
5444
5445#ifndef __ASSEMBLY__
5446/*
5447 * WARNING: The C register and register group struct declarations are provided for
5448 * convenience and illustrative purposes. They should, however, be used with
5449 * caution as the C language standard provides no guarantees about the alignment or
5450 * atomicity of device memory accesses. The recommended practice for writing
5451 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5452 * alt_write_word() functions.
5453 *
5454 * The struct declaration for register ALT_QSPI_FLSHCMD.
5455 */
5456 struct ALT_QSPI_FLSHCMD_s
5457{
5458 uint32_t execcmd : 1; /* Execute Command */
5459 const uint32_t cmdexecstat : 1; /* Command Execution Status */
5460 uint32_t : 5; /* *UNDEFINED* */
5461 uint32_t numdummybytes : 5; /* Number of Dummy Bytes */
5462 uint32_t numwrdatabytes : 3; /* Number of Write Data Bytes */
5463 uint32_t enwrdata : 1; /* Write Data Enable */
5464 uint32_t numaddrbytes : 2; /* Number of Address Bytes */
5465 uint32_t enmodebit : 1; /* Mode Bit Enable */
5466 uint32_t encmdaddr : 1; /* Command Address Enable */
5467 uint32_t numrddatabytes : 3; /* Number of Read Data Bytes */
5468 uint32_t enrddata : 1; /* Read Data Enable */
5469 uint32_t cmdopcode : 8; /* Command Opcode */
5470};
5471
5472/* The typedef declaration for register ALT_QSPI_FLSHCMD. */
5473typedef volatile struct ALT_QSPI_FLSHCMD_s ALT_QSPI_FLSHCMD_t;
5474#endif /* __ASSEMBLY__ */
5475
5476/* The byte offset of the ALT_QSPI_FLSHCMD register from the beginning of the component. */
5477#define ALT_QSPI_FLSHCMD_OFST 0x90
5478
5479/*
5480 * Register : Flash Command Address Registers - flashcmdaddr
5481 *
5482 * Register Layout
5483 *
5484 * Bits | Access | Reset | Description
5485 * :-------|:-------|:------|:----------------
5486 * [31:0] | RW | 0x0 | Command Address
5487 *
5488 */
5489/*
5490 * Field : Command Address - addr
5491 *
5492 * This should be setup before triggering the command with execute field (bit 0) of
5493 * the Flash Command Control register. It is the address used by the command
5494 * specified in the opcode field (bits 31:24) of the Flash Command Control
5495 * register.
5496 *
5497 * Field Access Macros:
5498 *
5499 */
5500/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
5501#define ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0
5502/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
5503#define ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31
5504/* The width in bits of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
5505#define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32
5506/* The mask used to set the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */
5507#define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff
5508/* The mask used to clear the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */
5509#define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000
5510/* The reset value of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
5511#define ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0
5512/* Extracts the ALT_QSPI_FLSHCMDADDR_ADDR field value from a register. */
5513#define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
5514/* Produces a ALT_QSPI_FLSHCMDADDR_ADDR register field value suitable for setting the register. */
5515#define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
5516
5517#ifndef __ASSEMBLY__
5518/*
5519 * WARNING: The C register and register group struct declarations are provided for
5520 * convenience and illustrative purposes. They should, however, be used with
5521 * caution as the C language standard provides no guarantees about the alignment or
5522 * atomicity of device memory accesses. The recommended practice for writing
5523 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5524 * alt_write_word() functions.
5525 *
5526 * The struct declaration for register ALT_QSPI_FLSHCMDADDR.
5527 */
5528 struct ALT_QSPI_FLSHCMDADDR_s
5529{
5530 uint32_t addr : 32; /* Command Address */
5531};
5532
5533/* The typedef declaration for register ALT_QSPI_FLSHCMDADDR. */
5534typedef volatile struct ALT_QSPI_FLSHCMDADDR_s ALT_QSPI_FLSHCMDADDR_t;
5535#endif /* __ASSEMBLY__ */
5536
5537/* The byte offset of the ALT_QSPI_FLSHCMDADDR register from the beginning of the component. */
5538#define ALT_QSPI_FLSHCMDADDR_OFST 0x94
5539
5540/*
5541 * Register : Flash Command Read Data Register (Lower) - flashcmdrddatalo
5542 *
5543 * Register Layout
5544 *
5545 * Bits | Access | Reset | Description
5546 * :-------|:-------|:------|:-------------------------------
5547 * [31:0] | RW | 0x0 | Command Read Data (Lower byte)
5548 *
5549 */
5550/*
5551 * Field : Command Read Data (Lower byte) - data
5552 *
5553 * This is the data that is returned by the flash device for any status or
5554 * configuration read operation carried out by triggering the event in the control
5555 * register. The register will be valid when the polling bit in the control
5556 * register is low.
5557 *
5558 * Field Access Macros:
5559 *
5560 */
5561/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
5562#define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0
5563/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
5564#define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31
5565/* The width in bits of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
5566#define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32
5567/* The mask used to set the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */
5568#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff
5569/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */
5570#define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000
5571/* The reset value of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
5572#define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0
5573/* Extracts the ALT_QSPI_FLSHCMDRDDATALO_DATA field value from a register. */
5574#define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5575/* Produces a ALT_QSPI_FLSHCMDRDDATALO_DATA register field value suitable for setting the register. */
5576#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
5577
5578#ifndef __ASSEMBLY__
5579/*
5580 * WARNING: The C register and register group struct declarations are provided for
5581 * convenience and illustrative purposes. They should, however, be used with
5582 * caution as the C language standard provides no guarantees about the alignment or
5583 * atomicity of device memory accesses. The recommended practice for writing
5584 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5585 * alt_write_word() functions.
5586 *
5587 * The struct declaration for register ALT_QSPI_FLSHCMDRDDATALO.
5588 */
5589 struct ALT_QSPI_FLSHCMDRDDATALO_s
5590{
5591 uint32_t data : 32; /* Command Read Data (Lower byte) */
5592};
5593
5594/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATALO. */
5595typedef volatile struct ALT_QSPI_FLSHCMDRDDATALO_s ALT_QSPI_FLSHCMDRDDATALO_t;
5596#endif /* __ASSEMBLY__ */
5597
5598/* The byte offset of the ALT_QSPI_FLSHCMDRDDATALO register from the beginning of the component. */
5599#define ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0
5600
5601/*
5602 * Register : Flash Command Read Data Register (Upper) - flashcmdrddataup
5603 *
5604 * Device Instruction Register
5605 *
5606 * Register Layout
5607 *
5608 * Bits | Access | Reset | Description
5609 * :-------|:-------|:------|:-------------------------------
5610 * [31:0] | RW | 0x0 | Command Read Data (Upper byte)
5611 *
5612 */
5613/*
5614 * Field : Command Read Data (Upper byte) - data
5615 *
5616 * This is the data that is returned by the FLASH device for any status or
5617 * configuration read operation carried out by triggering the event in the control
5618 * register. The register will be valid when the polling bit in the control
5619 * register is low.
5620 *
5621 * Field Access Macros:
5622 *
5623 */
5624/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
5625#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0
5626/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
5627#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31
5628/* The width in bits of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
5629#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32
5630/* The mask used to set the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */
5631#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff
5632/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */
5633#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000
5634/* The reset value of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
5635#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0
5636/* Extracts the ALT_QSPI_FLSHCMDRDDATAUP_DATA field value from a register. */
5637#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5638/* Produces a ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value suitable for setting the register. */
5639#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
5640
5641#ifndef __ASSEMBLY__
5642/*
5643 * WARNING: The C register and register group struct declarations are provided for
5644 * convenience and illustrative purposes. They should, however, be used with
5645 * caution as the C language standard provides no guarantees about the alignment or
5646 * atomicity of device memory accesses. The recommended practice for writing
5647 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5648 * alt_write_word() functions.
5649 *
5650 * The struct declaration for register ALT_QSPI_FLSHCMDRDDATAUP.
5651 */
5652 struct ALT_QSPI_FLSHCMDRDDATAUP_s
5653{
5654 uint32_t data : 32; /* Command Read Data (Upper byte) */
5655};
5656
5657/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATAUP. */
5658typedef volatile struct ALT_QSPI_FLSHCMDRDDATAUP_s ALT_QSPI_FLSHCMDRDDATAUP_t;
5659#endif /* __ASSEMBLY__ */
5660
5661/* The byte offset of the ALT_QSPI_FLSHCMDRDDATAUP register from the beginning of the component. */
5662#define ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4
5663
5664/*
5665 * Register : Flash Command Write Data Register (Lower) - flashcmdwrdatalo
5666 *
5667 * Register Layout
5668 *
5669 * Bits | Access | Reset | Description
5670 * :-------|:-------|:------|:------------------------------
5671 * [31:0] | RW | 0x0 | Command Write Data Lower Byte
5672 *
5673 */
5674/*
5675 * Field : Command Write Data Lower Byte - data
5676 *
5677 * This is the command write data lower byte. This should be setup before
5678 * triggering the command with execute field (bit 0) of the Flash Command Control
5679 * register. It is the data that is to be written to the flash for any status or
5680 * configuration write operation carried out by triggering the event in the Flash
5681 * Command Control register.
5682 *
5683 * Field Access Macros:
5684 *
5685 */
5686/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
5687#define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0
5688/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
5689#define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31
5690/* The width in bits of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
5691#define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32
5692/* The mask used to set the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */
5693#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff
5694/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */
5695#define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000
5696/* The reset value of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
5697#define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0
5698/* Extracts the ALT_QSPI_FLSHCMDWRDATALO_DATA field value from a register. */
5699#define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5700/* Produces a ALT_QSPI_FLSHCMDWRDATALO_DATA register field value suitable for setting the register. */
5701#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
5702
5703#ifndef __ASSEMBLY__
5704/*
5705 * WARNING: The C register and register group struct declarations are provided for
5706 * convenience and illustrative purposes. They should, however, be used with
5707 * caution as the C language standard provides no guarantees about the alignment or
5708 * atomicity of device memory accesses. The recommended practice for writing
5709 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5710 * alt_write_word() functions.
5711 *
5712 * The struct declaration for register ALT_QSPI_FLSHCMDWRDATALO.
5713 */
5714 struct ALT_QSPI_FLSHCMDWRDATALO_s
5715{
5716 uint32_t data : 32; /* Command Write Data Lower Byte */
5717};
5718
5719/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATALO. */
5720typedef volatile struct ALT_QSPI_FLSHCMDWRDATALO_s ALT_QSPI_FLSHCMDWRDATALO_t;
5721#endif /* __ASSEMBLY__ */
5722
5723/* The byte offset of the ALT_QSPI_FLSHCMDWRDATALO register from the beginning of the component. */
5724#define ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8
5725
5726/*
5727 * Register : Flash Command Write Data Register (Upper) - flashcmdwrdataup
5728 *
5729 * Register Layout
5730 *
5731 * Bits | Access | Reset | Description
5732 * :-------|:-------|:------|:------------------------------
5733 * [31:0] | RW | 0x0 | ALT_QSPI_FLSHCMDWRDATAUP_DATA
5734 *
5735 */
5736/*
5737 * Field : data
5738 *
5739 * This is the command write data upper byte. This should be setup before
5740 * triggering the command with execute field (bit 0) of the Flash Command Control
5741 * register. It is the data that is to be written to the flash for any status or
5742 * configuration write operation carried out by triggering the event in the Flash
5743 * Command Control register.
5744 *
5745 * Field Access Macros:
5746 *
5747 */
5748/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
5749#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0
5750/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
5751#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31
5752/* The width in bits of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
5753#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32
5754/* The mask used to set the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */
5755#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff
5756/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */
5757#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000
5758/* The reset value of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
5759#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0
5760/* Extracts the ALT_QSPI_FLSHCMDWRDATAUP_DATA field value from a register. */
5761#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5762/* Produces a ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value suitable for setting the register. */
5763#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
5764
5765#ifndef __ASSEMBLY__
5766/*
5767 * WARNING: The C register and register group struct declarations are provided for
5768 * convenience and illustrative purposes. They should, however, be used with
5769 * caution as the C language standard provides no guarantees about the alignment or
5770 * atomicity of device memory accesses. The recommended practice for writing
5771 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5772 * alt_write_word() functions.
5773 *
5774 * The struct declaration for register ALT_QSPI_FLSHCMDWRDATAUP.
5775 */
5776 struct ALT_QSPI_FLSHCMDWRDATAUP_s
5777{
5778 uint32_t data : 32; /* ALT_QSPI_FLSHCMDWRDATAUP_DATA */
5779};
5780
5781/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATAUP. */
5782typedef volatile struct ALT_QSPI_FLSHCMDWRDATAUP_s ALT_QSPI_FLSHCMDWRDATAUP_t;
5783#endif /* __ASSEMBLY__ */
5784
5785/* The byte offset of the ALT_QSPI_FLSHCMDWRDATAUP register from the beginning of the component. */
5786#define ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac
5787
5788/*
5789 * Register : Module ID Register - moduleid
5790 *
5791 * Register Layout
5792 *
5793 * Bits | Access | Reset | Description
5794 * :--------|:-------|:-------|:-----------------
5795 * [24:0] | R | 0x1001 | Module ID number
5796 * [31:25] | ??? | 0x0 | *UNDEFINED*
5797 *
5798 */
5799/*
5800 * Field : Module ID number - value
5801 *
5802 * Field Access Macros:
5803 *
5804 */
5805/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODULEID_VALUE register field. */
5806#define ALT_QSPI_MODULEID_VALUE_LSB 0
5807/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODULEID_VALUE register field. */
5808#define ALT_QSPI_MODULEID_VALUE_MSB 24
5809/* The width in bits of the ALT_QSPI_MODULEID_VALUE register field. */
5810#define ALT_QSPI_MODULEID_VALUE_WIDTH 25
5811/* The mask used to set the ALT_QSPI_MODULEID_VALUE register field value. */
5812#define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff
5813/* The mask used to clear the ALT_QSPI_MODULEID_VALUE register field value. */
5814#define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000
5815/* The reset value of the ALT_QSPI_MODULEID_VALUE register field. */
5816#define ALT_QSPI_MODULEID_VALUE_RESET 0x1001
5817/* Extracts the ALT_QSPI_MODULEID_VALUE field value from a register. */
5818#define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0)
5819/* Produces a ALT_QSPI_MODULEID_VALUE register field value suitable for setting the register. */
5820#define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff)
5821
5822#ifndef __ASSEMBLY__
5823/*
5824 * WARNING: The C register and register group struct declarations are provided for
5825 * convenience and illustrative purposes. They should, however, be used with
5826 * caution as the C language standard provides no guarantees about the alignment or
5827 * atomicity of device memory accesses. The recommended practice for writing
5828 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5829 * alt_write_word() functions.
5830 *
5831 * The struct declaration for register ALT_QSPI_MODULEID.
5832 */
5833 struct ALT_QSPI_MODULEID_s
5834{
5835 const uint32_t value : 25; /* Module ID number */
5836 uint32_t : 7; /* *UNDEFINED* */
5837};
5838
5839/* The typedef declaration for register ALT_QSPI_MODULEID. */
5840typedef volatile struct ALT_QSPI_MODULEID_s ALT_QSPI_MODULEID_t;
5841#endif /* __ASSEMBLY__ */
5842
5843/* The byte offset of the ALT_QSPI_MODULEID register from the beginning of the component. */
5844#define ALT_QSPI_MODULEID_OFST 0xfc
5845
5846#ifndef __ASSEMBLY__
5847/*
5848 * WARNING: The C register and register group struct declarations are provided for
5849 * convenience and illustrative purposes. They should, however, be used with
5850 * caution as the C language standard provides no guarantees about the alignment or
5851 * atomicity of device memory accesses. The recommended practice for writing
5852 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5853 * alt_write_word() functions.
5854 *
5855 * The struct declaration for register group ALT_QSPI.
5856 */
5857 struct ALT_QSPI_s
5858{
5859 volatile ALT_QSPI_CFG_t cfg; /* ALT_QSPI_CFG */
5860 volatile ALT_QSPI_DEVRD_t devrd; /* ALT_QSPI_DEVRD */
5861 volatile ALT_QSPI_DEVWR_t devwr; /* ALT_QSPI_DEVWR */
5862 volatile ALT_QSPI_DELAY_t delay; /* ALT_QSPI_DELAY */
5863 volatile ALT_QSPI_RDDATACAP_t rddatacap; /* ALT_QSPI_RDDATACAP */
5864 volatile ALT_QSPI_DEVSZ_t devsz; /* ALT_QSPI_DEVSZ */
5865 volatile ALT_QSPI_SRAMPART_t srampart; /* ALT_QSPI_SRAMPART */
5866 volatile ALT_QSPI_INDADDRTRIG_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */
5867 volatile ALT_QSPI_DMAPER_t dmaper; /* ALT_QSPI_DMAPER */
5868 volatile ALT_QSPI_REMAPADDR_t remapaddr; /* ALT_QSPI_REMAPADDR */
5869 volatile ALT_QSPI_MODBIT_t modebit; /* ALT_QSPI_MODBIT */
5870 volatile ALT_QSPI_SRAMFILL_t sramfill; /* ALT_QSPI_SRAMFILL */
5871 volatile ALT_QSPI_TXTHRESH_t txthresh; /* ALT_QSPI_TXTHRESH */
5872 volatile ALT_QSPI_RXTHRESH_t rxthresh; /* ALT_QSPI_RXTHRESH */
5873 volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */
5874 volatile ALT_QSPI_IRQSTAT_t irqstat; /* ALT_QSPI_IRQSTAT */
5875 volatile ALT_QSPI_IRQMSK_t irqmask; /* ALT_QSPI_IRQMSK */
5876 volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */
5877 volatile ALT_QSPI_LOWWRPROT_t lowwrprot; /* ALT_QSPI_LOWWRPROT */
5878 volatile ALT_QSPI_UPPWRPROT_t uppwrprot; /* ALT_QSPI_UPPWRPROT */
5879 volatile ALT_QSPI_WRPROT_t wrprot; /* ALT_QSPI_WRPROT */
5880 volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */
5881 volatile ALT_QSPI_INDRD_t indrd; /* ALT_QSPI_INDRD */
5882 volatile ALT_QSPI_INDRDWATER_t indrdwater; /* ALT_QSPI_INDRDWATER */
5883 volatile ALT_QSPI_INDRDSTADDR_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */
5884 volatile ALT_QSPI_INDRDCNT_t indrdcnt; /* ALT_QSPI_INDRDCNT */
5885 volatile ALT_QSPI_INDWR_t indwr; /* ALT_QSPI_INDWR */
5886 volatile ALT_QSPI_INDWRWATER_t indwrwater; /* ALT_QSPI_INDWRWATER */
5887 volatile ALT_QSPI_INDWRSTADDR_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */
5888 volatile ALT_QSPI_INDWRCNT_t indwrcnt; /* ALT_QSPI_INDWRCNT */
5889 volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */
5890 volatile ALT_QSPI_FLSHCMD_t flashcmd; /* ALT_QSPI_FLSHCMD */
5891 volatile ALT_QSPI_FLSHCMDADDR_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */
5892 volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */
5893 volatile ALT_QSPI_FLSHCMDRDDATALO_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */
5894 volatile ALT_QSPI_FLSHCMDRDDATAUP_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */
5895 volatile ALT_QSPI_FLSHCMDWRDATALO_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */
5896 volatile ALT_QSPI_FLSHCMDWRDATAUP_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */
5897 volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */
5898 volatile ALT_QSPI_MODULEID_t moduleid; /* ALT_QSPI_MODULEID */
5899};
5900
5901/* The typedef declaration for register group ALT_QSPI. */
5902typedef volatile struct ALT_QSPI_s ALT_QSPI_t;
5903/* The struct declaration for the raw register contents of register group ALT_QSPI. */
5904 struct ALT_QSPI_raw_s
5905{
5906 volatile uint32_t cfg; /* ALT_QSPI_CFG */
5907 volatile uint32_t devrd; /* ALT_QSPI_DEVRD */
5908 volatile uint32_t devwr; /* ALT_QSPI_DEVWR */
5909 volatile uint32_t delay; /* ALT_QSPI_DELAY */
5910 volatile uint32_t rddatacap; /* ALT_QSPI_RDDATACAP */
5911 volatile uint32_t devsz; /* ALT_QSPI_DEVSZ */
5912 volatile uint32_t srampart; /* ALT_QSPI_SRAMPART */
5913 volatile uint32_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */
5914 volatile uint32_t dmaper; /* ALT_QSPI_DMAPER */
5915 volatile uint32_t remapaddr; /* ALT_QSPI_REMAPADDR */
5916 volatile uint32_t modebit; /* ALT_QSPI_MODBIT */
5917 volatile uint32_t sramfill; /* ALT_QSPI_SRAMFILL */
5918 volatile uint32_t txthresh; /* ALT_QSPI_TXTHRESH */
5919 volatile uint32_t rxthresh; /* ALT_QSPI_RXTHRESH */
5920 volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */
5921 volatile uint32_t irqstat; /* ALT_QSPI_IRQSTAT */
5922 volatile uint32_t irqmask; /* ALT_QSPI_IRQMSK */
5923 volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */
5924 volatile uint32_t lowwrprot; /* ALT_QSPI_LOWWRPROT */
5925 volatile uint32_t uppwrprot; /* ALT_QSPI_UPPWRPROT */
5926 volatile uint32_t wrprot; /* ALT_QSPI_WRPROT */
5927 volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */
5928 volatile uint32_t indrd; /* ALT_QSPI_INDRD */
5929 volatile uint32_t indrdwater; /* ALT_QSPI_INDRDWATER */
5930 volatile uint32_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */
5931 volatile uint32_t indrdcnt; /* ALT_QSPI_INDRDCNT */
5932 volatile uint32_t indwr; /* ALT_QSPI_INDWR */
5933 volatile uint32_t indwrwater; /* ALT_QSPI_INDWRWATER */
5934 volatile uint32_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */
5935 volatile uint32_t indwrcnt; /* ALT_QSPI_INDWRCNT */
5936 volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */
5937 volatile uint32_t flashcmd; /* ALT_QSPI_FLSHCMD */
5938 volatile uint32_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */
5939 volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */
5940 volatile uint32_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */
5941 volatile uint32_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */
5942 volatile uint32_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */
5943 volatile uint32_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */
5944 volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */
5945 volatile uint32_t moduleid; /* ALT_QSPI_MODULEID */
5946};
5947
5948/* The typedef declaration for the raw register contents of register group ALT_QSPI. */
5949typedef volatile struct ALT_QSPI_raw_s ALT_QSPI_raw_t;
5950#endif /* __ASSEMBLY__ */
5951
5952
5953#ifdef __cplusplus
5954}
5955#endif /* __cplusplus */
5956#endif /* __ALTERA_ALT_QSPI_H__ */
5957
ALT_QSPI_CFG_s
Definition: alt_qspi.h:840
ALT_QSPI_DELAY_s
Definition: alt_qspi.h:1589
ALT_QSPI_DEVRD_s
Definition: alt_qspi.h:1204
ALT_QSPI_DEVSZ_s
Definition: alt_qspi.h:1813
ALT_QSPI_DEVWR_s
Definition: alt_qspi.h:1434
ALT_QSPI_DMAPER_s
Definition: alt_qspi.h:2031
ALT_QSPI_FLSHCMDADDR_s
Definition: alt_qspi.h:5529
ALT_QSPI_FLSHCMDRDDATALO_s
Definition: alt_qspi.h:5590
ALT_QSPI_FLSHCMDRDDATAUP_s
Definition: alt_qspi.h:5653
ALT_QSPI_FLSHCMDWRDATALO_s
Definition: alt_qspi.h:5715
ALT_QSPI_FLSHCMDWRDATAUP_s
Definition: alt_qspi.h:5777
ALT_QSPI_FLSHCMD_s
Definition: alt_qspi.h:5457
ALT_QSPI_INDADDRTRIG_s
Definition: alt_qspi.h:1939
ALT_QSPI_INDRDCNT_s
Definition: alt_qspi.h:4338
ALT_QSPI_INDRDSTADDR_s
Definition: alt_qspi.h:4279
ALT_QSPI_INDRDWATER_s
Definition: alt_qspi.h:4220
ALT_QSPI_INDRD_s
Definition: alt_qspi.h:4152
ALT_QSPI_INDWRCNT_s
Definition: alt_qspi.h:4841
ALT_QSPI_INDWRSTADDR_s
Definition: alt_qspi.h:4782
ALT_QSPI_INDWRWATER_s
Definition: alt_qspi.h:4723
ALT_QSPI_INDWR_s
Definition: alt_qspi.h:4655
ALT_QSPI_IRQMSK_s
Definition: alt_qspi.h:3545
ALT_QSPI_IRQSTAT_s
Definition: alt_qspi.h:2966
ALT_QSPI_LOWWRPROT_s
Definition: alt_qspi.h:3618
ALT_QSPI_MODBIT_s
Definition: alt_qspi.h:2156
ALT_QSPI_MODULEID_s
Definition: alt_qspi.h:5834
ALT_QSPI_RDDATACAP_s
Definition: alt_qspi.h:1697
ALT_QSPI_REMAPADDR_s
Definition: alt_qspi.h:2096
ALT_QSPI_RXTHRESH_s
Definition: alt_qspi.h:2359
ALT_QSPI_SRAMFILL_s
Definition: alt_qspi.h:2237
ALT_QSPI_SRAMPART_s
Definition: alt_qspi.h:1877
ALT_QSPI_TXTHRESH_s
Definition: alt_qspi.h:2297
ALT_QSPI_UPPWRPROT_s
Definition: alt_qspi.h:3678
ALT_QSPI_WRPROT_s
Definition: alt_qspi.h:3810
ALT_QSPI_raw_s
Definition: alt_qspi.h:5905
ALT_QSPI_s
Definition: alt_qspi.h:5858