RTEMS: bsps/arm/include/bsp/arm-a9mpcore-start.h Source File

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arm-a9mpcore-start.h
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1
9/*
10 * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
11 *
12 * embedded brains GmbH
13 * Dornierstr. 4
14 * 82178 Puchheim
15 * Germany
16 * <info@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H
24#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H
25
26#include <rtems/score/smpimpl.h>
27
28#include <libcpu/arm-cp15.h>
29
30#include <bsp.h>
31#include <bsp/start.h>
32#include <bsp/arm-a9mpcore-regs.h>
33#include <bsp/arm-errata.h>
34#include <bsp/arm-gic-irq.h>
35
36#ifdef __cplusplus
37extern "C" {
38#endif /* __cplusplus */
39
40BSP_START_TEXT_SECTION static inline void
41arm_a9mpcore_start_set_vector_base(void)
42{
43 /*
44 * Do not use bsp_vector_table_begin == 0, since this will get optimized away.
45 */
46 if (bsp_vector_table_end != bsp_vector_table_size) {
47 uint32_t ctrl;
48
49 /*
50 * For now we assume that every Cortex-A9 MPCore has the Security Extensions.
51 * Later it might be necessary to evaluate the ID_PFR1 register.
52 */
53 arm_cp15_set_vector_base_address(bsp_vector_table_begin);
54
55 ctrl = arm_cp15_get_control();
56 ctrl &= ~ARM_CP15_CTRL_V;
57 arm_cp15_set_control(ctrl);
58 }
59}
60
61BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_scu_invalidate(
62 volatile a9mpcore_scu *scu,
63 uint32_t cpu_id,
64 uint32_t ways
65)
66{
67 scu->invss = (ways & 0xf) << ((cpu_id & 0x3) * 4);
68}
69
70BSP_START_TEXT_SECTION static inline void
71arm_a9mpcore_start_errata_764369_handler(volatile a9mpcore_scu *scu)
72{
73 if (arm_errata_is_applicable_processor_errata_764369()) {
74 scu->diagn_ctrl |= A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE;
75 }
76}
77
78BSP_START_TEXT_SECTION static inline void
79arm_a9mpcore_start_scu_enable(volatile a9mpcore_scu *scu)
80{
81 scu->ctrl |= A9MPCORE_SCU_CTRL_SCU_EN;
82 arm_a9mpcore_start_errata_764369_handler(scu);
83}
84
85#ifdef RTEMS_SMP
86BSP_START_TEXT_SECTION static inline void
87arm_a9mpcore_start_on_secondary_processor(void)
88{
89 uint32_t ctrl;
90
91 arm_a9mpcore_start_set_vector_base();
92
93 arm_gic_irq_initialize_secondary_cpu();
94
95 ctrl = arm_cp15_start_setup_mmu_and_cache(
96 0,
97 ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
98 );
99
100 arm_cp15_set_domain_access_control(
101 ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT)
102 );
103
104 /* FIXME: Sharing the translation table between processors is brittle */
105 arm_cp15_set_translation_table_base(
106 (uint32_t *) bsp_translation_table_base
107 );
108
109 ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
110 arm_cp15_set_control(ctrl);
111
112 _SMP_Start_multitasking_on_secondary_processor(_Per_CPU_Get());
113}
114
115BSP_START_TEXT_SECTION static inline void
116arm_a9mpcore_start_enable_smp_in_auxiliary_control(void)
117{
118 /*
119 * Enable cache coherency support and cache/MMU maintenance broadcasts for
120 * this processor.
121 */
122 uint32_t actlr = arm_cp15_get_auxiliary_control();
123 actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW;
124 arm_cp15_set_auxiliary_control(actlr);
125}
126
127BSP_START_TEXT_SECTION static inline void
128arm_a9mpcore_start_errata_794072_handler(void)
129{
130 uint32_t diag;
131
132 /*
133 * Workaround for Errata 794072: A short loop including a DMB instruction
134 * might cause a denial of service on another which executes a CP15 broadcast
135 * operation.
136 */
137 diag = arm_cp15_get_diagnostic_control();
138 diag |= 1U << 4;
139 arm_cp15_set_diagnostic_control(diag);
140}
141
142BSP_START_TEXT_SECTION static inline void
143arm_a9mpcore_start_errata_845369_handler(void)
144{
145 uint32_t diag;
146
147 /*
148 * Workaround for Errata 845369: Under Very Rare Timing Circumstances
149 * Transition into Streaming Mode Might Create Data Corruption.
150 */
151 diag = arm_cp15_get_diagnostic_control();
152 diag |= 1U << 22;
153 arm_cp15_set_diagnostic_control(diag);
154}
155#endif
156
157BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_0(void)
158{
159 volatile a9mpcore_scu *scu =
160 (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
161 uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
162
163 arm_cp15_branch_predictor_invalidate_all();
164
165 if (cpu_id == 0) {
166 arm_a9mpcore_start_scu_enable(scu);
167 }
168
169#ifdef RTEMS_SMP
170 arm_a9mpcore_start_errata_794072_handler();
171 arm_a9mpcore_start_errata_845369_handler();
172 arm_a9mpcore_start_enable_smp_in_auxiliary_control();
173#endif
174
175 arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xf);
176
177#ifdef RTEMS_SMP
178 if (cpu_id != 0) {
179 arm_a9mpcore_start_on_secondary_processor();
180 }
181#endif
182}
183
184BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_global_timer(void)
185{
186 volatile a9mpcore_gt *gt = (volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE;
187
188 gt->ctrl = 0;
189 gt->cntrlower = 0;
190 gt->cntrupper = 0;
191 gt->ctrl = A9MPCORE_GT_CTRL_TMR_EN;
192}
193
194BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_1(void)
195{
196 arm_a9mpcore_start_global_timer();
197 arm_a9mpcore_start_set_vector_base();
198}
199
200#ifdef __cplusplus
201}
202#endif /* __cplusplus */
203
204#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H */
arm-a9mpcore-regs.h
ARM_A9MPCORE_REGS Support.
arm-cp15.h
ARM co-processor 15 (CP15) API.
arm-errata.h
Create #defines which state which erratas shall get applied.
arm-gic-irq.h
ARM GIC IRQ.
smpimpl.h
SuperCore SMP Implementation.
a9mpcore_gt
Definition: arm-a9mpcore-regs.h:75
a9mpcore_scu
Definition: arm-a9mpcore-regs.h:28