RTEMS: bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h Source File

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alt_uart.h
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1
7/*******************************************************************************
8* *
9* Copyright 2013 Altera Corporation. All Rights Reserved. *
10* *
11* Redistribution and use in source and binary forms, with or without *
12* modification, are permitted provided that the following conditions are met: *
13* *
14* 1. Redistributions of source code must retain the above copyright notice, *
15* this list of conditions and the following disclaimer. *
16* *
17* 2. Redistributions in binary form must reproduce the above copyright notice, *
18* this list of conditions and the following disclaimer in the documentation *
19* and/or other materials provided with the distribution. *
20* *
21* 3. The name of the author may not be used to endorse or promote products *
22* derived from this software without specific prior written permission. *
23* *
24* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
25* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
26* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
27* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
28* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
29* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
30* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
31* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
32* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
33* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
34* *
35*******************************************************************************/
36
37/* Altera - ALT_UART */
38
39#ifndef __ALTERA_ALT_UART_H__
40#define __ALTERA_ALT_UART_H__
41
42#ifdef __cplusplus
43extern "C"
44{
45#endif /* __cplusplus */
46
47/*
48 * Component : UART Module - ALT_UART
49 * UART Module
50 *
51 * Registers in the UART module
52 *
53 */
54/*
55 * Register : Rx Buffer, Tx Holding, and Divisor Latch Low - rbr_thr_dll
56 *
57 * This is a multi-function register. This register holds receives and transmit
58 * data and controls the least-signficant 8 bits of the baud rate divisor.
59 *
60 * Register Layout
61 *
62 * Bits | Access | Reset | Description
63 * :-------|:-------|:------|:------------
64 * [7:0] | RW | 0x0 | Value
65 * [31:8] | ??? | 0x0 | *UNDEFINED*
66 *
67 */
68/*
69 * Field : Value - value
70 *
71 * Receive Buffer Register:
72 *
73 * This register contains the data byte received on the serial input port
74 * (uart_rxd). The data in this register is valid only if the Data Ready ( bit [0]
75 * in the Line Status Register(LSR)) is set to 1. If FIFOs are disabled(bit[0] of
76 * Register FCR is set to 0) the data in the RBR must be read before the next data
77 * arrives, otherwise it will be overwritten, resulting in an overrun error. If
78 * FIFOs are enabled(bit [0] of Register FCR is set to 1) this register accesses
79 * the head of the receive FIFO. If the receive FIFO is full, and this register is
80 * not read before the next data character arrives, then the data already in the
81 * FIFO will be preserved but any incoming data will be lost. An overrun error will
82 * also occur.
83 *
84 * Transmit Holding Register:
85 *
86 * This register contains data to be transmitted on the serial output port. Data
87 * should only be written to the THR when the THR Empty bit [5] of the LSR Register
88 * is set to 1. If FIFOs are disabled (bit [0] of Register FCR) is set to 0 and
89 * THRE is set to 1, writing a single character to the THR clears the THRE. Any
90 * additional writes to the THR before the THRE is set again causes the THR data to
91 * be overwritten. If FIFO's are enabled bit [0] of Register FCR is set to 1 and
92 * THRE is set up to 128 characters of data may be written to the THR before the
93 * FIFO is full. Any attempt to write data when the FIFO is full results in the
94 * write data being lost.
95 *
96 * Divisor Latch Low:
97 *
98 * This register makes up the lower 8-bits of a 16-bit, Read/write, Divisor Latch
99 * register that contains the baud rate divisor for the UART. This register may
100 * only be accessed when the DLAB bit [7] of the LCR Register is set to 1. The
101 * output baud rate is equal to the serial clock l4_sp_clk frequency divided by
102 * sixteen times the value of the baud rate divisor, as follows:
103 *
104 * baud rate = (serial clock freq) / (16 * divisor)
105 *
106 * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud
107 * clock is disabled and no serial communications will occur. Also, once the DLL is
108 * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before
109 * transmitting or receiving data.
110 *
111 * Field Access Macros:
112 *
113 */
114/* The Least Significant Bit (LSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */
115#define ALT_UART_RBR_THR_DLL_VALUE_LSB 0
116/* The Most Significant Bit (MSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */
117#define ALT_UART_RBR_THR_DLL_VALUE_MSB 7
118/* The width in bits of the ALT_UART_RBR_THR_DLL_VALUE register field. */
119#define ALT_UART_RBR_THR_DLL_VALUE_WIDTH 8
120/* The mask used to set the ALT_UART_RBR_THR_DLL_VALUE register field value. */
121#define ALT_UART_RBR_THR_DLL_VALUE_SET_MSK 0x000000ff
122/* The mask used to clear the ALT_UART_RBR_THR_DLL_VALUE register field value. */
123#define ALT_UART_RBR_THR_DLL_VALUE_CLR_MSK 0xffffff00
124/* The reset value of the ALT_UART_RBR_THR_DLL_VALUE register field. */
125#define ALT_UART_RBR_THR_DLL_VALUE_RESET 0x0
126/* Extracts the ALT_UART_RBR_THR_DLL_VALUE field value from a register. */
127#define ALT_UART_RBR_THR_DLL_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
128/* Produces a ALT_UART_RBR_THR_DLL_VALUE register field value suitable for setting the register. */
129#define ALT_UART_RBR_THR_DLL_VALUE_SET(value) (((value) << 0) & 0x000000ff)
130
131#ifndef __ASSEMBLY__
132/*
133 * WARNING: The C register and register group struct declarations are provided for
134 * convenience and illustrative purposes. They should, however, be used with
135 * caution as the C language standard provides no guarantees about the alignment or
136 * atomicity of device memory accesses. The recommended practice for writing
137 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
138 * alt_write_word() functions.
139 *
140 * The struct declaration for register ALT_UART_RBR_THR_DLL.
141 */
142 struct ALT_UART_RBR_THR_DLL_s
143{
144 uint32_t value : 8; /* Value */
145 uint32_t : 24; /* *UNDEFINED* */
146};
147
148/* The typedef declaration for register ALT_UART_RBR_THR_DLL. */
149typedef volatile struct ALT_UART_RBR_THR_DLL_s ALT_UART_RBR_THR_DLL_t;
150#endif /* __ASSEMBLY__ */
151
152/* The byte offset of the ALT_UART_RBR_THR_DLL register from the beginning of the component. */
153#define ALT_UART_RBR_THR_DLL_OFST 0x0
154/* The address of the ALT_UART_RBR_THR_DLL register. */
155#define ALT_UART_RBR_THR_DLL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RBR_THR_DLL_OFST))
156
157/*
158 * Register : Interrupt Enable and Divisor Latch High - ier_dlh
159 *
160 * This is a multi-function register. This register enables/disables receive and
161 * transmit interrupts and also controls the most-significant 8-bits of the baud
162 * rate divisor.
163 *
164 * Divisor Latch High Register:
165 *
166 * This register is accessed when the DLAB bit [7] of the LCR Register is set to
167 * 1.Bits[7:0] contain the high order 8-bits of the baud rate divisor.The output
168 * baud rate is equal to the serial clock l4_sp_clk frequency divided by sixteen
169 * times the value of the baud rate divisor, as follows:
170 *
171 * baud rate = (serial clock freq) / (16 * divisor):
172 *
173 * Note that with the Divisor Latch Registers (DLLand DLH) set to zero, the baud
174 * clock is disabled and no serial communications will occur. Also, once the DLL is
175 * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before
176 * transmitting or receiving data.
177 *
178 * Interrupt Enable Register:
179 *
180 * This register may only be accessed when the DLAB bit [7] of the LCR Register is
181 * set to 0.Allows control of the Interrupt Enables for transmit and receive
182 * functions.
183 *
184 * Register Layout
185 *
186 * Bits | Access | Reset | Description
187 * :-------|:-------|:------|:--------------------------------------------
188 * [0] | RW | 0x0 | DLH[0] and Receive Data Interrupt Enable
189 * [1] | RW | 0x0 | DLH[1] and Transmit Data Interrupt Control
190 * [2] | RW | 0x0 | DLH[2] and Enable Receiver Line Status
191 * [3] | RW | 0x0 | DLH[3] and Enable Modem Status Interrupt
192 * [4] | RW | 0x0 | DLH[4]
193 * [5] | RW | 0x0 | DLH[5]
194 * [6] | RW | 0x0 | DLH[6]
195 * [7] | RW | 0x0 | DLH[7] and PTIME THRE Interrupt Mode Enable
196 * [31:8] | ??? | 0x0 | *UNDEFINED*
197 *
198 */
199/*
200 * Field : DLH[0] and Receive Data Interrupt Enable - erbfi_dlh0
201 *
202 * Divisor Latch High Register:
203 *
204 * Bit 0 of DLH value.
205 *
206 * Interrupt Enable Register:
207 *
208 * Used to enable/disable the generation of the Receive Data Available Interrupt
209 * and the Character Timeout Interrupt(if FIFO's enabled). These are the second
210 * highest priority interrupts.
211 *
212 * Field Enumeration Values:
213 *
214 * Enum | Value | Description
215 * :-----------------------------------|:------|:------------------
216 * ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD | 0x0 | Interrupt Disable
217 * ALT_UART_IER_DLH_ERBFI_DLH0_E_END | 0x1 | Interrupt Enable
218 *
219 * Field Access Macros:
220 *
221 */
222/*
223 * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0
224 *
225 * Interrupt Disable
226 */
227#define ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD 0x0
228/*
229 * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0
230 *
231 * Interrupt Enable
232 */
233#define ALT_UART_IER_DLH_ERBFI_DLH0_E_END 0x1
234
235/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
236#define ALT_UART_IER_DLH_ERBFI_DLH0_LSB 0
237/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
238#define ALT_UART_IER_DLH_ERBFI_DLH0_MSB 0
239/* The width in bits of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
240#define ALT_UART_IER_DLH_ERBFI_DLH0_WIDTH 1
241/* The mask used to set the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */
242#define ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK 0x00000001
243/* The mask used to clear the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */
244#define ALT_UART_IER_DLH_ERBFI_DLH0_CLR_MSK 0xfffffffe
245/* The reset value of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
246#define ALT_UART_IER_DLH_ERBFI_DLH0_RESET 0x0
247/* Extracts the ALT_UART_IER_DLH_ERBFI_DLH0 field value from a register. */
248#define ALT_UART_IER_DLH_ERBFI_DLH0_GET(value) (((value) & 0x00000001) >> 0)
249/* Produces a ALT_UART_IER_DLH_ERBFI_DLH0 register field value suitable for setting the register. */
250#define ALT_UART_IER_DLH_ERBFI_DLH0_SET(value) (((value) << 0) & 0x00000001)
251
252/*
253 * Field : DLH[1] and Transmit Data Interrupt Control - etbei_dlhl
254 *
255 * Divisor Latch High Register:
256 *
257 * Bit 1 of DLH value.
258 *
259 * Interrupt Enable Register:
260 *
261 * Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable
262 * the generation of Transmitter Holding Register Empty Interrupt. This is the
263 * third highest priority interrupt.
264 *
265 * Field Enumeration Values:
266 *
267 * Enum | Value | Description
268 * :-----------------------------------|:------|:------------
269 * ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD | 0x0 | Tx disable
270 * ALT_UART_IER_DLH_ETBEI_DLHL_E_END | 0x1 | Tx enable
271 *
272 * Field Access Macros:
273 *
274 */
275/*
276 * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL
277 *
278 * Tx disable
279 */
280#define ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD 0x0
281/*
282 * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL
283 *
284 * Tx enable
285 */
286#define ALT_UART_IER_DLH_ETBEI_DLHL_E_END 0x1
287
288/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
289#define ALT_UART_IER_DLH_ETBEI_DLHL_LSB 1
290/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
291#define ALT_UART_IER_DLH_ETBEI_DLHL_MSB 1
292/* The width in bits of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
293#define ALT_UART_IER_DLH_ETBEI_DLHL_WIDTH 1
294/* The mask used to set the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */
295#define ALT_UART_IER_DLH_ETBEI_DLHL_SET_MSK 0x00000002
296/* The mask used to clear the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */
297#define ALT_UART_IER_DLH_ETBEI_DLHL_CLR_MSK 0xfffffffd
298/* The reset value of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
299#define ALT_UART_IER_DLH_ETBEI_DLHL_RESET 0x0
300/* Extracts the ALT_UART_IER_DLH_ETBEI_DLHL field value from a register. */
301#define ALT_UART_IER_DLH_ETBEI_DLHL_GET(value) (((value) & 0x00000002) >> 1)
302/* Produces a ALT_UART_IER_DLH_ETBEI_DLHL register field value suitable for setting the register. */
303#define ALT_UART_IER_DLH_ETBEI_DLHL_SET(value) (((value) << 1) & 0x00000002)
304
305/*
306 * Field : DLH[2] and Enable Receiver Line Status - elsi_dhl2
307 *
308 * Divisor Latch High Register:
309 *
310 * Bit 2 of DLH value.
311 *
312 * Interrupt Enable Register:
313 *
314 * This is used to enable/disable the generation of Receiver Line Status Interrupt.
315 * This is the highest priority interrupt.
316 *
317 * Field Enumeration Values:
318 *
319 * Enum | Value | Description
320 * :----------------------------------|:------|:----------------------------
321 * ALT_UART_IER_DLH_ELSI_DHL2_E_DISD | 0x0 | Disable interrupt line stat
322 * ALT_UART_IER_DLH_ELSI_DHL2_E_END | 0x1 | Enable interrupt line stat
323 *
324 * Field Access Macros:
325 *
326 */
327/*
328 * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2
329 *
330 * Disable interrupt line stat
331 */
332#define ALT_UART_IER_DLH_ELSI_DHL2_E_DISD 0x0
333/*
334 * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2
335 *
336 * Enable interrupt line stat
337 */
338#define ALT_UART_IER_DLH_ELSI_DHL2_E_END 0x1
339
340/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
341#define ALT_UART_IER_DLH_ELSI_DHL2_LSB 2
342/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
343#define ALT_UART_IER_DLH_ELSI_DHL2_MSB 2
344/* The width in bits of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
345#define ALT_UART_IER_DLH_ELSI_DHL2_WIDTH 1
346/* The mask used to set the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */
347#define ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK 0x00000004
348/* The mask used to clear the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */
349#define ALT_UART_IER_DLH_ELSI_DHL2_CLR_MSK 0xfffffffb
350/* The reset value of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
351#define ALT_UART_IER_DLH_ELSI_DHL2_RESET 0x0
352/* Extracts the ALT_UART_IER_DLH_ELSI_DHL2 field value from a register. */
353#define ALT_UART_IER_DLH_ELSI_DHL2_GET(value) (((value) & 0x00000004) >> 2)
354/* Produces a ALT_UART_IER_DLH_ELSI_DHL2 register field value suitable for setting the register. */
355#define ALT_UART_IER_DLH_ELSI_DHL2_SET(value) (((value) << 2) & 0x00000004)
356
357/*
358 * Field : DLH[3] and Enable Modem Status Interrupt - edssi_dhl3
359 *
360 * Divisor Latch High Register:
361 *
362 * Bit 3 of DLH value.
363 *
364 * Interrupt Enable Register:
365 *
366 * This is used to enable/disable the generation of Modem Status Interrupts. This
367 * is the fourth highest priority interrupt.
368 *
369 * Field Enumeration Values:
370 *
371 * Enum | Value | Description
372 * :-----------------------------------|:------|:-------------------------------
373 * ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD | 0x0 | disable modem status interrupt
374 * ALT_UART_IER_DLH_EDSSI_DHL3_E_END | 0x1 | enable modem status interrupt
375 *
376 * Field Access Macros:
377 *
378 */
379/*
380 * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3
381 *
382 * disable modem status interrupt
383 */
384#define ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD 0x0
385/*
386 * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3
387 *
388 * enable modem status interrupt
389 */
390#define ALT_UART_IER_DLH_EDSSI_DHL3_E_END 0x1
391
392/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
393#define ALT_UART_IER_DLH_EDSSI_DHL3_LSB 3
394/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
395#define ALT_UART_IER_DLH_EDSSI_DHL3_MSB 3
396/* The width in bits of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
397#define ALT_UART_IER_DLH_EDSSI_DHL3_WIDTH 1
398/* The mask used to set the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */
399#define ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK 0x00000008
400/* The mask used to clear the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */
401#define ALT_UART_IER_DLH_EDSSI_DHL3_CLR_MSK 0xfffffff7
402/* The reset value of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
403#define ALT_UART_IER_DLH_EDSSI_DHL3_RESET 0x0
404/* Extracts the ALT_UART_IER_DLH_EDSSI_DHL3 field value from a register. */
405#define ALT_UART_IER_DLH_EDSSI_DHL3_GET(value) (((value) & 0x00000008) >> 3)
406/* Produces a ALT_UART_IER_DLH_EDSSI_DHL3 register field value suitable for setting the register. */
407#define ALT_UART_IER_DLH_EDSSI_DHL3_SET(value) (((value) << 3) & 0x00000008)
408
409/*
410 * Field : DLH[4] - dlh4
411 *
412 * Bit 4 of DLH value.
413 *
414 * Field Access Macros:
415 *
416 */
417/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH4 register field. */
418#define ALT_UART_IER_DLH_DLH4_LSB 4
419/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH4 register field. */
420#define ALT_UART_IER_DLH_DLH4_MSB 4
421/* The width in bits of the ALT_UART_IER_DLH_DLH4 register field. */
422#define ALT_UART_IER_DLH_DLH4_WIDTH 1
423/* The mask used to set the ALT_UART_IER_DLH_DLH4 register field value. */
424#define ALT_UART_IER_DLH_DLH4_SET_MSK 0x00000010
425/* The mask used to clear the ALT_UART_IER_DLH_DLH4 register field value. */
426#define ALT_UART_IER_DLH_DLH4_CLR_MSK 0xffffffef
427/* The reset value of the ALT_UART_IER_DLH_DLH4 register field. */
428#define ALT_UART_IER_DLH_DLH4_RESET 0x0
429/* Extracts the ALT_UART_IER_DLH_DLH4 field value from a register. */
430#define ALT_UART_IER_DLH_DLH4_GET(value) (((value) & 0x00000010) >> 4)
431/* Produces a ALT_UART_IER_DLH_DLH4 register field value suitable for setting the register. */
432#define ALT_UART_IER_DLH_DLH4_SET(value) (((value) << 4) & 0x00000010)
433
434/*
435 * Field : DLH[5] - dlh5
436 *
437 * Bit 5 of DLH value.
438 *
439 * Field Access Macros:
440 *
441 */
442/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH5 register field. */
443#define ALT_UART_IER_DLH_DLH5_LSB 5
444/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH5 register field. */
445#define ALT_UART_IER_DLH_DLH5_MSB 5
446/* The width in bits of the ALT_UART_IER_DLH_DLH5 register field. */
447#define ALT_UART_IER_DLH_DLH5_WIDTH 1
448/* The mask used to set the ALT_UART_IER_DLH_DLH5 register field value. */
449#define ALT_UART_IER_DLH_DLH5_SET_MSK 0x00000020
450/* The mask used to clear the ALT_UART_IER_DLH_DLH5 register field value. */
451#define ALT_UART_IER_DLH_DLH5_CLR_MSK 0xffffffdf
452/* The reset value of the ALT_UART_IER_DLH_DLH5 register field. */
453#define ALT_UART_IER_DLH_DLH5_RESET 0x0
454/* Extracts the ALT_UART_IER_DLH_DLH5 field value from a register. */
455#define ALT_UART_IER_DLH_DLH5_GET(value) (((value) & 0x00000020) >> 5)
456/* Produces a ALT_UART_IER_DLH_DLH5 register field value suitable for setting the register. */
457#define ALT_UART_IER_DLH_DLH5_SET(value) (((value) << 5) & 0x00000020)
458
459/*
460 * Field : DLH[6] - dlh6
461 *
462 * Bit 6 of DLH value.
463 *
464 * Field Access Macros:
465 *
466 */
467/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH6 register field. */
468#define ALT_UART_IER_DLH_DLH6_LSB 6
469/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH6 register field. */
470#define ALT_UART_IER_DLH_DLH6_MSB 6
471/* The width in bits of the ALT_UART_IER_DLH_DLH6 register field. */
472#define ALT_UART_IER_DLH_DLH6_WIDTH 1
473/* The mask used to set the ALT_UART_IER_DLH_DLH6 register field value. */
474#define ALT_UART_IER_DLH_DLH6_SET_MSK 0x00000040
475/* The mask used to clear the ALT_UART_IER_DLH_DLH6 register field value. */
476#define ALT_UART_IER_DLH_DLH6_CLR_MSK 0xffffffbf
477/* The reset value of the ALT_UART_IER_DLH_DLH6 register field. */
478#define ALT_UART_IER_DLH_DLH6_RESET 0x0
479/* Extracts the ALT_UART_IER_DLH_DLH6 field value from a register. */
480#define ALT_UART_IER_DLH_DLH6_GET(value) (((value) & 0x00000040) >> 6)
481/* Produces a ALT_UART_IER_DLH_DLH6 register field value suitable for setting the register. */
482#define ALT_UART_IER_DLH_DLH6_SET(value) (((value) << 6) & 0x00000040)
483
484/*
485 * Field : DLH[7] and PTIME THRE Interrupt Mode Enable - ptime_dlh7
486 *
487 * Divisor Latch High Register:
488 *
489 * Bit 7 of DLH value.
490 *
491 * Interrupt Enable Register:
492 *
493 * This is used to enable/disable the generation of THRE Interrupt.
494 *
495 * Field Enumeration Values:
496 *
497 * Enum | Value | Description
498 * :-----------------------------------|:------|:------------------------------------
499 * ALT_UART_IER_DLH_PTIME_DLH7_E_DISD | 0x0 | disable tx-hold-reg-empty interrupt
500 * ALT_UART_IER_DLH_PTIME_DLH7_E_END | 0x1 | enable tx-hold-reg-empty interrupt
501 *
502 * Field Access Macros:
503 *
504 */
505/*
506 * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7
507 *
508 * disable tx-hold-reg-empty interrupt
509 */
510#define ALT_UART_IER_DLH_PTIME_DLH7_E_DISD 0x0
511/*
512 * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7
513 *
514 * enable tx-hold-reg-empty interrupt
515 */
516#define ALT_UART_IER_DLH_PTIME_DLH7_E_END 0x1
517
518/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
519#define ALT_UART_IER_DLH_PTIME_DLH7_LSB 7
520/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
521#define ALT_UART_IER_DLH_PTIME_DLH7_MSB 7
522/* The width in bits of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
523#define ALT_UART_IER_DLH_PTIME_DLH7_WIDTH 1
524/* The mask used to set the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */
525#define ALT_UART_IER_DLH_PTIME_DLH7_SET_MSK 0x00000080
526/* The mask used to clear the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */
527#define ALT_UART_IER_DLH_PTIME_DLH7_CLR_MSK 0xffffff7f
528/* The reset value of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
529#define ALT_UART_IER_DLH_PTIME_DLH7_RESET 0x0
530/* Extracts the ALT_UART_IER_DLH_PTIME_DLH7 field value from a register. */
531#define ALT_UART_IER_DLH_PTIME_DLH7_GET(value) (((value) & 0x00000080) >> 7)
532/* Produces a ALT_UART_IER_DLH_PTIME_DLH7 register field value suitable for setting the register. */
533#define ALT_UART_IER_DLH_PTIME_DLH7_SET(value) (((value) << 7) & 0x00000080)
534
535#ifndef __ASSEMBLY__
536/*
537 * WARNING: The C register and register group struct declarations are provided for
538 * convenience and illustrative purposes. They should, however, be used with
539 * caution as the C language standard provides no guarantees about the alignment or
540 * atomicity of device memory accesses. The recommended practice for writing
541 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
542 * alt_write_word() functions.
543 *
544 * The struct declaration for register ALT_UART_IER_DLH.
545 */
546 struct ALT_UART_IER_DLH_s
547{
548 uint32_t erbfi_dlh0 : 1; /* DLH[0] and Receive Data Interrupt Enable */
549 uint32_t etbei_dlhl : 1; /* DLH[1] and Transmit Data Interrupt Control */
550 uint32_t elsi_dhl2 : 1; /* DLH[2] and Enable Receiver Line Status */
551 uint32_t edssi_dhl3 : 1; /* DLH[3] and Enable Modem Status Interrupt */
552 uint32_t dlh4 : 1; /* DLH[4] */
553 uint32_t dlh5 : 1; /* DLH[5] */
554 uint32_t dlh6 : 1; /* DLH[6] */
555 uint32_t ptime_dlh7 : 1; /* DLH[7] and PTIME THRE Interrupt Mode Enable */
556 uint32_t : 24; /* *UNDEFINED* */
557};
558
559/* The typedef declaration for register ALT_UART_IER_DLH. */
560typedef volatile struct ALT_UART_IER_DLH_s ALT_UART_IER_DLH_t;
561#endif /* __ASSEMBLY__ */
562
563/* The byte offset of the ALT_UART_IER_DLH register from the beginning of the component. */
564#define ALT_UART_IER_DLH_OFST 0x4
565/* The address of the ALT_UART_IER_DLH register. */
566#define ALT_UART_IER_DLH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IER_DLH_OFST))
567
568/*
569 * Register : Interrupt Identity Register (when read) - iir
570 *
571 * Returns interrupt identification and FIFO enable/disable when read.
572 *
573 * Register Layout
574 *
575 * Bits | Access | Reset | Description
576 * :-------|:-------|:------|:-------------
577 * [3:0] | R | 0x1 | Interrupt ID
578 * [5:4] | ??? | 0x0 | *UNDEFINED*
579 * [7:6] | R | 0x0 | FIFO Enabled
580 * [31:8] | ??? | 0x0 | *UNDEFINED*
581 *
582 */
583/*
584 * Field : Interrupt ID - id
585 *
586 * This indicates the highest priority pending interrupt.
587 *
588 * Field Enumeration Values:
589 *
590 * Enum | Value | Description
591 * :---------------------------------|:------|:-----------------------
592 * ALT_UART_IIR_ID_E_MODMSTAT | 0x0 | Modem status
593 * ALT_UART_IIR_ID_E_NOINTRPENDING | 0x1 | No Interrupt pending
594 * ALT_UART_IIR_ID_E_THREMPTY | 0x2 | THR empty
595 * ALT_UART_IIR_ID_E_RXDATAVAILABLE | 0x4 | Receive data available
596 * ALT_UART_IIR_ID_E_RXLINESTAT | 0x6 | Receive line status
597 * ALT_UART_IIR_ID_E_CHARTMO | 0xc | Character timeout
598 *
599 * Field Access Macros:
600 *
601 */
602/*
603 * Enumerated value for register field ALT_UART_IIR_ID
604 *
605 * Modem status
606 */
607#define ALT_UART_IIR_ID_E_MODMSTAT 0x0
608/*
609 * Enumerated value for register field ALT_UART_IIR_ID
610 *
611 * No Interrupt pending
612 */
613#define ALT_UART_IIR_ID_E_NOINTRPENDING 0x1
614/*
615 * Enumerated value for register field ALT_UART_IIR_ID
616 *
617 * THR empty
618 */
619#define ALT_UART_IIR_ID_E_THREMPTY 0x2
620/*
621 * Enumerated value for register field ALT_UART_IIR_ID
622 *
623 * Receive data available
624 */
625#define ALT_UART_IIR_ID_E_RXDATAVAILABLE 0x4
626/*
627 * Enumerated value for register field ALT_UART_IIR_ID
628 *
629 * Receive line status
630 */
631#define ALT_UART_IIR_ID_E_RXLINESTAT 0x6
632/*
633 * Enumerated value for register field ALT_UART_IIR_ID
634 *
635 * Character timeout
636 */
637#define ALT_UART_IIR_ID_E_CHARTMO 0xc
638
639/* The Least Significant Bit (LSB) position of the ALT_UART_IIR_ID register field. */
640#define ALT_UART_IIR_ID_LSB 0
641/* The Most Significant Bit (MSB) position of the ALT_UART_IIR_ID register field. */
642#define ALT_UART_IIR_ID_MSB 3
643/* The width in bits of the ALT_UART_IIR_ID register field. */
644#define ALT_UART_IIR_ID_WIDTH 4
645/* The mask used to set the ALT_UART_IIR_ID register field value. */
646#define ALT_UART_IIR_ID_SET_MSK 0x0000000f
647/* The mask used to clear the ALT_UART_IIR_ID register field value. */
648#define ALT_UART_IIR_ID_CLR_MSK 0xfffffff0
649/* The reset value of the ALT_UART_IIR_ID register field. */
650#define ALT_UART_IIR_ID_RESET 0x1
651/* Extracts the ALT_UART_IIR_ID field value from a register. */
652#define ALT_UART_IIR_ID_GET(value) (((value) & 0x0000000f) >> 0)
653/* Produces a ALT_UART_IIR_ID register field value suitable for setting the register. */
654#define ALT_UART_IIR_ID_SET(value) (((value) << 0) & 0x0000000f)
655
656/*
657 * Field : FIFO Enabled - fifoen
658 *
659 * This is used to indicate whether the FIFO's are enabled or disabled.
660 *
661 * Field Enumeration Values:
662 *
663 * Enum | Value | Description
664 * :---------------------------|:------|:--------------
665 * ALT_UART_IIR_FIFOEN_E_DISD | 0x0 | FIFO disabled
666 * ALT_UART_IIR_FIFOEN_E_END | 0x3 | FIFO enabled
667 *
668 * Field Access Macros:
669 *
670 */
671/*
672 * Enumerated value for register field ALT_UART_IIR_FIFOEN
673 *
674 * FIFO disabled
675 */
676#define ALT_UART_IIR_FIFOEN_E_DISD 0x0
677/*
678 * Enumerated value for register field ALT_UART_IIR_FIFOEN
679 *
680 * FIFO enabled
681 */
682#define ALT_UART_IIR_FIFOEN_E_END 0x3
683
684/* The Least Significant Bit (LSB) position of the ALT_UART_IIR_FIFOEN register field. */
685#define ALT_UART_IIR_FIFOEN_LSB 6
686/* The Most Significant Bit (MSB) position of the ALT_UART_IIR_FIFOEN register field. */
687#define ALT_UART_IIR_FIFOEN_MSB 7
688/* The width in bits of the ALT_UART_IIR_FIFOEN register field. */
689#define ALT_UART_IIR_FIFOEN_WIDTH 2
690/* The mask used to set the ALT_UART_IIR_FIFOEN register field value. */
691#define ALT_UART_IIR_FIFOEN_SET_MSK 0x000000c0
692/* The mask used to clear the ALT_UART_IIR_FIFOEN register field value. */
693#define ALT_UART_IIR_FIFOEN_CLR_MSK 0xffffff3f
694/* The reset value of the ALT_UART_IIR_FIFOEN register field. */
695#define ALT_UART_IIR_FIFOEN_RESET 0x0
696/* Extracts the ALT_UART_IIR_FIFOEN field value from a register. */
697#define ALT_UART_IIR_FIFOEN_GET(value) (((value) & 0x000000c0) >> 6)
698/* Produces a ALT_UART_IIR_FIFOEN register field value suitable for setting the register. */
699#define ALT_UART_IIR_FIFOEN_SET(value) (((value) << 6) & 0x000000c0)
700
701#ifndef __ASSEMBLY__
702/*
703 * WARNING: The C register and register group struct declarations are provided for
704 * convenience and illustrative purposes. They should, however, be used with
705 * caution as the C language standard provides no guarantees about the alignment or
706 * atomicity of device memory accesses. The recommended practice for writing
707 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
708 * alt_write_word() functions.
709 *
710 * The struct declaration for register ALT_UART_IIR.
711 */
712 struct ALT_UART_IIR_s
713{
714 const uint32_t id : 4; /* Interrupt ID */
715 uint32_t : 2; /* *UNDEFINED* */
716 const uint32_t fifoen : 2; /* FIFO Enabled */
717 uint32_t : 24; /* *UNDEFINED* */
718};
719
720/* The typedef declaration for register ALT_UART_IIR. */
721typedef volatile struct ALT_UART_IIR_s ALT_UART_IIR_t;
722#endif /* __ASSEMBLY__ */
723
724/* The byte offset of the ALT_UART_IIR register from the beginning of the component. */
725#define ALT_UART_IIR_OFST 0x8
726/* The address of the ALT_UART_IIR register. */
727#define ALT_UART_IIR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IIR_OFST))
728
729/*
730 * Register : FIFO Control (when written) - fcr
731 *
732 * Controls FIFO Operations when written.
733 *
734 * Register Layout
735 *
736 * Bits | Access | Reset | Description
737 * :-------|:-------|:--------|:-----------------------
738 * [0] | W | Unknown | FIFO Enable
739 * [1] | W | Unknown | Rx FIFO Reset
740 * [2] | W | Unknown | Tx FIFO Reset
741 * [3] | W | Unknown | DMA Mode
742 * [5:4] | W | Unknown | Tx Empty Trigger Level
743 * [7:6] | W | Unknown | Rx Trigger Level
744 * [31:8] | ??? | 0x0 | *UNDEFINED*
745 *
746 */
747/*
748 * Field : FIFO Enable - fifoe
749 *
750 * Enables/disables the transmit (Tx) and receive (Rx ) FIFO's. Whenever the value
751 * of this bit is changed both the Tx and Rx controller portion of FIFO's will be
752 * reset.
753 *
754 * Field Enumeration Values:
755 *
756 * Enum | Value | Description
757 * :--------------------------|:------|:---------------
758 * ALT_UART_FCR_FIFOE_E_DISD | 0x0 | FIFOs disabled
759 * ALT_UART_FCR_FIFOE_E_END | 0x1 | FIFOs enabled
760 *
761 * Field Access Macros:
762 *
763 */
764/*
765 * Enumerated value for register field ALT_UART_FCR_FIFOE
766 *
767 * FIFOs disabled
768 */
769#define ALT_UART_FCR_FIFOE_E_DISD 0x0
770/*
771 * Enumerated value for register field ALT_UART_FCR_FIFOE
772 *
773 * FIFOs enabled
774 */
775#define ALT_UART_FCR_FIFOE_E_END 0x1
776
777/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_FIFOE register field. */
778#define ALT_UART_FCR_FIFOE_LSB 0
779/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_FIFOE register field. */
780#define ALT_UART_FCR_FIFOE_MSB 0
781/* The width in bits of the ALT_UART_FCR_FIFOE register field. */
782#define ALT_UART_FCR_FIFOE_WIDTH 1
783/* The mask used to set the ALT_UART_FCR_FIFOE register field value. */
784#define ALT_UART_FCR_FIFOE_SET_MSK 0x00000001
785/* The mask used to clear the ALT_UART_FCR_FIFOE register field value. */
786#define ALT_UART_FCR_FIFOE_CLR_MSK 0xfffffffe
787/* The reset value of the ALT_UART_FCR_FIFOE register field is UNKNOWN. */
788#define ALT_UART_FCR_FIFOE_RESET 0x0
789/* Extracts the ALT_UART_FCR_FIFOE field value from a register. */
790#define ALT_UART_FCR_FIFOE_GET(value) (((value) & 0x00000001) >> 0)
791/* Produces a ALT_UART_FCR_FIFOE register field value suitable for setting the register. */
792#define ALT_UART_FCR_FIFOE_SET(value) (((value) << 0) & 0x00000001)
793
794/*
795 * Field : Rx FIFO Reset - rfifor
796 *
797 * Resets the control portion of the receive FIFO and treats the FIFO as empty.
798 * This will also de-assert the DMA Rxrequest and single signals. Note that this
799 * bit is self-clearing' and it is not necessary to clear this bit.
800 *
801 * Field Enumeration Values:
802 *
803 * Enum | Value | Description
804 * :----------------------------|:------|:----------------------------
805 * ALT_UART_FCR_RFIFOR_E_NORST | 0x0 | No Reset of Rx FIFO Control
806 * ALT_UART_FCR_RFIFOR_E_RST | 0x1 | Resets of Rx FIFO Control
807 *
808 * Field Access Macros:
809 *
810 */
811/*
812 * Enumerated value for register field ALT_UART_FCR_RFIFOR
813 *
814 * No Reset of Rx FIFO Control
815 */
816#define ALT_UART_FCR_RFIFOR_E_NORST 0x0
817/*
818 * Enumerated value for register field ALT_UART_FCR_RFIFOR
819 *
820 * Resets of Rx FIFO Control
821 */
822#define ALT_UART_FCR_RFIFOR_E_RST 0x1
823
824/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RFIFOR register field. */
825#define ALT_UART_FCR_RFIFOR_LSB 1
826/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RFIFOR register field. */
827#define ALT_UART_FCR_RFIFOR_MSB 1
828/* The width in bits of the ALT_UART_FCR_RFIFOR register field. */
829#define ALT_UART_FCR_RFIFOR_WIDTH 1
830/* The mask used to set the ALT_UART_FCR_RFIFOR register field value. */
831#define ALT_UART_FCR_RFIFOR_SET_MSK 0x00000002
832/* The mask used to clear the ALT_UART_FCR_RFIFOR register field value. */
833#define ALT_UART_FCR_RFIFOR_CLR_MSK 0xfffffffd
834/* The reset value of the ALT_UART_FCR_RFIFOR register field is UNKNOWN. */
835#define ALT_UART_FCR_RFIFOR_RESET 0x0
836/* Extracts the ALT_UART_FCR_RFIFOR field value from a register. */
837#define ALT_UART_FCR_RFIFOR_GET(value) (((value) & 0x00000002) >> 1)
838/* Produces a ALT_UART_FCR_RFIFOR register field value suitable for setting the register. */
839#define ALT_UART_FCR_RFIFOR_SET(value) (((value) << 1) & 0x00000002)
840
841/*
842 * Field : Tx FIFO Reset - xfifor
843 *
844 * Resets the control portion of the transmit FIFO and treats the FIFO as empty.
845 * This will also de-assert the DMA Tx request and single signals when additional
846 * DMA handshaking is used.
847 *
848 * Note that this bit is 'self-clearing' and it is not necessary to clear this bit.
849 *
850 * Field Enumeration Values:
851 *
852 * Enum | Value | Description
853 * :----------------------------|:------|:----------------------------
854 * ALT_UART_FCR_XFIFOR_E_NORST | 0x0 | No Reset of Tx FIFO Control
855 * ALT_UART_FCR_XFIFOR_E_RST | 0x1 | Resets Tx FIFO Control
856 *
857 * Field Access Macros:
858 *
859 */
860/*
861 * Enumerated value for register field ALT_UART_FCR_XFIFOR
862 *
863 * No Reset of Tx FIFO Control
864 */
865#define ALT_UART_FCR_XFIFOR_E_NORST 0x0
866/*
867 * Enumerated value for register field ALT_UART_FCR_XFIFOR
868 *
869 * Resets Tx FIFO Control
870 */
871#define ALT_UART_FCR_XFIFOR_E_RST 0x1
872
873/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_XFIFOR register field. */
874#define ALT_UART_FCR_XFIFOR_LSB 2
875/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_XFIFOR register field. */
876#define ALT_UART_FCR_XFIFOR_MSB 2
877/* The width in bits of the ALT_UART_FCR_XFIFOR register field. */
878#define ALT_UART_FCR_XFIFOR_WIDTH 1
879/* The mask used to set the ALT_UART_FCR_XFIFOR register field value. */
880#define ALT_UART_FCR_XFIFOR_SET_MSK 0x00000004
881/* The mask used to clear the ALT_UART_FCR_XFIFOR register field value. */
882#define ALT_UART_FCR_XFIFOR_CLR_MSK 0xfffffffb
883/* The reset value of the ALT_UART_FCR_XFIFOR register field is UNKNOWN. */
884#define ALT_UART_FCR_XFIFOR_RESET 0x0
885/* Extracts the ALT_UART_FCR_XFIFOR field value from a register. */
886#define ALT_UART_FCR_XFIFOR_GET(value) (((value) & 0x00000004) >> 2)
887/* Produces a ALT_UART_FCR_XFIFOR register field value suitable for setting the register. */
888#define ALT_UART_FCR_XFIFOR_SET(value) (((value) << 2) & 0x00000004)
889
890/*
891 * Field : DMA Mode - dmam
892 *
893 * This determines the DMA signalling mode used for the uart_dma_tx_req_n and
894 * uart_dma_rx_req_n output signals when additional DMA handshaking signals are not
895 * selected. DMA mode 0 supports single DMA data transfers at a time. In mode 0,
896 * the uart_dma_tx_req_n signal goes active low under the following conditions:
897 *
898 * * When the Transmitter Holding Register is empty in non-FIFO mode.
899 *
900 * * When the transmitter FIFO is empty in FIFO mode with Programmable THRE
901 * interrupt mode disabled.
902 *
903 * * When the transmitter FIFO is at or below the programmed threshold with
904 * Programmable THRE interrupt mode enabled.
905 *
906 * It goes inactive under the following conditions
907 *
908 * * When a single character has been written into the Transmitter Holding
909 * Register or transmitter FIFO with Programmable THRE interrupt mode disabled.
910 *
911 * * When the transmitter FIFO is above the threshold with Programmable THRE
912 * interrupt mode enabled.
913 *
914 * DMA mode 1 supports multi-DMA data transfers, where multiple transfers are made
915 * continuously until the receiver FIFO has been emptied or the transmit FIFO has
916 * been filled. In mode 1 the uart_dma_tx_req_n signal is asserted under the
917 * following conditions:
918 *
919 * * When the transmitter FIFO is empty with Programmable THRE interrupt mode
920 * disabled.
921 *
922 * * When the transmitter FIFO is at or below the programmed threshold with
923 * Programmable THRE interrupt mode enabled.
924 *
925 * Field Enumeration Values:
926 *
927 * Enum | Value | Description
928 * :---------------------------|:------|:---------------------------
929 * ALT_UART_FCR_DMAM_E_SINGLE | 0x0 | Single DMA Transfer Mode
930 * ALT_UART_FCR_DMAM_E_MULT | 0x1 | Multiple DMA Transfer Mode
931 *
932 * Field Access Macros:
933 *
934 */
935/*
936 * Enumerated value for register field ALT_UART_FCR_DMAM
937 *
938 * Single DMA Transfer Mode
939 */
940#define ALT_UART_FCR_DMAM_E_SINGLE 0x0
941/*
942 * Enumerated value for register field ALT_UART_FCR_DMAM
943 *
944 * Multiple DMA Transfer Mode
945 */
946#define ALT_UART_FCR_DMAM_E_MULT 0x1
947
948/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_DMAM register field. */
949#define ALT_UART_FCR_DMAM_LSB 3
950/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_DMAM register field. */
951#define ALT_UART_FCR_DMAM_MSB 3
952/* The width in bits of the ALT_UART_FCR_DMAM register field. */
953#define ALT_UART_FCR_DMAM_WIDTH 1
954/* The mask used to set the ALT_UART_FCR_DMAM register field value. */
955#define ALT_UART_FCR_DMAM_SET_MSK 0x00000008
956/* The mask used to clear the ALT_UART_FCR_DMAM register field value. */
957#define ALT_UART_FCR_DMAM_CLR_MSK 0xfffffff7
958/* The reset value of the ALT_UART_FCR_DMAM register field is UNKNOWN. */
959#define ALT_UART_FCR_DMAM_RESET 0x0
960/* Extracts the ALT_UART_FCR_DMAM field value from a register. */
961#define ALT_UART_FCR_DMAM_GET(value) (((value) & 0x00000008) >> 3)
962/* Produces a ALT_UART_FCR_DMAM register field value suitable for setting the register. */
963#define ALT_UART_FCR_DMAM_SET(value) (((value) << 3) & 0x00000008)
964
965/*
966 * Field : Tx Empty Trigger Level - tet
967 *
968 * This is used to select the empty threshold level at which the THRE Interrupts
969 * will be generated when the mode is active. It also determines when the uart DMA
970 * transmit request signal uart_dma_tx_req_n will be asserted when in certain modes
971 * of operation.
972 *
973 * Field Enumeration Values:
974 *
975 * Enum | Value | Description
976 * :-------------------------------|:------|:-----------------------
977 * ALT_UART_FCR_TET_E_FIFOEMPTY | 0x0 | FIFO empty
978 * ALT_UART_FCR_TET_E_TWOCHARS | 0x1 | Two characters in FIFO
979 * ALT_UART_FCR_TET_E_QUARTERFULL | 0x2 | FIFO 1/4 full
980 * ALT_UART_FCR_TET_E_HALFFULL | 0x3 | FIFO 1/2 full
981 *
982 * Field Access Macros:
983 *
984 */
985/*
986 * Enumerated value for register field ALT_UART_FCR_TET
987 *
988 * FIFO empty
989 */
990#define ALT_UART_FCR_TET_E_FIFOEMPTY 0x0
991/*
992 * Enumerated value for register field ALT_UART_FCR_TET
993 *
994 * Two characters in FIFO
995 */
996#define ALT_UART_FCR_TET_E_TWOCHARS 0x1
997/*
998 * Enumerated value for register field ALT_UART_FCR_TET
999 *
1000 * FIFO 1/4 full
1001 */
1002#define ALT_UART_FCR_TET_E_QUARTERFULL 0x2
1003/*
1004 * Enumerated value for register field ALT_UART_FCR_TET
1005 *
1006 * FIFO 1/2 full
1007 */
1008#define ALT_UART_FCR_TET_E_HALFFULL 0x3
1009
1010/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_TET register field. */
1011#define ALT_UART_FCR_TET_LSB 4
1012/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_TET register field. */
1013#define ALT_UART_FCR_TET_MSB 5
1014/* The width in bits of the ALT_UART_FCR_TET register field. */
1015#define ALT_UART_FCR_TET_WIDTH 2
1016/* The mask used to set the ALT_UART_FCR_TET register field value. */
1017#define ALT_UART_FCR_TET_SET_MSK 0x00000030
1018/* The mask used to clear the ALT_UART_FCR_TET register field value. */
1019#define ALT_UART_FCR_TET_CLR_MSK 0xffffffcf
1020/* The reset value of the ALT_UART_FCR_TET register field is UNKNOWN. */
1021#define ALT_UART_FCR_TET_RESET 0x0
1022/* Extracts the ALT_UART_FCR_TET field value from a register. */
1023#define ALT_UART_FCR_TET_GET(value) (((value) & 0x00000030) >> 4)
1024/* Produces a ALT_UART_FCR_TET register field value suitable for setting the register. */
1025#define ALT_UART_FCR_TET_SET(value) (((value) << 4) & 0x00000030)
1026
1027/*
1028 * Field : Rx Trigger Level - rt
1029 *
1030 * This register is configured to implement FIFOs. Bits[7:6], Rx Trigger (or RT):
1031 * This is used to select the trigger level in the receiver FIFO at which the
1032 * Received Data Available Interrupt will be generated. In auto flow control mode
1033 * it is used to determine when the uart_rts_n signal will be de-asserted. It also
1034 * determines when the uart_dma_rx_req_n signal will be asserted when in certain
1035 * modes of operation.
1036 *
1037 * Field Enumeration Values:
1038 *
1039 * Enum | Value | Description
1040 * :------------------------------|:------|:----------------------
1041 * ALT_UART_FCR_RT_E_ONECHAR | 0x0 | one character in fifo
1042 * ALT_UART_FCR_RT_E_QUARTERFULL | 0x1 | FIFO 1/4 full
1043 * ALT_UART_FCR_RT_E_HALFFULL | 0x2 | FIFO 1/2 full
1044 * ALT_UART_FCR_RT_E_FULLLESS2 | 0x3 | FIFO 2 less than full
1045 *
1046 * Field Access Macros:
1047 *
1048 */
1049/*
1050 * Enumerated value for register field ALT_UART_FCR_RT
1051 *
1052 * one character in fifo
1053 */
1054#define ALT_UART_FCR_RT_E_ONECHAR 0x0
1055/*
1056 * Enumerated value for register field ALT_UART_FCR_RT
1057 *
1058 * FIFO 1/4 full
1059 */
1060#define ALT_UART_FCR_RT_E_QUARTERFULL 0x1
1061/*
1062 * Enumerated value for register field ALT_UART_FCR_RT
1063 *
1064 * FIFO 1/2 full
1065 */
1066#define ALT_UART_FCR_RT_E_HALFFULL 0x2
1067/*
1068 * Enumerated value for register field ALT_UART_FCR_RT
1069 *
1070 * FIFO 2 less than full
1071 */
1072#define ALT_UART_FCR_RT_E_FULLLESS2 0x3
1073
1074/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RT register field. */
1075#define ALT_UART_FCR_RT_LSB 6
1076/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RT register field. */
1077#define ALT_UART_FCR_RT_MSB 7
1078/* The width in bits of the ALT_UART_FCR_RT register field. */
1079#define ALT_UART_FCR_RT_WIDTH 2
1080/* The mask used to set the ALT_UART_FCR_RT register field value. */
1081#define ALT_UART_FCR_RT_SET_MSK 0x000000c0
1082/* The mask used to clear the ALT_UART_FCR_RT register field value. */
1083#define ALT_UART_FCR_RT_CLR_MSK 0xffffff3f
1084/* The reset value of the ALT_UART_FCR_RT register field is UNKNOWN. */
1085#define ALT_UART_FCR_RT_RESET 0x0
1086/* Extracts the ALT_UART_FCR_RT field value from a register. */
1087#define ALT_UART_FCR_RT_GET(value) (((value) & 0x000000c0) >> 6)
1088/* Produces a ALT_UART_FCR_RT register field value suitable for setting the register. */
1089#define ALT_UART_FCR_RT_SET(value) (((value) << 6) & 0x000000c0)
1090
1091#ifndef __ASSEMBLY__
1092/*
1093 * WARNING: The C register and register group struct declarations are provided for
1094 * convenience and illustrative purposes. They should, however, be used with
1095 * caution as the C language standard provides no guarantees about the alignment or
1096 * atomicity of device memory accesses. The recommended practice for writing
1097 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1098 * alt_write_word() functions.
1099 *
1100 * The struct declaration for register ALT_UART_FCR.
1101 */
1102 struct ALT_UART_FCR_s
1103{
1104 uint32_t fifoe : 1; /* FIFO Enable */
1105 uint32_t rfifor : 1; /* Rx FIFO Reset */
1106 uint32_t xfifor : 1; /* Tx FIFO Reset */
1107 uint32_t dmam : 1; /* DMA Mode */
1108 uint32_t tet : 2; /* Tx Empty Trigger Level */
1109 uint32_t rt : 2; /* Rx Trigger Level */
1110 uint32_t : 24; /* *UNDEFINED* */
1111};
1112
1113/* The typedef declaration for register ALT_UART_FCR. */
1114typedef volatile struct ALT_UART_FCR_s ALT_UART_FCR_t;
1115#endif /* __ASSEMBLY__ */
1116
1117/* The byte offset of the ALT_UART_FCR register from the beginning of the component. */
1118#define ALT_UART_FCR_OFST 0x8
1119/* The address of the ALT_UART_FCR register. */
1120#define ALT_UART_FCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FCR_OFST))
1121
1122/*
1123 * Register : Line Control Register (When Written) - lcr
1124 *
1125 * Formats serial data.
1126 *
1127 * Register Layout
1128 *
1129 * Bits | Access | Reset | Description
1130 * :-------|:-------|:------|:-------------------------
1131 * [1:0] | RW | 0x0 | Data Length Select
1132 * [2] | RW | 0x0 | Stop Bits
1133 * [3] | RW | 0x0 | Parity Enable
1134 * [4] | RW | 0x0 | Even Parity Select
1135 * [5] | ??? | 0x0 | *UNDEFINED*
1136 * [6] | RW | 0x0 | Break Control Bit
1137 * [7] | RW | 0x0 | Divisor Latch Access Bit
1138 * [31:8] | ??? | 0x0 | *UNDEFINED*
1139 *
1140 */
1141/*
1142 * Field : Data Length Select - dls
1143 *
1144 * Data Length Select.Selects the number of data bits per character that the
1145 * peripheral will transmit and receive.
1146 *
1147 * Field Enumeration Values:
1148 *
1149 * Enum | Value | Description
1150 * :------------------------|:------|:------------
1151 * ALT_UART_LCR_DLS_E_LEN5 | 0x0 | 5 bits
1152 * ALT_UART_LCR_DLS_E_LEN6 | 0x1 | 6 bits
1153 * ALT_UART_LCR_DLS_E_LEN7 | 0x2 | 7 bits
1154 * ALT_UART_LCR_DLS_E_LEN8 | 0x3 | 8 bits
1155 *
1156 * Field Access Macros:
1157 *
1158 */
1159/*
1160 * Enumerated value for register field ALT_UART_LCR_DLS
1161 *
1162 * 5 bits
1163 */
1164#define ALT_UART_LCR_DLS_E_LEN5 0x0
1165/*
1166 * Enumerated value for register field ALT_UART_LCR_DLS
1167 *
1168 * 6 bits
1169 */
1170#define ALT_UART_LCR_DLS_E_LEN6 0x1
1171/*
1172 * Enumerated value for register field ALT_UART_LCR_DLS
1173 *
1174 * 7 bits
1175 */
1176#define ALT_UART_LCR_DLS_E_LEN7 0x2
1177/*
1178 * Enumerated value for register field ALT_UART_LCR_DLS
1179 *
1180 * 8 bits
1181 */
1182#define ALT_UART_LCR_DLS_E_LEN8 0x3
1183
1184/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLS register field. */
1185#define ALT_UART_LCR_DLS_LSB 0
1186/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLS register field. */
1187#define ALT_UART_LCR_DLS_MSB 1
1188/* The width in bits of the ALT_UART_LCR_DLS register field. */
1189#define ALT_UART_LCR_DLS_WIDTH 2
1190/* The mask used to set the ALT_UART_LCR_DLS register field value. */
1191#define ALT_UART_LCR_DLS_SET_MSK 0x00000003
1192/* The mask used to clear the ALT_UART_LCR_DLS register field value. */
1193#define ALT_UART_LCR_DLS_CLR_MSK 0xfffffffc
1194/* The reset value of the ALT_UART_LCR_DLS register field. */
1195#define ALT_UART_LCR_DLS_RESET 0x0
1196/* Extracts the ALT_UART_LCR_DLS field value from a register. */
1197#define ALT_UART_LCR_DLS_GET(value) (((value) & 0x00000003) >> 0)
1198/* Produces a ALT_UART_LCR_DLS register field value suitable for setting the register. */
1199#define ALT_UART_LCR_DLS_SET(value) (((value) << 0) & 0x00000003)
1200
1201/*
1202 * Field : Stop Bits - stop
1203 *
1204 * Number of stop bits. Used to select the number of stop bits per character that
1205 * the peripheral will transmit and receive.Note that regardless of the number of
1206 * stop bits selected the receiver will only check the first stop bit.
1207 *
1208 * Field Enumeration Values:
1209 *
1210 * Enum | Value | Description
1211 * :----------------------------------|:------|:------------------------------------------
1212 * ALT_UART_LCR_STOP_E_ONESTOP | 0x0 | one stop bit
1213 * ALT_UART_LCR_STOP_E_ONEPOINT5STOP | 0x1 | 1.5 stop bits when DLS (LCR[1:0]) is zero
1214 *
1215 * Field Access Macros:
1216 *
1217 */
1218/*
1219 * Enumerated value for register field ALT_UART_LCR_STOP
1220 *
1221 * one stop bit
1222 */
1223#define ALT_UART_LCR_STOP_E_ONESTOP 0x0
1224/*
1225 * Enumerated value for register field ALT_UART_LCR_STOP
1226 *
1227 * 1.5 stop bits when DLS (LCR[1:0]) is zero
1228 */
1229#define ALT_UART_LCR_STOP_E_ONEPOINT5STOP 0x1
1230
1231/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_STOP register field. */
1232#define ALT_UART_LCR_STOP_LSB 2
1233/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_STOP register field. */
1234#define ALT_UART_LCR_STOP_MSB 2
1235/* The width in bits of the ALT_UART_LCR_STOP register field. */
1236#define ALT_UART_LCR_STOP_WIDTH 1
1237/* The mask used to set the ALT_UART_LCR_STOP register field value. */
1238#define ALT_UART_LCR_STOP_SET_MSK 0x00000004
1239/* The mask used to clear the ALT_UART_LCR_STOP register field value. */
1240#define ALT_UART_LCR_STOP_CLR_MSK 0xfffffffb
1241/* The reset value of the ALT_UART_LCR_STOP register field. */
1242#define ALT_UART_LCR_STOP_RESET 0x0
1243/* Extracts the ALT_UART_LCR_STOP field value from a register. */
1244#define ALT_UART_LCR_STOP_GET(value) (((value) & 0x00000004) >> 2)
1245/* Produces a ALT_UART_LCR_STOP register field value suitable for setting the register. */
1246#define ALT_UART_LCR_STOP_SET(value) (((value) << 2) & 0x00000004)
1247
1248/*
1249 * Field : Parity Enable - pen
1250 *
1251 * This bit is used to enable and disable parity generation and detection in a
1252 * transmitted and received data character.
1253 *
1254 * Field Enumeration Values:
1255 *
1256 * Enum | Value | Description
1257 * :------------------------|:------|:----------------
1258 * ALT_UART_LCR_PEN_E_DISD | 0x0 | parity disabled
1259 * ALT_UART_LCR_PEN_E_END | 0x1 | parity enabled
1260 *
1261 * Field Access Macros:
1262 *
1263 */
1264/*
1265 * Enumerated value for register field ALT_UART_LCR_PEN
1266 *
1267 * parity disabled
1268 */
1269#define ALT_UART_LCR_PEN_E_DISD 0x0
1270/*
1271 * Enumerated value for register field ALT_UART_LCR_PEN
1272 *
1273 * parity enabled
1274 */
1275#define ALT_UART_LCR_PEN_E_END 0x1
1276
1277/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_PEN register field. */
1278#define ALT_UART_LCR_PEN_LSB 3
1279/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_PEN register field. */
1280#define ALT_UART_LCR_PEN_MSB 3
1281/* The width in bits of the ALT_UART_LCR_PEN register field. */
1282#define ALT_UART_LCR_PEN_WIDTH 1
1283/* The mask used to set the ALT_UART_LCR_PEN register field value. */
1284#define ALT_UART_LCR_PEN_SET_MSK 0x00000008
1285/* The mask used to clear the ALT_UART_LCR_PEN register field value. */
1286#define ALT_UART_LCR_PEN_CLR_MSK 0xfffffff7
1287/* The reset value of the ALT_UART_LCR_PEN register field. */
1288#define ALT_UART_LCR_PEN_RESET 0x0
1289/* Extracts the ALT_UART_LCR_PEN field value from a register. */
1290#define ALT_UART_LCR_PEN_GET(value) (((value) & 0x00000008) >> 3)
1291/* Produces a ALT_UART_LCR_PEN register field value suitable for setting the register. */
1292#define ALT_UART_LCR_PEN_SET(value) (((value) << 3) & 0x00000008)
1293
1294/*
1295 * Field : Even Parity Select - eps
1296 *
1297 * This is used to select between even and odd parity, when parity is enabled (PEN
1298 * set to one). If set to one, an even number of logic '1's is transmitted or
1299 * checked. If set to zero, an odd number of logic '1's is transmitted or checked.
1300 *
1301 * Field Enumeration Values:
1302 *
1303 * Enum | Value | Description
1304 * :---------------------------|:------|:------------
1305 * ALT_UART_LCR_EPS_E_ODDPAR | 0x0 | odd parity
1306 * ALT_UART_LCR_EPS_E_EVENPAR | 0x1 | even parity
1307 *
1308 * Field Access Macros:
1309 *
1310 */
1311/*
1312 * Enumerated value for register field ALT_UART_LCR_EPS
1313 *
1314 * odd parity
1315 */
1316#define ALT_UART_LCR_EPS_E_ODDPAR 0x0
1317/*
1318 * Enumerated value for register field ALT_UART_LCR_EPS
1319 *
1320 * even parity
1321 */
1322#define ALT_UART_LCR_EPS_E_EVENPAR 0x1
1323
1324/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_EPS register field. */
1325#define ALT_UART_LCR_EPS_LSB 4
1326/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_EPS register field. */
1327#define ALT_UART_LCR_EPS_MSB 4
1328/* The width in bits of the ALT_UART_LCR_EPS register field. */
1329#define ALT_UART_LCR_EPS_WIDTH 1
1330/* The mask used to set the ALT_UART_LCR_EPS register field value. */
1331#define ALT_UART_LCR_EPS_SET_MSK 0x00000010
1332/* The mask used to clear the ALT_UART_LCR_EPS register field value. */
1333#define ALT_UART_LCR_EPS_CLR_MSK 0xffffffef
1334/* The reset value of the ALT_UART_LCR_EPS register field. */
1335#define ALT_UART_LCR_EPS_RESET 0x0
1336/* Extracts the ALT_UART_LCR_EPS field value from a register. */
1337#define ALT_UART_LCR_EPS_GET(value) (((value) & 0x00000010) >> 4)
1338/* Produces a ALT_UART_LCR_EPS register field value suitable for setting the register. */
1339#define ALT_UART_LCR_EPS_SET(value) (((value) << 4) & 0x00000010)
1340
1341/*
1342 * Field : Break Control Bit - break
1343 *
1344 * This is used to cause a break condition to be transmitted to the receiving
1345 * device. If set to one the serial output is forced to the spacing (logic 0)
1346 * state. When not in Loopback Mode, as determined by MCR[4], the sout line is
1347 * forced low until the Break bit is cleared. When in Loopback Mode, the break
1348 * condition is internally looped back to the receiver and the sir_out_n line is
1349 * forced low.
1350 *
1351 * Field Access Macros:
1352 *
1353 */
1354/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_BREAK register field. */
1355#define ALT_UART_LCR_BREAK_LSB 6
1356/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_BREAK register field. */
1357#define ALT_UART_LCR_BREAK_MSB 6
1358/* The width in bits of the ALT_UART_LCR_BREAK register field. */
1359#define ALT_UART_LCR_BREAK_WIDTH 1
1360/* The mask used to set the ALT_UART_LCR_BREAK register field value. */
1361#define ALT_UART_LCR_BREAK_SET_MSK 0x00000040
1362/* The mask used to clear the ALT_UART_LCR_BREAK register field value. */
1363#define ALT_UART_LCR_BREAK_CLR_MSK 0xffffffbf
1364/* The reset value of the ALT_UART_LCR_BREAK register field. */
1365#define ALT_UART_LCR_BREAK_RESET 0x0
1366/* Extracts the ALT_UART_LCR_BREAK field value from a register. */
1367#define ALT_UART_LCR_BREAK_GET(value) (((value) & 0x00000040) >> 6)
1368/* Produces a ALT_UART_LCR_BREAK register field value suitable for setting the register. */
1369#define ALT_UART_LCR_BREAK_SET(value) (((value) << 6) & 0x00000040)
1370
1371/*
1372 * Field : Divisor Latch Access Bit - dlab
1373 *
1374 * Used to enable reading and writing of the Divisor Latch register (DLL and DLH)
1375 * to set the baud rate of the UART. This bit must be cleared after initial baud
1376 * rate setup in order to access other registers.
1377 *
1378 * Field Access Macros:
1379 *
1380 */
1381/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLAB register field. */
1382#define ALT_UART_LCR_DLAB_LSB 7
1383/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLAB register field. */
1384#define ALT_UART_LCR_DLAB_MSB 7
1385/* The width in bits of the ALT_UART_LCR_DLAB register field. */
1386#define ALT_UART_LCR_DLAB_WIDTH 1
1387/* The mask used to set the ALT_UART_LCR_DLAB register field value. */
1388#define ALT_UART_LCR_DLAB_SET_MSK 0x00000080
1389/* The mask used to clear the ALT_UART_LCR_DLAB register field value. */
1390#define ALT_UART_LCR_DLAB_CLR_MSK 0xffffff7f
1391/* The reset value of the ALT_UART_LCR_DLAB register field. */
1392#define ALT_UART_LCR_DLAB_RESET 0x0
1393/* Extracts the ALT_UART_LCR_DLAB field value from a register. */
1394#define ALT_UART_LCR_DLAB_GET(value) (((value) & 0x00000080) >> 7)
1395/* Produces a ALT_UART_LCR_DLAB register field value suitable for setting the register. */
1396#define ALT_UART_LCR_DLAB_SET(value) (((value) << 7) & 0x00000080)
1397
1398#ifndef __ASSEMBLY__
1399/*
1400 * WARNING: The C register and register group struct declarations are provided for
1401 * convenience and illustrative purposes. They should, however, be used with
1402 * caution as the C language standard provides no guarantees about the alignment or
1403 * atomicity of device memory accesses. The recommended practice for writing
1404 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1405 * alt_write_word() functions.
1406 *
1407 * The struct declaration for register ALT_UART_LCR.
1408 */
1409 struct ALT_UART_LCR_s
1410{
1411 uint32_t dls : 2; /* Data Length Select */
1412 uint32_t stop : 1; /* Stop Bits */
1413 uint32_t pen : 1; /* Parity Enable */
1414 uint32_t eps : 1; /* Even Parity Select */
1415 uint32_t : 1; /* *UNDEFINED* */
1416 uint32_t break_ : 1; /* Break Control Bit */
1417 uint32_t dlab : 1; /* Divisor Latch Access Bit */
1418 uint32_t : 24; /* *UNDEFINED* */
1419};
1420
1421/* The typedef declaration for register ALT_UART_LCR. */
1422typedef volatile struct ALT_UART_LCR_s ALT_UART_LCR_t;
1423#endif /* __ASSEMBLY__ */
1424
1425/* The byte offset of the ALT_UART_LCR register from the beginning of the component. */
1426#define ALT_UART_LCR_OFST 0xc
1427/* The address of the ALT_UART_LCR register. */
1428#define ALT_UART_LCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LCR_OFST))
1429
1430/*
1431 * Register : Modem Control Register - mcr
1432 *
1433 * Reports various operations of the modem signals
1434 *
1435 * Register Layout
1436 *
1437 * Bits | Access | Reset | Description
1438 * :-------|:-------|:------|:-------------------------
1439 * [0] | RW | 0x0 | Data Terminal Ready
1440 * [1] | RW | 0x0 | Request to Send
1441 * [2] | RW | 0x0 | Out1
1442 * [3] | RW | 0x0 | out2
1443 * [4] | RW | 0x0 | LoopBack Bit
1444 * [5] | RW | 0x0 | Auto Flow Control Enable
1445 * [31:6] | ??? | 0x0 | *UNDEFINED*
1446 *
1447 */
1448/*
1449 * Field : Data Terminal Ready - dtr
1450 *
1451 * This is used to directly control the Data Terminal Ready output. The value
1452 * written to this location is inverted and driven out on uart_dtr_n, that is: The
1453 * Data Terminal Ready output is used to inform the modem or data set that the UART
1454 * is ready to establish communications.
1455 *
1456 * Note that Loopback mode bit [4] of MCR is set to one, the uart_dtr_n output is
1457 * held inactive high while the value of this location is internally looped back
1458 * to an input.
1459 *
1460 * Field Enumeration Values:
1461 *
1462 * Enum | Value | Description
1463 * :--------------------------|:------|:---------------------------------
1464 * ALT_UART_MCR_DTR_E_LOGIC1 | 0x0 | uart_dtr_n de-asserted (logic 1)
1465 * ALT_UART_MCR_DTR_E_LOGIC0 | 0x1 | uart_dtr_n asserted (logic 0)
1466 *
1467 * Field Access Macros:
1468 *
1469 */
1470/*
1471 * Enumerated value for register field ALT_UART_MCR_DTR
1472 *
1473 * uart_dtr_n de-asserted (logic 1)
1474 */
1475#define ALT_UART_MCR_DTR_E_LOGIC1 0x0
1476/*
1477 * Enumerated value for register field ALT_UART_MCR_DTR
1478 *
1479 * uart_dtr_n asserted (logic 0)
1480 */
1481#define ALT_UART_MCR_DTR_E_LOGIC0 0x1
1482
1483/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_DTR register field. */
1484#define ALT_UART_MCR_DTR_LSB 0
1485/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_DTR register field. */
1486#define ALT_UART_MCR_DTR_MSB 0
1487/* The width in bits of the ALT_UART_MCR_DTR register field. */
1488#define ALT_UART_MCR_DTR_WIDTH 1
1489/* The mask used to set the ALT_UART_MCR_DTR register field value. */
1490#define ALT_UART_MCR_DTR_SET_MSK 0x00000001
1491/* The mask used to clear the ALT_UART_MCR_DTR register field value. */
1492#define ALT_UART_MCR_DTR_CLR_MSK 0xfffffffe
1493/* The reset value of the ALT_UART_MCR_DTR register field. */
1494#define ALT_UART_MCR_DTR_RESET 0x0
1495/* Extracts the ALT_UART_MCR_DTR field value from a register. */
1496#define ALT_UART_MCR_DTR_GET(value) (((value) & 0x00000001) >> 0)
1497/* Produces a ALT_UART_MCR_DTR register field value suitable for setting the register. */
1498#define ALT_UART_MCR_DTR_SET(value) (((value) << 0) & 0x00000001)
1499
1500/*
1501 * Field : Request to Send - rts
1502 *
1503 * This is used to directly control the Request to Send (uart_rts_n) output. The
1504 * Request to Send (uart_rts_n) output is used to inform the modem or data set that
1505 * the UART is ready to exchange data. When Auto RTS Flow Control is not enabled
1506 * (MCR[5] set to zero), the uart_rts_n signal is set low by programming MCR[1]
1507 * (RTS) to a high. If Auto Flow Control is active (MCR[5] set to one) and FIFO's
1508 * enable (FCR[0] set to one), the uart_rts_n output is controlled in the same way,
1509 * but is also gated with the receiver FIFO threshold trigger (uart_rts_n is
1510 * inactive high when above the threshold). The uart_rts_n signal will be de-
1511 * asserted when MCR[1] is set low.
1512 *
1513 * Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held
1514 * inactive high while the value of this location is internally looped back to an
1515 * input.
1516 *
1517 * Field Enumeration Values:
1518 *
1519 * Enum | Value | Description
1520 * :--------------------------|:------|:---------------------------------
1521 * ALT_UART_MCR_RTS_E_LOGIC1 | 0x0 | uart_rts_n de-asserted (logic 1)
1522 * ALT_UART_MCR_RTS_E_LOGIC0 | 0x1 | uart_rts_n asserted (logic 0)
1523 *
1524 * Field Access Macros:
1525 *
1526 */
1527/*
1528 * Enumerated value for register field ALT_UART_MCR_RTS
1529 *
1530 * uart_rts_n de-asserted (logic 1)
1531 */
1532#define ALT_UART_MCR_RTS_E_LOGIC1 0x0
1533/*
1534 * Enumerated value for register field ALT_UART_MCR_RTS
1535 *
1536 * uart_rts_n asserted (logic 0)
1537 */
1538#define ALT_UART_MCR_RTS_E_LOGIC0 0x1
1539
1540/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_RTS register field. */
1541#define ALT_UART_MCR_RTS_LSB 1
1542/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_RTS register field. */
1543#define ALT_UART_MCR_RTS_MSB 1
1544/* The width in bits of the ALT_UART_MCR_RTS register field. */
1545#define ALT_UART_MCR_RTS_WIDTH 1
1546/* The mask used to set the ALT_UART_MCR_RTS register field value. */
1547#define ALT_UART_MCR_RTS_SET_MSK 0x00000002
1548/* The mask used to clear the ALT_UART_MCR_RTS register field value. */
1549#define ALT_UART_MCR_RTS_CLR_MSK 0xfffffffd
1550/* The reset value of the ALT_UART_MCR_RTS register field. */
1551#define ALT_UART_MCR_RTS_RESET 0x0
1552/* Extracts the ALT_UART_MCR_RTS field value from a register. */
1553#define ALT_UART_MCR_RTS_GET(value) (((value) & 0x00000002) >> 1)
1554/* Produces a ALT_UART_MCR_RTS register field value suitable for setting the register. */
1555#define ALT_UART_MCR_RTS_SET(value) (((value) << 1) & 0x00000002)
1556
1557/*
1558 * Field : Out1 - out1
1559 *
1560 * The value written to this location is inverted and driven out on uart_out1_n
1561 * pin.
1562 *
1563 * Note that in Loopback mode (MCR[4] set to one), the uart_out1_n output is held
1564 * inactive high while the value of this location is internally looped back to an
1565 * input.
1566 *
1567 * Field Enumeration Values:
1568 *
1569 * Enum | Value | Description
1570 * :---------------------------|:------|:----------------------------------
1571 * ALT_UART_MCR_OUT1_E_LOGIC1 | 0x0 | uart_out1_n de-asserted (logic 1)
1572 * ALT_UART_MCR_OUT1_E_LOGIC0 | 0x1 | uart_out1_n asserted (logic 0)
1573 *
1574 * Field Access Macros:
1575 *
1576 */
1577/*
1578 * Enumerated value for register field ALT_UART_MCR_OUT1
1579 *
1580 * uart_out1_n de-asserted (logic 1)
1581 */
1582#define ALT_UART_MCR_OUT1_E_LOGIC1 0x0
1583/*
1584 * Enumerated value for register field ALT_UART_MCR_OUT1
1585 *
1586 * uart_out1_n asserted (logic 0)
1587 */
1588#define ALT_UART_MCR_OUT1_E_LOGIC0 0x1
1589
1590/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT1 register field. */
1591#define ALT_UART_MCR_OUT1_LSB 2
1592/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT1 register field. */
1593#define ALT_UART_MCR_OUT1_MSB 2
1594/* The width in bits of the ALT_UART_MCR_OUT1 register field. */
1595#define ALT_UART_MCR_OUT1_WIDTH 1
1596/* The mask used to set the ALT_UART_MCR_OUT1 register field value. */
1597#define ALT_UART_MCR_OUT1_SET_MSK 0x00000004
1598/* The mask used to clear the ALT_UART_MCR_OUT1 register field value. */
1599#define ALT_UART_MCR_OUT1_CLR_MSK 0xfffffffb
1600/* The reset value of the ALT_UART_MCR_OUT1 register field. */
1601#define ALT_UART_MCR_OUT1_RESET 0x0
1602/* Extracts the ALT_UART_MCR_OUT1 field value from a register. */
1603#define ALT_UART_MCR_OUT1_GET(value) (((value) & 0x00000004) >> 2)
1604/* Produces a ALT_UART_MCR_OUT1 register field value suitable for setting the register. */
1605#define ALT_UART_MCR_OUT1_SET(value) (((value) << 2) & 0x00000004)
1606
1607/*
1608 * Field : out2 - out2
1609 *
1610 * This is used to directly control the user-designated uart_out2_n output. The
1611 * value written to this location is inverted and driven out on uart_out2_n
1612 *
1613 * Note: In Loopback mode bit 4 of the modem control register (MCR) is set to one,
1614 * the uart_out2_n output is held inactive high while the value of this location is
1615 * internally looped back to an input.
1616 *
1617 * Field Enumeration Values:
1618 *
1619 * Enum | Value | Description
1620 * :---------------------------|:------|:----------------------------------
1621 * ALT_UART_MCR_OUT2_E_LOGIC1 | 0x0 | uart_out2_n de-asserted (logic 1)
1622 * ALT_UART_MCR_OUT2_E_LOGIC0 | 0x1 | uart_out2_n asserted (logic 0)
1623 *
1624 * Field Access Macros:
1625 *
1626 */
1627/*
1628 * Enumerated value for register field ALT_UART_MCR_OUT2
1629 *
1630 * uart_out2_n de-asserted (logic 1)
1631 */
1632#define ALT_UART_MCR_OUT2_E_LOGIC1 0x0
1633/*
1634 * Enumerated value for register field ALT_UART_MCR_OUT2
1635 *
1636 * uart_out2_n asserted (logic 0)
1637 */
1638#define ALT_UART_MCR_OUT2_E_LOGIC0 0x1
1639
1640/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT2 register field. */
1641#define ALT_UART_MCR_OUT2_LSB 3
1642/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT2 register field. */
1643#define ALT_UART_MCR_OUT2_MSB 3
1644/* The width in bits of the ALT_UART_MCR_OUT2 register field. */
1645#define ALT_UART_MCR_OUT2_WIDTH 1
1646/* The mask used to set the ALT_UART_MCR_OUT2 register field value. */
1647#define ALT_UART_MCR_OUT2_SET_MSK 0x00000008
1648/* The mask used to clear the ALT_UART_MCR_OUT2 register field value. */
1649#define ALT_UART_MCR_OUT2_CLR_MSK 0xfffffff7
1650/* The reset value of the ALT_UART_MCR_OUT2 register field. */
1651#define ALT_UART_MCR_OUT2_RESET 0x0
1652/* Extracts the ALT_UART_MCR_OUT2 field value from a register. */
1653#define ALT_UART_MCR_OUT2_GET(value) (((value) & 0x00000008) >> 3)
1654/* Produces a ALT_UART_MCR_OUT2 register field value suitable for setting the register. */
1655#define ALT_UART_MCR_OUT2_SET(value) (((value) << 3) & 0x00000008)
1656
1657/*
1658 * Field : LoopBack Bit - loopback
1659 *
1660 * This is used to put the UART into a diagnostic mode for test purposes. If UART
1661 * mode is NOT active, bit [6] of the modem control register MCR is set to zero,
1662 * data on the sout line is held high, while serial data output is looped back to
1663 * the sin line, internally. In this mode all the interrupts are fully functional.
1664 * Also, in loopback mode, the modem control inputs (uart_dsr_n, uart_cts_n,
1665 * uart_ri_n, uart_dcd_n) are disconnected and the modem control outputs
1666 * (uart_dtr_n, uart_rts_n, uart_out1_n, uart_out2_n) are loopedback to the inputs,
1667 * internally.
1668 *
1669 * Field Access Macros:
1670 *
1671 */
1672/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_LOOPBACK register field. */
1673#define ALT_UART_MCR_LOOPBACK_LSB 4
1674/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_LOOPBACK register field. */
1675#define ALT_UART_MCR_LOOPBACK_MSB 4
1676/* The width in bits of the ALT_UART_MCR_LOOPBACK register field. */
1677#define ALT_UART_MCR_LOOPBACK_WIDTH 1
1678/* The mask used to set the ALT_UART_MCR_LOOPBACK register field value. */
1679#define ALT_UART_MCR_LOOPBACK_SET_MSK 0x00000010
1680/* The mask used to clear the ALT_UART_MCR_LOOPBACK register field value. */
1681#define ALT_UART_MCR_LOOPBACK_CLR_MSK 0xffffffef
1682/* The reset value of the ALT_UART_MCR_LOOPBACK register field. */
1683#define ALT_UART_MCR_LOOPBACK_RESET 0x0
1684/* Extracts the ALT_UART_MCR_LOOPBACK field value from a register. */
1685#define ALT_UART_MCR_LOOPBACK_GET(value) (((value) & 0x00000010) >> 4)
1686/* Produces a ALT_UART_MCR_LOOPBACK register field value suitable for setting the register. */
1687#define ALT_UART_MCR_LOOPBACK_SET(value) (((value) << 4) & 0x00000010)
1688
1689/*
1690 * Field : Auto Flow Control Enable - afce
1691 *
1692 * When FIFOs are enabled, the Auto Flow Control enable bits are active.
1693 *
1694 * Field Enumeration Values:
1695 *
1696 * Enum | Value | Description
1697 * :-------------------------|:------|:--------------------------------
1698 * ALT_UART_MCR_AFCE_E_DISD | 0x0 | Auto Flow Control Mode disabled
1699 * ALT_UART_MCR_AFCE_E_END | 0x1 | Auto Flow Control Mode enabled
1700 *
1701 * Field Access Macros:
1702 *
1703 */
1704/*
1705 * Enumerated value for register field ALT_UART_MCR_AFCE
1706 *
1707 * Auto Flow Control Mode disabled
1708 */
1709#define ALT_UART_MCR_AFCE_E_DISD 0x0
1710/*
1711 * Enumerated value for register field ALT_UART_MCR_AFCE
1712 *
1713 * Auto Flow Control Mode enabled
1714 */
1715#define ALT_UART_MCR_AFCE_E_END 0x1
1716
1717/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_AFCE register field. */
1718#define ALT_UART_MCR_AFCE_LSB 5
1719/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_AFCE register field. */
1720#define ALT_UART_MCR_AFCE_MSB 5
1721/* The width in bits of the ALT_UART_MCR_AFCE register field. */
1722#define ALT_UART_MCR_AFCE_WIDTH 1
1723/* The mask used to set the ALT_UART_MCR_AFCE register field value. */
1724#define ALT_UART_MCR_AFCE_SET_MSK 0x00000020
1725/* The mask used to clear the ALT_UART_MCR_AFCE register field value. */
1726#define ALT_UART_MCR_AFCE_CLR_MSK 0xffffffdf
1727/* The reset value of the ALT_UART_MCR_AFCE register field. */
1728#define ALT_UART_MCR_AFCE_RESET 0x0
1729/* Extracts the ALT_UART_MCR_AFCE field value from a register. */
1730#define ALT_UART_MCR_AFCE_GET(value) (((value) & 0x00000020) >> 5)
1731/* Produces a ALT_UART_MCR_AFCE register field value suitable for setting the register. */
1732#define ALT_UART_MCR_AFCE_SET(value) (((value) << 5) & 0x00000020)
1733
1734#ifndef __ASSEMBLY__
1735/*
1736 * WARNING: The C register and register group struct declarations are provided for
1737 * convenience and illustrative purposes. They should, however, be used with
1738 * caution as the C language standard provides no guarantees about the alignment or
1739 * atomicity of device memory accesses. The recommended practice for writing
1740 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1741 * alt_write_word() functions.
1742 *
1743 * The struct declaration for register ALT_UART_MCR.
1744 */
1745 struct ALT_UART_MCR_s
1746{
1747 uint32_t dtr : 1; /* Data Terminal Ready */
1748 uint32_t rts : 1; /* Request to Send */
1749 uint32_t out1 : 1; /* Out1 */
1750 uint32_t out2 : 1; /* out2 */
1751 uint32_t loopback : 1; /* LoopBack Bit */
1752 uint32_t afce : 1; /* Auto Flow Control Enable */
1753 uint32_t : 26; /* *UNDEFINED* */
1754};
1755
1756/* The typedef declaration for register ALT_UART_MCR. */
1757typedef volatile struct ALT_UART_MCR_s ALT_UART_MCR_t;
1758#endif /* __ASSEMBLY__ */
1759
1760/* The byte offset of the ALT_UART_MCR register from the beginning of the component. */
1761#define ALT_UART_MCR_OFST 0x10
1762/* The address of the ALT_UART_MCR register. */
1763#define ALT_UART_MCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MCR_OFST))
1764
1765/*
1766 * Register : Line Status Register - lsr
1767 *
1768 * Reports status of transmit and receive.
1769 *
1770 * Register Layout
1771 *
1772 * Bits | Access | Reset | Description
1773 * :-------|:-------|:------|:------------------------------------
1774 * [0] | R | 0x0 | Data Ready bit
1775 * [1] | R | 0x0 | Overrun error
1776 * [2] | R | 0x0 | Parity Error
1777 * [3] | R | 0x0 | Framing Error
1778 * [4] | R | 0x0 | Break Interrupt
1779 * [5] | R | 0x1 | Transmit Holding Register Empty bit
1780 * [6] | R | 0x1 | Transmitter Empty bit
1781 * [7] | R | 0x0 | Receiver FIFO Error bit
1782 * [31:8] | ??? | 0x0 | *UNDEFINED*
1783 *
1784 */
1785/*
1786 * Field : Data Ready bit - dr
1787 *
1788 * This is used to indicate that the receiver contains at least one character in
1789 * the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the
1790 * non-FIFO mode, or when the receiver FIFO is empty, in the FIFO mode.
1791 *
1792 * Field Enumeration Values:
1793 *
1794 * Enum | Value | Description
1795 * :----------------------------|:------|:--------------
1796 * ALT_UART_LSR_DR_E_NODATARDY | 0x0 | no data ready
1797 * ALT_UART_LSR_DR_E_DATARDY | 0x1 | data ready
1798 *
1799 * Field Access Macros:
1800 *
1801 */
1802/*
1803 * Enumerated value for register field ALT_UART_LSR_DR
1804 *
1805 * no data ready
1806 */
1807#define ALT_UART_LSR_DR_E_NODATARDY 0x0
1808/*
1809 * Enumerated value for register field ALT_UART_LSR_DR
1810 *
1811 * data ready
1812 */
1813#define ALT_UART_LSR_DR_E_DATARDY 0x1
1814
1815/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_DR register field. */
1816#define ALT_UART_LSR_DR_LSB 0
1817/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_DR register field. */
1818#define ALT_UART_LSR_DR_MSB 0
1819/* The width in bits of the ALT_UART_LSR_DR register field. */
1820#define ALT_UART_LSR_DR_WIDTH 1
1821/* The mask used to set the ALT_UART_LSR_DR register field value. */
1822#define ALT_UART_LSR_DR_SET_MSK 0x00000001
1823/* The mask used to clear the ALT_UART_LSR_DR register field value. */
1824#define ALT_UART_LSR_DR_CLR_MSK 0xfffffffe
1825/* The reset value of the ALT_UART_LSR_DR register field. */
1826#define ALT_UART_LSR_DR_RESET 0x0
1827/* Extracts the ALT_UART_LSR_DR field value from a register. */
1828#define ALT_UART_LSR_DR_GET(value) (((value) & 0x00000001) >> 0)
1829/* Produces a ALT_UART_LSR_DR register field value suitable for setting the register. */
1830#define ALT_UART_LSR_DR_SET(value) (((value) << 0) & 0x00000001)
1831
1832/*
1833 * Field : Overrun error - oe
1834 *
1835 * This is used to indicate the occurrence of an overrun error. This occurs if a
1836 * new data character was received before the previous data was read. In the non-
1837 * FIFO mode, the OE bit is set when a new character arrives in the receiver before
1838 * the previous character was read from the RBR. When this happens, the data in the
1839 * RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is
1840 * full and new character arrives at the receiver. The data in the FIFO is retained
1841 * and the data in the receive shift register is lost.Reading the LSR clears the OE
1842 * bit.
1843 *
1844 * Field Enumeration Values:
1845 *
1846 * Enum | Value | Description
1847 * :----------------------------|:------|:-----------------
1848 * ALT_UART_LSR_OE_E_NOOVERRUN | 0x0 | no overrun error
1849 * ALT_UART_LSR_OE_E_OVERRUN | 0x1 | overrun error
1850 *
1851 * Field Access Macros:
1852 *
1853 */
1854/*
1855 * Enumerated value for register field ALT_UART_LSR_OE
1856 *
1857 * no overrun error
1858 */
1859#define ALT_UART_LSR_OE_E_NOOVERRUN 0x0
1860/*
1861 * Enumerated value for register field ALT_UART_LSR_OE
1862 *
1863 * overrun error
1864 */
1865#define ALT_UART_LSR_OE_E_OVERRUN 0x1
1866
1867/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_OE register field. */
1868#define ALT_UART_LSR_OE_LSB 1
1869/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_OE register field. */
1870#define ALT_UART_LSR_OE_MSB 1
1871/* The width in bits of the ALT_UART_LSR_OE register field. */
1872#define ALT_UART_LSR_OE_WIDTH 1
1873/* The mask used to set the ALT_UART_LSR_OE register field value. */
1874#define ALT_UART_LSR_OE_SET_MSK 0x00000002
1875/* The mask used to clear the ALT_UART_LSR_OE register field value. */
1876#define ALT_UART_LSR_OE_CLR_MSK 0xfffffffd
1877/* The reset value of the ALT_UART_LSR_OE register field. */
1878#define ALT_UART_LSR_OE_RESET 0x0
1879/* Extracts the ALT_UART_LSR_OE field value from a register. */
1880#define ALT_UART_LSR_OE_GET(value) (((value) & 0x00000002) >> 1)
1881/* Produces a ALT_UART_LSR_OE register field value suitable for setting the register. */
1882#define ALT_UART_LSR_OE_SET(value) (((value) << 1) & 0x00000002)
1883
1884/*
1885 * Field : Parity Error - pe
1886 *
1887 * This is used to indicate the occurrence of a parity error in the receiver if the
1888 * Parity Enable (PEN) bit (LCR[3]) is set. Since the parity error is associated
1889 * with a character received, it is revealed when the character with the parity
1890 * error arrives at the top of the FIFO. It should be noted that the Parity Error
1891 * (PE) bit (LSR[2]) will be set if a break interrupt has occurred, as indicated by
1892 * Break Interrupt (BI) bit (LSR[4]). Reading the LSR clears the PE bit.
1893 *
1894 * Field Enumeration Values:
1895 *
1896 * Enum | Value | Description
1897 * :------------------------------|:------|:----------------
1898 * ALT_UART_LSR_PE_E_NOPARITYERR | 0x0 | no parity error
1899 * ALT_UART_LSR_PE_E_PARITYERR | 0x1 | no parity error
1900 *
1901 * Field Access Macros:
1902 *
1903 */
1904/*
1905 * Enumerated value for register field ALT_UART_LSR_PE
1906 *
1907 * no parity error
1908 */
1909#define ALT_UART_LSR_PE_E_NOPARITYERR 0x0
1910/*
1911 * Enumerated value for register field ALT_UART_LSR_PE
1912 *
1913 * no parity error
1914 */
1915#define ALT_UART_LSR_PE_E_PARITYERR 0x1
1916
1917/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_PE register field. */
1918#define ALT_UART_LSR_PE_LSB 2
1919/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_PE register field. */
1920#define ALT_UART_LSR_PE_MSB 2
1921/* The width in bits of the ALT_UART_LSR_PE register field. */
1922#define ALT_UART_LSR_PE_WIDTH 1
1923/* The mask used to set the ALT_UART_LSR_PE register field value. */
1924#define ALT_UART_LSR_PE_SET_MSK 0x00000004
1925/* The mask used to clear the ALT_UART_LSR_PE register field value. */
1926#define ALT_UART_LSR_PE_CLR_MSK 0xfffffffb
1927/* The reset value of the ALT_UART_LSR_PE register field. */
1928#define ALT_UART_LSR_PE_RESET 0x0
1929/* Extracts the ALT_UART_LSR_PE field value from a register. */
1930#define ALT_UART_LSR_PE_GET(value) (((value) & 0x00000004) >> 2)
1931/* Produces a ALT_UART_LSR_PE register field value suitable for setting the register. */
1932#define ALT_UART_LSR_PE_SET(value) (((value) << 2) & 0x00000004)
1933
1934/*
1935 * Field : Framing Error - fe
1936 *
1937 * This is used to indicate the occurrence of a framing error in the receiver. A
1938 * framing error occurs when the receiver does not detect a valid STOP bit in the
1939 * received data. In the FIFO mode, since the framing error is associated with a
1940 * character received, it is revealed when the character with the framing error is
1941 * at the top of the FIFO. When a framing error occurs the UART will try to
1942 * resynchronize. It does this by assuming that the error was due to the start bit
1943 * of the next character and then continues receiving the other bit i.e. data,
1944 * and/or parity and stop. It should be noted that the Framing Error (FE)
1945 * bit(LSR[3]) will be set if a break interrupt has occurred, as indicated by a
1946 * Break Interrupt BIT bit (LSR[4]). Reading the LSR clears the FE bit.
1947 *
1948 * Field Enumeration Values:
1949 *
1950 * Enum | Value | Description
1951 * :---------------------------|:------|:-----------------
1952 * ALT_UART_LSR_FE_E_NOFRMERR | 0x0 | no framing error
1953 * ALT_UART_LSR_FE_E_FRMERR | 0x1 | framing error
1954 *
1955 * Field Access Macros:
1956 *
1957 */
1958/*
1959 * Enumerated value for register field ALT_UART_LSR_FE
1960 *
1961 * no framing error
1962 */
1963#define ALT_UART_LSR_FE_E_NOFRMERR 0x0
1964/*
1965 * Enumerated value for register field ALT_UART_LSR_FE
1966 *
1967 * framing error
1968 */
1969#define ALT_UART_LSR_FE_E_FRMERR 0x1
1970
1971/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_FE register field. */
1972#define ALT_UART_LSR_FE_LSB 3
1973/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_FE register field. */
1974#define ALT_UART_LSR_FE_MSB 3
1975/* The width in bits of the ALT_UART_LSR_FE register field. */
1976#define ALT_UART_LSR_FE_WIDTH 1
1977/* The mask used to set the ALT_UART_LSR_FE register field value. */
1978#define ALT_UART_LSR_FE_SET_MSK 0x00000008
1979/* The mask used to clear the ALT_UART_LSR_FE register field value. */
1980#define ALT_UART_LSR_FE_CLR_MSK 0xfffffff7
1981/* The reset value of the ALT_UART_LSR_FE register field. */
1982#define ALT_UART_LSR_FE_RESET 0x0
1983/* Extracts the ALT_UART_LSR_FE field value from a register. */
1984#define ALT_UART_LSR_FE_GET(value) (((value) & 0x00000008) >> 3)
1985/* Produces a ALT_UART_LSR_FE register field value suitable for setting the register. */
1986#define ALT_UART_LSR_FE_SET(value) (((value) << 3) & 0x00000008)
1987
1988/*
1989 * Field : Break Interrupt - bi
1990 *
1991 * This is used to indicate the detection of a break sequence on the serial input
1992 * data. Set whenever the serial input, sin, is held in a logic 0 state for longer
1993 * than the sum of start time + data bits + parity + stop bits. A break condition
1994 * on serial input causes one and only one character, consisting of all zeros, to
1995 * be received by the UART. The character associated with the break condition is
1996 * carried through the FIFO and is revealed when the character is at the top of the
1997 * FIFO. Reading the LSR clears the BI bit.
1998 *
1999 * Field Access Macros:
2000 *
2001 */
2002/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_BI register field. */
2003#define ALT_UART_LSR_BI_LSB 4
2004/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_BI register field. */
2005#define ALT_UART_LSR_BI_MSB 4
2006/* The width in bits of the ALT_UART_LSR_BI register field. */
2007#define ALT_UART_LSR_BI_WIDTH 1
2008/* The mask used to set the ALT_UART_LSR_BI register field value. */
2009#define ALT_UART_LSR_BI_SET_MSK 0x00000010
2010/* The mask used to clear the ALT_UART_LSR_BI register field value. */
2011#define ALT_UART_LSR_BI_CLR_MSK 0xffffffef
2012/* The reset value of the ALT_UART_LSR_BI register field. */
2013#define ALT_UART_LSR_BI_RESET 0x0
2014/* Extracts the ALT_UART_LSR_BI field value from a register. */
2015#define ALT_UART_LSR_BI_GET(value) (((value) & 0x00000010) >> 4)
2016/* Produces a ALT_UART_LSR_BI register field value suitable for setting the register. */
2017#define ALT_UART_LSR_BI_SET(value) (((value) << 4) & 0x00000010)
2018
2019/*
2020 * Field : Transmit Holding Register Empty bit - thre
2021 *
2022 * If THRE mode is disabled (IER[7] set to zero) this bit indicates that the THR or
2023 * Tx FIFO is empty. This bit is set whenever data is transferred from the THR or
2024 * Tx FIFO to the transmitter shift register and no new data has been written to
2025 * the THR or Tx FIFO. This also causes a THRE Interrupt to occur, if the THRE
2026 * Interrupt is enabled. If both THRE and FIFOs are enabled, both (IER[7] set to
2027 * one and FCR[0] set to one respectively), the functionality will indicate the
2028 * transmitter FIFO is full, and no longer controls THRE interrupts, which are then
2029 * controlled by the FCR[5:4] thresholdsetting.
2030 *
2031 * Field Access Macros:
2032 *
2033 */
2034/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_THRE register field. */
2035#define ALT_UART_LSR_THRE_LSB 5
2036/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_THRE register field. */
2037#define ALT_UART_LSR_THRE_MSB 5
2038/* The width in bits of the ALT_UART_LSR_THRE register field. */
2039#define ALT_UART_LSR_THRE_WIDTH 1
2040/* The mask used to set the ALT_UART_LSR_THRE register field value. */
2041#define ALT_UART_LSR_THRE_SET_MSK 0x00000020
2042/* The mask used to clear the ALT_UART_LSR_THRE register field value. */
2043#define ALT_UART_LSR_THRE_CLR_MSK 0xffffffdf
2044/* The reset value of the ALT_UART_LSR_THRE register field. */
2045#define ALT_UART_LSR_THRE_RESET 0x1
2046/* Extracts the ALT_UART_LSR_THRE field value from a register. */
2047#define ALT_UART_LSR_THRE_GET(value) (((value) & 0x00000020) >> 5)
2048/* Produces a ALT_UART_LSR_THRE register field value suitable for setting the register. */
2049#define ALT_UART_LSR_THRE_SET(value) (((value) << 5) & 0x00000020)
2050
2051/*
2052 * Field : Transmitter Empty bit - temt
2053 *
2054 * If in FIFO mode and FIFO's enabled (FCR[0] set to one), this bit is set whenever
2055 * the Transmitter Shift Register and the FIFO are both empty. If FIFO's are
2056 * disabled, this bit is set whenever the Transmitter Holding Register and the
2057 * Transmitter Shift Register are both empty.
2058 *
2059 * Field Enumeration Values:
2060 *
2061 * Enum | Value | Description
2062 * :-----------------------------|:------|:-----------------------
2063 * ALT_UART_LSR_TEMT_E_NOTEMPTY | 0x0 | Transmit Empty not set
2064 * ALT_UART_LSR_TEMT_E_EMPTY | 0x1 | Transmit Empty set
2065 *
2066 * Field Access Macros:
2067 *
2068 */
2069/*
2070 * Enumerated value for register field ALT_UART_LSR_TEMT
2071 *
2072 * Transmit Empty not set
2073 */
2074#define ALT_UART_LSR_TEMT_E_NOTEMPTY 0x0
2075/*
2076 * Enumerated value for register field ALT_UART_LSR_TEMT
2077 *
2078 * Transmit Empty set
2079 */
2080#define ALT_UART_LSR_TEMT_E_EMPTY 0x1
2081
2082/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_TEMT register field. */
2083#define ALT_UART_LSR_TEMT_LSB 6
2084/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_TEMT register field. */
2085#define ALT_UART_LSR_TEMT_MSB 6
2086/* The width in bits of the ALT_UART_LSR_TEMT register field. */
2087#define ALT_UART_LSR_TEMT_WIDTH 1
2088/* The mask used to set the ALT_UART_LSR_TEMT register field value. */
2089#define ALT_UART_LSR_TEMT_SET_MSK 0x00000040
2090/* The mask used to clear the ALT_UART_LSR_TEMT register field value. */
2091#define ALT_UART_LSR_TEMT_CLR_MSK 0xffffffbf
2092/* The reset value of the ALT_UART_LSR_TEMT register field. */
2093#define ALT_UART_LSR_TEMT_RESET 0x1
2094/* Extracts the ALT_UART_LSR_TEMT field value from a register. */
2095#define ALT_UART_LSR_TEMT_GET(value) (((value) & 0x00000040) >> 6)
2096/* Produces a ALT_UART_LSR_TEMT register field value suitable for setting the register. */
2097#define ALT_UART_LSR_TEMT_SET(value) (((value) << 6) & 0x00000040)
2098
2099/*
2100 * Field : Receiver FIFO Error bit - rfe
2101 *
2102 * This bit is only relevant when FIFO's are enabled (FCR[0] set to one). This is
2103 * used to indicate if there is at least one parity error, framing error, or break
2104 * indication in the FIFO. This bit is cleared when the LSR is read and the
2105 * character with the error is at the top of the receiver FIFO and there are no
2106 * subsequent errors in the FIFO.
2107 *
2108 * Field Enumeration Values:
2109 *
2110 * Enum | Value | Description
2111 * :-------------------------|:------|:--------------------
2112 * ALT_UART_LSR_RFE_E_NOERR | 0x0 | no error in Rx FIFO
2113 * ALT_UART_LSR_RFE_E_ERR | 0x1 | error in Rx FIFO
2114 *
2115 * Field Access Macros:
2116 *
2117 */
2118/*
2119 * Enumerated value for register field ALT_UART_LSR_RFE
2120 *
2121 * no error in Rx FIFO
2122 */
2123#define ALT_UART_LSR_RFE_E_NOERR 0x0
2124/*
2125 * Enumerated value for register field ALT_UART_LSR_RFE
2126 *
2127 * error in Rx FIFO
2128 */
2129#define ALT_UART_LSR_RFE_E_ERR 0x1
2130
2131/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_RFE register field. */
2132#define ALT_UART_LSR_RFE_LSB 7
2133/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_RFE register field. */
2134#define ALT_UART_LSR_RFE_MSB 7
2135/* The width in bits of the ALT_UART_LSR_RFE register field. */
2136#define ALT_UART_LSR_RFE_WIDTH 1
2137/* The mask used to set the ALT_UART_LSR_RFE register field value. */
2138#define ALT_UART_LSR_RFE_SET_MSK 0x00000080
2139/* The mask used to clear the ALT_UART_LSR_RFE register field value. */
2140#define ALT_UART_LSR_RFE_CLR_MSK 0xffffff7f
2141/* The reset value of the ALT_UART_LSR_RFE register field. */
2142#define ALT_UART_LSR_RFE_RESET 0x0
2143/* Extracts the ALT_UART_LSR_RFE field value from a register. */
2144#define ALT_UART_LSR_RFE_GET(value) (((value) & 0x00000080) >> 7)
2145/* Produces a ALT_UART_LSR_RFE register field value suitable for setting the register. */
2146#define ALT_UART_LSR_RFE_SET(value) (((value) << 7) & 0x00000080)
2147
2148#ifndef __ASSEMBLY__
2149/*
2150 * WARNING: The C register and register group struct declarations are provided for
2151 * convenience and illustrative purposes. They should, however, be used with
2152 * caution as the C language standard provides no guarantees about the alignment or
2153 * atomicity of device memory accesses. The recommended practice for writing
2154 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2155 * alt_write_word() functions.
2156 *
2157 * The struct declaration for register ALT_UART_LSR.
2158 */
2159 struct ALT_UART_LSR_s
2160{
2161 const uint32_t dr : 1; /* Data Ready bit */
2162 const uint32_t oe : 1; /* Overrun error */
2163 const uint32_t pe : 1; /* Parity Error */
2164 const uint32_t fe : 1; /* Framing Error */
2165 const uint32_t bi : 1; /* Break Interrupt */
2166 const uint32_t thre : 1; /* Transmit Holding Register Empty bit */
2167 const uint32_t temt : 1; /* Transmitter Empty bit */
2168 const uint32_t rfe : 1; /* Receiver FIFO Error bit */
2169 uint32_t : 24; /* *UNDEFINED* */
2170};
2171
2172/* The typedef declaration for register ALT_UART_LSR. */
2173typedef volatile struct ALT_UART_LSR_s ALT_UART_LSR_t;
2174#endif /* __ASSEMBLY__ */
2175
2176/* The byte offset of the ALT_UART_LSR register from the beginning of the component. */
2177#define ALT_UART_LSR_OFST 0x14
2178/* The address of the ALT_UART_LSR register. */
2179#define ALT_UART_LSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LSR_OFST))
2180
2181/*
2182 * Register : Modem Status Register - msr
2183 *
2184 * It should be noted that whenever bits 0, 1, 2 or 3 are set to logic one, to
2185 * indicate a change on the modem control inputs, a modem status interrupt will be
2186 * generated if enabled via the IER regardless of when the change occurred. Since
2187 * the delta bits (bits 0, 1, 3) can get set after a reset if their respective
2188 * modem signals are active (see individual bits for details), a read of the MSR
2189 * after reset can be performed to prevent unwanted interrupts.
2190 *
2191 * Register Layout
2192 *
2193 * Bits | Access | Reset | Description
2194 * :-------|:-------|:------|:--------------------------------
2195 * [0] | R | 0x0 | Delta Clear to Send
2196 * [1] | R | 0x0 | Delta Data Set Ready
2197 * [2] | R | 0x0 | Trailing Edge of Ring Indicator
2198 * [3] | R | 0x0 | Delta Data Carrier Detect
2199 * [4] | R | 0x0 | Clear to Send
2200 * [5] | R | 0x0 | Data Set Ready
2201 * [6] | R | 0x0 | Ring Indicator
2202 * [7] | R | 0x0 | Data Carrier Detect
2203 * [31:8] | ??? | 0x0 | *UNDEFINED*
2204 *
2205 */
2206/*
2207 * Field : Delta Clear to Send - dcts
2208 *
2209 * This is used to indicate that the modem control line uart_cts_n has changed
2210 * since the last time the MSR was read. That is: Reading the MSR clears the DCTS
2211 * bit. In Loopback Mode bit [4] of MCR set to one, DCTS reflects changes on bit
2212 * [1] RTS of register MCR.
2213 *
2214 * Note: If the DCTS bit is not set and the uart_cts_n signal is asserted (low) and
2215 * a reset occurs (software or otherwise), then the DCTS bit will get set when the
2216 * reset is removed if the uart_cts_n signal remains asserted.
2217 *
2218 * Field Enumeration Values:
2219 *
2220 * Enum | Value | Description
2221 * :--------------------------|:------|:-----------------------------------------------
2222 * ALT_UART_MSR_DCTS_E_NOCHG | 0x0 | no change on uart_cts_n since last read of MSR
2223 * ALT_UART_MSR_DCTS_E_CHG | 0x1 | change on uart_cts_n since last read of MSR
2224 *
2225 * Field Access Macros:
2226 *
2227 */
2228/*
2229 * Enumerated value for register field ALT_UART_MSR_DCTS
2230 *
2231 * no change on uart_cts_n since last read of MSR
2232 */
2233#define ALT_UART_MSR_DCTS_E_NOCHG 0x0
2234/*
2235 * Enumerated value for register field ALT_UART_MSR_DCTS
2236 *
2237 * change on uart_cts_n since last read of MSR
2238 */
2239#define ALT_UART_MSR_DCTS_E_CHG 0x1
2240
2241/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCTS register field. */
2242#define ALT_UART_MSR_DCTS_LSB 0
2243/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCTS register field. */
2244#define ALT_UART_MSR_DCTS_MSB 0
2245/* The width in bits of the ALT_UART_MSR_DCTS register field. */
2246#define ALT_UART_MSR_DCTS_WIDTH 1
2247/* The mask used to set the ALT_UART_MSR_DCTS register field value. */
2248#define ALT_UART_MSR_DCTS_SET_MSK 0x00000001
2249/* The mask used to clear the ALT_UART_MSR_DCTS register field value. */
2250#define ALT_UART_MSR_DCTS_CLR_MSK 0xfffffffe
2251/* The reset value of the ALT_UART_MSR_DCTS register field. */
2252#define ALT_UART_MSR_DCTS_RESET 0x0
2253/* Extracts the ALT_UART_MSR_DCTS field value from a register. */
2254#define ALT_UART_MSR_DCTS_GET(value) (((value) & 0x00000001) >> 0)
2255/* Produces a ALT_UART_MSR_DCTS register field value suitable for setting the register. */
2256#define ALT_UART_MSR_DCTS_SET(value) (((value) << 0) & 0x00000001)
2257
2258/*
2259 * Field : Delta Data Set Ready - ddsr
2260 *
2261 * This is used to indicate that the modem control line uart_dsr_n has changed
2262 * since the last time the MSR was read. Reading the MSR clears the DDSR bit.In
2263 * Loopback Mode (MCR[4] set to one), DDSR reflects changes on bit [0] DTR of
2264 * register MCR .
2265 *
2266 * Note, if the DDSR bit is not set and the uart_dsr_n signal is asserted (low) and
2267 * a reset occurs (software or otherwise), then the DDSR bit will get set when the
2268 * reset is removed if the uart_dsr_n signal remains asserted.
2269 *
2270 * Field Enumeration Values:
2271 *
2272 * Enum | Value | Description
2273 * :--------------------------|:------|:-----------------------------------------------
2274 * ALT_UART_MSR_DDSR_E_NOCHG | 0x0 | no change on uart_dsr_n since last read of MSR
2275 * ALT_UART_MSR_DDSR_E_CHG | 0x1 | change on uart_dsr_n since last read of MSR
2276 *
2277 * Field Access Macros:
2278 *
2279 */
2280/*
2281 * Enumerated value for register field ALT_UART_MSR_DDSR
2282 *
2283 * no change on uart_dsr_n since last read of MSR
2284 */
2285#define ALT_UART_MSR_DDSR_E_NOCHG 0x0
2286/*
2287 * Enumerated value for register field ALT_UART_MSR_DDSR
2288 *
2289 * change on uart_dsr_n since last read of MSR
2290 */
2291#define ALT_UART_MSR_DDSR_E_CHG 0x1
2292
2293/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDSR register field. */
2294#define ALT_UART_MSR_DDSR_LSB 1
2295/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDSR register field. */
2296#define ALT_UART_MSR_DDSR_MSB 1
2297/* The width in bits of the ALT_UART_MSR_DDSR register field. */
2298#define ALT_UART_MSR_DDSR_WIDTH 1
2299/* The mask used to set the ALT_UART_MSR_DDSR register field value. */
2300#define ALT_UART_MSR_DDSR_SET_MSK 0x00000002
2301/* The mask used to clear the ALT_UART_MSR_DDSR register field value. */
2302#define ALT_UART_MSR_DDSR_CLR_MSK 0xfffffffd
2303/* The reset value of the ALT_UART_MSR_DDSR register field. */
2304#define ALT_UART_MSR_DDSR_RESET 0x0
2305/* Extracts the ALT_UART_MSR_DDSR field value from a register. */
2306#define ALT_UART_MSR_DDSR_GET(value) (((value) & 0x00000002) >> 1)
2307/* Produces a ALT_UART_MSR_DDSR register field value suitable for setting the register. */
2308#define ALT_UART_MSR_DDSR_SET(value) (((value) << 1) & 0x00000002)
2309
2310/*
2311 * Field : Trailing Edge of Ring Indicator - teri
2312 *
2313 * This is used to indicate that a change on the input uart_ri_n (from an active
2314 * low, to an inactive high state) has occurred since the last time the MSR was
2315 * read. Reading the MSR clears the TERI bit. In Loopback Mode bit [4] of register
2316 * MCR is set to one, TERI reflects when bit [2] of register MCR has changed state
2317 * from a high to a low.
2318 *
2319 * Field Enumeration Values:
2320 *
2321 * Enum | Value | Description
2322 * :--------------------------|:------|:----------------------------------------------
2323 * ALT_UART_MSR_TERI_E_NOCHG | 0x0 | no change on uart_ri_n since last read of MSR
2324 * ALT_UART_MSR_TERI_E_CHG | 0x1 | change on uart_ri_n since last read of MSR
2325 *
2326 * Field Access Macros:
2327 *
2328 */
2329/*
2330 * Enumerated value for register field ALT_UART_MSR_TERI
2331 *
2332 * no change on uart_ri_n since last read of MSR
2333 */
2334#define ALT_UART_MSR_TERI_E_NOCHG 0x0
2335/*
2336 * Enumerated value for register field ALT_UART_MSR_TERI
2337 *
2338 * change on uart_ri_n since last read of MSR
2339 */
2340#define ALT_UART_MSR_TERI_E_CHG 0x1
2341
2342/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_TERI register field. */
2343#define ALT_UART_MSR_TERI_LSB 2
2344/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_TERI register field. */
2345#define ALT_UART_MSR_TERI_MSB 2
2346/* The width in bits of the ALT_UART_MSR_TERI register field. */
2347#define ALT_UART_MSR_TERI_WIDTH 1
2348/* The mask used to set the ALT_UART_MSR_TERI register field value. */
2349#define ALT_UART_MSR_TERI_SET_MSK 0x00000004
2350/* The mask used to clear the ALT_UART_MSR_TERI register field value. */
2351#define ALT_UART_MSR_TERI_CLR_MSK 0xfffffffb
2352/* The reset value of the ALT_UART_MSR_TERI register field. */
2353#define ALT_UART_MSR_TERI_RESET 0x0
2354/* Extracts the ALT_UART_MSR_TERI field value from a register. */
2355#define ALT_UART_MSR_TERI_GET(value) (((value) & 0x00000004) >> 2)
2356/* Produces a ALT_UART_MSR_TERI register field value suitable for setting the register. */
2357#define ALT_UART_MSR_TERI_SET(value) (((value) << 2) & 0x00000004)
2358
2359/*
2360 * Field : Delta Data Carrier Detect - ddcd
2361 *
2362 * This is used to indicate that the modem control line dcd_n has changed since the
2363 * last time the MSR was read. Reading the MSR clears the DDCD bit. In Loopback
2364 * Mode bit [4] of register MCR is set to one, DDCD reflects changes bit [3]
2365 * uart_out2 of register MCR.
2366 *
2367 * Note: If the DDCD bit is not set and the uart_dcd_n signal is asserted (low) and
2368 * a reset occurs (software or otherwise), then the DDCD bit will get set when the
2369 * reset is removed if the uart_dcd_n signal remains asserted.
2370 *
2371 * Field Enumeration Values:
2372 *
2373 * Enum | Value | Description
2374 * :--------------------------|:------|:-----------------------------------------------
2375 * ALT_UART_MSR_DDCD_E_NOCHG | 0x0 | no change on uart_dcd_n since last read of MSR
2376 * ALT_UART_MSR_DDCD_E_CHG | 0x1 | change on uart_dcd_n since last read of MSR
2377 *
2378 * Field Access Macros:
2379 *
2380 */
2381/*
2382 * Enumerated value for register field ALT_UART_MSR_DDCD
2383 *
2384 * no change on uart_dcd_n since last read of MSR
2385 */
2386#define ALT_UART_MSR_DDCD_E_NOCHG 0x0
2387/*
2388 * Enumerated value for register field ALT_UART_MSR_DDCD
2389 *
2390 * change on uart_dcd_n since last read of MSR
2391 */
2392#define ALT_UART_MSR_DDCD_E_CHG 0x1
2393
2394/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDCD register field. */
2395#define ALT_UART_MSR_DDCD_LSB 3
2396/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDCD register field. */
2397#define ALT_UART_MSR_DDCD_MSB 3
2398/* The width in bits of the ALT_UART_MSR_DDCD register field. */
2399#define ALT_UART_MSR_DDCD_WIDTH 1
2400/* The mask used to set the ALT_UART_MSR_DDCD register field value. */
2401#define ALT_UART_MSR_DDCD_SET_MSK 0x00000008
2402/* The mask used to clear the ALT_UART_MSR_DDCD register field value. */
2403#define ALT_UART_MSR_DDCD_CLR_MSK 0xfffffff7
2404/* The reset value of the ALT_UART_MSR_DDCD register field. */
2405#define ALT_UART_MSR_DDCD_RESET 0x0
2406/* Extracts the ALT_UART_MSR_DDCD field value from a register. */
2407#define ALT_UART_MSR_DDCD_GET(value) (((value) & 0x00000008) >> 3)
2408/* Produces a ALT_UART_MSR_DDCD register field value suitable for setting the register. */
2409#define ALT_UART_MSR_DDCD_SET(value) (((value) << 3) & 0x00000008)
2410
2411/*
2412 * Field : Clear to Send - cts
2413 *
2414 * This is used to indicate the current state of the modem control line uart_cts_n.
2415 * That is, this bit is the complement uart_cts_n. When the Clear to Send input
2416 * (uart_cts_n) is asserted it is an indication that the modem or data set is ready
2417 * to exchange data with the uart. In Loopback Mode bit [4] of register MCR is set
2418 * to one, CTS is the same as bit [1] RTS of register MCR.
2419 *
2420 * Field Enumeration Values:
2421 *
2422 * Enum | Value | Description
2423 * :--------------------------|:------|:------------------------------------------
2424 * ALT_UART_MSR_CTS_E_LOGIC1 | 0x0 | uart_cts_n input is de-asserted (logic 1)
2425 * ALT_UART_MSR_CTS_E_LOGIC0 | 0x1 | uart_cts_n input is asserted (logic 0)
2426 *
2427 * Field Access Macros:
2428 *
2429 */
2430/*
2431 * Enumerated value for register field ALT_UART_MSR_CTS
2432 *
2433 * uart_cts_n input is de-asserted (logic 1)
2434 */
2435#define ALT_UART_MSR_CTS_E_LOGIC1 0x0
2436/*
2437 * Enumerated value for register field ALT_UART_MSR_CTS
2438 *
2439 * uart_cts_n input is asserted (logic 0)
2440 */
2441#define ALT_UART_MSR_CTS_E_LOGIC0 0x1
2442
2443/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_CTS register field. */
2444#define ALT_UART_MSR_CTS_LSB 4
2445/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_CTS register field. */
2446#define ALT_UART_MSR_CTS_MSB 4
2447/* The width in bits of the ALT_UART_MSR_CTS register field. */
2448#define ALT_UART_MSR_CTS_WIDTH 1
2449/* The mask used to set the ALT_UART_MSR_CTS register field value. */
2450#define ALT_UART_MSR_CTS_SET_MSK 0x00000010
2451/* The mask used to clear the ALT_UART_MSR_CTS register field value. */
2452#define ALT_UART_MSR_CTS_CLR_MSK 0xffffffef
2453/* The reset value of the ALT_UART_MSR_CTS register field. */
2454#define ALT_UART_MSR_CTS_RESET 0x0
2455/* Extracts the ALT_UART_MSR_CTS field value from a register. */
2456#define ALT_UART_MSR_CTS_GET(value) (((value) & 0x00000010) >> 4)
2457/* Produces a ALT_UART_MSR_CTS register field value suitable for setting the register. */
2458#define ALT_UART_MSR_CTS_SET(value) (((value) << 4) & 0x00000010)
2459
2460/*
2461 * Field : Data Set Ready - dsr
2462 *
2463 * This is used to indicate the current state of the modem control line uart_dsr_n.
2464 * That is this bit is the complement f uart_dsr_n. When the Data Set Ready input
2465 * (uart_dsr_n) is asserted it is an indication that the modem or data set is ready
2466 * to establish communications with the uart. In Loopback Mode bit [4] of register
2467 * MCR is set to one, DSR is the same as bit [0] (DTR) of register MCR.
2468 *
2469 * Field Enumeration Values:
2470 *
2471 * Enum | Value | Description
2472 * :--------------------------|:------|:------------------------------------------
2473 * ALT_UART_MSR_DSR_E_LOGIC1 | 0x0 | uart_dsr_n input is de-asserted (logic 1)
2474 * ALT_UART_MSR_DSR_E_LOGIC0 | 0x1 | uart_dsr_n input is asserted (logic 0)
2475 *
2476 * Field Access Macros:
2477 *
2478 */
2479/*
2480 * Enumerated value for register field ALT_UART_MSR_DSR
2481 *
2482 * uart_dsr_n input is de-asserted (logic 1)
2483 */
2484#define ALT_UART_MSR_DSR_E_LOGIC1 0x0
2485/*
2486 * Enumerated value for register field ALT_UART_MSR_DSR
2487 *
2488 * uart_dsr_n input is asserted (logic 0)
2489 */
2490#define ALT_UART_MSR_DSR_E_LOGIC0 0x1
2491
2492/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DSR register field. */
2493#define ALT_UART_MSR_DSR_LSB 5
2494/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DSR register field. */
2495#define ALT_UART_MSR_DSR_MSB 5
2496/* The width in bits of the ALT_UART_MSR_DSR register field. */
2497#define ALT_UART_MSR_DSR_WIDTH 1
2498/* The mask used to set the ALT_UART_MSR_DSR register field value. */
2499#define ALT_UART_MSR_DSR_SET_MSK 0x00000020
2500/* The mask used to clear the ALT_UART_MSR_DSR register field value. */
2501#define ALT_UART_MSR_DSR_CLR_MSK 0xffffffdf
2502/* The reset value of the ALT_UART_MSR_DSR register field. */
2503#define ALT_UART_MSR_DSR_RESET 0x0
2504/* Extracts the ALT_UART_MSR_DSR field value from a register. */
2505#define ALT_UART_MSR_DSR_GET(value) (((value) & 0x00000020) >> 5)
2506/* Produces a ALT_UART_MSR_DSR register field value suitable for setting the register. */
2507#define ALT_UART_MSR_DSR_SET(value) (((value) << 5) & 0x00000020)
2508
2509/*
2510 * Field : Ring Indicator - ri
2511 *
2512 * This bit is used to indicate the current state of the modem control line
2513 * uart_ri_n. That is this bit is the complement uart_ri_n. When the Ring Indicator
2514 * input (uart_ri_n) is asserted it is an indication that a telephone ringing
2515 * signal has been received by the modem or data set. In Loopback Mode bit [4] of
2516 * register MCR set to one, RI is the same as bit [2] uart_out1_n of register MCR.
2517 *
2518 * Field Enumeration Values:
2519 *
2520 * Enum | Value | Description
2521 * :-------------------------|:------|:-----------------------------------------
2522 * ALT_UART_MSR_RI_E_LOGIC1 | 0x0 | uart_ri_n input is de-asserted (logic 1)
2523 * ALT_UART_MSR_RI_E_LOGIC0 | 0x1 | uart_ri_n input is asserted (logic 0)
2524 *
2525 * Field Access Macros:
2526 *
2527 */
2528/*
2529 * Enumerated value for register field ALT_UART_MSR_RI
2530 *
2531 * uart_ri_n input is de-asserted (logic 1)
2532 */
2533#define ALT_UART_MSR_RI_E_LOGIC1 0x0
2534/*
2535 * Enumerated value for register field ALT_UART_MSR_RI
2536 *
2537 * uart_ri_n input is asserted (logic 0)
2538 */
2539#define ALT_UART_MSR_RI_E_LOGIC0 0x1
2540
2541/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_RI register field. */
2542#define ALT_UART_MSR_RI_LSB 6
2543/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_RI register field. */
2544#define ALT_UART_MSR_RI_MSB 6
2545/* The width in bits of the ALT_UART_MSR_RI register field. */
2546#define ALT_UART_MSR_RI_WIDTH 1
2547/* The mask used to set the ALT_UART_MSR_RI register field value. */
2548#define ALT_UART_MSR_RI_SET_MSK 0x00000040
2549/* The mask used to clear the ALT_UART_MSR_RI register field value. */
2550#define ALT_UART_MSR_RI_CLR_MSK 0xffffffbf
2551/* The reset value of the ALT_UART_MSR_RI register field. */
2552#define ALT_UART_MSR_RI_RESET 0x0
2553/* Extracts the ALT_UART_MSR_RI field value from a register. */
2554#define ALT_UART_MSR_RI_GET(value) (((value) & 0x00000040) >> 6)
2555/* Produces a ALT_UART_MSR_RI register field value suitable for setting the register. */
2556#define ALT_UART_MSR_RI_SET(value) (((value) << 6) & 0x00000040)
2557
2558/*
2559 * Field : Data Carrier Detect - dcd
2560 *
2561 * This is used to indicate the current state of the modem control line uart_dcd_n.
2562 * That is this bit is the complement uart_dcd_n. When the Data Carrier Detect
2563 * input (uart_dcd_n) is asserted it is an indication that the carrier has been
2564 * detected by the modem or data set. In Loopback Mode (MCR[4] set to one), DCD is
2565 * the same as MCR[3] (uart_out2).
2566 *
2567 * Field Enumeration Values:
2568 *
2569 * Enum | Value | Description
2570 * :--------------------------|:------|:------------------------------------------
2571 * ALT_UART_MSR_DCD_E_LOGIC1 | 0x0 | uart_dcd_n input is de-asserted (logic 1)
2572 * ALT_UART_MSR_DCD_E_LOGIC0 | 0x1 | uart_dcd_n input is asserted (logic 0)
2573 *
2574 * Field Access Macros:
2575 *
2576 */
2577/*
2578 * Enumerated value for register field ALT_UART_MSR_DCD
2579 *
2580 * uart_dcd_n input is de-asserted (logic 1)
2581 */
2582#define ALT_UART_MSR_DCD_E_LOGIC1 0x0
2583/*
2584 * Enumerated value for register field ALT_UART_MSR_DCD
2585 *
2586 * uart_dcd_n input is asserted (logic 0)
2587 */
2588#define ALT_UART_MSR_DCD_E_LOGIC0 0x1
2589
2590/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCD register field. */
2591#define ALT_UART_MSR_DCD_LSB 7
2592/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCD register field. */
2593#define ALT_UART_MSR_DCD_MSB 7
2594/* The width in bits of the ALT_UART_MSR_DCD register field. */
2595#define ALT_UART_MSR_DCD_WIDTH 1
2596/* The mask used to set the ALT_UART_MSR_DCD register field value. */
2597#define ALT_UART_MSR_DCD_SET_MSK 0x00000080
2598/* The mask used to clear the ALT_UART_MSR_DCD register field value. */
2599#define ALT_UART_MSR_DCD_CLR_MSK 0xffffff7f
2600/* The reset value of the ALT_UART_MSR_DCD register field. */
2601#define ALT_UART_MSR_DCD_RESET 0x0
2602/* Extracts the ALT_UART_MSR_DCD field value from a register. */
2603#define ALT_UART_MSR_DCD_GET(value) (((value) & 0x00000080) >> 7)
2604/* Produces a ALT_UART_MSR_DCD register field value suitable for setting the register. */
2605#define ALT_UART_MSR_DCD_SET(value) (((value) << 7) & 0x00000080)
2606
2607#ifndef __ASSEMBLY__
2608/*
2609 * WARNING: The C register and register group struct declarations are provided for
2610 * convenience and illustrative purposes. They should, however, be used with
2611 * caution as the C language standard provides no guarantees about the alignment or
2612 * atomicity of device memory accesses. The recommended practice for writing
2613 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2614 * alt_write_word() functions.
2615 *
2616 * The struct declaration for register ALT_UART_MSR.
2617 */
2618 struct ALT_UART_MSR_s
2619{
2620 const uint32_t dcts : 1; /* Delta Clear to Send */
2621 const uint32_t ddsr : 1; /* Delta Data Set Ready */
2622 const uint32_t teri : 1; /* Trailing Edge of Ring Indicator */
2623 const uint32_t ddcd : 1; /* Delta Data Carrier Detect */
2624 const uint32_t cts : 1; /* Clear to Send */
2625 const uint32_t dsr : 1; /* Data Set Ready */
2626 const uint32_t ri : 1; /* Ring Indicator */
2627 const uint32_t dcd : 1; /* Data Carrier Detect */
2628 uint32_t : 24; /* *UNDEFINED* */
2629};
2630
2631/* The typedef declaration for register ALT_UART_MSR. */
2632typedef volatile struct ALT_UART_MSR_s ALT_UART_MSR_t;
2633#endif /* __ASSEMBLY__ */
2634
2635/* The byte offset of the ALT_UART_MSR register from the beginning of the component. */
2636#define ALT_UART_MSR_OFST 0x18
2637/* The address of the ALT_UART_MSR register. */
2638#define ALT_UART_MSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MSR_OFST))
2639
2640/*
2641 * Register : Scratchpad Register - scr
2642 *
2643 * Scratchpad Register
2644 *
2645 * Register Layout
2646 *
2647 * Bits | Access | Reset | Description
2648 * :-------|:-------|:------|:--------------------
2649 * [7:0] | RW | 0x0 | Scratchpad Register
2650 * [31:8] | ??? | 0x0 | *UNDEFINED*
2651 *
2652 */
2653/*
2654 * Field : Scratchpad Register - scr
2655 *
2656 * This register is for programmers to use as a temporary storage space.
2657 *
2658 * Field Access Macros:
2659 *
2660 */
2661/* The Least Significant Bit (LSB) position of the ALT_UART_SCR_SCR register field. */
2662#define ALT_UART_SCR_SCR_LSB 0
2663/* The Most Significant Bit (MSB) position of the ALT_UART_SCR_SCR register field. */
2664#define ALT_UART_SCR_SCR_MSB 7
2665/* The width in bits of the ALT_UART_SCR_SCR register field. */
2666#define ALT_UART_SCR_SCR_WIDTH 8
2667/* The mask used to set the ALT_UART_SCR_SCR register field value. */
2668#define ALT_UART_SCR_SCR_SET_MSK 0x000000ff
2669/* The mask used to clear the ALT_UART_SCR_SCR register field value. */
2670#define ALT_UART_SCR_SCR_CLR_MSK 0xffffff00
2671/* The reset value of the ALT_UART_SCR_SCR register field. */
2672#define ALT_UART_SCR_SCR_RESET 0x0
2673/* Extracts the ALT_UART_SCR_SCR field value from a register. */
2674#define ALT_UART_SCR_SCR_GET(value) (((value) & 0x000000ff) >> 0)
2675/* Produces a ALT_UART_SCR_SCR register field value suitable for setting the register. */
2676#define ALT_UART_SCR_SCR_SET(value) (((value) << 0) & 0x000000ff)
2677
2678#ifndef __ASSEMBLY__
2679/*
2680 * WARNING: The C register and register group struct declarations are provided for
2681 * convenience and illustrative purposes. They should, however, be used with
2682 * caution as the C language standard provides no guarantees about the alignment or
2683 * atomicity of device memory accesses. The recommended practice for writing
2684 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2685 * alt_write_word() functions.
2686 *
2687 * The struct declaration for register ALT_UART_SCR.
2688 */
2689 struct ALT_UART_SCR_s
2690{
2691 uint32_t scr : 8; /* Scratchpad Register */
2692 uint32_t : 24; /* *UNDEFINED* */
2693};
2694
2695/* The typedef declaration for register ALT_UART_SCR. */
2696typedef volatile struct ALT_UART_SCR_s ALT_UART_SCR_t;
2697#endif /* __ASSEMBLY__ */
2698
2699/* The byte offset of the ALT_UART_SCR register from the beginning of the component. */
2700#define ALT_UART_SCR_OFST 0x1c
2701/* The address of the ALT_UART_SCR register. */
2702#define ALT_UART_SCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SCR_OFST))
2703
2704/*
2705 * Register : Shadow Receive Buffer Register - srbr
2706 *
2707 * Used to accomadate burst accesses from the master.
2708 *
2709 * Register Layout
2710 *
2711 * Bits | Access | Reset | Description
2712 * :-------|:-------|:------|:----------------------
2713 * [7:0] | RW | 0x0 | Shadow Receive Buffer
2714 * [31:8] | ??? | 0x0 | *UNDEFINED*
2715 *
2716 */
2717/*
2718 * Field : Shadow Receive Buffer - srbr
2719 *
2720 * This is a shadow register for the RBR and has been allocated one 32-bit location
2721 * so as to accommodate burst accesses from the master.This register contains the
2722 * data byte received on the serial input port (sin). The data in this register is
2723 * valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set.
2724 * If FIFOs are disabled, bit [0] of register FCR set to zero, the data in the RBR
2725 * must be read before the next data arrives, otherwise it will be overwritten,
2726 * resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this
2727 * register accesses the head of the receive FIFO. If the receive FIFO is full and
2728 * this register is not read before the next data character arrives, then the data
2729 * already in the FIFO will be preserved but any incoming data will be lost. An
2730 * overrun error will also occur.
2731 *
2732 * Field Access Macros:
2733 *
2734 */
2735/* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_SRBR register field. */
2736#define ALT_UART_SRBR_SRBR_LSB 0
2737/* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_SRBR register field. */
2738#define ALT_UART_SRBR_SRBR_MSB 7
2739/* The width in bits of the ALT_UART_SRBR_SRBR register field. */
2740#define ALT_UART_SRBR_SRBR_WIDTH 8
2741/* The mask used to set the ALT_UART_SRBR_SRBR register field value. */
2742#define ALT_UART_SRBR_SRBR_SET_MSK 0x000000ff
2743/* The mask used to clear the ALT_UART_SRBR_SRBR register field value. */
2744#define ALT_UART_SRBR_SRBR_CLR_MSK 0xffffff00
2745/* The reset value of the ALT_UART_SRBR_SRBR register field. */
2746#define ALT_UART_SRBR_SRBR_RESET 0x0
2747/* Extracts the ALT_UART_SRBR_SRBR field value from a register. */
2748#define ALT_UART_SRBR_SRBR_GET(value) (((value) & 0x000000ff) >> 0)
2749/* Produces a ALT_UART_SRBR_SRBR register field value suitable for setting the register. */
2750#define ALT_UART_SRBR_SRBR_SET(value) (((value) << 0) & 0x000000ff)
2751
2752#ifndef __ASSEMBLY__
2753/*
2754 * WARNING: The C register and register group struct declarations are provided for
2755 * convenience and illustrative purposes. They should, however, be used with
2756 * caution as the C language standard provides no guarantees about the alignment or
2757 * atomicity of device memory accesses. The recommended practice for writing
2758 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2759 * alt_write_word() functions.
2760 *
2761 * The struct declaration for register ALT_UART_SRBR.
2762 */
2763 struct ALT_UART_SRBR_s
2764{
2765 uint32_t srbr : 8; /* Shadow Receive Buffer */
2766 uint32_t : 24; /* *UNDEFINED* */
2767};
2768
2769/* The typedef declaration for register ALT_UART_SRBR. */
2770typedef volatile struct ALT_UART_SRBR_s ALT_UART_SRBR_t;
2771#endif /* __ASSEMBLY__ */
2772
2773/* The byte offset of the ALT_UART_SRBR register from the beginning of the component. */
2774#define ALT_UART_SRBR_OFST 0x30
2775/* The address of the ALT_UART_SRBR register. */
2776#define ALT_UART_SRBR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_OFST))
2777
2778/*
2779 * Register : Shadow Transmit Buffer Register - sthr
2780 *
2781 * Used to accomadate burst accesses from the master.
2782 *
2783 * Register Layout
2784 *
2785 * Bits | Access | Reset | Description
2786 * :-------|:-------|:------|:-----------------------
2787 * [7:0] | RW | 0x0 | Shadow Transmit Buffer
2788 * [31:8] | ??? | 0x0 | *UNDEFINED*
2789 *
2790 */
2791/*
2792 * Field : Shadow Transmit Buffer - sthr
2793 *
2794 * This is a shadow register for the THR and has been allocated sixteen 32-bit
2795 * locations so as to accommodate burst accesses from the master. This register
2796 * contains data to be transmitted on the serial output port (sout). Data should
2797 * only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If
2798 * FIFO's are disabled bit [0] of register FCR set to zero and THRE is set, writing
2799 * a single character to the THR clears the THRE. Any additional writes to the THR
2800 * before the THRE is set again causes the THR data to be overwritten. If FIFO's
2801 * are enabled bit [0] of register FCR set to one and THRE is set, 128 characters
2802 * of data may be written to the THR before the FIFO is full. The UART FIFO depth
2803 * is configured for 128 characters. Any attempt to write data when the FIFO is
2804 * full results in the write data being lost.
2805 *
2806 * Field Access Macros:
2807 *
2808 */
2809/* The Least Significant Bit (LSB) position of the ALT_UART_STHR_STHR register field. */
2810#define ALT_UART_STHR_STHR_LSB 0
2811/* The Most Significant Bit (MSB) position of the ALT_UART_STHR_STHR register field. */
2812#define ALT_UART_STHR_STHR_MSB 7
2813/* The width in bits of the ALT_UART_STHR_STHR register field. */
2814#define ALT_UART_STHR_STHR_WIDTH 8
2815/* The mask used to set the ALT_UART_STHR_STHR register field value. */
2816#define ALT_UART_STHR_STHR_SET_MSK 0x000000ff
2817/* The mask used to clear the ALT_UART_STHR_STHR register field value. */
2818#define ALT_UART_STHR_STHR_CLR_MSK 0xffffff00
2819/* The reset value of the ALT_UART_STHR_STHR register field. */
2820#define ALT_UART_STHR_STHR_RESET 0x0
2821/* Extracts the ALT_UART_STHR_STHR field value from a register. */
2822#define ALT_UART_STHR_STHR_GET(value) (((value) & 0x000000ff) >> 0)
2823/* Produces a ALT_UART_STHR_STHR register field value suitable for setting the register. */
2824#define ALT_UART_STHR_STHR_SET(value) (((value) << 0) & 0x000000ff)
2825
2826#ifndef __ASSEMBLY__
2827/*
2828 * WARNING: The C register and register group struct declarations are provided for
2829 * convenience and illustrative purposes. They should, however, be used with
2830 * caution as the C language standard provides no guarantees about the alignment or
2831 * atomicity of device memory accesses. The recommended practice for writing
2832 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2833 * alt_write_word() functions.
2834 *
2835 * The struct declaration for register ALT_UART_STHR.
2836 */
2837 struct ALT_UART_STHR_s
2838{
2839 uint32_t sthr : 8; /* Shadow Transmit Buffer */
2840 uint32_t : 24; /* *UNDEFINED* */
2841};
2842
2843/* The typedef declaration for register ALT_UART_STHR. */
2844typedef volatile struct ALT_UART_STHR_s ALT_UART_STHR_t;
2845#endif /* __ASSEMBLY__ */
2846
2847/* The byte offset of the ALT_UART_STHR register from the beginning of the component. */
2848#define ALT_UART_STHR_OFST 0x34
2849/* The address of the ALT_UART_STHR register. */
2850#define ALT_UART_STHR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STHR_OFST))
2851
2852/*
2853 * Register : FIFO Access Register - far
2854 *
2855 * This register is used in FIFO access testing.
2856 *
2857 * Register Layout
2858 *
2859 * Bits | Access | Reset | Description
2860 * :-------|:-------|:------|:----------------
2861 * [0] | RW | 0x0 | FIFO ACCESS Bit
2862 * [31:1] | ??? | 0x0 | *UNDEFINED*
2863 *
2864 */
2865/*
2866 * Field : FIFO ACCESS Bit - srbr_sthr
2867 *
2868 * This register is used to enable a FIFO access mode for testing, so that the
2869 * receive FIFO can be written by the master and the transmit FIFO can be read by
2870 * the master when FIFO's are enabled. When FIFO's are not enabled it allows the
2871 * RBR to be written by the master and the THR to be read by the master
2872 *
2873 * Note: That when the FIFO access mode is enabled/disabled, the control portion of
2874 * the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty.
2875 *
2876 * Field Enumeration Values:
2877 *
2878 * Enum | Value | Description
2879 * :------------------------------|:------|:--------------------------
2880 * ALT_UART_FAR_SRBR_STHR_E_DISD | 0x0 | FIFO access mode disabled
2881 * ALT_UART_FAR_SRBR_STHR_E_END | 0x1 | FIFO access mode enabled
2882 *
2883 * Field Access Macros:
2884 *
2885 */
2886/*
2887 * Enumerated value for register field ALT_UART_FAR_SRBR_STHR
2888 *
2889 * FIFO access mode disabled
2890 */
2891#define ALT_UART_FAR_SRBR_STHR_E_DISD 0x0
2892/*
2893 * Enumerated value for register field ALT_UART_FAR_SRBR_STHR
2894 *
2895 * FIFO access mode enabled
2896 */
2897#define ALT_UART_FAR_SRBR_STHR_E_END 0x1
2898
2899/* The Least Significant Bit (LSB) position of the ALT_UART_FAR_SRBR_STHR register field. */
2900#define ALT_UART_FAR_SRBR_STHR_LSB 0
2901/* The Most Significant Bit (MSB) position of the ALT_UART_FAR_SRBR_STHR register field. */
2902#define ALT_UART_FAR_SRBR_STHR_MSB 0
2903/* The width in bits of the ALT_UART_FAR_SRBR_STHR register field. */
2904#define ALT_UART_FAR_SRBR_STHR_WIDTH 1
2905/* The mask used to set the ALT_UART_FAR_SRBR_STHR register field value. */
2906#define ALT_UART_FAR_SRBR_STHR_SET_MSK 0x00000001
2907/* The mask used to clear the ALT_UART_FAR_SRBR_STHR register field value. */
2908#define ALT_UART_FAR_SRBR_STHR_CLR_MSK 0xfffffffe
2909/* The reset value of the ALT_UART_FAR_SRBR_STHR register field. */
2910#define ALT_UART_FAR_SRBR_STHR_RESET 0x0
2911/* Extracts the ALT_UART_FAR_SRBR_STHR field value from a register. */
2912#define ALT_UART_FAR_SRBR_STHR_GET(value) (((value) & 0x00000001) >> 0)
2913/* Produces a ALT_UART_FAR_SRBR_STHR register field value suitable for setting the register. */
2914#define ALT_UART_FAR_SRBR_STHR_SET(value) (((value) << 0) & 0x00000001)
2915
2916#ifndef __ASSEMBLY__
2917/*
2918 * WARNING: The C register and register group struct declarations are provided for
2919 * convenience and illustrative purposes. They should, however, be used with
2920 * caution as the C language standard provides no guarantees about the alignment or
2921 * atomicity of device memory accesses. The recommended practice for writing
2922 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2923 * alt_write_word() functions.
2924 *
2925 * The struct declaration for register ALT_UART_FAR.
2926 */
2927 struct ALT_UART_FAR_s
2928{
2929 uint32_t srbr_sthr : 1; /* FIFO ACCESS Bit */
2930 uint32_t : 31; /* *UNDEFINED* */
2931};
2932
2933/* The typedef declaration for register ALT_UART_FAR. */
2934typedef volatile struct ALT_UART_FAR_s ALT_UART_FAR_t;
2935#endif /* __ASSEMBLY__ */
2936
2937/* The byte offset of the ALT_UART_FAR register from the beginning of the component. */
2938#define ALT_UART_FAR_OFST 0x70
2939/* The address of the ALT_UART_FAR register. */
2940#define ALT_UART_FAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FAR_OFST))
2941
2942/*
2943 * Register : Transmit FIFO Read Register - tfr
2944 *
2945 * Used in FIFO Access test mode.
2946 *
2947 * Register Layout
2948 *
2949 * Bits | Access | Reset | Description
2950 * :-------|:-------|:------|:-------------------
2951 * [7:0] | R | 0x0 | Transmit FIFO Read
2952 * [31:8] | ??? | 0x0 | *UNDEFINED*
2953 *
2954 */
2955/*
2956 * Field : Transmit FIFO Read - tfr
2957 *
2958 * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
2959 * one). When FIFO's are enabled, reading this register gives the data at the top
2960 * of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the
2961 * next data value that is currently at the top of the FIFO. When FIFO's are not
2962 * enabled, reading this register gives the data in the THR.
2963 *
2964 * Field Access Macros:
2965 *
2966 */
2967/* The Least Significant Bit (LSB) position of the ALT_UART_TFR_TFR register field. */
2968#define ALT_UART_TFR_TFR_LSB 0
2969/* The Most Significant Bit (MSB) position of the ALT_UART_TFR_TFR register field. */
2970#define ALT_UART_TFR_TFR_MSB 7
2971/* The width in bits of the ALT_UART_TFR_TFR register field. */
2972#define ALT_UART_TFR_TFR_WIDTH 8
2973/* The mask used to set the ALT_UART_TFR_TFR register field value. */
2974#define ALT_UART_TFR_TFR_SET_MSK 0x000000ff
2975/* The mask used to clear the ALT_UART_TFR_TFR register field value. */
2976#define ALT_UART_TFR_TFR_CLR_MSK 0xffffff00
2977/* The reset value of the ALT_UART_TFR_TFR register field. */
2978#define ALT_UART_TFR_TFR_RESET 0x0
2979/* Extracts the ALT_UART_TFR_TFR field value from a register. */
2980#define ALT_UART_TFR_TFR_GET(value) (((value) & 0x000000ff) >> 0)
2981/* Produces a ALT_UART_TFR_TFR register field value suitable for setting the register. */
2982#define ALT_UART_TFR_TFR_SET(value) (((value) << 0) & 0x000000ff)
2983
2984#ifndef __ASSEMBLY__
2985/*
2986 * WARNING: The C register and register group struct declarations are provided for
2987 * convenience and illustrative purposes. They should, however, be used with
2988 * caution as the C language standard provides no guarantees about the alignment or
2989 * atomicity of device memory accesses. The recommended practice for writing
2990 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2991 * alt_write_word() functions.
2992 *
2993 * The struct declaration for register ALT_UART_TFR.
2994 */
2995 struct ALT_UART_TFR_s
2996{
2997 const uint32_t tfr : 8; /* Transmit FIFO Read */
2998 uint32_t : 24; /* *UNDEFINED* */
2999};
3000
3001/* The typedef declaration for register ALT_UART_TFR. */
3002typedef volatile struct ALT_UART_TFR_s ALT_UART_TFR_t;
3003#endif /* __ASSEMBLY__ */
3004
3005/* The byte offset of the ALT_UART_TFR register from the beginning of the component. */
3006#define ALT_UART_TFR_OFST 0x74
3007/* The address of the ALT_UART_TFR register. */
3008#define ALT_UART_TFR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFR_OFST))
3009
3010/*
3011 * Register : Receive FIFO Write - RFW
3012 *
3013 * Used only with FIFO access test mode.
3014 *
3015 * Register Layout
3016 *
3017 * Bits | Access | Reset | Description
3018 * :--------|:-------|:------|:---------------------------
3019 * [7:0] | W | 0x0 | Receive FIFO Write Field
3020 * [8] | W | 0x0 | Receive FIFO Parity Error
3021 * [9] | W | 0x0 | Receive FIFO Framing Error
3022 * [31:10] | ??? | 0x0 | *UNDEFINED*
3023 *
3024 */
3025/*
3026 * Field : Receive FIFO Write Field - rfwd
3027 *
3028 * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
3029 * one). When FIFO's are enabled, the data that is written to the RFWD is pushed
3030 * into the receive FIFO. Each consecutive write pushes the new data to the next
3031 * write location in the receive FIFO. When FIFO's are not enabled, the data that
3032 * is written to the RFWD is pushed into the RBR.
3033 *
3034 * Field Access Macros:
3035 *
3036 */
3037/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFWD register field. */
3038#define ALT_UART_RFW_RFWD_LSB 0
3039/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFWD register field. */
3040#define ALT_UART_RFW_RFWD_MSB 7
3041/* The width in bits of the ALT_UART_RFW_RFWD register field. */
3042#define ALT_UART_RFW_RFWD_WIDTH 8
3043/* The mask used to set the ALT_UART_RFW_RFWD register field value. */
3044#define ALT_UART_RFW_RFWD_SET_MSK 0x000000ff
3045/* The mask used to clear the ALT_UART_RFW_RFWD register field value. */
3046#define ALT_UART_RFW_RFWD_CLR_MSK 0xffffff00
3047/* The reset value of the ALT_UART_RFW_RFWD register field. */
3048#define ALT_UART_RFW_RFWD_RESET 0x0
3049/* Extracts the ALT_UART_RFW_RFWD field value from a register. */
3050#define ALT_UART_RFW_RFWD_GET(value) (((value) & 0x000000ff) >> 0)
3051/* Produces a ALT_UART_RFW_RFWD register field value suitable for setting the register. */
3052#define ALT_UART_RFW_RFWD_SET(value) (((value) << 0) & 0x000000ff)
3053
3054/*
3055 * Field : Receive FIFO Parity Error - rfpe
3056 *
3057 * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
3058 * one). When FIFO's are enabled, this bit is used to write parity error detection
3059 * information to the receive FIFO. When FIFO's are not enabled, this bit is used
3060 * to write parity error detection information to the RBR.
3061 *
3062 * Field Access Macros:
3063 *
3064 */
3065/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFPE register field. */
3066#define ALT_UART_RFW_RFPE_LSB 8
3067/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFPE register field. */
3068#define ALT_UART_RFW_RFPE_MSB 8
3069/* The width in bits of the ALT_UART_RFW_RFPE register field. */
3070#define ALT_UART_RFW_RFPE_WIDTH 1
3071/* The mask used to set the ALT_UART_RFW_RFPE register field value. */
3072#define ALT_UART_RFW_RFPE_SET_MSK 0x00000100
3073/* The mask used to clear the ALT_UART_RFW_RFPE register field value. */
3074#define ALT_UART_RFW_RFPE_CLR_MSK 0xfffffeff
3075/* The reset value of the ALT_UART_RFW_RFPE register field. */
3076#define ALT_UART_RFW_RFPE_RESET 0x0
3077/* Extracts the ALT_UART_RFW_RFPE field value from a register. */
3078#define ALT_UART_RFW_RFPE_GET(value) (((value) & 0x00000100) >> 8)
3079/* Produces a ALT_UART_RFW_RFPE register field value suitable for setting the register. */
3080#define ALT_UART_RFW_RFPE_SET(value) (((value) << 8) & 0x00000100)
3081
3082/*
3083 * Field : Receive FIFO Framing Error - RFFE
3084 *
3085 * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
3086 * one). When FIFO's are enabled, this bit is used to write framing error detection
3087 * information to the receive FIFO. When FIFO's are not enabled, this bit is used
3088 * to write framing error detection information to the RBR.
3089 *
3090 * Field Access Macros:
3091 *
3092 */
3093/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFFE register field. */
3094#define ALT_UART_RFW_RFFE_LSB 9
3095/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFFE register field. */
3096#define ALT_UART_RFW_RFFE_MSB 9
3097/* The width in bits of the ALT_UART_RFW_RFFE register field. */
3098#define ALT_UART_RFW_RFFE_WIDTH 1
3099/* The mask used to set the ALT_UART_RFW_RFFE register field value. */
3100#define ALT_UART_RFW_RFFE_SET_MSK 0x00000200
3101/* The mask used to clear the ALT_UART_RFW_RFFE register field value. */
3102#define ALT_UART_RFW_RFFE_CLR_MSK 0xfffffdff
3103/* The reset value of the ALT_UART_RFW_RFFE register field. */
3104#define ALT_UART_RFW_RFFE_RESET 0x0
3105/* Extracts the ALT_UART_RFW_RFFE field value from a register. */
3106#define ALT_UART_RFW_RFFE_GET(value) (((value) & 0x00000200) >> 9)
3107/* Produces a ALT_UART_RFW_RFFE register field value suitable for setting the register. */
3108#define ALT_UART_RFW_RFFE_SET(value) (((value) << 9) & 0x00000200)
3109
3110#ifndef __ASSEMBLY__
3111/*
3112 * WARNING: The C register and register group struct declarations are provided for
3113 * convenience and illustrative purposes. They should, however, be used with
3114 * caution as the C language standard provides no guarantees about the alignment or
3115 * atomicity of device memory accesses. The recommended practice for writing
3116 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3117 * alt_write_word() functions.
3118 *
3119 * The struct declaration for register ALT_UART_RFW.
3120 */
3121 struct ALT_UART_RFW_s
3122{
3123 uint32_t rfwd : 8; /* Receive FIFO Write Field */
3124 uint32_t rfpe : 1; /* Receive FIFO Parity Error */
3125 uint32_t RFFE : 1; /* Receive FIFO Framing Error */
3126 uint32_t : 22; /* *UNDEFINED* */
3127};
3128
3129/* The typedef declaration for register ALT_UART_RFW. */
3130typedef volatile struct ALT_UART_RFW_s ALT_UART_RFW_t;
3131#endif /* __ASSEMBLY__ */
3132
3133/* The byte offset of the ALT_UART_RFW register from the beginning of the component. */
3134#define ALT_UART_RFW_OFST 0x78
3135/* The address of the ALT_UART_RFW register. */
3136#define ALT_UART_RFW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFW_OFST))
3137
3138/*
3139 * Register : UART Status Register - usr
3140 *
3141 * Status of FIFO Operations.
3142 *
3143 * Register Layout
3144 *
3145 * Bits | Access | Reset | Description
3146 * :-------|:-------|:------|:-----------------------
3147 * [0] | ??? | 0x0 | *UNDEFINED*
3148 * [1] | R | 0x1 | Transmit FIFO Not Full
3149 * [2] | R | 0x1 | Transmit FIFO Empty
3150 * [3] | R | 0x0 | Receive FIFO Not Empty
3151 * [4] | R | 0x0 | Receive FIFO Full
3152 * [31:5] | ??? | 0x0 | *UNDEFINED*
3153 *
3154 */
3155/*
3156 * Field : Transmit FIFO Not Full - tfnf
3157 *
3158 * This Bit is used to indicate that the transmit FIFO in not full. This bit is
3159 * cleared when the Tx FIFO is full.
3160 *
3161 * Field Enumeration Values:
3162 *
3163 * Enum | Value | Description
3164 * :----------------------------|:------|:--------------------------
3165 * ALT_UART_USR_TFNF_E_FULL | 0x0 | Transmit FIFO is full
3166 * ALT_UART_USR_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full
3167 *
3168 * Field Access Macros:
3169 *
3170 */
3171/*
3172 * Enumerated value for register field ALT_UART_USR_TFNF
3173 *
3174 * Transmit FIFO is full
3175 */
3176#define ALT_UART_USR_TFNF_E_FULL 0x0
3177/*
3178 * Enumerated value for register field ALT_UART_USR_TFNF
3179 *
3180 * Transmit FIFO is not full
3181 */
3182#define ALT_UART_USR_TFNF_E_NOTFULL 0x1
3183
3184/* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFNF register field. */
3185#define ALT_UART_USR_TFNF_LSB 1
3186/* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFNF register field. */
3187#define ALT_UART_USR_TFNF_MSB 1
3188/* The width in bits of the ALT_UART_USR_TFNF register field. */
3189#define ALT_UART_USR_TFNF_WIDTH 1
3190/* The mask used to set the ALT_UART_USR_TFNF register field value. */
3191#define ALT_UART_USR_TFNF_SET_MSK 0x00000002
3192/* The mask used to clear the ALT_UART_USR_TFNF register field value. */
3193#define ALT_UART_USR_TFNF_CLR_MSK 0xfffffffd
3194/* The reset value of the ALT_UART_USR_TFNF register field. */
3195#define ALT_UART_USR_TFNF_RESET 0x1
3196/* Extracts the ALT_UART_USR_TFNF field value from a register. */
3197#define ALT_UART_USR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
3198/* Produces a ALT_UART_USR_TFNF register field value suitable for setting the register. */
3199#define ALT_UART_USR_TFNF_SET(value) (((value) << 1) & 0x00000002)
3200
3201/*
3202 * Field : Transmit FIFO Empty - tfe
3203 *
3204 * This is used to indicate that the transmit FIFO is completely empty. This bit is
3205 * cleared when the Tx FIFO is no longer empty.
3206 *
3207 * Field Enumeration Values:
3208 *
3209 * Enum | Value | Description
3210 * :----------------------------|:------|:---------------------------
3211 * ALT_UART_USR_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty
3212 * ALT_UART_USR_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty
3213 *
3214 * Field Access Macros:
3215 *
3216 */
3217/*
3218 * Enumerated value for register field ALT_UART_USR_TFE
3219 *
3220 * Transmit FIFO is not empty
3221 */
3222#define ALT_UART_USR_TFE_E_NOTEMPTY 0x0
3223/*
3224 * Enumerated value for register field ALT_UART_USR_TFE
3225 *
3226 * Transmit FIFO is empty
3227 */
3228#define ALT_UART_USR_TFE_E_EMPTY 0x1
3229
3230/* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFE register field. */
3231#define ALT_UART_USR_TFE_LSB 2
3232/* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFE register field. */
3233#define ALT_UART_USR_TFE_MSB 2
3234/* The width in bits of the ALT_UART_USR_TFE register field. */
3235#define ALT_UART_USR_TFE_WIDTH 1
3236/* The mask used to set the ALT_UART_USR_TFE register field value. */
3237#define ALT_UART_USR_TFE_SET_MSK 0x00000004
3238/* The mask used to clear the ALT_UART_USR_TFE register field value. */
3239#define ALT_UART_USR_TFE_CLR_MSK 0xfffffffb
3240/* The reset value of the ALT_UART_USR_TFE register field. */
3241#define ALT_UART_USR_TFE_RESET 0x1
3242/* Extracts the ALT_UART_USR_TFE field value from a register. */
3243#define ALT_UART_USR_TFE_GET(value) (((value) & 0x00000004) >> 2)
3244/* Produces a ALT_UART_USR_TFE register field value suitable for setting the register. */
3245#define ALT_UART_USR_TFE_SET(value) (((value) << 2) & 0x00000004)
3246
3247/*
3248 * Field : Receive FIFO Not Empty - rfne
3249 *
3250 * This Bit is used to indicate that the receive FIFO contains one or more entries.
3251 * This bit is cleared when the Rx FIFO is empty.
3252 *
3253 * Field Enumeration Values:
3254 *
3255 * Enum | Value | Description
3256 * :-----------------------------|:------|:--------------------------
3257 * ALT_UART_USR_RFNE_E_EMPTY | 0x0 | Receiive FIFO is empty
3258 * ALT_UART_USR_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty
3259 *
3260 * Field Access Macros:
3261 *
3262 */
3263/*
3264 * Enumerated value for register field ALT_UART_USR_RFNE
3265 *
3266 * Receiive FIFO is empty
3267 */
3268#define ALT_UART_USR_RFNE_E_EMPTY 0x0
3269/*
3270 * Enumerated value for register field ALT_UART_USR_RFNE
3271 *
3272 * Receive FIFO is not empty
3273 */
3274#define ALT_UART_USR_RFNE_E_NOTEMPTY 0x1
3275
3276/* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFNE register field. */
3277#define ALT_UART_USR_RFNE_LSB 3
3278/* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFNE register field. */
3279#define ALT_UART_USR_RFNE_MSB 3
3280/* The width in bits of the ALT_UART_USR_RFNE register field. */
3281#define ALT_UART_USR_RFNE_WIDTH 1
3282/* The mask used to set the ALT_UART_USR_RFNE register field value. */
3283#define ALT_UART_USR_RFNE_SET_MSK 0x00000008
3284/* The mask used to clear the ALT_UART_USR_RFNE register field value. */
3285#define ALT_UART_USR_RFNE_CLR_MSK 0xfffffff7
3286/* The reset value of the ALT_UART_USR_RFNE register field. */
3287#define ALT_UART_USR_RFNE_RESET 0x0
3288/* Extracts the ALT_UART_USR_RFNE field value from a register. */
3289#define ALT_UART_USR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
3290/* Produces a ALT_UART_USR_RFNE register field value suitable for setting the register. */
3291#define ALT_UART_USR_RFNE_SET(value) (((value) << 3) & 0x00000008)
3292
3293/*
3294 * Field : Receive FIFO Full - rff
3295 *
3296 * This Bit is used to indicate that the receive FIFO is completely full. This bit
3297 * is cleared when the Rx FIFO is no longer full.
3298 *
3299 * Field Enumeration Values:
3300 *
3301 * Enum | Value | Description
3302 * :---------------------------|:------|:-----------------------
3303 * ALT_UART_USR_RFF_E_NOTFULL | 0x0 | Receiive FIFO not full
3304 * ALT_UART_USR_RFF_E_FULL | 0x1 | Transmit FIFO is full
3305 *
3306 * Field Access Macros:
3307 *
3308 */
3309/*
3310 * Enumerated value for register field ALT_UART_USR_RFF
3311 *
3312 * Receiive FIFO not full
3313 */
3314#define ALT_UART_USR_RFF_E_NOTFULL 0x0
3315/*
3316 * Enumerated value for register field ALT_UART_USR_RFF
3317 *
3318 * Transmit FIFO is full
3319 */
3320#define ALT_UART_USR_RFF_E_FULL 0x1
3321
3322/* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFF register field. */
3323#define ALT_UART_USR_RFF_LSB 4
3324/* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFF register field. */
3325#define ALT_UART_USR_RFF_MSB 4
3326/* The width in bits of the ALT_UART_USR_RFF register field. */
3327#define ALT_UART_USR_RFF_WIDTH 1
3328/* The mask used to set the ALT_UART_USR_RFF register field value. */
3329#define ALT_UART_USR_RFF_SET_MSK 0x00000010
3330/* The mask used to clear the ALT_UART_USR_RFF register field value. */
3331#define ALT_UART_USR_RFF_CLR_MSK 0xffffffef
3332/* The reset value of the ALT_UART_USR_RFF register field. */
3333#define ALT_UART_USR_RFF_RESET 0x0
3334/* Extracts the ALT_UART_USR_RFF field value from a register. */
3335#define ALT_UART_USR_RFF_GET(value) (((value) & 0x00000010) >> 4)
3336/* Produces a ALT_UART_USR_RFF register field value suitable for setting the register. */
3337#define ALT_UART_USR_RFF_SET(value) (((value) << 4) & 0x00000010)
3338
3339#ifndef __ASSEMBLY__
3340/*
3341 * WARNING: The C register and register group struct declarations are provided for
3342 * convenience and illustrative purposes. They should, however, be used with
3343 * caution as the C language standard provides no guarantees about the alignment or
3344 * atomicity of device memory accesses. The recommended practice for writing
3345 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3346 * alt_write_word() functions.
3347 *
3348 * The struct declaration for register ALT_UART_USR.
3349 */
3350 struct ALT_UART_USR_s
3351{
3352 uint32_t : 1; /* *UNDEFINED* */
3353 const uint32_t tfnf : 1; /* Transmit FIFO Not Full */
3354 const uint32_t tfe : 1; /* Transmit FIFO Empty */
3355 const uint32_t rfne : 1; /* Receive FIFO Not Empty */
3356 const uint32_t rff : 1; /* Receive FIFO Full */
3357 uint32_t : 27; /* *UNDEFINED* */
3358};
3359
3360/* The typedef declaration for register ALT_UART_USR. */
3361typedef volatile struct ALT_UART_USR_s ALT_UART_USR_t;
3362#endif /* __ASSEMBLY__ */
3363
3364/* The byte offset of the ALT_UART_USR register from the beginning of the component. */
3365#define ALT_UART_USR_OFST 0x7c
3366/* The address of the ALT_UART_USR register. */
3367#define ALT_UART_USR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_USR_OFST))
3368
3369/*
3370 * Register : Transmit FIFO Level - tfl
3371 *
3372 * This register is used to specify the number of data entries in the Tx FIFO.
3373 * Status Bits in USR register monitor the FIFO state.
3374 *
3375 * Register Layout
3376 *
3377 * Bits | Access | Reset | Description
3378 * :-------|:-------|:------|:--------------------
3379 * [4:0] | R | 0x0 | Transmit FIFO Level
3380 * [31:5] | ??? | 0x0 | *UNDEFINED*
3381 *
3382 */
3383/*
3384 * Field : Transmit FIFO Level - tfl
3385 *
3386 * This indicates the number of data entries in the transmit FIFO.
3387 *
3388 * Field Access Macros:
3389 *
3390 */
3391/* The Least Significant Bit (LSB) position of the ALT_UART_TFL_TFL register field. */
3392#define ALT_UART_TFL_TFL_LSB 0
3393/* The Most Significant Bit (MSB) position of the ALT_UART_TFL_TFL register field. */
3394#define ALT_UART_TFL_TFL_MSB 4
3395/* The width in bits of the ALT_UART_TFL_TFL register field. */
3396#define ALT_UART_TFL_TFL_WIDTH 5
3397/* The mask used to set the ALT_UART_TFL_TFL register field value. */
3398#define ALT_UART_TFL_TFL_SET_MSK 0x0000001f
3399/* The mask used to clear the ALT_UART_TFL_TFL register field value. */
3400#define ALT_UART_TFL_TFL_CLR_MSK 0xffffffe0
3401/* The reset value of the ALT_UART_TFL_TFL register field. */
3402#define ALT_UART_TFL_TFL_RESET 0x0
3403/* Extracts the ALT_UART_TFL_TFL field value from a register. */
3404#define ALT_UART_TFL_TFL_GET(value) (((value) & 0x0000001f) >> 0)
3405/* Produces a ALT_UART_TFL_TFL register field value suitable for setting the register. */
3406#define ALT_UART_TFL_TFL_SET(value) (((value) << 0) & 0x0000001f)
3407
3408#ifndef __ASSEMBLY__
3409/*
3410 * WARNING: The C register and register group struct declarations are provided for
3411 * convenience and illustrative purposes. They should, however, be used with
3412 * caution as the C language standard provides no guarantees about the alignment or
3413 * atomicity of device memory accesses. The recommended practice for writing
3414 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3415 * alt_write_word() functions.
3416 *
3417 * The struct declaration for register ALT_UART_TFL.
3418 */
3419 struct ALT_UART_TFL_s
3420{
3421 const uint32_t tfl : 5; /* Transmit FIFO Level */
3422 uint32_t : 27; /* *UNDEFINED* */
3423};
3424
3425/* The typedef declaration for register ALT_UART_TFL. */
3426typedef volatile struct ALT_UART_TFL_s ALT_UART_TFL_t;
3427#endif /* __ASSEMBLY__ */
3428
3429/* The byte offset of the ALT_UART_TFL register from the beginning of the component. */
3430#define ALT_UART_TFL_OFST 0x80
3431/* The address of the ALT_UART_TFL register. */
3432#define ALT_UART_TFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFL_OFST))
3433
3434/*
3435 * Register : Receive FIFO Level Write - rfl
3436 *
3437 * This register is used to specify the number of data entries in the Tx FIFO.
3438 * Status Bits in USR register monitor the FIFO state.
3439 *
3440 * Register Layout
3441 *
3442 * Bits | Access | Reset | Description
3443 * :-------|:-------|:------|:--------------------------
3444 * [4:0] | R | 0x0 | Receive FIFO Level Status
3445 * [31:5] | ??? | 0x0 | *UNDEFINED*
3446 *
3447 */
3448/*
3449 * Field : Receive FIFO Level Status - rfl
3450 *
3451 * This indicates the number of data entries in the receive FIFO.
3452 *
3453 * Field Access Macros:
3454 *
3455 */
3456/* The Least Significant Bit (LSB) position of the ALT_UART_RFL_RFL register field. */
3457#define ALT_UART_RFL_RFL_LSB 0
3458/* The Most Significant Bit (MSB) position of the ALT_UART_RFL_RFL register field. */
3459#define ALT_UART_RFL_RFL_MSB 4
3460/* The width in bits of the ALT_UART_RFL_RFL register field. */
3461#define ALT_UART_RFL_RFL_WIDTH 5
3462/* The mask used to set the ALT_UART_RFL_RFL register field value. */
3463#define ALT_UART_RFL_RFL_SET_MSK 0x0000001f
3464/* The mask used to clear the ALT_UART_RFL_RFL register field value. */
3465#define ALT_UART_RFL_RFL_CLR_MSK 0xffffffe0
3466/* The reset value of the ALT_UART_RFL_RFL register field. */
3467#define ALT_UART_RFL_RFL_RESET 0x0
3468/* Extracts the ALT_UART_RFL_RFL field value from a register. */
3469#define ALT_UART_RFL_RFL_GET(value) (((value) & 0x0000001f) >> 0)
3470/* Produces a ALT_UART_RFL_RFL register field value suitable for setting the register. */
3471#define ALT_UART_RFL_RFL_SET(value) (((value) << 0) & 0x0000001f)
3472
3473#ifndef __ASSEMBLY__
3474/*
3475 * WARNING: The C register and register group struct declarations are provided for
3476 * convenience and illustrative purposes. They should, however, be used with
3477 * caution as the C language standard provides no guarantees about the alignment or
3478 * atomicity of device memory accesses. The recommended practice for writing
3479 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3480 * alt_write_word() functions.
3481 *
3482 * The struct declaration for register ALT_UART_RFL.
3483 */
3484 struct ALT_UART_RFL_s
3485{
3486 const uint32_t rfl : 5; /* Receive FIFO Level Status */
3487 uint32_t : 27; /* *UNDEFINED* */
3488};
3489
3490/* The typedef declaration for register ALT_UART_RFL. */
3491typedef volatile struct ALT_UART_RFL_s ALT_UART_RFL_t;
3492#endif /* __ASSEMBLY__ */
3493
3494/* The byte offset of the ALT_UART_RFL register from the beginning of the component. */
3495#define ALT_UART_RFL_OFST 0x84
3496/* The address of the ALT_UART_RFL register. */
3497#define ALT_UART_RFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFL_OFST))
3498
3499/*
3500 * Register : Software Reset Register - srr
3501 *
3502 * Provides Software Resets for Tx/Rx FIFO's and the uart.
3503 *
3504 * Register Layout
3505 *
3506 * Bits | Access | Reset | Description
3507 * :-------|:-------|:------|:--------------
3508 * [0] | W | 0x0 | UART Reset
3509 * [1] | W | 0x0 | Rx FIFO Reset
3510 * [2] | W | 0x0 | Tx FIFO Reset
3511 * [31:3] | ??? | 0x0 | *UNDEFINED*
3512 *
3513 */
3514/*
3515 * Field : UART Reset - ur
3516 *
3517 * This asynchronously resets the UART and synchronously removes the reset
3518 * assertion.
3519 *
3520 * Field Enumeration Values:
3521 *
3522 * Enum | Value | Description
3523 * :------------------------|:------|:--------------
3524 * ALT_UART_SRR_UR_E_NORST | 0x0 | No reset Uart
3525 * ALT_UART_SRR_UR_E_RST | 0x1 | Reset Uart
3526 *
3527 * Field Access Macros:
3528 *
3529 */
3530/*
3531 * Enumerated value for register field ALT_UART_SRR_UR
3532 *
3533 * No reset Uart
3534 */
3535#define ALT_UART_SRR_UR_E_NORST 0x0
3536/*
3537 * Enumerated value for register field ALT_UART_SRR_UR
3538 *
3539 * Reset Uart
3540 */
3541#define ALT_UART_SRR_UR_E_RST 0x1
3542
3543/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_UR register field. */
3544#define ALT_UART_SRR_UR_LSB 0
3545/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_UR register field. */
3546#define ALT_UART_SRR_UR_MSB 0
3547/* The width in bits of the ALT_UART_SRR_UR register field. */
3548#define ALT_UART_SRR_UR_WIDTH 1
3549/* The mask used to set the ALT_UART_SRR_UR register field value. */
3550#define ALT_UART_SRR_UR_SET_MSK 0x00000001
3551/* The mask used to clear the ALT_UART_SRR_UR register field value. */
3552#define ALT_UART_SRR_UR_CLR_MSK 0xfffffffe
3553/* The reset value of the ALT_UART_SRR_UR register field. */
3554#define ALT_UART_SRR_UR_RESET 0x0
3555/* Extracts the ALT_UART_SRR_UR field value from a register. */
3556#define ALT_UART_SRR_UR_GET(value) (((value) & 0x00000001) >> 0)
3557/* Produces a ALT_UART_SRR_UR register field value suitable for setting the register. */
3558#define ALT_UART_SRR_UR_SET(value) (((value) << 0) & 0x00000001)
3559
3560/*
3561 * Field : Rx FIFO Reset - rfr
3562 *
3563 * This is a shadow register for the Rx FIFO Reset bit (FCR[1]). This can be used
3564 * to remove the burden on software having to store previously written FCR values
3565 * (which are pretty static) just to reset the receive FIFO. This resets the
3566 * control portion of the receive FIFO and treats the FIFO as empty. This will also
3567 * de-assert the DMA Rx request and single signals. Note that this bit is 'self-
3568 * clearing' and it is not necessary to clear this bit.
3569 *
3570 * Field Enumeration Values:
3571 *
3572 * Enum | Value | Description
3573 * :-------------------------|:------|:-----------------
3574 * ALT_UART_SRR_RFR_E_NORST | 0x0 | No reset Rx FIFO
3575 * ALT_UART_SRR_RFR_E_RST | 0x1 | Reset Rx FIFO
3576 *
3577 * Field Access Macros:
3578 *
3579 */
3580/*
3581 * Enumerated value for register field ALT_UART_SRR_RFR
3582 *
3583 * No reset Rx FIFO
3584 */
3585#define ALT_UART_SRR_RFR_E_NORST 0x0
3586/*
3587 * Enumerated value for register field ALT_UART_SRR_RFR
3588 *
3589 * Reset Rx FIFO
3590 */
3591#define ALT_UART_SRR_RFR_E_RST 0x1
3592
3593/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_RFR register field. */
3594#define ALT_UART_SRR_RFR_LSB 1
3595/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_RFR register field. */
3596#define ALT_UART_SRR_RFR_MSB 1
3597/* The width in bits of the ALT_UART_SRR_RFR register field. */
3598#define ALT_UART_SRR_RFR_WIDTH 1
3599/* The mask used to set the ALT_UART_SRR_RFR register field value. */
3600#define ALT_UART_SRR_RFR_SET_MSK 0x00000002
3601/* The mask used to clear the ALT_UART_SRR_RFR register field value. */
3602#define ALT_UART_SRR_RFR_CLR_MSK 0xfffffffd
3603/* The reset value of the ALT_UART_SRR_RFR register field. */
3604#define ALT_UART_SRR_RFR_RESET 0x0
3605/* Extracts the ALT_UART_SRR_RFR field value from a register. */
3606#define ALT_UART_SRR_RFR_GET(value) (((value) & 0x00000002) >> 1)
3607/* Produces a ALT_UART_SRR_RFR register field value suitable for setting the register. */
3608#define ALT_UART_SRR_RFR_SET(value) (((value) << 1) & 0x00000002)
3609
3610/*
3611 * Field : Tx FIFO Reset - xfr
3612 *
3613 * This is a shadow register forthe Tx FIFO Reset bit (FCR[2]). This can be used
3614 * to remove the burden on software having to store previously written FCR values
3615 * (which are pretty static) just to reset the transmit FIFO.This resets the
3616 * control portion of the transmit FIFO and treats the FIFO as empty. This will
3617 * also de-assert the DMA Tx request and single signals.
3618 *
3619 * Field Enumeration Values:
3620 *
3621 * Enum | Value | Description
3622 * :-------------------------|:------|:-----------------
3623 * ALT_UART_SRR_XFR_E_NORST | 0x0 | No reset Tx FIFO
3624 * ALT_UART_SRR_XFR_E_RST | 0x1 | Reset Tx FIFO
3625 *
3626 * Field Access Macros:
3627 *
3628 */
3629/*
3630 * Enumerated value for register field ALT_UART_SRR_XFR
3631 *
3632 * No reset Tx FIFO
3633 */
3634#define ALT_UART_SRR_XFR_E_NORST 0x0
3635/*
3636 * Enumerated value for register field ALT_UART_SRR_XFR
3637 *
3638 * Reset Tx FIFO
3639 */
3640#define ALT_UART_SRR_XFR_E_RST 0x1
3641
3642/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_XFR register field. */
3643#define ALT_UART_SRR_XFR_LSB 2
3644/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_XFR register field. */
3645#define ALT_UART_SRR_XFR_MSB 2
3646/* The width in bits of the ALT_UART_SRR_XFR register field. */
3647#define ALT_UART_SRR_XFR_WIDTH 1
3648/* The mask used to set the ALT_UART_SRR_XFR register field value. */
3649#define ALT_UART_SRR_XFR_SET_MSK 0x00000004
3650/* The mask used to clear the ALT_UART_SRR_XFR register field value. */
3651#define ALT_UART_SRR_XFR_CLR_MSK 0xfffffffb
3652/* The reset value of the ALT_UART_SRR_XFR register field. */
3653#define ALT_UART_SRR_XFR_RESET 0x0
3654/* Extracts the ALT_UART_SRR_XFR field value from a register. */
3655#define ALT_UART_SRR_XFR_GET(value) (((value) & 0x00000004) >> 2)
3656/* Produces a ALT_UART_SRR_XFR register field value suitable for setting the register. */
3657#define ALT_UART_SRR_XFR_SET(value) (((value) << 2) & 0x00000004)
3658
3659#ifndef __ASSEMBLY__
3660/*
3661 * WARNING: The C register and register group struct declarations are provided for
3662 * convenience and illustrative purposes. They should, however, be used with
3663 * caution as the C language standard provides no guarantees about the alignment or
3664 * atomicity of device memory accesses. The recommended practice for writing
3665 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3666 * alt_write_word() functions.
3667 *
3668 * The struct declaration for register ALT_UART_SRR.
3669 */
3670 struct ALT_UART_SRR_s
3671{
3672 uint32_t ur : 1; /* UART Reset */
3673 uint32_t rfr : 1; /* Rx FIFO Reset */
3674 uint32_t xfr : 1; /* Tx FIFO Reset */
3675 uint32_t : 29; /* *UNDEFINED* */
3676};
3677
3678/* The typedef declaration for register ALT_UART_SRR. */
3679typedef volatile struct ALT_UART_SRR_s ALT_UART_SRR_t;
3680#endif /* __ASSEMBLY__ */
3681
3682/* The byte offset of the ALT_UART_SRR register from the beginning of the component. */
3683#define ALT_UART_SRR_OFST 0x88
3684/* The address of the ALT_UART_SRR register. */
3685#define ALT_UART_SRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRR_OFST))
3686
3687/*
3688 * Register : Shadow Request to Send - srts
3689 *
3690 * This is a shadow register for the RTS status (MCR[1]), this can be used to
3691 * remove the burden of having to performing a read modify write on the MCR.
3692 *
3693 * Register Layout
3694 *
3695 * Bits | Access | Reset | Description
3696 * :-------|:-------|:------|:-----------------------
3697 * [0] | RW | 0x0 | Shadow Request to Send
3698 * [31:1] | ??? | 0x0 | *UNDEFINED*
3699 *
3700 */
3701/*
3702 * Field : Shadow Request to Send - srts
3703 *
3704 * This is used to directly control the Request to Send (uart_rts_n) output. The
3705 * Request to Send (uart_rts_n) output is used to inform the modem or data set that
3706 * the UART is read to exchange data. The uart_rts_n signal is set low by
3707 * programming MCR[1] (RTS) to a high. In Auto Flow Control, (MCR[5] set to one)
3708 * and FIFO's are enabled (FCR[0] set to one), the uart_rts_n output is controlled
3709 * in the same way, but is also gated with the receiver FIFO threshold trigger
3710 * (uart_rts_n is inactive high when above the threshold).
3711 *
3712 * Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held
3713 * inactive high while the value of this location is internally looped back to an
3714 * input.
3715 *
3716 * Field Enumeration Values:
3717 *
3718 * Enum | Value | Description
3719 * :----------------------------|:------|:------------------
3720 * ALT_UART_SRTS_SRTS_E_LOGIC0 | 0x1 | uart_rts_n logic0
3721 * ALT_UART_SRTS_SRTS_E_LOGIC1 | 0x0 | uart_rts_n logic1
3722 *
3723 * Field Access Macros:
3724 *
3725 */
3726/*
3727 * Enumerated value for register field ALT_UART_SRTS_SRTS
3728 *
3729 * uart_rts_n logic0
3730 */
3731#define ALT_UART_SRTS_SRTS_E_LOGIC0 0x1
3732/*
3733 * Enumerated value for register field ALT_UART_SRTS_SRTS
3734 *
3735 * uart_rts_n logic1
3736 */
3737#define ALT_UART_SRTS_SRTS_E_LOGIC1 0x0
3738
3739/* The Least Significant Bit (LSB) position of the ALT_UART_SRTS_SRTS register field. */
3740#define ALT_UART_SRTS_SRTS_LSB 0
3741/* The Most Significant Bit (MSB) position of the ALT_UART_SRTS_SRTS register field. */
3742#define ALT_UART_SRTS_SRTS_MSB 0
3743/* The width in bits of the ALT_UART_SRTS_SRTS register field. */
3744#define ALT_UART_SRTS_SRTS_WIDTH 1
3745/* The mask used to set the ALT_UART_SRTS_SRTS register field value. */
3746#define ALT_UART_SRTS_SRTS_SET_MSK 0x00000001
3747/* The mask used to clear the ALT_UART_SRTS_SRTS register field value. */
3748#define ALT_UART_SRTS_SRTS_CLR_MSK 0xfffffffe
3749/* The reset value of the ALT_UART_SRTS_SRTS register field. */
3750#define ALT_UART_SRTS_SRTS_RESET 0x0
3751/* Extracts the ALT_UART_SRTS_SRTS field value from a register. */
3752#define ALT_UART_SRTS_SRTS_GET(value) (((value) & 0x00000001) >> 0)
3753/* Produces a ALT_UART_SRTS_SRTS register field value suitable for setting the register. */
3754#define ALT_UART_SRTS_SRTS_SET(value) (((value) << 0) & 0x00000001)
3755
3756#ifndef __ASSEMBLY__
3757/*
3758 * WARNING: The C register and register group struct declarations are provided for
3759 * convenience and illustrative purposes. They should, however, be used with
3760 * caution as the C language standard provides no guarantees about the alignment or
3761 * atomicity of device memory accesses. The recommended practice for writing
3762 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3763 * alt_write_word() functions.
3764 *
3765 * The struct declaration for register ALT_UART_SRTS.
3766 */
3767 struct ALT_UART_SRTS_s
3768{
3769 uint32_t srts : 1; /* Shadow Request to Send */
3770 uint32_t : 31; /* *UNDEFINED* */
3771};
3772
3773/* The typedef declaration for register ALT_UART_SRTS. */
3774typedef volatile struct ALT_UART_SRTS_s ALT_UART_SRTS_t;
3775#endif /* __ASSEMBLY__ */
3776
3777/* The byte offset of the ALT_UART_SRTS register from the beginning of the component. */
3778#define ALT_UART_SRTS_OFST 0x8c
3779/* The address of the ALT_UART_SRTS register. */
3780#define ALT_UART_SRTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRTS_OFST))
3781
3782/*
3783 * Register : Shadow Break Control Register - sbcr
3784 *
3785 * This is a shadow register for the Break bit [6] of the register LCR. This can be
3786 * used to remove the burden of having to performing a read modify write on the
3787 * LCR.
3788 *
3789 * Register Layout
3790 *
3791 * Bits | Access | Reset | Description
3792 * :-------|:-------|:------|:---------------------
3793 * [0] | RW | 0x0 | Shadow Break Control
3794 * [31:1] | ??? | 0x0 | *UNDEFINED*
3795 *
3796 */
3797/*
3798 * Field : Shadow Break Control - sbcr
3799 *
3800 * This is used to cause a break condition to be transmitted to the receiving
3801 * device. If set to one the serial output is forced to the spacing (logic 0)
3802 * state. When not in Loopback Mode, as determined by MCR[4], the uart_txd line is
3803 * forced low until the Break bit is cleared. When in Loopback Mode, the break
3804 * condition is internally looped back to the receiver.
3805 *
3806 * Field Enumeration Values:
3807 *
3808 * Enum | Value | Description
3809 * :--------------------------|:------|:----------------------------
3810 * ALT_UART_SBCR_SBCR_E_DISD | 0x0 | no break
3811 * ALT_UART_SBCR_SBCR_E_END | 0x1 | break serial output spacing
3812 *
3813 * Field Access Macros:
3814 *
3815 */
3816/*
3817 * Enumerated value for register field ALT_UART_SBCR_SBCR
3818 *
3819 * no break
3820 */
3821#define ALT_UART_SBCR_SBCR_E_DISD 0x0
3822/*
3823 * Enumerated value for register field ALT_UART_SBCR_SBCR
3824 *
3825 * break serial output spacing
3826 */
3827#define ALT_UART_SBCR_SBCR_E_END 0x1
3828
3829/* The Least Significant Bit (LSB) position of the ALT_UART_SBCR_SBCR register field. */
3830#define ALT_UART_SBCR_SBCR_LSB 0
3831/* The Most Significant Bit (MSB) position of the ALT_UART_SBCR_SBCR register field. */
3832#define ALT_UART_SBCR_SBCR_MSB 0
3833/* The width in bits of the ALT_UART_SBCR_SBCR register field. */
3834#define ALT_UART_SBCR_SBCR_WIDTH 1
3835/* The mask used to set the ALT_UART_SBCR_SBCR register field value. */
3836#define ALT_UART_SBCR_SBCR_SET_MSK 0x00000001
3837/* The mask used to clear the ALT_UART_SBCR_SBCR register field value. */
3838#define ALT_UART_SBCR_SBCR_CLR_MSK 0xfffffffe
3839/* The reset value of the ALT_UART_SBCR_SBCR register field. */
3840#define ALT_UART_SBCR_SBCR_RESET 0x0
3841/* Extracts the ALT_UART_SBCR_SBCR field value from a register. */
3842#define ALT_UART_SBCR_SBCR_GET(value) (((value) & 0x00000001) >> 0)
3843/* Produces a ALT_UART_SBCR_SBCR register field value suitable for setting the register. */
3844#define ALT_UART_SBCR_SBCR_SET(value) (((value) << 0) & 0x00000001)
3845
3846#ifndef __ASSEMBLY__
3847/*
3848 * WARNING: The C register and register group struct declarations are provided for
3849 * convenience and illustrative purposes. They should, however, be used with
3850 * caution as the C language standard provides no guarantees about the alignment or
3851 * atomicity of device memory accesses. The recommended practice for writing
3852 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3853 * alt_write_word() functions.
3854 *
3855 * The struct declaration for register ALT_UART_SBCR.
3856 */
3857 struct ALT_UART_SBCR_s
3858{
3859 uint32_t sbcr : 1; /* Shadow Break Control */
3860 uint32_t : 31; /* *UNDEFINED* */
3861};
3862
3863/* The typedef declaration for register ALT_UART_SBCR. */
3864typedef volatile struct ALT_UART_SBCR_s ALT_UART_SBCR_t;
3865#endif /* __ASSEMBLY__ */
3866
3867/* The byte offset of the ALT_UART_SBCR register from the beginning of the component. */
3868#define ALT_UART_SBCR_OFST 0x90
3869/* The address of the ALT_UART_SBCR register. */
3870#define ALT_UART_SBCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SBCR_OFST))
3871
3872/*
3873 * Register : Shadow DMA Mode - sdmam
3874 *
3875 * This is a shadow register for the DMA mode bit (FCR[3]).
3876 *
3877 * Register Layout
3878 *
3879 * Bits | Access | Reset | Description
3880 * :-------|:-------|:------|:----------------
3881 * [0] | RW | 0x0 | Shadow DMA Mode
3882 * [31:1] | ??? | 0x0 | *UNDEFINED*
3883 *
3884 */
3885/*
3886 * Field : Shadow DMA Mode - sdmam
3887 *
3888 * This can be used to remove the burden of having to store the previously written
3889 * value to the FCR in memory and having to mask this value so that only the DMA
3890 * Mode bit gets updated.
3891 *
3892 * Field Enumeration Values:
3893 *
3894 * Enum | Value | Description
3895 * :------------------------------|:------|:---------------------------
3896 * ALT_UART_SDMAM_SDMAM_E_SINGLE | 0x0 | Single DMA Transfer Mode
3897 * ALT_UART_SDMAM_SDMAM_E_MULT | 0x1 | Multiple DMA Transfer Mode
3898 *
3899 * Field Access Macros:
3900 *
3901 */
3902/*
3903 * Enumerated value for register field ALT_UART_SDMAM_SDMAM
3904 *
3905 * Single DMA Transfer Mode
3906 */
3907#define ALT_UART_SDMAM_SDMAM_E_SINGLE 0x0
3908/*
3909 * Enumerated value for register field ALT_UART_SDMAM_SDMAM
3910 *
3911 * Multiple DMA Transfer Mode
3912 */
3913#define ALT_UART_SDMAM_SDMAM_E_MULT 0x1
3914
3915/* The Least Significant Bit (LSB) position of the ALT_UART_SDMAM_SDMAM register field. */
3916#define ALT_UART_SDMAM_SDMAM_LSB 0
3917/* The Most Significant Bit (MSB) position of the ALT_UART_SDMAM_SDMAM register field. */
3918#define ALT_UART_SDMAM_SDMAM_MSB 0
3919/* The width in bits of the ALT_UART_SDMAM_SDMAM register field. */
3920#define ALT_UART_SDMAM_SDMAM_WIDTH 1
3921/* The mask used to set the ALT_UART_SDMAM_SDMAM register field value. */
3922#define ALT_UART_SDMAM_SDMAM_SET_MSK 0x00000001
3923/* The mask used to clear the ALT_UART_SDMAM_SDMAM register field value. */
3924#define ALT_UART_SDMAM_SDMAM_CLR_MSK 0xfffffffe
3925/* The reset value of the ALT_UART_SDMAM_SDMAM register field. */
3926#define ALT_UART_SDMAM_SDMAM_RESET 0x0
3927/* Extracts the ALT_UART_SDMAM_SDMAM field value from a register. */
3928#define ALT_UART_SDMAM_SDMAM_GET(value) (((value) & 0x00000001) >> 0)
3929/* Produces a ALT_UART_SDMAM_SDMAM register field value suitable for setting the register. */
3930#define ALT_UART_SDMAM_SDMAM_SET(value) (((value) << 0) & 0x00000001)
3931
3932#ifndef __ASSEMBLY__
3933/*
3934 * WARNING: The C register and register group struct declarations are provided for
3935 * convenience and illustrative purposes. They should, however, be used with
3936 * caution as the C language standard provides no guarantees about the alignment or
3937 * atomicity of device memory accesses. The recommended practice for writing
3938 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3939 * alt_write_word() functions.
3940 *
3941 * The struct declaration for register ALT_UART_SDMAM.
3942 */
3943 struct ALT_UART_SDMAM_s
3944{
3945 uint32_t sdmam : 1; /* Shadow DMA Mode */
3946 uint32_t : 31; /* *UNDEFINED* */
3947};
3948
3949/* The typedef declaration for register ALT_UART_SDMAM. */
3950typedef volatile struct ALT_UART_SDMAM_s ALT_UART_SDMAM_t;
3951#endif /* __ASSEMBLY__ */
3952
3953/* The byte offset of the ALT_UART_SDMAM register from the beginning of the component. */
3954#define ALT_UART_SDMAM_OFST 0x94
3955/* The address of the ALT_UART_SDMAM register. */
3956#define ALT_UART_SDMAM_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SDMAM_OFST))
3957
3958/*
3959 * Register : Shadow FIFO Enable - sfe
3960 *
3961 * This is a shadow register for the FIFO enable bit [0] of register FCR.
3962 *
3963 * Register Layout
3964 *
3965 * Bits | Access | Reset | Description
3966 * :-------|:-------|:------|:-------------------
3967 * [0] | RW | 0x0 | Shadow FIFO Enable
3968 * [31:1] | ??? | 0x0 | *UNDEFINED*
3969 *
3970 */
3971/*
3972 * Field : Shadow FIFO Enable - sfe
3973 *
3974 * This can be used to remove the burden of having to store the previously written
3975 * value to the FCR in memory and having to mask this value so that only the FIFO
3976 * enable bit gets updated. This enables/disables the transmit (Tx) and receive (Rx
3977 * ) FIFO's. If this bit is set to zero (disabled) after being enabled then both
3978 * the Tx and Rx controller portion of FIFO's will be reset.
3979 *
3980 * Field Enumeration Values:
3981 *
3982 * Enum | Value | Description
3983 * :------------------------|:------|:--------------
3984 * ALT_UART_SFE_SFE_E_DISD | 0x0 | Disable Rx/Tx
3985 * ALT_UART_SFE_SFE_E_END | 0x1 | Enable Rx/Tx
3986 *
3987 * Field Access Macros:
3988 *
3989 */
3990/*
3991 * Enumerated value for register field ALT_UART_SFE_SFE
3992 *
3993 * Disable Rx/Tx
3994 */
3995#define ALT_UART_SFE_SFE_E_DISD 0x0
3996/*
3997 * Enumerated value for register field ALT_UART_SFE_SFE
3998 *
3999 * Enable Rx/Tx
4000 */
4001#define ALT_UART_SFE_SFE_E_END 0x1
4002
4003/* The Least Significant Bit (LSB) position of the ALT_UART_SFE_SFE register field. */
4004#define ALT_UART_SFE_SFE_LSB 0
4005/* The Most Significant Bit (MSB) position of the ALT_UART_SFE_SFE register field. */
4006#define ALT_UART_SFE_SFE_MSB 0
4007/* The width in bits of the ALT_UART_SFE_SFE register field. */
4008#define ALT_UART_SFE_SFE_WIDTH 1
4009/* The mask used to set the ALT_UART_SFE_SFE register field value. */
4010#define ALT_UART_SFE_SFE_SET_MSK 0x00000001
4011/* The mask used to clear the ALT_UART_SFE_SFE register field value. */
4012#define ALT_UART_SFE_SFE_CLR_MSK 0xfffffffe
4013/* The reset value of the ALT_UART_SFE_SFE register field. */
4014#define ALT_UART_SFE_SFE_RESET 0x0
4015/* Extracts the ALT_UART_SFE_SFE field value from a register. */
4016#define ALT_UART_SFE_SFE_GET(value) (((value) & 0x00000001) >> 0)
4017/* Produces a ALT_UART_SFE_SFE register field value suitable for setting the register. */
4018#define ALT_UART_SFE_SFE_SET(value) (((value) << 0) & 0x00000001)
4019
4020#ifndef __ASSEMBLY__
4021/*
4022 * WARNING: The C register and register group struct declarations are provided for
4023 * convenience and illustrative purposes. They should, however, be used with
4024 * caution as the C language standard provides no guarantees about the alignment or
4025 * atomicity of device memory accesses. The recommended practice for writing
4026 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4027 * alt_write_word() functions.
4028 *
4029 * The struct declaration for register ALT_UART_SFE.
4030 */
4031 struct ALT_UART_SFE_s
4032{
4033 uint32_t sfe : 1; /* Shadow FIFO Enable */
4034 uint32_t : 31; /* *UNDEFINED* */
4035};
4036
4037/* The typedef declaration for register ALT_UART_SFE. */
4038typedef volatile struct ALT_UART_SFE_s ALT_UART_SFE_t;
4039#endif /* __ASSEMBLY__ */
4040
4041/* The byte offset of the ALT_UART_SFE register from the beginning of the component. */
4042#define ALT_UART_SFE_OFST 0x98
4043/* The address of the ALT_UART_SFE register. */
4044#define ALT_UART_SFE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SFE_OFST))
4045
4046/*
4047 * Register : Shadow Rx Trigger - srt
4048 *
4049 * This is a shadow register for the Rx trigger bits (FCR[7:6]).
4050 *
4051 * Register Layout
4052 *
4053 * Bits | Access | Reset | Description
4054 * :-------|:-------|:------|:------------------------
4055 * [1:0] | RW | 0x0 | Shadow Rx Trigger Bits
4056 * [31:2] | ??? | 0x0 | *UNDEFINED*
4057 *
4058 */
4059/*
4060 * Field : Shadow Rx Trigger Bits - srt
4061 *
4062 * This can be used to remove the burden of having to store the previously written
4063 * value to the FCR in memory and having to mask this value so that only the Rx
4064 * trigger bit gets updated. This is used to select the trigger level in the
4065 * receiver FIFO at which the Received Data Available Interrupt will be generated.
4066 * It also determines when the uart_dma_rx_req_n signal will be asserted when DMA
4067 * Mode (FCR[3]) is set to one. The enum below shows trigger levels that are
4068 * supported.
4069 *
4070 * Field Enumeration Values:
4071 *
4072 * Enum | Value | Description
4073 * :-------------------------------|:------|:----------------------
4074 * ALT_UART_SRT_SRT_E_ONECHAR | 0x0 | one character in fifo
4075 * ALT_UART_SRT_SRT_E_QUARTERFULL | 0x1 | FIFO 1/4 full
4076 * ALT_UART_SRT_SRT_E_HALFFULL | 0x2 | FIFO 1/2 full
4077 * ALT_UART_SRT_SRT_E_FULLLESS2 | 0x3 | FIFO 2 less than full
4078 *
4079 * Field Access Macros:
4080 *
4081 */
4082/*
4083 * Enumerated value for register field ALT_UART_SRT_SRT
4084 *
4085 * one character in fifo
4086 */
4087#define ALT_UART_SRT_SRT_E_ONECHAR 0x0
4088/*
4089 * Enumerated value for register field ALT_UART_SRT_SRT
4090 *
4091 * FIFO 1/4 full
4092 */
4093#define ALT_UART_SRT_SRT_E_QUARTERFULL 0x1
4094/*
4095 * Enumerated value for register field ALT_UART_SRT_SRT
4096 *
4097 * FIFO 1/2 full
4098 */
4099#define ALT_UART_SRT_SRT_E_HALFFULL 0x2
4100/*
4101 * Enumerated value for register field ALT_UART_SRT_SRT
4102 *
4103 * FIFO 2 less than full
4104 */
4105#define ALT_UART_SRT_SRT_E_FULLLESS2 0x3
4106
4107/* The Least Significant Bit (LSB) position of the ALT_UART_SRT_SRT register field. */
4108#define ALT_UART_SRT_SRT_LSB 0
4109/* The Most Significant Bit (MSB) position of the ALT_UART_SRT_SRT register field. */
4110#define ALT_UART_SRT_SRT_MSB 1
4111/* The width in bits of the ALT_UART_SRT_SRT register field. */
4112#define ALT_UART_SRT_SRT_WIDTH 2
4113/* The mask used to set the ALT_UART_SRT_SRT register field value. */
4114#define ALT_UART_SRT_SRT_SET_MSK 0x00000003
4115/* The mask used to clear the ALT_UART_SRT_SRT register field value. */
4116#define ALT_UART_SRT_SRT_CLR_MSK 0xfffffffc
4117/* The reset value of the ALT_UART_SRT_SRT register field. */
4118#define ALT_UART_SRT_SRT_RESET 0x0
4119/* Extracts the ALT_UART_SRT_SRT field value from a register. */
4120#define ALT_UART_SRT_SRT_GET(value) (((value) & 0x00000003) >> 0)
4121/* Produces a ALT_UART_SRT_SRT register field value suitable for setting the register. */
4122#define ALT_UART_SRT_SRT_SET(value) (((value) << 0) & 0x00000003)
4123
4124#ifndef __ASSEMBLY__
4125/*
4126 * WARNING: The C register and register group struct declarations are provided for
4127 * convenience and illustrative purposes. They should, however, be used with
4128 * caution as the C language standard provides no guarantees about the alignment or
4129 * atomicity of device memory accesses. The recommended practice for writing
4130 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4131 * alt_write_word() functions.
4132 *
4133 * The struct declaration for register ALT_UART_SRT.
4134 */
4135 struct ALT_UART_SRT_s
4136{
4137 uint32_t srt : 2; /* Shadow Rx Trigger Bits */
4138 uint32_t : 30; /* *UNDEFINED* */
4139};
4140
4141/* The typedef declaration for register ALT_UART_SRT. */
4142typedef volatile struct ALT_UART_SRT_s ALT_UART_SRT_t;
4143#endif /* __ASSEMBLY__ */
4144
4145/* The byte offset of the ALT_UART_SRT register from the beginning of the component. */
4146#define ALT_UART_SRT_OFST 0x9c
4147/* The address of the ALT_UART_SRT register. */
4148#define ALT_UART_SRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRT_OFST))
4149
4150/*
4151 * Register : Shadow Tx Empty Trigger - stet
4152 *
4153 * This is a shadow register for the Tx empty trigger bits (FCR[5:4]).
4154 *
4155 * Register Layout
4156 *
4157 * Bits | Access | Reset | Description
4158 * :-------|:-------|:------|:-----------------------------
4159 * [1:0] | RW | 0x0 | Shadow Tx Empty Trigger Bits
4160 * [31:2] | ??? | 0x0 | *UNDEFINED*
4161 *
4162 */
4163/*
4164 * Field : Shadow Tx Empty Trigger Bits - stet
4165 *
4166 * This can be used to remove the burden of having to store the previously written
4167 * value to the FCR in memory and having to mask this value so that only the Tx
4168 * empty trigger bit gets updated. This is used to select the empty threshold level
4169 * at which the THRE Interrupts will be generated when the mode is active. These
4170 * threshold levels are also described in. The enum trigger levels are supported.
4171 *
4172 * Field Enumeration Values:
4173 *
4174 * Enum | Value | Description
4175 * :---------------------------------|:------|:-----------------------
4176 * ALT_UART_STET_STET_E_FIFOEMPTY | 0x0 | FIFO empty
4177 * ALT_UART_STET_STET_E_TWOCHARS | 0x1 | Two characters in FIFO
4178 * ALT_UART_STET_STET_E_QUARTERFULL | 0x2 | FIFO quarter full
4179 * ALT_UART_STET_STET_E_HALFFULL | 0x3 | FIFO half full
4180 *
4181 * Field Access Macros:
4182 *
4183 */
4184/*
4185 * Enumerated value for register field ALT_UART_STET_STET
4186 *
4187 * FIFO empty
4188 */
4189#define ALT_UART_STET_STET_E_FIFOEMPTY 0x0
4190/*
4191 * Enumerated value for register field ALT_UART_STET_STET
4192 *
4193 * Two characters in FIFO
4194 */
4195#define ALT_UART_STET_STET_E_TWOCHARS 0x1
4196/*
4197 * Enumerated value for register field ALT_UART_STET_STET
4198 *
4199 * FIFO quarter full
4200 */
4201#define ALT_UART_STET_STET_E_QUARTERFULL 0x2
4202/*
4203 * Enumerated value for register field ALT_UART_STET_STET
4204 *
4205 * FIFO half full
4206 */
4207#define ALT_UART_STET_STET_E_HALFFULL 0x3
4208
4209/* The Least Significant Bit (LSB) position of the ALT_UART_STET_STET register field. */
4210#define ALT_UART_STET_STET_LSB 0
4211/* The Most Significant Bit (MSB) position of the ALT_UART_STET_STET register field. */
4212#define ALT_UART_STET_STET_MSB 1
4213/* The width in bits of the ALT_UART_STET_STET register field. */
4214#define ALT_UART_STET_STET_WIDTH 2
4215/* The mask used to set the ALT_UART_STET_STET register field value. */
4216#define ALT_UART_STET_STET_SET_MSK 0x00000003
4217/* The mask used to clear the ALT_UART_STET_STET register field value. */
4218#define ALT_UART_STET_STET_CLR_MSK 0xfffffffc
4219/* The reset value of the ALT_UART_STET_STET register field. */
4220#define ALT_UART_STET_STET_RESET 0x0
4221/* Extracts the ALT_UART_STET_STET field value from a register. */
4222#define ALT_UART_STET_STET_GET(value) (((value) & 0x00000003) >> 0)
4223/* Produces a ALT_UART_STET_STET register field value suitable for setting the register. */
4224#define ALT_UART_STET_STET_SET(value) (((value) << 0) & 0x00000003)
4225
4226#ifndef __ASSEMBLY__
4227/*
4228 * WARNING: The C register and register group struct declarations are provided for
4229 * convenience and illustrative purposes. They should, however, be used with
4230 * caution as the C language standard provides no guarantees about the alignment or
4231 * atomicity of device memory accesses. The recommended practice for writing
4232 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4233 * alt_write_word() functions.
4234 *
4235 * The struct declaration for register ALT_UART_STET.
4236 */
4237 struct ALT_UART_STET_s
4238{
4239 uint32_t stet : 2; /* Shadow Tx Empty Trigger Bits */
4240 uint32_t : 30; /* *UNDEFINED* */
4241};
4242
4243/* The typedef declaration for register ALT_UART_STET. */
4244typedef volatile struct ALT_UART_STET_s ALT_UART_STET_t;
4245#endif /* __ASSEMBLY__ */
4246
4247/* The byte offset of the ALT_UART_STET register from the beginning of the component. */
4248#define ALT_UART_STET_OFST 0xa0
4249/* The address of the ALT_UART_STET register. */
4250#define ALT_UART_STET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STET_OFST))
4251
4252/*
4253 * Register : Halt Tx - htx
4254 *
4255 * Used to halt transmission for testing.
4256 *
4257 * Register Layout
4258 *
4259 * Bits | Access | Reset | Description
4260 * :-------|:-------|:------|:-------------
4261 * [0] | RW | 0x0 | Halt Tx Bits
4262 * [31:1] | ??? | 0x0 | *UNDEFINED*
4263 *
4264 */
4265/*
4266 * Field : Halt Tx Bits - htx
4267 *
4268 * This register is use to halt transmissions for testing, so that the transmit
4269 * FIFO can be filled by the master when FIFO's are enabled.
4270 *
4271 * Note, if FIFO's are not enabled, the setting of the halt Tx register will have
4272 * no effect on operation.
4273 *
4274 * Field Enumeration Values:
4275 *
4276 * Enum | Value | Description
4277 * :------------------------|:------|:-----------------
4278 * ALT_UART_HTX_HTX_E_DISD | 0x0 | Halt Tx disabled
4279 * ALT_UART_HTX_HTX_E_END | 0x1 | Halt Tx enabled
4280 *
4281 * Field Access Macros:
4282 *
4283 */
4284/*
4285 * Enumerated value for register field ALT_UART_HTX_HTX
4286 *
4287 * Halt Tx disabled
4288 */
4289#define ALT_UART_HTX_HTX_E_DISD 0x0
4290/*
4291 * Enumerated value for register field ALT_UART_HTX_HTX
4292 *
4293 * Halt Tx enabled
4294 */
4295#define ALT_UART_HTX_HTX_E_END 0x1
4296
4297/* The Least Significant Bit (LSB) position of the ALT_UART_HTX_HTX register field. */
4298#define ALT_UART_HTX_HTX_LSB 0
4299/* The Most Significant Bit (MSB) position of the ALT_UART_HTX_HTX register field. */
4300#define ALT_UART_HTX_HTX_MSB 0
4301/* The width in bits of the ALT_UART_HTX_HTX register field. */
4302#define ALT_UART_HTX_HTX_WIDTH 1
4303/* The mask used to set the ALT_UART_HTX_HTX register field value. */
4304#define ALT_UART_HTX_HTX_SET_MSK 0x00000001
4305/* The mask used to clear the ALT_UART_HTX_HTX register field value. */
4306#define ALT_UART_HTX_HTX_CLR_MSK 0xfffffffe
4307/* The reset value of the ALT_UART_HTX_HTX register field. */
4308#define ALT_UART_HTX_HTX_RESET 0x0
4309/* Extracts the ALT_UART_HTX_HTX field value from a register. */
4310#define ALT_UART_HTX_HTX_GET(value) (((value) & 0x00000001) >> 0)
4311/* Produces a ALT_UART_HTX_HTX register field value suitable for setting the register. */
4312#define ALT_UART_HTX_HTX_SET(value) (((value) << 0) & 0x00000001)
4313
4314#ifndef __ASSEMBLY__
4315/*
4316 * WARNING: The C register and register group struct declarations are provided for
4317 * convenience and illustrative purposes. They should, however, be used with
4318 * caution as the C language standard provides no guarantees about the alignment or
4319 * atomicity of device memory accesses. The recommended practice for writing
4320 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4321 * alt_write_word() functions.
4322 *
4323 * The struct declaration for register ALT_UART_HTX.
4324 */
4325 struct ALT_UART_HTX_s
4326{
4327 uint32_t htx : 1; /* Halt Tx Bits */
4328 uint32_t : 31; /* *UNDEFINED* */
4329};
4330
4331/* The typedef declaration for register ALT_UART_HTX. */
4332typedef volatile struct ALT_UART_HTX_s ALT_UART_HTX_t;
4333#endif /* __ASSEMBLY__ */
4334
4335/* The byte offset of the ALT_UART_HTX register from the beginning of the component. */
4336#define ALT_UART_HTX_OFST 0xa4
4337/* The address of the ALT_UART_HTX register. */
4338#define ALT_UART_HTX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_HTX_OFST))
4339
4340/*
4341 * Register : DMA Software Acknowledge - dmasa
4342 *
4343 * DMA Operation Control
4344 *
4345 * Register Layout
4346 *
4347 * Bits | Access | Reset | Description
4348 * :-------|:-------|:------|:------------------------------
4349 * [0] | W | 0x0 | DMA Software Acknowledge Bits
4350 * [31:1] | ??? | 0x0 | *UNDEFINED*
4351 *
4352 */
4353/*
4354 * Field : DMA Software Acknowledge Bits - dmasa
4355 *
4356 * This register is used to perform DMA software acknowledge if a transfer needs to
4357 * be terminated due to an error condition. For example, if the DMA disables the
4358 * channel, then the uart should clear its request. This will cause the Tx request,
4359 * Tx single, Rx request and Rx single signals to de-assert. Note that this bit is
4360 * 'self-clearing' and it is not necessary to clear this bit.
4361 *
4362 * Field Access Macros:
4363 *
4364 */
4365/* The Least Significant Bit (LSB) position of the ALT_UART_DMASA_DMASA register field. */
4366#define ALT_UART_DMASA_DMASA_LSB 0
4367/* The Most Significant Bit (MSB) position of the ALT_UART_DMASA_DMASA register field. */
4368#define ALT_UART_DMASA_DMASA_MSB 0
4369/* The width in bits of the ALT_UART_DMASA_DMASA register field. */
4370#define ALT_UART_DMASA_DMASA_WIDTH 1
4371/* The mask used to set the ALT_UART_DMASA_DMASA register field value. */
4372#define ALT_UART_DMASA_DMASA_SET_MSK 0x00000001
4373/* The mask used to clear the ALT_UART_DMASA_DMASA register field value. */
4374#define ALT_UART_DMASA_DMASA_CLR_MSK 0xfffffffe
4375/* The reset value of the ALT_UART_DMASA_DMASA register field. */
4376#define ALT_UART_DMASA_DMASA_RESET 0x0
4377/* Extracts the ALT_UART_DMASA_DMASA field value from a register. */
4378#define ALT_UART_DMASA_DMASA_GET(value) (((value) & 0x00000001) >> 0)
4379/* Produces a ALT_UART_DMASA_DMASA register field value suitable for setting the register. */
4380#define ALT_UART_DMASA_DMASA_SET(value) (((value) << 0) & 0x00000001)
4381
4382#ifndef __ASSEMBLY__
4383/*
4384 * WARNING: The C register and register group struct declarations are provided for
4385 * convenience and illustrative purposes. They should, however, be used with
4386 * caution as the C language standard provides no guarantees about the alignment or
4387 * atomicity of device memory accesses. The recommended practice for writing
4388 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4389 * alt_write_word() functions.
4390 *
4391 * The struct declaration for register ALT_UART_DMASA.
4392 */
4393 struct ALT_UART_DMASA_s
4394{
4395 uint32_t dmasa : 1; /* DMA Software Acknowledge Bits */
4396 uint32_t : 31; /* *UNDEFINED* */
4397};
4398
4399/* The typedef declaration for register ALT_UART_DMASA. */
4400typedef volatile struct ALT_UART_DMASA_s ALT_UART_DMASA_t;
4401#endif /* __ASSEMBLY__ */
4402
4403/* The byte offset of the ALT_UART_DMASA register from the beginning of the component. */
4404#define ALT_UART_DMASA_OFST 0xa8
4405/* The address of the ALT_UART_DMASA register. */
4406#define ALT_UART_DMASA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_DMASA_OFST))
4407
4408/*
4409 * Register : Component Parameter Register - cpr
4410 *
4411 * Describes various fixed hardware setups states.
4412 *
4413 * Register Layout
4414 *
4415 * Bits | Access | Reset | Description
4416 * :--------|:-------|:------|:----------------------------------
4417 * [1:0] | R | 0x2 | APB DATA WIDTH
4418 * [3:2] | ??? | 0x0 | *UNDEFINED*
4419 * [4] | R | 0x1 | Auto Flow Control
4420 * [5] | R | 0x1 | THRE MODE
4421 * [6] | R | 0x0 | SIR MODE Unsupported
4422 * [7] | R | 0x0 | SIR LP MODE Unsupported
4423 * [8] | R | 0x1 | ADDITIONAL FEATURES Supported
4424 * [9] | R | 0x1 | FIFO ACCESS Supported
4425 * [10] | R | 0x1 | FIFO STAT Supported
4426 * [11] | R | 0x1 | SHADOW Supported
4427 * [12] | R | 0x1 | Configuartion ID Register Present
4428 * [13] | R | 0x1 | DMA EXTRA Supported
4429 * [15:14] | ??? | 0x0 | *UNDEFINED*
4430 * [23:16] | R | 0x37 | FIFO Depth
4431 * [31:24] | ??? | 0x0 | *UNDEFINED*
4432 *
4433 */
4434/*
4435 * Field : APB DATA WIDTH - apbdatawidth
4436 *
4437 * Fixed to support an ABP data bus width of 32-bits.
4438 *
4439 * Field Enumeration Values:
4440 *
4441 * Enum | Value | Description
4442 * :----------------------------------------|:------|:-------------------------
4443 * ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits
4444 *
4445 * Field Access Macros:
4446 *
4447 */
4448/*
4449 * Enumerated value for register field ALT_UART_CPR_APBDATAWIDTH
4450 *
4451 * APB Data Width = 32-bits
4452 */
4453#define ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS 0x2
4454
4455/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */
4456#define ALT_UART_CPR_APBDATAWIDTH_LSB 0
4457/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */
4458#define ALT_UART_CPR_APBDATAWIDTH_MSB 1
4459/* The width in bits of the ALT_UART_CPR_APBDATAWIDTH register field. */
4460#define ALT_UART_CPR_APBDATAWIDTH_WIDTH 2
4461/* The mask used to set the ALT_UART_CPR_APBDATAWIDTH register field value. */
4462#define ALT_UART_CPR_APBDATAWIDTH_SET_MSK 0x00000003
4463/* The mask used to clear the ALT_UART_CPR_APBDATAWIDTH register field value. */
4464#define ALT_UART_CPR_APBDATAWIDTH_CLR_MSK 0xfffffffc
4465/* The reset value of the ALT_UART_CPR_APBDATAWIDTH register field. */
4466#define ALT_UART_CPR_APBDATAWIDTH_RESET 0x2
4467/* Extracts the ALT_UART_CPR_APBDATAWIDTH field value from a register. */
4468#define ALT_UART_CPR_APBDATAWIDTH_GET(value) (((value) & 0x00000003) >> 0)
4469/* Produces a ALT_UART_CPR_APBDATAWIDTH register field value suitable for setting the register. */
4470#define ALT_UART_CPR_APBDATAWIDTH_SET(value) (((value) << 0) & 0x00000003)
4471
4472/*
4473 * Field : Auto Flow Control - afce_mode
4474 *
4475 * Allows auto flow control.
4476 *
4477 * Field Enumeration Values:
4478 *
4479 * Enum | Value | Description
4480 * :----------------------------|:------|:------------
4481 * ALT_UART_CPR_AFCE_MOD_E_END | 0x1 | Auto Flow
4482 *
4483 * Field Access Macros:
4484 *
4485 */
4486/*
4487 * Enumerated value for register field ALT_UART_CPR_AFCE_MOD
4488 *
4489 * Auto Flow
4490 */
4491#define ALT_UART_CPR_AFCE_MOD_E_END 0x1
4492
4493/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_AFCE_MOD register field. */
4494#define ALT_UART_CPR_AFCE_MOD_LSB 4
4495/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_AFCE_MOD register field. */
4496#define ALT_UART_CPR_AFCE_MOD_MSB 4
4497/* The width in bits of the ALT_UART_CPR_AFCE_MOD register field. */
4498#define ALT_UART_CPR_AFCE_MOD_WIDTH 1
4499/* The mask used to set the ALT_UART_CPR_AFCE_MOD register field value. */
4500#define ALT_UART_CPR_AFCE_MOD_SET_MSK 0x00000010
4501/* The mask used to clear the ALT_UART_CPR_AFCE_MOD register field value. */
4502#define ALT_UART_CPR_AFCE_MOD_CLR_MSK 0xffffffef
4503/* The reset value of the ALT_UART_CPR_AFCE_MOD register field. */
4504#define ALT_UART_CPR_AFCE_MOD_RESET 0x1
4505/* Extracts the ALT_UART_CPR_AFCE_MOD field value from a register. */
4506#define ALT_UART_CPR_AFCE_MOD_GET(value) (((value) & 0x00000010) >> 4)
4507/* Produces a ALT_UART_CPR_AFCE_MOD register field value suitable for setting the register. */
4508#define ALT_UART_CPR_AFCE_MOD_SET(value) (((value) << 4) & 0x00000010)
4509
4510/*
4511 * Field : THRE MODE - thre_mode
4512 *
4513 * Programmable Transmitter Hold Register Empty interrupt
4514 *
4515 * Field Enumeration Values:
4516 *
4517 * Enum | Value | Description
4518 * :----------------------------|:------|:------------------------------------------
4519 * ALT_UART_CPR_THRE_MOD_E_END | 0x1 | Programmable Tx Hold Reg. Empty interrupt
4520 * : | | present
4521 *
4522 * Field Access Macros:
4523 *
4524 */
4525/*
4526 * Enumerated value for register field ALT_UART_CPR_THRE_MOD
4527 *
4528 * Programmable Tx Hold Reg. Empty interrupt present
4529 */
4530#define ALT_UART_CPR_THRE_MOD_E_END 0x1
4531
4532/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_THRE_MOD register field. */
4533#define ALT_UART_CPR_THRE_MOD_LSB 5
4534/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_THRE_MOD register field. */
4535#define ALT_UART_CPR_THRE_MOD_MSB 5
4536/* The width in bits of the ALT_UART_CPR_THRE_MOD register field. */
4537#define ALT_UART_CPR_THRE_MOD_WIDTH 1
4538/* The mask used to set the ALT_UART_CPR_THRE_MOD register field value. */
4539#define ALT_UART_CPR_THRE_MOD_SET_MSK 0x00000020
4540/* The mask used to clear the ALT_UART_CPR_THRE_MOD register field value. */
4541#define ALT_UART_CPR_THRE_MOD_CLR_MSK 0xffffffdf
4542/* The reset value of the ALT_UART_CPR_THRE_MOD register field. */
4543#define ALT_UART_CPR_THRE_MOD_RESET 0x1
4544/* Extracts the ALT_UART_CPR_THRE_MOD field value from a register. */
4545#define ALT_UART_CPR_THRE_MOD_GET(value) (((value) & 0x00000020) >> 5)
4546/* Produces a ALT_UART_CPR_THRE_MOD register field value suitable for setting the register. */
4547#define ALT_UART_CPR_THRE_MOD_SET(value) (((value) << 5) & 0x00000020)
4548
4549/*
4550 * Field : SIR MODE Unsupported - sir_mode
4551 *
4552 * Sir mode not used in this application.
4553 *
4554 * Field Enumeration Values:
4555 *
4556 * Enum | Value | Description
4557 * :----------------------------|:------|:-----------------------
4558 * ALT_UART_CPR_SIR_MOD_E_DISD | 0x0 | Sir Mode Not Supported
4559 *
4560 * Field Access Macros:
4561 *
4562 */
4563/*
4564 * Enumerated value for register field ALT_UART_CPR_SIR_MOD
4565 *
4566 * Sir Mode Not Supported
4567 */
4568#define ALT_UART_CPR_SIR_MOD_E_DISD 0x0
4569
4570/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_MOD register field. */
4571#define ALT_UART_CPR_SIR_MOD_LSB 6
4572/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_MOD register field. */
4573#define ALT_UART_CPR_SIR_MOD_MSB 6
4574/* The width in bits of the ALT_UART_CPR_SIR_MOD register field. */
4575#define ALT_UART_CPR_SIR_MOD_WIDTH 1
4576/* The mask used to set the ALT_UART_CPR_SIR_MOD register field value. */
4577#define ALT_UART_CPR_SIR_MOD_SET_MSK 0x00000040
4578/* The mask used to clear the ALT_UART_CPR_SIR_MOD register field value. */
4579#define ALT_UART_CPR_SIR_MOD_CLR_MSK 0xffffffbf
4580/* The reset value of the ALT_UART_CPR_SIR_MOD register field. */
4581#define ALT_UART_CPR_SIR_MOD_RESET 0x0
4582/* Extracts the ALT_UART_CPR_SIR_MOD field value from a register. */
4583#define ALT_UART_CPR_SIR_MOD_GET(value) (((value) & 0x00000040) >> 6)
4584/* Produces a ALT_UART_CPR_SIR_MOD register field value suitable for setting the register. */
4585#define ALT_UART_CPR_SIR_MOD_SET(value) (((value) << 6) & 0x00000040)
4586
4587/*
4588 * Field : SIR LP MODE Unsupported - sir_lp_mode
4589 *
4590 * LP Sir Mode not used in this application.
4591 *
4592 * Field Enumeration Values:
4593 *
4594 * Enum | Value | Description
4595 * :-------------------------------|:------|:--------------------------
4596 * ALT_UART_CPR_SIR_LP_MOD_E_DISD | 0x0 | LP Sir Mode Not Supported
4597 *
4598 * Field Access Macros:
4599 *
4600 */
4601/*
4602 * Enumerated value for register field ALT_UART_CPR_SIR_LP_MOD
4603 *
4604 * LP Sir Mode Not Supported
4605 */
4606#define ALT_UART_CPR_SIR_LP_MOD_E_DISD 0x0
4607
4608/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */
4609#define ALT_UART_CPR_SIR_LP_MOD_LSB 7
4610/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */
4611#define ALT_UART_CPR_SIR_LP_MOD_MSB 7
4612/* The width in bits of the ALT_UART_CPR_SIR_LP_MOD register field. */
4613#define ALT_UART_CPR_SIR_LP_MOD_WIDTH 1
4614/* The mask used to set the ALT_UART_CPR_SIR_LP_MOD register field value. */
4615#define ALT_UART_CPR_SIR_LP_MOD_SET_MSK 0x00000080
4616/* The mask used to clear the ALT_UART_CPR_SIR_LP_MOD register field value. */
4617#define ALT_UART_CPR_SIR_LP_MOD_CLR_MSK 0xffffff7f
4618/* The reset value of the ALT_UART_CPR_SIR_LP_MOD register field. */
4619#define ALT_UART_CPR_SIR_LP_MOD_RESET 0x0
4620/* Extracts the ALT_UART_CPR_SIR_LP_MOD field value from a register. */
4621#define ALT_UART_CPR_SIR_LP_MOD_GET(value) (((value) & 0x00000080) >> 7)
4622/* Produces a ALT_UART_CPR_SIR_LP_MOD register field value suitable for setting the register. */
4623#define ALT_UART_CPR_SIR_LP_MOD_SET(value) (((value) << 7) & 0x00000080)
4624
4625/*
4626 * Field : ADDITIONAL FEATURES Supported - additional_feat
4627 *
4628 * Configures the uart to include fifo status register, shadow registers and
4629 * encoded parameter register.
4630 *
4631 * Field Enumeration Values:
4632 *
4633 * Enum | Value | Description
4634 * :-----------------------------------|:------|:------------------------------
4635 * ALT_UART_CPR_ADDITIONAL_FEAT_E_END | 0x1 | Additional Features Supported
4636 *
4637 * Field Access Macros:
4638 *
4639 */
4640/*
4641 * Enumerated value for register field ALT_UART_CPR_ADDITIONAL_FEAT
4642 *
4643 * Additional Features Supported
4644 */
4645#define ALT_UART_CPR_ADDITIONAL_FEAT_E_END 0x1
4646
4647/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
4648#define ALT_UART_CPR_ADDITIONAL_FEAT_LSB 8
4649/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
4650#define ALT_UART_CPR_ADDITIONAL_FEAT_MSB 8
4651/* The width in bits of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
4652#define ALT_UART_CPR_ADDITIONAL_FEAT_WIDTH 1
4653/* The mask used to set the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */
4654#define ALT_UART_CPR_ADDITIONAL_FEAT_SET_MSK 0x00000100
4655/* The mask used to clear the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */
4656#define ALT_UART_CPR_ADDITIONAL_FEAT_CLR_MSK 0xfffffeff
4657/* The reset value of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
4658#define ALT_UART_CPR_ADDITIONAL_FEAT_RESET 0x1
4659/* Extracts the ALT_UART_CPR_ADDITIONAL_FEAT field value from a register. */
4660#define ALT_UART_CPR_ADDITIONAL_FEAT_GET(value) (((value) & 0x00000100) >> 8)
4661/* Produces a ALT_UART_CPR_ADDITIONAL_FEAT register field value suitable for setting the register. */
4662#define ALT_UART_CPR_ADDITIONAL_FEAT_SET(value) (((value) << 8) & 0x00000100)
4663
4664/*
4665 * Field : FIFO ACCESS Supported - fifo_access
4666 *
4667 * Configures the peripheral to have a programmable FIFO access mode. This is used
4668 * for test purposes, to allow the receiver FIFO to be written and the transmit
4669 * FIFO to be read when FIFOs are implemented and enabled.
4670 *
4671 * Field Enumeration Values:
4672 *
4673 * Enum | Value | Description
4674 * :-------------------------------|:------|:----------------------
4675 * ALT_UART_CPR_FIFO_ACCESS_E_END | 0x1 | FIFO Access Supported
4676 *
4677 * Field Access Macros:
4678 *
4679 */
4680/*
4681 * Enumerated value for register field ALT_UART_CPR_FIFO_ACCESS
4682 *
4683 * FIFO Access Supported
4684 */
4685#define ALT_UART_CPR_FIFO_ACCESS_E_END 0x1
4686
4687/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */
4688#define ALT_UART_CPR_FIFO_ACCESS_LSB 9
4689/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */
4690#define ALT_UART_CPR_FIFO_ACCESS_MSB 9
4691/* The width in bits of the ALT_UART_CPR_FIFO_ACCESS register field. */
4692#define ALT_UART_CPR_FIFO_ACCESS_WIDTH 1
4693/* The mask used to set the ALT_UART_CPR_FIFO_ACCESS register field value. */
4694#define ALT_UART_CPR_FIFO_ACCESS_SET_MSK 0x00000200
4695/* The mask used to clear the ALT_UART_CPR_FIFO_ACCESS register field value. */
4696#define ALT_UART_CPR_FIFO_ACCESS_CLR_MSK 0xfffffdff
4697/* The reset value of the ALT_UART_CPR_FIFO_ACCESS register field. */
4698#define ALT_UART_CPR_FIFO_ACCESS_RESET 0x1
4699/* Extracts the ALT_UART_CPR_FIFO_ACCESS field value from a register. */
4700#define ALT_UART_CPR_FIFO_ACCESS_GET(value) (((value) & 0x00000200) >> 9)
4701/* Produces a ALT_UART_CPR_FIFO_ACCESS register field value suitable for setting the register. */
4702#define ALT_UART_CPR_FIFO_ACCESS_SET(value) (((value) << 9) & 0x00000200)
4703
4704/*
4705 * Field : FIFO STAT Supported - fifo_stat
4706 *
4707 * Configures the peripheral to have three additional FIFO status registers.
4708 *
4709 * Field Enumeration Values:
4710 *
4711 * Enum | Value | Description
4712 * :-----------------------------|:------|:--------------------
4713 * ALT_UART_CPR_FIFO_STAT_E_END | 0x1 | FIFO Stat Supported
4714 *
4715 * Field Access Macros:
4716 *
4717 */
4718/*
4719 * Enumerated value for register field ALT_UART_CPR_FIFO_STAT
4720 *
4721 * FIFO Stat Supported
4722 */
4723#define ALT_UART_CPR_FIFO_STAT_E_END 0x1
4724
4725/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_STAT register field. */
4726#define ALT_UART_CPR_FIFO_STAT_LSB 10
4727/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_STAT register field. */
4728#define ALT_UART_CPR_FIFO_STAT_MSB 10
4729/* The width in bits of the ALT_UART_CPR_FIFO_STAT register field. */
4730#define ALT_UART_CPR_FIFO_STAT_WIDTH 1
4731/* The mask used to set the ALT_UART_CPR_FIFO_STAT register field value. */
4732#define ALT_UART_CPR_FIFO_STAT_SET_MSK 0x00000400
4733/* The mask used to clear the ALT_UART_CPR_FIFO_STAT register field value. */
4734#define ALT_UART_CPR_FIFO_STAT_CLR_MSK 0xfffffbff
4735/* The reset value of the ALT_UART_CPR_FIFO_STAT register field. */
4736#define ALT_UART_CPR_FIFO_STAT_RESET 0x1
4737/* Extracts the ALT_UART_CPR_FIFO_STAT field value from a register. */
4738#define ALT_UART_CPR_FIFO_STAT_GET(value) (((value) & 0x00000400) >> 10)
4739/* Produces a ALT_UART_CPR_FIFO_STAT register field value suitable for setting the register. */
4740#define ALT_UART_CPR_FIFO_STAT_SET(value) (((value) << 10) & 0x00000400)
4741
4742/*
4743 * Field : SHADOW Supported - shadow
4744 *
4745 * Configures the peripheral to have seven additional registers that shadow some of
4746 * the existing register bits that are regularly modified by software. These can be
4747 * used to reduce the software overhead that is introduced by having to perform
4748 * read-modify writes.
4749 *
4750 * Field Enumeration Values:
4751 *
4752 * Enum | Value | Description
4753 * :--------------------------|:------|:-----------------
4754 * ALT_UART_CPR_SHADOW_E_END | 0x1 | Shadow Supported
4755 *
4756 * Field Access Macros:
4757 *
4758 */
4759/*
4760 * Enumerated value for register field ALT_UART_CPR_SHADOW
4761 *
4762 * Shadow Supported
4763 */
4764#define ALT_UART_CPR_SHADOW_E_END 0x1
4765
4766/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SHADOW register field. */
4767#define ALT_UART_CPR_SHADOW_LSB 11
4768/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SHADOW register field. */
4769#define ALT_UART_CPR_SHADOW_MSB 11
4770/* The width in bits of the ALT_UART_CPR_SHADOW register field. */
4771#define ALT_UART_CPR_SHADOW_WIDTH 1
4772/* The mask used to set the ALT_UART_CPR_SHADOW register field value. */
4773#define ALT_UART_CPR_SHADOW_SET_MSK 0x00000800
4774/* The mask used to clear the ALT_UART_CPR_SHADOW register field value. */
4775#define ALT_UART_CPR_SHADOW_CLR_MSK 0xfffff7ff
4776/* The reset value of the ALT_UART_CPR_SHADOW register field. */
4777#define ALT_UART_CPR_SHADOW_RESET 0x1
4778/* Extracts the ALT_UART_CPR_SHADOW field value from a register. */
4779#define ALT_UART_CPR_SHADOW_GET(value) (((value) & 0x00000800) >> 11)
4780/* Produces a ALT_UART_CPR_SHADOW register field value suitable for setting the register. */
4781#define ALT_UART_CPR_SHADOW_SET(value) (((value) << 11) & 0x00000800)
4782
4783/*
4784 * Field : Configuartion ID Register Present - uart_add_encoded_param
4785 *
4786 * Configures the peripheral to have a configuration identification register.
4787 *
4788 * Field Enumeration Values:
4789 *
4790 * Enum | Value | Description
4791 * :--------------------------------------|:------|:--------------------
4792 * ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END | 0x1 | ID register present
4793 *
4794 * Field Access Macros:
4795 *
4796 */
4797/*
4798 * Enumerated value for register field ALT_UART_CPR_UART_ADD_ENC_PARAM
4799 *
4800 * ID register present
4801 */
4802#define ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END 0x1
4803
4804/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
4805#define ALT_UART_CPR_UART_ADD_ENC_PARAM_LSB 12
4806/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
4807#define ALT_UART_CPR_UART_ADD_ENC_PARAM_MSB 12
4808/* The width in bits of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
4809#define ALT_UART_CPR_UART_ADD_ENC_PARAM_WIDTH 1
4810/* The mask used to set the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */
4811#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET_MSK 0x00001000
4812/* The mask used to clear the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */
4813#define ALT_UART_CPR_UART_ADD_ENC_PARAM_CLR_MSK 0xffffefff
4814/* The reset value of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
4815#define ALT_UART_CPR_UART_ADD_ENC_PARAM_RESET 0x1
4816/* Extracts the ALT_UART_CPR_UART_ADD_ENC_PARAM field value from a register. */
4817#define ALT_UART_CPR_UART_ADD_ENC_PARAM_GET(value) (((value) & 0x00001000) >> 12)
4818/* Produces a ALT_UART_CPR_UART_ADD_ENC_PARAM register field value suitable for setting the register. */
4819#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET(value) (((value) << 12) & 0x00001000)
4820
4821/*
4822 * Field : DMA EXTRA Supported - dma_extra
4823 *
4824 * Configures the peripheral to have four additional DMA signals on the interface.
4825 *
4826 * Field Enumeration Values:
4827 *
4828 * Enum | Value | Description
4829 * :-----------------------------|:------|:--------------------
4830 * ALT_UART_CPR_DMA_EXTRA_E_END | 0x1 | DMA Extra Supported
4831 *
4832 * Field Access Macros:
4833 *
4834 */
4835/*
4836 * Enumerated value for register field ALT_UART_CPR_DMA_EXTRA
4837 *
4838 * DMA Extra Supported
4839 */
4840#define ALT_UART_CPR_DMA_EXTRA_E_END 0x1
4841
4842/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */
4843#define ALT_UART_CPR_DMA_EXTRA_LSB 13
4844/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */
4845#define ALT_UART_CPR_DMA_EXTRA_MSB 13
4846/* The width in bits of the ALT_UART_CPR_DMA_EXTRA register field. */
4847#define ALT_UART_CPR_DMA_EXTRA_WIDTH 1
4848/* The mask used to set the ALT_UART_CPR_DMA_EXTRA register field value. */
4849#define ALT_UART_CPR_DMA_EXTRA_SET_MSK 0x00002000
4850/* The mask used to clear the ALT_UART_CPR_DMA_EXTRA register field value. */
4851#define ALT_UART_CPR_DMA_EXTRA_CLR_MSK 0xffffdfff
4852/* The reset value of the ALT_UART_CPR_DMA_EXTRA register field. */
4853#define ALT_UART_CPR_DMA_EXTRA_RESET 0x1
4854/* Extracts the ALT_UART_CPR_DMA_EXTRA field value from a register. */
4855#define ALT_UART_CPR_DMA_EXTRA_GET(value) (((value) & 0x00002000) >> 13)
4856/* Produces a ALT_UART_CPR_DMA_EXTRA register field value suitable for setting the register. */
4857#define ALT_UART_CPR_DMA_EXTRA_SET(value) (((value) << 13) & 0x00002000)
4858
4859/*
4860 * Field : FIFO Depth - fifo_mode
4861 *
4862 * Receiver and Transmitter FIFO depth in bytes.
4863 *
4864 * Field Enumeration Values:
4865 *
4866 * Enum | Value | Description
4867 * :-------------------------------------|:------|:---------------------
4868 * ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES | 0x80 | FIFO Depth 128 bytes
4869 *
4870 * Field Access Macros:
4871 *
4872 */
4873/*
4874 * Enumerated value for register field ALT_UART_CPR_FIFO_MOD
4875 *
4876 * FIFO Depth 128 bytes
4877 */
4878#define ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES 0x80
4879
4880/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_MOD register field. */
4881#define ALT_UART_CPR_FIFO_MOD_LSB 16
4882/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_MOD register field. */
4883#define ALT_UART_CPR_FIFO_MOD_MSB 23
4884/* The width in bits of the ALT_UART_CPR_FIFO_MOD register field. */
4885#define ALT_UART_CPR_FIFO_MOD_WIDTH 8
4886/* The mask used to set the ALT_UART_CPR_FIFO_MOD register field value. */
4887#define ALT_UART_CPR_FIFO_MOD_SET_MSK 0x00ff0000
4888/* The mask used to clear the ALT_UART_CPR_FIFO_MOD register field value. */
4889#define ALT_UART_CPR_FIFO_MOD_CLR_MSK 0xff00ffff
4890/* The reset value of the ALT_UART_CPR_FIFO_MOD register field. */
4891#define ALT_UART_CPR_FIFO_MOD_RESET 0x37
4892/* Extracts the ALT_UART_CPR_FIFO_MOD field value from a register. */
4893#define ALT_UART_CPR_FIFO_MOD_GET(value) (((value) & 0x00ff0000) >> 16)
4894/* Produces a ALT_UART_CPR_FIFO_MOD register field value suitable for setting the register. */
4895#define ALT_UART_CPR_FIFO_MOD_SET(value) (((value) << 16) & 0x00ff0000)
4896
4897#ifndef __ASSEMBLY__
4898/*
4899 * WARNING: The C register and register group struct declarations are provided for
4900 * convenience and illustrative purposes. They should, however, be used with
4901 * caution as the C language standard provides no guarantees about the alignment or
4902 * atomicity of device memory accesses. The recommended practice for writing
4903 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4904 * alt_write_word() functions.
4905 *
4906 * The struct declaration for register ALT_UART_CPR.
4907 */
4908 struct ALT_UART_CPR_s
4909{
4910 const uint32_t apbdatawidth : 2; /* APB DATA WIDTH */
4911 uint32_t : 2; /* *UNDEFINED* */
4912 const uint32_t afce_mode : 1; /* Auto Flow Control */
4913 const uint32_t thre_mode : 1; /* THRE MODE */
4914 const uint32_t sir_mode : 1; /* SIR MODE Unsupported */
4915 const uint32_t sir_lp_mode : 1; /* SIR LP MODE Unsupported */
4916 const uint32_t additional_feat : 1; /* ADDITIONAL FEATURES Supported */
4917 const uint32_t fifo_access : 1; /* FIFO ACCESS Supported */
4918 const uint32_t fifo_stat : 1; /* FIFO STAT Supported */
4919 const uint32_t shadow : 1; /* SHADOW Supported */
4920 const uint32_t uart_add_encoded_param : 1; /* Configuartion ID Register Present */
4921 const uint32_t dma_extra : 1; /* DMA EXTRA Supported */
4922 uint32_t : 2; /* *UNDEFINED* */
4923 const uint32_t fifo_mode : 8; /* FIFO Depth */
4924 uint32_t : 8; /* *UNDEFINED* */
4925};
4926
4927/* The typedef declaration for register ALT_UART_CPR. */
4928typedef volatile struct ALT_UART_CPR_s ALT_UART_CPR_t;
4929#endif /* __ASSEMBLY__ */
4930
4931/* The byte offset of the ALT_UART_CPR register from the beginning of the component. */
4932#define ALT_UART_CPR_OFST 0xf4
4933/* The address of the ALT_UART_CPR register. */
4934#define ALT_UART_CPR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CPR_OFST))
4935
4936/*
4937 * Register : Component Version - ucv
4938 *
4939 * Used only with Additional Features
4940 *
4941 * Register Layout
4942 *
4943 * Bits | Access | Reset | Description
4944 * :-------|:-------|:-----------|:--------------
4945 * [31:0] | R | 0x3331312a | ASCII version
4946 *
4947 */
4948/*
4949 * Field : ASCII version - uart_component_version
4950 *
4951 * ASCII value for each number in the version, followed by *For example 32_30_31_2A
4952 * represents the version 2.01a
4953 *
4954 * Field Access Macros:
4955 *
4956 */
4957/* The Least Significant Bit (LSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
4958#define ALT_UART_UCV_UART_COMPONENT_VER_LSB 0
4959/* The Most Significant Bit (MSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
4960#define ALT_UART_UCV_UART_COMPONENT_VER_MSB 31
4961/* The width in bits of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
4962#define ALT_UART_UCV_UART_COMPONENT_VER_WIDTH 32
4963/* The mask used to set the ALT_UART_UCV_UART_COMPONENT_VER register field value. */
4964#define ALT_UART_UCV_UART_COMPONENT_VER_SET_MSK 0xffffffff
4965/* The mask used to clear the ALT_UART_UCV_UART_COMPONENT_VER register field value. */
4966#define ALT_UART_UCV_UART_COMPONENT_VER_CLR_MSK 0x00000000
4967/* The reset value of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
4968#define ALT_UART_UCV_UART_COMPONENT_VER_RESET 0x3331312a
4969/* Extracts the ALT_UART_UCV_UART_COMPONENT_VER field value from a register. */
4970#define ALT_UART_UCV_UART_COMPONENT_VER_GET(value) (((value) & 0xffffffff) >> 0)
4971/* Produces a ALT_UART_UCV_UART_COMPONENT_VER register field value suitable for setting the register. */
4972#define ALT_UART_UCV_UART_COMPONENT_VER_SET(value) (((value) << 0) & 0xffffffff)
4973
4974#ifndef __ASSEMBLY__
4975/*
4976 * WARNING: The C register and register group struct declarations are provided for
4977 * convenience and illustrative purposes. They should, however, be used with
4978 * caution as the C language standard provides no guarantees about the alignment or
4979 * atomicity of device memory accesses. The recommended practice for writing
4980 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4981 * alt_write_word() functions.
4982 *
4983 * The struct declaration for register ALT_UART_UCV.
4984 */
4985 struct ALT_UART_UCV_s
4986{
4987 const uint32_t uart_component_version : 32; /* ASCII version */
4988};
4989
4990/* The typedef declaration for register ALT_UART_UCV. */
4991typedef volatile struct ALT_UART_UCV_s ALT_UART_UCV_t;
4992#endif /* __ASSEMBLY__ */
4993
4994/* The byte offset of the ALT_UART_UCV register from the beginning of the component. */
4995#define ALT_UART_UCV_OFST 0xf8
4996/* The address of the ALT_UART_UCV register. */
4997#define ALT_UART_UCV_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_UCV_OFST))
4998
4999/*
5000 * Register : Component Type Register - ctr
5001 *
5002 * Describes a hex value associated with the component.
5003 *
5004 * Register Layout
5005 *
5006 * Bits | Access | Reset | Description
5007 * :-------|:-------|:-----------|:--------------
5008 * [31:0] | R | 0x44570110 | Peripheral ID
5009 *
5010 */
5011/*
5012 * Field : Peripheral ID - peripheral_id
5013 *
5014 * This register contains the peripherals identification code.
5015 *
5016 * Field Access Macros:
5017 *
5018 */
5019/* The Least Significant Bit (LSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */
5020#define ALT_UART_CTR_PERIPHERAL_ID_LSB 0
5021/* The Most Significant Bit (MSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */
5022#define ALT_UART_CTR_PERIPHERAL_ID_MSB 31
5023/* The width in bits of the ALT_UART_CTR_PERIPHERAL_ID register field. */
5024#define ALT_UART_CTR_PERIPHERAL_ID_WIDTH 32
5025/* The mask used to set the ALT_UART_CTR_PERIPHERAL_ID register field value. */
5026#define ALT_UART_CTR_PERIPHERAL_ID_SET_MSK 0xffffffff
5027/* The mask used to clear the ALT_UART_CTR_PERIPHERAL_ID register field value. */
5028#define ALT_UART_CTR_PERIPHERAL_ID_CLR_MSK 0x00000000
5029/* The reset value of the ALT_UART_CTR_PERIPHERAL_ID register field. */
5030#define ALT_UART_CTR_PERIPHERAL_ID_RESET 0x44570110
5031/* Extracts the ALT_UART_CTR_PERIPHERAL_ID field value from a register. */
5032#define ALT_UART_CTR_PERIPHERAL_ID_GET(value) (((value) & 0xffffffff) >> 0)
5033/* Produces a ALT_UART_CTR_PERIPHERAL_ID register field value suitable for setting the register. */
5034#define ALT_UART_CTR_PERIPHERAL_ID_SET(value) (((value) << 0) & 0xffffffff)
5035
5036#ifndef __ASSEMBLY__
5037/*
5038 * WARNING: The C register and register group struct declarations are provided for
5039 * convenience and illustrative purposes. They should, however, be used with
5040 * caution as the C language standard provides no guarantees about the alignment or
5041 * atomicity of device memory accesses. The recommended practice for writing
5042 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5043 * alt_write_word() functions.
5044 *
5045 * The struct declaration for register ALT_UART_CTR.
5046 */
5047 struct ALT_UART_CTR_s
5048{
5049 const uint32_t peripheral_id : 32; /* Peripheral ID */
5050};
5051
5052/* The typedef declaration for register ALT_UART_CTR. */
5053typedef volatile struct ALT_UART_CTR_s ALT_UART_CTR_t;
5054#endif /* __ASSEMBLY__ */
5055
5056/* The byte offset of the ALT_UART_CTR register from the beginning of the component. */
5057#define ALT_UART_CTR_OFST 0xfc
5058/* The address of the ALT_UART_CTR register. */
5059#define ALT_UART_CTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CTR_OFST))
5060
5061#ifndef __ASSEMBLY__
5062/*
5063 * WARNING: The C register and register group struct declarations are provided for
5064 * convenience and illustrative purposes. They should, however, be used with
5065 * caution as the C language standard provides no guarantees about the alignment or
5066 * atomicity of device memory accesses. The recommended practice for writing
5067 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5068 * alt_write_word() functions.
5069 *
5070 * The struct declaration for register group ALT_UART.
5071 */
5072 struct ALT_UART_s
5073{
5074 volatile ALT_UART_RBR_THR_DLL_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */
5075 volatile ALT_UART_IER_DLH_t ier_dlh; /* ALT_UART_IER_DLH */
5076 /* Union for registers colocated at base address offset #0x. */
5077 union
5078 {
5079 volatile ALT_UART_IIR_t iir; /* ALT_UART_IIR */
5080 volatile ALT_UART_FCR_t fcr; /* ALT_UART_FCR */
5081 } _u_0x8;
5082 volatile ALT_UART_LCR_t lcr; /* ALT_UART_LCR */
5083 volatile ALT_UART_MCR_t mcr; /* ALT_UART_MCR */
5084 volatile ALT_UART_LSR_t lsr; /* ALT_UART_LSR */
5085 volatile ALT_UART_MSR_t msr; /* ALT_UART_MSR */
5086 volatile ALT_UART_SCR_t scr; /* ALT_UART_SCR */
5087 volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */
5088 volatile ALT_UART_SRBR_t srbr; /* ALT_UART_SRBR */
5089 volatile ALT_UART_STHR_t sthr; /* ALT_UART_STHR */
5090 volatile uint32_t _pad_0x38_0x6f[14]; /* *UNDEFINED* */
5091 volatile ALT_UART_FAR_t far; /* ALT_UART_FAR */
5092 volatile ALT_UART_TFR_t tfr; /* ALT_UART_TFR */
5093 volatile ALT_UART_RFW_t RFW; /* ALT_UART_RFW */
5094 volatile ALT_UART_USR_t usr; /* ALT_UART_USR */
5095 volatile ALT_UART_TFL_t tfl; /* ALT_UART_TFL */
5096 volatile ALT_UART_RFL_t rfl; /* ALT_UART_RFL */
5097 volatile ALT_UART_SRR_t srr; /* ALT_UART_SRR */
5098 volatile ALT_UART_SRTS_t srts; /* ALT_UART_SRTS */
5099 volatile ALT_UART_SBCR_t sbcr; /* ALT_UART_SBCR */
5100 volatile ALT_UART_SDMAM_t sdmam; /* ALT_UART_SDMAM */
5101 volatile ALT_UART_SFE_t sfe; /* ALT_UART_SFE */
5102 volatile ALT_UART_SRT_t srt; /* ALT_UART_SRT */
5103 volatile ALT_UART_STET_t stet; /* ALT_UART_STET */
5104 volatile ALT_UART_HTX_t htx; /* ALT_UART_HTX */
5105 volatile ALT_UART_DMASA_t dmasa; /* ALT_UART_DMASA */
5106 volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */
5107 volatile ALT_UART_CPR_t cpr; /* ALT_UART_CPR */
5108 volatile ALT_UART_UCV_t ucv; /* ALT_UART_UCV */
5109 volatile ALT_UART_CTR_t ctr; /* ALT_UART_CTR */
5110};
5111
5112/* The typedef declaration for register group ALT_UART. */
5113typedef volatile struct ALT_UART_s ALT_UART_t;
5114/* The struct declaration for the raw register contents of register group ALT_UART. */
5115 struct ALT_UART_raw_s
5116{
5117 volatile uint32_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */
5118 volatile uint32_t ier_dlh; /* ALT_UART_IER_DLH */
5119 /* Union for registers colocated at base address offset #0x. */
5120 union
5121 {
5122 volatile uint32_t iir; /* ALT_UART_IIR */
5123 volatile uint32_t fcr; /* ALT_UART_FCR */
5124 } _u_0x8;
5125 volatile uint32_t lcr; /* ALT_UART_LCR */
5126 volatile uint32_t mcr; /* ALT_UART_MCR */
5127 volatile uint32_t lsr; /* ALT_UART_LSR */
5128 volatile uint32_t msr; /* ALT_UART_MSR */
5129 volatile uint32_t scr; /* ALT_UART_SCR */
5130 volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */
5131 volatile uint32_t srbr; /* ALT_UART_SRBR */
5132 volatile uint32_t sthr; /* ALT_UART_STHR */
5133 volatile uint32_t _pad_0x38_0x6f[14]; /* *UNDEFINED* */
5134 volatile uint32_t far; /* ALT_UART_FAR */
5135 volatile uint32_t tfr; /* ALT_UART_TFR */
5136 volatile uint32_t RFW; /* ALT_UART_RFW */
5137 volatile uint32_t usr; /* ALT_UART_USR */
5138 volatile uint32_t tfl; /* ALT_UART_TFL */
5139 volatile uint32_t rfl; /* ALT_UART_RFL */
5140 volatile uint32_t srr; /* ALT_UART_SRR */
5141 volatile uint32_t srts; /* ALT_UART_SRTS */
5142 volatile uint32_t sbcr; /* ALT_UART_SBCR */
5143 volatile uint32_t sdmam; /* ALT_UART_SDMAM */
5144 volatile uint32_t sfe; /* ALT_UART_SFE */
5145 volatile uint32_t srt; /* ALT_UART_SRT */
5146 volatile uint32_t stet; /* ALT_UART_STET */
5147 volatile uint32_t htx; /* ALT_UART_HTX */
5148 volatile uint32_t dmasa; /* ALT_UART_DMASA */
5149 volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */
5150 volatile uint32_t cpr; /* ALT_UART_CPR */
5151 volatile uint32_t ucv; /* ALT_UART_UCV */
5152 volatile uint32_t ctr; /* ALT_UART_CTR */
5153};
5154
5155/* The typedef declaration for the raw register contents of register group ALT_UART. */
5156typedef volatile struct ALT_UART_raw_s ALT_UART_raw_t;
5157#endif /* __ASSEMBLY__ */
5158
5159
5160#ifdef __cplusplus
5161}
5162#endif /* __cplusplus */
5163#endif /* __ALTERA_ALT_UART_H__ */
5164
ALT_UART_CPR_s
Definition: alt_uart.h:4909
ALT_UART_CTR_s
Definition: alt_uart.h:5048
ALT_UART_DMASA_s
Definition: alt_uart.h:4394
ALT_UART_FAR_s
Definition: alt_uart.h:2928
ALT_UART_FCR_s
Definition: alt_uart.h:1103
ALT_UART_HTX_s
Definition: alt_uart.h:4326
ALT_UART_IER_DLH_s
Definition: alt_uart.h:547
ALT_UART_IIR_s
Definition: alt_uart.h:713
ALT_UART_LCR_s
Definition: alt_uart.h:1410
ALT_UART_LSR_s
Definition: alt_uart.h:2160
ALT_UART_MCR_s
Definition: alt_uart.h:1746
ALT_UART_MSR_s
Definition: alt_uart.h:2619
ALT_UART_RBR_THR_DLL_s
Definition: alt_uart.h:143
ALT_UART_RFL_s
Definition: alt_uart.h:3485
ALT_UART_RFW_s
Definition: alt_uart.h:3122
ALT_UART_SBCR_s
Definition: alt_uart.h:3858
ALT_UART_SCR_s
Definition: alt_uart.h:2690
ALT_UART_SDMAM_s
Definition: alt_uart.h:3944
ALT_UART_SFE_s
Definition: alt_uart.h:4032
ALT_UART_SRBR_s
Definition: alt_uart.h:2764
ALT_UART_SRR_s
Definition: alt_uart.h:3671
ALT_UART_SRTS_s
Definition: alt_uart.h:3768
ALT_UART_SRT_s
Definition: alt_uart.h:4136
ALT_UART_STET_s
Definition: alt_uart.h:4238
ALT_UART_STHR_s
Definition: alt_uart.h:2838
ALT_UART_TFL_s
Definition: alt_uart.h:3420
ALT_UART_TFR_s
Definition: alt_uart.h:2996
ALT_UART_UCV_s
Definition: alt_uart.h:4986
ALT_UART_USR_s
Definition: alt_uart.h:3351
ALT_UART_raw_s
Definition: alt_uart.h:5116
ALT_UART_s
Definition: alt_uart.h:5073