RTEMS: bsps/sh/gensh1/include/rtems/score/ispsh7032.h Source File

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ispsh7032.h
1/*
2 * This include file contains information pertaining to the Hitachi SH
3 * processor.
4 *
5 * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
6 * Bernd Becker (becker@faw.uni-ulm.de)
7 *
8 * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 *
15 * COPYRIGHT (c) 1998.
16 * On-Line Applications Research Corporation (OAR).
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef __CPU_ISPS_H
24#define __CPU_ISPS_H
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30extern void __ISR_Handler( uint32_t vector );
31
32
33/*
34 * interrupt vector table offsets
35 */
36#define NMI_ISP_V 11
37#define USB_ISP_V 12
38#define IRQ0_ISP_V 64
39#define IRQ1_ISP_V 65
40#define IRQ2_ISP_V 66
41#define IRQ3_ISP_V 67
42#define IRQ4_ISP_V 68
43#define IRQ5_ISP_V 69
44#define IRQ6_ISP_V 70
45#define IRQ7_ISP_V 71
46#define DMA0_ISP_V 72
47#define DMA1_ISP_V 74
48#define DMA2_ISP_V 76
49#define DMA3_ISP_V 78
50
51#define IMIA0_ISP_V 80
52#define IMIB0_ISP_V 81
53#define OVI0_ISP_V 82
54
55#define IMIA1_ISP_V 84
56#define IMIB1_ISP_V 85
57#define OVI1_ISP_V 86
58
59#define IMIA2_ISP_V 88
60#define IMIB2_ISP_V 89
61#define OVI2_ISP_V 90
62
63#define IMIA3_ISP_V 92
64#define IMIB3_ISP_V 93
65#define OVI3_ISP_V 94
66
67#define IMIA4_ISP_V 96
68#define IMIB4_ISP_V 97
69#define OVI4_ISP_V 98
70
71#define ERI0_ISP_V 100
72#define RXI0_ISP_V 101
73#define TXI0_ISP_V 102
74#define TEI0_ISP_V 103
75
76#define ERI1_ISP_V 104
77#define RXI1_ISP_V 105
78#define TXI1_ISP_V 106
79#define TEI1_ISP_V 107
80
81#define PRT_ISP_V 108
82#define ADU_ISP_V 109
83#define WDT_ISP_V 112
84#define DREF_ISP_V 113
85
86
87/* dummy ISP */
88extern void _dummy_isp( void );
89
90/* Non Maskable Interrupt */
91extern void _nmi_isp( void );
92
93/* User Break Controller */
94extern void _usb_isp( void );
95
96/* External interrupts 0-7 */
97extern void _irq0_isp( void );
98extern void _irq1_isp( void );
99extern void _irq2_isp( void );
100extern void _irq3_isp( void );
101extern void _irq4_isp( void );
102extern void _irq5_isp( void );
103extern void _irq6_isp( void );
104extern void _irq7_isp( void );
105
106/* DMA - Controller */
107extern void _dma0_isp( void );
108extern void _dma1_isp( void );
109extern void _dma2_isp( void );
110extern void _dma3_isp( void );
111
112/* Interrupt Timer Unit */
113/* Timer 0 */
114extern void _imia0_isp( void );
115extern void _imib0_isp( void );
116extern void _ovi0_isp( void );
117/* Timer 1 */
118extern void _imia1_isp( void );
119extern void _imib1_isp( void );
120extern void _ovi1_isp( void );
121/* Timer 2 */
122extern void _imia2_isp( void );
123extern void _imib2_isp( void );
124extern void _ovi2_isp( void );
125/* Timer 3 */
126extern void _imia3_isp( void );
127extern void _imib3_isp( void );
128extern void _ovi3_isp( void );
129/* Timer 4 */
130extern void _imia4_isp( void );
131extern void _imib4_isp( void );
132extern void _ovi4_isp( void );
133
134/* seriell interfaces */
135extern void _eri0_isp( void );
136extern void _rxi0_isp( void );
137extern void _txi0_isp( void );
138extern void _tei0_isp( void );
139extern void _eri1_isp( void );
140extern void _rxi1_isp( void );
141extern void _txi1_isp( void );
142extern void _tei1_isp( void );
143
144/* Parity Control Unit of the Bus State Controllers */
145extern void _prt_isp( void );
146
147/* ADC */
148extern void _adu_isp( void );
149
150/* Watchdog Timer */
151extern void _wdt_isp( void );
152
153/* DRAM refresh control unit of bus state controller */
154extern void _dref_isp( void );
155
156#ifdef __cplusplus
157}
158#endif
159
160#endif