RTEMS: bsps/powerpc/virtex/include/xparameters_dflt.h Source File

| RTEMS 5.4-rc2

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xparameters_dflt.h
1/*******************************************************************
2*
3* CAUTION: This file is automatically generated by libgen.
4* Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
5* DO NOT EDIT.
6*
7* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
8*
9* Description: Driver parameters
10*
11*******************************************************************/
12
13#define STDIN_BASEADDRESS 0x40600000
14#define STDOUT_BASEADDRESS 0x40600000
15
16/******************************************************************/
17
18/* Definitions for driver PLBARB */
19#define XPAR_XPLBARB_NUM_INSTANCES 1
20
21/* Definitions for peripheral PLB */
22#define XPAR_PLB_BASEADDR 0x00000000
23#define XPAR_PLB_HIGHADDR 0x00000000
24#define XPAR_PLB_DEVICE_ID 0
25#define XPAR_PLB_PLB_NUM_MASTERS 3
26
27
28/******************************************************************/
29
30/* Definitions for driver OPBARB */
31#define XPAR_XOPBARB_NUM_INSTANCES 1
32
33/* Definitions for peripheral OPB */
34#define XPAR_OPB_BASEADDR 0xFFFFFFFF
35#define XPAR_OPB_HIGHADDR 0x00000000
36#define XPAR_OPB_DEVICE_ID 0
37#define XPAR_OPB_NUM_MASTERS 1
38
39
40/******************************************************************/
41
42/* Definitions for driver UARTLITE */
43#define XPAR_XUARTLITE_NUM_INSTANCES 1
44
45/* Definitions for peripheral CONSOLE */
46#define XPAR_CONSOLE_BASEADDR 0x40600000
47#define XPAR_CONSOLE_HIGHADDR 0x4060FFFF
48#define XPAR_CONSOLE_DEVICE_ID 0
49#define XPAR_CONSOLE_BAUDRATE 115200
50#define XPAR_CONSOLE_USE_PARITY 0
51#define XPAR_CONSOLE_ODD_PARITY 0
52#define XPAR_CONSOLE_DATA_BITS 8
53
54
55/******************************************************************/
56
57/* Definitions for driver GPIO */
58#define XPAR_XGPIO_NUM_INSTANCES 3
59
60/* Definitions for peripheral LEDS */
61#define XPAR_LEDS_BASEADDR 0x40000000
62#define XPAR_LEDS_HIGHADDR 0x4000FFFF
63#define XPAR_LEDS_DEVICE_ID 0
64#define XPAR_LEDS_INTERRUPT_PRESENT 0
65#define XPAR_LEDS_IS_DUAL 0
66
67
68/* Definitions for peripheral PBLEDS */
69#define XPAR_PBLEDS_BASEADDR 0x40020000
70#define XPAR_PBLEDS_HIGHADDR 0x4002FFFF
71#define XPAR_PBLEDS_DEVICE_ID 1
72#define XPAR_PBLEDS_INTERRUPT_PRESENT 0
73#define XPAR_PBLEDS_IS_DUAL 0
74
75
76/* Definitions for peripheral PUSHBUTTONS */
77#define XPAR_PUSHBUTTONS_BASEADDR 0x40040000
78#define XPAR_PUSHBUTTONS_HIGHADDR 0x4004FFFF
79#define XPAR_PUSHBUTTONS_DEVICE_ID 2
80#define XPAR_PUSHBUTTONS_INTERRUPT_PRESENT 1
81#define XPAR_PUSHBUTTONS_IS_DUAL 0
82
83
84/******************************************************************/
85
86/* Definitions for driver TMRCTR */
87#define XPAR_XTMRCTR_NUM_INSTANCES 1
88
89/* Definitions for peripheral OPBTIMER */
90#define XPAR_OPBTIMER_BASEADDR 0x41C00000
91#define XPAR_OPBTIMER_HIGHADDR 0x41C0FFFF
92#define XPAR_OPBTIMER_DEVICE_ID 0
93
94
95/******************************************************************/
96
97#define XPAR_INTC_MAX_NUM_INTR_INPUTS 3
98#define XPAR_XINTC_HAS_IPR 1
99#define XPAR_XINTC_USE_DCR 0
100/* Definitions for driver INTC */
101#define XPAR_XINTC_NUM_INSTANCES 1
102
103/* Definitions for peripheral INTC */
104#define XPAR_INTC_BASEADDR 0x41200000
105#define XPAR_INTC_HIGHADDR 0x4120FFFF
106#define XPAR_INTC_DEVICE_ID 0
107#define XPAR_INTC_KIND_OF_INTR 0x00000000
108
109
110/******************************************************************/
111
112#define XPAR_INTC_SINGLE_BASEADDR 0x41200000
113#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
114#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_INTC_DEVICE_ID
115#define XPAR_OPBTIMER_INTERRUPT_MASK 0X000001
116#define XPAR_INTC_OPBTIMER_INTERRUPT_INTR 0
117#define XPAR_ETHERNET_IP2INTC_IRPT_MASK 0X000002
118#define XPAR_INTC_ETHERNET_IP2INTC_IRPT_INTR 1
119#define XPAR_PUSHBUTTONS_IP2INTC_IRPT_MASK 0X000004
120#define XPAR_INTC_PUSHBUTTONS_IP2INTC_IRPT_INTR 2
121
122/******************************************************************/
123
124/* Definitions for driver DDR */
125#define XPAR_XDDR_NUM_INSTANCES 1
126
127/* Definitions for peripheral DDR_SDRAM_64MX32 */
128#define XPAR_DDR_SDRAM_64MX32_ECC_BASEADDR 0xFFFFFFFF
129#define XPAR_DDR_SDRAM_64MX32_ECC_HIGHADDR 0x00000000
130#define XPAR_DDR_SDRAM_64MX32_DEVICE_ID 0
131#define XPAR_DDR_SDRAM_64MX32_INCLUDE_ECC_INTR 0
132
133
134/******************************************************************/
135
136/* Definitions for peripheral DDR_SDRAM_64MX32 */
137#define XPAR_DDR_SDRAM_64MX32_MEM0_BASEADDR 0x00000000
138#define XPAR_DDR_SDRAM_64MX32_MEM0_HIGHADDR 0x03FFFFFF
139
140/******************************************************************/
141
142
143/* Definitions for peripheral HARD_TEMAC_0 */
144#define XPAR_HARD_TEMAC_0_PHY_TYPE 1
145
146
147/******************************************************************/
148
149/* Definitions for driver TEMAC */
150#define XPAR_XTEMAC_NUM_INSTANCES 1
151
152/* Definitions for peripheral ETHERNET */
153#define XPAR_ETHERNET_DEVICE_ID 0
154#define XPAR_ETHERNET_BASEADDR 0x81200000
155#define XPAR_ETHERNET_HIGHADDR 0x8120FFFF
156#define XPAR_ETHERNET_RXFIFO_DEPTH 32768
157#define XPAR_ETHERNET_TXFIFO_DEPTH 32768
158#define XPAR_ETHERNET_MAC_FIFO_DEPTH 64
159#define XPAR_ETHERNET_DMA_TYPE 1
160#define XPAR_ETHERNET_TX_DRE_TYPE 0
161#define XPAR_ETHERNET_RX_DRE_TYPE 0
162#define XPAR_ETHERNET_INCLUDE_TX_CSUM 0
163#define XPAR_ETHERNET_INCLUDE_RX_CSUM 0
164
165
166/******************************************************************/
167
168
169/* Definitions for peripheral FLASH */
170#define XPAR_FLASH_NUM_BANKS_MEM 1
171
172
173/******************************************************************/
174
175/* Definitions for peripheral FLASH */
176#define XPAR_FLASH_MEM0_BASEADDR 0x06000000
177#define XPAR_FLASH_MEM0_HIGHADDR 0x067FFFFF
178
179/******************************************************************/
180
181
182/* Definitions for peripheral PLB_BRAM_IF_CNTLR_1 */
183#define XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR 0xffff8000
184#define XPAR_PLB_BRAM_IF_CNTLR_1_HIGHADDR 0xffffffff
185
186
187/******************************************************************/
188
189#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
190
191/******************************************************************/
192