RTEMS: bsps/powerpc/beatnik/net/if_gfe/if_gfevar.h Source File

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if_gfevar.h
1#ifndef IF_GFEVAR_H
2#define IF_GFEVAR_H
3/* $NetBSD: if_gfevar.h,v 1.4.10.1 2005/04/29 11:28:56 kent Exp $ */
4
5/*
6 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Allegro Networks, Inc., and Wasabi Systems, Inc.
21 * 4. The name of Allegro Networks, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 * 5. The name of Wasabi Systems, Inc. may not be used to endorse
25 * or promote products derived from this software without specific prior
26 * written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
29 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
30 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
31 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
32 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
40 */
41
42/* NOTE: GE_RXDESC_MAX * 16 <= GE_RXDESC_MEMSIZE */
43/* NOTE: the driver needs 4*GE_RXDESC_MAX mbuf clusters (4 queues) */
44#ifndef __rtems__
45#define GE_RXDESC_MEMSIZE (1 * PAGE_SIZE)
46#define GE_RXDESC_MAX 64
47#define GE_RXBUF_SIZE 2048
48#define GE_RXBUF_MEMSIZE (GE_RXDESC_MAX*GE_RXBUF_SIZE)
49#else
50#define GE_RXDESC_MEMSIZE (GE_RXDESC_MAX * sizeof(struct gt_eth_desc))
51#define GE_RXDESC_MAX (sc->num_rxdesc)
52#define GE_RXBUF_MEMSIZE 0
53#endif
54
55#define GE_RXBUF_NSEGS ((GE_RXBUF_MEMSIZE/PAGE_SIZE)+1)
56#define GE_DMSEG_MAX (GE_RXBUF_NSEGS)
57
58 struct gfe_dmamem {
59 bus_dmamap_t gdm_map; /* dmamem'ed memory */
60#ifdef __rtems__
61 void *gdm_unaligned_buf;
62#endif
63 caddr_t gdm_kva; /* kva of tx memory */
64 int gdm_nsegs; /* # of segment in gdm_segs */
65 int gdm_maxsegs; /* maximum # of segments allowed */
66 size_t gdm_size; /* size of memory region */
67 bus_dma_segment_t gdm_segs[GE_DMSEG_MAX]; /* dma segment of tx memory */
68};
69
70/* With a 4096 page size, we get 256 descriptors per page.
71 */
72#ifndef __rtems__
73#define GE_TXDESC_MEMSIZE (1 * PAGE_SIZE)
74#define GE_TXDESC_MAX (GE_TXDESC_MEMSIZE / 16)
75#define GE_TXBUF_SIZE (4 * PAGE_SIZE)
76#else
77#define GE_TXDESC_MEMSIZE (sc->num_txdesc * sizeof(struct gt_eth_desc))
78#define GE_TXDESC_MAX (sc->num_txdesc)
79#endif
80
81 struct gfe_txqueue {
82 struct ifqueue txq_pendq; /* these are ready to go to the GT */
83 struct ifqueue txq_sentq;
84 struct gfe_dmamem txq_desc_mem; /* transmit descriptor memory */
85#ifndef __rtems__
86 struct gfe_dmamem txq_buf_mem; /* transmit buffer memory */
87#endif
88 unsigned int txq_lo; /* next to be given to GT */
89 unsigned int txq_fi; /* next to be returned to CPU */
90#ifndef __rtems__
91 unsigned int txq_ei_gapcount; /* counter until next EI */
92#endif
93 unsigned int txq_nactive; /* number of active descriptors */
94#ifndef __rtems__
95 unsigned int txq_outptr; /* where to put next transmit packet */
96 unsigned int txq_inptr; /* start of 1st queued tx packet */
97#endif
98 uint32_t txq_intrbits; /* bits to write to EIMR */
99 uint32_t txq_esdcmrbits; /* bits to write to ESDCMR */
100 uint32_t txq_epsrbits; /* bits to test with EPSR */
101 volatile struct gt_eth_desc *txq_descs; /* ptr to tx descriptors */
102 bus_addr_t txq_ectdp; /* offset to cur. tx desc ptr reg */
103 bus_addr_t txq_desc_busaddr; /* bus addr of tx descriptors */
104#ifndef __rtems__
105 bus_addr_t txq_buf_busaddr; /* bus addr of tx buffers */
106#endif
107};
108
109/* With a 4096 page size, we get 256 descriptors per page. We want 1024
110 * which will give us about 8ms of 64 byte packets (2ms for each priority
111 * queue).
112 */
113
114#ifndef __rtems__
115 struct gfe_rxbuf {
116 uint8_t rb_data[GE_RXBUF_SIZE];
117};
118#endif
119
120 struct gfe_rxqueue {
121 struct gfe_dmamem rxq_desc_mem; /* receive descriptor memory */
122#ifndef __rtems__
123 struct gfe_dmamem rxq_buf_mem; /* receive buffer memory */
124 struct mbuf *rxq_curpkt; /* mbuf for current packet */
125#endif
126 volatile struct gt_eth_desc *rxq_descs;
127#ifndef __rtems__
128 struct gfe_rxbuf *rxq_bufs;
129#else
130 struct mbuf **rxq_bufs;
131#endif
132 unsigned int rxq_fi; /* next to be returned to CPU */
133 unsigned int rxq_active; /* # of descriptors given to GT */
134 uint32_t rxq_intrbits; /* bits to write to EIMR */
135 bus_addr_t rxq_desc_busaddr; /* bus addr of rx descriptors */
136 uint32_t rxq_cmdsts; /* save cmdsts from first descriptor */
137 bus_size_t rxq_efrdp;
138 bus_size_t rxq_ecrdp;
139};
140
141enum gfe_txprio {
142 GE_TXPRIO_HI=1,
143 GE_TXPRIO_LO=0,
144 GE_TXPRIO_NONE=2
145};
146enum gfe_rxprio {
147 GE_RXPRIO_HI=3,
148 GE_RXPRIO_MEDHI=2,
149 GE_RXPRIO_MEDLO=1,
150 GE_RXPRIO_LO=0
151};
152
153#ifdef __rtems__
154#define sc_ec arpcom
155#define ec_if ac_if
156#define sc_dev arpcom
157#define dv_xname ac_if.if_name
158#endif
159
160 struct gfe_softc {
161#ifndef __rtems__
162 struct device sc_dev; /* must be first */
163 struct ethercom sc_ec; /* common ethernet glue */
164 struct callout sc_co; /* resource recovery */
165 mii_data_t sc_mii; /* mii interface */
166
167 /*
168 *
169 */
170 bus_space_tag_t sc_gt_memt;
171 bus_space_handle_t sc_gt_memh;
172 bus_space_handle_t sc_memh; /* subregion for ethernet */
173 bus_dma_tag_t sc_dmat;
174#else
175 struct arpcom sc_ec;
176 unsigned sc_gt_memh;
177 unsigned sc_memh;
178 unsigned char irq_no;
179 rtems_id tid;
180 int sc_phyaddr;
181 int num_rxdesc, num_txdesc;
182#endif
183 int sc_macno; /* which mac? 0, 1, or 2 */
184
185 unsigned int sc_tickflags;
186#define GE_TICK_TX_IFSTART 0x0001
187#define GE_TICK_RX_RESTART 0x0002
188 unsigned int sc_flags;
189#define GE_ALLMULTI 0x0001
190#define GE_PHYSTSCHG 0x0002
191#define GE_RXACTIVE 0x0004
192#define GE_NOFREE 0x0008 /* Don't free on disable */
193 uint32_t sc_pcr; /* current EPCR value */
194 uint32_t sc_pcxr; /* current EPCXR value */
195 uint32_t sc_intrmask; /* current EIMR value */
196 uint32_t sc_idlemask; /* suspended EIMR bits */
197 size_t sc_max_frame_length; /* maximum frame length */
198
199 /*
200 * Hash table related members
201 */
202 struct gfe_dmamem sc_hash_mem; /* dma'ble hash table */
203 uint64_t *sc_hashtable;
204 unsigned int sc_hashmask; /* 0x1ff or 0x1fff */
205
206 /*
207 * Transmit related members
208 */
209 struct gfe_txqueue sc_txq[2]; /* High & Low transmit queues */
210
211 /*
212 * Receive related members
213 */
214 struct gfe_rxqueue sc_rxq[4]; /* Hi/MedHi/MedLo/Lo receive queues */
215};
216
217#ifdef __rtems__
218int
219gfe_mii_read(int phy, void *arg, unsigned reg, uint32_t *pval);
220
221int
222gfe_mii_write(int phy, void *arg, unsigned reg, uint32_t value);
223#endif
224
225#endif
rtems_id
Objects_Id rtems_id
Used to manage and manipulate RTEMS object identifiers.
Definition: types.h:83
bus_dma_segment_t
Definition: rtemscompat_defs.h:91
callout
Definition: rtemsmain.c:734
device
Definition: rtemscompat1.h:15
gfe_dmamem
Definition: if_gfevar.h:58
gfe_rxbuf
Definition: if_gfevar.h:115
gfe_rxqueue
Definition: if_gfevar.h:120
gfe_softc
Definition: if_gfevar.h:160
gfe_txqueue
Definition: if_gfevar.h:81
gt_eth_desc
Definition: gtethreg.h:61