RTEMS: cpukit/score/cpu/arm/include/rtems/asm.h Source File

| RTEMS 5.4-rc2

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asm.h
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1
17/*
18 * COPYRIGHT:
19 *
20 * This file is based on similar code found in newlib available
21 * from ftp.cygnus.com. The file which was used had no copyright
22 * notice. This file is freely distributable as long as the source
23 * of the file is noted. This file is:
24 *
25 * COPYRIGHT (c) 2000 Canon Research Centre France SA.
26 * Emmanuel Raguet, mailto:raguet@crf.canon.fr
27 *
28 * The license and distribution terms for this file may be
29 * found in the file LICENSE in this distribution or at
30 * http://www.rtems.org/license/LICENSE.
31 *
32 */
33
34#ifndef _RTEMS_ASM_H
35#define _RTEMS_ASM_H
36
37/*
38 * Indicate we are in an assembly file and get the basic CPU definitions.
39 */
40
41#ifndef ASM
42#define ASM
43#endif
44#include <rtems/score/percpu.h>
45
55/*
56 * Recent versions of GNU cpp define variables which indicate the
57 * need for underscores and percents. If not using GNU cpp or
58 * the version does not support this, then you will obviously
59 * have to define these as appropriate.
60 */
61
62#ifndef __USER_LABEL_PREFIX__
63#define __USER_LABEL_PREFIX__ _
64#endif
65
66#ifndef __REGISTER_PREFIX__
67#define __REGISTER_PREFIX__
68#endif
69
70#include <rtems/concat.h>
71
72/* Use the right prefix for global labels. */
73
74#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
75
76/* Use the right prefix for registers. */
77
78#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
79
80/*
81 * define macros for all of the registers on this CPU
82 *
83 * EXAMPLE: #define d0 REG (d0)
84 */
85
86#define r0 REG(r0)
87#define r1 REG(r1)
88#define r2 REG(r2)
89#define r3 REG(r3)
90#define r4 REG(r4)
91#define r5 REG(r5)
92#define r6 REG(r6)
93#define r7 REG(r7)
94#define r8 REG(r8)
95#define r9 REG(r9)
96#define r10 REG(r10)
97#define r11 REG(r11)
98#define r12 REG(r12)
99#define r13 REG(r13)
100#define r14 REG(r14)
101#define r15 REG(r15)
102
103#define CPSR REG(CPSR)
104
105#define SPSR REG(SPSR)
106
107#define NUM_IRQ_VECTOR 6 // IRQ number
108#define NUM_FIQ_VECTOR 7 // IRQ number
109 // //
110#define CPSR_IRQ_DISABLE 0x80 // FIQ disabled when =1
111#define CPSR_FIQ_DISABLE 0x40 // FIQ disabled when =1
112#define CPSR_THUMB_ENABLE 0x20 // Thumb mode when =1
113#define CPSR_FIQ_MODE 0x11
114#define CPSR_IRQ_MODE 0x12
115#define CPSR_SUPERVISOR_MODE 0x13
116#define CPSR_UNDEF_MODE 0x1B
117
118#define CPSR_MODE_BITS 0x1F
119
120/*
121 * Define macros to handle section beginning and ends.
122 */
123
124
125#define BEGIN_CODE_DCL .text
126#define END_CODE_DCL
127#define BEGIN_DATA_DCL .data
128#define END_DATA_DCL
129#define BEGIN_CODE .text
130#define END_CODE
131#define BEGIN_DATA
132#define END_DATA
133#define BEGIN_BSS
134#define END_BSS
135#define END
136
137/*
138 * Following must be tailor for a particular flavor of the C compiler.
139 * They may need to put underscores in front of the symbols.
140 */
141
142#define PUBLIC(sym) .globl SYM (sym)
143#define EXTERN(sym) .globl SYM (sym)
144
145#define FUNCTION_THUMB_ENTRY(name) \
146 .thumb; \
147 .thumb_func; \
148 .align 2; \
149 .globl name; \
150 .type name, %function; \
151 name:
152
153#define FUNCTION_ENTRY(name) \
154 .align 2; \
155 .globl name; \
156 .type name, %function; \
157 name:
158
159#define FUNCTION_END(name) \
160 .size name, . - name
161
162#if defined(ARM_MULTILIB_ARCH_V7M)
163 #define DEFINE_FUNCTION_ARM(name) \
164 .thumb_func ; .globl name ; name:
165#elif defined(__thumb__)
166 #define DEFINE_FUNCTION_ARM(name) \
167 .thumb_func ; .globl name ; name: ; bx pc ; \
168 .arm ; .globl name ## _arm ; name ## _arm:
169#else
170 #define DEFINE_FUNCTION_ARM(name) \
171 .globl name ; name: ; .globl name ## _arm ; name ## _arm:
172#endif
173
174.macro SWITCH_FROM_THUMB_TO_ARM
175#ifdef __thumb__
176.align 2
177 bx pc
178.arm
179#endif /* __thumb__ */
180.endm
181
182.macro SWITCH_FROM_ARM_TO_THUMB REG
183#ifdef __thumb__
184 add \REG, pc, #1
185 bx \REG
186.thumb
187#endif /* __thumb__ */
188.endm
189
190.macro SWITCH_FROM_THUMB_2_TO_ARM
191#ifdef __thumb2__
192.align 2
193 bx pc
194.arm
195#endif /* __thumb__ */
196.endm
197
198.macro SWITCH_FROM_ARM_TO_THUMB_2 REG
199#ifdef __thumb2__
200 add \REG, pc, #1
201 bx \REG
202.thumb
203#endif /* __thumb__ */
204.endm
205
206.macro BLX_TO_THUMB_1 TARGET
207#if defined(__thumb__) && !defined(__thumb2__)
208 add lr, pc, #1
209 bx lr
210.thumb
211 bl \TARGET
212.align 2
213 bx pc
214.arm
215#else
216 bl \TARGET
217#endif
218.endm
219
220.macro GET_SELF_CPU_CONTROL REG
221#ifdef RTEMS_SMP
222 /* Use PL1 only Thread ID Register (TPIDRPRW) */
223 mrc p15, 0, \REG, c13, c0, 4
224#else
225 ldr \REG, =_Per_CPU_Information
226#endif
227.endm
228
231#endif /* _RTEMS_ASM_H */
concat.h
pc
#define pc
pc, used on mips16 *‍/
Definition: regs.h:67
percpu.h