RTEMS: bsps/arm/atsam/include/libchip/include/sams70/component/component_qspi.h Source File

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component_qspi.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70_QSPI_COMPONENT_
31#define _SAMS70_QSPI_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __O uint32_t QSPI_CR;
43 __IO uint32_t QSPI_MR;
44 __I uint32_t QSPI_RDR;
45 __O uint32_t QSPI_TDR;
46 __I uint32_t QSPI_SR;
47 __O uint32_t QSPI_IER;
48 __O uint32_t QSPI_IDR;
49 __I uint32_t QSPI_IMR;
50 __IO uint32_t QSPI_SCR;
51 __I uint32_t Reserved1[3];
52 __IO uint32_t QSPI_IAR;
53 __IO uint32_t QSPI_ICR;
54 __IO uint32_t QSPI_IFR;
55 __I uint32_t Reserved2[1];
56 __IO uint32_t QSPI_SMR;
57 __O uint32_t QSPI_SKR;
58 __I uint32_t Reserved3[39];
59 __IO uint32_t QSPI_WPMR;
60 __I uint32_t QSPI_WPSR;
61} Qspi;
62#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
63/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */
64#define QSPI_CR_QSPIEN (0x1u << 0)
65#define QSPI_CR_QSPIDIS (0x1u << 1)
66#define QSPI_CR_SWRST (0x1u << 7)
67#define QSPI_CR_LASTXFER (0x1u << 24)
68/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */
69#define QSPI_MR_SMM (0x1u << 0)
70#define QSPI_MR_SMM_SPI (0x0u << 0)
71#define QSPI_MR_SMM_MEMORY (0x1u << 0)
72#define QSPI_MR_LLB (0x1u << 1)
73#define QSPI_MR_LLB_DISABLED (0x0u << 1)
74#define QSPI_MR_LLB_ENABLED (0x1u << 1)
75#define QSPI_MR_WDRBT (0x1u << 2)
76#define QSPI_MR_WDRBT_DISABLED (0x0u << 2)
77#define QSPI_MR_WDRBT_ENABLED (0x1u << 2)
78#define QSPI_MR_CSMODE_Pos 4
79#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos)
80#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos)))
81#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4)
82#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4)
83#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4)
84#define QSPI_MR_NBBITS_Pos 8
85#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos)
86#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos)))
87#define QSPI_MR_NBBITS_8_BIT (0x0u << 8)
88#define QSPI_MR_NBBITS_16_BIT (0x8u << 8)
89#define QSPI_MR_DLYBCT_Pos 16
90#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos)
91#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos)))
92#define QSPI_MR_DLYCS_Pos 24
93#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos)
94#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos)))
95/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */
96#define QSPI_RDR_RD_Pos 0
97#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos)
98/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */
99#define QSPI_TDR_TD_Pos 0
100#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos)
101#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos)))
102/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */
103#define QSPI_SR_RDRF (0x1u << 0)
104#define QSPI_SR_TDRE (0x1u << 1)
105#define QSPI_SR_TXEMPTY (0x1u << 2)
106#define QSPI_SR_OVRES (0x1u << 3)
107#define QSPI_SR_CSR (0x1u << 8)
108#define QSPI_SR_CSS (0x1u << 9)
109#define QSPI_SR_INSTRE (0x1u << 10)
110#define QSPI_SR_QSPIENS (0x1u << 24)
111/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */
112#define QSPI_IER_RDRF (0x1u << 0)
113#define QSPI_IER_TDRE (0x1u << 1)
114#define QSPI_IER_TXEMPTY (0x1u << 2)
115#define QSPI_IER_OVRES (0x1u << 3)
116#define QSPI_IER_CSR (0x1u << 8)
117#define QSPI_IER_CSS (0x1u << 9)
118#define QSPI_IER_INSTRE (0x1u << 10)
119/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */
120#define QSPI_IDR_RDRF (0x1u << 0)
121#define QSPI_IDR_TDRE (0x1u << 1)
122#define QSPI_IDR_TXEMPTY (0x1u << 2)
123#define QSPI_IDR_OVRES (0x1u << 3)
124#define QSPI_IDR_CSR (0x1u << 8)
125#define QSPI_IDR_CSS (0x1u << 9)
126#define QSPI_IDR_INSTRE (0x1u << 10)
127/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */
128#define QSPI_IMR_RDRF (0x1u << 0)
129#define QSPI_IMR_TDRE (0x1u << 1)
130#define QSPI_IMR_TXEMPTY (0x1u << 2)
131#define QSPI_IMR_OVRES (0x1u << 3)
132#define QSPI_IMR_CSR (0x1u << 8)
133#define QSPI_IMR_CSS (0x1u << 9)
134#define QSPI_IMR_INSTRE (0x1u << 10)
135/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */
136#define QSPI_SCR_CPOL (0x1u << 0)
137#define QSPI_SCR_CPHA (0x1u << 1)
138#define QSPI_SCR_SCBR_Pos 8
139#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos)
140#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos)))
141#define QSPI_SCR_DLYBS_Pos 16
142#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos)
143#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos)))
144/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */
145#define QSPI_IAR_ADDR_Pos 0
146#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos)
147#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos)))
148/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */
149#define QSPI_ICR_INST_Pos 0
150#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos)
151#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos)))
152#define QSPI_ICR_OPT_Pos 16
153#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos)
154#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos)))
155/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */
156#define QSPI_IFR_WIDTH_Pos 0
157#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos)
158#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos)))
159#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0)
160#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0)
161#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0)
162#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0)
163#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0)
164#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0)
165#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0)
166#define QSPI_IFR_INSTEN (0x1u << 4)
167#define QSPI_IFR_ADDREN (0x1u << 5)
168#define QSPI_IFR_OPTEN (0x1u << 6)
169#define QSPI_IFR_DATAEN (0x1u << 7)
170#define QSPI_IFR_OPTL_Pos 8
171#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos)
172#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos)))
173#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8)
174#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8)
175#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8)
176#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8)
177#define QSPI_IFR_ADDRL (0x1u << 10)
178#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10)
179#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10)
180#define QSPI_IFR_TFRTYP_Pos 12
181#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos)
182#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos)))
183#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12)
184#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12)
185#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12)
186#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12)
187#define QSPI_IFR_CRM (0x1u << 14)
188#define QSPI_IFR_CRM_DISABLED (0x0u << 14)
189#define QSPI_IFR_CRM_ENABLED (0x1u << 14)
190#define QSPI_IFR_NBDUM_Pos 16
191#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos)
192#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos)))
193/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */
194#define QSPI_SMR_SCREN (0x1u << 0)
195#define QSPI_SMR_SCREN_DISABLED (0x0u << 0)
196#define QSPI_SMR_SCREN_ENABLED (0x1u << 0)
197#define QSPI_SMR_RVDIS (0x1u << 1)
198/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */
199#define QSPI_SKR_USRK_Pos 0
200#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos)
201#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos)))
202/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */
203#define QSPI_WPMR_WPEN (0x1u << 0)
204#define QSPI_WPMR_WPKEY_Pos 8
205#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos)
206#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos)))
207#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8)
208/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */
209#define QSPI_WPSR_WPVS (0x1u << 0)
210#define QSPI_WPSR_WPVSRC_Pos 8
211#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos)
214
215
216#endif /* _SAMS70_QSPI_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Qspi
Qspi hardware registers.
Definition: component_qspi.h:41