RTEMS: bsps/arm/atsam/include/libchip/include/mpu.h Source File

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mpu.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _MPU_H_
31#define _MPU_H_
32#ifdef __rtems__
33#include <bsp.h>
34#endif /* __rtems__ */
35
36/*----------------------------------------------------------------------------
37 * Definitions
38 *----------------------------------------------------------------------------*/
39#define ARM_MODE_USR 0x10
40
41#define PRIVILEGE_MODE 0
42#define USER_MODE 1
43
44#define MPU_DEFAULT_ITCM_REGION (1)
45#define MPU_DEFAULT_IFLASH_REGION (2)
46#define MPU_DEFAULT_DTCM_REGION (3)
47#define MPU_DEFAULT_SRAM_REGION_1 (4)
48#define MPU_DEFAULT_SRAM_REGION_2 (5)
49#define MPU_PERIPHERALS_REGION (6)
50#define MPU_EXT_EBI_REGION (7)
51#define MPU_DEFAULT_SDRAM_REGION (8)
52#define MPU_QSPIMEM_REGION (9)
53#define MPU_USBHSRAM_REGION (10)
54#if defined MPU_HAS_NOCACHE_REGION
55 #define MPU_NOCACHE_SRAM_REGION (11)
56#endif
57#define MPU_SYSTEM_REGION (12)
58#ifdef __rtems__
59/* Reserve the region with highest priority for user applications */
60#define MPU_USER_DEFINED_REGION (15)
61#endif /* __rtems__ */
62
63#define MPU_REGION_VALID (0x10)
64#define MPU_REGION_ENABLE (0x01)
65#define MPU_REGION_DISABLE (0x0)
66
67#define MPU_ENABLE (0x1 << MPU_CTRL_ENABLE_Pos)
68#define MPU_HFNMIENA (0x1 << MPU_CTRL_HFNMIENA_Pos)
69#define MPU_PRIVDEFENA (0x1 << MPU_CTRL_PRIVDEFENA_Pos)
70
71
72#define MPU_REGION_BUFFERABLE (0x01 << MPU_RASR_B_Pos)
73#define MPU_REGION_CACHEABLE (0x01 << MPU_RASR_C_Pos)
74#define MPU_REGION_SHAREABLE (0x01 << MPU_RASR_S_Pos)
75
76#define MPU_REGION_EXECUTE_NEVER (0x01 << MPU_RASR_XN_Pos)
77
78#define MPU_AP_NO_ACCESS (0x00 << MPU_RASR_AP_Pos)
79#define MPU_AP_PRIVILEGED_READ_WRITE (0x01 << MPU_RASR_AP_Pos)
80#define MPU_AP_UNPRIVILEGED_READONLY (0x02 << MPU_RASR_AP_Pos)
81#define MPU_AP_FULL_ACCESS (0x03 << MPU_RASR_AP_Pos)
82#define MPU_AP_RES (0x04 << MPU_RASR_AP_Pos)
83#define MPU_AP_PRIVILEGED_READONLY (0x05 << MPU_RASR_AP_Pos)
84#define MPU_AP_READONLY (0x06 << MPU_RASR_AP_Pos)
85#define MPU_AP_READONLY2 (0x07 << MPU_RASR_AP_Pos)
86
87#define MPU_TEX_B000 (0x01 << MPU_RASR_TEX_Pos)
88#define MPU_TEX_B001 (0x01 << MPU_RASR_TEX_Pos)
89#define MPU_TEX_B010 (0x01 << MPU_RASR_TEX_Pos)
90#define MPU_TEX_B011 (0x01 << MPU_RASR_TEX_Pos)
91#define MPU_TEX_B100 (0x01 << MPU_RASR_TEX_Pos)
92#define MPU_TEX_B101 (0x01 << MPU_RASR_TEX_Pos)
93#define MPU_TEX_B110 (0x01 << MPU_RASR_TEX_Pos)
94#define MPU_TEX_B111 (0x01 << MPU_RASR_TEX_Pos)
95
96/* Default memory map
97 Address range Memory region Memory type Shareability Cache policy
98 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT
99 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA
100 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable -
101 0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA
102 0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT
103 0xA0000000- 0xBFFFFFFF Device Device Shareable
104 0xC0000000- 0xDFFFFFFF Device Device Non Shareable
105 0xE0000000- 0xFFFFFFFF System - -
106 */
107
108/********* IFLASH memory macros *********************/
109#ifdef __rtems__
110#define ITCM_START_ADDRESS ((uintptr_t) atsam_memory_itcm_begin)
111#define ITCM_END_ADDRESS ((uintptr_t) atsam_memory_itcm_end - 1)
112#define IFLASH_START_ADDRESS ((uintptr_t) atsam_memory_intflash_begin)
113#define IFLASH_END_ADDRESS ((uintptr_t) atsam_memory_intflash_end - 1)
114#else /* !__rtems__ */
115#define ITCM_START_ADDRESS 0x00000000UL
116#define ITCM_END_ADDRESS 0x003FFFFFUL
117#define IFLASH_START_ADDRESS 0x00400000UL
118#define IFLASH_END_ADDRESS 0x005FFFFFUL
119#endif /* __rtems__ */
120
121
122#define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS)
123#define IFLASH_PRIVILEGE_END_ADDRESS (IFLASH_START_ADDRESS + 0xFFF)
124
125#define IFLASH_UNPRIVILEGE_START_ADDRESS (IFLASH_PRIVILEGE_END_ADDRESS + 1)
126#define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS)
127
128/**************** DTCM *******************************/
129#ifdef __rtems__
130#define DTCM_START_ADDRESS ((uintptr_t) atsam_memory_dtcm_begin)
131#define DTCM_END_ADDRESS ((uintptr_t) atsam_memory_dtcm_end - 1)
132#else /* !__rtems__ */
133#define DTCM_START_ADDRESS 0x20000000UL
134#define DTCM_END_ADDRESS 0x203FFFFFUL
135#endif /* __rtems__ */
136
137
138/******* SRAM memory macros ***************************/
139
140#ifdef __rtems__
141#define SRAM_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin)
142#define SRAM_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1)
143#else /* !__rtems__ */
144#define SRAM_START_ADDRESS 0x20400000UL
145#define SRAM_END_ADDRESS 0x2045FFFFUL
146#endif /* __rtems__ */
147
148#ifndef __rtems__
149#if defined MPU_HAS_NOCACHE_REGION
150 #define NOCACHE_SRAM_REGION_SIZE 0x1000
151#endif
152#endif /* __rtems__ */
153
154/* Regions should be a 2^(N+1) where 4 < N < 31 */
155#ifdef __rtems__
156#define SRAM_FIRST_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin)
157#define SRAM_FIRST_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1)
158#else /* !__rtems__ */
159#define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS)
160#define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB
161#endif /* __rtems__ */
162
163#if defined MPU_HAS_NOCACHE_REGION
164#ifdef __rtems__
165 #define SRAM_NOCACHE_START_ADDRESS ((uintptr_t) atsam_memory_nocache_begin)
166 #define SRAM_NOCACHE_END_ADDRESS ((uintptr_t) atsam_memory_nocache_end - 1)
167 #define NOCACHE_SRAM_REGION_SIZE (SRAM_NOCACHE_END_ADDRESS - SRAM_NOCACHE_START_ADDRESS)
168#else /* !__rtems__ */
169 #define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1)
170 #define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE) // (2^17) 128 - 0x1000 KB
171 #define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1)
172 #define SRAM_NOCACHE_END_ADDRESS (SRAM_END_ADDRESS)
173#endif /* __rtems__ */
174#else
175#ifndef __rtems__
176 #define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS + 1)
177 #define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS) // (2^17) 128 KB
178#endif /* __rtems__ */
179#endif
180/************** Peripherals memory region macros ********/
181#define PERIPHERALS_START_ADDRESS 0x40000000UL
182#define PERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
183#ifdef __rtems__
184#define SYSTEM_START_ADDRESS 0xE0000000UL
185#define SYSTEM_END_ADDRESS 0xFFFFFFFFUL
186#endif /* __rtems__ */
187
188/******* Ext EBI memory macros ***************************/
189#define EXT_EBI_START_ADDRESS 0x60000000UL
190#define EXT_EBI_END_ADDRESS 0x6FFFFFFFUL
191
192/******* Ext-SRAM memory macros ***************************/
193#ifdef __rtems__
194#define SDRAM_START_ADDRESS ((uintptr_t) atsam_memory_sdram_begin)
195#define SDRAM_END_ADDRESS ((uintptr_t) atsam_memory_sdram_end - 1)
196#else /* !__rtems__ */
197#define SDRAM_START_ADDRESS 0x70000000UL
198#define SDRAM_END_ADDRESS 0x7FFFFFFFUL
199#endif /* __rtems__ */
200
201/******* QSPI macros ***************************/
202#ifdef __rtems__
203#define QSPI_START_ADDRESS ((uintptr_t) atsam_memory_qspiflash_begin)
204#define QSPI_END_ADDRESS ((uintptr_t) atsam_memory_qspiflash_end - 1)
205#else /* !__rtems__ */
206#define QSPI_START_ADDRESS 0x80000000UL
207#define QSPI_END_ADDRESS 0x9FFFFFFFUL
208#endif /* __rtems__ */
209
210/************** USBHS_RAM region macros ******************/
211#define USBHSRAM_START_ADDRESS 0xA0100000UL
212#define USBHSRAM_END_ADDRESS 0xA01FFFFFUL
213
214/*----------------------------------------------------------------------------
215 * Export functions
216 *----------------------------------------------------------------------------*/
217void MPU_Enable(uint32_t dwMPUEnable);
218void MPU_SetRegion(uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr);
219void MPU_SetRegionNum(uint32_t dwRegionNum);
220void MPU_DisableRegion(void);
221uint32_t MPU_CalMPURegionSize(uint32_t dwActualSizeInBytes);
222void MPU_UpdateRegions(uint32_t dwRegionNum, uint32_t dwRegionBaseAddr,
223 uint32_t dwRegionAttr);
224
225#endif /* #ifndef _MMU_ */
226
MPU_Enable
void MPU_Enable(uint32_t dwMPUEnable)
Enables the MPU module.
Definition: mpu.c:78
MPU_SetRegion
void MPU_SetRegion(uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr)
Setup a memory region.
Definition: mpu.c:107
MPU_CalMPURegionSize
uint32_t MPU_CalMPURegionSize(uint32_t dwActualSizeInBytes)
Calculate region size for the RASR.
Definition: mpu.c:117
MPU_SetRegionNum
void MPU_SetRegionNum(uint32_t dwRegionNum)
Set active memory region.
Definition: mpu.c:88
MPU_UpdateRegions
void MPU_UpdateRegions(uint32_t dwRegionNum, uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr)
Update MPU regions.
Definition: mpu.c:140
MPU_DisableRegion
void MPU_DisableRegion(void)
Disable the current active region.
Definition: mpu.c:96