RTEMS: bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h File Reference

| RTEMS 5.4-rc2

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Data Structures | Macros | Typedefs
alt_sysmgr.h File Reference
Board Support Packages » ARM » Intel Cyclone V » Contributed Code

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## Data Structures
struct | ALT_SYSMGR_SILICONID1_s
struct | ALT_SYSMGR_SILICONID2_s
struct | ALT_SYSMGR_WDDBG_s
struct | ALT_SYSMGR_BOOT_s
struct | ALT_SYSMGR_HPSINFO_s
struct | ALT_SYSMGR_PARITYINJ_s
struct | ALT_SYSMGR_FPGAINTF_GBL_s
struct | ALT_SYSMGR_FPGAINTF_INDIV_s
struct | ALT_SYSMGR_FPGAINTF_MODULE_s
struct | ALT_SYSMGR_FPGAINTF_s
struct | ALT_SYSMGR_FPGAINTF_raw_s
struct | ALT_SYSMGR_SCANMGR_CTL_s
struct | ALT_SYSMGR_SCANMGR_s
struct | ALT_SYSMGR_SCANMGR_raw_s
struct | ALT_SYSMGR_FRZCTL_VIOCTL_s
struct | ALT_SYSMGR_FRZCTL_HIOCTL_s
struct | ALT_SYSMGR_FRZCTL_SRC_s
struct | ALT_SYSMGR_FRZCTL_HWCTL_s
struct | ALT_SYSMGR_FRZCTL_s
struct | ALT_SYSMGR_FRZCTL_raw_s
struct | ALT_SYSMGR_EMAC_CTL_s
struct | ALT_SYSMGR_EMAC_L3MST_s
struct | ALT_SYSMGR_EMAC_s
struct | ALT_SYSMGR_EMAC_raw_s
struct | ALT_SYSMGR_DMA_CTL_s
struct | ALT_SYSMGR_DMA_PERSECURITY_s
struct | ALT_SYSMGR_DMA_s
struct | ALT_SYSMGR_DMA_raw_s
struct | ALT_SYSMGR_ISW_HANDOFF_s
struct | ALT_SYSMGR_ISW_s
struct | ALT_SYSMGR_ISW_raw_s
struct | ALT_SYSMGR_ROMCODE_CTL_s
struct | ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s
struct | ALT_SYSMGR_ROMCODE_INITSWSTATE_s
struct | ALT_SYSMGR_ROMCODE_INITSWLASTLD_s
struct | ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_s
struct | ALT_SYSMGR_ROMCODE_WARMRAM_EN_s
struct | ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_s
struct | ALT_SYSMGR_ROMCODE_WARMRAM_LEN_s
struct | ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_s
struct | ALT_SYSMGR_ROMCODE_WARMRAM_CRC_s
struct | ALT_SYSMGR_ROMCODE_WARMRAM_s
struct | ALT_SYSMGR_ROMCODE_WARMRAM_raw_s
struct | ALT_SYSMGR_ROMCODE_s
struct | ALT_SYSMGR_ROMCODE_raw_s
struct | ALT_SYSMGR_ROMHW_CTL_s
struct | ALT_SYSMGR_ROMHW_s
struct | ALT_SYSMGR_ROMHW_raw_s
struct | ALT_SYSMGR_SDMMC_CTL_s
struct | ALT_SYSMGR_SDMMC_L3MST_s
struct | ALT_SYSMGR_SDMMC_s
struct | ALT_SYSMGR_SDMMC_raw_s
struct | ALT_SYSMGR_NAND_BOOTSTRAP_s
struct | ALT_SYSMGR_NAND_L3MST_s
struct | ALT_SYSMGR_NAND_s
struct | ALT_SYSMGR_NAND_raw_s
struct | ALT_SYSMGR_USB_L3MST_s
struct | ALT_SYSMGR_USB_s
struct | ALT_SYSMGR_USB_raw_s
struct | ALT_SYSMGR_ECC_L2_s
struct | ALT_SYSMGR_ECC_OCRAM_s
struct | ALT_SYSMGR_ECC_USB0_s
struct | ALT_SYSMGR_ECC_USB1_s
struct | ALT_SYSMGR_ECC_EMAC0_s
struct | ALT_SYSMGR_ECC_EMAC1_s
struct | ALT_SYSMGR_ECC_DMA_s
struct | ALT_SYSMGR_ECC_CAN0_s
struct | ALT_SYSMGR_ECC_CAN1_s
struct | ALT_SYSMGR_ECC_NAND_s
struct | ALT_SYSMGR_ECC_QSPI_s
struct | ALT_SYSMGR_ECC_SDMMC_s
struct | ALT_SYSMGR_ECC_s
struct | ALT_SYSMGR_ECC_raw_s
struct | ALT_SYSMGR_PINMUX_EMACIO0_s
struct | ALT_SYSMGR_PINMUX_EMACIO1_s
struct | ALT_SYSMGR_PINMUX_EMACIO2_s
struct | ALT_SYSMGR_PINMUX_EMACIO3_s
struct | ALT_SYSMGR_PINMUX_EMACIO4_s
struct | ALT_SYSMGR_PINMUX_EMACIO5_s
struct | ALT_SYSMGR_PINMUX_EMACIO6_s
struct | ALT_SYSMGR_PINMUX_EMACIO7_s
struct | ALT_SYSMGR_PINMUX_EMACIO8_s
struct | ALT_SYSMGR_PINMUX_EMACIO9_s
struct | ALT_SYSMGR_PINMUX_EMACIO10_s
struct | ALT_SYSMGR_PINMUX_EMACIO11_s
struct | ALT_SYSMGR_PINMUX_EMACIO12_s
struct | ALT_SYSMGR_PINMUX_EMACIO13_s
struct | ALT_SYSMGR_PINMUX_EMACIO14_s
struct | ALT_SYSMGR_PINMUX_EMACIO15_s
struct | ALT_SYSMGR_PINMUX_EMACIO16_s
struct | ALT_SYSMGR_PINMUX_EMACIO17_s
struct | ALT_SYSMGR_PINMUX_EMACIO18_s
struct | ALT_SYSMGR_PINMUX_EMACIO19_s
struct | ALT_SYSMGR_PINMUX_FLSHIO0_s
struct | ALT_SYSMGR_PINMUX_FLSHIO1_s
struct | ALT_SYSMGR_PINMUX_FLSHIO2_s
struct | ALT_SYSMGR_PINMUX_FLSHIO3_s
struct | ALT_SYSMGR_PINMUX_FLSHIO4_s
struct | ALT_SYSMGR_PINMUX_FLSHIO5_s
struct | ALT_SYSMGR_PINMUX_FLSHIO6_s
struct | ALT_SYSMGR_PINMUX_FLSHIO7_s
struct | ALT_SYSMGR_PINMUX_FLSHIO8_s
struct | ALT_SYSMGR_PINMUX_FLSHIO9_s
struct | ALT_SYSMGR_PINMUX_FLSHIO10_s
struct | ALT_SYSMGR_PINMUX_FLSHIO11_s
struct | ALT_SYSMGR_PINMUX_GENERALIO0_s
struct | ALT_SYSMGR_PINMUX_GENERALIO1_s
struct | ALT_SYSMGR_PINMUX_GENERALIO2_s
struct | ALT_SYSMGR_PINMUX_GENERALIO3_s
struct | ALT_SYSMGR_PINMUX_GENERALIO4_s
struct | ALT_SYSMGR_PINMUX_GENERALIO5_s
struct | ALT_SYSMGR_PINMUX_GENERALIO6_s
struct | ALT_SYSMGR_PINMUX_GENERALIO7_s
struct | ALT_SYSMGR_PINMUX_GENERALIO8_s
struct | ALT_SYSMGR_PINMUX_GENERALIO9_s
struct | ALT_SYSMGR_PINMUX_GENERALIO10_s
struct | ALT_SYSMGR_PINMUX_GENERALIO11_s
struct | ALT_SYSMGR_PINMUX_GENERALIO12_s
struct | ALT_SYSMGR_PINMUX_GENERALIO13_s
struct | ALT_SYSMGR_PINMUX_GENERALIO14_s
struct | ALT_SYSMGR_PINMUX_GENERALIO15_s
struct | ALT_SYSMGR_PINMUX_GENERALIO16_s
struct | ALT_SYSMGR_PINMUX_GENERALIO17_s
struct | ALT_SYSMGR_PINMUX_GENERALIO18_s
struct | ALT_SYSMGR_PINMUX_GENERALIO19_s
struct | ALT_SYSMGR_PINMUX_GENERALIO20_s
struct | ALT_SYSMGR_PINMUX_GENERALIO21_s
struct | ALT_SYSMGR_PINMUX_GENERALIO22_s
struct | ALT_SYSMGR_PINMUX_GENERALIO23_s
struct | ALT_SYSMGR_PINMUX_GENERALIO24_s
struct | ALT_SYSMGR_PINMUX_GENERALIO25_s
struct | ALT_SYSMGR_PINMUX_GENERALIO26_s
struct | ALT_SYSMGR_PINMUX_GENERALIO27_s
struct | ALT_SYSMGR_PINMUX_GENERALIO28_s
struct | ALT_SYSMGR_PINMUX_GENERALIO29_s
struct | ALT_SYSMGR_PINMUX_GENERALIO30_s
struct | ALT_SYSMGR_PINMUX_GENERALIO31_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO0_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO1_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO2_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO3_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO4_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO5_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO6_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO7_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO8_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO9_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO10_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO11_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO12_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO13_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO14_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO15_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO16_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO17_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO18_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO19_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO20_s
struct | ALT_SYSMGR_PINMUX_MIXED1IO21_s
struct | ALT_SYSMGR_PINMUX_MIXED2IO0_s
struct | ALT_SYSMGR_PINMUX_MIXED2IO1_s
struct | ALT_SYSMGR_PINMUX_MIXED2IO2_s
struct | ALT_SYSMGR_PINMUX_MIXED2IO3_s
struct | ALT_SYSMGR_PINMUX_MIXED2IO4_s
struct | ALT_SYSMGR_PINMUX_MIXED2IO5_s
struct | ALT_SYSMGR_PINMUX_MIXED2IO6_s
struct | ALT_SYSMGR_PINMUX_MIXED2IO7_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX48_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX49_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX50_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX51_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX52_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX53_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX54_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX55_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX56_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX57_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX58_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX59_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX60_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX61_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX62_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX63_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX64_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX65_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX66_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX67_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX68_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX69_s
struct | ALT_SYSMGR_PINMUX_GPLINMUX70_s
struct | ALT_SYSMGR_PINMUX_GPLMUX0_s
struct | ALT_SYSMGR_PINMUX_GPLMUX1_s
struct | ALT_SYSMGR_PINMUX_GPLMUX2_s
struct | ALT_SYSMGR_PINMUX_GPLMUX3_s
struct | ALT_SYSMGR_PINMUX_GPLMUX4_s
struct | ALT_SYSMGR_PINMUX_GPLMUX5_s
struct | ALT_SYSMGR_PINMUX_GPLMUX6_s
struct | ALT_SYSMGR_PINMUX_GPLMUX7_s
struct | ALT_SYSMGR_PINMUX_GPLMUX8_s
struct | ALT_SYSMGR_PINMUX_GPLMUX9_s
struct | ALT_SYSMGR_PINMUX_GPLMUX10_s
struct | ALT_SYSMGR_PINMUX_GPLMUX11_s
struct | ALT_SYSMGR_PINMUX_GPLMUX12_s
struct | ALT_SYSMGR_PINMUX_GPLMUX13_s
struct | ALT_SYSMGR_PINMUX_GPLMUX14_s
struct | ALT_SYSMGR_PINMUX_GPLMUX15_s
struct | ALT_SYSMGR_PINMUX_GPLMUX16_s
struct | ALT_SYSMGR_PINMUX_GPLMUX17_s
struct | ALT_SYSMGR_PINMUX_GPLMUX18_s
struct | ALT_SYSMGR_PINMUX_GPLMUX19_s
struct | ALT_SYSMGR_PINMUX_GPLMUX20_s
struct | ALT_SYSMGR_PINMUX_GPLMUX21_s
struct | ALT_SYSMGR_PINMUX_GPLMUX22_s
struct | ALT_SYSMGR_PINMUX_GPLMUX23_s
struct | ALT_SYSMGR_PINMUX_GPLMUX24_s
struct | ALT_SYSMGR_PINMUX_GPLMUX25_s
struct | ALT_SYSMGR_PINMUX_GPLMUX26_s
struct | ALT_SYSMGR_PINMUX_GPLMUX27_s
struct | ALT_SYSMGR_PINMUX_GPLMUX28_s
struct | ALT_SYSMGR_PINMUX_GPLMUX29_s
struct | ALT_SYSMGR_PINMUX_GPLMUX30_s
struct | ALT_SYSMGR_PINMUX_GPLMUX31_s
struct | ALT_SYSMGR_PINMUX_GPLMUX32_s
struct | ALT_SYSMGR_PINMUX_GPLMUX33_s
struct | ALT_SYSMGR_PINMUX_GPLMUX34_s
struct | ALT_SYSMGR_PINMUX_GPLMUX35_s
struct | ALT_SYSMGR_PINMUX_GPLMUX36_s
struct | ALT_SYSMGR_PINMUX_GPLMUX37_s
struct | ALT_SYSMGR_PINMUX_GPLMUX38_s
struct | ALT_SYSMGR_PINMUX_GPLMUX39_s
struct | ALT_SYSMGR_PINMUX_GPLMUX40_s
struct | ALT_SYSMGR_PINMUX_GPLMUX41_s
struct | ALT_SYSMGR_PINMUX_GPLMUX42_s
struct | ALT_SYSMGR_PINMUX_GPLMUX43_s
struct | ALT_SYSMGR_PINMUX_GPLMUX44_s
struct | ALT_SYSMGR_PINMUX_GPLMUX45_s
struct | ALT_SYSMGR_PINMUX_GPLMUX46_s
struct | ALT_SYSMGR_PINMUX_GPLMUX47_s
struct | ALT_SYSMGR_PINMUX_GPLMUX48_s
struct | ALT_SYSMGR_PINMUX_GPLMUX49_s
struct | ALT_SYSMGR_PINMUX_GPLMUX50_s
struct | ALT_SYSMGR_PINMUX_GPLMUX51_s
struct | ALT_SYSMGR_PINMUX_GPLMUX52_s
struct | ALT_SYSMGR_PINMUX_GPLMUX53_s
struct | ALT_SYSMGR_PINMUX_GPLMUX54_s
struct | ALT_SYSMGR_PINMUX_GPLMUX55_s
struct | ALT_SYSMGR_PINMUX_GPLMUX56_s
struct | ALT_SYSMGR_PINMUX_GPLMUX57_s
struct | ALT_SYSMGR_PINMUX_GPLMUX58_s
struct | ALT_SYSMGR_PINMUX_GPLMUX59_s
struct | ALT_SYSMGR_PINMUX_GPLMUX60_s
struct | ALT_SYSMGR_PINMUX_GPLMUX61_s
struct | ALT_SYSMGR_PINMUX_GPLMUX62_s
struct | ALT_SYSMGR_PINMUX_GPLMUX63_s
struct | ALT_SYSMGR_PINMUX_GPLMUX64_s
struct | ALT_SYSMGR_PINMUX_GPLMUX65_s
struct | ALT_SYSMGR_PINMUX_GPLMUX66_s
struct | ALT_SYSMGR_PINMUX_GPLMUX67_s
struct | ALT_SYSMGR_PINMUX_GPLMUX68_s
struct | ALT_SYSMGR_PINMUX_GPLMUX69_s
struct | ALT_SYSMGR_PINMUX_GPLMUX70_s
struct | ALT_SYSMGR_PINMUX_NANDUSEFPGA_s
struct | ALT_SYSMGR_PINMUX_RGMII1USEFPGA_s
struct | ALT_SYSMGR_PINMUX_I2C0USEFPGA_s
struct | ALT_SYSMGR_PINMUX_RGMII0USEFPGA_s
struct | ALT_SYSMGR_PINMUX_I2C3USEFPGA_s
struct | ALT_SYSMGR_PINMUX_I2C2USEFPGA_s
struct | ALT_SYSMGR_PINMUX_I2C1USEFPGA_s
struct | ALT_SYSMGR_PINMUX_SPIM1USEFPGA_s
struct | ALT_SYSMGR_PINMUX_SPIM0USEFPGA_s
struct | ALT_SYSMGR_PINMUX_s
struct | ALT_SYSMGR_PINMUX_raw_s
struct | ALT_SYSMGR_s
struct | ALT_SYSMGR_raw_s

## Macros
#define | ALT_SYSMGR_SILICONID1_REV_E_REV1 0x1
#define | ALT_SYSMGR_SILICONID1_REV_LSB 0
#define | ALT_SYSMGR_SILICONID1_REV_MSB 15
#define | ALT_SYSMGR_SILICONID1_REV_WIDTH 16
#define | ALT_SYSMGR_SILICONID1_REV_SET_MSK 0x0000ffff
#define | ALT_SYSMGR_SILICONID1_REV_CLR_MSK 0xffff0000
#define | ALT_SYSMGR_SILICONID1_REV_RESET 0x1
#define | ALT_SYSMGR_SILICONID1_REV_GET(value) (((value) & 0x0000ffff) >> 0)
#define | ALT_SYSMGR_SILICONID1_REV_SET(value) (((value) << 0) & 0x0000ffff)
#define | ALT_SYSMGR_SILICONID1_ID_E_CYCLONEV_ARRIAV 0x0
#define | ALT_SYSMGR_SILICONID1_ID_LSB 16
#define | ALT_SYSMGR_SILICONID1_ID_MSB 31
#define | ALT_SYSMGR_SILICONID1_ID_WIDTH 16
#define | ALT_SYSMGR_SILICONID1_ID_SET_MSK 0xffff0000
#define | ALT_SYSMGR_SILICONID1_ID_CLR_MSK 0x0000ffff
#define | ALT_SYSMGR_SILICONID1_ID_RESET 0x0
#define | ALT_SYSMGR_SILICONID1_ID_GET(value) (((value) & 0xffff0000) >> 16)
#define | ALT_SYSMGR_SILICONID1_ID_SET(value) (((value) << 16) & 0xffff0000)
#define | ALT_SYSMGR_SILICONID1_OFST 0x0
#define | ALT_SYSMGR_SILICONID2_RSV_LSB 0
#define | ALT_SYSMGR_SILICONID2_RSV_MSB 31
#define | ALT_SYSMGR_SILICONID2_RSV_WIDTH 32
#define | ALT_SYSMGR_SILICONID2_RSV_SET_MSK 0xffffffff
#define | ALT_SYSMGR_SILICONID2_RSV_CLR_MSK 0x00000000
#define | ALT_SYSMGR_SILICONID2_RSV_RESET 0x0
#define | ALT_SYSMGR_SILICONID2_RSV_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_SYSMGR_SILICONID2_RSV_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_SYSMGR_SILICONID2_OFST 0x4
#define | ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE 0x0
#define | ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 0x1
#define | ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 0x2
#define | ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER 0x3
#define | ALT_SYSMGR_WDDBG_MOD_0_LSB 0
#define | ALT_SYSMGR_WDDBG_MOD_0_MSB 1
#define | ALT_SYSMGR_WDDBG_MOD_0_WIDTH 2
#define | ALT_SYSMGR_WDDBG_MOD_0_SET_MSK 0x00000003
#define | ALT_SYSMGR_WDDBG_MOD_0_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_WDDBG_MOD_0_RESET 0x3
#define | ALT_SYSMGR_WDDBG_MOD_0_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_WDDBG_MOD_0_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE 0x0
#define | ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 0x1
#define | ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 0x2
#define | ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER 0x3
#define | ALT_SYSMGR_WDDBG_MOD_1_LSB 2
#define | ALT_SYSMGR_WDDBG_MOD_1_MSB 3
#define | ALT_SYSMGR_WDDBG_MOD_1_WIDTH 2
#define | ALT_SYSMGR_WDDBG_MOD_1_SET_MSK 0x0000000c
#define | ALT_SYSMGR_WDDBG_MOD_1_CLR_MSK 0xfffffff3
#define | ALT_SYSMGR_WDDBG_MOD_1_RESET 0x3
#define | ALT_SYSMGR_WDDBG_MOD_1_GET(value) (((value) & 0x0000000c) >> 2)
#define | ALT_SYSMGR_WDDBG_MOD_1_SET(value) (((value) << 2) & 0x0000000c)
#define | ALT_SYSMGR_WDDBG_OFST 0x10
#define | ALT_SYSMGR_BOOT_BSEL_E_RSVD 0x0
#define | ALT_SYSMGR_BOOT_BSEL_E_FPGA 0x1
#define | ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V 0x2
#define | ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V 0x3
#define | ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4
#define | ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5
#define | ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V 0x6
#define | ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V 0x7
#define | ALT_SYSMGR_BOOT_BSEL_LSB 0
#define | ALT_SYSMGR_BOOT_BSEL_MSB 2
#define | ALT_SYSMGR_BOOT_BSEL_WIDTH 3
#define | ALT_SYSMGR_BOOT_BSEL_SET_MSK 0x00000007
#define | ALT_SYSMGR_BOOT_BSEL_CLR_MSK 0xfffffff8
#define | ALT_SYSMGR_BOOT_BSEL_RESET 0x0
#define | ALT_SYSMGR_BOOT_BSEL_GET(value) (((value) & 0x00000007) >> 0)
#define | ALT_SYSMGR_BOOT_BSEL_SET(value) (((value) << 0) & 0x00000007)
#define | ALT_SYSMGR_BOOT_CSEL_E_CSEL_0 0x0
#define | ALT_SYSMGR_BOOT_CSEL_E_CSEL_1 0x1
#define | ALT_SYSMGR_BOOT_CSEL_E_CSEL_2 0x2
#define | ALT_SYSMGR_BOOT_CSEL_E_CSEL_3 0x3
#define | ALT_SYSMGR_BOOT_CSEL_LSB 3
#define | ALT_SYSMGR_BOOT_CSEL_MSB 4
#define | ALT_SYSMGR_BOOT_CSEL_WIDTH 2
#define | ALT_SYSMGR_BOOT_CSEL_SET_MSK 0x00000018
#define | ALT_SYSMGR_BOOT_CSEL_CLR_MSK 0xffffffe7
#define | ALT_SYSMGR_BOOT_CSEL_RESET 0x0
#define | ALT_SYSMGR_BOOT_CSEL_GET(value) (((value) & 0x00000018) >> 3)
#define | ALT_SYSMGR_BOOT_CSEL_SET(value) (((value) << 3) & 0x00000018)
#define | ALT_SYSMGR_BOOT_PINBSEL_LSB 5
#define | ALT_SYSMGR_BOOT_PINBSEL_MSB 7
#define | ALT_SYSMGR_BOOT_PINBSEL_WIDTH 3
#define | ALT_SYSMGR_BOOT_PINBSEL_SET_MSK 0x000000e0
#define | ALT_SYSMGR_BOOT_PINBSEL_CLR_MSK 0xffffff1f
#define | ALT_SYSMGR_BOOT_PINBSEL_RESET 0x0
#define | ALT_SYSMGR_BOOT_PINBSEL_GET(value) (((value) & 0x000000e0) >> 5)
#define | ALT_SYSMGR_BOOT_PINBSEL_SET(value) (((value) << 5) & 0x000000e0)
#define | ALT_SYSMGR_BOOT_PINCSEL_LSB 8
#define | ALT_SYSMGR_BOOT_PINCSEL_MSB 9
#define | ALT_SYSMGR_BOOT_PINCSEL_WIDTH 2
#define | ALT_SYSMGR_BOOT_PINCSEL_SET_MSK 0x00000300
#define | ALT_SYSMGR_BOOT_PINCSEL_CLR_MSK 0xfffffcff
#define | ALT_SYSMGR_BOOT_PINCSEL_RESET 0x0
#define | ALT_SYSMGR_BOOT_PINCSEL_GET(value) (((value) & 0x00000300) >> 8)
#define | ALT_SYSMGR_BOOT_PINCSEL_SET(value) (((value) << 8) & 0x00000300)
#define | ALT_SYSMGR_BOOT_OFST 0x14
#define | ALT_SYSMGR_HPSINFO_DUALCORE_E_SINGLECORE 0x0
#define | ALT_SYSMGR_HPSINFO_DUALCORE_E_DUALCORE 0x1
#define | ALT_SYSMGR_HPSINFO_DUALCORE_LSB 0
#define | ALT_SYSMGR_HPSINFO_DUALCORE_MSB 0
#define | ALT_SYSMGR_HPSINFO_DUALCORE_WIDTH 1
#define | ALT_SYSMGR_HPSINFO_DUALCORE_SET_MSK 0x00000001
#define | ALT_SYSMGR_HPSINFO_DUALCORE_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_HPSINFO_DUALCORE_RESET 0x0
#define | ALT_SYSMGR_HPSINFO_DUALCORE_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_HPSINFO_DUALCORE_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_HPSINFO_CAN_E_CAN_UNAVAILABLE 0x0
#define | ALT_SYSMGR_HPSINFO_CAN_E_CAN_AVAILABLE 0x1
#define | ALT_SYSMGR_HPSINFO_CAN_LSB 1
#define | ALT_SYSMGR_HPSINFO_CAN_MSB 1
#define | ALT_SYSMGR_HPSINFO_CAN_WIDTH 1
#define | ALT_SYSMGR_HPSINFO_CAN_SET_MSK 0x00000002
#define | ALT_SYSMGR_HPSINFO_CAN_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_HPSINFO_CAN_RESET 0x0
#define | ALT_SYSMGR_HPSINFO_CAN_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_HPSINFO_CAN_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_HPSINFO_OFST 0x18
#define | ALT_SYSMGR_PARITYINJ_DCDATA_0_LSB 0
#define | ALT_SYSMGR_PARITYINJ_DCDATA_0_MSB 0
#define | ALT_SYSMGR_PARITYINJ_DCDATA_0_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_DCDATA_0_SET_MSK 0x00000001
#define | ALT_SYSMGR_PARITYINJ_DCDATA_0_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PARITYINJ_DCDATA_0_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_DCDATA_0_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PARITYINJ_DCDATA_0_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PARITYINJ_DCDATA_1_LSB 1
#define | ALT_SYSMGR_PARITYINJ_DCDATA_1_MSB 1
#define | ALT_SYSMGR_PARITYINJ_DCDATA_1_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_DCDATA_1_SET_MSK 0x00000002
#define | ALT_SYSMGR_PARITYINJ_DCDATA_1_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_PARITYINJ_DCDATA_1_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_DCDATA_1_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_PARITYINJ_DCDATA_1_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_PARITYINJ_DCTAG_0_LSB 2
#define | ALT_SYSMGR_PARITYINJ_DCTAG_0_MSB 2
#define | ALT_SYSMGR_PARITYINJ_DCTAG_0_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_DCTAG_0_SET_MSK 0x00000004
#define | ALT_SYSMGR_PARITYINJ_DCTAG_0_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_PARITYINJ_DCTAG_0_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_DCTAG_0_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_PARITYINJ_DCTAG_0_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_PARITYINJ_DCTAG_1_LSB 3
#define | ALT_SYSMGR_PARITYINJ_DCTAG_1_MSB 3
#define | ALT_SYSMGR_PARITYINJ_DCTAG_1_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_DCTAG_1_SET_MSK 0x00000008
#define | ALT_SYSMGR_PARITYINJ_DCTAG_1_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_PARITYINJ_DCTAG_1_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_DCTAG_1_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_PARITYINJ_DCTAG_1_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_0_LSB 4
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_0_MSB 4
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_0_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET_MSK 0x00000010
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_0_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_0_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_0_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_1_LSB 5
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_1_MSB 5
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_1_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET_MSK 0x00000020
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_1_CLR_MSK 0xffffffdf
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_1_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_1_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_0_LSB 6
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_0_MSB 6
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_0_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET_MSK 0x00000040
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_0_CLR_MSK 0xffffffbf
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_0_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_0_GET(value) (((value) & 0x00000040) >> 6)
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET(value) (((value) << 6) & 0x00000040)
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_1_LSB 7
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_1_MSB 7
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_1_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET_MSK 0x00000080
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_1_CLR_MSK 0xffffff7f
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_1_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_1_GET(value) (((value) & 0x00000080) >> 7)
#define | ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET(value) (((value) << 7) & 0x00000080)
#define | ALT_SYSMGR_PARITYINJ_ICDATA_0_LSB 8
#define | ALT_SYSMGR_PARITYINJ_ICDATA_0_MSB 8
#define | ALT_SYSMGR_PARITYINJ_ICDATA_0_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_ICDATA_0_SET_MSK 0x00000100
#define | ALT_SYSMGR_PARITYINJ_ICDATA_0_CLR_MSK 0xfffffeff
#define | ALT_SYSMGR_PARITYINJ_ICDATA_0_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_ICDATA_0_GET(value) (((value) & 0x00000100) >> 8)
#define | ALT_SYSMGR_PARITYINJ_ICDATA_0_SET(value) (((value) << 8) & 0x00000100)
#define | ALT_SYSMGR_PARITYINJ_ICDATA_1_LSB 9
#define | ALT_SYSMGR_PARITYINJ_ICDATA_1_MSB 9
#define | ALT_SYSMGR_PARITYINJ_ICDATA_1_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_ICDATA_1_SET_MSK 0x00000200
#define | ALT_SYSMGR_PARITYINJ_ICDATA_1_CLR_MSK 0xfffffdff
#define | ALT_SYSMGR_PARITYINJ_ICDATA_1_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_ICDATA_1_GET(value) (((value) & 0x00000200) >> 9)
#define | ALT_SYSMGR_PARITYINJ_ICDATA_1_SET(value) (((value) << 9) & 0x00000200)
#define | ALT_SYSMGR_PARITYINJ_ICTAG_0_LSB 10
#define | ALT_SYSMGR_PARITYINJ_ICTAG_0_MSB 10
#define | ALT_SYSMGR_PARITYINJ_ICTAG_0_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_ICTAG_0_SET_MSK 0x00000400
#define | ALT_SYSMGR_PARITYINJ_ICTAG_0_CLR_MSK 0xfffffbff
#define | ALT_SYSMGR_PARITYINJ_ICTAG_0_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_ICTAG_0_GET(value) (((value) & 0x00000400) >> 10)
#define | ALT_SYSMGR_PARITYINJ_ICTAG_0_SET(value) (((value) << 10) & 0x00000400)
#define | ALT_SYSMGR_PARITYINJ_ICTAG_1_LSB 11
#define | ALT_SYSMGR_PARITYINJ_ICTAG_1_MSB 11
#define | ALT_SYSMGR_PARITYINJ_ICTAG_1_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_ICTAG_1_SET_MSK 0x00000800
#define | ALT_SYSMGR_PARITYINJ_ICTAG_1_CLR_MSK 0xfffff7ff
#define | ALT_SYSMGR_PARITYINJ_ICTAG_1_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_ICTAG_1_GET(value) (((value) & 0x00000800) >> 11)
#define | ALT_SYSMGR_PARITYINJ_ICTAG_1_SET(value) (((value) << 11) & 0x00000800)
#define | ALT_SYSMGR_PARITYINJ_GHB_0_LSB 12
#define | ALT_SYSMGR_PARITYINJ_GHB_0_MSB 12
#define | ALT_SYSMGR_PARITYINJ_GHB_0_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_GHB_0_SET_MSK 0x00001000
#define | ALT_SYSMGR_PARITYINJ_GHB_0_CLR_MSK 0xffffefff
#define | ALT_SYSMGR_PARITYINJ_GHB_0_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_GHB_0_GET(value) (((value) & 0x00001000) >> 12)
#define | ALT_SYSMGR_PARITYINJ_GHB_0_SET(value) (((value) << 12) & 0x00001000)
#define | ALT_SYSMGR_PARITYINJ_GHB_1_LSB 13
#define | ALT_SYSMGR_PARITYINJ_GHB_1_MSB 13
#define | ALT_SYSMGR_PARITYINJ_GHB_1_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_GHB_1_SET_MSK 0x00002000
#define | ALT_SYSMGR_PARITYINJ_GHB_1_CLR_MSK 0xffffdfff
#define | ALT_SYSMGR_PARITYINJ_GHB_1_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_GHB_1_GET(value) (((value) & 0x00002000) >> 13)
#define | ALT_SYSMGR_PARITYINJ_GHB_1_SET(value) (((value) << 13) & 0x00002000)
#define | ALT_SYSMGR_PARITYINJ_BTAC_0_LSB 14
#define | ALT_SYSMGR_PARITYINJ_BTAC_0_MSB 14
#define | ALT_SYSMGR_PARITYINJ_BTAC_0_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_BTAC_0_SET_MSK 0x00004000
#define | ALT_SYSMGR_PARITYINJ_BTAC_0_CLR_MSK 0xffffbfff
#define | ALT_SYSMGR_PARITYINJ_BTAC_0_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_BTAC_0_GET(value) (((value) & 0x00004000) >> 14)
#define | ALT_SYSMGR_PARITYINJ_BTAC_0_SET(value) (((value) << 14) & 0x00004000)
#define | ALT_SYSMGR_PARITYINJ_BTAC_1_LSB 15
#define | ALT_SYSMGR_PARITYINJ_BTAC_1_MSB 15
#define | ALT_SYSMGR_PARITYINJ_BTAC_1_WIDTH 1
#define | ALT_SYSMGR_PARITYINJ_BTAC_1_SET_MSK 0x00008000
#define | ALT_SYSMGR_PARITYINJ_BTAC_1_CLR_MSK 0xffff7fff
#define | ALT_SYSMGR_PARITYINJ_BTAC_1_RESET 0x0
#define | ALT_SYSMGR_PARITYINJ_BTAC_1_GET(value) (((value) & 0x00008000) >> 15)
#define | ALT_SYSMGR_PARITYINJ_BTAC_1_SET(value) (((value) << 15) & 0x00008000)
#define | ALT_SYSMGR_PARITYINJ_OFST 0x1c
#define | ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS 0x0
#define | ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN 0x1
#define | ALT_SYSMGR_FPGAINTF_GBL_INTF_LSB 0
#define | ALT_SYSMGR_FPGAINTF_GBL_INTF_MSB 0
#define | ALT_SYSMGR_FPGAINTF_GBL_INTF_WIDTH 1
#define | ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK 0x00000001
#define | ALT_SYSMGR_FPGAINTF_GBL_INTF_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_FPGAINTF_GBL_INTF_RESET 0x1
#define | ALT_SYSMGR_FPGAINTF_GBL_INTF_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_FPGAINTF_GBL_INTF_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_FPGAINTF_GBL_OFST 0x0
#define | ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS 0x0
#define | ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN 0x1
#define | ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_LSB 0
#define | ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_MSB 0
#define | ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_WIDTH 1
#define | ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK 0x00000001
#define | ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_RESET 0x1
#define | ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS 0x0
#define | ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN 0x1
#define | ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_LSB 1
#define | ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_MSB 1
#define | ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_WIDTH 1
#define | ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK 0x00000002
#define | ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_RESET 0x1
#define | ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS 0x0
#define | ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN 0x1
#define | ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_LSB 2
#define | ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_MSB 2
#define | ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_WIDTH 1
#define | ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK 0x00000004
#define | ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_RESET 0x1
#define | ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS 0x0
#define | ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN 0x1
#define | ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_LSB 3
#define | ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_MSB 3
#define | ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_WIDTH 1
#define | ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK 0x00000008
#define | ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_RESET 0x1
#define | ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS 0x0
#define | ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN 0x1
#define | ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_LSB 4
#define | ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_MSB 4
#define | ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_WIDTH 1
#define | ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK 0x00000010
#define | ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_RESET 0x1
#define | ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS 0x0
#define | ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN 0x1
#define | ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_LSB 6
#define | ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_MSB 6
#define | ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_WIDTH 1
#define | ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK 0x00000040
#define | ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_CLR_MSK 0xffffffbf
#define | ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_RESET 0x1
#define | ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_GET(value) (((value) & 0x00000040) >> 6)
#define | ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET(value) (((value) << 6) & 0x00000040)
#define | ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS 0x0
#define | ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN 0x1
#define | ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_LSB 7
#define | ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_MSB 7
#define | ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_WIDTH 1
#define | ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK 0x00000080
#define | ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_CLR_MSK 0xffffff7f
#define | ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_RESET 0x1
#define | ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_GET(value) (((value) & 0x00000080) >> 7)
#define | ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET(value) (((value) << 7) & 0x00000080)
#define | ALT_SYSMGR_FPGAINTF_INDIV_OFST 0x4
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_DIS 0x0
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_EN 0x1
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_LSB 2
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_MSB 2
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_WIDTH 1
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK 0x00000004
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_RESET 0x0
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_DIS 0x0
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_EN 0x1
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_LSB 3
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_MSB 3
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_WIDTH 1
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK 0x00000008
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_RESET 0x0
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_FPGAINTF_MODULE_OFST 0x8
#define | ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS 0x0
#define | ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR 0x1
#define | ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_LSB 0
#define | ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_MSB 0
#define | ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_WIDTH 1
#define | ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET_MSK 0x00000001
#define | ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_RESET 0x0
#define | ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_SCANMGR_CTL_OFST 0x0
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS 0x0
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG 0x1
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_LSB 0
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_MSB 0
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET_MSK 0x00000001
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_RESET 0x0
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS 0x0
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG 0x1
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_LSB 1
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_MSB 1
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET_MSK 0x00000002
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_RESET 0x0
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN 0x0
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG 0x1
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_LSB 2
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_MSB 2
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET_MSK 0x00000004
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_RESET 0x0
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN 0x0
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG 0x1
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_LSB 3
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_MSB 3
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET_MSK 0x00000008
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_RESET 0x0
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW 0x0
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG 0x1
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_LSB 4
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_MSB 4
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET_MSK 0x00000010
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_RESET 0x0
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_FRZCTL_VIOCTL_OFST 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG 0x1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_LSB 0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_MSB 0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET_MSK 0x00000001
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_RESET 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG 0x1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_LSB 1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_MSB 1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET_MSK 0x00000002
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_RESET 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG 0x1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_LSB 2
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_MSB 2
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET_MSK 0x00000004
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_RESET 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG 0x1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_LSB 3
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_MSB 3
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET_MSK 0x00000008
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_RESET 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG 0x1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_LSB 4
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_MSB 4
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET_MSK 0x00000010
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_RESET 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN 0x1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_LSB 5
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_MSB 5
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET_MSK 0x00000020
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_CLR_MSK 0xffffffdf
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_RESET 0x1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN 0x1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_LSB 6
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_MSB 6
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET_MSK 0x00000040
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_CLR_MSK 0xffffffbf
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_RESET 0x1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_GET(value) (((value) & 0x00000040) >> 6)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET(value) (((value) << 6) & 0x00000040)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN 0x1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_LSB 7
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_MSB 7
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET_MSK 0x00000080
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_CLR_MSK 0xffffff7f
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_RESET 0x1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_GET(value) (((value) & 0x00000080) >> 7)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET(value) (((value) << 7) & 0x00000080)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN 0x1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_LSB 8
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_MSB 8
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET_MSK 0x00000100
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_CLR_MSK 0xfffffeff
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_RESET 0x0
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_GET(value) (((value) & 0x00000100) >> 8)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET(value) (((value) << 8) & 0x00000100)
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OFST 0x10
#define | ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW 0x0
#define | ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW 0x1
#define | ALT_SYSMGR_FRZCTL_SRC_VIO1_LSB 0
#define | ALT_SYSMGR_FRZCTL_SRC_VIO1_MSB 0
#define | ALT_SYSMGR_FRZCTL_SRC_VIO1_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_SRC_VIO1_SET_MSK 0x00000001
#define | ALT_SYSMGR_FRZCTL_SRC_VIO1_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_FRZCTL_SRC_VIO1_RESET 0x0
#define | ALT_SYSMGR_FRZCTL_SRC_VIO1_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_FRZCTL_SRC_VIO1_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_FRZCTL_SRC_OFST 0x14
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW 0x0
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ 0x1
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_LSB 0
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_MSB 0
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_WIDTH 1
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET_MSK 0x00000001
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_RESET 0x1
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN 0x0
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED 0x1
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN 0x2
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED 0x3
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_LSB 1
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_MSB 2
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_WIDTH 2
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET_MSK 0x00000006
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_CLR_MSK 0xfffffff9
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_RESET 0x2
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_GET(value) (((value) & 0x00000006) >> 1)
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET(value) (((value) << 1) & 0x00000006)
#define | ALT_SYSMGR_FRZCTL_HWCTL_OFST 0x18
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII 0x0
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII 0x1
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII 0x2
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_LSB 0
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_MSB 1
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_WIDTH 2
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET_MSK 0x00000003
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_RESET 0x2
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII 0x0
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII 0x1
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII 0x2
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_LSB 2
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_MSB 3
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_WIDTH 2
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET_MSK 0x0000000c
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_CLR_MSK 0xfffffff3
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_RESET 0x2
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_GET(value) (((value) & 0x0000000c) >> 2)
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET(value) (((value) << 2) & 0x0000000c)
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK 0x0
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK 0x1
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_LSB 4
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_MSB 4
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_WIDTH 1
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET_MSK 0x00000010
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_RESET 0x0
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK 0x0
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK 0x1
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_LSB 5
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_MSB 5
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_WIDTH 1
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET_MSK 0x00000020
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_CLR_MSK 0xffffffdf
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_RESET 0x0
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_SYSMGR_EMAC_CTL_OFST 0x0
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF 0x1
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1 0x4
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2 0x5
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3 0x8
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4 0x9
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5 0xc
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6 0xd
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_LSB 0
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_MSB 3
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_WIDTH 4
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET_MSK 0x0000000f
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_RESET 0x0
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0)
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f)
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF 0x0
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF 0x1
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC 0x2
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC 0x3
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1 0x4
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2 0x5
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3 0x8
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4 0x9
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5 0xc
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6 0xd
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC 0xf
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_LSB 4
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_MSB 7
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_WIDTH 4
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET_MSK 0x000000f0
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_CLR_MSK 0xffffff0f
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_RESET 0x0
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_GET(value) (((value) & 0x000000f0) >> 4)
#define | ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET(value) (((value) << 4) & 0x000000f0)
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF 0x1
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1 0x4
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2 0x5
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3 0x8
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4 0x9
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5 0xc
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6 0xd
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_LSB 8
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_MSB 11
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_WIDTH 4
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET_MSK 0x00000f00
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_CLR_MSK 0xfffff0ff
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_RESET 0x0
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_GET(value) (((value) & 0x00000f00) >> 8)
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET(value) (((value) << 8) & 0x00000f00)
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF 0x0
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF 0x1
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC 0x2
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC 0x3
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1 0x4
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2 0x5
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3 0x8
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4 0x9
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5 0xc
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6 0xd
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC 0xf
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_LSB 12
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_MSB 15
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_WIDTH 4
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET_MSK 0x0000f000
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_CLR_MSK 0xffff0fff
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_RESET 0x0
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_GET(value) (((value) & 0x0000f000) >> 12)
#define | ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET(value) (((value) << 12) & 0x0000f000)
#define | ALT_SYSMGR_EMAC_L3MST_OFST 0x4
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA 0x0
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN 0x1
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_LSB 0
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_MSB 0
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_WIDTH 1
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET_MSK 0x00000001
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_RESET 0x0
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA 0x0
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN 0x1
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_LSB 1
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_MSB 1
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_WIDTH 1
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET_MSK 0x00000002
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_RESET 0x0
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA 0x0
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN 0x1
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_LSB 2
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_MSB 2
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_WIDTH 1
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET_MSK 0x00000004
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_RESET 0x0
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA 0x0
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN 0x1
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_LSB 3
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_MSB 3
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_WIDTH 1
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET_MSK 0x00000008
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_RESET 0x0
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_LSB 4
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_MSB 4
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_WIDTH 1
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET_MSK 0x00000010
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_RESET 0x0
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_LSB 5
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_MSB 12
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_WIDTH 8
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET_MSK 0x00001fe0
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_CLR_MSK 0xffffe01f
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_RESET 0x0
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_GET(value) (((value) & 0x00001fe0) >> 5)
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET(value) (((value) << 5) & 0x00001fe0)
#define | ALT_SYSMGR_DMA_CTL_OFST 0x0
#define | ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_LSB 0
#define | ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_MSB 31
#define | ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_WIDTH 32
#define | ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET_MSK 0xffffffff
#define | ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_CLR_MSK 0x00000000
#define | ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_RESET 0x0
#define | ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_SYSMGR_DMA_PERSECURITY_OFST 0x4
#define | ALT_SYSMGR_ISW_HANDOFF_VALUE_LSB 0
#define | ALT_SYSMGR_ISW_HANDOFF_VALUE_MSB 31
#define | ALT_SYSMGR_ISW_HANDOFF_VALUE_WIDTH 32
#define | ALT_SYSMGR_ISW_HANDOFF_VALUE_SET_MSK 0xffffffff
#define | ALT_SYSMGR_ISW_HANDOFF_VALUE_CLR_MSK 0x00000000
#define | ALT_SYSMGR_ISW_HANDOFF_VALUE_RESET 0x0
#define | ALT_SYSMGR_ISW_HANDOFF_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_SYSMGR_ISW_HANDOFF_VALUE_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_SYSMGR_ISW_HANDOFF_OFST 0x0
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD 0x0
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END 0x1
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_LSB 0
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_MSB 0
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_WIDTH 1
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET_MSK 0x00000001
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_RESET 0x0
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_DISD 0x0
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_END 0x1
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_LSB 1
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_MSB 1
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_WIDTH 1
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET_MSK 0x00000002
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_RESET 0x0
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_ROMCODE_CTL_OFST 0x0
#define | ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_LSB 0
#define | ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_MSB 31
#define | ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_WIDTH 32
#define | ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET_MSK 0xffffffff
#define | ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_CLR_MSK 0x00000000
#define | ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_RESET 0x0
#define | ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST 0x4
#define | ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_INVALID 0x0
#define | ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_VALID 0x49535756
#define | ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_LSB 0
#define | ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_MSB 31
#define | ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_WIDTH 32
#define | ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET_MSK 0xffffffff
#define | ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_CLR_MSK 0x00000000
#define | ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_RESET 0x0
#define | ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_SYSMGR_ROMCODE_INITSWSTATE_OFST 0x8
#define | ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_LSB 0
#define | ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_MSB 1
#define | ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_WIDTH 2
#define | ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET_MSK 0x00000003
#define | ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_RESET 0x0
#define | ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_ROMCODE_INITSWLASTLD_OFST 0xc
#define | ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_LSB 0
#define | ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_MSB 31
#define | ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_WIDTH 32
#define | ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET_MSK 0xffffffff
#define | ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_CLR_MSK 0x00000000
#define | ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_RESET 0x0
#define | ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_OFST 0x10
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_DISD 0x0
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_END 0xae9efebc
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_LSB 0
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_MSB 31
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_WIDTH 32
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET_MSK 0xffffffff
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_CLR_MSK 0x00000000
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_RESET 0x0
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST 0x0
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST))
#define | ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_LSB 0
#define | ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_MSB 15
#define | ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_WIDTH 16
#define | ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET_MSK 0x0000ffff
#define | ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_CLR_MSK 0xffff0000
#define | ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_RESET 0x0
#define | ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0)
#define | ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET(value) (((value) << 0) & 0x0000ffff)
#define | ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST 0x4
#define | ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST))
#define | ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_LSB 0
#define | ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_MSB 15
#define | ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_WIDTH 16
#define | ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET_MSK 0x0000ffff
#define | ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_CLR_MSK 0xffff0000
#define | ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_RESET 0x0
#define | ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_GET(value) (((value) & 0x0000ffff) >> 0)
#define | ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET(value) (((value) << 0) & 0x0000ffff)
#define | ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST 0x8
#define | ALT_SYSMGR_ROMCODE_WARMRAM_LEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST))
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_LSB 0
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_MSB 15
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_WIDTH 16
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET_MSK 0x0000ffff
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_CLR_MSK 0xffff0000
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_RESET 0x0
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0)
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET(value) (((value) << 0) & 0x0000ffff)
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST 0xc
#define | ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST))
#define | ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_LSB 0
#define | ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_MSB 31
#define | ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_WIDTH 32
#define | ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET_MSK 0xffffffff
#define | ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_CLR_MSK 0x00000000
#define | ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_RESET 0xe763552a
#define | ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_GET(value) (((value) & 0xffffffff) >> 0)
#define | ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET(value) (((value) << 0) & 0xffffffff)
#define | ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST 0x10
#define | ALT_SYSMGR_ROMCODE_WARMRAM_CRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST))
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS 0x0
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN 0x1
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_LSB 0
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_MSB 0
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_WIDTH 1
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET_MSK 0x00000001
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_RESET 0x0
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS 0x0
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN 0x1
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_LSB 1
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_MSB 1
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_WIDTH 1
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET_MSK 0x00000002
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_RESET 0x1
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_ROMHW_CTL_OFST 0x0
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0 0x0
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45 0x1
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90 0x2
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135 0x3
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180 0x4
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225 0x5
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270 0x6
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315 0x7
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_LSB 0
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_MSB 2
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_WIDTH 3
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET_MSK 0x00000007
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_CLR_MSK 0xfffffff8
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_RESET 0x0
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_GET(value) (((value) & 0x00000007) >> 0)
#define | ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET(value) (((value) << 0) & 0x00000007)
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0 0x0
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45 0x1
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90 0x2
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135 0x3
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180 0x4
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225 0x5
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270 0x6
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315 0x7
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_LSB 3
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_MSB 5
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_WIDTH 3
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET_MSK 0x00000038
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_CLR_MSK 0xffffffc7
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_RESET 0x0
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_GET(value) (((value) & 0x00000038) >> 3)
#define | ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET(value) (((value) << 3) & 0x00000038)
#define | ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_LSB 6
#define | ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_MSB 6
#define | ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_WIDTH 1
#define | ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET_MSK 0x00000040
#define | ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_CLR_MSK 0xffffffbf
#define | ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_RESET 0x0
#define | ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_GET(value) (((value) & 0x00000040) >> 6)
#define | ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET(value) (((value) << 6) & 0x00000040)
#define | ALT_SYSMGR_SDMMC_CTL_OFST 0x0
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_OPCODE 0x0
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_DATA 0x1
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_LSB 0
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_MSB 0
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_WIDTH 1
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET_MSK 0x00000001
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_RESET 0x1
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_LSB 1
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_MSB 1
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_WIDTH 1
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET_MSK 0x00000002
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_RESET 0x1
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_LSB 2
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_MSB 2
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_WIDTH 1
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET_MSK 0x00000004
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_RESET 0x0
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_LSB 3
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_MSB 3
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_WIDTH 1
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET_MSK 0x00000008
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_RESET 0x0
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_SDMMC_L3MST_OFST 0x4
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_LSB 0
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_MSB 0
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_WIDTH 1
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET_MSK 0x00000001
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_RESET 0x0
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_LSB 1
#define | ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_MSB 1
#define | ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_WIDTH 1
#define | ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET_MSK 0x00000002
#define | ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_RESET 0x0
#define | ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_LSB 2
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_MSB 2
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_WIDTH 1
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET_MSK 0x00000004
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_RESET 0x0
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_LSB 3
#define | ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_MSB 3
#define | ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_WIDTH 1
#define | ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET_MSK 0x00000008
#define | ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_RESET 0x0
#define | ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_NAND_BOOTSTRAP_OFST 0x0
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF 0x1
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 0x4
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 0x5
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 0x8
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 0x9
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 0xc
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 0xd
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_LSB 0
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_MSB 3
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_WIDTH 4
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET_MSK 0x0000000f
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_RESET 0x0
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0)
#define | ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f)
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF 0x1
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 0x4
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 0x5
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 0x8
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 0x9
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 0xc
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 0xd
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_LSB 4
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_MSB 7
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_WIDTH 4
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET_MSK 0x000000f0
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_CLR_MSK 0xffffff0f
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_RESET 0x0
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_GET(value) (((value) & 0x000000f0) >> 4)
#define | ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET(value) (((value) << 4) & 0x000000f0)
#define | ALT_SYSMGR_NAND_L3MST_OFST 0x4
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_OPCODE 0x0
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_DATA 0x1
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_0_LSB 0
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_0_MSB 0
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_0_WIDTH 1
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET_MSK 0x00000001
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_0_RESET 0x1
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_OPCODE 0x0
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_DATA 0x1
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_1_LSB 1
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_1_MSB 1
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_1_WIDTH 1
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET_MSK 0x00000002
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_1_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_1_RESET 0x1
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_1_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_LSB 2
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_MSB 2
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_WIDTH 1
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET_MSK 0x00000004
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_RESET 0x1
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_LSB 3
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_MSB 3
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_WIDTH 1
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET_MSK 0x00000008
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_RESET 0x1
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_LSB 4
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_MSB 4
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_WIDTH 1
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET_MSK 0x00000010
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_RESET 0x0
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_LSB 5
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_MSB 5
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_WIDTH 1
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET_MSK 0x00000020
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_CLR_MSK 0xffffffdf
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_RESET 0x0
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_LSB 6
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_MSB 6
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_WIDTH 1
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET_MSK 0x00000040
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_CLR_MSK 0xffffffbf
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_RESET 0x0
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000040) >> 6)
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET(value) (((value) << 6) & 0x00000040)
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_LSB 7
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_MSB 7
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_WIDTH 1
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET_MSK 0x00000080
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_CLR_MSK 0xffffff7f
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_RESET 0x0
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_GET(value) (((value) & 0x00000080) >> 7)
#define | ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET(value) (((value) << 7) & 0x00000080)
#define | ALT_SYSMGR_USB_L3MST_OFST 0x0
#define | ALT_SYSMGR_ECC_L2_EN_LSB 0
#define | ALT_SYSMGR_ECC_L2_EN_MSB 0
#define | ALT_SYSMGR_ECC_L2_EN_WIDTH 1
#define | ALT_SYSMGR_ECC_L2_EN_SET_MSK 0x00000001
#define | ALT_SYSMGR_ECC_L2_EN_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_ECC_L2_EN_RESET 0x0
#define | ALT_SYSMGR_ECC_L2_EN_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_ECC_L2_EN_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_ECC_L2_INJS_LSB 1
#define | ALT_SYSMGR_ECC_L2_INJS_MSB 1
#define | ALT_SYSMGR_ECC_L2_INJS_WIDTH 1
#define | ALT_SYSMGR_ECC_L2_INJS_SET_MSK 0x00000002
#define | ALT_SYSMGR_ECC_L2_INJS_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_ECC_L2_INJS_RESET 0x0
#define | ALT_SYSMGR_ECC_L2_INJS_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_ECC_L2_INJS_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_ECC_L2_INJD_LSB 2
#define | ALT_SYSMGR_ECC_L2_INJD_MSB 2
#define | ALT_SYSMGR_ECC_L2_INJD_WIDTH 1
#define | ALT_SYSMGR_ECC_L2_INJD_SET_MSK 0x00000004
#define | ALT_SYSMGR_ECC_L2_INJD_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_ECC_L2_INJD_RESET 0x0
#define | ALT_SYSMGR_ECC_L2_INJD_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_ECC_L2_INJD_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_ECC_L2_OFST 0x0
#define | ALT_SYSMGR_ECC_OCRAM_EN_LSB 0
#define | ALT_SYSMGR_ECC_OCRAM_EN_MSB 0
#define | ALT_SYSMGR_ECC_OCRAM_EN_WIDTH 1
#define | ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK 0x00000001
#define | ALT_SYSMGR_ECC_OCRAM_EN_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_ECC_OCRAM_EN_RESET 0x0
#define | ALT_SYSMGR_ECC_OCRAM_EN_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_ECC_OCRAM_EN_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_ECC_OCRAM_INJS_LSB 1
#define | ALT_SYSMGR_ECC_OCRAM_INJS_MSB 1
#define | ALT_SYSMGR_ECC_OCRAM_INJS_WIDTH 1
#define | ALT_SYSMGR_ECC_OCRAM_INJS_SET_MSK 0x00000002
#define | ALT_SYSMGR_ECC_OCRAM_INJS_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_ECC_OCRAM_INJS_RESET 0x0
#define | ALT_SYSMGR_ECC_OCRAM_INJS_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_ECC_OCRAM_INJS_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_ECC_OCRAM_INJD_LSB 2
#define | ALT_SYSMGR_ECC_OCRAM_INJD_MSB 2
#define | ALT_SYSMGR_ECC_OCRAM_INJD_WIDTH 1
#define | ALT_SYSMGR_ECC_OCRAM_INJD_SET_MSK 0x00000004
#define | ALT_SYSMGR_ECC_OCRAM_INJD_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_ECC_OCRAM_INJD_RESET 0x0
#define | ALT_SYSMGR_ECC_OCRAM_INJD_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_ECC_OCRAM_INJD_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_ECC_OCRAM_SERR_LSB 3
#define | ALT_SYSMGR_ECC_OCRAM_SERR_MSB 3
#define | ALT_SYSMGR_ECC_OCRAM_SERR_WIDTH 1
#define | ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK 0x00000008
#define | ALT_SYSMGR_ECC_OCRAM_SERR_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_ECC_OCRAM_SERR_RESET 0x0
#define | ALT_SYSMGR_ECC_OCRAM_SERR_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_ECC_OCRAM_SERR_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_ECC_OCRAM_DERR_LSB 4
#define | ALT_SYSMGR_ECC_OCRAM_DERR_MSB 4
#define | ALT_SYSMGR_ECC_OCRAM_DERR_WIDTH 1
#define | ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK 0x00000010
#define | ALT_SYSMGR_ECC_OCRAM_DERR_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_ECC_OCRAM_DERR_RESET 0x0
#define | ALT_SYSMGR_ECC_OCRAM_DERR_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_ECC_OCRAM_DERR_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_ECC_OCRAM_OFST 0x4
#define | ALT_SYSMGR_ECC_USB0_EN_LSB 0
#define | ALT_SYSMGR_ECC_USB0_EN_MSB 0
#define | ALT_SYSMGR_ECC_USB0_EN_WIDTH 1
#define | ALT_SYSMGR_ECC_USB0_EN_SET_MSK 0x00000001
#define | ALT_SYSMGR_ECC_USB0_EN_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_ECC_USB0_EN_RESET 0x0
#define | ALT_SYSMGR_ECC_USB0_EN_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_ECC_USB0_EN_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_ECC_USB0_INJS_LSB 1
#define | ALT_SYSMGR_ECC_USB0_INJS_MSB 1
#define | ALT_SYSMGR_ECC_USB0_INJS_WIDTH 1
#define | ALT_SYSMGR_ECC_USB0_INJS_SET_MSK 0x00000002
#define | ALT_SYSMGR_ECC_USB0_INJS_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_ECC_USB0_INJS_RESET 0x0
#define | ALT_SYSMGR_ECC_USB0_INJS_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_ECC_USB0_INJS_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_ECC_USB0_INJD_LSB 2
#define | ALT_SYSMGR_ECC_USB0_INJD_MSB 2
#define | ALT_SYSMGR_ECC_USB0_INJD_WIDTH 1
#define | ALT_SYSMGR_ECC_USB0_INJD_SET_MSK 0x00000004
#define | ALT_SYSMGR_ECC_USB0_INJD_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_ECC_USB0_INJD_RESET 0x0
#define | ALT_SYSMGR_ECC_USB0_INJD_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_ECC_USB0_INJD_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_ECC_USB0_SERR_LSB 3
#define | ALT_SYSMGR_ECC_USB0_SERR_MSB 3
#define | ALT_SYSMGR_ECC_USB0_SERR_WIDTH 1
#define | ALT_SYSMGR_ECC_USB0_SERR_SET_MSK 0x00000008
#define | ALT_SYSMGR_ECC_USB0_SERR_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_ECC_USB0_SERR_RESET 0x0
#define | ALT_SYSMGR_ECC_USB0_SERR_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_ECC_USB0_SERR_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_ECC_USB0_DERR_LSB 4
#define | ALT_SYSMGR_ECC_USB0_DERR_MSB 4
#define | ALT_SYSMGR_ECC_USB0_DERR_WIDTH 1
#define | ALT_SYSMGR_ECC_USB0_DERR_SET_MSK 0x00000010
#define | ALT_SYSMGR_ECC_USB0_DERR_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_ECC_USB0_DERR_RESET 0x0
#define | ALT_SYSMGR_ECC_USB0_DERR_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_ECC_USB0_DERR_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_ECC_USB0_OFST 0x8
#define | ALT_SYSMGR_ECC_USB1_EN_LSB 0
#define | ALT_SYSMGR_ECC_USB1_EN_MSB 0
#define | ALT_SYSMGR_ECC_USB1_EN_WIDTH 1
#define | ALT_SYSMGR_ECC_USB1_EN_SET_MSK 0x00000001
#define | ALT_SYSMGR_ECC_USB1_EN_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_ECC_USB1_EN_RESET 0x0
#define | ALT_SYSMGR_ECC_USB1_EN_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_ECC_USB1_EN_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_ECC_USB1_INJS_LSB 1
#define | ALT_SYSMGR_ECC_USB1_INJS_MSB 1
#define | ALT_SYSMGR_ECC_USB1_INJS_WIDTH 1
#define | ALT_SYSMGR_ECC_USB1_INJS_SET_MSK 0x00000002
#define | ALT_SYSMGR_ECC_USB1_INJS_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_ECC_USB1_INJS_RESET 0x0
#define | ALT_SYSMGR_ECC_USB1_INJS_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_ECC_USB1_INJS_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_ECC_USB1_INJD_LSB 2
#define | ALT_SYSMGR_ECC_USB1_INJD_MSB 2
#define | ALT_SYSMGR_ECC_USB1_INJD_WIDTH 1
#define | ALT_SYSMGR_ECC_USB1_INJD_SET_MSK 0x00000004
#define | ALT_SYSMGR_ECC_USB1_INJD_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_ECC_USB1_INJD_RESET 0x0
#define | ALT_SYSMGR_ECC_USB1_INJD_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_ECC_USB1_INJD_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_ECC_USB1_SERR_LSB 3
#define | ALT_SYSMGR_ECC_USB1_SERR_MSB 3
#define | ALT_SYSMGR_ECC_USB1_SERR_WIDTH 1
#define | ALT_SYSMGR_ECC_USB1_SERR_SET_MSK 0x00000008
#define | ALT_SYSMGR_ECC_USB1_SERR_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_ECC_USB1_SERR_RESET 0x0
#define | ALT_SYSMGR_ECC_USB1_SERR_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_ECC_USB1_SERR_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_ECC_USB1_DERR_LSB 4
#define | ALT_SYSMGR_ECC_USB1_DERR_MSB 4
#define | ALT_SYSMGR_ECC_USB1_DERR_WIDTH 1
#define | ALT_SYSMGR_ECC_USB1_DERR_SET_MSK 0x00000010
#define | ALT_SYSMGR_ECC_USB1_DERR_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_ECC_USB1_DERR_RESET 0x0
#define | ALT_SYSMGR_ECC_USB1_DERR_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_ECC_USB1_DERR_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_ECC_USB1_OFST 0xc
#define | ALT_SYSMGR_ECC_EMAC0_EN_LSB 0
#define | ALT_SYSMGR_ECC_EMAC0_EN_MSB 0
#define | ALT_SYSMGR_ECC_EMAC0_EN_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK 0x00000001
#define | ALT_SYSMGR_ECC_EMAC0_EN_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_ECC_EMAC0_EN_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC0_EN_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_ECC_EMAC0_EN_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_LSB 1
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_MSB 1
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET_MSK 0x00000002
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_LSB 2
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_MSB 2
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET_MSK 0x00000004
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_LSB 3
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_MSB 3
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET_MSK 0x00000008
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_LSB 4
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_MSB 4
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET_MSK 0x00000010
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_LSB 5
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_MSB 5
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK 0x00000020
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_CLR_MSK 0xffffffdf
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_LSB 6
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_MSB 6
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK 0x00000040
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_CLR_MSK 0xffffffbf
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6)
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040)
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_LSB 7
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_MSB 7
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK 0x00000080
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_CLR_MSK 0xffffff7f
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7)
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080)
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_LSB 8
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_MSB 8
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK 0x00000100
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_CLR_MSK 0xfffffeff
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8)
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100)
#define | ALT_SYSMGR_ECC_EMAC0_OFST 0x10
#define | ALT_SYSMGR_ECC_EMAC1_EN_LSB 0
#define | ALT_SYSMGR_ECC_EMAC1_EN_MSB 0
#define | ALT_SYSMGR_ECC_EMAC1_EN_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC1_EN_SET_MSK 0x00000001
#define | ALT_SYSMGR_ECC_EMAC1_EN_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_ECC_EMAC1_EN_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC1_EN_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_ECC_EMAC1_EN_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_LSB 1
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_MSB 1
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET_MSK 0x00000002
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_LSB 2
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_MSB 2
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET_MSK 0x00000004
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_LSB 3
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_MSB 3
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET_MSK 0x00000008
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_LSB 4
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_MSB 4
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET_MSK 0x00000010
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_LSB 5
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_MSB 5
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET_MSK 0x00000020
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_CLR_MSK 0xffffffdf
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_LSB 6
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_MSB 6
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET_MSK 0x00000040
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_CLR_MSK 0xffffffbf
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6)
#define | ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040)
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_LSB 7
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_MSB 7
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET_MSK 0x00000080
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_CLR_MSK 0xffffff7f
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7)
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080)
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_LSB 8
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_MSB 8
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_WIDTH 1
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET_MSK 0x00000100
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_CLR_MSK 0xfffffeff
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_RESET 0x0
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8)
#define | ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100)
#define | ALT_SYSMGR_ECC_EMAC1_OFST 0x14
#define | ALT_SYSMGR_ECC_DMA_EN_LSB 0
#define | ALT_SYSMGR_ECC_DMA_EN_MSB 0
#define | ALT_SYSMGR_ECC_DMA_EN_WIDTH 1
#define | ALT_SYSMGR_ECC_DMA_EN_SET_MSK 0x00000001
#define | ALT_SYSMGR_ECC_DMA_EN_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_ECC_DMA_EN_RESET 0x0
#define | ALT_SYSMGR_ECC_DMA_EN_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_ECC_DMA_EN_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_ECC_DMA_INJS_LSB 1
#define | ALT_SYSMGR_ECC_DMA_INJS_MSB 1
#define | ALT_SYSMGR_ECC_DMA_INJS_WIDTH 1
#define | ALT_SYSMGR_ECC_DMA_INJS_SET_MSK 0x00000002
#define | ALT_SYSMGR_ECC_DMA_INJS_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_ECC_DMA_INJS_RESET 0x0
#define | ALT_SYSMGR_ECC_DMA_INJS_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_ECC_DMA_INJS_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_ECC_DMA_INJD_LSB 2
#define | ALT_SYSMGR_ECC_DMA_INJD_MSB 2
#define | ALT_SYSMGR_ECC_DMA_INJD_WIDTH 1
#define | ALT_SYSMGR_ECC_DMA_INJD_SET_MSK 0x00000004
#define | ALT_SYSMGR_ECC_DMA_INJD_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_ECC_DMA_INJD_RESET 0x0
#define | ALT_SYSMGR_ECC_DMA_INJD_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_ECC_DMA_INJD_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_ECC_DMA_SERR_LSB 3
#define | ALT_SYSMGR_ECC_DMA_SERR_MSB 3
#define | ALT_SYSMGR_ECC_DMA_SERR_WIDTH 1
#define | ALT_SYSMGR_ECC_DMA_SERR_SET_MSK 0x00000008
#define | ALT_SYSMGR_ECC_DMA_SERR_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_ECC_DMA_SERR_RESET 0x0
#define | ALT_SYSMGR_ECC_DMA_SERR_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_ECC_DMA_SERR_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_ECC_DMA_DERR_LSB 4
#define | ALT_SYSMGR_ECC_DMA_DERR_MSB 4
#define | ALT_SYSMGR_ECC_DMA_DERR_WIDTH 1
#define | ALT_SYSMGR_ECC_DMA_DERR_SET_MSK 0x00000010
#define | ALT_SYSMGR_ECC_DMA_DERR_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_ECC_DMA_DERR_RESET 0x0
#define | ALT_SYSMGR_ECC_DMA_DERR_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_ECC_DMA_DERR_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_ECC_DMA_OFST 0x18
#define | ALT_SYSMGR_ECC_CAN0_EN_LSB 0
#define | ALT_SYSMGR_ECC_CAN0_EN_MSB 0
#define | ALT_SYSMGR_ECC_CAN0_EN_WIDTH 1
#define | ALT_SYSMGR_ECC_CAN0_EN_SET_MSK 0x00000001
#define | ALT_SYSMGR_ECC_CAN0_EN_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_ECC_CAN0_EN_RESET 0x0
#define | ALT_SYSMGR_ECC_CAN0_EN_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_ECC_CAN0_EN_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_ECC_CAN0_INJS_LSB 1
#define | ALT_SYSMGR_ECC_CAN0_INJS_MSB 1
#define | ALT_SYSMGR_ECC_CAN0_INJS_WIDTH 1
#define | ALT_SYSMGR_ECC_CAN0_INJS_SET_MSK 0x00000002
#define | ALT_SYSMGR_ECC_CAN0_INJS_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_ECC_CAN0_INJS_RESET 0x0
#define | ALT_SYSMGR_ECC_CAN0_INJS_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_ECC_CAN0_INJS_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_ECC_CAN0_INJD_LSB 2
#define | ALT_SYSMGR_ECC_CAN0_INJD_MSB 2
#define | ALT_SYSMGR_ECC_CAN0_INJD_WIDTH 1
#define | ALT_SYSMGR_ECC_CAN0_INJD_SET_MSK 0x00000004
#define | ALT_SYSMGR_ECC_CAN0_INJD_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_ECC_CAN0_INJD_RESET 0x0
#define | ALT_SYSMGR_ECC_CAN0_INJD_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_ECC_CAN0_INJD_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_ECC_CAN0_SERR_LSB 3
#define | ALT_SYSMGR_ECC_CAN0_SERR_MSB 3
#define | ALT_SYSMGR_ECC_CAN0_SERR_WIDTH 1
#define | ALT_SYSMGR_ECC_CAN0_SERR_SET_MSK 0x00000008
#define | ALT_SYSMGR_ECC_CAN0_SERR_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_ECC_CAN0_SERR_RESET 0x0
#define | ALT_SYSMGR_ECC_CAN0_SERR_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_ECC_CAN0_SERR_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_ECC_CAN0_DERR_LSB 4
#define | ALT_SYSMGR_ECC_CAN0_DERR_MSB 4
#define | ALT_SYSMGR_ECC_CAN0_DERR_WIDTH 1
#define | ALT_SYSMGR_ECC_CAN0_DERR_SET_MSK 0x00000010
#define | ALT_SYSMGR_ECC_CAN0_DERR_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_ECC_CAN0_DERR_RESET 0x0
#define | ALT_SYSMGR_ECC_CAN0_DERR_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_ECC_CAN0_DERR_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_ECC_CAN0_OFST 0x1c
#define | ALT_SYSMGR_ECC_CAN1_EN_LSB 0
#define | ALT_SYSMGR_ECC_CAN1_EN_MSB 0
#define | ALT_SYSMGR_ECC_CAN1_EN_WIDTH 1
#define | ALT_SYSMGR_ECC_CAN1_EN_SET_MSK 0x00000001
#define | ALT_SYSMGR_ECC_CAN1_EN_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_ECC_CAN1_EN_RESET 0x0
#define | ALT_SYSMGR_ECC_CAN1_EN_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_ECC_CAN1_EN_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_ECC_CAN1_INJS_LSB 1
#define | ALT_SYSMGR_ECC_CAN1_INJS_MSB 1
#define | ALT_SYSMGR_ECC_CAN1_INJS_WIDTH 1
#define | ALT_SYSMGR_ECC_CAN1_INJS_SET_MSK 0x00000002
#define | ALT_SYSMGR_ECC_CAN1_INJS_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_ECC_CAN1_INJS_RESET 0x0
#define | ALT_SYSMGR_ECC_CAN1_INJS_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_ECC_CAN1_INJS_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_ECC_CAN1_INJD_LSB 2
#define | ALT_SYSMGR_ECC_CAN1_INJD_MSB 2
#define | ALT_SYSMGR_ECC_CAN1_INJD_WIDTH 1
#define | ALT_SYSMGR_ECC_CAN1_INJD_SET_MSK 0x00000004
#define | ALT_SYSMGR_ECC_CAN1_INJD_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_ECC_CAN1_INJD_RESET 0x0
#define | ALT_SYSMGR_ECC_CAN1_INJD_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_ECC_CAN1_INJD_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_ECC_CAN1_SERR_LSB 3
#define | ALT_SYSMGR_ECC_CAN1_SERR_MSB 3
#define | ALT_SYSMGR_ECC_CAN1_SERR_WIDTH 1
#define | ALT_SYSMGR_ECC_CAN1_SERR_SET_MSK 0x00000008
#define | ALT_SYSMGR_ECC_CAN1_SERR_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_ECC_CAN1_SERR_RESET 0x0
#define | ALT_SYSMGR_ECC_CAN1_SERR_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_ECC_CAN1_SERR_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_ECC_CAN1_DERR_LSB 4
#define | ALT_SYSMGR_ECC_CAN1_DERR_MSB 4
#define | ALT_SYSMGR_ECC_CAN1_DERR_WIDTH 1
#define | ALT_SYSMGR_ECC_CAN1_DERR_SET_MSK 0x00000010
#define | ALT_SYSMGR_ECC_CAN1_DERR_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_ECC_CAN1_DERR_RESET 0x0
#define | ALT_SYSMGR_ECC_CAN1_DERR_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_ECC_CAN1_DERR_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_ECC_CAN1_OFST 0x20
#define | ALT_SYSMGR_ECC_NAND_EN_LSB 0
#define | ALT_SYSMGR_ECC_NAND_EN_MSB 0
#define | ALT_SYSMGR_ECC_NAND_EN_WIDTH 1
#define | ALT_SYSMGR_ECC_NAND_EN_SET_MSK 0x00000001
#define | ALT_SYSMGR_ECC_NAND_EN_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_ECC_NAND_EN_RESET 0x0
#define | ALT_SYSMGR_ECC_NAND_EN_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_ECC_NAND_EN_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJS_LSB 1
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJS_MSB 1
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJS_WIDTH 1
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET_MSK 0x00000002
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJS_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJS_RESET 0x0
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJS_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJD_LSB 2
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJD_MSB 2
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJD_WIDTH 1
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET_MSK 0x00000004
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJD_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJD_RESET 0x0
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJD_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJS_LSB 3
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJS_MSB 3
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJS_WIDTH 1
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET_MSK 0x00000008
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJS_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJS_RESET 0x0
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJS_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJD_LSB 4
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJD_MSB 4
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJD_WIDTH 1
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET_MSK 0x00000010
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJD_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJD_RESET 0x0
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJD_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJS_LSB 5
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJS_MSB 5
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJS_WIDTH 1
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET_MSK 0x00000020
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJS_CLR_MSK 0xffffffdf
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJS_RESET 0x0
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJS_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJD_LSB 6
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJD_MSB 6
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJD_WIDTH 1
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET_MSK 0x00000040
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJD_CLR_MSK 0xffffffbf
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJD_RESET 0x0
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJD_GET(value) (((value) & 0x00000040) >> 6)
#define | ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET(value) (((value) << 6) & 0x00000040)
#define | ALT_SYSMGR_ECC_NAND_ECCBUFSERR_LSB 7
#define | ALT_SYSMGR_ECC_NAND_ECCBUFSERR_MSB 7
#define | ALT_SYSMGR_ECC_NAND_ECCBUFSERR_WIDTH 1
#define | ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK 0x00000080
#define | ALT_SYSMGR_ECC_NAND_ECCBUFSERR_CLR_MSK 0xffffff7f
#define | ALT_SYSMGR_ECC_NAND_ECCBUFSERR_RESET 0x0
#define | ALT_SYSMGR_ECC_NAND_ECCBUFSERR_GET(value) (((value) & 0x00000080) >> 7)
#define | ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET(value) (((value) << 7) & 0x00000080)
#define | ALT_SYSMGR_ECC_NAND_ECCBUFDERR_LSB 8
#define | ALT_SYSMGR_ECC_NAND_ECCBUFDERR_MSB 8
#define | ALT_SYSMGR_ECC_NAND_ECCBUFDERR_WIDTH 1
#define | ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK 0x00000100
#define | ALT_SYSMGR_ECC_NAND_ECCBUFDERR_CLR_MSK 0xfffffeff
#define | ALT_SYSMGR_ECC_NAND_ECCBUFDERR_RESET 0x0
#define | ALT_SYSMGR_ECC_NAND_ECCBUFDERR_GET(value) (((value) & 0x00000100) >> 8)
#define | ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET(value) (((value) << 8) & 0x00000100)
#define | ALT_SYSMGR_ECC_NAND_WRFIFOSERR_LSB 9
#define | ALT_SYSMGR_ECC_NAND_WRFIFOSERR_MSB 9
#define | ALT_SYSMGR_ECC_NAND_WRFIFOSERR_WIDTH 1
#define | ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK 0x00000200
#define | ALT_SYSMGR_ECC_NAND_WRFIFOSERR_CLR_MSK 0xfffffdff
#define | ALT_SYSMGR_ECC_NAND_WRFIFOSERR_RESET 0x0
#define | ALT_SYSMGR_ECC_NAND_WRFIFOSERR_GET(value) (((value) & 0x00000200) >> 9)
#define | ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET(value) (((value) << 9) & 0x00000200)
#define | ALT_SYSMGR_ECC_NAND_WRFIFODERR_LSB 10
#define | ALT_SYSMGR_ECC_NAND_WRFIFODERR_MSB 10
#define | ALT_SYSMGR_ECC_NAND_WRFIFODERR_WIDTH 1
#define | ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK 0x00000400
#define | ALT_SYSMGR_ECC_NAND_WRFIFODERR_CLR_MSK 0xfffffbff
#define | ALT_SYSMGR_ECC_NAND_WRFIFODERR_RESET 0x0
#define | ALT_SYSMGR_ECC_NAND_WRFIFODERR_GET(value) (((value) & 0x00000400) >> 10)
#define | ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET(value) (((value) << 10) & 0x00000400)
#define | ALT_SYSMGR_ECC_NAND_RDFIFOSERR_LSB 11
#define | ALT_SYSMGR_ECC_NAND_RDFIFOSERR_MSB 11
#define | ALT_SYSMGR_ECC_NAND_RDFIFOSERR_WIDTH 1
#define | ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK 0x00000800
#define | ALT_SYSMGR_ECC_NAND_RDFIFOSERR_CLR_MSK 0xfffff7ff
#define | ALT_SYSMGR_ECC_NAND_RDFIFOSERR_RESET 0x0
#define | ALT_SYSMGR_ECC_NAND_RDFIFOSERR_GET(value) (((value) & 0x00000800) >> 11)
#define | ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET(value) (((value) << 11) & 0x00000800)
#define | ALT_SYSMGR_ECC_NAND_RDFIFODERR_LSB 12
#define | ALT_SYSMGR_ECC_NAND_RDFIFODERR_MSB 12
#define | ALT_SYSMGR_ECC_NAND_RDFIFODERR_WIDTH 1
#define | ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK 0x00001000
#define | ALT_SYSMGR_ECC_NAND_RDFIFODERR_CLR_MSK 0xffffefff
#define | ALT_SYSMGR_ECC_NAND_RDFIFODERR_RESET 0x0
#define | ALT_SYSMGR_ECC_NAND_RDFIFODERR_GET(value) (((value) & 0x00001000) >> 12)
#define | ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET(value) (((value) << 12) & 0x00001000)
#define | ALT_SYSMGR_ECC_NAND_OFST 0x24
#define | ALT_SYSMGR_ECC_QSPI_EN_LSB 0
#define | ALT_SYSMGR_ECC_QSPI_EN_MSB 0
#define | ALT_SYSMGR_ECC_QSPI_EN_WIDTH 1
#define | ALT_SYSMGR_ECC_QSPI_EN_SET_MSK 0x00000001
#define | ALT_SYSMGR_ECC_QSPI_EN_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_ECC_QSPI_EN_RESET 0x0
#define | ALT_SYSMGR_ECC_QSPI_EN_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_ECC_QSPI_EN_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_ECC_QSPI_INJS_LSB 1
#define | ALT_SYSMGR_ECC_QSPI_INJS_MSB 1
#define | ALT_SYSMGR_ECC_QSPI_INJS_WIDTH 1
#define | ALT_SYSMGR_ECC_QSPI_INJS_SET_MSK 0x00000002
#define | ALT_SYSMGR_ECC_QSPI_INJS_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_ECC_QSPI_INJS_RESET 0x0
#define | ALT_SYSMGR_ECC_QSPI_INJS_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_ECC_QSPI_INJS_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_ECC_QSPI_INJD_LSB 2
#define | ALT_SYSMGR_ECC_QSPI_INJD_MSB 2
#define | ALT_SYSMGR_ECC_QSPI_INJD_WIDTH 1
#define | ALT_SYSMGR_ECC_QSPI_INJD_SET_MSK 0x00000004
#define | ALT_SYSMGR_ECC_QSPI_INJD_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_ECC_QSPI_INJD_RESET 0x0
#define | ALT_SYSMGR_ECC_QSPI_INJD_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_ECC_QSPI_INJD_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_ECC_QSPI_SERR_LSB 3
#define | ALT_SYSMGR_ECC_QSPI_SERR_MSB 3
#define | ALT_SYSMGR_ECC_QSPI_SERR_WIDTH 1
#define | ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK 0x00000008
#define | ALT_SYSMGR_ECC_QSPI_SERR_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_ECC_QSPI_SERR_RESET 0x0
#define | ALT_SYSMGR_ECC_QSPI_SERR_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_ECC_QSPI_SERR_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_ECC_QSPI_DERR_LSB 4
#define | ALT_SYSMGR_ECC_QSPI_DERR_MSB 4
#define | ALT_SYSMGR_ECC_QSPI_DERR_WIDTH 1
#define | ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK 0x00000010
#define | ALT_SYSMGR_ECC_QSPI_DERR_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_ECC_QSPI_DERR_RESET 0x0
#define | ALT_SYSMGR_ECC_QSPI_DERR_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_ECC_QSPI_DERR_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_ECC_QSPI_OFST 0x28
#define | ALT_SYSMGR_ECC_SDMMC_EN_LSB 0
#define | ALT_SYSMGR_ECC_SDMMC_EN_MSB 0
#define | ALT_SYSMGR_ECC_SDMMC_EN_WIDTH 1
#define | ALT_SYSMGR_ECC_SDMMC_EN_SET_MSK 0x00000001
#define | ALT_SYSMGR_ECC_SDMMC_EN_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_ECC_SDMMC_EN_RESET 0x0
#define | ALT_SYSMGR_ECC_SDMMC_EN_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_ECC_SDMMC_EN_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTA_LSB 1
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTA_MSB 1
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTA_WIDTH 1
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET_MSK 0x00000002
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTA_CLR_MSK 0xfffffffd
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTA_RESET 0x0
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTA_GET(value) (((value) & 0x00000002) >> 1)
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET(value) (((value) << 1) & 0x00000002)
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTA_LSB 2
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTA_MSB 2
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTA_WIDTH 1
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET_MSK 0x00000004
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTA_CLR_MSK 0xfffffffb
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTA_RESET 0x0
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTA_GET(value) (((value) & 0x00000004) >> 2)
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET(value) (((value) << 2) & 0x00000004)
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTB_LSB 3
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTB_MSB 3
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTB_WIDTH 1
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET_MSK 0x00000008
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTB_CLR_MSK 0xfffffff7
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTB_RESET 0x0
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTB_GET(value) (((value) & 0x00000008) >> 3)
#define | ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET(value) (((value) << 3) & 0x00000008)
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTB_LSB 4
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTB_MSB 4
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTB_WIDTH 1
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET_MSK 0x00000010
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTB_CLR_MSK 0xffffffef
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTB_RESET 0x0
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTB_GET(value) (((value) & 0x00000010) >> 4)
#define | ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET(value) (((value) << 4) & 0x00000010)
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTA_LSB 5
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTA_MSB 5
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTA_WIDTH 1
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET_MSK 0x00000020
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTA_CLR_MSK 0xffffffdf
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTA_RESET 0x0
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTA_GET(value) (((value) & 0x00000020) >> 5)
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET(value) (((value) << 5) & 0x00000020)
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTA_LSB 6
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTA_MSB 6
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTA_WIDTH 1
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET_MSK 0x00000040
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTA_CLR_MSK 0xffffffbf
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTA_RESET 0x0
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTA_GET(value) (((value) & 0x00000040) >> 6)
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET(value) (((value) << 6) & 0x00000040)
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTB_LSB 7
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTB_MSB 7
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTB_WIDTH 1
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET_MSK 0x00000080
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTB_CLR_MSK 0xffffff7f
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTB_RESET 0x0
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTB_GET(value) (((value) & 0x00000080) >> 7)
#define | ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET(value) (((value) << 7) & 0x00000080)
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTB_LSB 8
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTB_MSB 8
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTB_WIDTH 1
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET_MSK 0x00000100
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTB_CLR_MSK 0xfffffeff
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTB_RESET 0x0
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTB_GET(value) (((value) & 0x00000100) >> 8)
#define | ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET(value) (((value) << 8) & 0x00000100)
#define | ALT_SYSMGR_ECC_SDMMC_OFST 0x2c
#define | ALT_SYSMGR_PINMUX_EMACIO0_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO0_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO0_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO0_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO0_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO0_OFST 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO1_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO1_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO1_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO1_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO1_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO1_OFST 0x4
#define | ALT_SYSMGR_PINMUX_EMACIO2_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO2_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO2_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO2_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO2_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO2_OFST 0x8
#define | ALT_SYSMGR_PINMUX_EMACIO3_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO3_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO3_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO3_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO3_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO3_OFST 0xc
#define | ALT_SYSMGR_PINMUX_EMACIO4_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO4_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO4_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO4_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO4_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO4_OFST 0x10
#define | ALT_SYSMGR_PINMUX_EMACIO5_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO5_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO5_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO5_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO5_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO5_OFST 0x14
#define | ALT_SYSMGR_PINMUX_EMACIO6_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO6_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO6_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO6_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO6_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO6_OFST 0x18
#define | ALT_SYSMGR_PINMUX_EMACIO7_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO7_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO7_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO7_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO7_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO7_OFST 0x1c
#define | ALT_SYSMGR_PINMUX_EMACIO8_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO8_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO8_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO8_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO8_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO8_OFST 0x20
#define | ALT_SYSMGR_PINMUX_EMACIO9_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO9_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO9_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO9_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO9_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO9_OFST 0x24
#define | ALT_SYSMGR_PINMUX_EMACIO10_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO10_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO10_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO10_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO10_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO10_OFST 0x28
#define | ALT_SYSMGR_PINMUX_EMACIO11_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO11_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO11_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO11_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO11_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO11_OFST 0x2c
#define | ALT_SYSMGR_PINMUX_EMACIO12_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO12_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO12_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO12_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO12_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO12_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO12_OFST 0x30
#define | ALT_SYSMGR_PINMUX_EMACIO13_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO13_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO13_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO13_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO13_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO13_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO13_OFST 0x34
#define | ALT_SYSMGR_PINMUX_EMACIO14_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO14_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO14_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO14_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO14_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO14_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO14_OFST 0x38
#define | ALT_SYSMGR_PINMUX_EMACIO15_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO15_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO15_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO15_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO15_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO15_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO15_OFST 0x3c
#define | ALT_SYSMGR_PINMUX_EMACIO16_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO16_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO16_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO16_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO16_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO16_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO16_OFST 0x40
#define | ALT_SYSMGR_PINMUX_EMACIO17_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO17_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO17_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO17_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO17_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO17_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO17_OFST 0x44
#define | ALT_SYSMGR_PINMUX_EMACIO18_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO18_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO18_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO18_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO18_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO18_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO18_OFST 0x48
#define | ALT_SYSMGR_PINMUX_EMACIO19_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_EMACIO19_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_EMACIO19_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_EMACIO19_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_EMACIO19_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_EMACIO19_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_EMACIO19_OFST 0x4c
#define | ALT_SYSMGR_PINMUX_FLSHIO0_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_FLSHIO0_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_FLSHIO0_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_FLSHIO0_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_FLSHIO0_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_FLSHIO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_FLSHIO0_OFST 0x50
#define | ALT_SYSMGR_PINMUX_FLSHIO1_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_FLSHIO1_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_FLSHIO1_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_FLSHIO1_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_FLSHIO1_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_FLSHIO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_FLSHIO1_OFST 0x54
#define | ALT_SYSMGR_PINMUX_FLSHIO2_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_FLSHIO2_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_FLSHIO2_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_FLSHIO2_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_FLSHIO2_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_FLSHIO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_FLSHIO2_OFST 0x58
#define | ALT_SYSMGR_PINMUX_FLSHIO3_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_FLSHIO3_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_FLSHIO3_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_FLSHIO3_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_FLSHIO3_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_FLSHIO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_FLSHIO3_OFST 0x5c
#define | ALT_SYSMGR_PINMUX_FLSHIO4_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_FLSHIO4_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_FLSHIO4_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_FLSHIO4_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_FLSHIO4_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_FLSHIO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_FLSHIO4_OFST 0x60
#define | ALT_SYSMGR_PINMUX_FLSHIO5_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_FLSHIO5_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_FLSHIO5_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_FLSHIO5_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_FLSHIO5_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_FLSHIO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_FLSHIO5_OFST 0x64
#define | ALT_SYSMGR_PINMUX_FLSHIO6_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_FLSHIO6_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_FLSHIO6_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_FLSHIO6_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_FLSHIO6_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_FLSHIO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_FLSHIO6_OFST 0x68
#define | ALT_SYSMGR_PINMUX_FLSHIO7_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_FLSHIO7_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_FLSHIO7_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_FLSHIO7_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_FLSHIO7_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_FLSHIO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_FLSHIO7_OFST 0x6c
#define | ALT_SYSMGR_PINMUX_FLSHIO8_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_FLSHIO8_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_FLSHIO8_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_FLSHIO8_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_FLSHIO8_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_FLSHIO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_FLSHIO8_OFST 0x70
#define | ALT_SYSMGR_PINMUX_FLSHIO9_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_FLSHIO9_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_FLSHIO9_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_FLSHIO9_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_FLSHIO9_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_FLSHIO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_FLSHIO9_OFST 0x74
#define | ALT_SYSMGR_PINMUX_FLSHIO10_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_FLSHIO10_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_FLSHIO10_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_FLSHIO10_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_FLSHIO10_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_FLSHIO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_FLSHIO10_OFST 0x78
#define | ALT_SYSMGR_PINMUX_FLSHIO11_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_FLSHIO11_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_FLSHIO11_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_FLSHIO11_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_FLSHIO11_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_FLSHIO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_FLSHIO11_OFST 0x7c
#define | ALT_SYSMGR_PINMUX_GENERALIO0_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO0_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO0_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO0_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO0_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO0_OFST 0x80
#define | ALT_SYSMGR_PINMUX_GENERALIO1_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO1_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO1_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO1_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO1_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO1_OFST 0x84
#define | ALT_SYSMGR_PINMUX_GENERALIO2_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO2_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO2_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO2_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO2_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO2_OFST 0x88
#define | ALT_SYSMGR_PINMUX_GENERALIO3_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO3_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO3_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO3_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO3_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO3_OFST 0x8c
#define | ALT_SYSMGR_PINMUX_GENERALIO4_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO4_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO4_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO4_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO4_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO4_OFST 0x90
#define | ALT_SYSMGR_PINMUX_GENERALIO5_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO5_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO5_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO5_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO5_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO5_OFST 0x94
#define | ALT_SYSMGR_PINMUX_GENERALIO6_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO6_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO6_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO6_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO6_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO6_OFST 0x98
#define | ALT_SYSMGR_PINMUX_GENERALIO7_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO7_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO7_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO7_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO7_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO7_OFST 0x9c
#define | ALT_SYSMGR_PINMUX_GENERALIO8_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO8_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO8_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO8_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO8_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO8_OFST 0xa0
#define | ALT_SYSMGR_PINMUX_GENERALIO9_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO9_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO9_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO9_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO9_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO9_OFST 0xa4
#define | ALT_SYSMGR_PINMUX_GENERALIO10_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO10_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO10_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO10_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO10_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO10_OFST 0xa8
#define | ALT_SYSMGR_PINMUX_GENERALIO11_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO11_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO11_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO11_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO11_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO11_OFST 0xac
#define | ALT_SYSMGR_PINMUX_GENERALIO12_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO12_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO12_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO12_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO12_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO12_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO12_OFST 0xb0
#define | ALT_SYSMGR_PINMUX_GENERALIO13_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO13_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO13_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO13_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO13_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO13_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO13_OFST 0xb4
#define | ALT_SYSMGR_PINMUX_GENERALIO14_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO14_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO14_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO14_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO14_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO14_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO14_OFST 0xb8
#define | ALT_SYSMGR_PINMUX_GENERALIO15_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO15_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO15_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO15_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO15_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO15_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO15_OFST 0xbc
#define | ALT_SYSMGR_PINMUX_GENERALIO16_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO16_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO16_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO16_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO16_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO16_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO16_OFST 0xc0
#define | ALT_SYSMGR_PINMUX_GENERALIO17_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO17_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO17_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO17_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO17_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO17_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO17_OFST 0xc4
#define | ALT_SYSMGR_PINMUX_GENERALIO18_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO18_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO18_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO18_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO18_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO18_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO18_OFST 0xc8
#define | ALT_SYSMGR_PINMUX_GENERALIO19_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO19_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO19_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO19_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO19_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO19_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO19_OFST 0xcc
#define | ALT_SYSMGR_PINMUX_GENERALIO20_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO20_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO20_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO20_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO20_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO20_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO20_OFST 0xd0
#define | ALT_SYSMGR_PINMUX_GENERALIO21_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO21_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO21_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO21_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO21_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO21_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO21_OFST 0xd4
#define | ALT_SYSMGR_PINMUX_GENERALIO22_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO22_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO22_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO22_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO22_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO22_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO22_OFST 0xd8
#define | ALT_SYSMGR_PINMUX_GENERALIO23_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO23_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO23_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO23_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO23_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO23_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO23_OFST 0xdc
#define | ALT_SYSMGR_PINMUX_GENERALIO24_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO24_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO24_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO24_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO24_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO24_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO24_OFST 0xe0
#define | ALT_SYSMGR_PINMUX_GENERALIO25_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO25_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO25_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO25_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO25_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO25_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO25_OFST 0xe4
#define | ALT_SYSMGR_PINMUX_GENERALIO26_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO26_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO26_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO26_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO26_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO26_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO26_OFST 0xe8
#define | ALT_SYSMGR_PINMUX_GENERALIO27_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO27_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO27_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO27_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO27_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO27_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO27_OFST 0xec
#define | ALT_SYSMGR_PINMUX_GENERALIO28_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO28_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO28_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO28_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO28_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO28_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO28_OFST 0xf0
#define | ALT_SYSMGR_PINMUX_GENERALIO29_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO29_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO29_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO29_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO29_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO29_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO29_OFST 0xf4
#define | ALT_SYSMGR_PINMUX_GENERALIO30_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO30_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO30_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO30_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO30_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO30_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO30_OFST 0xf8
#define | ALT_SYSMGR_PINMUX_GENERALIO31_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GENERALIO31_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_GENERALIO31_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_GENERALIO31_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_GENERALIO31_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GENERALIO31_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_GENERALIO31_OFST 0xfc
#define | ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO0_OFST 0x100
#define | ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO1_OFST 0x104
#define | ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO2_OFST 0x108
#define | ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO3_OFST 0x10c
#define | ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO4_OFST 0x110
#define | ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO5_OFST 0x114
#define | ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO6_OFST 0x118
#define | ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO7_OFST 0x11c
#define | ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO8_OFST 0x120
#define | ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO9_OFST 0x124
#define | ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO10_OFST 0x128
#define | ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO11_OFST 0x12c
#define | ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO12_OFST 0x130
#define | ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO13_OFST 0x134
#define | ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO14_OFST 0x138
#define | ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO15_OFST 0x13c
#define | ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO16_OFST 0x140
#define | ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO17_OFST 0x144
#define | ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO18_OFST 0x148
#define | ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO19_OFST 0x14c
#define | ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO20_OFST 0x150
#define | ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED1IO21_OFST 0x154
#define | ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED2IO0_OFST 0x158
#define | ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED2IO1_OFST 0x15c
#define | ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED2IO2_OFST 0x160
#define | ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED2IO3_OFST 0x164
#define | ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED2IO4_OFST 0x168
#define | ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED2IO5_OFST 0x16c
#define | ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED2IO6_OFST 0x170
#define | ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_MSB 1
#define | ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_WIDTH 2
#define | ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET_MSK 0x00000003
#define | ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_CLR_MSK 0xfffffffc
#define | ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
#define | ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET(value) (((value) << 0) & 0x00000003)
#define | ALT_SYSMGR_PINMUX_MIXED2IO7_OFST 0x174
#define | ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX48_OFST 0x178
#define | ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX49_OFST 0x17c
#define | ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX50_OFST 0x180
#define | ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX51_OFST 0x184
#define | ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX52_OFST 0x188
#define | ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX53_OFST 0x18c
#define | ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX54_OFST 0x190
#define | ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX55_OFST 0x194
#define | ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX56_OFST 0x198
#define | ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX57_OFST 0x19c
#define | ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX58_OFST 0x1a0
#define | ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX59_OFST 0x1a4
#define | ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX60_OFST 0x1a8
#define | ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX61_OFST 0x1ac
#define | ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX62_OFST 0x1b0
#define | ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX63_OFST 0x1b4
#define | ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX64_OFST 0x1b8
#define | ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX65_OFST 0x1bc
#define | ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX66_OFST 0x1c0
#define | ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX67_OFST 0x1c4
#define | ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX68_OFST 0x1c8
#define | ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX69_OFST 0x1cc
#define | ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLINMUX70_OFST 0x1d0
#define | ALT_SYSMGR_PINMUX_GPLMUX0_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX0_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX0_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX0_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX0_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX0_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX0_OFST 0x1d4
#define | ALT_SYSMGR_PINMUX_GPLMUX1_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX1_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX1_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX1_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX1_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX1_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX1_OFST 0x1d8
#define | ALT_SYSMGR_PINMUX_GPLMUX2_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX2_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX2_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX2_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX2_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX2_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX2_OFST 0x1dc
#define | ALT_SYSMGR_PINMUX_GPLMUX3_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX3_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX3_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX3_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX3_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX3_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX3_OFST 0x1e0
#define | ALT_SYSMGR_PINMUX_GPLMUX4_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX4_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX4_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX4_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX4_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX4_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX4_OFST 0x1e4
#define | ALT_SYSMGR_PINMUX_GPLMUX5_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX5_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX5_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX5_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX5_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX5_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX5_OFST 0x1e8
#define | ALT_SYSMGR_PINMUX_GPLMUX6_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX6_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX6_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX6_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX6_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX6_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX6_OFST 0x1ec
#define | ALT_SYSMGR_PINMUX_GPLMUX7_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX7_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX7_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX7_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX7_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX7_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX7_OFST 0x1f0
#define | ALT_SYSMGR_PINMUX_GPLMUX8_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX8_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX8_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX8_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX8_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX8_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX8_OFST 0x1f4
#define | ALT_SYSMGR_PINMUX_GPLMUX9_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX9_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX9_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX9_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX9_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX9_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX9_OFST 0x1f8
#define | ALT_SYSMGR_PINMUX_GPLMUX10_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX10_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX10_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX10_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX10_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX10_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX10_OFST 0x1fc
#define | ALT_SYSMGR_PINMUX_GPLMUX11_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX11_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX11_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX11_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX11_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX11_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX11_OFST 0x200
#define | ALT_SYSMGR_PINMUX_GPLMUX12_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX12_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX12_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX12_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX12_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX12_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX12_OFST 0x204
#define | ALT_SYSMGR_PINMUX_GPLMUX13_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX13_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX13_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX13_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX13_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX13_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX13_OFST 0x208
#define | ALT_SYSMGR_PINMUX_GPLMUX14_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX14_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX14_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX14_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX14_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX14_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX14_OFST 0x20c
#define | ALT_SYSMGR_PINMUX_GPLMUX15_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX15_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX15_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX15_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX15_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX15_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX15_OFST 0x210
#define | ALT_SYSMGR_PINMUX_GPLMUX16_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX16_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX16_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX16_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX16_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX16_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX16_OFST 0x214
#define | ALT_SYSMGR_PINMUX_GPLMUX17_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX17_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX17_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX17_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX17_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX17_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX17_OFST 0x218
#define | ALT_SYSMGR_PINMUX_GPLMUX18_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX18_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX18_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX18_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX18_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX18_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX18_OFST 0x21c
#define | ALT_SYSMGR_PINMUX_GPLMUX19_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX19_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX19_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX19_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX19_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX19_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX19_OFST 0x220
#define | ALT_SYSMGR_PINMUX_GPLMUX20_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX20_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX20_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX20_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX20_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX20_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX20_OFST 0x224
#define | ALT_SYSMGR_PINMUX_GPLMUX21_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX21_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX21_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX21_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX21_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX21_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX21_OFST 0x228
#define | ALT_SYSMGR_PINMUX_GPLMUX22_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX22_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX22_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX22_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX22_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX22_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX22_OFST 0x22c
#define | ALT_SYSMGR_PINMUX_GPLMUX23_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX23_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX23_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX23_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX23_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX23_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX23_OFST 0x230
#define | ALT_SYSMGR_PINMUX_GPLMUX24_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX24_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX24_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX24_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX24_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX24_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX24_OFST 0x234
#define | ALT_SYSMGR_PINMUX_GPLMUX25_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX25_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX25_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX25_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX25_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX25_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX25_OFST 0x238
#define | ALT_SYSMGR_PINMUX_GPLMUX26_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX26_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX26_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX26_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX26_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX26_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX26_OFST 0x23c
#define | ALT_SYSMGR_PINMUX_GPLMUX27_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX27_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX27_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX27_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX27_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX27_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX27_OFST 0x240
#define | ALT_SYSMGR_PINMUX_GPLMUX28_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX28_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX28_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX28_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX28_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX28_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX28_OFST 0x244
#define | ALT_SYSMGR_PINMUX_GPLMUX29_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX29_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX29_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX29_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX29_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX29_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX29_OFST 0x248
#define | ALT_SYSMGR_PINMUX_GPLMUX30_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX30_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX30_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX30_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX30_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX30_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX30_OFST 0x24c
#define | ALT_SYSMGR_PINMUX_GPLMUX31_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX31_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX31_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX31_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX31_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX31_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX31_OFST 0x250
#define | ALT_SYSMGR_PINMUX_GPLMUX32_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX32_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX32_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX32_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX32_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX32_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX32_OFST 0x254
#define | ALT_SYSMGR_PINMUX_GPLMUX33_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX33_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX33_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX33_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX33_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX33_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX33_OFST 0x258
#define | ALT_SYSMGR_PINMUX_GPLMUX34_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX34_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX34_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX34_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX34_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX34_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX34_OFST 0x25c
#define | ALT_SYSMGR_PINMUX_GPLMUX35_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX35_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX35_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX35_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX35_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX35_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX35_OFST 0x260
#define | ALT_SYSMGR_PINMUX_GPLMUX36_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX36_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX36_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX36_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX36_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX36_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX36_OFST 0x264
#define | ALT_SYSMGR_PINMUX_GPLMUX37_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX37_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX37_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX37_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX37_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX37_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX37_OFST 0x268
#define | ALT_SYSMGR_PINMUX_GPLMUX38_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX38_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX38_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX38_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX38_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX38_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX38_OFST 0x26c
#define | ALT_SYSMGR_PINMUX_GPLMUX39_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX39_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX39_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX39_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX39_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX39_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX39_OFST 0x270
#define | ALT_SYSMGR_PINMUX_GPLMUX40_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX40_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX40_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX40_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX40_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX40_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX40_OFST 0x274
#define | ALT_SYSMGR_PINMUX_GPLMUX41_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX41_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX41_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX41_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX41_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX41_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX41_OFST 0x278
#define | ALT_SYSMGR_PINMUX_GPLMUX42_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX42_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX42_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX42_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX42_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX42_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX42_OFST 0x27c
#define | ALT_SYSMGR_PINMUX_GPLMUX43_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX43_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX43_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX43_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX43_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX43_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX43_OFST 0x280
#define | ALT_SYSMGR_PINMUX_GPLMUX44_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX44_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX44_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX44_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX44_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX44_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX44_OFST 0x284
#define | ALT_SYSMGR_PINMUX_GPLMUX45_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX45_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX45_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX45_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX45_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX45_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX45_OFST 0x288
#define | ALT_SYSMGR_PINMUX_GPLMUX46_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX46_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX46_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX46_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX46_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX46_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX46_OFST 0x28c
#define | ALT_SYSMGR_PINMUX_GPLMUX47_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX47_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX47_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX47_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX47_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX47_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX47_OFST 0x290
#define | ALT_SYSMGR_PINMUX_GPLMUX48_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX48_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX48_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX48_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX48_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX48_OFST 0x294
#define | ALT_SYSMGR_PINMUX_GPLMUX49_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX49_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX49_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX49_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX49_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX49_OFST 0x298
#define | ALT_SYSMGR_PINMUX_GPLMUX50_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX50_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX50_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX50_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX50_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX50_OFST 0x29c
#define | ALT_SYSMGR_PINMUX_GPLMUX51_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX51_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX51_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX51_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX51_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX51_OFST 0x2a0
#define | ALT_SYSMGR_PINMUX_GPLMUX52_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX52_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX52_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX52_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX52_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX52_OFST 0x2a4
#define | ALT_SYSMGR_PINMUX_GPLMUX53_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX53_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX53_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX53_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX53_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX53_OFST 0x2a8
#define | ALT_SYSMGR_PINMUX_GPLMUX54_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX54_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX54_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX54_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX54_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX54_OFST 0x2ac
#define | ALT_SYSMGR_PINMUX_GPLMUX55_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX55_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX55_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX55_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX55_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX55_OFST 0x2b0
#define | ALT_SYSMGR_PINMUX_GPLMUX56_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX56_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX56_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX56_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX56_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX56_OFST 0x2b4
#define | ALT_SYSMGR_PINMUX_GPLMUX57_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX57_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX57_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX57_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX57_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX57_OFST 0x2b8
#define | ALT_SYSMGR_PINMUX_GPLMUX58_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX58_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX58_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX58_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX58_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX58_OFST 0x2bc
#define | ALT_SYSMGR_PINMUX_GPLMUX59_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX59_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX59_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX59_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX59_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX59_OFST 0x2c0
#define | ALT_SYSMGR_PINMUX_GPLMUX60_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX60_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX60_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX60_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX60_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX60_OFST 0x2c4
#define | ALT_SYSMGR_PINMUX_GPLMUX61_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX61_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX61_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX61_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX61_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX61_OFST 0x2c8
#define | ALT_SYSMGR_PINMUX_GPLMUX62_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX62_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX62_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX62_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX62_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX62_OFST 0x2cc
#define | ALT_SYSMGR_PINMUX_GPLMUX63_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX63_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX63_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX63_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX63_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX63_OFST 0x2d0
#define | ALT_SYSMGR_PINMUX_GPLMUX64_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX64_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX64_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX64_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX64_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX64_OFST 0x2d4
#define | ALT_SYSMGR_PINMUX_GPLMUX65_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX65_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX65_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX65_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX65_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX65_OFST 0x2d8
#define | ALT_SYSMGR_PINMUX_GPLMUX66_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX66_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX66_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX66_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX66_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX66_OFST 0x2dc
#define | ALT_SYSMGR_PINMUX_GPLMUX67_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX67_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX67_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX67_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX67_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX67_OFST 0x2e0
#define | ALT_SYSMGR_PINMUX_GPLMUX68_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX68_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX68_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX68_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX68_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX68_OFST 0x2e4
#define | ALT_SYSMGR_PINMUX_GPLMUX69_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX69_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX69_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX69_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX69_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX69_OFST 0x2e8
#define | ALT_SYSMGR_PINMUX_GPLMUX70_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX70_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_GPLMUX70_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_GPLMUX70_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_GPLMUX70_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_GPLMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_GPLMUX70_OFST 0x2ec
#define | ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_NANDUSEFPGA_OFST 0x2f0
#define | ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_RGMII1USEFPGA_OFST 0x2f8
#define | ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_I2C0USEFPGA_OFST 0x304
#define | ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_RGMII0USEFPGA_OFST 0x314
#define | ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_I2C3USEFPGA_OFST 0x324
#define | ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_I2C2USEFPGA_OFST 0x328
#define | ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_I2C1USEFPGA_OFST 0x32c
#define | ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_SPIM1USEFPGA_OFST 0x330
#define | ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_LSB 0
#define | ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_MSB 0
#define | ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_WIDTH 1
#define | ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET_MSK 0x00000001
#define | ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_CLR_MSK 0xfffffffe
#define | ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_RESET 0x0
#define | ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
#define | ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
#define | ALT_SYSMGR_PINMUX_SPIM0USEFPGA_OFST 0x338

## Typedefs
typedef volatile struct ALT_SYSMGR_SILICONID1_s | ALT_SYSMGR_SILICONID1_t
typedef volatile struct ALT_SYSMGR_SILICONID2_s | ALT_SYSMGR_SILICONID2_t
typedef volatile struct ALT_SYSMGR_WDDBG_s | ALT_SYSMGR_WDDBG_t
typedef volatile struct ALT_SYSMGR_BOOT_s | ALT_SYSMGR_BOOT_t
typedef volatile struct ALT_SYSMGR_HPSINFO_s | ALT_SYSMGR_HPSINFO_t
typedef volatile struct ALT_SYSMGR_PARITYINJ_s | ALT_SYSMGR_PARITYINJ_t
typedef volatile struct ALT_SYSMGR_FPGAINTF_GBL_s | ALT_SYSMGR_FPGAINTF_GBL_t
typedef volatile struct ALT_SYSMGR_FPGAINTF_INDIV_s | ALT_SYSMGR_FPGAINTF_INDIV_t
typedef volatile struct ALT_SYSMGR_FPGAINTF_MODULE_s | ALT_SYSMGR_FPGAINTF_MODULE_t
typedef volatile struct ALT_SYSMGR_FPGAINTF_s | ALT_SYSMGR_FPGAINTF_t
typedef volatile struct ALT_SYSMGR_FPGAINTF_raw_s | ALT_SYSMGR_FPGAINTF_raw_t
typedef volatile struct ALT_SYSMGR_SCANMGR_CTL_s | ALT_SYSMGR_SCANMGR_CTL_t
typedef volatile struct ALT_SYSMGR_SCANMGR_s | ALT_SYSMGR_SCANMGR_t
typedef volatile struct ALT_SYSMGR_SCANMGR_raw_s | ALT_SYSMGR_SCANMGR_raw_t
typedef volatile struct ALT_SYSMGR_FRZCTL_VIOCTL_s | ALT_SYSMGR_FRZCTL_VIOCTL_t
typedef volatile struct ALT_SYSMGR_FRZCTL_HIOCTL_s | ALT_SYSMGR_FRZCTL_HIOCTL_t
typedef volatile struct ALT_SYSMGR_FRZCTL_SRC_s | ALT_SYSMGR_FRZCTL_SRC_t
typedef volatile struct ALT_SYSMGR_FRZCTL_HWCTL_s | ALT_SYSMGR_FRZCTL_HWCTL_t
typedef volatile struct ALT_SYSMGR_FRZCTL_s | ALT_SYSMGR_FRZCTL_t
typedef volatile struct ALT_SYSMGR_FRZCTL_raw_s | ALT_SYSMGR_FRZCTL_raw_t
typedef volatile struct ALT_SYSMGR_EMAC_CTL_s | ALT_SYSMGR_EMAC_CTL_t
typedef volatile struct ALT_SYSMGR_EMAC_L3MST_s | ALT_SYSMGR_EMAC_L3MST_t
typedef volatile struct ALT_SYSMGR_EMAC_s | ALT_SYSMGR_EMAC_t
typedef volatile struct ALT_SYSMGR_EMAC_raw_s | ALT_SYSMGR_EMAC_raw_t
typedef volatile struct ALT_SYSMGR_DMA_CTL_s | ALT_SYSMGR_DMA_CTL_t
typedef volatile struct ALT_SYSMGR_DMA_PERSECURITY_s | ALT_SYSMGR_DMA_PERSECURITY_t
typedef volatile struct ALT_SYSMGR_DMA_s | ALT_SYSMGR_DMA_t
typedef volatile struct ALT_SYSMGR_DMA_raw_s | ALT_SYSMGR_DMA_raw_t
typedef volatile struct ALT_SYSMGR_ISW_HANDOFF_s | ALT_SYSMGR_ISW_HANDOFF_t
typedef volatile struct ALT_SYSMGR_ISW_s | ALT_SYSMGR_ISW_t
typedef volatile struct ALT_SYSMGR_ISW_raw_s | ALT_SYSMGR_ISW_raw_t
typedef volatile struct ALT_SYSMGR_ROMCODE_CTL_s | ALT_SYSMGR_ROMCODE_CTL_t
typedef volatile struct ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s | ALT_SYSMGR_ROMCODE_CPU1STARTADDR_t
typedef volatile struct ALT_SYSMGR_ROMCODE_INITSWSTATE_s | ALT_SYSMGR_ROMCODE_INITSWSTATE_t
typedef volatile struct ALT_SYSMGR_ROMCODE_INITSWLASTLD_s | ALT_SYSMGR_ROMCODE_INITSWLASTLD_t
typedef volatile struct ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_s | ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_t
typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_EN_s | ALT_SYSMGR_ROMCODE_WARMRAM_EN_t
typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_s | ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_t
typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_LEN_s | ALT_SYSMGR_ROMCODE_WARMRAM_LEN_t
typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_s | ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_t
typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_CRC_s | ALT_SYSMGR_ROMCODE_WARMRAM_CRC_t
typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_s | ALT_SYSMGR_ROMCODE_WARMRAM_t
typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_raw_s | ALT_SYSMGR_ROMCODE_WARMRAM_raw_t
typedef volatile struct ALT_SYSMGR_ROMCODE_s | ALT_SYSMGR_ROMCODE_t
typedef volatile struct ALT_SYSMGR_ROMCODE_raw_s | ALT_SYSMGR_ROMCODE_raw_t
typedef volatile struct ALT_SYSMGR_ROMHW_CTL_s | ALT_SYSMGR_ROMHW_CTL_t
typedef volatile struct ALT_SYSMGR_ROMHW_s | ALT_SYSMGR_ROMHW_t
typedef volatile struct ALT_SYSMGR_ROMHW_raw_s | ALT_SYSMGR_ROMHW_raw_t
typedef volatile struct ALT_SYSMGR_SDMMC_CTL_s | ALT_SYSMGR_SDMMC_CTL_t
typedef volatile struct ALT_SYSMGR_SDMMC_L3MST_s | ALT_SYSMGR_SDMMC_L3MST_t
typedef volatile struct ALT_SYSMGR_SDMMC_s | ALT_SYSMGR_SDMMC_t
typedef volatile struct ALT_SYSMGR_SDMMC_raw_s | ALT_SYSMGR_SDMMC_raw_t
typedef volatile struct ALT_SYSMGR_NAND_BOOTSTRAP_s | ALT_SYSMGR_NAND_BOOTSTRAP_t
typedef volatile struct ALT_SYSMGR_NAND_L3MST_s | ALT_SYSMGR_NAND_L3MST_t
typedef volatile struct ALT_SYSMGR_NAND_s | ALT_SYSMGR_NAND_t
typedef volatile struct ALT_SYSMGR_NAND_raw_s | ALT_SYSMGR_NAND_raw_t
typedef volatile struct ALT_SYSMGR_USB_L3MST_s | ALT_SYSMGR_USB_L3MST_t
typedef volatile struct ALT_SYSMGR_USB_s | ALT_SYSMGR_USB_t
typedef volatile struct ALT_SYSMGR_USB_raw_s | ALT_SYSMGR_USB_raw_t
typedef volatile struct ALT_SYSMGR_ECC_L2_s | ALT_SYSMGR_ECC_L2_t
typedef volatile struct ALT_SYSMGR_ECC_OCRAM_s | ALT_SYSMGR_ECC_OCRAM_t
typedef volatile struct ALT_SYSMGR_ECC_USB0_s | ALT_SYSMGR_ECC_USB0_t
typedef volatile struct ALT_SYSMGR_ECC_USB1_s | ALT_SYSMGR_ECC_USB1_t
typedef volatile struct ALT_SYSMGR_ECC_EMAC0_s | ALT_SYSMGR_ECC_EMAC0_t
typedef volatile struct ALT_SYSMGR_ECC_EMAC1_s | ALT_SYSMGR_ECC_EMAC1_t
typedef volatile struct ALT_SYSMGR_ECC_DMA_s | ALT_SYSMGR_ECC_DMA_t
typedef volatile struct ALT_SYSMGR_ECC_CAN0_s | ALT_SYSMGR_ECC_CAN0_t
typedef volatile struct ALT_SYSMGR_ECC_CAN1_s | ALT_SYSMGR_ECC_CAN1_t
typedef volatile struct ALT_SYSMGR_ECC_NAND_s | ALT_SYSMGR_ECC_NAND_t
typedef volatile struct ALT_SYSMGR_ECC_QSPI_s | ALT_SYSMGR_ECC_QSPI_t
typedef volatile struct ALT_SYSMGR_ECC_SDMMC_s | ALT_SYSMGR_ECC_SDMMC_t
typedef volatile struct ALT_SYSMGR_ECC_s | ALT_SYSMGR_ECC_t
typedef volatile struct ALT_SYSMGR_ECC_raw_s | ALT_SYSMGR_ECC_raw_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO0_s | ALT_SYSMGR_PINMUX_EMACIO0_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO1_s | ALT_SYSMGR_PINMUX_EMACIO1_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO2_s | ALT_SYSMGR_PINMUX_EMACIO2_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO3_s | ALT_SYSMGR_PINMUX_EMACIO3_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO4_s | ALT_SYSMGR_PINMUX_EMACIO4_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO5_s | ALT_SYSMGR_PINMUX_EMACIO5_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO6_s | ALT_SYSMGR_PINMUX_EMACIO6_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO7_s | ALT_SYSMGR_PINMUX_EMACIO7_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO8_s | ALT_SYSMGR_PINMUX_EMACIO8_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO9_s | ALT_SYSMGR_PINMUX_EMACIO9_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO10_s | ALT_SYSMGR_PINMUX_EMACIO10_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO11_s | ALT_SYSMGR_PINMUX_EMACIO11_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO12_s | ALT_SYSMGR_PINMUX_EMACIO12_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO13_s | ALT_SYSMGR_PINMUX_EMACIO13_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO14_s | ALT_SYSMGR_PINMUX_EMACIO14_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO15_s | ALT_SYSMGR_PINMUX_EMACIO15_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO16_s | ALT_SYSMGR_PINMUX_EMACIO16_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO17_s | ALT_SYSMGR_PINMUX_EMACIO17_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO18_s | ALT_SYSMGR_PINMUX_EMACIO18_t
typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO19_s | ALT_SYSMGR_PINMUX_EMACIO19_t
typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO0_s | ALT_SYSMGR_PINMUX_FLSHIO0_t
typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO1_s | ALT_SYSMGR_PINMUX_FLSHIO1_t
typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO2_s | ALT_SYSMGR_PINMUX_FLSHIO2_t
typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO3_s | ALT_SYSMGR_PINMUX_FLSHIO3_t
typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO4_s | ALT_SYSMGR_PINMUX_FLSHIO4_t
typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO5_s | ALT_SYSMGR_PINMUX_FLSHIO5_t
typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO6_s | ALT_SYSMGR_PINMUX_FLSHIO6_t
typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO7_s | ALT_SYSMGR_PINMUX_FLSHIO7_t
typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO8_s | ALT_SYSMGR_PINMUX_FLSHIO8_t
typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO9_s | ALT_SYSMGR_PINMUX_FLSHIO9_t
typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO10_s | ALT_SYSMGR_PINMUX_FLSHIO10_t
typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO11_s | ALT_SYSMGR_PINMUX_FLSHIO11_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO0_s | ALT_SYSMGR_PINMUX_GENERALIO0_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO1_s | ALT_SYSMGR_PINMUX_GENERALIO1_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO2_s | ALT_SYSMGR_PINMUX_GENERALIO2_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO3_s | ALT_SYSMGR_PINMUX_GENERALIO3_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO4_s | ALT_SYSMGR_PINMUX_GENERALIO4_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO5_s | ALT_SYSMGR_PINMUX_GENERALIO5_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO6_s | ALT_SYSMGR_PINMUX_GENERALIO6_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO7_s | ALT_SYSMGR_PINMUX_GENERALIO7_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO8_s | ALT_SYSMGR_PINMUX_GENERALIO8_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO9_s | ALT_SYSMGR_PINMUX_GENERALIO9_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO10_s | ALT_SYSMGR_PINMUX_GENERALIO10_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO11_s | ALT_SYSMGR_PINMUX_GENERALIO11_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO12_s | ALT_SYSMGR_PINMUX_GENERALIO12_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO13_s | ALT_SYSMGR_PINMUX_GENERALIO13_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO14_s | ALT_SYSMGR_PINMUX_GENERALIO14_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO15_s | ALT_SYSMGR_PINMUX_GENERALIO15_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO16_s | ALT_SYSMGR_PINMUX_GENERALIO16_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO17_s | ALT_SYSMGR_PINMUX_GENERALIO17_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO18_s | ALT_SYSMGR_PINMUX_GENERALIO18_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO19_s | ALT_SYSMGR_PINMUX_GENERALIO19_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO20_s | ALT_SYSMGR_PINMUX_GENERALIO20_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO21_s | ALT_SYSMGR_PINMUX_GENERALIO21_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO22_s | ALT_SYSMGR_PINMUX_GENERALIO22_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO23_s | ALT_SYSMGR_PINMUX_GENERALIO23_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO24_s | ALT_SYSMGR_PINMUX_GENERALIO24_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO25_s | ALT_SYSMGR_PINMUX_GENERALIO25_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO26_s | ALT_SYSMGR_PINMUX_GENERALIO26_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO27_s | ALT_SYSMGR_PINMUX_GENERALIO27_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO28_s | ALT_SYSMGR_PINMUX_GENERALIO28_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO29_s | ALT_SYSMGR_PINMUX_GENERALIO29_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO30_s | ALT_SYSMGR_PINMUX_GENERALIO30_t
typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO31_s | ALT_SYSMGR_PINMUX_GENERALIO31_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO0_s | ALT_SYSMGR_PINMUX_MIXED1IO0_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO1_s | ALT_SYSMGR_PINMUX_MIXED1IO1_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO2_s | ALT_SYSMGR_PINMUX_MIXED1IO2_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO3_s | ALT_SYSMGR_PINMUX_MIXED1IO3_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO4_s | ALT_SYSMGR_PINMUX_MIXED1IO4_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO5_s | ALT_SYSMGR_PINMUX_MIXED1IO5_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO6_s | ALT_SYSMGR_PINMUX_MIXED1IO6_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO7_s | ALT_SYSMGR_PINMUX_MIXED1IO7_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO8_s | ALT_SYSMGR_PINMUX_MIXED1IO8_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO9_s | ALT_SYSMGR_PINMUX_MIXED1IO9_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO10_s | ALT_SYSMGR_PINMUX_MIXED1IO10_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO11_s | ALT_SYSMGR_PINMUX_MIXED1IO11_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO12_s | ALT_SYSMGR_PINMUX_MIXED1IO12_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO13_s | ALT_SYSMGR_PINMUX_MIXED1IO13_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO14_s | ALT_SYSMGR_PINMUX_MIXED1IO14_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO15_s | ALT_SYSMGR_PINMUX_MIXED1IO15_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO16_s | ALT_SYSMGR_PINMUX_MIXED1IO16_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO17_s | ALT_SYSMGR_PINMUX_MIXED1IO17_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO18_s | ALT_SYSMGR_PINMUX_MIXED1IO18_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO19_s | ALT_SYSMGR_PINMUX_MIXED1IO19_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO20_s | ALT_SYSMGR_PINMUX_MIXED1IO20_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO21_s | ALT_SYSMGR_PINMUX_MIXED1IO21_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO0_s | ALT_SYSMGR_PINMUX_MIXED2IO0_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO1_s | ALT_SYSMGR_PINMUX_MIXED2IO1_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO2_s | ALT_SYSMGR_PINMUX_MIXED2IO2_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO3_s | ALT_SYSMGR_PINMUX_MIXED2IO3_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO4_s | ALT_SYSMGR_PINMUX_MIXED2IO4_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO5_s | ALT_SYSMGR_PINMUX_MIXED2IO5_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO6_s | ALT_SYSMGR_PINMUX_MIXED2IO6_t
typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO7_s | ALT_SYSMGR_PINMUX_MIXED2IO7_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX48_s | ALT_SYSMGR_PINMUX_GPLINMUX48_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX49_s | ALT_SYSMGR_PINMUX_GPLINMUX49_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX50_s | ALT_SYSMGR_PINMUX_GPLINMUX50_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX51_s | ALT_SYSMGR_PINMUX_GPLINMUX51_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX52_s | ALT_SYSMGR_PINMUX_GPLINMUX52_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX53_s | ALT_SYSMGR_PINMUX_GPLINMUX53_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX54_s | ALT_SYSMGR_PINMUX_GPLINMUX54_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX55_s | ALT_SYSMGR_PINMUX_GPLINMUX55_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX56_s | ALT_SYSMGR_PINMUX_GPLINMUX56_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX57_s | ALT_SYSMGR_PINMUX_GPLINMUX57_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX58_s | ALT_SYSMGR_PINMUX_GPLINMUX58_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX59_s | ALT_SYSMGR_PINMUX_GPLINMUX59_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX60_s | ALT_SYSMGR_PINMUX_GPLINMUX60_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX61_s | ALT_SYSMGR_PINMUX_GPLINMUX61_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX62_s | ALT_SYSMGR_PINMUX_GPLINMUX62_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX63_s | ALT_SYSMGR_PINMUX_GPLINMUX63_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX64_s | ALT_SYSMGR_PINMUX_GPLINMUX64_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX65_s | ALT_SYSMGR_PINMUX_GPLINMUX65_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX66_s | ALT_SYSMGR_PINMUX_GPLINMUX66_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX67_s | ALT_SYSMGR_PINMUX_GPLINMUX67_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX68_s | ALT_SYSMGR_PINMUX_GPLINMUX68_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX69_s | ALT_SYSMGR_PINMUX_GPLINMUX69_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX70_s | ALT_SYSMGR_PINMUX_GPLINMUX70_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX0_s | ALT_SYSMGR_PINMUX_GPLMUX0_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX1_s | ALT_SYSMGR_PINMUX_GPLMUX1_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX2_s | ALT_SYSMGR_PINMUX_GPLMUX2_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX3_s | ALT_SYSMGR_PINMUX_GPLMUX3_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX4_s | ALT_SYSMGR_PINMUX_GPLMUX4_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX5_s | ALT_SYSMGR_PINMUX_GPLMUX5_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX6_s | ALT_SYSMGR_PINMUX_GPLMUX6_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX7_s | ALT_SYSMGR_PINMUX_GPLMUX7_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX8_s | ALT_SYSMGR_PINMUX_GPLMUX8_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX9_s | ALT_SYSMGR_PINMUX_GPLMUX9_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX10_s | ALT_SYSMGR_PINMUX_GPLMUX10_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX11_s | ALT_SYSMGR_PINMUX_GPLMUX11_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX12_s | ALT_SYSMGR_PINMUX_GPLMUX12_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX13_s | ALT_SYSMGR_PINMUX_GPLMUX13_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX14_s | ALT_SYSMGR_PINMUX_GPLMUX14_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX15_s | ALT_SYSMGR_PINMUX_GPLMUX15_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX16_s | ALT_SYSMGR_PINMUX_GPLMUX16_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX17_s | ALT_SYSMGR_PINMUX_GPLMUX17_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX18_s | ALT_SYSMGR_PINMUX_GPLMUX18_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX19_s | ALT_SYSMGR_PINMUX_GPLMUX19_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX20_s | ALT_SYSMGR_PINMUX_GPLMUX20_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX21_s | ALT_SYSMGR_PINMUX_GPLMUX21_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX22_s | ALT_SYSMGR_PINMUX_GPLMUX22_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX23_s | ALT_SYSMGR_PINMUX_GPLMUX23_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX24_s | ALT_SYSMGR_PINMUX_GPLMUX24_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX25_s | ALT_SYSMGR_PINMUX_GPLMUX25_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX26_s | ALT_SYSMGR_PINMUX_GPLMUX26_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX27_s | ALT_SYSMGR_PINMUX_GPLMUX27_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX28_s | ALT_SYSMGR_PINMUX_GPLMUX28_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX29_s | ALT_SYSMGR_PINMUX_GPLMUX29_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX30_s | ALT_SYSMGR_PINMUX_GPLMUX30_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX31_s | ALT_SYSMGR_PINMUX_GPLMUX31_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX32_s | ALT_SYSMGR_PINMUX_GPLMUX32_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX33_s | ALT_SYSMGR_PINMUX_GPLMUX33_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX34_s | ALT_SYSMGR_PINMUX_GPLMUX34_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX35_s | ALT_SYSMGR_PINMUX_GPLMUX35_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX36_s | ALT_SYSMGR_PINMUX_GPLMUX36_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX37_s | ALT_SYSMGR_PINMUX_GPLMUX37_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX38_s | ALT_SYSMGR_PINMUX_GPLMUX38_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX39_s | ALT_SYSMGR_PINMUX_GPLMUX39_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX40_s | ALT_SYSMGR_PINMUX_GPLMUX40_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX41_s | ALT_SYSMGR_PINMUX_GPLMUX41_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX42_s | ALT_SYSMGR_PINMUX_GPLMUX42_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX43_s | ALT_SYSMGR_PINMUX_GPLMUX43_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX44_s | ALT_SYSMGR_PINMUX_GPLMUX44_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX45_s | ALT_SYSMGR_PINMUX_GPLMUX45_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX46_s | ALT_SYSMGR_PINMUX_GPLMUX46_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX47_s | ALT_SYSMGR_PINMUX_GPLMUX47_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX48_s | ALT_SYSMGR_PINMUX_GPLMUX48_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX49_s | ALT_SYSMGR_PINMUX_GPLMUX49_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX50_s | ALT_SYSMGR_PINMUX_GPLMUX50_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX51_s | ALT_SYSMGR_PINMUX_GPLMUX51_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX52_s | ALT_SYSMGR_PINMUX_GPLMUX52_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX53_s | ALT_SYSMGR_PINMUX_GPLMUX53_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX54_s | ALT_SYSMGR_PINMUX_GPLMUX54_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX55_s | ALT_SYSMGR_PINMUX_GPLMUX55_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX56_s | ALT_SYSMGR_PINMUX_GPLMUX56_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX57_s | ALT_SYSMGR_PINMUX_GPLMUX57_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX58_s | ALT_SYSMGR_PINMUX_GPLMUX58_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX59_s | ALT_SYSMGR_PINMUX_GPLMUX59_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX60_s | ALT_SYSMGR_PINMUX_GPLMUX60_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX61_s | ALT_SYSMGR_PINMUX_GPLMUX61_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX62_s | ALT_SYSMGR_PINMUX_GPLMUX62_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX63_s | ALT_SYSMGR_PINMUX_GPLMUX63_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX64_s | ALT_SYSMGR_PINMUX_GPLMUX64_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX65_s | ALT_SYSMGR_PINMUX_GPLMUX65_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX66_s | ALT_SYSMGR_PINMUX_GPLMUX66_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX67_s | ALT_SYSMGR_PINMUX_GPLMUX67_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX68_s | ALT_SYSMGR_PINMUX_GPLMUX68_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX69_s | ALT_SYSMGR_PINMUX_GPLMUX69_t
typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX70_s | ALT_SYSMGR_PINMUX_GPLMUX70_t
typedef volatile struct ALT_SYSMGR_PINMUX_NANDUSEFPGA_s | ALT_SYSMGR_PINMUX_NANDUSEFPGA_t
typedef volatile struct ALT_SYSMGR_PINMUX_RGMII1USEFPGA_s | ALT_SYSMGR_PINMUX_RGMII1USEFPGA_t
typedef volatile struct ALT_SYSMGR_PINMUX_I2C0USEFPGA_s | ALT_SYSMGR_PINMUX_I2C0USEFPGA_t
typedef volatile struct ALT_SYSMGR_PINMUX_RGMII0USEFPGA_s | ALT_SYSMGR_PINMUX_RGMII0USEFPGA_t
typedef volatile struct ALT_SYSMGR_PINMUX_I2C3USEFPGA_s | ALT_SYSMGR_PINMUX_I2C3USEFPGA_t
typedef volatile struct ALT_SYSMGR_PINMUX_I2C2USEFPGA_s | ALT_SYSMGR_PINMUX_I2C2USEFPGA_t
typedef volatile struct ALT_SYSMGR_PINMUX_I2C1USEFPGA_s | ALT_SYSMGR_PINMUX_I2C1USEFPGA_t
typedef volatile struct ALT_SYSMGR_PINMUX_SPIM1USEFPGA_s | ALT_SYSMGR_PINMUX_SPIM1USEFPGA_t
typedef volatile struct ALT_SYSMGR_PINMUX_SPIM0USEFPGA_s | ALT_SYSMGR_PINMUX_SPIM0USEFPGA_t
typedef volatile struct ALT_SYSMGR_PINMUX_s | ALT_SYSMGR_PINMUX_t
typedef volatile struct ALT_SYSMGR_PINMUX_raw_s | ALT_SYSMGR_PINMUX_raw_t
typedef volatile struct ALT_SYSMGR_s | ALT_SYSMGR_t
typedef volatile struct ALT_SYSMGR_raw_s | ALT_SYSMGR_raw_t