RTEMS: bsps/mips/jmr3904/include/tm27.h File Reference

| RTEMS 5.4-rc2

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Macros
tm27.h File Reference
`#include <bsp/irq.h>`

Go to the source code of this file.

## Macros
#define | MUST_WAIT_FOR_INTERRUPT 1
#define | Install_tm27_vector(handler)
#define | Cause_tm27_intr()
#define | Clear_tm27_intr()
#define | Lower_tm27_intr() mips_enable_in_interrupt_mask( 0xff01 );

## Macro Definition Documentation

## ◆ Cause_tm27_intr

#define Cause_tm27_intr | ( |  | void | ) |

Value:
do { \
uint32_t _clicks = 20; \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, _clicks ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR, 0xC0 ); \
*((volatile uint32_t*) 0xFFFFC01C) = 0x00000700; \
} while(0)

## ◆ Clear_tm27_intr

#define Clear_tm27_intr | ( |  | void | ) |

Value:
do { \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x0001 ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \
} while(0)

## ◆ Install_tm27_vector

#define Install_tm27_vector | ( |  | handler | ) |

Value:
rtems_interrupt_handler_install( \
TX3904_IRQ_TMR0, "benchmark", 0, \
(rtems_interrupt_handler)handler, NULL );
NULL
#define NULL
Requests a GPIO pin group configuration.
Definition: bestcomm_api.h:77
rtems_interrupt_handler_install
rtems_status_code rtems_interrupt_handler_install(rtems_vector_number vector, const char *info, rtems_option options, rtems_interrupt_handler handler, void *arg)
Installs the interrupt handler routine handler for the interrupt vector with number vector.
Definition: irq.c:127
rtems_interrupt_handler
void(* rtems_interrupt_handler)(void *)
Interrupt handler routine type.
Definition: irq-extension.h:79