RTEMS: bsps/arm/atsam/include/libchip/include/same70/component/component_matrix.h Source File

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component_matrix.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAME70_MATRIX_COMPONENT_
31#define _SAME70_MATRIX_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41 typedef struct {
42 __IO uint32_t MATRIX_PRAS;
43 __IO uint32_t MATRIX_PRBS;
44} MatrixPr;
46#define MATRIXPR_NUMBER 9
47 typedef struct {
48 __IO uint32_t MATRIX_MCFG0;
49 __IO uint32_t MATRIX_MCFG1;
50 __IO uint32_t MATRIX_MCFG2;
51 __IO uint32_t MATRIX_MCFG3;
52 __IO uint32_t MATRIX_MCFG4;
53 __IO uint32_t MATRIX_MCFG5;
54 __IO uint32_t MATRIX_MCFG6;
55 __I uint32_t Reserved1[1];
56 __IO uint32_t MATRIX_MCFG8;
57 __IO uint32_t MATRIX_MCFG9;
58 __IO uint32_t MATRIX_MCFG10;
59 __IO uint32_t MATRIX_MCFG11;
60 __I uint32_t Reserved2[4];
61 __IO uint32_t MATRIX_SCFG[9];
62 __I uint32_t Reserved3[7];
63 MatrixPr MATRIX_PR[MATRIXPR_NUMBER];
64 __I uint32_t Reserved4[14];
65 __IO uint32_t MATRIX_MRCR;
66 __I uint32_t Reserved5[3];
67 __IO uint32_t CCFG_CAN0;
68 __IO uint32_t CCFG_SYSIO;
69 __I uint32_t Reserved6[3];
70 __IO uint32_t CCFG_SMCNFCS;
71 __I uint32_t Reserved7[47];
72 __IO uint32_t MATRIX_WPMR;
73 __I uint32_t MATRIX_WPSR;
74} Matrix;
75#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
76/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */
77#define MATRIX_MCFG0_ULBT_Pos 0
78#define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos)
79#define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos)))
80#define MATRIX_MCFG0_ULBT_UNLTD_LENGTH (0x0u << 0)
81#define MATRIX_MCFG0_ULBT_SINGLE_ACCESS (0x1u << 0)
82#define MATRIX_MCFG0_ULBT_4BEAT_BURST (0x2u << 0)
83#define MATRIX_MCFG0_ULBT_8BEAT_BURST (0x3u << 0)
84#define MATRIX_MCFG0_ULBT_16BEAT_BURST (0x4u << 0)
85#define MATRIX_MCFG0_ULBT_32BEAT_BURST (0x5u << 0)
86#define MATRIX_MCFG0_ULBT_64BEAT_BURST (0x6u << 0)
87#define MATRIX_MCFG0_ULBT_128BEAT_BURST (0x7u << 0)
88/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */
89#define MATRIX_MCFG1_ULBT_Pos 0
90#define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos)
91#define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos)))
92#define MATRIX_MCFG1_ULBT_UNLTD_LENGTH (0x0u << 0)
93#define MATRIX_MCFG1_ULBT_SINGLE_ACCESS (0x1u << 0)
94#define MATRIX_MCFG1_ULBT_4BEAT_BURST (0x2u << 0)
95#define MATRIX_MCFG1_ULBT_8BEAT_BURST (0x3u << 0)
96#define MATRIX_MCFG1_ULBT_16BEAT_BURST (0x4u << 0)
97#define MATRIX_MCFG1_ULBT_32BEAT_BURST (0x5u << 0)
98#define MATRIX_MCFG1_ULBT_64BEAT_BURST (0x6u << 0)
99#define MATRIX_MCFG1_ULBT_128BEAT_BURST (0x7u << 0)
100/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */
101#define MATRIX_MCFG2_ULBT_Pos 0
102#define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos)
103#define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos)))
104#define MATRIX_MCFG2_ULBT_UNLTD_LENGTH (0x0u << 0)
105#define MATRIX_MCFG2_ULBT_SINGLE_ACCESS (0x1u << 0)
106#define MATRIX_MCFG2_ULBT_4BEAT_BURST (0x2u << 0)
107#define MATRIX_MCFG2_ULBT_8BEAT_BURST (0x3u << 0)
108#define MATRIX_MCFG2_ULBT_16BEAT_BURST (0x4u << 0)
109#define MATRIX_MCFG2_ULBT_32BEAT_BURST (0x5u << 0)
110#define MATRIX_MCFG2_ULBT_64BEAT_BURST (0x6u << 0)
111#define MATRIX_MCFG2_ULBT_128BEAT_BURST (0x7u << 0)
112/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */
113#define MATRIX_MCFG3_ULBT_Pos 0
114#define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos)
115#define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos)))
116#define MATRIX_MCFG3_ULBT_UNLTD_LENGTH (0x0u << 0)
117#define MATRIX_MCFG3_ULBT_SINGLE_ACCESS (0x1u << 0)
118#define MATRIX_MCFG3_ULBT_4BEAT_BURST (0x2u << 0)
119#define MATRIX_MCFG3_ULBT_8BEAT_BURST (0x3u << 0)
120#define MATRIX_MCFG3_ULBT_16BEAT_BURST (0x4u << 0)
121#define MATRIX_MCFG3_ULBT_32BEAT_BURST (0x5u << 0)
122#define MATRIX_MCFG3_ULBT_64BEAT_BURST (0x6u << 0)
123#define MATRIX_MCFG3_ULBT_128BEAT_BURST (0x7u << 0)
124/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */
125#define MATRIX_MCFG4_ULBT_Pos 0
126#define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos)
127#define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos)))
128#define MATRIX_MCFG4_ULBT_UNLTD_LENGTH (0x0u << 0)
129#define MATRIX_MCFG4_ULBT_SINGLE_ACCESS (0x1u << 0)
130#define MATRIX_MCFG4_ULBT_4BEAT_BURST (0x2u << 0)
131#define MATRIX_MCFG4_ULBT_8BEAT_BURST (0x3u << 0)
132#define MATRIX_MCFG4_ULBT_16BEAT_BURST (0x4u << 0)
133#define MATRIX_MCFG4_ULBT_32BEAT_BURST (0x5u << 0)
134#define MATRIX_MCFG4_ULBT_64BEAT_BURST (0x6u << 0)
135#define MATRIX_MCFG4_ULBT_128BEAT_BURST (0x7u << 0)
136/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */
137#define MATRIX_MCFG5_ULBT_Pos 0
138#define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos)
139#define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos)))
140#define MATRIX_MCFG5_ULBT_UNLTD_LENGTH (0x0u << 0)
141#define MATRIX_MCFG5_ULBT_SINGLE_ACCESS (0x1u << 0)
142#define MATRIX_MCFG5_ULBT_4BEAT_BURST (0x2u << 0)
143#define MATRIX_MCFG5_ULBT_8BEAT_BURST (0x3u << 0)
144#define MATRIX_MCFG5_ULBT_16BEAT_BURST (0x4u << 0)
145#define MATRIX_MCFG5_ULBT_32BEAT_BURST (0x5u << 0)
146#define MATRIX_MCFG5_ULBT_64BEAT_BURST (0x6u << 0)
147#define MATRIX_MCFG5_ULBT_128BEAT_BURST (0x7u << 0)
148/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */
149#define MATRIX_MCFG6_ULBT_Pos 0
150#define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos)
151#define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos)))
152#define MATRIX_MCFG6_ULBT_UNLTD_LENGTH (0x0u << 0)
153#define MATRIX_MCFG6_ULBT_SINGLE_ACCESS (0x1u << 0)
154#define MATRIX_MCFG6_ULBT_4BEAT_BURST (0x2u << 0)
155#define MATRIX_MCFG6_ULBT_8BEAT_BURST (0x3u << 0)
156#define MATRIX_MCFG6_ULBT_16BEAT_BURST (0x4u << 0)
157#define MATRIX_MCFG6_ULBT_32BEAT_BURST (0x5u << 0)
158#define MATRIX_MCFG6_ULBT_64BEAT_BURST (0x6u << 0)
159#define MATRIX_MCFG6_ULBT_128BEAT_BURST (0x7u << 0)
160/* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */
161#define MATRIX_MCFG8_ULBT_Pos 0
162#define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos)
163#define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos)))
164#define MATRIX_MCFG8_ULBT_UNLTD_LENGTH (0x0u << 0)
165#define MATRIX_MCFG8_ULBT_SINGLE_ACCESS (0x1u << 0)
166#define MATRIX_MCFG8_ULBT_4BEAT_BURST (0x2u << 0)
167#define MATRIX_MCFG8_ULBT_8BEAT_BURST (0x3u << 0)
168#define MATRIX_MCFG8_ULBT_16BEAT_BURST (0x4u << 0)
169#define MATRIX_MCFG8_ULBT_32BEAT_BURST (0x5u << 0)
170#define MATRIX_MCFG8_ULBT_64BEAT_BURST (0x6u << 0)
171#define MATRIX_MCFG8_ULBT_128BEAT_BURST (0x7u << 0)
172/* -------- MATRIX_MCFG9 : (MATRIX Offset: 0x0024) Master Configuration Register 9 -------- */
173#define MATRIX_MCFG9_ULBT_Pos 0
174#define MATRIX_MCFG9_ULBT_Msk (0x7u << MATRIX_MCFG9_ULBT_Pos)
175#define MATRIX_MCFG9_ULBT(value) ((MATRIX_MCFG9_ULBT_Msk & ((value) << MATRIX_MCFG9_ULBT_Pos)))
176#define MATRIX_MCFG9_ULBT_UNLTD_LENGTH (0x0u << 0)
177#define MATRIX_MCFG9_ULBT_SINGLE_ACCESS (0x1u << 0)
178#define MATRIX_MCFG9_ULBT_4BEAT_BURST (0x2u << 0)
179#define MATRIX_MCFG9_ULBT_8BEAT_BURST (0x3u << 0)
180#define MATRIX_MCFG9_ULBT_16BEAT_BURST (0x4u << 0)
181#define MATRIX_MCFG9_ULBT_32BEAT_BURST (0x5u << 0)
182#define MATRIX_MCFG9_ULBT_64BEAT_BURST (0x6u << 0)
183#define MATRIX_MCFG9_ULBT_128BEAT_BURST (0x7u << 0)
184/* -------- MATRIX_MCFG10 : (MATRIX Offset: 0x0028) Master Configuration Register 10 -------- */
185#define MATRIX_MCFG10_ULBT_Pos 0
186#define MATRIX_MCFG10_ULBT_Msk (0x7u << MATRIX_MCFG10_ULBT_Pos)
187#define MATRIX_MCFG10_ULBT(value) ((MATRIX_MCFG10_ULBT_Msk & ((value) << MATRIX_MCFG10_ULBT_Pos)))
188#define MATRIX_MCFG10_ULBT_UNLTD_LENGTH (0x0u << 0)
189#define MATRIX_MCFG10_ULBT_SINGLE_ACCESS (0x1u << 0)
190#define MATRIX_MCFG10_ULBT_4BEAT_BURST (0x2u << 0)
191#define MATRIX_MCFG10_ULBT_8BEAT_BURST (0x3u << 0)
192#define MATRIX_MCFG10_ULBT_16BEAT_BURST (0x4u << 0)
193#define MATRIX_MCFG10_ULBT_32BEAT_BURST (0x5u << 0)
194#define MATRIX_MCFG10_ULBT_64BEAT_BURST (0x6u << 0)
195#define MATRIX_MCFG10_ULBT_128BEAT_BURST (0x7u << 0)
196/* -------- MATRIX_MCFG11 : (MATRIX Offset: 0x002C) Master Configuration Register 11 -------- */
197#define MATRIX_MCFG11_ULBT_Pos 0
198#define MATRIX_MCFG11_ULBT_Msk (0x7u << MATRIX_MCFG11_ULBT_Pos)
199#define MATRIX_MCFG11_ULBT(value) ((MATRIX_MCFG11_ULBT_Msk & ((value) << MATRIX_MCFG11_ULBT_Pos)))
200#define MATRIX_MCFG11_ULBT_UNLTD_LENGTH (0x0u << 0)
201#define MATRIX_MCFG11_ULBT_SINGLE_ACCESS (0x1u << 0)
202#define MATRIX_MCFG11_ULBT_4BEAT_BURST (0x2u << 0)
203#define MATRIX_MCFG11_ULBT_8BEAT_BURST (0x3u << 0)
204#define MATRIX_MCFG11_ULBT_16BEAT_BURST (0x4u << 0)
205#define MATRIX_MCFG11_ULBT_32BEAT_BURST (0x5u << 0)
206#define MATRIX_MCFG11_ULBT_64BEAT_BURST (0x6u << 0)
207#define MATRIX_MCFG11_ULBT_128BEAT_BURST (0x7u << 0)
208/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
209#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
210#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos)
211#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
212#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
213#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos)
214#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
215#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16)
216#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16)
217#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16)
218#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
219#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos)
220#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
221/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */
222#define MATRIX_PRAS_M0PR_Pos 0
223#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos)
224#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos)))
225#define MATRIX_PRAS_M1PR_Pos 4
226#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos)
227#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos)))
228#define MATRIX_PRAS_M2PR_Pos 8
229#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos)
230#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos)))
231#define MATRIX_PRAS_M3PR_Pos 12
232#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos)
233#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos)))
234#define MATRIX_PRAS_M4PR_Pos 16
235#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos)
236#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos)))
237#define MATRIX_PRAS_M5PR_Pos 20
238#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos)
239#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos)))
240#define MATRIX_PRAS_M6PR_Pos 24
241#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos)
242#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos)))
243/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */
244#define MATRIX_PRBS_M8PR_Pos 0
245#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos)
246#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos)))
247#define MATRIX_PRBS_M9PR_Pos 4
248#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos)
249#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos)))
250#define MATRIX_PRBS_M10PR_Pos 8
251#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos)
252#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos)))
253#define MATRIX_PRBS_M11PR_Pos 12
254#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos)
255#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos)))
256/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
257#define MATRIX_MRCR_RCB0 (0x1u << 0)
258#define MATRIX_MRCR_RCB1 (0x1u << 1)
259#define MATRIX_MRCR_RCB2 (0x1u << 2)
260#define MATRIX_MRCR_RCB3 (0x1u << 3)
261#define MATRIX_MRCR_RCB4 (0x1u << 4)
262#define MATRIX_MRCR_RCB5 (0x1u << 5)
263#define MATRIX_MRCR_RCB6 (0x1u << 6)
264#define MATRIX_MRCR_RCB8 (0x1u << 8)
265#define MATRIX_MRCR_RCB9 (0x1u << 9)
266#define MATRIX_MRCR_RCB10 (0x1u << 10)
267#define MATRIX_MRCR_RCB11 (0x1u << 11)
268/* -------- CCFG_CAN0 : (MATRIX Offset: 0x0110) CAN0 Configuration Register -------- */
269#define CCFG_CAN0_CAN0DMABA_Pos 16
270#define CCFG_CAN0_CAN0DMABA_Msk (0xffffu << CCFG_CAN0_CAN0DMABA_Pos)
271#define CCFG_CAN0_CAN0DMABA(value) ((CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos)))
272/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O and CAN1 Configuration Register -------- */
273#define CCFG_SYSIO_SYSIO4 (0x1u << 4)
274#define CCFG_SYSIO_SYSIO5 (0x1u << 5)
275#define CCFG_SYSIO_SYSIO6 (0x1u << 6)
276#define CCFG_SYSIO_SYSIO7 (0x1u << 7)
277#define CCFG_SYSIO_SYSIO12 (0x1u << 12)
278#define CCFG_SYSIO_CAN1DMABA_Pos 16
279#define CCFG_SYSIO_CAN1DMABA_Msk (0xffffu << CCFG_SYSIO_CAN1DMABA_Pos)
280#define CCFG_SYSIO_CAN1DMABA(value) ((CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos)))
281/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */
282#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0)
283#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1)
284#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2)
285#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3)
286#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4)
287/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */
288#define MATRIX_WPMR_WPEN (0x1u << 0)
289#define MATRIX_WPMR_WPKEY_Pos 8
290#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos)
291#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
292#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8)
293/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */
294#define MATRIX_WPSR_WPVS (0x1u << 0)
295#define MATRIX_WPSR_WPVSRC_Pos 8
296#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos)
299
300
301#endif /* _SAME70_MATRIX_COMPONENT_ */
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
MatrixPr
MatrixPr hardware registers.
Definition: component_matrix.h:41
MatrixPr::MATRIX_PRBS
__IO uint32_t MATRIX_PRBS
(MatrixPr Offset: 0x4) Priority Register B for Slave 0
Definition: component_matrix.h:43
MatrixPr::MATRIX_PRAS
__IO uint32_t MATRIX_PRAS
(MatrixPr Offset: 0x0) Priority Register A for Slave 0
Definition: component_matrix.h:42
Matrix
Matrix hardware registers.
Definition: component_matrix.h:47
Matrix::CCFG_CAN0
__IO uint32_t CCFG_CAN0
(Matrix Offset: 0x0110) CAN0 Configuration Register
Definition: component_matrix.h:67
Matrix::MATRIX_MCFG5
__IO uint32_t MATRIX_MCFG5
(Matrix Offset: 0x0014) Master Configuration Register 5
Definition: component_matrix.h:53
Matrix::CCFG_SYSIO
__IO uint32_t CCFG_SYSIO
(Matrix Offset: 0x0114) System I/O and CAN1 Configuration Register
Definition: component_matrix.h:68
Matrix::MATRIX_MCFG9
__IO uint32_t MATRIX_MCFG9
(Matrix Offset: 0x0024) Master Configuration Register 9
Definition: component_matrix.h:57
Matrix::MATRIX_MCFG1
__IO uint32_t MATRIX_MCFG1
(Matrix Offset: 0x0004) Master Configuration Register 1
Definition: component_matrix.h:49
Matrix::MATRIX_MCFG3
__IO uint32_t MATRIX_MCFG3
(Matrix Offset: 0x000C) Master Configuration Register 3
Definition: component_matrix.h:51
Matrix::MATRIX_MCFG2
__IO uint32_t MATRIX_MCFG2
(Matrix Offset: 0x0008) Master Configuration Register 2
Definition: component_matrix.h:50
Matrix::MATRIX_MCFG8
__IO uint32_t MATRIX_MCFG8
(Matrix Offset: 0x0020) Master Configuration Register 8
Definition: component_matrix.h:56
Matrix::MATRIX_MRCR
__IO uint32_t MATRIX_MRCR
(Matrix Offset: 0x0100) Master Remap Control Register
Definition: component_matrix.h:65
Matrix::MATRIX_WPMR
__IO uint32_t MATRIX_WPMR
(Matrix Offset: 0x01E4) Write Protection Mode Register
Definition: component_matrix.h:72
Matrix::MATRIX_WPSR
__I uint32_t MATRIX_WPSR
(Matrix Offset: 0x01E8) Write Protection Status Register
Definition: component_matrix.h:73
Matrix::CCFG_SMCNFCS
__IO uint32_t CCFG_SMCNFCS
(Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register
Definition: component_matrix.h:70
Matrix::MATRIX_MCFG10
__IO uint32_t MATRIX_MCFG10
(Matrix Offset: 0x0028) Master Configuration Register 10
Definition: component_matrix.h:58
Matrix::MATRIX_MCFG0
__IO uint32_t MATRIX_MCFG0
(Matrix Offset: 0x0000) Master Configuration Register 0
Definition: component_matrix.h:48
Matrix::MATRIX_MCFG11
__IO uint32_t MATRIX_MCFG11
(Matrix Offset: 0x002C) Master Configuration Register 11
Definition: component_matrix.h:59
Matrix::MATRIX_MCFG6
__IO uint32_t MATRIX_MCFG6
(Matrix Offset: 0x0018) Master Configuration Register 6
Definition: component_matrix.h:54
Matrix::MATRIX_MCFG4
__IO uint32_t MATRIX_MCFG4
(Matrix Offset: 0x0010) Master Configuration Register 4
Definition: component_matrix.h:52