RTEMS: bsps/arm/atsam/include/libchip/include/same70/component/component_afec.h Source File

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component_afec.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAME70_AFEC_COMPONENT_
31#define _SAME70_AFEC_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41 typedef struct {
42 __O uint32_t AFEC_CR;
43 __IO uint32_t AFEC_MR;
44 __IO uint32_t AFEC_EMR;
45 __IO uint32_t AFEC_SEQ1R;
46 __IO uint32_t AFEC_SEQ2R;
47 __O uint32_t AFEC_CHER;
48 __O uint32_t AFEC_CHDR;
49 __I uint32_t AFEC_CHSR;
50 __I uint32_t AFEC_LCDR;
51 __O uint32_t AFEC_IER;
52 __O uint32_t AFEC_IDR;
53 __I uint32_t AFEC_IMR;
54 __I uint32_t AFEC_ISR;
55 __I uint32_t Reserved1[6];
56 __I uint32_t AFEC_OVER;
57 __IO uint32_t AFEC_CWR;
58 __IO uint32_t AFEC_CGR;
59 __I uint32_t Reserved2[2];
60 __IO uint32_t AFEC_DIFFR;
61 __IO uint32_t AFEC_CSELR;
62 __I uint32_t AFEC_CDR;
63 __IO uint32_t AFEC_COCR;
64 __IO uint32_t AFEC_TEMPMR;
65 __IO uint32_t AFEC_TEMPCWR;
66 __I uint32_t Reserved3[7];
67 __IO uint32_t AFEC_ACR;
68 __I uint32_t Reserved4[2];
69 __IO uint32_t AFEC_SHMR;
70 __I uint32_t Reserved5[11];
71 __IO uint32_t AFEC_COSR;
72 __IO uint32_t AFEC_CVR;
73 __IO uint32_t AFEC_CECR;
74 __I uint32_t Reserved6[2];
75 __IO uint32_t AFEC_WPMR;
76 __I uint32_t AFEC_WPSR;
77} Afec;
78#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
79/* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */
80#define AFEC_CR_SWRST (0x1u << 0)
81#define AFEC_CR_START (0x1u << 1)
82/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */
83#define AFEC_MR_TRGEN (0x1u << 0)
84#define AFEC_MR_TRGEN_DIS (0x0u << 0)
85#define AFEC_MR_TRGEN_EN (0x1u << 0)
86#define AFEC_MR_TRGSEL_Pos 1
87#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos)
88#define AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos)))
89#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1)
90#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1)
91#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1)
92#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1)
93#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1)
94#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1)
95#define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1)
96#define AFEC_MR_SLEEP (0x1u << 5)
97#define AFEC_MR_SLEEP_NORMAL (0x0u << 5)
98#define AFEC_MR_SLEEP_SLEEP (0x1u << 5)
99#define AFEC_MR_FWUP (0x1u << 6)
100#define AFEC_MR_FWUP_OFF (0x0u << 6)
101#define AFEC_MR_FWUP_ON (0x1u << 6)
102#define AFEC_MR_FREERUN (0x1u << 7)
103#define AFEC_MR_FREERUN_OFF (0x0u << 7)
104#define AFEC_MR_FREERUN_ON (0x1u << 7)
105#define AFEC_MR_PRESCAL_Pos 8
106#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos)
107#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos)))
108#define AFEC_MR_STARTUP_Pos 16
109#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos)
110#define AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos)))
111#define AFEC_MR_STARTUP_SUT0 (0x0u << 16)
112#define AFEC_MR_STARTUP_SUT8 (0x1u << 16)
113#define AFEC_MR_STARTUP_SUT16 (0x2u << 16)
114#define AFEC_MR_STARTUP_SUT24 (0x3u << 16)
115#define AFEC_MR_STARTUP_SUT64 (0x4u << 16)
116#define AFEC_MR_STARTUP_SUT80 (0x5u << 16)
117#define AFEC_MR_STARTUP_SUT96 (0x6u << 16)
118#define AFEC_MR_STARTUP_SUT112 (0x7u << 16)
119#define AFEC_MR_STARTUP_SUT512 (0x8u << 16)
120#define AFEC_MR_STARTUP_SUT576 (0x9u << 16)
121#define AFEC_MR_STARTUP_SUT640 (0xAu << 16)
122#define AFEC_MR_STARTUP_SUT704 (0xBu << 16)
123#define AFEC_MR_STARTUP_SUT768 (0xCu << 16)
124#define AFEC_MR_STARTUP_SUT832 (0xDu << 16)
125#define AFEC_MR_STARTUP_SUT896 (0xEu << 16)
126#define AFEC_MR_STARTUP_SUT960 (0xFu << 16)
127#define AFEC_MR_ONE (0x1u << 23)
128#define AFEC_MR_TRACKTIM_Pos 24
129#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos)
130#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos)))
131#define AFEC_MR_TRANSFER_Pos 28
132#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos)
133#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos)))
134#define AFEC_MR_USEQ (0x1u << 31)
135#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31)
136#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31)
137/* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */
138#define AFEC_EMR_CMPMODE_Pos 0
139#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos)
140#define AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos)))
141#define AFEC_EMR_CMPMODE_LOW (0x0u << 0)
142#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0)
143#define AFEC_EMR_CMPMODE_IN (0x2u << 0)
144#define AFEC_EMR_CMPMODE_OUT (0x3u << 0)
145#define AFEC_EMR_CMPSEL_Pos 3
146#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos)
147#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos)))
148#define AFEC_EMR_CMPALL (0x1u << 9)
149#define AFEC_EMR_CMPFILTER_Pos 12
150#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos)
151#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos)))
152#define AFEC_EMR_RES_Pos 16
153#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos)
154#define AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos)))
155#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16)
156#define AFEC_EMR_RES_OSR4 (0x2u << 16)
157#define AFEC_EMR_RES_OSR16 (0x3u << 16)
158#define AFEC_EMR_RES_OSR64 (0x4u << 16)
159#define AFEC_EMR_RES_OSR256 (0x5u << 16)
160#define AFEC_EMR_TAG (0x1u << 24)
161#define AFEC_EMR_STM (0x1u << 25)
162#define AFEC_EMR_SIGNMODE_Pos 28
163#define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos)
164#define AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos)))
165#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28)
166#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28)
167#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28)
168#define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28)
169/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */
170#define AFEC_SEQ1R_USCH0_Pos 0
171#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos)
172#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos)))
173#define AFEC_SEQ1R_USCH1_Pos 4
174#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos)
175#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos)))
176#define AFEC_SEQ1R_USCH2_Pos 8
177#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos)
178#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos)))
179#define AFEC_SEQ1R_USCH3_Pos 12
180#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos)
181#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos)))
182#define AFEC_SEQ1R_USCH4_Pos 16
183#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos)
184#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos)))
185#define AFEC_SEQ1R_USCH5_Pos 20
186#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos)
187#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos)))
188#define AFEC_SEQ1R_USCH6_Pos 24
189#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos)
190#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos)))
191#define AFEC_SEQ1R_USCH7_Pos 28
192#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos)
193#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos)))
194/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */
195#define AFEC_SEQ2R_USCH8_Pos 0
196#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos)
197#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos)))
198#define AFEC_SEQ2R_USCH9_Pos 4
199#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos)
200#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos)))
201#define AFEC_SEQ2R_USCH10_Pos 8
202#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos)
203#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos)))
204#define AFEC_SEQ2R_USCH11_Pos 12
205#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos)
206#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos)))
207#define AFEC_SEQ2R_USCH12_Pos 16
208#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos)
209#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos)))
210#define AFEC_SEQ2R_USCH13_Pos 20
211#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos)
212#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos)))
213#define AFEC_SEQ2R_USCH14_Pos 24
214#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos)
215#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos)))
216#define AFEC_SEQ2R_USCH15_Pos 28
217#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos)
218#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos)))
219/* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */
220#define AFEC_CHER_CH0 (0x1u << 0)
221#define AFEC_CHER_CH1 (0x1u << 1)
222#define AFEC_CHER_CH2 (0x1u << 2)
223#define AFEC_CHER_CH3 (0x1u << 3)
224#define AFEC_CHER_CH4 (0x1u << 4)
225#define AFEC_CHER_CH5 (0x1u << 5)
226#define AFEC_CHER_CH6 (0x1u << 6)
227#define AFEC_CHER_CH7 (0x1u << 7)
228#define AFEC_CHER_CH8 (0x1u << 8)
229#define AFEC_CHER_CH9 (0x1u << 9)
230#define AFEC_CHER_CH10 (0x1u << 10)
231#define AFEC_CHER_CH11 (0x1u << 11)
232/* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */
233#define AFEC_CHDR_CH0 (0x1u << 0)
234#define AFEC_CHDR_CH1 (0x1u << 1)
235#define AFEC_CHDR_CH2 (0x1u << 2)
236#define AFEC_CHDR_CH3 (0x1u << 3)
237#define AFEC_CHDR_CH4 (0x1u << 4)
238#define AFEC_CHDR_CH5 (0x1u << 5)
239#define AFEC_CHDR_CH6 (0x1u << 6)
240#define AFEC_CHDR_CH7 (0x1u << 7)
241#define AFEC_CHDR_CH8 (0x1u << 8)
242#define AFEC_CHDR_CH9 (0x1u << 9)
243#define AFEC_CHDR_CH10 (0x1u << 10)
244#define AFEC_CHDR_CH11 (0x1u << 11)
245/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */
246#define AFEC_CHSR_CH0 (0x1u << 0)
247#define AFEC_CHSR_CH1 (0x1u << 1)
248#define AFEC_CHSR_CH2 (0x1u << 2)
249#define AFEC_CHSR_CH3 (0x1u << 3)
250#define AFEC_CHSR_CH4 (0x1u << 4)
251#define AFEC_CHSR_CH5 (0x1u << 5)
252#define AFEC_CHSR_CH6 (0x1u << 6)
253#define AFEC_CHSR_CH7 (0x1u << 7)
254#define AFEC_CHSR_CH8 (0x1u << 8)
255#define AFEC_CHSR_CH9 (0x1u << 9)
256#define AFEC_CHSR_CH10 (0x1u << 10)
257#define AFEC_CHSR_CH11 (0x1u << 11)
258/* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */
259#define AFEC_LCDR_LDATA_Pos 0
260#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos)
261#define AFEC_LCDR_CHNB_Pos 24
262#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos)
263/* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */
264#define AFEC_IER_EOC0 (0x1u << 0)
265#define AFEC_IER_EOC1 (0x1u << 1)
266#define AFEC_IER_EOC2 (0x1u << 2)
267#define AFEC_IER_EOC3 (0x1u << 3)
268#define AFEC_IER_EOC4 (0x1u << 4)
269#define AFEC_IER_EOC5 (0x1u << 5)
270#define AFEC_IER_EOC6 (0x1u << 6)
271#define AFEC_IER_EOC7 (0x1u << 7)
272#define AFEC_IER_EOC8 (0x1u << 8)
273#define AFEC_IER_EOC9 (0x1u << 9)
274#define AFEC_IER_EOC10 (0x1u << 10)
275#define AFEC_IER_EOC11 (0x1u << 11)
276#define AFEC_IER_DRDY (0x1u << 24)
277#define AFEC_IER_GOVRE (0x1u << 25)
278#define AFEC_IER_COMPE (0x1u << 26)
279#define AFEC_IER_TEMPCHG (0x1u << 30)
280/* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */
281#define AFEC_IDR_EOC0 (0x1u << 0)
282#define AFEC_IDR_EOC1 (0x1u << 1)
283#define AFEC_IDR_EOC2 (0x1u << 2)
284#define AFEC_IDR_EOC3 (0x1u << 3)
285#define AFEC_IDR_EOC4 (0x1u << 4)
286#define AFEC_IDR_EOC5 (0x1u << 5)
287#define AFEC_IDR_EOC6 (0x1u << 6)
288#define AFEC_IDR_EOC7 (0x1u << 7)
289#define AFEC_IDR_EOC8 (0x1u << 8)
290#define AFEC_IDR_EOC9 (0x1u << 9)
291#define AFEC_IDR_EOC10 (0x1u << 10)
292#define AFEC_IDR_EOC11 (0x1u << 11)
293#define AFEC_IDR_DRDY (0x1u << 24)
294#define AFEC_IDR_GOVRE (0x1u << 25)
295#define AFEC_IDR_COMPE (0x1u << 26)
296#define AFEC_IDR_TEMPCHG (0x1u << 30)
297/* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */
298#define AFEC_IMR_EOC0 (0x1u << 0)
299#define AFEC_IMR_EOC1 (0x1u << 1)
300#define AFEC_IMR_EOC2 (0x1u << 2)
301#define AFEC_IMR_EOC3 (0x1u << 3)
302#define AFEC_IMR_EOC4 (0x1u << 4)
303#define AFEC_IMR_EOC5 (0x1u << 5)
304#define AFEC_IMR_EOC6 (0x1u << 6)
305#define AFEC_IMR_EOC7 (0x1u << 7)
306#define AFEC_IMR_EOC8 (0x1u << 8)
307#define AFEC_IMR_EOC9 (0x1u << 9)
308#define AFEC_IMR_EOC10 (0x1u << 10)
309#define AFEC_IMR_EOC11 (0x1u << 11)
310#define AFEC_IMR_DRDY (0x1u << 24)
311#define AFEC_IMR_GOVRE (0x1u << 25)
312#define AFEC_IMR_COMPE (0x1u << 26)
313#define AFEC_IMR_TEMPCHG (0x1u << 30)
314/* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */
315#define AFEC_ISR_EOC0 (0x1u << 0)
316#define AFEC_ISR_EOC1 (0x1u << 1)
317#define AFEC_ISR_EOC2 (0x1u << 2)
318#define AFEC_ISR_EOC3 (0x1u << 3)
319#define AFEC_ISR_EOC4 (0x1u << 4)
320#define AFEC_ISR_EOC5 (0x1u << 5)
321#define AFEC_ISR_EOC6 (0x1u << 6)
322#define AFEC_ISR_EOC7 (0x1u << 7)
323#define AFEC_ISR_EOC8 (0x1u << 8)
324#define AFEC_ISR_EOC9 (0x1u << 9)
325#define AFEC_ISR_EOC10 (0x1u << 10)
326#define AFEC_ISR_EOC11 (0x1u << 11)
327#define AFEC_ISR_DRDY (0x1u << 24)
328#define AFEC_ISR_GOVRE (0x1u << 25)
329#define AFEC_ISR_COMPE (0x1u << 26)
330#define AFEC_ISR_TEMPCHG (0x1u << 30)
331/* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */
332#define AFEC_OVER_OVRE0 (0x1u << 0)
333#define AFEC_OVER_OVRE1 (0x1u << 1)
334#define AFEC_OVER_OVRE2 (0x1u << 2)
335#define AFEC_OVER_OVRE3 (0x1u << 3)
336#define AFEC_OVER_OVRE4 (0x1u << 4)
337#define AFEC_OVER_OVRE5 (0x1u << 5)
338#define AFEC_OVER_OVRE6 (0x1u << 6)
339#define AFEC_OVER_OVRE7 (0x1u << 7)
340#define AFEC_OVER_OVRE8 (0x1u << 8)
341#define AFEC_OVER_OVRE9 (0x1u << 9)
342#define AFEC_OVER_OVRE10 (0x1u << 10)
343#define AFEC_OVER_OVRE11 (0x1u << 11)
344/* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */
345#define AFEC_CWR_LOWTHRES_Pos 0
346#define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos)
347#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos)))
348#define AFEC_CWR_HIGHTHRES_Pos 16
349#define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos)
350#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos)))
351/* -------- AFEC_CGR : (AFEC Offset: 0x54) AFEC Channel Gain Register -------- */
352#define AFEC_CGR_GAIN0_Pos 0
353#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos)
354#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos)))
355#define AFEC_CGR_GAIN1_Pos 2
356#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos)
357#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos)))
358#define AFEC_CGR_GAIN2_Pos 4
359#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos)
360#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos)))
361#define AFEC_CGR_GAIN3_Pos 6
362#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos)
363#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos)))
364#define AFEC_CGR_GAIN4_Pos 8
365#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos)
366#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos)))
367#define AFEC_CGR_GAIN5_Pos 10
368#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos)
369#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos)))
370#define AFEC_CGR_GAIN6_Pos 12
371#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos)
372#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos)))
373#define AFEC_CGR_GAIN7_Pos 14
374#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos)
375#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos)))
376#define AFEC_CGR_GAIN8_Pos 16
377#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos)
378#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos)))
379#define AFEC_CGR_GAIN9_Pos 18
380#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos)
381#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos)))
382#define AFEC_CGR_GAIN10_Pos 20
383#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos)
384#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos)))
385#define AFEC_CGR_GAIN11_Pos 22
386#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos)
387#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos)))
388/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */
389#define AFEC_DIFFR_DIFF0 (0x1u << 0)
390#define AFEC_DIFFR_DIFF1 (0x1u << 1)
391#define AFEC_DIFFR_DIFF2 (0x1u << 2)
392#define AFEC_DIFFR_DIFF3 (0x1u << 3)
393#define AFEC_DIFFR_DIFF4 (0x1u << 4)
394#define AFEC_DIFFR_DIFF5 (0x1u << 5)
395#define AFEC_DIFFR_DIFF6 (0x1u << 6)
396#define AFEC_DIFFR_DIFF7 (0x1u << 7)
397#define AFEC_DIFFR_DIFF8 (0x1u << 8)
398#define AFEC_DIFFR_DIFF9 (0x1u << 9)
399#define AFEC_DIFFR_DIFF10 (0x1u << 10)
400#define AFEC_DIFFR_DIFF11 (0x1u << 11)
401/* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Selection Register -------- */
402#define AFEC_CSELR_CSEL_Pos 0
403#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos)
404#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos)))
405/* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */
406#define AFEC_CDR_DATA_Pos 0
407#define AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos)
408/* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */
409#define AFEC_COCR_AOFF_Pos 0
410#define AFEC_COCR_AOFF_Msk (0x3ffu << AFEC_COCR_AOFF_Pos)
411#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos)))
412/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */
413#define AFEC_TEMPMR_RTCT (0x1u << 0)
414#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4
415#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos)
416#define AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos)))
417#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4)
418#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4)
419#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4)
420#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4)
421/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */
422#define AFEC_TEMPCWR_TLOWTHRES_Pos 0
423#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos)
424#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos)))
425#define AFEC_TEMPCWR_THIGHTHRES_Pos 16
426#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos)
427#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos)))
428/* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */
429#define AFEC_ACR_PGA0EN (0x1u << 2)
430#define AFEC_ACR_PGA1EN (0x1u << 3)
431#define AFEC_ACR_IBCTL_Pos 8
432#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos)
433#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos)))
434/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */
435#define AFEC_SHMR_DUAL0 (0x1u << 0)
436#define AFEC_SHMR_DUAL1 (0x1u << 1)
437#define AFEC_SHMR_DUAL2 (0x1u << 2)
438#define AFEC_SHMR_DUAL3 (0x1u << 3)
439#define AFEC_SHMR_DUAL4 (0x1u << 4)
440#define AFEC_SHMR_DUAL5 (0x1u << 5)
441#define AFEC_SHMR_DUAL6 (0x1u << 6)
442#define AFEC_SHMR_DUAL7 (0x1u << 7)
443#define AFEC_SHMR_DUAL8 (0x1u << 8)
444#define AFEC_SHMR_DUAL9 (0x1u << 9)
445#define AFEC_SHMR_DUAL10 (0x1u << 10)
446#define AFEC_SHMR_DUAL11 (0x1u << 11)
447/* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */
448#define AFEC_COSR_CSEL (0x1u << 0)
449/* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */
450#define AFEC_CVR_OFFSETCORR_Pos 0
451#define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos)
452#define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos)))
453#define AFEC_CVR_GAINCORR_Pos 16
454#define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos)
455#define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos)))
456/* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */
457#define AFEC_CECR_ECORR0 (0x1u << 0)
458#define AFEC_CECR_ECORR1 (0x1u << 1)
459#define AFEC_CECR_ECORR2 (0x1u << 2)
460#define AFEC_CECR_ECORR3 (0x1u << 3)
461#define AFEC_CECR_ECORR4 (0x1u << 4)
462#define AFEC_CECR_ECORR5 (0x1u << 5)
463#define AFEC_CECR_ECORR6 (0x1u << 6)
464#define AFEC_CECR_ECORR7 (0x1u << 7)
465#define AFEC_CECR_ECORR8 (0x1u << 8)
466#define AFEC_CECR_ECORR9 (0x1u << 9)
467#define AFEC_CECR_ECORR10 (0x1u << 10)
468#define AFEC_CECR_ECORR11 (0x1u << 11)
469/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */
470#define AFEC_WPMR_WPEN (0x1u << 0)
471#define AFEC_WPMR_WPKEY_Pos 8
472#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos)
473#define AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos)))
474#define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8)
475/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */
476#define AFEC_WPSR_WPVS (0x1u << 0)
477#define AFEC_WPSR_WPVSRC_Pos 8
478#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos)
481
482
483#endif /* _SAME70_AFEC_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Afec
Afec hardware registers.
Definition: component_afec.h:41
Afec::AFEC_CHSR
__I uint32_t AFEC_CHSR
(Afec Offset: 0x1C) AFEC Channel Status Register
Definition: component_afec.h:49
Afec::AFEC_LCDR
__I uint32_t AFEC_LCDR
(Afec Offset: 0x20) AFEC Last Converted Data Register
Definition: component_afec.h:50
Afec::AFEC_IDR
__O uint32_t AFEC_IDR
(Afec Offset: 0x28) AFEC Interrupt Disable Register
Definition: component_afec.h:52
Afec::AFEC_IER
__O uint32_t AFEC_IER
(Afec Offset: 0x24) AFEC Interrupt Enable Register
Definition: component_afec.h:51
Afec::AFEC_CECR
__IO uint32_t AFEC_CECR
(Afec Offset: 0xD8) AFEC Channel Error Correction Register
Definition: component_afec.h:73
Afec::AFEC_COCR
__IO uint32_t AFEC_COCR
(Afec Offset: 0x6C) AFEC Channel Offset Compensation Register
Definition: component_afec.h:63
Afec::AFEC_CDR
__I uint32_t AFEC_CDR
(Afec Offset: 0x68) AFEC Channel Data Register
Definition: component_afec.h:62
Afec::AFEC_EMR
__IO uint32_t AFEC_EMR
(Afec Offset: 0x08) AFEC Extended Mode Register
Definition: component_afec.h:44
Afec::AFEC_CSELR
__IO uint32_t AFEC_CSELR
(Afec Offset: 0x64) AFEC Channel Selection Register
Definition: component_afec.h:61
Afec::AFEC_ACR
__IO uint32_t AFEC_ACR
(Afec Offset: 0x94) AFEC Analog Control Register
Definition: component_afec.h:67
Afec::AFEC_SEQ2R
__IO uint32_t AFEC_SEQ2R
(Afec Offset: 0x10) AFEC Channel Sequence 2 Register
Definition: component_afec.h:46
Afec::AFEC_COSR
__IO uint32_t AFEC_COSR
(Afec Offset: 0xD0) AFEC Correction Select Register
Definition: component_afec.h:71
Afec::AFEC_TEMPCWR
__IO uint32_t AFEC_TEMPCWR
(Afec Offset: 0x74) AFEC Temperature Compare Window Register
Definition: component_afec.h:65
Afec::AFEC_CWR
__IO uint32_t AFEC_CWR
(Afec Offset: 0x50) AFEC Compare Window Register
Definition: component_afec.h:57
Afec::AFEC_TEMPMR
__IO uint32_t AFEC_TEMPMR
(Afec Offset: 0x70) AFEC Temperature Sensor Mode Register
Definition: component_afec.h:64
Afec::AFEC_WPMR
__IO uint32_t AFEC_WPMR
(Afec Offset: 0xE4) AFEC Write Protection Mode Register
Definition: component_afec.h:75
Afec::AFEC_CHDR
__O uint32_t AFEC_CHDR
(Afec Offset: 0x18) AFEC Channel Disable Register
Definition: component_afec.h:48
Afec::AFEC_DIFFR
__IO uint32_t AFEC_DIFFR
(Afec Offset: 0x60) AFEC Channel Differential Register
Definition: component_afec.h:60
Afec::AFEC_OVER
__I uint32_t AFEC_OVER
(Afec Offset: 0x4C) AFEC Overrun Status Register
Definition: component_afec.h:56
Afec::AFEC_CHER
__O uint32_t AFEC_CHER
(Afec Offset: 0x14) AFEC Channel Enable Register
Definition: component_afec.h:47
Afec::AFEC_IMR
__I uint32_t AFEC_IMR
(Afec Offset: 0x2C) AFEC Interrupt Mask Register
Definition: component_afec.h:53
Afec::AFEC_CR
__O uint32_t AFEC_CR
(Afec Offset: 0x00) AFEC Control Register
Definition: component_afec.h:42
Afec::AFEC_SHMR
__IO uint32_t AFEC_SHMR
(Afec Offset: 0xA0) AFEC Sample & Hold Mode Register
Definition: component_afec.h:69
Afec::AFEC_MR
__IO uint32_t AFEC_MR
(Afec Offset: 0x04) AFEC Mode Register
Definition: component_afec.h:43
Afec::AFEC_WPSR
__I uint32_t AFEC_WPSR
(Afec Offset: 0xE8) AFEC Write Protection Status Register
Definition: component_afec.h:76
Afec::AFEC_CVR
__IO uint32_t AFEC_CVR
(Afec Offset: 0xD4) AFEC Correction Values Register
Definition: component_afec.h:72
Afec::AFEC_SEQ1R
__IO uint32_t AFEC_SEQ1R
(Afec Offset: 0x0C) AFEC Channel Sequence 1 Register
Definition: component_afec.h:45
Afec::AFEC_ISR
__I uint32_t AFEC_ISR
(Afec Offset: 0x30) AFEC Interrupt Status Register
Definition: component_afec.h:54
Afec::AFEC_CGR
__IO uint32_t AFEC_CGR
(Afec Offset: 0x54) AFEC Channel Gain Register
Definition: component_afec.h:58