RTEMS: cpukit/score/cpu/mips/include/rtems/score/mips.h Source File

| RTEMS 5.4-rc2

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mips.h
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1
14/*
15 * COPYRIGHT (c) 1989-2001.
16 * On-Line Applications Research Corporation (OAR).
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef _RTEMS_SCORE_MIPS_H
24#define _RTEMS_SCORE_MIPS_H
25
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#ifndef ASM
39#include <rtems/mips/idtcpu.h>
40#endif
41
42/*
43 * SR bits that enable/disable interrupts
44 *
45 * NOTE: XXX what about SR_ERL?
46 */
47
48#if (__mips == 3) || (__mips == 32)
49#ifdef ASM
50#define SR_INTERRUPT_ENABLE_BITS 0x01
51#else
52#define SR_INTERRUPT_ENABLE_BITS SR_IE
53#endif
54
55#elif __mips == 1
56#define SR_INTERRUPT_ENABLE_BITS SR_IEC
57
58#else
59#error "mips interrupt enable bits: unknown architecture level!"
60#endif
61
62/*
63 * This file contains the information required to build
64 * RTEMS for a particular member of the "no cpu"
65 * family when executing in protected mode. It does
66 * this by setting variables to indicate which implementation
67 * dependent features are present in a particular member
68 * of the family.
69 */
70
71#if defined(__mips_soft_float)
72#define MIPS_HAS_FPU 0
73#else
74#define MIPS_HAS_FPU 1
75#endif
76
77
78#if (__mips == 1)
79#define CPU_MODEL_NAME "ISA Level 1 or 2"
80#elif (__mips == 3) || (__mips == 32)
81#if defined(__mips64)
82#define CPU_MODEL_NAME "ISA Level 4"
83#else
84#define CPU_MODEL_NAME "ISA Level 3"
85#endif
86#else
87#error "Unknown MIPS ISA level"
88#endif
89
90/*
91 * Define the name of the CPU family.
92 */
93
94#define CPU_NAME "MIPS"
95
96/*
97 * RTEMS Vector numbers for exception conditions. This is a direct
98 * map to the causes.
99 */
100
101#define MIPS_EXCEPTION_BASE 0
102
103#define MIPS_EXCEPTION_INT MIPS_EXCEPTION_BASE+0
104#define MIPS_EXCEPTION_MOD MIPS_EXCEPTION_BASE+1
105#define MIPS_EXCEPTION_TLBL MIPS_EXCEPTION_BASE+2
106#define MIPS_EXCEPTION_TLBS MIPS_EXCEPTION_BASE+3
107#define MIPS_EXCEPTION_ADEL MIPS_EXCEPTION_BASE+4
108#define MIPS_EXCEPTION_ADES MIPS_EXCEPTION_BASE+5
109#define MIPS_EXCEPTION_IBE MIPS_EXCEPTION_BASE+6
110#define MIPS_EXCEPTION_DBE MIPS_EXCEPTION_BASE+7
111#define MIPS_EXCEPTION_SYSCALL MIPS_EXCEPTION_BASE+8
112#define MIPS_EXCEPTION_BREAK MIPS_EXCEPTION_BASE+9
113#define MIPS_EXCEPTION_RI MIPS_EXCEPTION_BASE+10
114#define MIPS_EXCEPTION_CPU MIPS_EXCEPTION_BASE+11
115#define MIPS_EXCEPTION_OVERFLOW MIPS_EXCEPTION_BASE+12
116#define MIPS_EXCEPTION_TRAP MIPS_EXCEPTION_BASE+13
117#define MIPS_EXCEPTION_VCEI MIPS_EXCEPTION_BASE+14
118/* FPE only on mips2 and higher */
119#define MIPS_EXCEPTION_FPE MIPS_EXCEPTION_BASE+15
120#define MIPS_EXCEPTION_C2E MIPS_EXCEPTION_BASE+16
121/* 17-22 reserved */
122#define MIPS_EXCEPTION_WATCH MIPS_EXCEPTION_BASE+23
123/* 24-30 reserved */
124#define MIPS_EXCEPTION_VCED MIPS_EXCEPTION_BASE+31
125
126#define MIPS_INTERRUPT_BASE MIPS_EXCEPTION_BASE+32
127
128/*
129 * Some macros to access registers
130 */
131
132#define mips_get_sr( _x ) \
133 do { \
134 __asm__ volatile( "mfc0 %0, $12; nop" : "=r" (_x) : ); \
135 } while (0)
136
137#define mips_set_sr( _x ) \
138 do { \
139 unsigned int __x = (_x); \
140 __asm__ volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \
141 } while (0)
142
143
144/*
145 * Access the Cause register
146 */
147
148#define mips_get_cause( _x ) \
149 do { \
150 __asm__ volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \
151 } while (0)
152
153
154#define mips_set_cause( _x ) \
155 do { \
156 unsigned int __x = (_x); \
157 __asm__ volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \
158 } while (0)
159
160
161
162
163/*
164 * Access the Debug Cache Invalidate Control register
165 */
166
167#define mips_get_dcic( _x ) \
168 do { \
169 __asm__ volatile( "mfc0 %0, $7; nop" : "=r" (_x) : ); \
170 } while (0)
171
172
173#define mips_set_dcic( _x ) \
174 do { \
175 unsigned int __x = (_x); \
176 __asm__ volatile( "mtc0 %0, $7; nop" : : "r" (__x) ); \
177 } while (0)
178
179
180
181
182/*
183 * Access the Breakpoint Program Counter & Mask registers
184 * (_x for BPC, _y for mask)
185 */
186
187#define mips_get_bpcrm( _x, _y ) \
188 do { \
189 __asm__ volatile( "mfc0 %0, $3; nop" : "=r" (_x) : ); \
190 __asm__ volatile( "mfc0 %0, $11; nop" : "=r" (_y) : ); \
191 } while (0)
192
193
194#define mips_set_bpcrm( _x, _y ) \
195 do { \
196 unsigned int __x = (_x); \
197 unsigned int __y = (_y); \
198 __asm__ volatile( "mtc0 %0, $11; nop" : : "r" (__y) ); \
199 __asm__ volatile( "mtc0 %0, $3; nop" : : "r" (__x) ); \
200 } while (0)
201
202
203
204
205
206
207/*
208 * Access the Breakpoint Data Address & Mask registers
209 * (_x for BDA, _y for mask)
210 */
211
212#define mips_get_bdarm( _x, _y ) \
213 do { \
214 __asm__ volatile( "mfc0 %0, $5; nop" : "=r" (_x) : ); \
215 __asm__ volatile( "mfc0 %0, $9; nop" : "=r" (_y) : ); \
216 } while (0)
217
218
219#define mips_set_bdarm( _x, _y ) \
220 do { \
221 unsigned int __x = (_x); \
222 unsigned int __y = (_y); \
223 __asm__ volatile( "mtc0 %0, $9; nop" : : "r" (__y) ); \
224 __asm__ volatile( "mtc0 %0, $5; nop" : : "r" (__x) ); \
225 } while (0)
226
227
228
229
230
231
232
233/*
234 * Access FCR31
235 */
236
237#if ( MIPS_HAS_FPU == 1 )
238
239#define mips_get_fcr31( _x ) \
240 do { \
241 __asm__ volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \
242 } while(0)
243
244
245#define mips_set_fcr31( _x ) \
246 do { \
247 unsigned int __x = (_x); \
248 __asm__ volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \
249 } while(0)
250
251#else
252
253#define mips_get_fcr31( _x )
254#define mips_set_fcr31( _x )
255
256#endif
257
258/*
259 * Manipulate interrupt mask
260 *
261 * mips_unmask_interrupt( _mask)
262 * enables interrupts - mask is positioned so it only needs to be or'ed
263 * into the status reg. This also does some other things !!!! Caution
264 * should be used if invoking this while in the middle of a debugging
265 * session where the client may have nested interrupts.
266 *
267 * mips_mask_interrupt( _mask )
268 * disable the interrupt - mask is the complement of the bits to be
269 * cleared - i.e. to clear ext int 5 the mask would be - 0xffff7fff
270 *
271 *
272 * NOTE: mips_mask_interrupt() used to be disable_int().
273 * mips_unmask_interrupt() used to be enable_int().
274 *
275 */
276
277#define mips_enable_in_interrupt_mask( _mask ) \
278 do { \
279 unsigned int _sr; \
280 mips_get_sr( _sr ); \
281 _sr |= (_mask); \
282 mips_set_sr( _sr ); \
283 } while (0)
284
285#define mips_disable_in_interrupt_mask( _mask ) \
286 do { \
287 unsigned int _sr; \
288 mips_get_sr( _sr ); \
289 _sr &= ~(_mask); \
290 mips_set_sr( _sr ); \
291 } while (0)
292
293#ifdef __cplusplus
294}
295#endif
296
298#endif /* _RTEMS_SCORE_MIPS_H */
299/* end of include file */
idtcpu.h
CPU Related Definitions.