RTEMS: Processor Dependent Interrupt Management

| RTEMS 5.4-rc2

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Macros | Functions
Processor Dependent Interrupt Management
Internal » SuperCore » CPU Architecture Support » Blackfin

## Macros
#define | _CPU_Initialize_vectors()
#define | _CPU_ISR_Disable(_level)
#define | _CPU_ISR_Enable(_level)
#define | _CPU_ISR_Flash(_level)
#define | _CPU_ISR_Set_level(_new_level)

## Functions
RTEMS_INLINE_ROUTINE bool | _CPU_ISR_Is_enabled (uint32_t level)
uint32_t | _CPU_ISR_Get_level (void)

## Detailed Description

The following defines the number of bits actually used in the interrupt field of the task mode. How those bits map to the CPU interrupt levels is defined by the routine _CPU_ISR_Set_level.

Port Specific Information:

XXX document implementation including references if appropriate

Amount of extra stack (above minimum stack size) required by MPCI receive server thread. Remember that in a multiprocessor system this thread must exist and be able to process all directives.

Port Specific Information:

XXX document implementation including references if appropriate

This defines the number of entries in the _ISR_Vector_table managed by RTEMS.

Port Specific Information:

XXX document implementation including references if appropriate

This defines the highest interrupt vector number for this port.

This is defined if the port has a special way to report the ISR nesting level. Most ports maintain the variable _ISR_Nest_level.

## Macro Definition Documentation

## ◆ _CPU_Initialize_vectors

#define _CPU_Initialize_vectors | ( |  | ) |

Support routine to initialize the RTEMS vector table after it is allocated.

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ _CPU_ISR_Disable

#define _CPU_ISR_Disable | ( |  | _level | ) |

Value:
{ \
__asm__ volatile ("cli %0; csync \n" : "=d" (_level) ); \
}

Disable all interrupts for an RTEMS critical section. The previous level is returned in _isr_cookie.

Parameters

  [out] | _isr_cookie | will contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ _CPU_ISR_Enable

#define _CPU_ISR_Enable | ( |  | _level | ) |

Value:
{ \
__asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) ); \
}

Enable interrupts to the previous level (returned by _CPU_ISR_Disable). This indicates the end of an RTEMS critical section. The parameter _isr_cookie is not modified.

Parameters

  [in] | _isr_cookie | contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ _CPU_ISR_Flash

#define _CPU_ISR_Flash | ( |  | _level | ) |

Value:
{ \
__asm__ __volatile__ ("sti %0; csync; cli r0; csync" \
: : "d"(_level) : "R0" ); \
}

This temporarily restores the interrupt to _isr_cookie before immediately disabling them again. This is used to divide long RTEMS critical sections into two or more parts. The parameter _isr_cookie is not modified.

Parameters

  [in] | _isr_cookie | contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ _CPU_ISR_Set_level

#define _CPU_ISR_Set_level | ( |  | _new_level | ) |

Value:
{ \
__asm__ __volatile__ ( "sti %0; csync" : : "d"(_new_level ? 0 : 0xffff) ); \
}

This routine and _CPU_ISR_Get_level Map the interrupt level in task mode onto the hardware that the CPU actually provides. Currently, interrupt levels which do not map onto the CPU in a generic fashion are undefined. Someday, it would be nice if these were "mapped" by the application via a callout. For example, m68k has 8 levels 0 - 7, levels 8 - 255 would be available for bsp/application specific meaning. This could be used to manage a programmable interrupt controller via the rtems_task_mode directive.

Port Specific Information:

XXX document implementation including references if appropriate

## Function Documentation

## ◆ _CPU_ISR_Get_level()

uint32_t _CPU_ISR_Get_level | ( | void |  | ) |

Return the current interrupt disable level for this task in the format used by the interrupt level portion of the task mode.

Note
  This routine usually must be implemented as a subroutine.

Port Specific Information:

XXX document implementation including references if appropriate