RTEMS: cpukit/score/cpu/sh/include/rtems/score/cpu.h Source File

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cpu.h
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1
5/*
6 * This include file contains information pertaining to the Hitachi SH
7 * processor.
8 *
9 * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
10 * Bernd Becker (becker@faw.uni-ulm.de)
11 *
12 * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 *
18 *
19 * COPYRIGHT (c) 1998-2006.
20 * On-Line Applications Research Corporation (OAR).
21 *
22 * The license and distribution terms for this file may be
23 * found in the file LICENSE in this distribution or at
24 * http://www.rtems.org/license/LICENSE.
25 */
26
27#ifndef _RTEMS_SCORE_CPU_H
28#define _RTEMS_SCORE_CPU_H
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
34#include <rtems/score/basedefs.h>
35#include <rtems/score/sh.h>
36
37/* conditional compilation parameters */
38
39/*
40 * Does the CPU follow the simple vectored interrupt model?
41 *
42 * If TRUE, then RTEMS allocates the vector table it internally manages.
43 * If FALSE, then the BSP is assumed to allocate and manage the vector
44 * table
45 *
46 * SH Specific Information:
47 *
48 * XXX document implementation including references if appropriate
49 */
50#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
51
52/*
53 * Does the RTEMS invoke the user's ISR with the vector number and
54 * a pointer to the saved interrupt frame (1) or just the vector
55 * number (0)?
56 */
57
58#define CPU_ISR_PASSES_FRAME_POINTER FALSE
59
60/*
61 * Does the CPU have hardware floating point?
62 *
63 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
64 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
65 *
66 * We currently support sh1 only, which has no FPU, other SHes have an FPU
67 *
68 * The macro name "SH_HAS_FPU" should be made CPU specific.
69 * It indicates whether or not this CPU model has FP support. For
70 * example, it would be possible to have an i386_nofp CPU model
71 * which set this to false to indicate that you have an i386 without
72 * an i387 and wish to leave floating point support out of RTEMS.
73 */
74
75#if SH_HAS_FPU
76#define CPU_HARDWARE_FP TRUE
77#define CPU_SOFTWARE_FP FALSE
78#else
79#define CPU_SOFTWARE_FP FALSE
80#define CPU_HARDWARE_FP FALSE
81#endif
82
83/*
84 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
85 *
86 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
87 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
88 *
89 * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
90 */
91
92#if SH_HAS_FPU
93#define CPU_ALL_TASKS_ARE_FP TRUE
94#else
95#define CPU_ALL_TASKS_ARE_FP FALSE
96#endif
97
98/*
99 * Should the IDLE task have a floating point context?
100 *
101 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
102 * and it has a floating point context which is switched in and out.
103 * If FALSE, then the IDLE task does not have a floating point context.
104 *
105 * Setting this to TRUE negatively impacts the time required to preempt
106 * the IDLE task from an interrupt because the floating point context
107 * must be saved as part of the preemption.
108 */
109
110#if SH_HAS_FPU
111#define CPU_IDLE_TASK_IS_FP TRUE
112#else
113#define CPU_IDLE_TASK_IS_FP FALSE
114#endif
115
116/*
117 * Should the saving of the floating point registers be deferred
118 * until a context switch is made to another different floating point
119 * task?
120 *
121 * If TRUE, then the floating point context will not be stored until
122 * necessary. It will remain in the floating point registers and not
123 * disturned until another floating point task is switched to.
124 *
125 * If FALSE, then the floating point context is saved when a floating
126 * point task is switched out and restored when the next floating point
127 * task is restored. The state of the floating point registers between
128 * those two operations is not specified.
129 *
130 * If the floating point context does NOT have to be saved as part of
131 * interrupt dispatching, then it should be safe to set this to TRUE.
132 *
133 * Setting this flag to TRUE results in using a different algorithm
134 * for deciding when to save and restore the floating point context.
135 * The deferred FP switch algorithm minimizes the number of times
136 * the FP context is saved and restored. The FP context is not saved
137 * until a context switch is made to another, different FP task.
138 * Thus in a system with only one FP task, the FP context will never
139 * be saved or restored.
140 */
141
142#if SH_HAS_FPU
143#define CPU_USE_DEFERRED_FP_SWITCH FALSE
144#else
145#define CPU_USE_DEFERRED_FP_SWITCH TRUE
146#endif
147
148#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
149
150/*
151 * Does the stack grow up (toward higher addresses) or down
152 * (toward lower addresses)?
153 *
154 * If TRUE, then the grows upward.
155 * If FALSE, then the grows toward smaller addresses.
156 */
157
158#define CPU_STACK_GROWS_UP FALSE
159
160/* FIXME: Is this the right value? */
161#define CPU_CACHE_LINE_BYTES 16
162
163#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
164
165/*
166 * The following defines the number of bits actually used in the
167 * interrupt field of the task mode. How those bits map to the
168 * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
169 */
170
171#define CPU_MODES_INTERRUPT_MASK 0x0000000f
172
173#define CPU_MAXIMUM_PROCESSORS 32
174
175/*
176 * Processor defined structures required for cpukit/score.
177 */
178
179/* may need to put some structures here. */
180
181/*
182 * Contexts
183 *
184 * Generally there are 2 types of context to save.
185 * 1. Interrupt registers to save
186 * 2. Task level registers to save
187 *
188 * This means we have the following 3 context items:
189 * 1. task level context stuff:: Context_Control
190 * 2. floating point task stuff:: Context_Control_fp
191 * 3. special interrupt level context :: Context_Control_interrupt
192 *
193 * On some processors, it is cost-effective to save only the callee
194 * preserved registers during a task context switch. This means
195 * that the ISR code needs to save those registers which do not
196 * persist across function calls. It is not mandatory to make this
197 * distinctions between the caller/callee saves registers for the
198 * purpose of minimizing context saved during task switch and on interrupts.
199 * If the cost of saving extra registers is minimal, simplicity is the
200 * choice. Save the same context on interrupt entry as for tasks in
201 * this case.
202 *
203 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
204 * care should be used in designing the context area.
205 *
206 * On some CPUs with hardware floating point support, the Context_Control_fp
207 * structure will not be used or it simply consist of an array of a
208 * fixed number of bytes. This is done when the floating point context
209 * is dumped by a "FP save context" type instruction and the format
210 * is not really defined by the CPU. In this case, there is no need
211 * to figure out the exact format -- only the size. Of course, although
212 * this is enough information for RTEMS, it is probably not enough for
213 * a debugger such as gdb. But that is another problem.
214 */
215
216typedef struct {
217 uint32_t *r15; /* stack pointer */
218
219 uint32_t macl;
220 uint32_t mach;
221 uint32_t *pr;
222
223 uint32_t *r14; /* frame pointer/call saved */
224
225 uint32_t r13; /* call saved */
226 uint32_t r12; /* call saved */
227 uint32_t r11; /* call saved */
228 uint32_t r10; /* call saved */
229 uint32_t r9; /* call saved */
230 uint32_t r8; /* call saved */
231
232 uint32_t *r7; /* arg in */
233 uint32_t *r6; /* arg in */
234
235#if 0
236 uint32_t *r5; /* arg in */
237 uint32_t *r4; /* arg in */
238#endif
239
240 uint32_t *r3; /* scratch */
241 uint32_t *r2; /* scratch */
242 uint32_t *r1; /* scratch */
243
244 uint32_t *r0; /* arg return */
245
246 uint32_t gbr;
247 uint32_t sr;
248
249} Context_Control;
250
251#define _CPU_Context_Get_SP( _context ) \
252 (_context)->r15
253
254typedef struct {
255#if SH_HAS_FPU
256#ifdef SH4_USE_X_REGISTERS
257 union {
258 float f[16];
259 double d[8];
260 } x;
261#endif
262 union {
263 float f[16];
264 double d[8];
265 } r;
266 float fpul; /* fp communication register */
267 uint32_t fpscr; /* fp control register */
268#endif /* SH_HAS_FPU */
269} Context_Control_fp;
270
271typedef struct {
272} CPU_Interrupt_frame;
273
274/*
275 * This variable is optional. It is used on CPUs on which it is difficult
276 * to generate an "uninitialized" FP context. It is filled in by
277 * _CPU_Initialize and copied into the task's FP context area during
278 * _CPU_Context_Initialize.
279 */
280
281#if SH_HAS_FPU
282extern Context_Control_fp _CPU_Null_fp_context;
283#endif
284
285/*
286 * Nothing prevents the porter from declaring more CPU specific variables.
287 */
288
289/* XXX: if needed, put more variables here */
290void CPU_delay( uint32_t microseconds );
291
292/*
293 * The size of the floating point context area. On some CPUs this
294 * will not be a "sizeof" because the format of the floating point
295 * area is not defined -- only the size is. This is usually on
296 * CPUs with a "floating point save context" instruction.
297 */
298
299#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
300
301/*
302 * Amount of extra stack (above minimum stack size) required by
303 * MPCI receive server thread. Remember that in a multiprocessor
304 * system this thread must exist and be able to process all directives.
305 */
306
307#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
308
309/*
310 * This defines the number of entries in the ISR_Vector_table managed
311 * by RTEMS.
312 */
313
314#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
315#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
316
317/*
318 * This is defined if the port has a special way to report the ISR nesting
319 * level. Most ports maintain the variable _ISR_Nest_level.
320 */
321
322#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
323
324/*
325 * Should be large enough to run all RTEMS tests. This ensures
326 * that a "reasonable" small application should not have any problems.
327 *
328 * We have been able to run the sptests with this value, but have not
329 * been able to run the tmtest suite.
330 */
331
332#define CPU_STACK_MINIMUM_SIZE 4096
333
334#define CPU_SIZEOF_POINTER 4
335
336/*
337 * CPU's worst alignment requirement for data types on a byte boundary. This
338 * alignment does not take into account the requirements for the stack.
339 */
340#if defined(__SH4__)
341/* FIXME: sh3 and SH3E? */
342#define CPU_ALIGNMENT 8
343#else
344#define CPU_ALIGNMENT 4
345#endif
346
347/*
348 * This number corresponds to the byte alignment requirement for the
349 * heap handler. This alignment requirement may be stricter than that
350 * for the data types alignment specified by CPU_ALIGNMENT. It is
351 * common for the heap to follow the same alignment requirement as
352 * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
353 * then this should be set to CPU_ALIGNMENT.
354 *
355 * NOTE: This does not have to be a power of 2. It does have to
356 * be greater or equal to than CPU_ALIGNMENT.
357 */
358
359#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
360
361/*
362 * This number corresponds to the byte alignment requirement for the
363 * stack. This alignment requirement may be stricter than that for the
364 * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
365 * is strict enough for the stack, then this should be set to 0.
366 *
367 * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
368 */
369
370#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
371
372#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
373
374/*
375 * ISR handler macros
376 */
377
378/*
379 * Support routine to initialize the RTEMS vector table after it is allocated.
380 *
381 * SH Specific Information: NONE
382 */
383
384#define _CPU_Initialize_vectors()
385
386/*
387 * Disable all interrupts for an RTEMS critical section. The previous
388 * level is returned in _level.
389 */
390
391#define _CPU_ISR_Disable( _level) \
392 sh_disable_interrupts( _level )
393
394/*
395 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
396 * This indicates the end of an RTEMS critical section. The parameter
397 * _level is not modified.
398 */
399
400#define _CPU_ISR_Enable( _level) \
401 sh_enable_interrupts( _level)
402
403/*
404 * This temporarily restores the interrupt to _level before immediately
405 * disabling them again. This is used to divide long RTEMS critical
406 * sections into two or more parts. The parameter _level is not
407 * modified.
408 */
409
410#define _CPU_ISR_Flash( _level) \
411 sh_flash_interrupts( _level)
412
413 RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
414{
415 sh_get_interrupt_level( level );
416 return level == 0;
417}
418
419/*
420 * Map interrupt level in task mode onto the hardware that the CPU
421 * actually provides. Currently, interrupt levels which do not
422 * map onto the CPU in a generic fashion are undefined. Someday,
423 * it would be nice if these were "mapped" by the application
424 * via a callout. For example, m68k has 8 levels 0 - 7, levels
425 * 8 - 255 would be available for bsp/application specific meaning.
426 * This could be used to manage a programmable interrupt controller
427 * via the rtems_task_mode directive.
428 */
429
430#define _CPU_ISR_Set_level( _newlevel) \
431 sh_set_interrupt_level(_newlevel)
432
433uint32_t _CPU_ISR_Get_level( void );
434
435/* end of ISR handler macros */
436
437/* Context handler macros */
438
439/*
440 * Initialize the context to a state suitable for starting a
441 * task after a context restore operation. Generally, this
442 * involves:
443 *
444 * - setting a starting address
445 * - preparing the stack
446 * - preparing the stack and frame pointers
447 * - setting the proper interrupt level in the context
448 * - initializing the floating point context
449 *
450 * This routine generally does not set any unnecessary register
451 * in the context. The state of the "general data" registers is
452 * undefined at task start time.
453 *
454 * NOTE: This is_fp parameter is TRUE if the thread is to be a floating
455 * point thread. This is typically only used on CPUs where the
456 * FPU may be easily disabled by software such as on the SPARC
457 * where the PSR contains an enable FPU bit.
458 */
459
460/*
461 * FIXME: defined as a function for debugging - should be a macro
462 */
463void _CPU_Context_Initialize(
464 Context_Control *_the_context,
465 void *_stack_base,
466 uint32_t _size,
467 uint32_t _isr,
468 void (*_entry_point)(void),
469 int _is_fp,
470 void *_tls_area );
471
472/*
473 * This routine is responsible for somehow restarting the currently
474 * executing task. If you are lucky, then all that is necessary
475 * is restoring the context. Otherwise, there will need to be
476 * a special assembly routine which does something special in this
477 * case. Context_Restore should work most of the time. It will
478 * not work if restarting self conflicts with the stack frame
479 * assumptions of restoring a context.
480 */
481
482#define _CPU_Context_Restart_self( _the_context ) \
483 _CPU_Context_restore( (_the_context) );
484
485/*
486 * This routine initializes the FP context area passed to it to.
487 * There are a few standard ways in which to initialize the
488 * floating point context. The code included for this macro assumes
489 * that this is a CPU in which a "initial" FP context was saved into
490 * _CPU_Null_fp_context and it simply copies it to the destination
491 * context passed to it.
492 *
493 * Other models include (1) not doing anything, and (2) putting
494 * a "null FP status word" in the correct place in the FP context.
495 * SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have.
496 */
497
498#if SH_HAS_FPU
499#define _CPU_Context_Initialize_fp( _destination ) \
500 do { \
501 *(*(_destination)) = _CPU_Null_fp_context;\
502 } while(0)
503#else
504#define _CPU_Context_Initialize_fp( _destination ) \
505 { }
506#endif
507
508/* end of Context handler macros */
509
510/* Fatal Error manager macros */
511
512/*
513 * FIXME: Trap32 ???
514 *
515 * This routine copies _error into a known place -- typically a stack
516 * location or a register, optionally disables interrupts, and
517 * invokes a Trap32 Instruction which returns to the breakpoint
518 * routine of cmon.
519 */
520
521#ifdef BSP_FATAL_HALT
522 /* we manage the fatal error in the board support package */
523 void bsp_fatal_halt( uint32_t _error);
524#define _CPU_Fatal_halt( _source, _error ) bsp_fatal_halt( _error)
525#else
526#define _CPU_Fatal_halt( _source, _error)\
527{ \
528 __asm__ volatile("mov.l %0,r0"::"m" (_error)); \
529 __asm__ volatile("mov #1, r4"); \
530 __asm__ volatile("trapa #34"); \
531}
532#endif
533
534/* end of Fatal Error manager macros */
535
536#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
537
538/* functions */
539
540/*
541 * @brief CPU Initialize
542 *
543 * _CPU_Initialize
544 *
545 * This routine performs CPU dependent initialization.
546 */
547void _CPU_Initialize(void);
548
549typedef void ( *CPU_ISR_raw_handler )( void );
550
551extern CPU_ISR_raw_handler _Hardware_isr_Table[];
552
553void _CPU_ISR_install_raw_handler(
554 uint32_t vector,
555 CPU_ISR_raw_handler new_handler,
556 CPU_ISR_raw_handler *old_handler
557);
558
559typedef void ( *CPU_ISR_handler )( uint32_t );
560
561void _CPU_ISR_install_vector(
562 uint32_t vector,
563 CPU_ISR_handler new_handler,
564 CPU_ISR_handler *old_handler
565);
566
567void *_CPU_Thread_Idle_body( uintptr_t ignored );
568
569/*
570 * _CPU_Context_switch
571 *
572 * This routine switches from the run context to the heir context.
573 */
574
575void _CPU_Context_switch(
576 Context_Control *run,
577 Context_Control *heir
578);
579
580/*
581 * _CPU_Context_restore
582 *
583 * This routine is generally used only to restart self in an
584 * efficient manner. It may simply be a label in _CPU_Context_switch.
585 */
586
587void _CPU_Context_restore(
588 Context_Control *new_context
589) RTEMS_NO_RETURN;
590
591/*
592 * @brief This routine saves the floating point context passed to it.
593 *
594 * _CPU_Context_save_fp
595 *
596 */
597void _CPU_Context_save_fp(
598 Context_Control_fp **fp_context_ptr
599);
600
601/*
602 * @brief This routine restores the floating point context passed to it.
603 *
604 * _CPU_Context_restore_fp
605 *
606 */
607void _CPU_Context_restore_fp(
608 Context_Control_fp **fp_context_ptr
609);
610
611/* FIXME */
612typedef CPU_Interrupt_frame CPU_Exception_frame;
613
614void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
615
616typedef uint32_t CPU_Counter_ticks;
617
618uint32_t _CPU_Counter_frequency( void );
619
620CPU_Counter_ticks _CPU_Counter_read( void );
621
622static inline CPU_Counter_ticks _CPU_Counter_difference(
623 CPU_Counter_ticks second,
624 CPU_Counter_ticks first
625)
626{
627 return second - first;
628}
629
631 typedef uintptr_t CPU_Uint32ptr;
632
634 typedef void sh_isr;
635typedef void ( *sh_isr_entry )( void );
636
637#ifdef __cplusplus
638}
639#endif
640
641#endif
basedefs.h
Basic Definitions.
_CPU_ISR_install_raw_handler
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:103
RTEMS_NO_RETURN
#define RTEMS_NO_RETURN
Definition: basedefs.h:102
RTEMS_INLINE_ROUTINE
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:66
_CPU_Thread_Idle_body
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
_CPU_Initialize
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
CPU_Uint32ptr
uintptr_t CPU_Uint32ptr
Definition: cpu.h:662
_CPU_ISR_install_vector
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
_CPU_Exception_frame_print
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
_CPU_Counter_frequency
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
_CPU_Context_switch
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
_CPU_Counter_read
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
sh_isr
void sh_isr
Definition: cpu.h:634
sh.h
Hitachi SH CPU Department Source.
_CPU_Context_restore_fp
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:904
_CPU_Context_save_fp
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:898
CPU_Exception_frame
The set of registers that specifies the complete processor state.
Definition: cpu.h:629
CPU_Interrupt_frame
Interrupt stack frame (ISF).
Definition: cpu.h:191
Context_Control_fp
SPARC basic context.
Definition: cpu.h:194
Context_Control
Thread register context.
Definition: cpu.h:194