RTEMS: bsps/powerpc/mpc8260ads/include/bsp/irq.h Source File

| RTEMS 5.4-rc2

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irq.h
1/* irq.h
2 *
3 * This include file describe the data structure and the functions implemented
4 * by rtems to write interrupt handlers.
5 *
6 * CopyRight (C) 1999 valette@crf.canon.fr
7 *
8 * This code is heavilly inspired by the public specification of STREAM V2
9 * that can be found at :
10 *
11 * <http://www.chorus.com/Documentation/index.html> by following
12 * the STREAM API Specification Document link.
13 *
14 * Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk>
15 * Surrey Satellite Technology Limited
16 * The interrupt handling on the mpc8260 seems quite different from
17 * the 860 (I don't know the 860 well). Although some interrupts
18 * are routed via the CPM irq and some are direct to the SIU they all
19 * appear logically the same. Therefore I removed the distinction
20 * between SIU and CPM interrupts.
21 *
22 * The license and distribution terms for this file may be
23 * found in the file LICENSE in this distribution or at
24 * http://www.rtems.org/license/LICENSE.
25 */
26
27#ifndef LIBBSP_POWERPC_IRQ_H
28#define LIBBSP_POWERPC_IRQ_H
29#include <rtems/irq.h>
30
31#ifndef ASM
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37/*
38extern volatile unsigned int ppc_cached_irq_mask;
39*/
40
41/*
42 * Symblolic IRQ names and related definitions.
43 */
44
45 /*
46 * CPM IRQ handlers related definitions
47 * CAUTION : BSP_CPM_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
48 */
49#define BSP_CPM_IRQ_NUMBER (64)
50#define BSP_CPM_IRQ_LOWEST_OFFSET (0)
51#define BSP_CPM_IRQ_MAX_OFFSET (BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER - 1)
52 /*
53 * PowerPc exceptions handled as interrupt where a rtems managed interrupt
54 * handler might be connected
55 */
56#define BSP_PROCESSOR_IRQ_NUMBER (1)
57#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CPM_IRQ_MAX_OFFSET + 1)
58#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
59 /*
60 * Summary
61 */
62#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
63#define BSP_LOWEST_OFFSET (BSP_CPM_IRQ_LOWEST_OFFSET)
64#define BSP_MAX_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET)
65
66 /*
67 * Some SIU IRQ symbolic name definition. Please note that
68 * INT IRQ are defined but a single one will be used to
69 * redirect all CPM interrupt.
70 *
71 * On the mpc8260 all this seems to be transparent. Although the
72 * CPM, PIT and TMCNT interrupt may well be the only interrupts routed
73 * to the SIU at the hardware level all of them appear as CPM interupts
74 * to software apart from the registers for setting priority.
75 *
76 * The MPC8260 User Manual seems shot through with inconsistencies
77 * about this whole area.
78 */
79
80 /*
81 * Some CPM IRQ symbolic name definition
82 */
83#define BSP_CPM_IRQ_ERROR (BSP_CPM_IRQ_LOWEST_OFFSET + 0)
84#define BSP_CPM_IRQ_I2C (BSP_CPM_IRQ_LOWEST_OFFSET + 1)
85#define BSP_CPM_IRQ_SPI (BSP_CPM_IRQ_LOWEST_OFFSET + 2)
86#define BSP_CPM_IRQ_RISC_TIMERS (BSP_CPM_IRQ_LOWEST_OFFSET + 3)
87#define BSP_CPM_IRQ_SMC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 4)
88#define BSP_CPM_IRQ_SMC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 5)
89#define BSP_CPM_IRQ_IDMA1 (BSP_CPM_IRQ_LOWEST_OFFSET + 6)
90#define BSP_CPM_IRQ_IDMA2 (BSP_CPM_IRQ_LOWEST_OFFSET + 7)
91#define BSP_CPM_IRQ_IDMA3 (BSP_CPM_IRQ_LOWEST_OFFSET + 8)
92#define BSP_CPM_IRQ_IDMA4 (BSP_CPM_IRQ_LOWEST_OFFSET + 9)
93#define BSP_CPM_IRQ_SDMA (BSP_CPM_IRQ_LOWEST_OFFSET + 10)
94
95#define BSP_CPM_IRQ_TIMER_1 (BSP_CPM_IRQ_LOWEST_OFFSET + 12)
96#define BSP_CPM_IRQ_TIMER_2 (BSP_CPM_IRQ_LOWEST_OFFSET + 13)
97#define BSP_CPM_IRQ_TIMER_3 (BSP_CPM_IRQ_LOWEST_OFFSET + 14)
98#define BSP_CPM_IRQ_TIMER_4 (BSP_CPM_IRQ_LOWEST_OFFSET + 15)
99#define BSP_CPM_IRQ_TMCNT (BSP_CPM_IRQ_LOWEST_OFFSET + 16)
100#define BSP_CPM_IRQ_PIT (BSP_CPM_IRQ_LOWEST_OFFSET + 17)
101
102#define BSP_CPM_IRQ_IRQ1 (BSP_CPM_IRQ_LOWEST_OFFSET + 19)
103#define BSP_CPM_IRQ_IRQ2 (BSP_CPM_IRQ_LOWEST_OFFSET + 20)
104#define BSP_CPM_IRQ_IRQ3 (BSP_CPM_IRQ_LOWEST_OFFSET + 21)
105#define BSP_CPM_IRQ_IRQ4 (BSP_CPM_IRQ_LOWEST_OFFSET + 22)
106#define BSP_CPM_IRQ_IRQ5 (BSP_CPM_IRQ_LOWEST_OFFSET + 23)
107#define BSP_CPM_IRQ_IRQ6 (BSP_CPM_IRQ_LOWEST_OFFSET + 24)
108#define BSP_CPM_IRQ_IRQ7 (BSP_CPM_IRQ_LOWEST_OFFSET + 25)
109
110#define BSP_CPM_IRQ_FCC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 32)
111#define BSP_CPM_IRQ_FCC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 33)
112#define BSP_CPM_IRQ_FCC3 (BSP_CPM_IRQ_LOWEST_OFFSET + 34)
113#define BSP_CPM_IRQ_MCC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 36)
114#define BSP_CPM_IRQ_MCC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 37)
115
116#define BSP_CPM_IRQ_SCC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 40)
117#define BSP_CPM_IRQ_SCC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 41)
118#define BSP_CPM_IRQ_SCC3 (BSP_CPM_IRQ_LOWEST_OFFSET + 42)
119#define BSP_CPM_IRQ_SCC4 (BSP_CPM_IRQ_LOWEST_OFFSET + 43)
120
121#define BSP_CPM_IRQ_PC15 (BSP_CPM_IRQ_LOWEST_OFFSET + 48)
122#define BSP_CPM_IRQ_PC14 (BSP_CPM_IRQ_LOWEST_OFFSET + 49)
123#define BSP_CPM_IRQ_PC13 (BSP_CPM_IRQ_LOWEST_OFFSET + 50)
124#define BSP_CPM_IRQ_PC12 (BSP_CPM_IRQ_LOWEST_OFFSET + 51)
125#define BSP_CPM_IRQ_PC11 (BSP_CPM_IRQ_LOWEST_OFFSET + 52)
126#define BSP_CPM_IRQ_PC10 (BSP_CPM_IRQ_LOWEST_OFFSET + 53)
127#define BSP_CPM_IRQ_PC9 (BSP_CPM_IRQ_LOWEST_OFFSET + 54)
128#define BSP_CPM_IRQ_PC8 (BSP_CPM_IRQ_LOWEST_OFFSET + 55)
129#define BSP_CPM_IRQ_PC7 (BSP_CPM_IRQ_LOWEST_OFFSET + 56)
130#define BSP_CPM_IRQ_PC6 (BSP_CPM_IRQ_LOWEST_OFFSET + 57)
131#define BSP_CPM_IRQ_PC5 (BSP_CPM_IRQ_LOWEST_OFFSET + 58)
132#define BSP_CPM_IRQ_PC4 (BSP_CPM_IRQ_LOWEST_OFFSET + 59)
133#define BSP_CPM_IRQ_PC3 (BSP_CPM_IRQ_LOWEST_OFFSET + 60)
134#define BSP_CPM_IRQ_PC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 61)
135#define BSP_CPM_IRQ_PC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 62)
136#define BSP_CPM_IRQ_PC0 (BSP_CPM_IRQ_LOWEST_OFFSET + 63)
137
138 /*
139 * Some Processor exception handled as rtems IRQ symbolic name definition
140 */
141#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
142#define BSP_PERIODIC_TIMER (BSP_DECREMENTER)
143
144#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET
145
146#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET
147
148#define CPM_INTERRUPT
149
150/*-------------------------------------------------------------------------+
151| Function Prototypes.
152+--------------------------------------------------------------------------*/
153/*
154 * ------------------------ PPC CPM Mngt Routines -------
155 */
156
157/*
158 * function to disable a particular irq. After calling
159 * this function, even if the device asserts the interrupt line it will
160 * not be propagated further to the processor
161 */
162int BSP_irq_disable_at_cpm (const rtems_irq_number irqLine);
163/*
164 * function to enable a particular irq. After calling
165 * this function, if the device asserts the interrupt line it will
166 * be propagated further to the processor
167 */
168int BSP_irq_enable_at_cpm (const rtems_irq_number irqLine);
169/*
170 * function to acknoledge a particular irq. After calling
171 * this function, if a device asserts an enabled interrupt line it will
172 * be propagated further to the processor. Mainly usefull for people
173 * writting raw handlers as this is automagically done for rtems managed
174 * handlers.
175 */
176int BSP_irq_ack_at_cpm (const rtems_irq_number irqLine);
177/*
178 * function to check if a particular irq is enabled. After calling
179 */
180int BSP_irq_enabled_at_cpm (const rtems_irq_number irqLine);
181
182extern void BSP_rtems_irq_mng_init(unsigned cpuId);
183
184#ifdef __cplusplus
185}
186#endif
187
188/* Now that we have defined some basics, include the generic support */
189#include <bsp/irq-generic.h>
190
191#endif
192
193#endif
irq.h
irq-generic.h
This header file provides interfaces of the generic interrupt controller support.