RTEMS: bsps/arm/atsam/include/libchip/include/samv71/component/component_efc.h Source File

| RTEMS 5.4-rc2

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component_efc.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMV71_EFC_COMPONENT_
31#define _SAMV71_EFC_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __IO uint32_t EEFC_FMR;
43 __O uint32_t EEFC_FCR;
44 __I uint32_t EEFC_FSR;
45 __I uint32_t EEFC_FRR;
46 __I uint32_t Reserved1[1];
47 __I uint32_t EEFC_VERSION;
48 __I uint32_t Reserved2[51];
49 __IO uint32_t EEFC_WPMR;
50} Efc;
51#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
52/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
53#define EEFC_FMR_FRDY (0x1u << 0)
54#define EEFC_FMR_FWS_Pos 8
55#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos)
56#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
57#define EEFC_FMR_SCOD (0x1u << 16)
58#define EEFC_FMR_CLOE (0x1u << 26)
59/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
60#define EEFC_FCR_FCMD_Pos 0
61#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos)
62#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
63#define EEFC_FCR_FCMD_GETD (0x0u << 0)
64#define EEFC_FCR_FCMD_WP (0x1u << 0)
65#define EEFC_FCR_FCMD_WPL (0x2u << 0)
66#define EEFC_FCR_FCMD_EWP (0x3u << 0)
67#define EEFC_FCR_FCMD_EWPL (0x4u << 0)
68#define EEFC_FCR_FCMD_EA (0x5u << 0)
69#define EEFC_FCR_FCMD_EPA (0x7u << 0)
70#define EEFC_FCR_FCMD_SLB (0x8u << 0)
71#define EEFC_FCR_FCMD_CLB (0x9u << 0)
72#define EEFC_FCR_FCMD_GLB (0xAu << 0)
73#define EEFC_FCR_FCMD_SGPB (0xBu << 0)
74#define EEFC_FCR_FCMD_CGPB (0xCu << 0)
75#define EEFC_FCR_FCMD_GGPB (0xDu << 0)
76#define EEFC_FCR_FCMD_STUI (0xEu << 0)
77#define EEFC_FCR_FCMD_SPUI (0xFu << 0)
78#define EEFC_FCR_FCMD_GCALB (0x10u << 0)
79#define EEFC_FCR_FCMD_ES (0x11u << 0)
80#define EEFC_FCR_FCMD_WUS (0x12u << 0)
81#define EEFC_FCR_FCMD_EUS (0x13u << 0)
82#define EEFC_FCR_FCMD_STUS (0x14u << 0)
83#define EEFC_FCR_FCMD_SPUS (0x15u << 0)
84#define EEFC_FCR_FARG_Pos 8
85#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos)
86#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
87#define EEFC_FCR_FKEY_Pos 24
88#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos)
89#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
90#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24)
91/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
92#define EEFC_FSR_FRDY (0x1u << 0)
93#define EEFC_FSR_FCMDE (0x1u << 1)
94#define EEFC_FSR_FLOCKE (0x1u << 2)
95#define EEFC_FSR_FLERR (0x1u << 3)
96#define EEFC_FSR_UECCELSB (0x1u << 16)
97#define EEFC_FSR_MECCELSB (0x1u << 17)
98#define EEFC_FSR_UECCEMSB (0x1u << 18)
99#define EEFC_FSR_MECCEMSB (0x1u << 19)
100/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
101#define EEFC_FRR_FVALUE_Pos 0
102#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos)
103/* -------- EEFC_VERSION : (EFC Offset: 0x14) EEFC Version Register -------- */
104#define EEFC_VERSION_VERSION_Pos 0
105#define EEFC_VERSION_VERSION_Msk (0xfffu << EEFC_VERSION_VERSION_Pos)
106#define EEFC_VERSION_MFN_Pos 16
107#define EEFC_VERSION_MFN_Msk (0x7u << EEFC_VERSION_MFN_Pos)
108/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */
109#define EEFC_WPMR_WPEN (0x1u << 0)
110#define EEFC_WPMR_WPKEY_Pos 8
111#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos)
112#define EEFC_WPMR_WPKEY(value) ((EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos)))
113#define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8)
116
117
118#endif /* _SAMV71_EFC_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Efc
Efc hardware registers.
Definition: component_efc.h:41
Efc::EEFC_VERSION
__I uint32_t EEFC_VERSION
(Efc Offset: 0x14) EEFC Version Register
Definition: component_efc.h:47