RTEMS: cpukit/score/cpu/riscv/include/rtems/asm.h Source File

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asm.h
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1
11/*
12 * NOTE: The spacing in the use of these macros
13 * is critical to them working as advertised.
14 *
15 * This file is based on similar code found in newlib available
16 * from ftp.cygnus.com. The file which was used had no copyright
17 * notice. This file is freely distributable as long as the source
18 * of the file is noted. This file is:
19 *
20 * Copyright (c) 2015 University of York.
21 * Hesham Almatary <hesham@alumni.york.ac.uk>
22 *
23 *
24 * COPYRIGHT (c) 1994-1997.
25 * On-Line Applications Research Corporation (OAR).
26 *
27 * Redistribution and use in source and binary forms, with or without
28 * modification, are permitted provided that the following conditions
29 * are met:
30 * 1. Redistributions of source code must retain the above copyright
31 * notice, this list of conditions and the following disclaimer.
32 * 2. Redistributions in binary form must reproduce the above copyright
33 * notice, this list of conditions and the following disclaimer in the
34 * documentation and/or other materials provided with the distribution.
35 *
36 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
37 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
38 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
39 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
40 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
41 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
42 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
43 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
44 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
45 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
46 * SUCH DAMAGE.
47 */
48
49#ifndef __RISCV_ASM_H
50#define __RISCV_ASM_H
51
52/*
53 * Indicate we are in an assembly file and get the basic CPU definitions.
54 */
55
56#ifndef ASM
57#define ASM
58#endif
59#include <rtems/score/cpuopts.h>
60#include <rtems/score/riscv.h>
61
72/*
73 * Recent versions of GNU cpp define variables which indicate the
74 * need for underscores and percents. If not using GNU cpp or
75 * the version does not support this, then you will obviously
76 * have to define these as appropriate.
77 */
78
79#ifndef __USER_LABEL_PREFIX__
80#define __USER_LABEL_PREFIX__ _
81#endif
82
83#ifndef __REGISTER_PREFIX__
84#define __REGISTER_PREFIX__
85#endif
86
87/* ANSI concatenation macros. */
88
89#define CONCAT1(a, b) CONCAT2(a, b)
90#define CONCAT2(a, b) a ## b
91
92/* Use the right prefix for global labels. */
93
94#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
95
96/* Use the right prefix for registers. */
97
98#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
99
100/*
101 * define macros for all of the registers on this CPU
102 *
103 * EXAMPLE: #define d0 REG (d0)
104 */
105
106/*
107 * Define macros to handle section beginning and ends.
108 */
109#define BEGIN_CODE_DCL .text
110#define END_CODE_DCL
111#define BEGIN_DATA_DCL .data
112#define END_DATA_DCL
113#define BEGIN_CODE .text
114#define END_CODE
115#define BEGIN_DATA
116#define END_DATA
117#define BEGIN_BSS
118#define END_BSS
119#define END
120
121/*
122 * Following must be tailor for a particular flavor of the C compiler.
123 * They may need to put underscores in front of the symbols.
124 */
125
126#define PUBLIC(sym) .global SYM (sym)
127#define EXTERN(sym) .extern SYM (sym)
128#define TYPE_FUNC(sym) .type SYM (sym), %function
129
130#if __riscv_xlen == 32
131
132#define LREG lw
133
134#define SREG sw
135
136#elif __riscv_xlen == 64
137
138#define LREG ld
139
140#define SREG sd
141
142#endif /* __riscv_xlen */
143
144#ifdef __riscv_cmodel_medany
145
146#define LADDR lla
147
148#else /* !__riscv_cmodel_medany */
149
150#define LADDR la
151
152#endif /* __riscv_cmodel_medany */
153
154#if __riscv_flen == 32
155
156#define FLREG flw
157
158#define FSREG fsw
159
160#define FMVYX fmv.s.x
161
162#define FMVXY fmv.x.s
163
164#elif __riscv_flen == 64
165
166#define FLREG fld
167
168#define FSREG fsd
169
170#if __riscv_xlen == 32
171
172#define FMVYX fmv.s.x
173
174#define FMVXY fmv.x.s
175
176#elif __riscv_xlen == 64
177
178#define FMVYX fmv.d.x
179
180#define FMVXY fmv.x.d
181
182#endif /* __riscv_xlen */
183
184#endif /* __riscv_flen */
185
186.macro GET_SELF_CPU_CONTROL REG
187#ifdef RTEMS_SMP
188 csrr \REG, mscratch
189#else
190 LADDR \REG, _Per_CPU_Information
191#endif
192.endm
193
194.macro CLEAR_RESERVATIONS REG
195#ifdef __riscv_atomic
196 /*
197 * Clear reservations, see also RISC-V User-Level ISA V2.3, comment in
198 * section 8.2 "Load-Reserved/Store-Conditional Instructions".
199 */
200 sc.w zero, zero, (\REG)
201#endif
202.endm
203
204#endif
205
riscv.h