RTEMS: bsps/arm/atsam/include/libchip/include/same70/component/component_twihs.h Source File

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component_twihs.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAME70_TWIHS_COMPONENT_
31#define _SAME70_TWIHS_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41 typedef struct {
42 __O uint32_t TWIHS_CR;
43 __IO uint32_t TWIHS_MMR;
44 __IO uint32_t TWIHS_SMR;
45 __IO uint32_t TWIHS_IADR;
46 __IO uint32_t TWIHS_CWGR;
47 __I uint32_t Reserved1[3];
48 __I uint32_t TWIHS_SR;
49 __O uint32_t TWIHS_IER;
50 __O uint32_t TWIHS_IDR;
51 __I uint32_t TWIHS_IMR;
52 __I uint32_t TWIHS_RHR;
53 __O uint32_t TWIHS_THR;
54 __IO uint32_t TWIHS_SMBTR;
55 __I uint32_t Reserved2[2];
56 __IO uint32_t TWIHS_FILTR;
57 __I uint32_t Reserved3[1];
58 __IO uint32_t TWIHS_SWMR;
59 __I uint32_t Reserved4[37];
60 __IO uint32_t TWIHS_WPMR;
61 __I uint32_t TWIHS_WPSR;
62} Twihs;
63#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
64/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */
65#define TWIHS_CR_START (0x1u << 0)
66#define TWIHS_CR_STOP (0x1u << 1)
67#define TWIHS_CR_MSEN (0x1u << 2)
68#define TWIHS_CR_MSDIS (0x1u << 3)
69#define TWIHS_CR_SVEN (0x1u << 4)
70#define TWIHS_CR_SVDIS (0x1u << 5)
71#define TWIHS_CR_QUICK (0x1u << 6)
72#define TWIHS_CR_SWRST (0x1u << 7)
73#define TWIHS_CR_HSEN (0x1u << 8)
74#define TWIHS_CR_HSDIS (0x1u << 9)
75#define TWIHS_CR_SMBEN (0x1u << 10)
76#define TWIHS_CR_SMBDIS (0x1u << 11)
77#define TWIHS_CR_PECEN (0x1u << 12)
78#define TWIHS_CR_PECDIS (0x1u << 13)
79#define TWIHS_CR_PECRQ (0x1u << 14)
80#define TWIHS_CR_CLEAR (0x1u << 15)
81/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */
82#define TWIHS_MMR_IADRSZ_Pos 8
83#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos)
84#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos)))
85#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8)
86#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8)
87#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8)
88#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8)
89#define TWIHS_MMR_MREAD (0x1u << 12)
90#define TWIHS_MMR_DADR_Pos 16
91#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos)
92#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos)))
93/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */
94#define TWIHS_SMR_NACKEN (0x1u << 0)
95#define TWIHS_SMR_SMDA (0x1u << 2)
96#define TWIHS_SMR_SMHH (0x1u << 3)
97#define TWIHS_SMR_SCLWSDIS (0x1u << 6)
98#define TWIHS_SMR_MASK_Pos 8
99#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos)
100#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos)))
101#define TWIHS_SMR_SADR_Pos 16
102#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos)
103#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos)))
104#define TWIHS_SMR_SADR1EN (0x1u << 28)
105#define TWIHS_SMR_SADR2EN (0x1u << 29)
106#define TWIHS_SMR_SADR3EN (0x1u << 30)
107#define TWIHS_SMR_DATAMEN (0x1u << 31)
108/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */
109#define TWIHS_IADR_IADR_Pos 0
110#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos)
111#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos)))
112/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */
113#define TWIHS_CWGR_CLDIV_Pos 0
114#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos)
115#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos)))
116#define TWIHS_CWGR_CHDIV_Pos 8
117#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos)
118#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos)))
119#define TWIHS_CWGR_CKDIV_Pos 16
120#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos)
121#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos)))
122#define TWIHS_CWGR_HOLD_Pos 24
123#define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos)
124#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos)))
125/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */
126#define TWIHS_SR_TXCOMP (0x1u << 0)
127#define TWIHS_SR_RXRDY (0x1u << 1)
128#define TWIHS_SR_TXRDY (0x1u << 2)
129#define TWIHS_SR_SVREAD (0x1u << 3)
130#define TWIHS_SR_SVACC (0x1u << 4)
131#define TWIHS_SR_GACC (0x1u << 5)
132#define TWIHS_SR_OVRE (0x1u << 6)
133#define TWIHS_SR_UNRE (0x1u << 7)
134#define TWIHS_SR_NACK (0x1u << 8)
135#define TWIHS_SR_ARBLST (0x1u << 9)
136#define TWIHS_SR_SCLWS (0x1u << 10)
137#define TWIHS_SR_EOSACC (0x1u << 11)
138#define TWIHS_SR_MCACK (0x1u << 16)
139#define TWIHS_SR_TOUT (0x1u << 18)
140#define TWIHS_SR_PECERR (0x1u << 19)
141#define TWIHS_SR_SMBDAM (0x1u << 20)
142#define TWIHS_SR_SMBHHM (0x1u << 21)
143#define TWIHS_SR_SCL (0x1u << 24)
144#define TWIHS_SR_SDA (0x1u << 25)
145/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */
146#define TWIHS_IER_TXCOMP (0x1u << 0)
147#define TWIHS_IER_RXRDY (0x1u << 1)
148#define TWIHS_IER_TXRDY (0x1u << 2)
149#define TWIHS_IER_SVACC (0x1u << 4)
150#define TWIHS_IER_GACC (0x1u << 5)
151#define TWIHS_IER_OVRE (0x1u << 6)
152#define TWIHS_IER_UNRE (0x1u << 7)
153#define TWIHS_IER_NACK (0x1u << 8)
154#define TWIHS_IER_ARBLST (0x1u << 9)
155#define TWIHS_IER_SCL_WS (0x1u << 10)
156#define TWIHS_IER_EOSACC (0x1u << 11)
157#define TWIHS_IER_MCACK (0x1u << 16)
158#define TWIHS_IER_TOUT (0x1u << 18)
159#define TWIHS_IER_PECERR (0x1u << 19)
160#define TWIHS_IER_SMBDAM (0x1u << 20)
161#define TWIHS_IER_SMBHHM (0x1u << 21)
162/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */
163#define TWIHS_IDR_TXCOMP (0x1u << 0)
164#define TWIHS_IDR_RXRDY (0x1u << 1)
165#define TWIHS_IDR_TXRDY (0x1u << 2)
166#define TWIHS_IDR_SVACC (0x1u << 4)
167#define TWIHS_IDR_GACC (0x1u << 5)
168#define TWIHS_IDR_OVRE (0x1u << 6)
169#define TWIHS_IDR_UNRE (0x1u << 7)
170#define TWIHS_IDR_NACK (0x1u << 8)
171#define TWIHS_IDR_ARBLST (0x1u << 9)
172#define TWIHS_IDR_SCL_WS (0x1u << 10)
173#define TWIHS_IDR_EOSACC (0x1u << 11)
174#define TWIHS_IDR_MCACK (0x1u << 16)
175#define TWIHS_IDR_TOUT (0x1u << 18)
176#define TWIHS_IDR_PECERR (0x1u << 19)
177#define TWIHS_IDR_SMBDAM (0x1u << 20)
178#define TWIHS_IDR_SMBHHM (0x1u << 21)
179/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */
180#define TWIHS_IMR_TXCOMP (0x1u << 0)
181#define TWIHS_IMR_RXRDY (0x1u << 1)
182#define TWIHS_IMR_TXRDY (0x1u << 2)
183#define TWIHS_IMR_SVACC (0x1u << 4)
184#define TWIHS_IMR_GACC (0x1u << 5)
185#define TWIHS_IMR_OVRE (0x1u << 6)
186#define TWIHS_IMR_UNRE (0x1u << 7)
187#define TWIHS_IMR_NACK (0x1u << 8)
188#define TWIHS_IMR_ARBLST (0x1u << 9)
189#define TWIHS_IMR_SCL_WS (0x1u << 10)
190#define TWIHS_IMR_EOSACC (0x1u << 11)
191#define TWIHS_IMR_MCACK (0x1u << 16)
192#define TWIHS_IMR_TOUT (0x1u << 18)
193#define TWIHS_IMR_PECERR (0x1u << 19)
194#define TWIHS_IMR_SMBDAM (0x1u << 20)
195#define TWIHS_IMR_SMBHHM (0x1u << 21)
196/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */
197#define TWIHS_RHR_RXDATA_Pos 0
198#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos)
199/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */
200#define TWIHS_THR_TXDATA_Pos 0
201#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos)
202#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos)))
203/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */
204#define TWIHS_SMBTR_PRESC_Pos 0
205#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos)
206#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos)))
207#define TWIHS_SMBTR_TLOWS_Pos 8
208#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos)
209#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos)))
210#define TWIHS_SMBTR_TLOWM_Pos 16
211#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos)
212#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos)))
213#define TWIHS_SMBTR_THMAX_Pos 24
214#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos)
215#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos)))
216/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */
217#define TWIHS_FILTR_FILT (0x1u << 0)
218#define TWIHS_FILTR_PADFEN (0x1u << 1)
219#define TWIHS_FILTR_PADFCFG (0x1u << 2)
220#define TWIHS_FILTR_THRES_Pos 8
221#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos)
222#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos)))
223/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */
224#define TWIHS_SWMR_SADR1_Pos 0
225#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos)
226#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos)))
227#define TWIHS_SWMR_SADR2_Pos 8
228#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos)
229#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos)))
230#define TWIHS_SWMR_SADR3_Pos 16
231#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos)
232#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos)))
233#define TWIHS_SWMR_DATAM_Pos 24
234#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos)
235#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos)))
236/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */
237#define TWIHS_WPMR_WPEN (0x1u << 0)
238#define TWIHS_WPMR_WPKEY_Pos 8
239#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos)
240#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos)))
241#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8)
242/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */
243#define TWIHS_WPSR_WPVS (0x1u << 0)
244#define TWIHS_WPSR_WPVSRC_Pos 8
245#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos)
248
249
250#endif /* _SAME70_TWIHS_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Twihs
Twihs hardware registers.
Definition: component_twihs.h:41
Twihs::TWIHS_THR
__O uint32_t TWIHS_THR
(Twihs Offset: 0x34) Transmit Holding Register
Definition: component_twihs.h:53
Twihs::TWIHS_CWGR
__IO uint32_t TWIHS_CWGR
(Twihs Offset: 0x10) Clock Waveform Generator Register
Definition: component_twihs.h:46
Twihs::TWIHS_SWMR
__IO uint32_t TWIHS_SWMR
(Twihs Offset: 0x4C) SleepWalking Matching Register
Definition: component_twihs.h:58
Twihs::TWIHS_SMBTR
__IO uint32_t TWIHS_SMBTR
(Twihs Offset: 0x38) SMBus Timing Register
Definition: component_twihs.h:54
Twihs::TWIHS_MMR
__IO uint32_t TWIHS_MMR
(Twihs Offset: 0x04) Master Mode Register
Definition: component_twihs.h:43
Twihs::TWIHS_IADR
__IO uint32_t TWIHS_IADR
(Twihs Offset: 0x0C) Internal Address Register
Definition: component_twihs.h:45
Twihs::TWIHS_SMR
__IO uint32_t TWIHS_SMR
(Twihs Offset: 0x08) Slave Mode Register
Definition: component_twihs.h:44
Twihs::TWIHS_WPMR
__IO uint32_t TWIHS_WPMR
(Twihs Offset: 0xE4) Write Protection Mode Register
Definition: component_twihs.h:60
Twihs::TWIHS_IMR
__I uint32_t TWIHS_IMR
(Twihs Offset: 0x2C) Interrupt Mask Register
Definition: component_twihs.h:51
Twihs::TWIHS_CR
__O uint32_t TWIHS_CR
(Twihs Offset: 0x00) Control Register
Definition: component_twihs.h:42
Twihs::TWIHS_IER
__O uint32_t TWIHS_IER
(Twihs Offset: 0x24) Interrupt Enable Register
Definition: component_twihs.h:49
Twihs::TWIHS_FILTR
__IO uint32_t TWIHS_FILTR
(Twihs Offset: 0x44) Filter Register
Definition: component_twihs.h:56
Twihs::TWIHS_RHR
__I uint32_t TWIHS_RHR
(Twihs Offset: 0x30) Receive Holding Register
Definition: component_twihs.h:52
Twihs::TWIHS_IDR
__O uint32_t TWIHS_IDR
(Twihs Offset: 0x28) Interrupt Disable Register
Definition: component_twihs.h:50
Twihs::TWIHS_WPSR
__I uint32_t TWIHS_WPSR
(Twihs Offset: 0xE8) Write Protection Status Register
Definition: component_twihs.h:61
Twihs::TWIHS_SR
__I uint32_t TWIHS_SR
(Twihs Offset: 0x20) Status Register
Definition: component_twihs.h:48