RTEMS: bsps/arm/atsam/include/libchip/include/same70/component/component_pwm.h Source File

| RTEMS 5.4-rc2

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component_pwm.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAME70_PWM_COMPONENT_
31#define _SAME70_PWM_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41 typedef struct {
42 __IO uint32_t PWM_CMR;
43 __IO uint32_t PWM_CDTY;
44 __O uint32_t PWM_CDTYUPD;
45 __IO uint32_t PWM_CPRD;
46 __O uint32_t PWM_CPRDUPD;
47 __I uint32_t PWM_CCNT;
48 __IO uint32_t PWM_DT;
49 __O uint32_t PWM_DTUPD;
50} PwmCh_num;
52 typedef struct {
53 __IO uint32_t PWM_CMPV;
54 __O uint32_t PWM_CMPVUPD;
55 __IO uint32_t PWM_CMPM;
56 __O uint32_t PWM_CMPMUPD;
57} PwmCmp;
59#define PWMCMP_NUMBER 8
60#define PWMCH_NUM_NUMBER 4
61 typedef struct {
62 __IO uint32_t PWM_CLK;
63 __O uint32_t PWM_ENA;
64 __O uint32_t PWM_DIS;
65 __I uint32_t PWM_SR;
66 __O uint32_t PWM_IER1;
67 __O uint32_t PWM_IDR1;
68 __I uint32_t PWM_IMR1;
69 __I uint32_t PWM_ISR1;
70 __IO uint32_t PWM_SCM;
71 __O uint32_t PWM_DMAR;
72 __IO uint32_t PWM_SCUC;
73 __IO uint32_t PWM_SCUP;
74 __O uint32_t PWM_SCUPUPD;
75 __O uint32_t PWM_IER2;
76 __O uint32_t PWM_IDR2;
77 __I uint32_t PWM_IMR2;
78 __I uint32_t PWM_ISR2;
79 __IO uint32_t PWM_OOV;
80 __IO uint32_t PWM_OS;
81 __O uint32_t PWM_OSS;
82 __O uint32_t PWM_OSC;
83 __O uint32_t PWM_OSSUPD;
84 __O uint32_t PWM_OSCUPD;
85 __IO uint32_t PWM_FMR;
86 __I uint32_t PWM_FSR;
87 __O uint32_t PWM_FCR;
88 __IO uint32_t PWM_FPV1;
89 __IO uint32_t PWM_FPE;
90 __I uint32_t Reserved1[3];
91 __IO uint32_t PWM_ELMR[2];
92 __I uint32_t Reserved2[7];
93 __IO uint32_t PWM_SSPR;
94 __O uint32_t PWM_SSPUP;
95 __I uint32_t Reserved3[2];
96 __IO uint32_t PWM_SMMR;
97 __I uint32_t Reserved4[3];
98 __IO uint32_t PWM_FPV2;
99 __I uint32_t Reserved5[8];
100 __O uint32_t PWM_WPCR;
101 __I uint32_t PWM_WPSR;
102 __I uint32_t Reserved6[17];
103 PwmCmp PWM_CMP[PWMCMP_NUMBER];
104 __I uint32_t Reserved7[20];
105 PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER];
106 __I uint32_t Reserved8[96];
107 __O uint32_t PWM_CMUPD0;
108 __I uint32_t Reserved9[7];
109 __O uint32_t PWM_CMUPD1;
110 __I uint32_t Reserved10[2];
111 __IO uint32_t PWM_ETRG1;
112 __IO uint32_t PWM_LEBR1;
113 __I uint32_t Reserved11[3];
114 __O uint32_t PWM_CMUPD2;
115 __I uint32_t Reserved12[2];
116 __IO uint32_t PWM_ETRG2;
117 __IO uint32_t PWM_LEBR2;
118 __I uint32_t Reserved13[3];
119 __O uint32_t PWM_CMUPD3;
120} Pwm;
121#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
122/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
123#define PWM_CLK_DIVA_Pos 0
124#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos)
125#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
126#define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0)
127#define PWM_CLK_DIVA_PREA (0x1u << 0)
128#define PWM_CLK_PREA_Pos 8
129#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos)
130#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
131#define PWM_CLK_PREA_CLK (0x0u << 8)
132#define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8)
133#define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8)
134#define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8)
135#define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8)
136#define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8)
137#define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8)
138#define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8)
139#define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8)
140#define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8)
141#define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8)
142#define PWM_CLK_DIVB_Pos 16
143#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos)
144#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
145#define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16)
146#define PWM_CLK_DIVB_PREB (0x1u << 16)
147#define PWM_CLK_PREB_Pos 24
148#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos)
149#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
150#define PWM_CLK_PREB_CLK (0x0u << 24)
151#define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24)
152#define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24)
153#define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24)
154#define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24)
155#define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24)
156#define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24)
157#define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24)
158#define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24)
159#define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24)
160#define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24)
161/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
162#define PWM_ENA_CHID0 (0x1u << 0)
163#define PWM_ENA_CHID1 (0x1u << 1)
164#define PWM_ENA_CHID2 (0x1u << 2)
165#define PWM_ENA_CHID3 (0x1u << 3)
166/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
167#define PWM_DIS_CHID0 (0x1u << 0)
168#define PWM_DIS_CHID1 (0x1u << 1)
169#define PWM_DIS_CHID2 (0x1u << 2)
170#define PWM_DIS_CHID3 (0x1u << 3)
171/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
172#define PWM_SR_CHID0 (0x1u << 0)
173#define PWM_SR_CHID1 (0x1u << 1)
174#define PWM_SR_CHID2 (0x1u << 2)
175#define PWM_SR_CHID3 (0x1u << 3)
176/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
177#define PWM_IER1_CHID0 (0x1u << 0)
178#define PWM_IER1_CHID1 (0x1u << 1)
179#define PWM_IER1_CHID2 (0x1u << 2)
180#define PWM_IER1_CHID3 (0x1u << 3)
181#define PWM_IER1_FCHID0 (0x1u << 16)
182#define PWM_IER1_FCHID1 (0x1u << 17)
183#define PWM_IER1_FCHID2 (0x1u << 18)
184#define PWM_IER1_FCHID3 (0x1u << 19)
185/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
186#define PWM_IDR1_CHID0 (0x1u << 0)
187#define PWM_IDR1_CHID1 (0x1u << 1)
188#define PWM_IDR1_CHID2 (0x1u << 2)
189#define PWM_IDR1_CHID3 (0x1u << 3)
190#define PWM_IDR1_FCHID0 (0x1u << 16)
191#define PWM_IDR1_FCHID1 (0x1u << 17)
192#define PWM_IDR1_FCHID2 (0x1u << 18)
193#define PWM_IDR1_FCHID3 (0x1u << 19)
194/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
195#define PWM_IMR1_CHID0 (0x1u << 0)
196#define PWM_IMR1_CHID1 (0x1u << 1)
197#define PWM_IMR1_CHID2 (0x1u << 2)
198#define PWM_IMR1_CHID3 (0x1u << 3)
199#define PWM_IMR1_FCHID0 (0x1u << 16)
200#define PWM_IMR1_FCHID1 (0x1u << 17)
201#define PWM_IMR1_FCHID2 (0x1u << 18)
202#define PWM_IMR1_FCHID3 (0x1u << 19)
203/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
204#define PWM_ISR1_CHID0 (0x1u << 0)
205#define PWM_ISR1_CHID1 (0x1u << 1)
206#define PWM_ISR1_CHID2 (0x1u << 2)
207#define PWM_ISR1_CHID3 (0x1u << 3)
208#define PWM_ISR1_FCHID0 (0x1u << 16)
209#define PWM_ISR1_FCHID1 (0x1u << 17)
210#define PWM_ISR1_FCHID2 (0x1u << 18)
211#define PWM_ISR1_FCHID3 (0x1u << 19)
212/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
213#define PWM_SCM_SYNC0 (0x1u << 0)
214#define PWM_SCM_SYNC1 (0x1u << 1)
215#define PWM_SCM_SYNC2 (0x1u << 2)
216#define PWM_SCM_SYNC3 (0x1u << 3)
217#define PWM_SCM_UPDM_Pos 16
218#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos)
219#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos)))
220#define PWM_SCM_UPDM_MODE0 (0x0u << 16)
221#define PWM_SCM_UPDM_MODE1 (0x1u << 16)
222#define PWM_SCM_UPDM_MODE2 (0x2u << 16)
223#define PWM_SCM_PTRM (0x1u << 20)
224#define PWM_SCM_PTRCS_Pos 21
225#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos)
226#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
227/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */
228#define PWM_DMAR_DMADUTY_Pos 0
229#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos)
230#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos)))
231/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
232#define PWM_SCUC_UPDULOCK (0x1u << 0)
233/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
234#define PWM_SCUP_UPR_Pos 0
235#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos)
236#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
237#define PWM_SCUP_UPRCNT_Pos 4
238#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos)
239#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
240/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
241#define PWM_SCUPUPD_UPRUPD_Pos 0
242#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos)
243#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
244/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
245#define PWM_IER2_WRDY (0x1u << 0)
246#define PWM_IER2_UNRE (0x1u << 3)
247#define PWM_IER2_CMPM0 (0x1u << 8)
248#define PWM_IER2_CMPM1 (0x1u << 9)
249#define PWM_IER2_CMPM2 (0x1u << 10)
250#define PWM_IER2_CMPM3 (0x1u << 11)
251#define PWM_IER2_CMPM4 (0x1u << 12)
252#define PWM_IER2_CMPM5 (0x1u << 13)
253#define PWM_IER2_CMPM6 (0x1u << 14)
254#define PWM_IER2_CMPM7 (0x1u << 15)
255#define PWM_IER2_CMPU0 (0x1u << 16)
256#define PWM_IER2_CMPU1 (0x1u << 17)
257#define PWM_IER2_CMPU2 (0x1u << 18)
258#define PWM_IER2_CMPU3 (0x1u << 19)
259#define PWM_IER2_CMPU4 (0x1u << 20)
260#define PWM_IER2_CMPU5 (0x1u << 21)
261#define PWM_IER2_CMPU6 (0x1u << 22)
262#define PWM_IER2_CMPU7 (0x1u << 23)
263/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
264#define PWM_IDR2_WRDY (0x1u << 0)
265#define PWM_IDR2_UNRE (0x1u << 3)
266#define PWM_IDR2_CMPM0 (0x1u << 8)
267#define PWM_IDR2_CMPM1 (0x1u << 9)
268#define PWM_IDR2_CMPM2 (0x1u << 10)
269#define PWM_IDR2_CMPM3 (0x1u << 11)
270#define PWM_IDR2_CMPM4 (0x1u << 12)
271#define PWM_IDR2_CMPM5 (0x1u << 13)
272#define PWM_IDR2_CMPM6 (0x1u << 14)
273#define PWM_IDR2_CMPM7 (0x1u << 15)
274#define PWM_IDR2_CMPU0 (0x1u << 16)
275#define PWM_IDR2_CMPU1 (0x1u << 17)
276#define PWM_IDR2_CMPU2 (0x1u << 18)
277#define PWM_IDR2_CMPU3 (0x1u << 19)
278#define PWM_IDR2_CMPU4 (0x1u << 20)
279#define PWM_IDR2_CMPU5 (0x1u << 21)
280#define PWM_IDR2_CMPU6 (0x1u << 22)
281#define PWM_IDR2_CMPU7 (0x1u << 23)
282/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
283#define PWM_IMR2_WRDY (0x1u << 0)
284#define PWM_IMR2_UNRE (0x1u << 3)
285#define PWM_IMR2_CMPM0 (0x1u << 8)
286#define PWM_IMR2_CMPM1 (0x1u << 9)
287#define PWM_IMR2_CMPM2 (0x1u << 10)
288#define PWM_IMR2_CMPM3 (0x1u << 11)
289#define PWM_IMR2_CMPM4 (0x1u << 12)
290#define PWM_IMR2_CMPM5 (0x1u << 13)
291#define PWM_IMR2_CMPM6 (0x1u << 14)
292#define PWM_IMR2_CMPM7 (0x1u << 15)
293#define PWM_IMR2_CMPU0 (0x1u << 16)
294#define PWM_IMR2_CMPU1 (0x1u << 17)
295#define PWM_IMR2_CMPU2 (0x1u << 18)
296#define PWM_IMR2_CMPU3 (0x1u << 19)
297#define PWM_IMR2_CMPU4 (0x1u << 20)
298#define PWM_IMR2_CMPU5 (0x1u << 21)
299#define PWM_IMR2_CMPU6 (0x1u << 22)
300#define PWM_IMR2_CMPU7 (0x1u << 23)
301/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
302#define PWM_ISR2_WRDY (0x1u << 0)
303#define PWM_ISR2_UNRE (0x1u << 3)
304#define PWM_ISR2_CMPM0 (0x1u << 8)
305#define PWM_ISR2_CMPM1 (0x1u << 9)
306#define PWM_ISR2_CMPM2 (0x1u << 10)
307#define PWM_ISR2_CMPM3 (0x1u << 11)
308#define PWM_ISR2_CMPM4 (0x1u << 12)
309#define PWM_ISR2_CMPM5 (0x1u << 13)
310#define PWM_ISR2_CMPM6 (0x1u << 14)
311#define PWM_ISR2_CMPM7 (0x1u << 15)
312#define PWM_ISR2_CMPU0 (0x1u << 16)
313#define PWM_ISR2_CMPU1 (0x1u << 17)
314#define PWM_ISR2_CMPU2 (0x1u << 18)
315#define PWM_ISR2_CMPU3 (0x1u << 19)
316#define PWM_ISR2_CMPU4 (0x1u << 20)
317#define PWM_ISR2_CMPU5 (0x1u << 21)
318#define PWM_ISR2_CMPU6 (0x1u << 22)
319#define PWM_ISR2_CMPU7 (0x1u << 23)
320/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
321#define PWM_OOV_OOVH0 (0x1u << 0)
322#define PWM_OOV_OOVH1 (0x1u << 1)
323#define PWM_OOV_OOVH2 (0x1u << 2)
324#define PWM_OOV_OOVH3 (0x1u << 3)
325#define PWM_OOV_OOVL0 (0x1u << 16)
326#define PWM_OOV_OOVL1 (0x1u << 17)
327#define PWM_OOV_OOVL2 (0x1u << 18)
328#define PWM_OOV_OOVL3 (0x1u << 19)
329/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
330#define PWM_OS_OSH0 (0x1u << 0)
331#define PWM_OS_OSH1 (0x1u << 1)
332#define PWM_OS_OSH2 (0x1u << 2)
333#define PWM_OS_OSH3 (0x1u << 3)
334#define PWM_OS_OSL0 (0x1u << 16)
335#define PWM_OS_OSL1 (0x1u << 17)
336#define PWM_OS_OSL2 (0x1u << 18)
337#define PWM_OS_OSL3 (0x1u << 19)
338/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
339#define PWM_OSS_OSSH0 (0x1u << 0)
340#define PWM_OSS_OSSH1 (0x1u << 1)
341#define PWM_OSS_OSSH2 (0x1u << 2)
342#define PWM_OSS_OSSH3 (0x1u << 3)
343#define PWM_OSS_OSSL0 (0x1u << 16)
344#define PWM_OSS_OSSL1 (0x1u << 17)
345#define PWM_OSS_OSSL2 (0x1u << 18)
346#define PWM_OSS_OSSL3 (0x1u << 19)
347/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
348#define PWM_OSC_OSCH0 (0x1u << 0)
349#define PWM_OSC_OSCH1 (0x1u << 1)
350#define PWM_OSC_OSCH2 (0x1u << 2)
351#define PWM_OSC_OSCH3 (0x1u << 3)
352#define PWM_OSC_OSCL0 (0x1u << 16)
353#define PWM_OSC_OSCL1 (0x1u << 17)
354#define PWM_OSC_OSCL2 (0x1u << 18)
355#define PWM_OSC_OSCL3 (0x1u << 19)
356/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
357#define PWM_OSSUPD_OSSUPH0 (0x1u << 0)
358#define PWM_OSSUPD_OSSUPH1 (0x1u << 1)
359#define PWM_OSSUPD_OSSUPH2 (0x1u << 2)
360#define PWM_OSSUPD_OSSUPH3 (0x1u << 3)
361#define PWM_OSSUPD_OSSUPL0 (0x1u << 16)
362#define PWM_OSSUPD_OSSUPL1 (0x1u << 17)
363#define PWM_OSSUPD_OSSUPL2 (0x1u << 18)
364#define PWM_OSSUPD_OSSUPL3 (0x1u << 19)
365/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
366#define PWM_OSCUPD_OSCUPH0 (0x1u << 0)
367#define PWM_OSCUPD_OSCUPH1 (0x1u << 1)
368#define PWM_OSCUPD_OSCUPH2 (0x1u << 2)
369#define PWM_OSCUPD_OSCUPH3 (0x1u << 3)
370#define PWM_OSCUPD_OSCUPL0 (0x1u << 16)
371#define PWM_OSCUPD_OSCUPL1 (0x1u << 17)
372#define PWM_OSCUPD_OSCUPL2 (0x1u << 18)
373#define PWM_OSCUPD_OSCUPL3 (0x1u << 19)
374/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
375#define PWM_FMR_FPOL_Pos 0
376#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos)
377#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
378#define PWM_FMR_FMOD_Pos 8
379#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos)
380#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
381#define PWM_FMR_FFIL_Pos 16
382#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos)
383#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
384/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
385#define PWM_FSR_FIV_Pos 0
386#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos)
387#define PWM_FSR_FS_Pos 8
388#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos)
389/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
390#define PWM_FCR_FCLR_Pos 0
391#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos)
392#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
393/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */
394#define PWM_FPV1_FPVH0 (0x1u << 0)
395#define PWM_FPV1_FPVH1 (0x1u << 1)
396#define PWM_FPV1_FPVH2 (0x1u << 2)
397#define PWM_FPV1_FPVH3 (0x1u << 3)
398#define PWM_FPV1_FPVL0 (0x1u << 16)
399#define PWM_FPV1_FPVL1 (0x1u << 17)
400#define PWM_FPV1_FPVL2 (0x1u << 18)
401#define PWM_FPV1_FPVL3 (0x1u << 19)
402/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
403#define PWM_FPE_FPE0_Pos 0
404#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos)
405#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
406#define PWM_FPE_FPE1_Pos 8
407#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos)
408#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
409#define PWM_FPE_FPE2_Pos 16
410#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos)
411#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
412#define PWM_FPE_FPE3_Pos 24
413#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos)
414#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
415/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
416#define PWM_ELMR_CSEL0 (0x1u << 0)
417#define PWM_ELMR_CSEL1 (0x1u << 1)
418#define PWM_ELMR_CSEL2 (0x1u << 2)
419#define PWM_ELMR_CSEL3 (0x1u << 3)
420#define PWM_ELMR_CSEL4 (0x1u << 4)
421#define PWM_ELMR_CSEL5 (0x1u << 5)
422#define PWM_ELMR_CSEL6 (0x1u << 6)
423#define PWM_ELMR_CSEL7 (0x1u << 7)
424/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */
425#define PWM_SSPR_SPRD_Pos 0
426#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos)
427#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos)))
428#define PWM_SSPR_SPRDM (0x1u << 24)
429/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */
430#define PWM_SSPUP_SPRDUP_Pos 0
431#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos)
432#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos)))
433/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
434#define PWM_SMMR_GCEN0 (0x1u << 0)
435#define PWM_SMMR_GCEN1 (0x1u << 1)
436#define PWM_SMMR_DOWN0 (0x1u << 16)
437#define PWM_SMMR_DOWN1 (0x1u << 17)
438/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */
439#define PWM_FPV2_FPZH0 (0x1u << 0)
440#define PWM_FPV2_FPZH1 (0x1u << 1)
441#define PWM_FPV2_FPZH2 (0x1u << 2)
442#define PWM_FPV2_FPZH3 (0x1u << 3)
443#define PWM_FPV2_FPZL0 (0x1u << 16)
444#define PWM_FPV2_FPZL1 (0x1u << 17)
445#define PWM_FPV2_FPZL2 (0x1u << 18)
446#define PWM_FPV2_FPZL3 (0x1u << 19)
447/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */
448#define PWM_WPCR_WPCMD_Pos 0
449#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos)
450#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
451#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0)
452#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0)
453#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0)
454#define PWM_WPCR_WPRG0 (0x1u << 2)
455#define PWM_WPCR_WPRG1 (0x1u << 3)
456#define PWM_WPCR_WPRG2 (0x1u << 4)
457#define PWM_WPCR_WPRG3 (0x1u << 5)
458#define PWM_WPCR_WPRG4 (0x1u << 6)
459#define PWM_WPCR_WPRG5 (0x1u << 7)
460#define PWM_WPCR_WPKEY_Pos 8
461#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos)
462#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
463#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8)
464/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */
465#define PWM_WPSR_WPSWS0 (0x1u << 0)
466#define PWM_WPSR_WPSWS1 (0x1u << 1)
467#define PWM_WPSR_WPSWS2 (0x1u << 2)
468#define PWM_WPSR_WPSWS3 (0x1u << 3)
469#define PWM_WPSR_WPSWS4 (0x1u << 4)
470#define PWM_WPSR_WPSWS5 (0x1u << 5)
471#define PWM_WPSR_WPVS (0x1u << 7)
472#define PWM_WPSR_WPHWS0 (0x1u << 8)
473#define PWM_WPSR_WPHWS1 (0x1u << 9)
474#define PWM_WPSR_WPHWS2 (0x1u << 10)
475#define PWM_WPSR_WPHWS3 (0x1u << 11)
476#define PWM_WPSR_WPHWS4 (0x1u << 12)
477#define PWM_WPSR_WPHWS5 (0x1u << 13)
478#define PWM_WPSR_WPVSRC_Pos 16
479#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos)
480/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
481#define PWM_CMPV_CV_Pos 0
482#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos)
483#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
484#define PWM_CMPV_CVM (0x1u << 24)
485/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
486#define PWM_CMPVUPD_CVUPD_Pos 0
487#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos)
488#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
489#define PWM_CMPVUPD_CVMUPD (0x1u << 24)
490/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
491#define PWM_CMPM_CEN (0x1u << 0)
492#define PWM_CMPM_CTR_Pos 4
493#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos)
494#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
495#define PWM_CMPM_CPR_Pos 8
496#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos)
497#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
498#define PWM_CMPM_CPRCNT_Pos 12
499#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos)
500#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
501#define PWM_CMPM_CUPR_Pos 16
502#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos)
503#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
504#define PWM_CMPM_CUPRCNT_Pos 20
505#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos)
506#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
507/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
508#define PWM_CMPMUPD_CENUPD (0x1u << 0)
509#define PWM_CMPMUPD_CTRUPD_Pos 4
510#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos)
511#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
512#define PWM_CMPMUPD_CPRUPD_Pos 8
513#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos)
514#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
515#define PWM_CMPMUPD_CUPRUPD_Pos 16
516#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos)
517#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
518/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
519#define PWM_CMR_CPRE_Pos 0
520#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos)
521#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos)))
522#define PWM_CMR_CPRE_MCK (0x0u << 0)
523#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0)
524#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0)
525#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0)
526#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0)
527#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0)
528#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0)
529#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0)
530#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0)
531#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0)
532#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0)
533#define PWM_CMR_CPRE_CLKA (0xBu << 0)
534#define PWM_CMR_CPRE_CLKB (0xCu << 0)
535#define PWM_CMR_CALG (0x1u << 8)
536#define PWM_CMR_CPOL (0x1u << 9)
537#define PWM_CMR_CES (0x1u << 10)
538#define PWM_CMR_UPDS (0x1u << 11)
539#define PWM_CMR_DPOLI (0x1u << 12)
540#define PWM_CMR_TCTS (0x1u << 13)
541#define PWM_CMR_DTE (0x1u << 16)
542#define PWM_CMR_DTHI (0x1u << 17)
543#define PWM_CMR_DTLI (0x1u << 18)
544#define PWM_CMR_PPM (0x1u << 19)
545/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
546#define PWM_CDTY_CDTY_Pos 0
547#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos)
548#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
549/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
550#define PWM_CDTYUPD_CDTYUPD_Pos 0
551#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos)
552#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
553/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
554#define PWM_CPRD_CPRD_Pos 0
555#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos)
556#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
557/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
558#define PWM_CPRDUPD_CPRDUPD_Pos 0
559#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos)
560#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
561/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
562#define PWM_CCNT_CNT_Pos 0
563#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos)
564/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
565#define PWM_DT_DTH_Pos 0
566#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos)
567#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
568#define PWM_DT_DTL_Pos 16
569#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos)
570#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
571/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
572#define PWM_DTUPD_DTHUPD_Pos 0
573#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos)
574#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
575#define PWM_DTUPD_DTLUPD_Pos 16
576#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos)
577#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
578/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */
579#define PWM_CMUPD0_CPOLUP (0x1u << 9)
580#define PWM_CMUPD0_CPOLINVUP (0x1u << 13)
581/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */
582#define PWM_CMUPD1_CPOLUP (0x1u << 9)
583#define PWM_CMUPD1_CPOLINVUP (0x1u << 13)
584/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */
585#define PWM_ETRG1_MAXCNT_Pos 0
586#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos)
587#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos)))
588#define PWM_ETRG1_TRGMODE_Pos 24
589#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos)
590#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos)))
591#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24)
592#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24)
593#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24)
594#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24)
595#define PWM_ETRG1_TRGEDGE (0x1u << 28)
596#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28)
597#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28)
598#define PWM_ETRG1_TRGFILT (0x1u << 29)
599#define PWM_ETRG1_TRGSRC (0x1u << 30)
600#define PWM_ETRG1_RFEN (0x1u << 31)
601/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */
602#define PWM_LEBR1_LEBDELAY_Pos 0
603#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos)
604#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos)))
605#define PWM_LEBR1_PWMLFEN (0x1u << 16)
606#define PWM_LEBR1_PWMLREN (0x1u << 17)
607#define PWM_LEBR1_PWMHFEN (0x1u << 18)
608#define PWM_LEBR1_PWMHREN (0x1u << 19)
609/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */
610#define PWM_CMUPD2_CPOLUP (0x1u << 9)
611#define PWM_CMUPD2_CPOLINVUP (0x1u << 13)
612/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */
613#define PWM_ETRG2_MAXCNT_Pos 0
614#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos)
615#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos)))
616#define PWM_ETRG2_TRGMODE_Pos 24
617#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos)
618#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos)))
619#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24)
620#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24)
621#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24)
622#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24)
623#define PWM_ETRG2_TRGEDGE (0x1u << 28)
624#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28)
625#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28)
626#define PWM_ETRG2_TRGFILT (0x1u << 29)
627#define PWM_ETRG2_TRGSRC (0x1u << 30)
628#define PWM_ETRG2_RFEN (0x1u << 31)
629/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */
630#define PWM_LEBR2_LEBDELAY_Pos 0
631#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos)
632#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos)))
633#define PWM_LEBR2_PWMLFEN (0x1u << 16)
634#define PWM_LEBR2_PWMLREN (0x1u << 17)
635#define PWM_LEBR2_PWMHFEN (0x1u << 18)
636#define PWM_LEBR2_PWMHREN (0x1u << 19)
637/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */
638#define PWM_CMUPD3_CPOLUP (0x1u << 9)
639#define PWM_CMUPD3_CPOLINVUP (0x1u << 13)
642
643
644#endif /* _SAME70_PWM_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
PwmCh_num
PwmCh_num hardware registers.
Definition: component_pwm.h:41
PwmCh_num::PWM_DTUPD
__O uint32_t PWM_DTUPD
(PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register
Definition: component_pwm.h:49
PwmCh_num::PWM_CPRDUPD
__O uint32_t PWM_CPRDUPD
(PwmCh_num Offset: 0x10) PWM Channel Period Update Register
Definition: component_pwm.h:46
PwmCh_num::PWM_CCNT
__I uint32_t PWM_CCNT
(PwmCh_num Offset: 0x14) PWM Channel Counter Register
Definition: component_pwm.h:47
PwmCh_num::PWM_CMR
__IO uint32_t PWM_CMR
(PwmCh_num Offset: 0x0) PWM Channel Mode Register
Definition: component_pwm.h:42
PwmCh_num::PWM_CDTYUPD
__O uint32_t PWM_CDTYUPD
(PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register
Definition: component_pwm.h:44
PwmCh_num::PWM_CPRD
__IO uint32_t PWM_CPRD
(PwmCh_num Offset: 0xC) PWM Channel Period Register
Definition: component_pwm.h:45
PwmCh_num::PWM_CDTY
__IO uint32_t PWM_CDTY
(PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register
Definition: component_pwm.h:43
PwmCh_num::PWM_DT
__IO uint32_t PWM_DT
(PwmCh_num Offset: 0x18) PWM Channel Dead Time Register
Definition: component_pwm.h:48
PwmCmp
PwmCmp hardware registers.
Definition: component_pwm.h:52
PwmCmp::PWM_CMPM
__IO uint32_t PWM_CMPM
(PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register
Definition: component_pwm.h:55
PwmCmp::PWM_CMPV
__IO uint32_t PWM_CMPV
(PwmCmp Offset: 0x0) PWM Comparison 0 Value Register
Definition: component_pwm.h:53
PwmCmp::PWM_CMPMUPD
__O uint32_t PWM_CMPMUPD
(PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register
Definition: component_pwm.h:56
PwmCmp::PWM_CMPVUPD
__O uint32_t PWM_CMPVUPD
(PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register
Definition: component_pwm.h:54
Pwm
Definition: component_pwm.h:61
Pwm::PWM_FMR
__IO uint32_t PWM_FMR
(Pwm Offset: 0x5C) PWM Fault Mode Register
Definition: component_pwm.h:85
Pwm::PWM_FPV2
__IO uint32_t PWM_FPV2
(Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register
Definition: component_pwm.h:98
Pwm::PWM_IMR1
__I uint32_t PWM_IMR1
(Pwm Offset: 0x18) PWM Interrupt Mask Register 1
Definition: component_pwm.h:68
Pwm::PWM_IMR2
__I uint32_t PWM_IMR2
(Pwm Offset: 0x3C) PWM Interrupt Mask Register 2
Definition: component_pwm.h:77
Pwm::PWM_OSCUPD
__O uint32_t PWM_OSCUPD
(Pwm Offset: 0x58) PWM Output Selection Clear Update Register
Definition: component_pwm.h:84
Pwm::PWM_WPCR
__O uint32_t PWM_WPCR
(Pwm Offset: 0xE4) PWM Write Protection Control Register
Definition: component_pwm.h:100
Pwm::PWM_CMUPD2
__O uint32_t PWM_CMUPD2
(Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2)
Definition: component_pwm.h:114
Pwm::PWM_CMUPD1
__O uint32_t PWM_CMUPD1
(Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1)
Definition: component_pwm.h:109
Pwm::PWM_SCM
__IO uint32_t PWM_SCM
(Pwm Offset: 0x20) PWM Sync Channels Mode Register
Definition: component_pwm.h:70
Pwm::PWM_FPV1
__IO uint32_t PWM_FPV1
(Pwm Offset: 0x68) PWM Fault Protection Value Register 1
Definition: component_pwm.h:88
Pwm::PWM_FSR
__I uint32_t PWM_FSR
(Pwm Offset: 0x60) PWM Fault Status Register
Definition: component_pwm.h:86
Pwm::PWM_ETRG2
__IO uint32_t PWM_ETRG2
(Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2)
Definition: component_pwm.h:116
Pwm::PWM_SCUC
__IO uint32_t PWM_SCUC
(Pwm Offset: 0x28) PWM Sync Channels Update Control Register
Definition: component_pwm.h:72
Pwm::PWM_IDR2
__O uint32_t PWM_IDR2
(Pwm Offset: 0x38) PWM Interrupt Disable Register 2
Definition: component_pwm.h:76
Pwm::PWM_LEBR2
__IO uint32_t PWM_LEBR2
(Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2)
Definition: component_pwm.h:117
Pwm::PWM_SR
__I uint32_t PWM_SR
(Pwm Offset: 0x0C) PWM Status Register
Definition: component_pwm.h:65
Pwm::PWM_LEBR1
__IO uint32_t PWM_LEBR1
(Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1)
Definition: component_pwm.h:112
Pwm::PWM_SSPR
__IO uint32_t PWM_SSPR
(Pwm Offset: 0xA0) PWM Spread Spectrum Register
Definition: component_pwm.h:93
Pwm::PWM_OSSUPD
__O uint32_t PWM_OSSUPD
(Pwm Offset: 0x54) PWM Output Selection Set Update Register
Definition: component_pwm.h:83
Pwm::PWM_SCUPUPD
__O uint32_t PWM_SCUPUPD
(Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register
Definition: component_pwm.h:74
Pwm::PWM_ISR2
__I uint32_t PWM_ISR2
(Pwm Offset: 0x40) PWM Interrupt Status Register 2
Definition: component_pwm.h:78
Pwm::PWM_FPE
__IO uint32_t PWM_FPE
(Pwm Offset: 0x6C) PWM Fault Protection Enable Register
Definition: component_pwm.h:89
Pwm::PWM_CMUPD3
__O uint32_t PWM_CMUPD3
(Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3)
Definition: component_pwm.h:119
Pwm::PWM_CMUPD0
__O uint32_t PWM_CMUPD0
(Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0)
Definition: component_pwm.h:107
Pwm::PWM_SSPUP
__O uint32_t PWM_SSPUP
(Pwm Offset: 0xA4) PWM Spread Spectrum Update Register
Definition: component_pwm.h:94
Pwm::PWM_IER1
__O uint32_t PWM_IER1
(Pwm Offset: 0x10) PWM Interrupt Enable Register 1
Definition: component_pwm.h:66
Pwm::PWM_IER2
__O uint32_t PWM_IER2
(Pwm Offset: 0x34) PWM Interrupt Enable Register 2
Definition: component_pwm.h:75
Pwm::PWM_DIS
__O uint32_t PWM_DIS
(Pwm Offset: 0x08) PWM Disable Register
Definition: component_pwm.h:64
Pwm::PWM_ETRG1
__IO uint32_t PWM_ETRG1
(Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1)
Definition: component_pwm.h:111
Pwm::PWM_OSS
__O uint32_t PWM_OSS
(Pwm Offset: 0x4C) PWM Output Selection Set Register
Definition: component_pwm.h:81
Pwm::PWM_DMAR
__O uint32_t PWM_DMAR
(Pwm Offset: 0x24) PWM DMA Register
Definition: component_pwm.h:71
Pwm::PWM_OOV
__IO uint32_t PWM_OOV
(Pwm Offset: 0x44) PWM Output Override Value Register
Definition: component_pwm.h:79
Pwm::PWM_WPSR
__I uint32_t PWM_WPSR
(Pwm Offset: 0xE8) PWM Write Protection Status Register
Definition: component_pwm.h:101
Pwm::PWM_FCR
__O uint32_t PWM_FCR
(Pwm Offset: 0x64) PWM Fault Clear Register
Definition: component_pwm.h:87
Pwm::PWM_ISR1
__I uint32_t PWM_ISR1
(Pwm Offset: 0x1C) PWM Interrupt Status Register 1
Definition: component_pwm.h:69
Pwm::PWM_IDR1
__O uint32_t PWM_IDR1
(Pwm Offset: 0x14) PWM Interrupt Disable Register 1
Definition: component_pwm.h:67
Pwm::PWM_SMMR
__IO uint32_t PWM_SMMR
(Pwm Offset: 0xB0) PWM Stepper Motor Mode Register
Definition: component_pwm.h:96
Pwm::PWM_OS
__IO uint32_t PWM_OS
(Pwm Offset: 0x48) PWM Output Selection Register
Definition: component_pwm.h:80
Pwm::PWM_CLK
__IO uint32_t PWM_CLK
(Pwm Offset: 0x00) PWM Clock Register
Definition: component_pwm.h:62
Pwm::PWM_SCUP
__IO uint32_t PWM_SCUP
(Pwm Offset: 0x2C) PWM Sync Channels Update Period Register
Definition: component_pwm.h:73
Pwm::PWM_ENA
__O uint32_t PWM_ENA
(Pwm Offset: 0x04) PWM Enable Register
Definition: component_pwm.h:63
Pwm::PWM_OSC
__O uint32_t PWM_OSC
(Pwm Offset: 0x50) PWM Output Selection Clear Register
Definition: component_pwm.h:82