RTEMS: bsps/arm/csb337/include/sed1356_16bit.h File Reference

| RTEMS 5.4-rc2

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Macros | Variables
sed1356_16bit.h File Reference
Board Support Packages » ARM » CSB337

SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637) 16-Bit access mode. More...

`#include "bits.h"`

Go to the source code of this file.

## Macros
#define | SED1356_REG_REV_and_MISC SED_REG16(0x00)
#define | SED1356_REG_GPIO_CFG SED_REG16(0x04)
#define | SED1356_REG_GPIO_CTL SED_REG16(0x08)
#define | SED1356_REG_MD_CFG_RD_LO_and_HI SED_REG16(0x0c)
#define | SED1356_REG_MCLK_CFG SED_REG16(0x10)
#define | SED1356_REG_LCD_PCLK_CFG SED_REG16(0x14)
#define | SED1356_REG_CRT_PCLK_CFG SED_REG16(0x18)
#define | SED1356_REG_MEDIA_PCLK_CFG SED_REG16(0x1c)
#define | SED1356_REG_WAIT_STATE SED_REG16(0x1e)
#define | SED1356_REG_MEM_CFG_and_REF_RATE SED_REG16(0x20)
#define | SED1356_REG_MEM_TMG0_and_1 SED_REG16(0x2a)
#define | SED1356_REG_PANEL_TYPE_and_MOD_RATE SED_REG16(0x30)
#define | SED1356_REG_LCD_HOR_DISP SED_REG16(0x32)
#define | SED1356_REG_LCD_HOR_NONDISP_and_START SED_REG16(0x34)
#define | SED1356_REG_LCD_HOR_PULSE SED_REG16(0x36)
#define | SED1356_REG_LCD_VER_DISP_HT_LO_and_HI SED_REG16(0x38)
#define | SED1356_REG_LCD_VER_NONDISP_and_START SED_REG16(0x3a)
#define | SED1356_REG_LCD_VER_PULSE SED_REG16(0x3c)
#define | SED1356_REG_LCD_DISP_MODE_and_MISC SED_REG16(0x40)
#define | SED1356_REG_LCD_DISP_START_LO_and_MID SED_REG16(0x42)
#define | SED1356_REG_LCD_DISP_START_HI SED_REG16(0x44)
#define | SED1356_REG_LCD_ADD_OFFSET_LO_and_HI SED_REG16(0x46)
#define | SED1356_REG_LCD_PIXEL_PAN SED_REG16(0x48)
#define | SED1356_REG_LCD_FIFO_THRESH_LO_and_HI SED_REG16(0x4a)
#define | SED1356_REG_CRT_HOR_DISP SED_REG16(0x50)
#define | SED1356_REG_CRT_HOR_NONDISP_and_START SED_REG16(0x52)
#define | SED1356_REG_CRT_HOR_PULSE SED_REG16(0x54)
#define | SED1356_REG_CRT_VER_DISP_HT_LO_and_HI SED_REG16(0x56)
#define | SED1356_REG_CRT_VER_NONDISP_and_START SED_REG16(0x58)
#define | SED1356_REG_CRT_VER_PULSE_and_OUT_CTL SED_REG16(0x5a)
#define | SED1356_REG_CRT_DISP_MODE SED_REG16(0x60)
#define | SED1356_REG_CRT_DISP_START_LO_and_MID SED_REG16(0x62)
#define | SED1356_REG_CRT_DISP_START_HI SED_REG16(0x64)
#define | SED1356_REG_CRT_ADD_OFFSET_LO_and_HI SED_REG16(0x66)
#define | SED1356_REG_CRT_PIXEL_PAN SED_REG16(0x68)
#define | SED1356_REG_CRT_FIFO_THRESH_LO_and_HI SED_REG16(0x6a)
#define | SED1356_REG_LCD_CURSOR_CTL_and_START_ADD SED_REG16(0x70)
#define | SED1356_REG_LCD_CURSOR_X_POS_LO_and_HI SED_REG16(0x72)
#define | SED1356_REG_LCD_CURSOR_Y_POS_LO_and_HI SED_REG16(0x74)
#define | SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x76)
#define | SED1356_REG_LCD_CURSOR_RED_CLR_0 SED_REG16(0x78)
#define | SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x7a)
#define | SED1356_REG_LCD_CURSOR_RED_CLR_1 SED_REG16(0x7c)
#define | SED1356_REG_LCD_CURSOR_FIFO_THRESH SED_REG16(0x7e)
#define | SED1356_REG_CRT_CURSOR_CTL_and_START_ADD SED_REG16(0x80)
#define | SED1356_REG_CRT_CURSOR_X_POS_LO_and_HI SED_REG16(0x82)
#define | SED1356_REG_CRT_CURSOR_Y_POS_LO_and_HI SED_REG16(0x84)
#define | SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x86)
#define | SED1356_REG_CRT_CURSOR_RED_CLR_0 SED_REG16(0x88)
#define | SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x8a)
#define | SED1356_REG_CRT_CURSOR_RED_CLR_1 SED_REG16(0x8c)
#define | SED1356_REG_CRT_CURSOR_FIFO_THRESH SED_REG16(0x8e)
#define | SED1356_REG_BLT_CTL_0_and_1 SED_REG16(0x100)
#define | SED1356_REG_BLT_ROP_CODE_and_BLT_OP SED_REG16(0x102)
#define | SED1356_REG_BLT_SRC_START_LO_and_MID SED_REG16(0x104)
#define | SED1356_REG_BLT_SRC_START_HI SED_REG16(0x106)
#define | SED1356_REG_BLT_DEST_START_LO_and_MID SED_REG16(0x108)
#define | SED1356_REG_BLT_DEST_START_HI SED_REG16(0x10a)
#define | SED1356_REG_BLT_ADD_OFFSET_LO_and_HI SED_REG16(0x10c)
#define | SED1356_REG_BLT_WID_LO_and_HI SED_REG16(0x110)
#define | SED1356_REG_BLT_HGT_LO_and_HI SED_REG16(0x112)
#define | SED1356_REG_BLT_BG_CLR_LO_and_HI SED_REG16(0x114)
#define | SED1356_REG_BLT_FG_CLR_LO_and_HI SED_REG16(0x118)
#define | SED1356_REG_LUT_MODE SED_REG16(0x1e0)
#define | SED1356_REG_LUT_ADD SED_REG16(0x1e2)
#define | SED1356_REG_LUT_DATA SED_REG16(0x1e4)
#define | SED1356_REG_PWR_CFG_and_STAT SED_REG16(0x1f0)
#define | SED1356_REG_WATCHDOG_CTL SED_REG16(0x1f4)
#define | SED1356_REG_DISP_MODE SED_REG16(0x1fc)
#define | SED1356_REV_ID_MASK 0xfc /* ID bits - masks off the rev bits */
#define | SED1356_REV_ID_1356 BIT4
#define | SED1356_REV_ID_1355 BIT3
#define | SED1356_MISC_HOST_DIS BIT7 << 8 /* 0 = enable host access, 1 = disable */
#define | SED1356_GPIO_GPIO3 BIT3 /* 0 = input, 1 = output, if configured as GPIO */
#define | SED1356_GPIO_GPIO2 BIT2
#define | SED1356_GPIO_GPIO1 BIT1
#define | SED1356_MCLK_DIV2 BIT4
#define | SED1356_MCLK_SRC_BCLK BIT0
#define | SED1356_MCLK_SRC_CLKI 0x00
#define | SED1356_PCLK_X2 BIT7 /* SED1356_REG_CRT_PCLK_CFG only */
#define | SED1356_PCLK_DIV1 0x00 << 4
#define | SED1356_PCLK_DIV2 0x01 << 4
#define | SED1356_PCLK_DIV3 0x02 << 4
#define | SED1356_PCLK_DIV4 0x03 << 4
#define | SED1356_PCLK_SRC_CLKI 0x00
#define | SED1356_PCLK_SRC_BCLK 0x01
#define | SED1356_PCLK_SRC_CLKI2 0x02
#define | SED1356_PCLK_SRC_MCLK 0x03
#define | SED1356_MEM_CFG_2CAS_EDO 0x00
#define | SED1356_MEM_CFG_2CAS_FPM 0x01
#define | SED1356_MEM_CFG_2WE_EDO 0x02
#define | SED1356_MEM_CFG_2WE_FPM 0x03
#define | SED1356_MEM_CFG_MASK 0x03
#define | SED1356_REF_TYPE_CBR 0x00 << 6 << 8
#define | SED1356_REF_TYPE_SELF 0x01 << 6 << 8
#define | SED1356_REF_TYPE_NONE 0x02 << 6 << 8
#define | SED1356_REF_TYPE_MASK 0x03 << 6 << 8
#define | SED1356_REF_RATE_64 0x00 << 0 << 8 /* MCLK / 64 */
#define | SED1356_REF_RATE_128 0x01 << 0 << 8 /* MCLK / 128 */
#define | SED1356_REF_RATE_256 0x02 << 0 << 8 /* MCLK / 256 */
#define | SED1356_REF_RATE_512 0x03 << 0 << 8 /* MCLK / 512 */
#define | SED1356_REF_RATE_1024 0x04 << 0 << 8 /* MCLK / 1024 */
#define | SED1356_REF_RATE_2048 0x05 << 0 << 8 /* MCLK / 2048 */
#define | SED1356_REF_RATE_4096 0x06 << 0 << 8 /* MCLK / 4096 */
#define | SED1356_REF_RATE_8192 0x07 << 0 << 8 /* MCLK / 8192 */
#define | SED1356_REF_RATE_MASK 0x07 << 0 << 8 /* MCLK / 8192 */
#define | SED1356_MEM_TMG0_EDO50_MCLK40 0x01
#define | SED1356_MEM_TMG0_EDO50_MCLK33 0x01
#define | SED1356_MEM_TMG0_EDO60_MCLK33 0x01
#define | SED1356_MEM_TMG0_EDO50_MCLK30 0x12
#define | SED1356_MEM_TMG0_EDO60_MCLK30 0x01
#define | SED1356_MEM_TMG0_EDO70_MCLK30 0x00
#define | SED1356_MEM_TMG0_EDO50_MCLK25 0x12
#define | SED1356_MEM_TMG0_EDO60_MCLK25 0x12
#define | SED1356_MEM_TMG0_EDO70_MCLK25 0x01
#define | SED1356_MEM_TMG0_EDO80_MCLK25 0x00
#define | SED1356_MEM_TMG0_EDO50_MCLK20 0x12
#define | SED1356_MEM_TMG0_EDO60_MCLK20 0x12
#define | SED1356_MEM_TMG0_EDO70_MCLK20 0x12
#define | SED1356_MEM_TMG0_EDO80_MCLK20 0x01
#define | SED1356_MEM_TMG0_FPM50_MCLK25 0x12
#define | SED1356_MEM_TMG0_FPM60_MCLK25 0x01
#define | SED1356_MEM_TMG0_FPM50_MCLK20 0x12
#define | SED1356_MEM_TMG0_FPM60_MCLK20 0x12
#define | SED1356_MEM_TMG0_FPM70_MCLK20 0x11
#define | SED1356_MEM_TMG0_FPM80_MCLK20 0x01
#define | SED1356_MEM_TMG1_EDO50_MCLK40 0x01 << 8
#define | SED1356_MEM_TMG1_EDO50_MCLK33 0x01 << 8
#define | SED1356_MEM_TMG1_EDO60_MCLK33 0x01 << 8
#define | SED1356_MEM_TMG1_EDO50_MCLK30 0x02 << 8
#define | SED1356_MEM_TMG1_EDO60_MCLK30 0x01 << 8
#define | SED1356_MEM_TMG1_EDO70_MCLK30 0x00 << 8
#define | SED1356_MEM_TMG1_EDO50_MCLK25 0x02 << 8
#define | SED1356_MEM_TMG1_EDO60_MCLK25 0x02 << 8
#define | SED1356_MEM_TMG1_EDO70_MCLK25 0x01 << 8
#define | SED1356_MEM_TMG1_EDO80_MCLK25 0x01 << 8
#define | SED1356_MEM_TMG1_EDO50_MCLK20 0x02 << 8
#define | SED1356_MEM_TMG1_EDO60_MCLK20 0x02 << 8
#define | SED1356_MEM_TMG1_EDO70_MCLK20 0x02 << 8
#define | SED1356_MEM_TMG1_EDO80_MCLK20 0x01 << 8
#define | SED1356_MEM_TMG1_FPM50_MCLK25 0x02 << 8
#define | SED1356_MEM_TMG1_FPM60_MCLK25 0x01 << 8
#define | SED1356_MEM_TMG1_FPM50_MCLK20 0x02 << 8
#define | SED1356_MEM_TMG1_FPM60_MCLK20 0x02 << 8
#define | SED1356_MEM_TMG1_FPM70_MCLK20 0x02 << 8
#define | SED1356_MEM_TMG1_FPM80_MCLK20 0x01 << 8
#define | SED1356_PANEL_TYPE_EL BIT7
#define | SED1356_PANEL_TYPE_4_9 (0x00 << 4) /* Passive 4-Bit, TFT 9-Bit */
#define | SED1356_PANEL_TYPE_8_12 (0x01 << 4) /* Passive 8-Bit, TFT 12-Bit */
#define | SED1356_PANEL_TYPE_16 (0x02 << 4) /* Passive 16-Bit, or TFT 18-Bit */
#define | SED1356_PANEL_TYPE_MASK (0x03 << 4)
#define | SED1356_PANEL_TYPE_FMT BIT3 /* 0 = Passive Format 1, 1 = Passive Format 2 */
#define | SED1356_PANEL_TYPE_CLR BIT2 /* 0 = Passive Mono, 1 = Passive Color */
#define | SED1356_PANEL_TYPE_DUAL BIT1 /* 0 = Passive Single, 1 = Passive Dual */
#define | SED1356_PANEL_TYPE_TFT BIT0 /* 0 = Passive, 1 = TFT (DUAL, FMT & CLR are don't cares) */
#define | SED1356_PULSE_POL_HIGH BIT7 /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */
#define | SED1356_PULSE_POL_LOW 0x00 /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */
#define | SED1356_PULSE_WID(_x_) (_x_ & 0x0f) /* Pulse Width in Pixels */
#define | SED1356_LCD_DISP_BLANK BIT7 /* 1 = Blank LCD Display */
#define | SED1356_LCD_DISP_SWIV_NORM (0x00 << 4) /* Used with SED1356_REG_DISP_MODE Bit 6 */
#define | SED1356_LCD_DISP_SWIV_90 (0x00 << 4)
#define | SED1356_LCD_DISP_SWIV_180 (0x01 << 4)
#define | SED1356_LCD_DISP_SWIV_270 (0x01 << 4)
#define | SED1356_LCD_DISP_SWIV_MASK (0x01 << 4)
#define | SED1356_LCD_DISP_16BPP 0x05 /* Bit Per Pixel Selection */
#define | SED1356_LCD_DISP_15BPP 0x04
#define | SED1356_LCD_DISP_8BPP 0x03
#define | SED1356_LCD_DISP_4BPP 0x02
#define | SED1356_LCD_DISP_BPP_MASK 0x07
#define | SED1356_LCD_MISC_DITH BIT1 << 8 /* 1 = Dither Disable, Passive Panel Only */
#define | SED1356_LCD_MISC_DUAL BIT0 << 8 /* 1 = Dual Panel Disable, Passive Panel Only */
#define | SED1356_CRT_OUT_CHROM BIT5 << 8 /* 1 = TV Chrominance Filter Enable */
#define | SED1356_CRT_OUT_LUM BIT4 << 8 /* 1 = TV Luminance Filter Enable */
#define | SED1356_CRT_OUT_DAC_LVL BIT3 << 8 /* 1 = 4.6ma IREF, 0 = 9.2 IREF */
#define | SED1356_CRT_OUT_SVIDEO BIT1 << 8 /* 1 = S-Video Output, 0 = Composite Video Output */
#define | SED1356_CRT_OUT_PAL BIT0 << 8 /* 1 = PAL Format Output, 0 = NTSC Format Output */
#define | SED1356_CRT_DISP_BLANK BIT7 /* 1 = Blank CRT Display */
#define | SED1356_CRT_DISP_16BPP 0x05 /* Bit Per Pixel Selection */
#define | SED1356_CRT_DISP_15BPP 0x04
#define | SED1356_CRT_DISP_8BPP 0x03
#define | SED1356_CRT_DISP_4BPP 0x02
#define | SED1356_CRT_DISP_BPP_MASK 0x07
#define | SED1356_DISP_SWIV_NORM (0x00 << 6) /* Used with SED1356_LCD_DISP_MODE Bit 4 */
#define | SED1356_DISP_SWIV_90 (0x01 << 6)
#define | SED1356_DISP_SWIV_180 (0x00 << 6)
#define | SED1356_DISP_SWIV_270 (0x01 << 6)
#define | SED1356_DISP_MODE_OFF 0x00 /* All Displays Off */
#define | SED1356_DISP_MODE_LCD 0x01 /* LCD Only */
#define | SED1356_DISP_MODE_CRT 0x02 /* CRT Only */
#define | SED1356_DISP_MODE_LCD_CRT 0x03 /* Simultaneous LCD and CRT */
#define | SED1356_DISP_MODE_TV 0x04 /* TV Only, Flicker Filter Off */
#define | SED1356_DISP_MODE_TV_LCD 0x05 /* Simultaneous LCD and TV, Flicker Filter Off */
#define | SED1356_DISP_MODE_TV_FLICK 0x06 /* TV Only, Flicker Filter On */
#define | SED1356_DISP_MODE_TV_LCD_FLICK 0x07 /* Simultaneous LCD and TV, Flicker Filter On */
#define | SED1356_PWR_PCLK BIT1 /* SED1356_REG_PWR_STAT only */
#define | SED1356_PWR_MCLK BIT0
#define | SED1356_VER_NONDISP BIT7 /* vertical retrace status 1 = in retrace */
#define | BYTES_PER_PIXEL 2
#define | RED_SUBPIXEL(n) ((n & 0x1f) << 11)
#define | GREEN_SUBPIXEL(n) ((n & 0x1f) << 5)
#define | BLUE_SUBPIXEL(n) ((n & 0x1f) << 0)
#define | BLUE (0x14 << 0)
#define | GREEN (0x14 << 6)
#define | RED (0x14 << 11)
#define | HALF_BLUE (0x0a << 0)
#define | HALF_GREEN (0x0a << 6)
#define | HALF_RED (0x0a << 11)
#define | BRT_BLUE (0x1e << 0)
#define | BRT_GREEN (0x1e << 6)
#define | BRT_RED (0x1e << 11)
#define | LU_BLACK 0
#define | LU_BLUE (BLUE)
#define | LU_GREEN (GREEN)
#define | LU_CYAN (GREEN | BLUE)
#define | LU_RED (RED)
#define | LU_VIOLET (RED | BLUE)
#define | LU_YELLOW (RED | GREEN)
#define | LU_WHITE (RED | GREEN | BLUE)
#define | LU_GREY (HALF_RED | HALF_GREEN | HALF_BLUE)
#define | LU_BRT_BLUE (HALF_RED | HALF_GREEN | BRT_BLUE)
#define | LU_BRT_GREEN (HALF_RED | BRT_GREEN | HALF_BLUE)
#define | LU_BRT_CYAN (HALF_RED | BRT_GREEN | BRT_BLUE)
#define | LU_BRT_RED (BRT_RED | HALF_GREEN | HALF_BLUE)
#define | LU_BRT_VIOLET (BRT_RED | HALF_GREEN | BRT_BLUE)
#define | LU_BRT_YELLOW (BRT_RED | BRT_GREEN | HALF_BLUE)
#define | LU_BRT_WHITE (BRT_RED | BRT_GREEN | BRT_BLUE)
#define | SED_BG_DEF 1
#define | SED_FG_DEF 14
#define | TOP 0
#define | BOTTOM (PIXELS_PER_COL-1)
#define | LEFT 0
#define | RIGHT (PIXELS_PER_ROW-1)
#define | CENTER_X (PIXELS_PER_ROW/2)
#define | CENTER_Y (PIXELS_PER_COL/2)
#define | SED_HOR_PULSE_WIDTH_CRT 0x07 /* Horizontal Pulse Width Register = (Thp/8) - 1 */
#define | SED_HOR_PULSE_START_CRT 0x02 /* Horizontal Pulse Start Position Register = ((Thfp + 2)/8) - 1 */
#define | SED_HOR_NONDISP_CRT 0x17 /* Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1 */
#define | SED_VER_PULSE_WIDTH_CRT 0x02
#define | SED_VER_PULSE_START_CRT 0x08
#define | SED_VER_NONDISP_CRT 0x27

## Variables
long | PIXELS_PER_ROW
long | PIXELS_PER_COL
long | COLS_PER_SCREEN
long | ROWS_PER_SCREEN
const ushort | vga_lookup []
long | SED_HOR_PULSE_WIDTH_LCD
long | SED_HOR_PULSE_START_LCD
long | SED_HOR_NONDISP_LCD
long | SED_VER_PULSE_WIDTH_LCD
long | SED_VER_PULSE_START_LCD
long | SED_VER_NONDISP_LCD

## Detailed Description

SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637) 16-Bit access mode.

## Variable Documentation

## ◆ vga_lookup

const ushort vga_lookup[]

Initial value:
= {
LU_BLACK,
LU_BLUE,
LU_GREEN,
LU_CYAN,
LU_RED,
LU_VIOLET,
LU_YELLOW,
LU_WHITE,
LU_GREY,
LU_BRT_BLUE,
LU_BRT_GREEN,
LU_BRT_CYAN,
LU_BRT_RED,
LU_BRT_VIOLET,
LU_BRT_YELLOW,
LU_BRT_WHITE
}