RTEMS: bsps/bfin/include/libcpu/sportRegs.h Source File

| RTEMS 5.4-rc2

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sportRegs.h
1/* Blackfin SPORT Registers
2 *
3 * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
4 * written by Allan Hessenflow <allanh@kallisti.com>
5 *
6 * The license and distribution terms for this file may be
7 * found in the file LICENSE in this distribution or at
8 * http://www.rtems.org/license/LICENSE.
9 */
10
11#ifndef _sportRegs_h_
12#define _sportRegs_h_
13
14
15/* register addresses */
16
17#define SPORT_TCR1_OFFSET 0x0000
18#define SPORT_TCR2_OFFSET 0x0004
19#define SPORT_TCLKDIV_OFFSET 0x0008
20#define SPORT_TFSDIV_OFFSET 0x000c
21#define SPORT_TX_OFFSET 0x0010
22#define SPORT_RX_OFFSET 0x0018
23#define SPORT_RCR1_OFFSET 0x0020
24#define SPORT_RCR2_OFFSET 0x0024
25#define SPORT_RCLKDIV_OFFSET 0x0028
26#define SPORT_RFSDIV_OFFSET 0x002c
27#define SPORT_STAT_OFFSET 0x0030
28#define SPORT_CHNL_OFFSET 0x0034
29#define SPORT_MCMC1_OFFSET 0x0038
30#define SPORT_MCMC2_OFFSET 0x003c
31#define SPORT_MTCS0_OFFSET 0x0040
32#define SPORT_MTCS1_OFFSET 0x0044
33#define SPORT_MTCS2_OFFSET 0x0048
34#define SPORT_MTCS3_OFFSET 0x004c
35#define SPORT_MRCS0_OFFSET 0x0050
36#define SPORT_MRCS1_OFFSET 0x0054
37#define SPORT_MRCS2_OFFSET 0x0058
38#define SPORT_MRCS3_OFFSET 0x005c
39
40
41/* register fields */
42
43#define SPORT_TCR1_TCKFE 0x4000
44#define SPORT_TCR1_LATFS 0x2000
45#define SPORT_TCR1_LTFS 0x1000
46#define SPORT_TCR1_DITFS 0x0800
47#define SPORT_TCR1_TFSR 0x0400
48#define SPORT_TCR1_ITFS 0x0200
49#define SPORT_TCR1_TLSBIT 0x0010
50#define SPORT_TCR1_TDTYPE_MASK 0x000c
51#define SPORT_TCR1_TDTYPE_NORMAL 0x0000
52#define SPORT_TCR1_TDTYPE_ULAW 0x0008
53#define SPORT_TCR1_TDTYPE_ALAW 0x000c
54#define SPORT_TCR1_ITCLK 0x0002
55#define SPORT_TCR1_TSPEN 0x0001
56
57#define SPORT_TCR2_TRFST 0x0400
58#define SPORT_TCR2_TSFSE 0x0200
59#define SPORT_TCR2_TXSE 0x0100
60#define SPORT_TCR2_SLEN_MASK 0x001f
61#define SPORT_TCR2_SLEN_SHIFT 0
62
63#define SPORT_RCR1_RCKFE 0x4000
64#define SPORT_RCR1_LARFS 0x2000
65#define SPORT_RCR1_LRFS 0x1000
66#define SPORT_RCR1_RFSR 0x0400
67#define SPORT_RCR1_IRFS 0x0200
68#define SPORT_RCR1_RLSBIT 0x0010
69#define SPORT_RCR1_RDTYPE_MASK 0x000c
70#define SPORT_RCR1_RDTYPE_ZEROFILL 0x0000
71#define SPORT_RCR1_RDTYPE_SIGNEXTEND 0x0004
72#define SPORT_RCR1_RDTYPE_ULAW 0x0008
73#define SPORT_RCR1_RDTYPE_ALAW 0x000c
74#define SPORT_RCR1_IRCLK 0x0002
75#define SPORT_RCR1_RSPEN 0x0001
76
77#define SPORT_RCR2_RRFST 0x0400
78#define SPORT_RCR2_RSFSE 0x0200
79#define SPORT_RCR2_RXSE 0x0100
80#define SPORT_RCR2_SLEN_MASK 0x001f
81#define SPORT_RCR2_SLEN_SHIFT 0
82
83#define SPORT_STAT_TXHRE 0x0040
84#define SPORT_STAT_TOVF 0x0020
85#define SPORT_STAT_TUVF 0x0010
86#define SPORT_STAT_TXF 0x0008
87#define SPORT_STAT_ROVF 0x0004
88#define SPORT_STAT_RUVF 0x0002
89#define SPORT_STAT_RXNE 0x0001
90
91#define SPORT_CHNL_CHNL_MASK 0x03ff
92#define SPORT_CHNL_CHNL_SHIFT 0
93
94#define SPORT_MCMC1_WSIZE_MASK 0xf000
95#define SPORT_MCMC1_WSIZE_SHIFT 12
96#define SPORT_MCMC1_WOFF_MASK 0x03ff
97#define SPORT_MCMC1_WOFF_SHIFT 0
98
99#define SPORT_MCMC2_MFD_MASK 0xf000
100#define SPORT_MCMC2_MFD_SHIFT 12
101#define SPORT_MCMC2_FSDR 0x0080
102#define SPORT_MCMC2_MCMEN 0x0010
103#define SPORT_MCMC2_MCDRXPE 0x0008
104#define SPORT_MCMC2_MCDTXPE 0x0004
105#define SPORT_MCMC2_MCCRM_MASK 0x0003
106#define SPORT_MCMC2_MCCRM_BYPASS 0x0000
107#define SPORT_MCMC2_MCCRM_2_4 0x0002
108#define SPORT_MCMC2_MCCRM_8_16 0x0003
109
110
111#endif /* _sportRegs_h_ */