RTEMS: cpukit/score/cpu/m68k/include/rtems/m68k/m68360.h Source File

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m68360.h
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1
6/*
7 **************************************************************************
8 **************************************************************************
9 ** **
10 ** MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC) **
11 ** **
12 ** HARDWARE DECLARATIONS **
13 ** **
14 ** **
15 ** Submitted By: **
16 ** **
17 ** W. Eric Norum **
18 ** Saskatchewan Accelerator Laboratory **
19 ** University of Saskatchewan **
20 ** 107 North Road **
21 ** Saskatoon, Saskatchewan, CANADA **
22 ** S7N 5C6 **
23 ** **
24 ** eric@skatter.usask.ca **
25 ** **
26 **************************************************************************
27 **************************************************************************
28 */
29
30#ifndef _RTEMS_M68K_M68360_H
31#define _RTEMS_M68K_M68360_H
32
33/*
34 *************************************************************************
35 * REGISTER SUBBLOCKS *
36 *************************************************************************
37 */
38
39/*
40 * Memory controller registers
41 */
42 typedef struct m360MEMCRegisters_ {
43 unsigned long br;
44 unsigned long or;
45 unsigned long _pad[2];
46} m360MEMCRegisters_t;
47
48/*
49 * Serial Communications Controller registers
50 */
51 typedef struct m360SCCRegisters_ {
52 unsigned long gsmr_l;
53 unsigned long gsmr_h;
54 unsigned short psmr;
55 unsigned short _pad0;
56 unsigned short todr;
57 unsigned short dsr;
58 unsigned short scce;
59 unsigned short _pad1;
60 unsigned short sccm;
61 unsigned char _pad2;
62 unsigned char sccs;
63 unsigned long _pad3[2];
64} m360SCCRegisters_t;
65
66/*
67 * Serial Management Controller registers
68 */
69 typedef struct m360SMCRegisters_ {
70 unsigned short _pad0;
71 unsigned short smcmr;
72 unsigned short _pad1;
73 unsigned char smce;
74 unsigned char _pad2;
75 unsigned short _pad3;
76 unsigned char smcm;
77 unsigned char _pad4;
78 unsigned long _pad5;
79} m360SMCRegisters_t;
80
81
82/*
83 *************************************************************************
84 * Miscellaneous Parameters *
85 *************************************************************************
86 */
87 typedef struct m360MiscParms_ {
88 unsigned short rev_num;
89 unsigned short _res1;
90 unsigned long _res2;
91 unsigned long _res3;
92} m360MiscParms_t;
93
94/*
95 *************************************************************************
96 * RISC Timers *
97 *************************************************************************
98 */
99 typedef struct m360TimerParms_ {
100 unsigned short tm_base;
101 unsigned short _tm_ptr;
102 unsigned short _r_tmr;
103 unsigned short _r_tmv;
104 unsigned long tm_cmd;
105 unsigned long tm_cnt;
106} m360TimerParms_t;
107
108/*
109 * RISC Controller Configuration Register (RCCR)
110 * All other bits in this register are either reserved or
111 * used only with a Motorola-supplied RAM microcode packge.
112 */
113#define M360_RCCR_TIME (1<<15) /* Enable timer */
114#define M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */
115
116/*
117 * Command register
118 * Set up this register before issuing a M360_CR_OP_SET_TIMER command.
119 */
120#define M360_TM_CMD_V (1<<31) /* Set to enable timer */
121#define M360_TM_CMD_R (1<<30) /* Set for automatic restart */
122#define M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */
123#define M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */
124
125/*
126 *************************************************************************
127 * DMA Controllers *
128 *************************************************************************
129 */
130 typedef struct m360IDMAparms_ {
131 unsigned short ibase;
132 unsigned short ibptr;
133 unsigned long _istate;
134 unsigned long _itemp;
135} m360IDMAparms_t;
136
137/*
138 *************************************************************************
139 * Serial Communication Controllers *
140 *************************************************************************
141 */
142 typedef struct m360SCCparms_ {
143 unsigned short rbase;
144 unsigned short tbase;
145 unsigned char rfcr;
146 unsigned char tfcr;
147 unsigned short mrblr;
148 unsigned long _rstate;
149 unsigned long _pad0;
150 unsigned short _rbptr;
151 unsigned short _pad1;
152 unsigned long _pad2;
153 unsigned long _tstate;
154 unsigned long _pad3;
155 unsigned short _tbptr;
156 unsigned short _pad4;
157 unsigned long _pad5;
158 unsigned long _rcrc;
159 unsigned long _tcrc;
160 union {
161 struct {
162 unsigned long _res0;
163 unsigned long _res1;
164 unsigned short max_idl;
165 unsigned short _idlc;
166 unsigned short brkcr;
167 unsigned short parec;
168 unsigned short frmec;
169 unsigned short nosec;
170 unsigned short brkec;
171 unsigned short brklen;
172 unsigned short uaddr[2];
173 unsigned short _rtemp;
174 unsigned short toseq;
175 unsigned short character[8];
176 unsigned short rccm;
177 unsigned short rccr;
178 unsigned short rlbc;
179 } uart;
180 struct {
181 unsigned long crc_p;
182 unsigned long crc_c;
183 } transparent;
184
185 } un;
186} m360SCCparms_t;
187
188 typedef struct m360SCCENparms_ {
189 unsigned short rbase;
190 unsigned short tbase;
191 unsigned char rfcr;
192 unsigned char tfcr;
193 unsigned short mrblr;
194 unsigned long _rstate;
195 unsigned long _pad0;
196 unsigned short _rbptr;
197 unsigned short _pad1;
198 unsigned long _pad2;
199 unsigned long _tstate;
200 unsigned long _pad3;
201 unsigned short _tbptr;
202 unsigned short _pad4;
203 unsigned long _pad5;
204 unsigned long _rcrc;
205 unsigned long _tcrc;
206 union {
207 struct {
208 unsigned long _res0;
209 unsigned long _res1;
210 unsigned short max_idl;
211 unsigned short _idlc;
212 unsigned short brkcr;
213 unsigned short parec;
214 unsigned short frmec;
215 unsigned short nosec;
216 unsigned short brkec;
217 unsigned short brklen;
218 unsigned short uaddr[2];
219 unsigned short _rtemp;
220 unsigned short toseq;
221 unsigned short character[8];
222 unsigned short rccm;
223 unsigned short rccr;
224 unsigned short rlbc;
225 } uart;
226 struct {
227 unsigned long c_pres;
228 unsigned long c_mask;
229 unsigned long crcec;
230 unsigned long alec;
231 unsigned long disfc;
232 unsigned short pads;
233 unsigned short ret_lim;
234 unsigned short _ret_cnt;
235 unsigned short mflr;
236 unsigned short minflr;
237 unsigned short maxd1;
238 unsigned short maxd2;
239 unsigned short _maxd;
240 unsigned short dma_cnt;
241 unsigned short _max_b;
242 unsigned short gaddr1;
243 unsigned short gaddr2;
244 unsigned short gaddr3;
245 unsigned short gaddr4;
246 unsigned long _tbuf0data0;
247 unsigned long _tbuf0data1;
248 unsigned long _tbuf0rba0;
249 unsigned long _tbuf0crc;
250 unsigned short _tbuf0bcnt;
251 unsigned short paddr_h;
252 unsigned short paddr_m;
253 unsigned short paddr_l;
254 unsigned short p_per;
255 unsigned short _rfbd_ptr;
256 unsigned short _tfbd_ptr;
257 unsigned short _tlbd_ptr;
258 unsigned long _tbuf1data0;
259 unsigned long _tbuf1data1;
260 unsigned long _tbuf1rba0;
261 unsigned long _tbuf1crc;
262 unsigned short _tbuf1bcnt;
263 unsigned short _tx_len;
264 unsigned short iaddr1;
265 unsigned short iaddr2;
266 unsigned short iaddr3;
267 unsigned short iaddr4;
268 unsigned short _boff_cnt;
269 unsigned short taddr_h;
270 unsigned short taddr_m;
271 unsigned short taddr_l;
272 } ethernet;
273 struct {
274 unsigned long crc_p;
275 unsigned long crc_c;
276 } transparent;
277 } un;
278} m360SCCENparms_t;
279
280/*
281 * Receive and transmit function code register bits
282 * These apply to the function code registers of all devices, not just SCC.
283 */
284#define M360_RFCR_MOT (1<<4)
285#define M360_RFCR_DMA_SPACE 0x8
286#define M360_TFCR_MOT (1<<4)
287#define M360_TFCR_DMA_SPACE 0x8
288
289/*
290 *************************************************************************
291 * Serial Management Controllers *
292 *************************************************************************
293 */
294 typedef struct m360SMCparms_ {
295 unsigned short rbase;
296 unsigned short tbase;
297 unsigned char rfcr;
298 unsigned char tfcr;
299 unsigned short mrblr;
300 unsigned long _rstate;
301 unsigned long _pad0;
302 unsigned short _rbptr;
303 unsigned short _pad1;
304 unsigned long _pad2;
305 unsigned long _tstate;
306 unsigned long _pad3;
307 unsigned short _tbptr;
308 unsigned short _pad4;
309 unsigned long _pad5;
310 union {
311 struct {
312 unsigned short max_idl;
313 unsigned short _pad0;
314 unsigned short brklen;
315 unsigned short brkec;
316 unsigned short brkcr;
317 unsigned short _r_mask;
318 } uart;
319 struct {
320 unsigned short _pad0[5];
321 } transparent;
322 } un;
323} m360SMCparms_t;
324
325/*
326 * Mode register
327 */
328#define M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */
329#define M360_SMCMR_2STOP (1<<10) /* 2 stop bits */
330#define M360_SMCMR_PARITY (1<<9) /* Enable parity */
331#define M360_SMCMR_EVEN (1<<8) /* Even parity */
332#define M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */
333#define M360_SMCMR_SM_UART (2<<4) /* UART Mode */
334#define M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */
335#define M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */
336#define M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */
337#define M360_SMCMR_TEN (1<<1) /* Enable transmitter */
338#define M360_SMCMR_REN (1<<0) /* Enable receiver */
339
340/*
341 * Event and mask registers (SMCE, SMCM)
342 */
343#define M360_SMCE_BRK (1<<4)
344#define M360_SMCE_BSY (1<<2)
345#define M360_SMCE_TX (1<<1)
346#define M360_SMCE_RX (1<<0)
347
348/*
349 *************************************************************************
350 * Serial Peripheral Interface *
351 *************************************************************************
352 */
353 typedef struct m360SPIparms_ {
354 unsigned short rbase;
355 unsigned short tbase;
356 unsigned char rfcr;
357 unsigned char tfcr;
358 unsigned short mrblr;
359 unsigned long _rstate;
360 unsigned long _pad0;
361 unsigned short _rbptr;
362 unsigned short _pad1;
363 unsigned long _pad2;
364 unsigned long _tstate;
365 unsigned long _pad3;
366 unsigned short _tbptr;
367 unsigned short _pad4;
368 unsigned long _pad5;
369} m360SPIparms_t;
370
371/*
372 * Mode register (SPMODE)
373 */
374#define M360_SPMODE_LOOP (1<<14) /* Local loopback mode */
375#define M360_SPMODE_CI (1<<13) /* Clock invert */
376#define M360_SPMODE_CP (1<<12) /* Clock phase */
377#define M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */
378#define M360_SPMODE_REV (1<<10) /* Reverse data */
379#define M360_SPMODE_MASTER (1<<9) /* SPI is master */
380#define M360_SPMODE_EN (1<<8) /* Enable SPI */
381#define M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */
382#define M360_SPMODE_PM(x) (x) /* Prescaler modulus */
383
384/*
385 * Mode register (SPCOM)
386 */
387#define M360_SPCOM_STR (1<<7) /* Start transmit */
388
389/*
390 * Event and mask registers (SPIE, SPIM)
391 */
392#define M360_SPIE_MME (1<<5) /* Multi-master error */
393#define M360_SPIE_TXE (1<<4) /* Tx error */
394#define M360_SPIE_BSY (1<<2) /* Busy condition*/
395#define M360_SPIE_TXB (1<<1) /* Tx buffer */
396#define M360_SPIE_RXB (1<<0) /* Rx buffer */
397
398/*
399 *************************************************************************
400 * SDMA (SCC, SMC, SPI) Buffer Descriptors *
401 *************************************************************************
402 */
403 typedef struct m360BufferDescriptor_ {
404 unsigned short status;
405 unsigned short length;
406 volatile void *buffer;
407} m360BufferDescriptor_t;
408
409/*
410 * Bits in receive buffer descriptor status word
411 */
412#define M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
413#define M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
414#define M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
415#define M360_BD_LAST (1<<11) /* Ethernet, SPI */
416#define M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */
417#define M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
418#define M360_BD_ADDRESS (1<<10) /* SCC UART */
419#define M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
420#define M360_BD_MISS (1<<8) /* Ethernet */
421#define M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */
422#define M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
423#define M360_BD_LONG (1<<5) /* Ethernet */
424#define M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */
425#define M360_BD_NONALIGNED (1<<4) /* Ethernet */
426#define M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
427#define M360_BD_SHORT (1<<3) /* Ethernet */
428#define M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
429#define M360_BD_CRC_ERROR (1<<2) /* Ethernet */
430#define M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
431#define M360_BD_COLLISION (1<<0) /* Ethernet */
432#define M360_BD_CARRIER_LOST (1<<0) /* SCC UART */
433#define M360_BD_MASTER_ERROR (1<<0) /* SPI */
434
435/*
436 * Bits in transmit buffer descriptor status word
437 * Many bits have the same meaning as those in receiver buffer descriptors.
438 */
439#define M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
440#define M360_BD_PAD (1<<14) /* Ethernet */
441#define M360_BD_CTS_REPORT (1<<11) /* SCC UART */
442#define M360_BD_TX_CRC (1<<10) /* Ethernet */
443#define M360_BD_DEFER (1<<9) /* Ethernet */
444#define M360_BD_HEARTBEAT (1<<8) /* Ethernet */
445#define M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
446#define M360_BD_LATE_COLLISION (1<<7) /* Ethernet */
447#define M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */
448#define M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */
449#define M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
450#define M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */
451#define M360_BD_CARRIER_LOST (1<<0) /* Ethernet */
452#define M360_BD_CTS_LOST (1<<0) /* SCC UART */
453
454/*
455 *************************************************************************
456 * IDMA Buffer Descriptors *
457 *************************************************************************
458 */
459 typedef struct m360IDMABufferDescriptor_ {
460 unsigned short status;
461 unsigned short _pad;
462 unsigned long length;
463 void *source;
464 void *destination;
465} m360IDMABufferDescriptor_t;
466
467/*
468 *************************************************************************
469 * RISC Communication Processor Module Command Register (CR) *
470 *************************************************************************
471 */
472#define M360_CR_RST (1<<15) /* Reset communication processor */
473#define M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */
474#define M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */
475#define M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */
476#define M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */
477#define M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */
478#define M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */
479#define M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */
480#define M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */
481#define M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */
482#define M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */
483#define M360_CR_OP_SET_TIMER (8<<8) /* Timer */
484#define M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */
485#define M360_CR_OP_RESERT_BCS (10<<8) /* SCC */
486#define M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */
487#define M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */
488#define M360_CR_CHAN_SCC2 (4<<4)
489#define M360_CR_CHAN_SPI (5<<4)
490#define M360_CR_CHAN_TIMER (5<<4)
491#define M360_CR_CHAN_SCC3 (8<<4)
492#define M360_CR_CHAN_SMC1 (9<<4)
493#define M360_CR_CHAN_IDMA1 (9<<4)
494#define M360_CR_CHAN_SCC4 (12<<4)
495#define M360_CR_CHAN_SMC2 (13<<4)
496#define M360_CR_CHAN_IDMA2 (13<<4)
497#define M360_CR_FLG (1<<0) /* Command flag */
498
499/*
500 *************************************************************************
501 * System Protection Control Register (SYPCR) *
502 *************************************************************************
503 */
504#define M360_SYPCR_SWE (1<<7) /* Software watchdog enable */
505#define M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */
506#define M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */
507#define M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */
508#define M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */
509#define M360_SYPCR_BME (1<<2) /* Bus monitor external enable */
510#define M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */
511#define M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */
512
513/*
514 *************************************************************************
515 * Memory Control Registers *
516 *************************************************************************
517 */
518#define M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */
519#define M360_GMR_RFEN (1<<23) /* Refresh enable */
520#define M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */
521#define M360_GMR_PGS(x) ((x)<<18) /* Page size */
522#define M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */
523#define M360_GMR_DPS_16BIT (1<<16)
524#define M360_GMR_DPS_8BIT (2<<16)
525#define M360_GMR_DPS_DSACK (3<<16)
526#define M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */
527#define M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */
528#define M360_GMR_SYNC (1<<13) /* Synchronous external access */
529#define M360_GMR_EMWS (1<<12) /* External master wait state */
530#define M360_GMR_OPAR (1<<11) /* Odd parity */
531#define M360_GMR_PBEE (1<<10) /* Parity bus error enable */
532#define M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */
533#define M360_GMR_NCS (1<<8) /* No CPU space */
534#define M360_GMR_DWQ (1<<7) /* Delay write for 360 */
535#define M360_GMR_DW40 (1<<6) /* Delay write for 040 */
536#define M360_GMR_GAMX (1<<5) /* Global address mux enable */
537
538#define M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */
539#define M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */
540#define M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */
541#define M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */
542#define M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */
543#define M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */
544#define M360_MEMC_BR_WP (1<<1) /* Write Protect */
545#define M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */
546
547#define M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */
548#define M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1)
549#define M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */
550#define M360_MEMC_OR_4KB 0x0FFFF000
551#define M360_MEMC_OR_8KB 0x0FFFE000
552#define M360_MEMC_OR_16KB 0x0FFFC000
553#define M360_MEMC_OR_32KB 0x0FFF8000
554#define M360_MEMC_OR_64KB 0x0FFF0000
555#define M360_MEMC_OR_128KB 0x0FFE0000
556#define M360_MEMC_OR_256KB 0x0FFC0000
557#define M360_MEMC_OR_512KB 0x0FF80000
558#define M360_MEMC_OR_1MB 0x0FF00000
559#define M360_MEMC_OR_2MB 0x0FE00000
560#define M360_MEMC_OR_4MB 0x0FC00000
561#define M360_MEMC_OR_8MB 0x0F800000
562#define M360_MEMC_OR_16MB 0x0F000000
563#define M360_MEMC_OR_32MB 0x0E000000
564#define M360_MEMC_OR_64MB 0x0C000000
565#define M360_MEMC_OR_128MB 0x08000000
566#define M360_MEMC_OR_256MB 0x00000000
567#define M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */
568#define M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */
569#define M360_MEMC_OR_PGME (1<<3) /* Page mode enable */
570#define M360_MEMC_OR_32BIT (0<<1) /* Port size */
571#define M360_MEMC_OR_16BIT (1<<1)
572#define M360_MEMC_OR_8BIT (2<<1)
573#define M360_MEMC_OR_DSACK (3<<1)
574#define M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */
575
576/*
577 *************************************************************************
578 * SI Mode Register (SIMODE) *
579 *************************************************************************
580 */
581#define M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */
582#define M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */
583#define M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */
584#define M360_SI_SMC2_BRG2 (1<<28)
585#define M360_SI_SMC2_BRG3 (2<<28)
586#define M360_SI_SMC2_BRG4 (3<<28)
587#define M360_SI_SMC2_CLK5 (0<<28)
588#define M360_SI_SMC2_CLK6 (1<<28)
589#define M360_SI_SMC2_CLK7 (2<<28)
590#define M360_SI_SMC2_CLK8 (3<<28)
591#define M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */
592#define M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */
593#define M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */
594#define M360_SI_SMC1_BRG2 (1<<12)
595#define M360_SI_SMC1_BRG3 (2<<12)
596#define M360_SI_SMC1_BRG4 (3<<12)
597#define M360_SI_SMC1_CLK1 (0<<12)
598#define M360_SI_SMC1_CLK2 (1<<12)
599#define M360_SI_SMC1_CLK3 (2<<12)
600#define M360_SI_SMC1_CLK4 (3<<12)
601
602/*
603 *************************************************************************
604 * SDMA Configuration Register (SDMA) *
605 *************************************************************************
606 */
607#define M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */
608#define M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */
609#define M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */
610#define M360_SDMA_INTE (1<<1) /* SBER interrupt enable */
611#define M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */
612
613/*
614 *************************************************************************
615 * Baud (sic) Rate Generators *
616 *************************************************************************
617 */
618#define M360_BRG_RST (1<<17) /* Reset generator */
619#define M360_BRG_EN (1<<16) /* Enable generator */
620#define M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
621#define M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */
622#define M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */
623#define M360_BRG_ATB (1<<13) /* Autobaud */
624#define M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */
625#define M360_BRG_57600 (26<<1)
626#define M360_BRG_38400 (40<<1)
627#define M360_BRG_19200 (80<<1)
628#define M360_BRG_9600 (162<<1)
629#define M360_BRG_4800 (324<<1)
630#define M360_BRG_2400 (650<<1)
631#define M360_BRG_1200 (1301<<1)
632#define M360_BRG_600 (2603<<1)
633#define M360_BRG_300 ((324<<1) | 1)
634#define M360_BRG_150 ((650<<1) | 1)
635#define M360_BRG_75 ((1301<<1) | 1)
636
637/*
638 *************************************************************************
639 * MC68360 DUAL-PORT RAM AND REGISTERS *
640 *************************************************************************
641 */
642 typedef struct m360_ {
643 /*
644 * Dual-port RAM
645 */
646 unsigned char dpram0[0x400]; /* Microcode program */
647 unsigned char dpram1[0x200];
648 unsigned char dpram2[0x100]; /* Microcode scratch */
649 unsigned char dpram3[0x100]; /* Not on REV A or B masks */
650 unsigned char _rsv0[0xC00-0x800];
651 m360SCCENparms_t scc1p;
652 unsigned char _rsv1[0xCB0-0xC00-sizeof(m360SCCENparms_t)];
653 m360MiscParms_t miscp;
654 unsigned char _rsv2[0xD00-0xCB0-sizeof(m360MiscParms_t)];
655 m360SCCparms_t scc2p;
656 unsigned char _rsv3[0xD80-0xD00-sizeof(m360SCCparms_t)];
657 m360SPIparms_t spip;
658 unsigned char _rsv4[0xDB0-0xD80-sizeof(m360SPIparms_t)];
659 m360TimerParms_t tmp;
660 unsigned char _rsv5[0xE00-0xDB0-sizeof(m360TimerParms_t)];
661 m360SCCparms_t scc3p;
662 unsigned char _rsv6[0xE70-0xE00-sizeof(m360SCCparms_t)];
663 m360IDMAparms_t idma1p;
664 unsigned char _rsv7[0xE80-0xE70-sizeof(m360IDMAparms_t)];
665 m360SMCparms_t smc1p;
666 unsigned char _rsv8[0xF00-0xE80-sizeof(m360SMCparms_t)];
667 m360SCCparms_t scc4p;
668 unsigned char _rsv9[0xF70-0xF00-sizeof(m360SCCparms_t)];
669 m360IDMAparms_t idma2p;
670 unsigned char _rsv10[0xF80-0xF70-sizeof(m360IDMAparms_t)];
671 m360SMCparms_t smc2p;
672 unsigned char _rsv11[0x1000-0xF80-sizeof(m360SMCparms_t)];
673
674 /*
675 * SIM Block
676 */
677 unsigned long mcr;
678 unsigned long _pad00;
679 unsigned char avr;
680 unsigned char rsr;
681 unsigned short _pad01;
682 unsigned char clkocr;
683 unsigned char _pad02;
684 unsigned short _pad03;
685 unsigned short pllcr;
686 unsigned short _pad04;
687 unsigned short cdvcr;
688 unsigned short pepar;
689 unsigned long _pad05[2];
690 unsigned short _pad06;
691 unsigned char sypcr;
692 unsigned char swiv;
693 unsigned short _pad07;
694 unsigned short picr;
695 unsigned short _pad08;
696 unsigned short pitr;
697 unsigned short _pad09;
698 unsigned char _pad10;
699 unsigned char swsr;
700 unsigned long bkar;
701 unsigned long bcar;
702 unsigned long _pad11[2];
703
704 /*
705 * MEMC Block
706 */
707 unsigned long gmr;
708 unsigned short mstat;
709 unsigned short _pad12;
710 unsigned long _pad13[2];
711 m360MEMCRegisters_t memc[8];
712 unsigned char _pad14[0xF0-0xD0];
713 unsigned char _pad15[0x100-0xF0];
714 unsigned char _pad16[0x500-0x100];
715
716 /*
717 * IDMA1 Block
718 */
719 unsigned short iccr;
720 unsigned short _pad17;
721 unsigned short cmr1;
722 unsigned short _pad18;
723 unsigned long sapr1;
724 unsigned long dapr1;
725 unsigned long bcr1;
726 unsigned char fcr1;
727 unsigned char _pad19;
728 unsigned char cmar1;
729 unsigned char _pad20;
730 unsigned char csr1;
731 unsigned char _pad21;
732 unsigned short _pad22;
733
734 /*
735 * SDMA Block
736 */
737 unsigned char sdsr;
738 unsigned char _pad23;
739 unsigned short sdcr;
740 unsigned long sdar;
741
742 /*
743 * IDMA2 Block
744 */
745 unsigned short _pad24;
746 unsigned short cmr2;
747 unsigned long sapr2;
748 unsigned long dapr2;
749 unsigned long bcr2;
750 unsigned char fcr2;
751 unsigned char _pad26;
752 unsigned char cmar2;
753 unsigned char _pad27;
754 unsigned char csr2;
755 unsigned char _pad28;
756 unsigned short _pad29;
757 unsigned long _pad30;
758
759 /*
760 * CPIC Block
761 */
762 unsigned long cicr;
763 unsigned long cipr;
764 unsigned long cimr;
765 unsigned long cisr;
766
767 /*
768 * Parallel I/O Block
769 */
770 unsigned short padir;
771 unsigned short papar;
772 unsigned short paodr;
773 unsigned short padat;
774 unsigned long _pad31[2];
775 unsigned short pcdir;
776 unsigned short pcpar;
777 unsigned short pcso;
778 unsigned short pcdat;
779 unsigned short pcint;
780 unsigned short _pad32;
781 unsigned long _pad33[5];
782
783 /*
784 * TIMER Block
785 */
786 unsigned short tgcr;
787 unsigned short _pad34;
788 unsigned long _pad35[3];
789 unsigned short tmr1;
790 unsigned short tmr2;
791 unsigned short trr1;
792 unsigned short trr2;
793 unsigned short tcr1;
794 unsigned short tcr2;
795 unsigned short tcn1;
796 unsigned short tcn2;
797 unsigned short tmr3;
798 unsigned short tmr4;
799 unsigned short trr3;
800 unsigned short trr4;
801 unsigned short tcr3;
802 unsigned short tcr4;
803 unsigned short tcn3;
804 unsigned short tcn4;
805 unsigned short ter1;
806 unsigned short ter2;
807 unsigned short ter3;
808 unsigned short ter4;
809 unsigned long _pad36[2];
810
811 /*
812 * CP Block
813 */
814 unsigned short cr;
815 unsigned short _pad37;
816 unsigned short rccr;
817 unsigned short _pad38;
818 unsigned long _pad39[3];
819 unsigned short _pad40;
820 unsigned short rter;
821 unsigned short _pad41;
822 unsigned short rtmr;
823 unsigned long _pad42[5];
824
825 /*
826 * BRG Block
827 */
828 unsigned long brgc1;
829 unsigned long brgc2;
830 unsigned long brgc3;
831 unsigned long brgc4;
832
833 /*
834 * SCC Block
835 */
836 m360SCCRegisters_t scc1;
837 m360SCCRegisters_t scc2;
838 m360SCCRegisters_t scc3;
839 m360SCCRegisters_t scc4;
840
841 /*
842 * SMC Block
843 */
844 m360SMCRegisters_t smc1;
845 m360SMCRegisters_t smc2;
846
847 /*
848 * SPI Block
849 */
850 unsigned short spmode;
851 unsigned short _pad43[2];
852 unsigned char spie;
853 unsigned char _pad44;
854 unsigned short _pad45;
855 unsigned char spim;
856 unsigned char _pad46[2];
857 unsigned char spcom;
858 unsigned short _pad47[2];
859
860 /*
861 * PIP Block
862 */
863 unsigned short pipc;
864 unsigned short _pad48;
865 unsigned short ptpr;
866 unsigned long pbdir;
867 unsigned long pbpar;
868 unsigned short _pad49;
869 unsigned short pbodr;
870 unsigned long pbdat;
871 unsigned long _pad50[6];
872
873 /*
874 * SI Block
875 */
876 unsigned long simode;
877 unsigned char sigmr;
878 unsigned char _pad51;
879 unsigned char sistr;
880 unsigned char sicmr;
881 unsigned long _pad52;
882 unsigned long sicr;
883 unsigned short _pad53;
884 unsigned short sirp[2];
885 unsigned short _pad54;
886 unsigned long _pad55[2];
887 unsigned char siram[256];
888} m360_t;
889
890extern volatile m360_t m360;
891
892/*
893 * definitions for the port b SPI pin bits
894 */
895#define M360_PB_SPI_MISO_MSK (1<< 3)
896#define M360_PB_SPI_MOSI_MSK (1<< 2)
897#define M360_PB_SPI_CLK_MSK (1<< 1)
898
899#endif /* _RTEMS_M68K_M68360_H */
m360BufferDescriptor_
Definition: m68360.h:403
m360IDMABufferDescriptor_
Definition: m68360.h:459
m360IDMAparms_
Definition: m68360.h:130
m360MEMCRegisters_
Definition: m68360.h:42
m360MiscParms_
Definition: m68360.h:87
m360SCCENparms_
Definition: m68360.h:188
m360SCCRegisters_
Definition: m68360.h:51
m360SCCparms_
Definition: m68360.h:142
m360SMCRegisters_
Definition: m68360.h:69
m360SMCparms_
Definition: m68360.h:294
m360SPIparms_
Definition: m68360.h:353
m360TimerParms_
Definition: m68360.h:99
m360_
Definition: m68360.h:642