RTEMS: bsps/powerpc/virtex/include/xiltemac.h Source File

| RTEMS 5.4-rc2

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xiltemac.h
1/*
2 * Driver for plb inteface of the xilinx temac 3.00a
3 *
4 * Author: Keith Robertson <kjrobert@alumni.uwaterloo.ca>
5 * Copyright (c) 2007 Linn Products Ltd, Scotland.
6 *
7 * The license and distribution terms for this file may be
8 * found in the file LICENSE in this distribution or at
9 * http://www.rtems.org/license/LICENSE.
10 *
11 */
12
13#ifndef _XILINX_TEMAC_
14#define _XILINX_TEMAC_
15#include <rtems/irq.h>
16
17
18#define XILTEMAC_DRIVER_PREFIX "xiltemac"
19
20#define DRIVER_PREFIX XILTEMAC_DRIVER_PREFIX
21
22
25#define XTE_DISR_OFFSET 0x00000000
26#define XTE_DIPR_OFFSET 0x00000004
27#define XTE_DIER_OFFSET 0x00000008
28#define XTE_DIIR_OFFSET 0x00000018
29#define XTE_DGIE_OFFSET 0x0000001C
30#define XTE_IPISR_OFFSET 0x00000020
31#define XTE_IPIER_OFFSET 0x00000028
32#define XTE_DSR_OFFSET 0x00000040
36#define XTE_PFIFO_TX_BASE_OFFSET 0x00002000
37#define XTE_PFIFO_TX_VACANCY_OFFSET 0x00002004
38#define XTE_PFIFO_TX_DATA_OFFSET 0x00002100
42#define XTE_PFIFO_RX_BASE_OFFSET 0x00002010
43#define XTE_PFIFO_RX_VACANCY_OFFSET 0x00002014
44#define XTE_PFIFO_RX_DATA_OFFSET 0x00002200
48#define XTE_PFIFO_COUNT_MASK 0x00FFFFFF
49
52#define XTE_DMA_SEND_OFFSET 0x00002300
53#define XTE_DMA_RECV_OFFSET 0x00002340
57#define XTE_CR_OFFSET 0x00001000
58#define XTE_TPLR_OFFSET 0x00001004
59#define XTE_TSR_OFFSET 0x00001008
60#define XTE_RPLR_OFFSET 0x0000100C
61#define XTE_RSR_OFFSET 0x00001010
62#define XTE_IFGP_OFFSET 0x00001014
63#define XTE_TPPR_OFFSET 0x00001018
71#define XTE_HOST_IPIF_OFFSET 0x00003000
73#define XTE_ERXC0_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000200)
74#define XTE_ERXC1_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000240)
75#define XTE_ETXC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000280)
76#define XTE_EFCC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000002C0)
77#define XTE_ECFG_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000300)
78#define XTE_EGMIC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000320)
79#define XTE_EMC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000340)
80#define XTE_EUAW0_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000380)
81#define XTE_EUAW1_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000384)
82#define XTE_EMAW0_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000388)
83#define XTE_EMAW1_OFFSET (XTE_HOST_IPIF_OFFSET + 0x0000038C)
84#define XTE_EAFM_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000390)
85#define XTE_EIRS_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003A0)
86#define XTE_EIREN_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003A4)
87#define XTE_EMIID_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003B0)
88#define XTE_EMIIC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003B4)
90/* Register masks. The following constants define bit locations of various
91 * control bits in the registers. Constants are not defined for those registers
92 * that have a single bit field representing all 32 bits. For further
93 * information on the meaning of the various bit masks, refer to the HW spec.
94 */
95
100#define XTE_DXR_SEND_FIFO_MASK 0x00000040
101#define XTE_DXR_RECV_FIFO_MASK 0x00000020
102#define XTE_DXR_RECV_DMA_MASK 0x00000010
103#define XTE_DXR_SEND_DMA_MASK 0x00000008
104#define XTE_DXR_CORE_MASK 0x00000004
105#define XTE_DXR_DPTO_MASK 0x00000002
106#define XTE_DXR_TERR_MASK 0x00000001
112#define XTE_IPXR_XMIT_DONE_MASK 0x00000001
113#define XTE_IPXR_RECV_DONE_MASK 0x00000002
114#define XTE_IPXR_AUTO_NEG_MASK 0x00000004
115#define XTE_IPXR_RECV_REJECT_MASK 0x00000008
116#define XTE_IPXR_XMIT_SFIFO_EMPTY_MASK 0x00000010
117#define XTE_IPXR_RECV_LFIFO_EMPTY_MASK 0x00000020
118#define XTE_IPXR_XMIT_LFIFO_FULL_MASK 0x00000040
119#define XTE_IPXR_RECV_LFIFO_OVER_MASK 0x00000080
123#define XTE_IPXR_RECV_LFIFO_UNDER_MASK 0x00000100
124#define XTE_IPXR_XMIT_SFIFO_OVER_MASK 0x00000200
125#define XTE_IPXR_XMIT_SFIFO_UNDER_MASK 0x00000400
126#define XTE_IPXR_XMIT_LFIFO_OVER_MASK 0x00000800
127#define XTE_IPXR_XMIT_LFIFO_UNDER_MASK 0x00001000
128#define XTE_IPXR_RECV_PFIFO_ABORT_MASK 0x00002000
130#define XTE_IPXR_RECV_LFIFO_ABORT_MASK 0x00004000
133#define XTE_IPXR_RECV_DROPPED_MASK \
134 (XTE_IPXR_RECV_REJECT_MASK | \
135 XTE_IPXR_RECV_PFIFO_ABORT_MASK | \
136 XTE_IPXR_RECV_LFIFO_ABORT_MASK)
138#define XTE_IPXR_XMIT_ERROR_MASK \
139 (XTE_IPXR_XMIT_SFIFO_OVER_MASK | \
140 XTE_IPXR_XMIT_SFIFO_UNDER_MASK | \
141 XTE_IPXR_XMIT_LFIFO_OVER_MASK | \
142 XTE_IPXR_XMIT_LFIFO_UNDER_MASK)
145#define XTE_IPXR_RECV_ERROR_MASK \
146 (XTE_IPXR_RECV_DROPPED_MASK | \
147 XTE_IPXR_RECV_LFIFO_UNDER_MASK)
150#define XTE_IPXR_FIFO_FATAL_ERROR_MASK \
151 (XTE_IPXR_XMIT_SFIFO_OVER_MASK | \
152 XTE_IPXR_XMIT_SFIFO_UNDER_MASK | \
153 XTE_IPXR_XMIT_LFIFO_OVER_MASK | \
154 XTE_IPXR_XMIT_LFIFO_UNDER_MASK | \
155 XTE_IPXR_RECV_LFIFO_UNDER_MASK)
163#define XTE_DSR_RESET_MASK 0x0000000A
169#define XTE_DGIE_ENABLE_MASK 0x80000000
175#define XTE_CR_HTRST_MASK 0x00000008
176#define XTE_CR_BCREJ_MASK 0x00000004
178#define XTE_CR_MCREJ_MASK 0x00000002
180#define XTE_CR_HDUPLEX_MASK 0x00000001
185#define XTE_TPLR_TXPL_MASK 0x00003FFF
190#define XTE_TSR_TXED_MASK 0x80000000
191#define XTE_TSR_PFIFOU_MASK 0x40000000
192#define XTE_TSR_TXA_MASK 0x3E000000
193#define XTE_TSR_TXLC_MASK 0x01000000
194#define XTE_TSR_TPCF_MASK 0x00000001
197#define XTE_TSR_ERROR_MASK \
198 (XTE_TSR_TXED_MASK | \
199 XTE_TSR_PFIFOU_MASK | \
200 XTE_TSR_TXLC_MASK)
206#define XTE_RPLR_RXPL_MASK 0x00003FFF
211#define XTE_RSR_RPCF_MASK 0x00000001
216#define XTE_IFG_IFGD_MASK 0x000000FF
221#define XTE_TPPR_TPPD_MASK 0x0000FFFF
226#define XTE_ERXC1_RXRST_MASK 0x80000000
227#define XTE_ERXC1_RXJMBO_MASK 0x40000000
228#define XTE_ERXC1_RXFCS_MASK 0x20000000
229#define XTE_ERXC1_RXEN_MASK 0x10000000
230#define XTE_ERXC1_RXVLAN_MASK 0x08000000
231#define XTE_ERXC1_RXHD_MASK 0x04000000
232#define XTE_ERXC1_RXLT_MASK 0x02000000
233#define XTE_ERXC1_ERXC1_MASK 0x0000FFFF
241#define XTE_ETXC_TXRST_MASK 0x80000000
242#define XTE_ETXC_TXJMBO_MASK 0x40000000
243#define XTE_ETXC_TXFCS_MASK 0x20000000
244#define XTE_ETXC_TXEN_MASK 0x10000000
245#define XTE_ETXC_TXVLAN_MASK 0x08000000
246#define XTE_ETXC_TXHD_MASK 0x04000000
247#define XTE_ETXC_TXIFG_MASK 0x02000000
252#define XTE_EFCC_TXFLO_MASK 0x40000000
253#define XTE_EFCC_RXFLO_MASK 0x20000000
258#define XTE_ECFG_LINKSPD_MASK 0xC0000000
259#define XTE_ECFG_RGMII_MASK 0x20000000
260#define XTE_ECFG_SGMII_MASK 0x10000000
261#define XTE_ECFG_1000BASEX_MASK 0x08000000
262#define XTE_ECFG_HOSTEN_MASK 0x04000000
263#define XTE_ECFG_TX16BIT 0x02000000
264#define XTE_ECFG_RX16BIT 0x01000000
266#define XTE_ECFG_LINKSPD_10 0x00000000
268#define XTE_ECFG_LINKSPD_100 0x40000000
270#define XTE_ECFG_LINKSPD_1000 0x80000000
275#define XTE_EGMIC_RGLINKSPD_MASK 0xC0000000
276#define XTE_EGMIC_SGLINKSPD_MASK 0x0000000C
277#define XTE_EGMIC_RGSTATUS_MASK 0x00000002
278#define XTE_EGMIC_RGHALFDUPLEX_MASK 0x00000001
280#define XTE_EGMIC_RGLINKSPD_10 0x00000000
282#define XTE_EGMIC_RGLINKSPD_100 0x40000000
284#define XTE_EGMIC_RGLINKSPD_1000 0x80000000
286#define XTE_EGMIC_SGLINKSPD_10 0x00000000
288#define XTE_EGMIC_SGLINKSPD_100 0x00000004
290#define XTE_EGMIC_SGLINKSPD_1000 0x00000008
295#define XTE_EMC_MDIO_MASK 0x00000040
296#define XTE_EMC_CLK_DVD_MAX 0x3F
301#define XTE_EUAW1_MASK 0x0000FFFF
309#define XTE_EMAW1_CAMRNW_MASK 0x00800000
310#define XTE_EMAW1_CAMADDR_MASK 0x00030000
311#define XTE_EUAW1_MASK 0x0000FFFF
315#define XTE_EMAW1_CAMMADDR_SHIFT_MASK 16
322#define XTE_EAFM_EPPRM_MASK 0x80000000
327#define XTE_EMIID_MIIMWRDATA_MASK 0x0000FFFF
332#define XTE_EMIID_MIIMDECADDR_MASK 0x0000FFFF
335 struct XilTemacStats
336{
337 volatile uint32_t iInterrupts;
338
339 volatile uint32_t iRxInterrupts;
340 volatile uint32_t iRxRejectedInterrupts;
341 volatile uint32_t iRxRejectedInvalidFrame;
342 volatile uint32_t iRxRejectedDataFifoFull;
343 volatile uint32_t iRxRejectedLengthFifoFull;
344 volatile uint32_t iRxMaxDrained;
345 volatile uint32_t iRxStrayEvents;
346
347 volatile uint32_t iTxInterrupts;
348 volatile uint32_t iTxMaxDrained;
349};
350
351#define MAX_UNIT_BYTES 50
352
353 struct XilTemac
354{
355 struct arpcom iArpcom;
356 struct XilTemacStats iStats;
357 struct ifnet* iIfp;
358
359 char iUnitName[MAX_UNIT_BYTES];
360
361 uint32_t iAddr;
362 rtems_event_set iIoEvent;
363
364 int iIsrVector;
365
366#if PPC_HAS_CLASSIC_EXCEPTIONS
367 rtems_isr_entry iOldHandler;
368#else
369 rtems_irq_connect_data iOldHandler;
370#endif
371 int iIsPresent;
372};
373
374
375#endif /* _XILINX_EMAC_*/
irq.h
rtems_event_set
uint32_t rtems_event_set
Integer type to hold an event set of up to 32 events represented as a bit field.
Definition: event.h:40
XilTemacStats
Definition: xiltemac.h:336
XilTemac
Definition: xiltemac.h:354
__rtems_irq_connect_data__
Definition: irq.h:45