RTEMS: cpukit/score/cpu/mips/include/rtems/mips/idtcpu.h Source File

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idtcpu.h
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1
11/*
12 * Based upon IDT provided code with the following release:
13 *
14 * This source code has been made available to you by IDT on an AS-IS
15 * basis. Anyone receiving this source is licensed under IDT copyrights
16 * to use it in any way he or she deems fit, including copying it,
17 * modifying it, compiling it, and redistributing it either with or
18 * without modifications. No license under IDT patents or patent
19 * applications is to be implied by the copyright license.
20 *
21 * Any user of this software should understand that IDT cannot provide
22 * technical support for this software and will not be responsible for
23 * any consequences resulting from the use of this software.
24 *
25 * Any person who transfers this source code or any derivative work must
26 * include the IDT copyright notice, this paragraph, and the preceeding
27 * two paragraphs in the transferred software.
28 *
29 * COPYRIGHT IDT CORPORATION 1996
30 * LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
31 */
32
33#ifndef _RTEMS_MIPS_IDTCPU_H
34#define _RTEMS_MIPS_IDTCPU_H
35
44/*
45 * 950313: Ketan added Register definition for XContext reg.
46 * added define for WAIT instruction.
47 * 950421: Ketan added Register definition for Config reg (R3081)
48 */
49
50/*
51** memory configuration and mapping
52*/
53#define K0BASE 0x80000000
54#define K0SIZE 0x20000000
55#define K1BASE 0xa0000000
56#define K1SIZE 0x20000000
57#define K2BASE 0xc0000000
58#define K2SIZE 0x20000000
59#if __mips == 3
60#define KSBASE 0xe0000000
61#define KSSIZE 0x20000000
62#endif
63
64#define KUBASE 0
65#define KUSIZE 0x80000000
66
67/*
68** Exception Vectors
69*/
70#if __mips == 1
71#define UT_VEC K0BASE /* utlbmiss vector */
72#define DB_VEC (K0BASE+0x40) /* debug vector */
73#define E_VEC (K0BASE+0x80) /* exception vector */
74#elif __mips == 32
75#define T_VEC (K0BASE+0x000) /* tlbmiss vector */
76#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */
77#define C_VEC (K0BASE+0x100) /* cache error vector */
78#define E_VEC (K0BASE+0x180) /* exception vector */
79#elif __mips == 3
80#define T_VEC (K0BASE+0x000) /* tlbmiss vector */
81#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */
82#define C_VEC (K0BASE+0x100) /* cache error vector */
83#define E_VEC (K0BASE+0x180) /* exception vector */
84#else
85#error "EXCEPTION VECTORS: unknown ISA level"
86#endif
87#define R_VEC (K1BASE+0x1fc00000) /* reset vector */
88
89/*
90** Address conversion macros
91*/
92#ifdef CLANGUAGE
93#define CAST(as) (as)
94#else
95#define CAST(as)
96#endif
97#define K0_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */
98#define K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */
99#define K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */
100#define K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */
101#define PHYS_TO_K0(x) (CAST(unsigned)(x)|0x80000000) /* physical to kseg0 */
102#define PHYS_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* physical to kseg1 */
103
104/*
105** Cache size constants
106*/
107#define MINCACHE 0x200 /* 512 For 3041. */
108#define MAXCACHE 0x40000 /* 256*1024 256k */
109
110#if __mips == 32
111/* R4000 configuration register definitions */
112#define CFG_CM 0x80000000 /* Master-Checker mode */
113#define CFG_ECMASK 0x70000000 /* System Clock Ratio */
114#define CFG_ECBY2 0x00000000 /* divide by 2 */
115#define CFG_ECBY3 0x10000000 /* divide by 3 */
116#define CFG_ECBY4 0x20000000 /* divide by 4 */
117#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */
118#define CFG_EPD 0x00000000 /* D */
119#define CFG_EPDDX 0x01000000 /* DDX */
120#define CFG_EPDDXX 0x02000000 /* DDXX */
121#define CFG_EPDXDX 0x03000000 /* DXDX */
122#define CFG_EPDDXXX 0x04000000 /* DDXXX */
123#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */
124#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */
125#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */
126#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */
127#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */
128#define CFG_SBSHIFT 22
129#define CFG_SB4 0x00000000 /* 4 words */
130#define CFG_SB8 0x00400000 /* 8 words */
131#define CFG_SB16 0x00800000 /* 16 words */
132#define CFG_SB32 0x00c00000 /* 32 words */
133#define CFG_SS 0x00200000 /* Split secondary cache */
134#define CFG_SW 0x00100000 /* Secondary cache port width */
135#define CFG_EWMASK 0x000c0000 /* System port width */
136#define CFG_EWSHIFT 18
137#define CFG_EW64 0x00000000 /* 64 bit */
138#define CFG_EW32 0x00010000 /* 32 bit */
139#define CFG_SC 0x00020000 /* Secondary cache absent */
140#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */
141#define CFG_BE 0x00008000 /* Big Endian */
142#define CFG_EM 0x00004000 /* ECC mode enable */
143#define CFG_EB 0x00002000 /* Block ordering */
144#define CFG_ICMASK 0x00000e00 /* Instruction cache size */
145#define CFG_ICSHIFT 9
146#define CFG_DCMASK 0x000001c0 /* Data cache size */
147#define CFG_DCSHIFT 6
148#define CFG_IB 0x00000020 /* Instruction cache block size */
149#define CFG_DB 0x00000010 /* Data cache block size */
150#define CFG_CU 0x00000008 /* Update on Store Conditional */
151#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */
152
153/*
154 * R4000 primary cache mode
155 */
156#define CFG_C_UNCACHED 2
157#define CFG_C_NONCOHERENT 3
158#define CFG_C_COHERENTXCL 4
159#define CFG_C_COHERENTXCLW 5
160#define CFG_C_COHERENTUPD 6
161
162/*
163 * R4000 cache operations (should be in assembler...?)
164 */
165#define Index_Invalidate_I 0x0 /* 0 0 */
166#define Index_Writeback_Inv_D 0x1 /* 0 1 */
167#define Index_Invalidate_SI 0x2 /* 0 2 */
168#define Index_Writeback_Inv_SD 0x3 /* 0 3 */
169#define Index_Load_Tag_I 0x4 /* 1 0 */
170#define Index_Load_Tag_D 0x5 /* 1 1 */
171#define Index_Load_Tag_SI 0x6 /* 1 2 */
172#define Index_Load_Tag_SD 0x7 /* 1 3 */
173#define Index_Store_Tag_I 0x8 /* 2 0 */
174#define Index_Store_Tag_D 0x9 /* 2 1 */
175#define Index_Store_Tag_SI 0xA /* 2 2 */
176#define Index_Store_Tag_SD 0xB /* 2 3 */
177#define Create_Dirty_Exc_D 0xD /* 3 1 */
178#define Create_Dirty_Exc_SD 0xF /* 3 3 */
179#define Hit_Invalidate_I 0x10 /* 4 0 */
180#define Hit_Invalidate_D 0x11 /* 4 1 */
181#define Hit_Invalidate_SI 0x12 /* 4 2 */
182#define Hit_Invalidate_SD 0x13 /* 4 3 */
183#define Hit_Writeback_Inv_D 0x15 /* 5 1 */
184#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */
185#define Fill_I 0x14 /* 5 0 */
186#define Hit_Writeback_D 0x19 /* 6 1 */
187#define Hit_Writeback_SD 0x1B /* 6 3 */
188#define Hit_Writeback_I 0x18 /* 6 0 */
189#define Hit_Set_Virtual_SI 0x1E /* 7 2 */
190#define Hit_Set_Virtual_SD 0x1F /* 7 3 */
191
192/* Disabled by chris -- horrible overload of common word.
193#ifndef WAIT
194#define WAIT .word 0x42000020
195#endif
196*/
197/* Disabled by joel -- horrible overload of common word.
198#ifndef wait
199#define wait .word 0x42000020
200#endif wait
201*/
202
203#endif
204
205#if __mips == 3
206/* R4000 configuration register definitions */
207#define CFG_CM 0x80000000 /* Master-Checker mode */
208#define CFG_ECMASK 0x70000000 /* System Clock Ratio */
209#define CFG_ECBY2 0x00000000 /* divide by 2 */
210#define CFG_ECBY3 0x10000000 /* divide by 3 */
211#define CFG_ECBY4 0x20000000 /* divide by 4 */
212#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */
213#define CFG_EPD 0x00000000 /* D */
214#define CFG_EPDDX 0x01000000 /* DDX */
215#define CFG_EPDDXX 0x02000000 /* DDXX */
216#define CFG_EPDXDX 0x03000000 /* DXDX */
217#define CFG_EPDDXXX 0x04000000 /* DDXXX */
218#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */
219#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */
220#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */
221#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */
222#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */
223#define CFG_SBSHIFT 22
224#define CFG_SB4 0x00000000 /* 4 words */
225#define CFG_SB8 0x00400000 /* 8 words */
226#define CFG_SB16 0x00800000 /* 16 words */
227#define CFG_SB32 0x00c00000 /* 32 words */
228#define CFG_SS 0x00200000 /* Split secondary cache */
229#define CFG_SW 0x00100000 /* Secondary cache port width */
230#define CFG_EWMASK 0x000c0000 /* System port width */
231#define CFG_EWSHIFT 18
232#define CFG_EW64 0x00000000 /* 64 bit */
233#define CFG_EW32 0x00010000 /* 32 bit */
234#define CFG_SC 0x00020000 /* Secondary cache absent */
235#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */
236#define CFG_BE 0x00008000 /* Big Endian */
237#define CFG_EM 0x00004000 /* ECC mode enable */
238#define CFG_EB 0x00002000 /* Block ordering */
239#define CFG_ICMASK 0x00000e00 /* Instruction cache size */
240#define CFG_ICSHIFT 9
241#define CFG_DCMASK 0x000001c0 /* Data cache size */
242#define CFG_DCSHIFT 6
243#define CFG_IB 0x00000020 /* Instruction cache block size */
244#define CFG_DB 0x00000010 /* Data cache block size */
245#define CFG_CU 0x00000008 /* Update on Store Conditional */
246#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */
247
248/*
249 * R4000 primary cache mode
250 */
251#define CFG_C_UNCACHED 2
252#define CFG_C_NONCOHERENT 3
253#define CFG_C_COHERENTXCL 4
254#define CFG_C_COHERENTXCLW 5
255#define CFG_C_COHERENTUPD 6
256
257/*
258 * R4000 cache operations (should be in assembler...?)
259 */
260#define Index_Invalidate_I 0x0 /* 0 0 */
261#define Index_Writeback_Inv_D 0x1 /* 0 1 */
262#define Index_Invalidate_SI 0x2 /* 0 2 */
263#define Index_Writeback_Inv_SD 0x3 /* 0 3 */
264#define Index_Load_Tag_I 0x4 /* 1 0 */
265#define Index_Load_Tag_D 0x5 /* 1 1 */
266#define Index_Load_Tag_SI 0x6 /* 1 2 */
267#define Index_Load_Tag_SD 0x7 /* 1 3 */
268#define Index_Store_Tag_I 0x8 /* 2 0 */
269#define Index_Store_Tag_D 0x9 /* 2 1 */
270#define Index_Store_Tag_SI 0xA /* 2 2 */
271#define Index_Store_Tag_SD 0xB /* 2 3 */
272#define Create_Dirty_Exc_D 0xD /* 3 1 */
273#define Create_Dirty_Exc_SD 0xF /* 3 3 */
274#define Hit_Invalidate_I 0x10 /* 4 0 */
275#define Hit_Invalidate_D 0x11 /* 4 1 */
276#define Hit_Invalidate_SI 0x12 /* 4 2 */
277#define Hit_Invalidate_SD 0x13 /* 4 3 */
278#define Hit_Writeback_Inv_D 0x15 /* 5 1 */
279#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */
280#define Fill_I 0x14 /* 5 0 */
281#define Hit_Writeback_D 0x19 /* 6 1 */
282#define Hit_Writeback_SD 0x1B /* 6 3 */
283#define Hit_Writeback_I 0x18 /* 6 0 */
284#define Hit_Set_Virtual_SI 0x1E /* 7 2 */
285#define Hit_Set_Virtual_SD 0x1F /* 7 3 */
286
287/* Disabled by chris -- horrible overload of common word.
288#ifndef WAIT
289#define WAIT .word 0x42000020
290#endif
291*/
292/* Disabled by joel -- horrible overload of common word.
293#ifndef wait
294#define wait .word 0x42000020
295#endif wait
296*/
297
298#endif
299
300/*
301** TLB resource defines
302*/
303#if __mips == 1
304#define N_TLB_ENTRIES 64
305#define TLB_PGSIZE 0x1000
306#define RANDBASE 8
307#define TLBLO_PFNMASK 0xfffff000
308#define TLBLO_PFNSHIFT 12
309#define TLBLO_N 0x800 /* non-cacheable */
310#define TLBLO_D 0x400 /* writeable */
311#define TLBLO_V 0x200 /* valid bit */
312#define TLBLO_G 0x100 /* global access bit */
313
314#define TLBHI_VPNMASK 0xfffff000
315#define TLBHI_VPNSHIFT 12
316#define TLBHI_PIDMASK 0xfc0
317#define TLBHI_PIDSHIFT 6
318#define TLBHI_NPID 64
319
320#define TLBINX_PROBE 0x80000000
321#define TLBINX_INXMASK 0x00003f00
322#define TLBINX_INXSHIFT 8
323
324#define TLBRAND_RANDMASK 0x00003f00
325#define TLBRAND_RANDSHIFT 8
326
327#define TLBCTXT_BASEMASK 0xffe00000
328#define TLBCTXT_BASESHIFT 21
329
330#define TLBCTXT_VPNMASK 0x001ffffc
331#define TLBCTXT_VPNSHIFT 2
332#endif
333#if __mips == 3
334#define N_TLB_ENTRIES 48
335
336#define TLBHI_VPN2MASK 0xffffe000
337#define TLBHI_PIDMASK 0x000000ff
338#define TLBHI_NPID 256
339
340#define TLBLO_PFNMASK 0x3fffffc0
341#define TLBLO_PFNSHIFT 6
342#define TLBLO_D 0x00000004 /* writeable */
343#define TLBLO_V 0x00000002 /* valid bit */
344#define TLBLO_G 0x00000001 /* global access bit */
345#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */
346#define TLBLO_CSHIFT 3
347
348#define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT)
349#define TLBLO_NONCOHERENT (CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
350#define TLBLO_COHERENTXCL (CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
351#define TLBLO_COHERENTXCLW (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
352#define TLBLO_COHERENTUPD (CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
353
354#define TLBINX_PROBE 0x80000000
355#define TLBINX_INXMASK 0x0000003f
356
357#define TLBRAND_RANDMASK 0x0000003f
358
359#define TLBCTXT_BASEMASK 0xff800000
360#define TLBCTXT_BASESHIFT 23
361
362#define TLBCTXT_VPN2MASK 0x007ffff0
363#define TLBCTXT_VPN2SHIFT 4
364
365#define TLBPGMASK_MASK 0x01ffe000
366#endif
367
368#if __mips == 32
369#define N_TLB_ENTRIES 16
370
371#define TLBHI_VPN2MASK 0xffffe000
372#define TLBHI_PIDMASK 0x000000ff
373#define TLBHI_NPID 256
374
375#define TLBLO_PFNMASK 0x3fffffc0
376#define TLBLO_PFNSHIFT 6
377#define TLBLO_D 0x00000004 /* writeable */
378#define TLBLO_V 0x00000002 /* valid bit */
379#define TLBLO_G 0x00000001 /* global access bit */
380#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */
381#define TLBLO_CSHIFT 3
382
383#define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT)
384#define TLBLO_NONCOHERENT (CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
385#define TLBLO_COHERENTXCL (CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
386#define TLBLO_COHERENTXCLW (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
387#define TLBLO_COHERENTUPD (CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
388
389#define TLBINX_PROBE 0x80000000
390#define TLBINX_INXMASK 0x0000003f
391
392#define TLBRAND_RANDMASK 0x0000003f
393
394#define TLBCTXT_BASEMASK 0xff800000
395#define TLBCTXT_BASESHIFT 23
396
397#define TLBCTXT_VPN2MASK 0x007ffff0
398#define TLBCTXT_VPN2SHIFT 4
399
400#define TLBPGMASK_MASK 0x01ffe000
401#endif
402
403#if __mips == 1
404
405
406/* definitions for Debug and Cache Invalidate control (DCIC) register bits */
407#define DCIC_TR 0x80000000 /* Trap enable */
408#define DCIC_UD 0x40000000 /* User debug enable */
409#define DCIC_KD 0x20000000 /* Kernel debug enable */
410#define DCIC_TE 0x10000000 /* Trace enable */
411#define DCIC_DW 0x08000000 /* Enable data breakpoints on write */
412#define DCIC_DR 0x04000000 /* Enable data breakpoints on read */
413#define DCIC_DAE 0x02000000 /* Enable data addresss breakpoints */
414#define DCIC_PCE 0x01000000 /* Enable instruction breakpoints */
415#define DCIC_DE 0x00800000 /* Debug enable */
416#define DCIC_DL 0x00008000 /* Data cache line invalidate */
417#define DCIC_IL 0x00004000 /* Instruction cache line invalidate */
418#define DCIC_D 0x00002000 /* Data cache invalidate enable */
419#define DCIC_I 0x00001000 /* Instr. cache invalidate enable */
420#define DCIC_T 0x00000020 /* Trace, set by CPU */
421#define DCIC_W 0x00000010 /* Write reference, set by CPU */
422#define DCIC_R 0x00000008 /* Read reference, set by CPU */
423#define DCIC_DA 0x00000004 /* Data address, set by CPU */
424#define DCIC_PC 0x00000002 /* Program counter, set by CPU */
425#define DCIC_DB 0x00000001 /* Debug, set by CPU */
426
427
428
429
430#define SR_CUMASK 0xf0000000 /* coproc usable bits */
431#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
432#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
433#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
434#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
435
436#define SR_BEV 0x00400000 /* use boot exception vectors */
437
438/* Cache control bits */
439#define SR_TS 0x00200000 /* TLB shutdown */
440#define SR_PE 0x00100000 /* cache parity error */
441#define SR_CM 0x00080000 /* cache miss */
442#define SR_PZ 0x00040000 /* cache parity zero */
443#define SR_SWC 0x00020000 /* swap cache */
444#define SR_ISC 0x00010000 /* Isolate data cache */
445
446/*
447** status register interrupt masks and bits
448*/
449
450#define SR_IMASK 0x0000ff00 /* Interrupt mask */
451#define SR_IMASK8 0x00000000 /* mask level 8 */
452#define SR_IMASK7 0x00008000 /* mask level 7 */
453#define SR_IMASK6 0x0000c000 /* mask level 6 */
454#define SR_IMASK5 0x0000e000 /* mask level 5 */
455#define SR_IMASK4 0x0000f000 /* mask level 4 */
456#define SR_IMASK3 0x0000f800 /* mask level 3 */
457#define SR_IMASK2 0x0000fc00 /* mask level 2 */
458#define SR_IMASK1 0x0000fe00 /* mask level 1 */
459#define SR_IMASK0 0x0000ff00 /* mask level 0 */
460
461#define SR_IMASKSHIFT 8
462
463#define SR_IBIT8 0x00008000 /* bit level 8 */
464#define SR_IBIT7 0x00004000 /* bit level 7 */
465#define SR_IBIT6 0x00002000 /* bit level 6 */
466#define SR_IBIT5 0x00001000 /* bit level 5 */
467#define SR_IBIT4 0x00000800 /* bit level 4 */
468#define SR_IBIT3 0x00000400 /* bit level 3 */
469#define SR_IBIT2 0x00000200 /* bit level 2 */
470#define SR_IBIT1 0x00000100 /* bit level 1 */
471
472#define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */
473#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */
474#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */
475#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */
476#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */
477#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */
478#endif
479
480#if __mips == 3
481#define SR_CUMASK 0xf0000000 /* coproc usable bits */
482#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
483#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
484#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
485#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
486
487#define SR_RP 0x08000000 /* Reduced power operation */
488#define SR_FR 0x04000000 /* Additional floating point registers */
489#define SR_RE 0x02000000 /* Reverse endian in user mode */
490
491#define SR_BEV 0x00400000 /* Use boot exception vectors */
492#define SR_TS 0x00200000 /* TLB shutdown */
493#define SR_SR 0x00100000 /* Soft reset */
494#define SR_CH 0x00040000 /* Cache hit */
495#define SR_CE 0x00020000 /* Use cache ECC */
496#define SR_DE 0x00010000 /* Disable cache exceptions */
497
498/*
499** status register interrupt masks and bits
500*/
501
502#define SR_IMASK 0x0000ff00 /* Interrupt mask */
503#define SR_IMASK8 0x00000000 /* mask level 8 */
504#define SR_IMASK7 0x00008000 /* mask level 7 */
505#define SR_IMASK6 0x0000c000 /* mask level 6 */
506#define SR_IMASK5 0x0000e000 /* mask level 5 */
507#define SR_IMASK4 0x0000f000 /* mask level 4 */
508#define SR_IMASK3 0x0000f800 /* mask level 3 */
509#define SR_IMASK2 0x0000fc00 /* mask level 2 */
510#define SR_IMASK1 0x0000fe00 /* mask level 1 */
511#define SR_IMASK0 0x0000ff00 /* mask level 0 */
512
513#define SR_IMASKSHIFT 8
514
515#define SR_IBIT8 0x00008000 /* bit level 8 */
516#define SR_IBIT7 0x00004000 /* bit level 7 */
517#define SR_IBIT6 0x00002000 /* bit level 6 */
518#define SR_IBIT5 0x00001000 /* bit level 5 */
519#define SR_IBIT4 0x00000800 /* bit level 4 */
520#define SR_IBIT3 0x00000400 /* bit level 3 */
521#define SR_IBIT2 0x00000200 /* bit level 2 */
522#define SR_IBIT1 0x00000100 /* bit level 1 */
523
524#define SR_KSMASK 0x00000018 /* Kernel mode mask */
525#define SR_KSUSER 0x00000010 /* User mode */
526#define SR_KSSUPER 0x00000008 /* Supervisor mode */
527#define SR_KSKERNEL 0x00000000 /* Kernel mode */
528#define SR_ERL 0x00000004 /* Error level */
529#define SR_EXL 0x00000002 /* Exception level */
530#define SR_IE 0x00000001 /* Interrupts enabled */
531#endif
532
533#if __mips == 32
534#define SR_CUMASK 0xf0000000 /* coproc usable bits */
535#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
536#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
537#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
538#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
539
540#define SR_RP 0x08000000 /* Reduced power operation */
541#define SR_FR 0x04000000 /* Additional floating point registers */
542#define SR_RE 0x02000000 /* Reverse endian in user mode */
543
544#define SR_BEV 0x00400000 /* Use boot exception vectors */
545#define SR_TS 0x00200000 /* TLB shutdown */
546#define SR_SR 0x00100000 /* Soft reset */
547#define SR_CH 0x00040000 /* Cache hit */
548#define SR_CE 0x00020000 /* Use cache ECC */
549#define SR_DE 0x00010000 /* Disable cache exceptions */
550
551/*
552** status register interrupt masks and bits
553*/
554
555#define SR_IMASK 0x0000ff00 /* Interrupt mask */
556#define SR_IMASK8 0x00000000 /* mask level 8 */
557#define SR_IMASK7 0x00008000 /* mask level 7 */
558#define SR_IMASK6 0x0000c000 /* mask level 6 */
559#define SR_IMASK5 0x0000e000 /* mask level 5 */
560#define SR_IMASK4 0x0000f000 /* mask level 4 */
561#define SR_IMASK3 0x0000f800 /* mask level 3 */
562#define SR_IMASK2 0x0000fc00 /* mask level 2 */
563#define SR_IMASK1 0x0000fe00 /* mask level 1 */
564#define SR_IMASK0 0x0000ff00 /* mask level 0 */
565
566#define SR_IMASKSHIFT 8
567
568#define SR_IBIT8 0x00008000 /* bit level 8 */
569#define SR_IBIT7 0x00004000 /* bit level 7 */
570#define SR_IBIT6 0x00002000 /* bit level 6 */
571#define SR_IBIT5 0x00001000 /* bit level 5 */
572#define SR_IBIT4 0x00000800 /* bit level 4 */
573#define SR_IBIT3 0x00000400 /* bit level 3 */
574#define SR_IBIT2 0x00000200 /* bit level 2 */
575#define SR_IBIT1 0x00000100 /* bit level 1 */
576
577#define SR_KSMASK 0x00000018 /* Kernel mode mask */
578#define SR_KSUSER 0x00000010 /* User mode */
579#define SR_KSSUPER 0x00000008 /* Supervisor mode */
580#define SR_KSKERNEL 0x00000000 /* Kernel mode */
581#define SR_ERL 0x00000004 /* Error level */
582#define SR_EXL 0x00000002 /* Exception level */
583#define SR_IE 0x00000001 /* Interrupts enabled */
584#endif
585
586/*
587 * Cause Register
588 */
589#define CAUSE_BD 0x80000000 /* Branch delay slot */
590#define CAUSE_BT 0x40000000 /* Branch Taken */
591#define CAUSE_CEMASK 0x30000000 /* coprocessor error */
592#define CAUSE_CESHIFT 28
593
594
595#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */
596#define CAUSE_IPSHIFT 8
597
598#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */
599#define CAUSE_EXCSHIFT 2
600
601#ifndef XDS
602/*
603** Coprocessor 0 registers
604*/
605#define C0_INX $0 /* tlb index */
606#define C0_RAND $1 /* tlb random */
607#if __mips == 1
608#define C0_TLBLO $2 /* tlb entry low */
609#endif
610#if __mips == 3
611#define C0_TLBLO0 $2 /* tlb entry low 0 */
612#define C0_TLBLO1 $3 /* tlb entry low 1 */
613#endif
614
615#if __mips == 32
616#define C0_TLBLO0 $2 /* tlb entry low 0 */
617#define C0_TLBLO1 $3 /* tlb entry low 1 */
618#endif
619
620
621#define C0_CTXT $4 /* tlb context */
622
623#if __mips == 3
624#define C0_PAGEMASK $5 /* tlb page mask */
625#define C0_WIRED $6 /* number of wired tlb entries */
626#endif
627
628#if __mips == 32
629#define C0_PAGEMASK $5 /* tlb page mask */
630#define C0_WIRED $6 /* number of wired tlb entries */
631#endif
632
633#if __mips == 1
634#define C0_TAR $6
635#endif
636
637#define C0_BADVADDR $8 /* bad virtual address */
638
639#if __mips == 3
640#define C0_COUNT $9 /* cycle count */
641#endif
642#if __mips == 32
643#define C0_COUNT $9 /* cycle count */
644#endif
645
646#define C0_TLBHI $10 /* tlb entry hi */
647
648#if __mips == 3
649#define C0_COMPARE $11 /* cyccle count comparator */
650#endif
651
652#if __mips == 32
653#define C0_COMPARE $11 /* cyccle count comparator */
654#endif
655
656#define C0_SR $12 /* status register */
657#define C0_CAUSE $13 /* exception cause */
658#define C0_EPC $14 /* exception pc */
659#define C0_PRID $15 /* revision identifier */
660
661#if __mips == 1
662#define C0_CONFIG $3 /* configuration register R3081*/
663#endif
664
665#if __mips == 3
666#define C0_CONFIG $16 /* configuration register */
667#define C0_LLADDR $17 /* linked load address */
668#define C0_WATCHLO $18 /* watchpoint trap register */
669#define C0_WATCHHI $19 /* watchpoint trap register */
670#define C0_XCTXT $20 /* extended tlb context */
671#define C0_ECC $26 /* secondary cache ECC control */
672#define C0_CACHEERR $27 /* cache error status */
673#define C0_TAGLO $28 /* cache tag lo */
674#define C0_TAGHI $29 /* cache tag hi */
675#define C0_ERRPC $30 /* cache error pc */
676#endif
677
678#if __mips == 32
679#define C0_CONFIG $16 /* configuration register */
680#define C0_LLADDR $17 /* linked load address */
681#define C0_WATCHLO $18 /* watchpoint trap register */
682#define C0_WATCHHI $19 /* watchpoint trap register */
683#define C0_XCTXT $20 /* extended tlb context */
684#define C0_ECC $26 /* secondary cache ECC control */
685#define C0_CACHEERR $27 /* cache error status */
686#define C0_TAGLO $28 /* cache tag lo */
687#define C0_TAGHI $29 /* cache tag hi */
688#define C0_ERRPC $30 /* cache error pc */
689#endif
690
691
692#define C1_REVISION $0
693#define C1_STATUS $31
694
695#endif /* XDS */
696
697#ifdef R4650
698#define IWATCH $18
699#define DWATCH $19
700#define IBASE $0
701#define IBOUND $1
702#define DBASE $2
703#define DBOUND $3
704#define CALG $17
705#endif
706
708#endif /* _RTEMS_MIPS_IDTCPU_H */