RTEMS: bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h Source File

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reg_rti.h
1/* The header file is generated by make_header.py from RTI.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 * list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 * this list of conditions and the following disclaimer in the documentation
22 * and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_TMS570_RTI
40#define LIBBSP_ARM_TMS570_RTI
41
42#include <bsp/utility.h>
43
44 typedef struct{
45 uint32_t COMPx; /*RTI Compare x Register*/
46 uint32_t UDCPx; /*RTI Update Compare x Register*/
47} tms570_rti_compare_t;
48
49 typedef struct{
50 uint32_t FRCx; /*RTI Free Running Counter x Register*/
51 uint32_t UCx; /*RTI Up Counter x Register*/
52 uint32_t CPUCx; /*RTI Compare Up Counter x Register*/
53 uint8_t reserved1 [4];
54 uint32_t CAFRCx; /*RTI Capture Free Running Counter x Register*/
55 uint32_t CAUCx; /*RTI Capture Up Counter x Register*/
56 uint32_t rsvd[2]; /*Reserved*/
57} tms570_rti_counter_t;
58
59 typedef struct{
60 uint32_t GCTRL; /*RTI Global Control Register*/
61 uint32_t TBCTRL; /*RTI Timebase Control Register*/
62 uint32_t CAPCTRL; /*RTI Capture Control Register*/
63 uint32_t COMPCTRL; /*RTI Compare Control Register*/
64 tms570_rti_counter_t CNT[2];/*Counters*/
65 tms570_rti_compare_t CMP[4];/*Compares*/
66 uint32_t TBLCOMP; /*RTI Timebase Low Compare Register*/
67 uint32_t TBHCOMP; /*RTI Timebase High Compare Register*/
68 uint8_t reserved2 [8];
69 uint32_t SETINTENA; /*RTI Set Interrupt Enable Register*/
70 uint32_t CLEARINTENA; /*RTI Clear Interrupt Enable Register*/
71 uint32_t INTFLAG; /*RTI Interrupt Flag Register*/
72 uint8_t reserved3 [4];
73 uint32_t DWDCTRL; /*Digital Watchdog Control Register*/
74 uint32_t DWDPRLD; /*Digital Watchdog Preload Register*/
75 uint32_t WDSTATUS; /*Watchdog Status Register*/
76 uint32_t WDKEY; /*RTI Watchdog Key Register*/
77 uint32_t DWDCNTR; /*RTI Digital Watchdog Down Counter Register*/
78 uint32_t WWDRXNCTRL; /*Digital Windowed Watchdog Reaction Control Register*/
79 uint32_t WWDSIZECTRL; /*Digital Windowed Watchdog Window Size Control Register*/
80 uint32_t INTCLRENABLE; /*RTI Compare Interrupt Clear Enable Register*/
81 uint32_t COMP0CLR; /*RTI Compare 0 Clear Register*/
82 uint32_t COMP1CLR; /*RTI Compare 1 Clear Register*/
83 uint32_t COMP2CLR; /*RTI Compare 2 Clear Register*/
84 uint32_t COMP3CLR; /*RTI Compare 3 Clear Register*/
85} tms570_rti_t;
86
87
88/*----------------------TMS570_RTI_COMPx----------------------*/
89/* field: COMPx - Compare x. */
90/* Whole 32 bits */
91
92/*----------------------TMS570_RTI_UDCPx----------------------*/
93/* field: UDCPx - Update compare x. */
94/* Whole 32 bits */
95
96/*----------------------TMS570_RTI_FRCx----------------------*/
97/* field: FRC0 - FRC0 */
98/* Whole 32 bits */
99
100/*-----------------------TMS570_RTI_UCx-----------------------*/
101/* field: UC0 - Up counter 0. */
102/* Whole 32 bits */
103
104/*----------------------TMS570_RTI_CPUCx----------------------*/
105/* field: CPUC0 - Compare up counter 0. This register holds the value that is compared with the up counter 0. */
106/* Whole 32 bits */
107
108/*---------------------TMS570_RTI_CAFRCx---------------------*/
109/* field: CAFRC0 - Capture free running counter 0. */
110/* Whole 32 bits */
111
112/*----------------------TMS570_RTI_CAUCx----------------------*/
113/* field: CAUC0 - Capture up counter 0. */
114/* Whole 32 bits */
115
116/*----------------------TMS570_RTI_rsvd----------------------*/
117/* field: CAUC0 - Capture up counter 0. */
118/* Whole 32 bits */
119
120/*----------------------TMS570_RTI_GCTRL----------------------*/
121/* field: NTUSEL - Select NTU signal. */
122#define TMS570_RTI_GCTRL_NTUSEL(val) BSP_FLD32(val,16, 19)
123#define TMS570_RTI_GCTRL_NTUSEL_GET(reg) BSP_FLD32GET(reg,16, 19)
124#define TMS570_RTI_GCTRL_NTUSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
125
126/* field: COS - Continue on suspend. */
127#define TMS570_RTI_GCTRL_COS BSP_BIT32(15)
128
129/* field: CNT1EN - Counter 1 enable. This bit starts and stops counter block 1 (RTIUC1 and RTIFRC1). */
130#define TMS570_RTI_GCTRL_CNT1EN BSP_BIT32(1)
131
132/* field: CNT0EN - Counter 0 enable. This bit starts and stops counter block 0 (RTIUC0 and RTIFRC0). */
133#define TMS570_RTI_GCTRL_CNT0EN BSP_BIT32(0)
134
135
136/*---------------------TMS570_RTI_TBCTRL---------------------*/
137/* field: INC - Increment free running counter 0. */
138#define TMS570_RTI_TBCTRL_INC BSP_BIT32(1)
139
140/* field: TBEXT - Timebase external. */
141#define TMS570_RTI_TBCTRL_TBEXT BSP_BIT32(0)
142
143
144/*---------------------TMS570_RTI_CAPCTRL---------------------*/
145/* field: CAPCNTR1 - Capture counter 1. */
146#define TMS570_RTI_CAPCTRL_CAPCNTR1 BSP_BIT32(1)
147
148/* field: CAPCNTR0 - Capture counter 0. */
149#define TMS570_RTI_CAPCTRL_CAPCNTR0 BSP_BIT32(0)
150
151
152/*--------------------TMS570_RTI_COMPCTRL--------------------*/
153/* field: COMPSEL3 - Compare select 3. */
154#define TMS570_RTI_COMPCTRL_COMPSEL3 BSP_BIT32(12)
155
156/* field: COMPSEL2 - Compare select 2. */
157#define TMS570_RTI_COMPCTRL_COMPSEL2 BSP_BIT32(8)
158
159/* field: COMPSEL1 - Compare select 1. */
160#define TMS570_RTI_COMPCTRL_COMPSEL1 BSP_BIT32(4)
161
162/* field: COMPSEL0 - Compare select 0. */
163#define TMS570_RTI_COMPCTRL_COMPSEL0 BSP_BIT32(0)
164
165
166/*---------------------TMS570_RTI_TBLCOMP---------------------*/
167/* field: TBLCOMP - Timebase low compare value. */
168/* Whole 32 bits */
169
170/*---------------------TMS570_RTI_TBHCOMP---------------------*/
171/* field: TBHCOMP - Timebase high compare value. */
172/* Whole 32 bits */
173
174/*--------------------TMS570_RTI_SETINTENA--------------------*/
175/* field: SETOVL1INT - Set free running counter 1 overflow interrupt. */
176#define TMS570_RTI_SETINTENA_SETOVL1INT BSP_BIT32(18)
177
178/* field: SETOVL0INT - Set free running counter 0 overflow interrupt. */
179#define TMS570_RTI_SETINTENA_SETOVL0INT BSP_BIT32(17)
180
181/* field: SETTBINT - Set timebase interrupt. */
182#define TMS570_RTI_SETINTENA_SETTBINT BSP_BIT32(16)
183
184/* field: SETDMA3 - Set compare DMA request 3. */
185#define TMS570_RTI_SETINTENA_SETDMA3 BSP_BIT32(11)
186
187/* field: SETDMA2 - Set compare DMA request 2. */
188#define TMS570_RTI_SETINTENA_SETDMA2 BSP_BIT32(10)
189
190/* field: SETDMA1 - Set compare DMA request 1. */
191#define TMS570_RTI_SETINTENA_SETDMA1 BSP_BIT32(9)
192
193/* field: SETDMA0 - Set compare DMA request 0. */
194#define TMS570_RTI_SETINTENA_SETDMA0 BSP_BIT32(8)
195
196/* field: SETINT3 - Set compare interrupt 3. */
197#define TMS570_RTI_SETINTENA_SETINT3 BSP_BIT32(3)
198
199/* field: SETINT2 - Set compare interrupt 2. */
200#define TMS570_RTI_SETINTENA_SETINT2 BSP_BIT32(2)
201
202/* field: SETINT1 - Set compare interrupt 1. */
203#define TMS570_RTI_SETINTENA_SETINT1 BSP_BIT32(1)
204
205/* field: SETINT0 - Set compare interrupt 0. */
206#define TMS570_RTI_SETINTENA_SETINT0 BSP_BIT32(0)
207
208
209/*-------------------TMS570_RTI_CLEARINTENA-------------------*/
210/* field: CLEAROVL1INT - Clear free running counter 1 overflow interrupt. */
211#define TMS570_RTI_CLEARINTENA_CLEAROVL1INT BSP_BIT32(18)
212
213/* field: CLEAROVL0INT - Clear free running counter 0 overflow interrupt. */
214#define TMS570_RTI_CLEARINTENA_CLEAROVL0INT BSP_BIT32(17)
215
216/* field: CLEARTBINT - Clear timebase interrupt. */
217#define TMS570_RTI_CLEARINTENA_CLEARTBINT BSP_BIT32(16)
218
219/* field: CLEARDMA3 - Clear compare DMA request 3. */
220#define TMS570_RTI_CLEARINTENA_CLEARDMA3 BSP_BIT32(11)
221
222/* field: CLEARDMA2 - Clear compare DMA request 2. */
223#define TMS570_RTI_CLEARINTENA_CLEARDMA2 BSP_BIT32(10)
224
225/* field: CLEARDMA1 - Clear compare DMA request 1. */
226#define TMS570_RTI_CLEARINTENA_CLEARDMA1 BSP_BIT32(9)
227
228/* field: CLEARDMA0 - Clear compare DMA request 0. */
229#define TMS570_RTI_CLEARINTENA_CLEARDMA0 BSP_BIT32(8)
230
231/* field: CLEARINT3 - Clear compare interrupt 3. */
232#define TMS570_RTI_CLEARINTENA_CLEARINT3 BSP_BIT32(3)
233
234/* field: CLEARINT2 - Clear compare interrupt 2. */
235#define TMS570_RTI_CLEARINTENA_CLEARINT2 BSP_BIT32(2)
236
237/* field: CLEARINT1 - Clear compare interrupt 1. */
238#define TMS570_RTI_CLEARINTENA_CLEARINT1 BSP_BIT32(1)
239
240/* field: CLEARINT0 - Clear compare interrupt 0. */
241#define TMS570_RTI_CLEARINTENA_CLEARINT0 BSP_BIT32(0)
242
243
244/*---------------------TMS570_RTI_INTFLAG---------------------*/
245/* field: OVL1INT - Free running counter 1 overflow interrupt flag. This bit determines if an interrupt is pending. */
246#define TMS570_RTI_INTFLAG_OVL1INT BSP_BIT32(18)
247
248/* field: OVL0INT - Free running counter 0 overflow interrupt flag. This bit determines if an interrupt is pending. */
249#define TMS570_RTI_INTFLAG_OVL0INT BSP_BIT32(17)
250
251/* field: TBINT - Timebase interrupt flag. */
252#define TMS570_RTI_INTFLAG_TBINT BSP_BIT32(16)
253
254/* field: INT3 - Interrupt flag 3. These bits determine if an interrupt due to a Compare 3 match is pending. */
255#define TMS570_RTI_INTFLAG_INT3 BSP_BIT32(3)
256
257/* field: INT2 - Interrupt flag 2. These bits determine if an interrupt due to a Compare 2 match is pending. */
258#define TMS570_RTI_INTFLAG_INT2 BSP_BIT32(2)
259
260/* field: INT1 - Interrupt flag 1. These bits determine if an interrupt due to a Compare 1 match is pending. */
261#define TMS570_RTI_INTFLAG_INT1 BSP_BIT32(1)
262
263/* field: INT0 - Interrupt flag 0. These bits determine if an interrupt due to a Compare 0 match is pending. */
264#define TMS570_RTI_INTFLAG_INT0 BSP_BIT32(0)
265
266
267/*---------------------TMS570_RTI_DWDCTRL---------------------*/
268/* field: DWDCTRL - DWDCTRL Digital Watchdog Control. */
269/* Whole 32 bits */
270
271/*---------------------TMS570_RTI_DWDPRLD---------------------*/
272/* field: DWDPRLD - Digital Watchdog Preload Value. */
273#define TMS570_RTI_DWDPRLD_DWDPRLD(val) BSP_FLD32(val,0, 15)
274#define TMS570_RTI_DWDPRLD_DWDPRLD_GET(reg) BSP_FLD32GET(reg,0, 15)
275#define TMS570_RTI_DWDPRLD_DWDPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
276
277
278/*--------------------TMS570_RTI_WDSTATUS--------------------*/
279/* field: DWWD_ST - Windowed Watchdog Status */
280#define TMS570_RTI_WDSTATUS_DWWD_ST BSP_BIT32(5)
281
282/* field: END_TIME_VIOL - Windowed Watchdog End Time Violation Status. */
283#define TMS570_RTI_WDSTATUS_END_TIME_VIOL BSP_BIT32(4)
284
285/* field: START_TIME_VIOL - Windowed Watchdog Start Time Violation Status. */
286#define TMS570_RTI_WDSTATUS_START_TIME_VIOL BSP_BIT32(3)
287
288/* field: KEY_ST - Watchdog key status. */
289#define TMS570_RTI_WDSTATUS_KEY_ST BSP_BIT32(2)
290
291/* field: DWD_ST - DWD status. */
292#define TMS570_RTI_WDSTATUS_DWD_ST BSP_BIT32(1)
293
294
295/*----------------------TMS570_RTI_WDKEY----------------------*/
296/* field: WDKEY - Watchdog key. These bits provide the key sequence location. */
297#define TMS570_RTI_WDKEY_WDKEY(val) BSP_FLD32(val,0, 15)
298#define TMS570_RTI_WDKEY_WDKEY_GET(reg) BSP_FLD32GET(reg,0, 15)
299#define TMS570_RTI_WDKEY_WDKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
300
301
302/*---------------------TMS570_RTI_DWDCNTR---------------------*/
303/* field: DWDCNTR - DWD down counter. */
304#define TMS570_RTI_DWDCNTR_DWDCNTR(val) BSP_FLD32(val,0, 24)
305#define TMS570_RTI_DWDCNTR_DWDCNTR_GET(reg) BSP_FLD32GET(reg,0, 24)
306#define TMS570_RTI_DWDCNTR_DWDCNTR_SET(reg,val) BSP_FLD32SET(reg, val,0, 24)
307
308
309/*-------------------TMS570_RTI_WWDRXNCTRL-------------------*/
310/* field: WWDRXN - The DWWD reaction */
311#define TMS570_RTI_WWDRXNCTRL_WWDRXN(val) BSP_FLD32(val,0, 3)
312#define TMS570_RTI_WWDRXNCTRL_WWDRXN_GET(reg) BSP_FLD32GET(reg,0, 3)
313#define TMS570_RTI_WWDRXNCTRL_WWDRXN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
314
315
316/*-------------------TMS570_RTI_WWDSIZECTRL-------------------*/
317/* field: WWDSIZE - The DWWD window size */
318/* Whole 32 bits */
319
320/*------------------TMS570_RTI_INTCLRENABLE------------------*/
321/* field: INTCLRENABLE3 - Enables the auto-clear functionality on the compare 3 interrupt. */
322#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3(val) BSP_FLD32(val,24, 27)
323#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_GET(reg) BSP_FLD32GET(reg,24, 27)
324#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
325
326/* field: INTCLRENABLE2 - Enables the auto-clear functionality on the compare 2 interrupt. */
327#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2(val) BSP_FLD32(val,16, 19)
328#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_GET(reg) BSP_FLD32GET(reg,16, 19)
329#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
330
331/* field: INTCLRENABLE1 - Enables the auto-clear functionality on the compare 1 interrupt. */
332#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1(val) BSP_FLD32(val,8, 11)
333#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_GET(reg) BSP_FLD32GET(reg,8, 11)
334#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
335
336/* field: INTCLRENABLE0 - Enables the auto-clear functionality on the compare 0 interrupt. */
337#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0(val) BSP_FLD32(val,0, 3)
338#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_GET(reg) BSP_FLD32GET(reg,0, 3)
339#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
340
341
342/*--------------------TMS570_RTI_COMP0CLR--------------------*/
343/* field: CMP0CLR - Compare 0 clear. */
344/* Whole 32 bits */
345
346/*--------------------TMS570_RTI_COMP1CLR--------------------*/
347/* field: CMP0CLR - Compare 1 clear. */
348/* Whole 32 bits */
349
350/*--------------------TMS570_RTI_COMP2CLR--------------------*/
351/* field: CMP2CLR - Compare 2 clear. */
352/* Whole 32 bits */
353
354/*--------------------TMS570_RTI_COMP3CLR--------------------*/
355/* field: CMP3CLR - Compare 3 clear. */
356/* Whole 32 bits */
357
358
359#endif /* LIBBSP_ARM_TMS570_RTI */
utility.h
Utility macros.
tms570_rti_compare_t
Definition: reg_rti.h:44
tms570_rti_counter_t
Definition: reg_rti.h:49
tms570_rti_t
Definition: reg_rti.h:59