RTEMS: bsps/powerpc/gen83xx/include/bsp/irq.h Source File

| RTEMS 5.4-rc2

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irq.h
1/*===============================================================*\
2| Project: RTEMS generic MPC83xx BSP |
3+-----------------------------------------------------------------+
4| Copyright (c) 2007, 2010 |
5| Embedded Brains GmbH |
6| Obere Lagerstr. 30 |
7| D-82178 Puchheim |
8| Germany |
9| rtems@embedded-brains.de |
10+-----------------------------------------------------------------+
11| The license and distribution terms for this file may be |
12| found in the file LICENSE in this distribution or at |
13| |
14| http://www.rtems.org/license/LICENSE. |
15| |
16+-----------------------------------------------------------------+
17| this file declares constants of the interrupt controller |
18\*===============================================================*/
19
20
21#ifndef GEN83xx_IRQ_IRQ_H
22#define GEN83xx_IRQ_IRQ_H
23
24#include <rtems.h>
25#include <rtems/irq.h>
26#include <rtems/irq-extension.h>
27
28#include <bspopts.h>
29
30/*
31 * the following definitions specify the indices used
32 * to interface the interrupt handler API
33 */
34
35/*
36 * Peripheral IRQ handlers related definitions
37 */
38#define BSP_IPIC_PER_IRQ_NUMBER 128
39#define BSP_IPIC_IRQ_LOWEST_OFFSET 0
40#define BSP_IPIC_IRQ_MAX_OFFSET (BSP_IPIC_IRQ_LOWEST_OFFSET\
41 +BSP_IPIC_PER_IRQ_NUMBER-1)
42
43#define BSP_IS_IPIC_IRQ(irqnum) \
44 (((irqnum) >= BSP_IPIC_IRQ_LOWEST_OFFSET) && \
45 ((irqnum) <= BSP_IPIC_IRQ_MAX_OFFSET))
46/*
47 * Processor IRQ handlers related definitions
48 */
49#define BSP_PROCESSOR_IRQ_NUMBER 1
50#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_IPIC_IRQ_MAX_OFFSET+1)
51#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\
52 +BSP_PROCESSOR_IRQ_NUMBER-1)
53
54#define BSP_IS_PROCESSOR_IRQ(irqnum) \
55 (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \
56 ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET))
57/*
58 * Summary
59 */
60#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1)
61#define BSP_LOWEST_OFFSET BSP_IPIC_IRQ_LOWEST_OFFSET
62#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET
63
64#define BSP_IS_VALID_IRQ(irqnum) \
65 (BSP_IS_PROCESSOR_IRQ(irqnum) \
66 || BSP_IS_IPIC_IRQ(irqnum))
67
68#ifndef ASM
69#ifdef __cplusplus
70extern "C" {
71#endif
72
73/*
74 * index table for the module specific handlers, a few entries are only placeholders
75 */
76 typedef enum {
77 BSP_IPIC_IRQ_FIRST = BSP_IPIC_IRQ_LOWEST_OFFSET,
78 BSP_IPIC_IRQ_ERROR = BSP_IPIC_IRQ_LOWEST_OFFSET + 0,
79#if MPC83XX_CHIP_TYPE / 10 == 830
80 BSP_IPIC_IRQ_DMA1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 3,
81 BSP_IPIC_IRQ_UART = BSP_IPIC_IRQ_LOWEST_OFFSET + 9,
82 BSP_IPIC_IRQ_FLEXCAN = BSP_IPIC_IRQ_LOWEST_OFFSET + 10,
83#else
84 BSP_IPIC_IRQ_UART1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 9,
85 BSP_IPIC_IRQ_UART2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 10,
86 BSP_IPIC_IRQ_SEC = BSP_IPIC_IRQ_LOWEST_OFFSET + 11,
87#endif
88 BSP_IPIC_IRQ_I2C1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 14,
89 BSP_IPIC_IRQ_I2C2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 15,
90 BSP_IPIC_IRQ_SPI = BSP_IPIC_IRQ_LOWEST_OFFSET + 16,
91 BSP_IPIC_IRQ_IRQ1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 17,
92 BSP_IPIC_IRQ_IRQ2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 18,
93 BSP_IPIC_IRQ_IRQ3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 19,
94#if MPC83XX_CHIP_TYPE / 10 == 830
95 BSP_IPIC_IRQ_QUICC_HI = BSP_IPIC_IRQ_LOWEST_OFFSET + 32,
96 BSP_IPIC_IRQ_QUICC_LO = BSP_IPIC_IRQ_LOWEST_OFFSET + 33,
97#else
98 BSP_IPIC_IRQ_IRQ4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 20,
99 BSP_IPIC_IRQ_IRQ5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 21,
100 BSP_IPIC_IRQ_IRQ6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 22,
101 BSP_IPIC_IRQ_IRQ7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 23,
102 BSP_IPIC_IRQ_TSEC1_TX = BSP_IPIC_IRQ_LOWEST_OFFSET + 32,
103 BSP_IPIC_IRQ_TSEC1_RX = BSP_IPIC_IRQ_LOWEST_OFFSET + 33,
104 BSP_IPIC_IRQ_TSEC1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 34,
105 BSP_IPIC_IRQ_TSEC2_TX = BSP_IPIC_IRQ_LOWEST_OFFSET + 35,
106 BSP_IPIC_IRQ_TSEC2_RX = BSP_IPIC_IRQ_LOWEST_OFFSET + 36,
107 BSP_IPIC_IRQ_TSEC2_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 37,
108#endif
109 BSP_IPIC_IRQ_USB_DR = BSP_IPIC_IRQ_LOWEST_OFFSET + 38,
110#if MPC83XX_CHIP_TYPE / 10 == 830
111 BSP_IPIC_IRQ_ESDHC = BSP_IPIC_IRQ_LOWEST_OFFSET + 42,
112#else
113 BSP_IPIC_IRQ_USB_MPH = BSP_IPIC_IRQ_LOWEST_OFFSET + 39,
114#endif
115 BSP_IPIC_IRQ_IRQ0 = BSP_IPIC_IRQ_LOWEST_OFFSET + 48,
116 BSP_IPIC_IRQ_RTC_SEC = BSP_IPIC_IRQ_LOWEST_OFFSET + 64,
117 BSP_IPIC_IRQ_PIT = BSP_IPIC_IRQ_LOWEST_OFFSET + 65,
118 BSP_IPIC_IRQ_PCI1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 66,
119#if MPC83XX_CHIP_TYPE / 10 == 830
120 BSP_IPIC_IRQ_MSIR1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 67,
121#else
122 BSP_IPIC_IRQ_PCI2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 67,
123#endif
124 BSP_IPIC_IRQ_RTC_ALR = BSP_IPIC_IRQ_LOWEST_OFFSET + 68,
125 BSP_IPIC_IRQ_MU = BSP_IPIC_IRQ_LOWEST_OFFSET + 69,
126 BSP_IPIC_IRQ_SBA = BSP_IPIC_IRQ_LOWEST_OFFSET + 70,
127 BSP_IPIC_IRQ_DMA = BSP_IPIC_IRQ_LOWEST_OFFSET + 71,
128 BSP_IPIC_IRQ_GTM4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 72,
129 BSP_IPIC_IRQ_GTM8 = BSP_IPIC_IRQ_LOWEST_OFFSET + 73,
130#if MPC83XX_CHIP_TYPE / 10 == 830
131 BSP_IPIC_IRQ_QUICC_PORTS = BSP_IPIC_IRQ_LOWEST_OFFSET + 74,
132 BSP_IPIC_IRQ_GPIO = BSP_IPIC_IRQ_LOWEST_OFFSET + 75,
133#else
134 BSP_IPIC_IRQ_GPIO1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 74,
135 BSP_IPIC_IRQ_GPIO2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 75,
136#endif
137 BSP_IPIC_IRQ_DDR = BSP_IPIC_IRQ_LOWEST_OFFSET + 76,
138 BSP_IPIC_IRQ_LBC = BSP_IPIC_IRQ_LOWEST_OFFSET + 77,
139 BSP_IPIC_IRQ_GTM2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 78,
140 BSP_IPIC_IRQ_GTM6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 79,
141 BSP_IPIC_IRQ_PMC = BSP_IPIC_IRQ_LOWEST_OFFSET + 80,
142#if MPC83XX_CHIP_TYPE / 10 == 830
143 BSP_IPIC_IRQ_MSIR2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 81,
144 BSP_IPIC_IRQ_MSIR3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 82,
145#else
146 BSP_IPIC_IRQ_GTM3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 84,
147 BSP_IPIC_IRQ_GTM7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 85,
148#endif
149#if MPC83XX_CHIP_TYPE / 10 == 830
150 BSP_IPIC_IRQ_MSIR4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 86,
151 BSP_IPIC_IRQ_MSIR5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 87,
152 BSP_IPIC_IRQ_MSIR6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 88,
153 BSP_IPIC_IRQ_MSIR7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 89,
154#endif
155 BSP_IPIC_IRQ_GTM1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 90,
156 BSP_IPIC_IRQ_GTM5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 91,
157#if MPC83XX_CHIP_TYPE / 10 == 830
158 BSP_IPIC_IRQ_DMA1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 94,
159 BSP_IPIC_IRQ_DPTC = BSP_IPIC_IRQ_LOWEST_OFFSET + 95,
160#endif
161
162 BSP_IPIC_IRQ_LAST = BSP_IPIC_IRQ_MAX_OFFSET,
163 } rtems_irq_symbolic_name;
164
165#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET
166
167#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET
168
169 rtems_status_code mpc83xx_ipic_set_mask( rtems_vector_number vector, rtems_vector_number mask_vector, bool mask);
170
171#define MPC83XX_IPIC_INTERRUPT_NORMAL 0
172
173#define MPC83XX_IPIC_INTERRUPT_SYSTEM 1
174
175#define MPC83XX_IPIC_INTERRUPT_CRITICAL 2
176
177 rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt( rtems_vector_number vector, int type);
178
179#ifdef __cplusplus
180}
181#endif
182#endif /* ASM */
183
184#endif /* GEN83XX_IRQ_IRQ_H */
irq.h
rtems_vector_number
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition: intr.h:47
rtems_status_code
rtems_status_code
Classic API Status.
Definition: status.h:43
irq-extension.h
Header file for the Interrupt Manager Extension.
rtems.h