RTEMS: Processor Dependent Interrupt Management

| RTEMS 5.4-rc2

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Macros | Functions
Processor Dependent Interrupt Management
Internal » SuperCore » CPU Architecture Support » V850

## Macros
#define | CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
#define | CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
#define | _CPU_ISR_Disable(_isr_cookie)
#define | _CPU_ISR_Enable(_isr_cookie)
#define | _CPU_ISR_Flash(_isr_cookie)
#define | _CPU_ISR_Set_level(new_level)

## Functions
RTEMS_INLINE_ROUTINE bool | _CPU_ISR_Is_enabled (uint32_t level)
| Returns true if interrupts are enabled in the specified ISR level, otherwise returns false.
uint32_t | _CPU_ISR_Get_level (void)
| Returns the interrupt level of the executing thread.

## Detailed Description

The following defines the number of bits actually used in the interrupt field of the task mode. How those bits map to the CPU interrupt levels is defined by the routine _CPU_ISR_Set_level.

Port Specific Information:

The v850 only has a single bit in the CPU for interrupt disable/enable.

## Macro Definition Documentation

## ◆ _CPU_ISR_Disable

#define _CPU_ISR_Disable | ( |  | _isr_cookie | ) |

Value:
do { \
unsigned int _psw; \
\
v850_get_psw( _psw ); \
__asm__ __volatile__( "di" ); \
_isr_cookie = _psw; \
} while (0)

Disable all interrupts for an RTEMS critical section. The previous level is returned in _isr_cookie.

Parameters

  [out] | _isr_cookie | will contain the previous level cookie

Port Specific Information:

On the v850, we need to save the PSW and use "di" to disable interrupts.

## ◆ _CPU_ISR_Enable

#define _CPU_ISR_Enable | ( |  | _isr_cookie | ) |

Value:
do { \
unsigned int _psw = (_isr_cookie); \
\
v850_set_psw( _psw ); \
} while (0)

Enable interrupts to the previous level (returned by _CPU_ISR_Disable). This indicates the end of an RTEMS critical section. The parameter _isr_cookie is not modified.

Parameters

  [in] | _isr_cookie | contain the previous level cookie

Port Specific Information:

On the v850, we simply need to restore the PSW.

## ◆ _CPU_ISR_Flash

#define _CPU_ISR_Flash | ( |  | _isr_cookie | ) |

Value:
do { \
unsigned int _psw = (_isr_cookie); \
v850_set_psw( _psw ); \
__asm__ __volatile__( "di" ); \
} while (0)

This temporarily restores the interrupt to _isr_cookie before immediately disabling them again. This is used to divide long RTEMS critical sections into two or more parts. The parameter _isr_cookie is not modified.

Parameters

  [in] | _isr_cookie | contain the previous level cookie

Port Specific Information:

This saves at least one instruction over using enable/disable back to back.

## ◆ _CPU_ISR_Set_level

#define _CPU_ISR_Set_level | ( |  | new_level | ) |

Value:
do { \
if ( new_level ) \
__asm__ __volatile__( "di" ); \
else \
__asm__ __volatile__( "ei" ); \
} while (0)

This routine and _CPU_ISR_Get_level Map the interrupt level in task mode onto the hardware that the CPU actually provides. Currently, interrupt levels which do not map onto the CPU in a generic fashion are undefined. Someday, it would be nice if these were "mapped" by the application via a callout. For example, m68k has 8 levels 0 - 7, levels 8 - 255 would be available for bsp/application specific meaning. This could be used to manage a programmable interrupt controller via the rtems_task_mode directive.

Port Specific Information:

On the v850, level 0 is enabled. Non-zero is disabled.

## ◆ CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK

#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0

Amount of extra stack (above minimum stack size) required by MPCI receive server thread. Remember that in a multiprocessor system this thread must exist and be able to process all directives.

Port Specific Information:

There is no reason to think the v850 needs extra MPCI receive server stack.

## ◆ CPU_PROVIDES_ISR_IS_IN_PROGRESS

#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE

This is defined if the port has a special way to report the ISR nesting level. Most ports maintain the variable _ISR_Nest_level.

## Function Documentation

## ◆ _CPU_ISR_Get_level()

uint32_t _CPU_ISR_Get_level | ( | void |  | ) |

Returns the interrupt level of the executing thread.

Return the current interrupt disable level for this task in the format used by the interrupt level portion of the task mode.

Note
  This routine usually must be implemented as a subroutine.

Port Specific Information:

This method is implemented in C on the v850.

Obtain the current interrupt disable level.

Return the current interrupt disable level for this task in the format used by the interrupt level portion of the task mode.

Note
  This routine usually must be implemented as a subroutine.

Port Specific Information:

XXX document implementation including references if appropriate

## ◆ _CPU_ISR_Is_enabled()

RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled | ( | uint32_t | level | ) |

Returns true if interrupts are enabled in the specified ISR level, otherwise returns false.

Parameters

  [in] | level | The ISR level.

Return values

  true | Interrupts are enabled in the ISR level.
  false | Otherwise.