RTEMS: bsps/arm/atsam/include/libchip/include/samv71/component/component_icm.h Source File

| RTEMS 5.4-rc2

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component_icm.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMV71_ICM_COMPONENT_
31#define _SAMV71_ICM_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __IO uint32_t ICM_CFG;
43 __O uint32_t ICM_CTRL;
44 __O uint32_t ICM_SR;
45 __I uint32_t Reserved1[1];
46 __O uint32_t ICM_IER;
47 __O uint32_t ICM_IDR;
48 __I uint32_t ICM_IMR;
49 __I uint32_t ICM_ISR;
50 __I uint32_t ICM_UASR;
51 __I uint32_t Reserved2[3];
52 __IO uint32_t ICM_DSCR;
53 __IO uint32_t ICM_HASH;
54 __O uint32_t ICM_UIHVAL[8];
55 __I uint32_t Reserved3[37];
56 __I uint32_t ICM_ADDRSIZE;
57 __I uint32_t ICM_IPNAME[2];
58 __I uint32_t ICM_FEATURES;
59 __I uint32_t ICM_VERSION;
60} Icm;
61#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
62/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */
63#define ICM_CFG_WBDIS (0x1u << 0)
64#define ICM_CFG_EOMDIS (0x1u << 1)
65#define ICM_CFG_SLBDIS (0x1u << 2)
66#define ICM_CFG_BBC_Pos 4
67#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos)
68#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)))
69#define ICM_CFG_ASCD (0x1u << 8)
70#define ICM_CFG_DUALBUFF (0x1u << 9)
71#define ICM_CFG_UIHASH (0x1u << 12)
72#define ICM_CFG_UALGO_Pos 13
73#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos)
74#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)))
75#define ICM_CFG_UALGO_SHA1 (0x0u << 13)
76#define ICM_CFG_UALGO_SHA256 (0x1u << 13)
77#define ICM_CFG_UALGO_SHA224 (0x4u << 13)
78#define ICM_CFG_HAPROT_Pos 16
79#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos)
80#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos)))
81#define ICM_CFG_DAPROT_Pos 24
82#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos)
83#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos)))
84/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */
85#define ICM_CTRL_ENABLE (0x1u << 0)
86#define ICM_CTRL_DISABLE (0x1u << 1)
87#define ICM_CTRL_SWRST (0x1u << 2)
88#define ICM_CTRL_REHASH_Pos 4
89#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos)
90#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos)))
91#define ICM_CTRL_RMDIS_Pos 8
92#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos)
93#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos)))
94#define ICM_CTRL_RMEN_Pos 12
95#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos)
96#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos)))
97/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */
98#define ICM_SR_ENABLE (0x1u << 0)
99#define ICM_SR_RAWRMDIS_Pos 8
100#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos)
101#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos)))
102#define ICM_SR_RMDIS_Pos 12
103#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos)
104#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos)))
105/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */
106#define ICM_IER_RHC_Pos 0
107#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos)
108#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)))
109#define ICM_IER_RDM_Pos 4
110#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos)
111#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)))
112#define ICM_IER_RBE_Pos 8
113#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos)
114#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)))
115#define ICM_IER_RWC_Pos 12
116#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos)
117#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)))
118#define ICM_IER_REC_Pos 16
119#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos)
120#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)))
121#define ICM_IER_RSU_Pos 20
122#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos)
123#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)))
124#define ICM_IER_URAD (0x1u << 24)
125/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */
126#define ICM_IDR_RHC_Pos 0
127#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos)
128#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)))
129#define ICM_IDR_RDM_Pos 4
130#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos)
131#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)))
132#define ICM_IDR_RBE_Pos 8
133#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos)
134#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)))
135#define ICM_IDR_RWC_Pos 12
136#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos)
137#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos)))
138#define ICM_IDR_REC_Pos 16
139#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos)
140#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos)))
141#define ICM_IDR_RSU_Pos 20
142#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos)
143#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos)))
144#define ICM_IDR_URAD (0x1u << 24)
145/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */
146#define ICM_IMR_RHC_Pos 0
147#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos)
148#define ICM_IMR_RDM_Pos 4
149#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos)
150#define ICM_IMR_RBE_Pos 8
151#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos)
152#define ICM_IMR_RWC_Pos 12
153#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos)
154#define ICM_IMR_REC_Pos 16
155#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos)
156#define ICM_IMR_RSU_Pos 20
157#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos)
158#define ICM_IMR_URAD (0x1u << 24)
159/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */
160#define ICM_ISR_RHC_Pos 0
161#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos)
162#define ICM_ISR_RDM_Pos 4
163#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos)
164#define ICM_ISR_RBE_Pos 8
165#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos)
166#define ICM_ISR_RWC_Pos 12
167#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos)
168#define ICM_ISR_REC_Pos 16
169#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos)
170#define ICM_ISR_RSU_Pos 20
171#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos)
172#define ICM_ISR_URAD (0x1u << 24)
173/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */
174#define ICM_UASR_URAT_Pos 0
175#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos)
176#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0)
177#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0)
178#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0)
179#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0)
180#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0)
181/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */
182#define ICM_DSCR_DASA_Pos 6
183#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos)
184#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos)))
185/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */
186#define ICM_HASH_HASA_Pos 7
187#define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos)
188#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos)))
189/* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */
190#define ICM_UIHVAL_VAL_Pos 0
191#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos)
192#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos)))
193/* -------- ICM_ADDRSIZE : (ICM Offset: 0xEC) Address Size Register -------- */
194#define ICM_ADDRSIZE_ADDRSIZE_Pos 0
195#define ICM_ADDRSIZE_ADDRSIZE_Msk (0xffffu << ICM_ADDRSIZE_ADDRSIZE_Pos)
196/* -------- ICM_IPNAME[2] : (ICM Offset: 0xF0) IP Name 1 Register -------- */
197#define ICM_IPNAME_IPNAME_Pos 0
198#define ICM_IPNAME_IPNAME_Msk (0xffffffffu << ICM_IPNAME_IPNAME_Pos)
199/* -------- ICM_FEATURES : (ICM Offset: 0xF8) Feature Register -------- */
200#define ICM_FEATURES_CFGALGO (0x1u << 0)
201#define ICM_FEATURES_RFU (0x1u << 1)
202#define ICM_FEATURES_CFGPP (0x1u << 2)
203#define ICM_FEATURES_HDPP (0x1u << 3)
204#define ICM_FEATURES_PDC (0x1u << 4)
205#define ICM_FEATURES_NAIS (0x1u << 5)
206#define ICM_FEATURES_EF (0x1u << 6)
207#define ICM_FEATURES_SI (0x1u << 7)
208#define ICM_FEATURES_BTYP (0x1u << 8)
209#define ICM_FEATURES_PDCOFF0C (0x1u << 9)
210#define ICM_FEATURES_HSHA1 (0x1u << 16)
211#define ICM_FEATURES_HSHA224 (0x1u << 17)
212#define ICM_FEATURES_HSHA256 (0x1u << 18)
213#define ICM_FEATURES_HSHA384 (0x1u << 19)
214#define ICM_FEATURES_HSHA512 (0x1u << 20)
215/* -------- ICM_VERSION : (ICM Offset: 0xFC) Version Register -------- */
216#define ICM_VERSION_VERSION_Pos 0
217#define ICM_VERSION_VERSION_Msk (0xfffu << ICM_VERSION_VERSION_Pos)
218#define ICM_VERSION_MFN_Pos 16
219#define ICM_VERSION_MFN_Msk (0x7u << ICM_VERSION_MFN_Pos)
222
223
224#endif /* _SAMV71_ICM_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Icm
Icm hardware registers.
Definition: component_icm.h:41
Icm::ICM_FEATURES
__I uint32_t ICM_FEATURES
(Icm Offset: 0xF8) Feature Register
Definition: component_icm.h:58
Icm::ICM_VERSION
__I uint32_t ICM_VERSION
(Icm Offset: 0xFC) Version Register
Definition: component_icm.h:59
Icm::ICM_ADDRSIZE
__I uint32_t ICM_ADDRSIZE
(Icm Offset: 0xEC) Address Size Register
Definition: component_icm.h:56