RTEMS: bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h Source File

| RTEMS 5.4-rc2

Loading...
Searching...
No Matches
reg_pll.h
1/* The header file is generated by make_header.py from PLL.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 * list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 * this list of conditions and the following disclaimer in the documentation
22 * and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_TMS570_PLL
40#define LIBBSP_ARM_TMS570_PLL
41
42#include <bsp/utility.h>
43
44 typedef struct{
45 uint32_t PLLCTL3; /*PLL Control 3 Register*/
46 uint8_t reserved1 [108];
47 uint32_t CLKSLIP; /*PLL Clock Slip Control Register*/
48 uint8_t reserved2 [7600];
49 uint32_t SSWPLL1; /*PLL Modulation Depth Measurement Control Register*/
50 uint32_t SSWPLL2; /*SSW PLL BIST Control Register 2*/
51 uint32_t SSWPLL3; /*SSW PLL BIST Control Register 3*/
52 uint32_t CSDIS; /*Clock Source Disable Register*/
53 uint32_t CSDISSET; /*Clock Source Disable Set Register*/
54 uint32_t CSDISCLR; /*Clock Source Disable Clear Register*/
55 uint8_t reserved3 [24];
56 uint32_t CSVSTAT; /*Clock Source Valid Status Register*/
57 uint8_t reserved4 [24];
58 uint32_t PLLCTL1; /*PLL Control 1 Register*/
59 uint32_t PLLCTL2; /*PLL Control 2 Register*/
60 uint8_t reserved5 [16];
61 uint32_t LPOMONCTL; /*LPO/Clock Monitor Control Register*/
62 uint32_t CLKTEST; /*Clock Test Register*/
63 uint8_t reserved6 [16];
64 uint32_t GPREG1; /*General Purpose Register*/
65 uint8_t reserved7 [72];
66 uint32_t GLBSTAT; /*Global Status Register*/
67} tms570_pll_t;
68
69
70/*---------------------TMS570_PLL_PLLCTL3---------------------*/
71/* field: ODPLL2 - Internal PLL Output Divider */
72#define TMS570_PLL_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31)
73#define TMS570_PLL_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31)
74#define TMS570_PLL_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31)
75
76/* field: PLLDIV2 - PLL2 Output Clock Divider */
77#define TMS570_PLL_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28)
78#define TMS570_PLL_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28)
79#define TMS570_PLL_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
80
81/* field: REFCLKDIV2 - Reference Clock Divider */
82#define TMS570_PLL_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21)
83#define TMS570_PLL_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21)
84#define TMS570_PLL_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
85
86/* field: PLLMUL2 - PLL2 Multiplication Factor */
87#define TMS570_PLL_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15)
88#define TMS570_PLL_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15)
89#define TMS570_PLL_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
90
91
92/*---------------------TMS570_PLL_CLKSLIP---------------------*/
93/* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */
94#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13)
95#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13)
96#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13)
97
98/* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */
99#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3)
100#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
101#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
102
103
104/*---------------------TMS570_PLL_SSWPLL1---------------------*/
105/* field: CAPTURE_WINDOW_INDEX - The capture counter present in the PLL wrapper will count the PLL clock edges when */
106#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX(val) BSP_FLD32(val,8, 15)
107#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_GET(reg) BSP_FLD32GET(reg,8, 15)
108#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
109
110/* field: COUNTER_READ_READY - Counter read ready. */
111#define TMS570_PLL_SSWPLL1_COUNTER_READ_READY BSP_BIT32(6)
112
113/* field: COUNTER_RESET - Counter reset. */
114#define TMS570_PLL_SSWPLL1_COUNTER_RESET BSP_BIT32(5)
115
116/* field: COUNTER_EN - Counter enable. */
117#define TMS570_PLL_SSWPLL1_COUNTER_EN BSP_BIT32(4)
118
119/* field: TAP_COUNTER_DIS - The value in this register is used to program a particular bit in CLKOUT counter. */
120#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS(val) BSP_FLD32(val,1, 3)
121#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_GET(reg) BSP_FLD32GET(reg,1, 3)
122#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_SET(reg,val) BSP_FLD32SET(reg, val,1, 3)
123
124/* field: EXT_COUNTER_EN - Modulation Depth Measurement mode */
125#define TMS570_PLL_SSWPLL1_EXT_COUNTER_EN BSP_BIT32(0)
126
127
128/*---------------------TMS570_PLL_SSWPLL2---------------------*/
129/* field: SSW_CAPTURE_COUNT - Capture count. This register returns the value of the capture count. */
130/* Whole 32 bits */
131
132/*---------------------TMS570_PLL_SSWPLL3---------------------*/
133/* field: SSW_CAPTURE_COUNT - Value of CLKout count register. */
134/* Whole 32 bits */
135
136/*----------------------TMS570_PLL_CSDIS----------------------*/
137/* field: CLKSR_7_3_OFF - Clock source[7-3] off. */
138#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
139#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
140#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
141
142/* field: CLKSR_1_0_OFF - Clock source[1-0] off. */
143#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
144#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
145#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
146
147
148/*--------------------TMS570_PLL_CSDISSET--------------------*/
149/* field: SETCLKSR_7_3_OFF - Set clock source[7-3] to the disabled state. */
150#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
151#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
152#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
153
154/* field: SETCLKSR_1_0_OFF - Set clock source[1-0] to the disabled state. */
155#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
156#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
157#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
158
159
160/*--------------------TMS570_PLL_CSDISCLR--------------------*/
161/* field: CLRCLKSR_7_3_OFF - Enables clock source[7-3]. */
162#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
163#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
164#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
165
166/* field: CLRCLKSR_1_0_OFF - Enables clock source[1-0]. */
167#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
168#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
169#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
170
171
172/*---------------------TMS570_PLL_CSVSTAT---------------------*/
173/* field: CLKSR_7_3V - Clock source[7-0] valid. */
174#define TMS570_PLL_CSVSTAT_CLKSR_7_3V(val) BSP_FLD32(val,3, 7)
175#define TMS570_PLL_CSVSTAT_CLKSR_7_3V_GET(reg) BSP_FLD32GET(reg,3, 7)
176#define TMS570_PLL_CSVSTAT_CLKSR_7_3V_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
177
178/* field: CLKSR_1_0V - Clock source[1-0] valid. */
179#define TMS570_PLL_CSVSTAT_CLKSR_1_0V(val) BSP_FLD32(val,0, 1)
180#define TMS570_PLL_CSVSTAT_CLKSR_1_0V_GET(reg) BSP_FLD32GET(reg,0, 1)
181#define TMS570_PLL_CSVSTAT_CLKSR_1_0V_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
182
183
184/*---------------------TMS570_PLL_PLLCTL1---------------------*/
185/* field: ROS - Reset on PLL Slip */
186#define TMS570_PLL_PLLCTL1_ROS BSP_BIT32(31)
187
188/* field: MASK_SLIP - Mask detection of PLL slip */
189#define TMS570_PLL_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
190#define TMS570_PLL_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30)
191#define TMS570_PLL_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
192
193/* field: PLLDIV - PLL Output Clock Divider */
194#define TMS570_PLL_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28)
195#define TMS570_PLL_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28)
196#define TMS570_PLL_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
197
198/* field: ROF - Reset on Oscillator Fail */
199#define TMS570_PLL_PLLCTL1_ROF BSP_BIT32(23)
200
201/* field: REFCLKDIV - Reference Clock Divider */
202#define TMS570_PLL_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21)
203#define TMS570_PLL_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21)
204#define TMS570_PLL_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
205
206/* field: PLLMUL - PLL Multiplication Factor */
207#define TMS570_PLL_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15)
208#define TMS570_PLL_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15)
209#define TMS570_PLL_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
210
211
212/*---------------------TMS570_PLL_PLLCTL2---------------------*/
213/* field: FMENA - Frequency Modulation Enable. */
214#define TMS570_PLL_PLLCTL2_FMENA BSP_BIT32(31)
215
216/* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */
217#define TMS570_PLL_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30)
218#define TMS570_PLL_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30)
219#define TMS570_PLL_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30)
220
221/* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */
222#define TMS570_PLL_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20)
223#define TMS570_PLL_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20)
224#define TMS570_PLL_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20)
225
226/* field: ODPLL - Internal PLL Output Divider. */
227#define TMS570_PLL_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11)
228#define TMS570_PLL_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11)
229#define TMS570_PLL_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
230
231/* field: SPR_AMOUNT - Spreading Amount. */
232#define TMS570_PLL_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8)
233#define TMS570_PLL_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8)
234#define TMS570_PLL_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
235
236
237/*--------------------TMS570_PLL_LPOMONCTL--------------------*/
238/* field: BIAS_ENABLE - Bias enable. */
239#define TMS570_PLL_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24)
240
241/* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */
242#define TMS570_PLL_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16)
243
244/* field: HFTRIM - High frequency oscillator trim value. */
245#define TMS570_PLL_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12)
246#define TMS570_PLL_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12)
247#define TMS570_PLL_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
248
249
250/*---------------------TMS570_PLL_CLKTEST---------------------*/
251/* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */
252#define TMS570_PLL_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26)
253
254/* field: RANGEDETCTRL - Range detection control. */
255#define TMS570_PLL_CLKTEST_RANGEDETCTRL BSP_BIT32(25)
256
257/* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */
258#define TMS570_PLL_CLKTEST_RANGEDETENASSEL BSP_BIT32(24)
259
260/* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */
261#define TMS570_PLL_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19)
262#define TMS570_PLL_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
263#define TMS570_PLL_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
264
265
266/*---------------------TMS570_PLL_GPREG1---------------------*/
267/* field: EMIF_FUNC - Enable EMIF functions to be output. */
268#define TMS570_PLL_GPREG1_EMIF_FUNC BSP_BIT32(31)
269
270/* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */
271#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25)
272#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25)
273#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
274
275/* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */
276#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19)
277#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19)
278#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
279
280/* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */
281#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15)
282#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15)
283#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
284
285
286/*---------------------TMS570_PLL_GLBSTAT---------------------*/
287/* field: FBSLIP - PLL over cycle slip detection. */
288#define TMS570_PLL_GLBSTAT_FBSLIP BSP_BIT32(9)
289
290/* field: RFSLIP - PLL under cycle slip detection. */
291#define TMS570_PLL_GLBSTAT_RFSLIP BSP_BIT32(8)
292
293/* field: OSCFAIL - Oscillator fail flag bit. */
294#define TMS570_PLL_GLBSTAT_OSCFAIL BSP_BIT32(0)
295
296
297
298#endif /* LIBBSP_ARM_TMS570_PLL */
utility.h
Utility macros.
tms570_pll_t
Definition: reg_pll.h:44