RTEMS: bsps/powerpc/virtex/include/bsp/opbintctrl.h Source File

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opbintctrl.h
1/* opbintctrl.h
2 *
3 * This file contains definitions and declarations for the
4 * Xilinx Off Processor Bus (OPB) Interrupt Controller
5 *
6 * Author: Keith Robertson <kjrobert@alumni.uwaterloo.ca>
7 * COPYRIGHT (c) 2005 by Linn Products Ltd, Scotland
8 *
9 * The license and distribution terms for this file may be
10 * found in the file LICENSE in this distribution or at
11 * http://www.rtems.org/license/LICENSE.
12 */
13
14#ifndef _INCLUDE_OPBINTCTRL_H
15#define _INCLUDE_OPBINTCTRL_H
16
17#include <rtems.h>
18#include <rtems/score/isr.h>
19#include <rtems/irq.h>
20#include <bspopts.h>
21#include RTEMS_XPARAMETERS_H
22
23#define USE_GREG_INTERRUPTS
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29
30/* extern XIntc InterruptController;
31 */
32
33
34/* Maximum number of IRQs. Defined in vhdl model */
35#define OPB_INTC_IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
36
37/* Width of INTC registers. Defined in vhdl model */
38#define OPB_INTC_REGISTER_WIDTH 32
39
40/* Base Register address and register offsets. Defined in vhdl model */
41#define OPB_INTC_BASE XPAR_INTC_SINGLE_BASEADDR
42
43
44
45
46
47/* Interrupt Status Register */
48#define OPB_INTC_ISR 0x0
49/* Interrupt Pending Register (ISR && IER) */
50#define OPB_INTC_IPR 0x4
51/* Interrupt Enable Register */
52#define OPB_INTC_IER 0x8
53/* Interrupt Acknowledge Register */
54#define OPB_INTC_IAR 0xC
55/* Set Interrupt Enable (same as read/mask/write to IER) */
56#define OPB_INTC_SIE 0x10
57/* Clear Interrupt Enable (same as read/mask/write to IER) */
58#define OPB_INTC_CIE 0x14
59/* Interrupt Vector Address (highest priority vector number from IPR) */
60#define OPB_INTC_IVR 0x18
61/* Master Enable Register */
62#define OPB_INTC_MER 0x1C
63
64/* Master Enable Register: Hardware Interrupt Enable */
65#define OPB_INTC_MER_HIE 0x2
66
67/* Master Enable Register: Master IRQ Enable */
68#define OPB_INTC_MER_ME 0x1
69
70#ifdef __cplusplus
71}
72#endif
73
74#endif /* _INCLUDE_OPBINTCTRL_H */
irq.h
isr.h
Data Related to the Management of Processor Interrupt Levels.
rtems.h