RTEMS: bsps/sparc/erc32/include/erc32.h File Reference

| RTEMS 5.4-rc2

Loading...
Searching...
No Matches
Data Structures | Macros | Variables
erc32.h File Reference

Contains information pertaining to the ERC32. More...

`#include <rtems/score/sparc.h>`

Go to the source code of this file.

## Data Structures
struct | ERC32_Register_Map

## Macros
#define | ERC32_INTERRUPT_MASKED_ERRORS 1
#define | ERC32_INTERRUPT_EXTERNAL_1 2
#define | ERC32_INTERRUPT_EXTERNAL_2 3
#define | ERC32_INTERRUPT_UART_A_RX_TX 4
#define | ERC32_INTERRUPT_UART_B_RX_TX 5
#define | ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR 6
#define | ERC32_INTERRUPT_UART_ERROR 7
#define | ERC32_INTERRUPT_DMA_ACCESS_ERROR 8
#define | ERC32_INTERRUPT_DMA_TIMEOUT 9
#define | ERC32_INTERRUPT_EXTERNAL_3 10
#define | ERC32_INTERRUPT_EXTERNAL_4 11
#define | ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER 12
#define | ERC32_INTERRUPT_REAL_TIME_CLOCK 13
#define | ERC32_INTERRUPT_EXTERNAL_5 14
#define | ERC32_INTERRUPT_WATCHDOG_TIMEOUT 15
#define | ERC32_TRAP_TYPE(_source) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10)
#define | ERC32_TRAP_SOURCE(_trap) ((_trap) - 0x10)
#define | ERC32_Is_MEC_Trap(_trap)
#define | ERC32_CONFIGURATION_POWER_DOWN_MASK 0x00000001
#define | ERC32_CONFIGURATION_POWER_DOWN_ALLOWED 0x00000001
#define | ERC32_CONFIGURATION_POWER_DOWN_DISABLED 0x00000000
#define | ERC32_CONFIGURATION_SOFTWARE_RESET_MASK 0x00000002
#define | ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED 0x00000002
#define | ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED 0x00000000
#define | ERC32_CONFIGURATION_BUS_TIMEOUT_MASK 0x00000004
#define | ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED 0x00000004
#define | ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED 0x00000000
#define | ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK 0x00000008
#define | ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED 0x00000008
#define | ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED 0x00000000
#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001C00
#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K ( 0 << 10 )
#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K ( 1 << 10 )
#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB ( 2 << 10 )
#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB ( 3 << 10 )
#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB ( 4 << 10 )
#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB ( 5 << 10 )
#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB ( 6 << 10 )
#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB ( 7 << 10 )
#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x001C0000
#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K ( 0 << 18 )
#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K ( 1 << 18 )
#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K ( 2 << 18 )
#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M ( 3 << 18 )
#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M ( 4 << 18 )
#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M ( 5 << 18 )
#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M ( 6 << 18 )
#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M ( 7 << 18 )
#define | ERC32_MEC_TIMER_CONTROL_GCR 0x00000001 /* 1 = reload at 0 */
#define | ERC32_MEC_TIMER_CONTROL_GCL 0x00000002 /* 1 = load and start */
#define | ERC32_MEC_TIMER_CONTROL_GSE 0x00000004 /* 1 = enable counting */
#define | ERC32_MEC_TIMER_CONTROL_GSL 0x00000008 /* 1 = load scalar and start*/
#define | ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */
#define | ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */
#define | ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */
#define | ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start*/
#define | ERC32_MEC_UART_CONTROL_RTD 0x000000FF /* RX/TX data */
#define | ERC32_MEC_UART_STATUS_DR 0x00000001 /* Data Ready */
#define | ERC32_MEC_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
#define | ERC32_MEC_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
#define | ERC32_MEC_UART_STATUS_FE 0x00000010 /* RX Framing Error */
#define | ERC32_MEC_UART_STATUS_PE 0x00000020 /* RX Parity Error */
#define | ERC32_MEC_UART_STATUS_OE 0x00000040 /* RX Overrun Error */
#define | ERC32_MEC_UART_STATUS_CU 0x00000080 /* Clear Errors */
#define | ERC32_MEC_UART_STATUS_TXE 0x00000006 /* TX Empty */
#define | ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */
#define | ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */
#define | ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */
#define | ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */
#define | ERC32_MEC_UART_STATUS_DRA (ERC32_MEC_UART_STATUS_DR << 0)
#define | ERC32_MEC_UART_STATUS_TSEA (ERC32_MEC_UART_STATUS_TSE << 0)
#define | ERC32_MEC_UART_STATUS_THEA (ERC32_MEC_UART_STATUS_THE << 0)
#define | ERC32_MEC_UART_STATUS_FEA (ERC32_MEC_UART_STATUS_FE << 0)
#define | ERC32_MEC_UART_STATUS_PEA (ERC32_MEC_UART_STATUS_PE << 0)
#define | ERC32_MEC_UART_STATUS_OEA (ERC32_MEC_UART_STATUS_OE << 0)
#define | ERC32_MEC_UART_STATUS_CUA (ERC32_MEC_UART_STATUS_CU << 0)
#define | ERC32_MEC_UART_STATUS_TXEA (ERC32_MEC_UART_STATUS_TXE << 0)
#define | ERC32_MEC_UART_STATUS_DRB (ERC32_MEC_UART_STATUS_DR << 16)
#define | ERC32_MEC_UART_STATUS_TSEB (ERC32_MEC_UART_STATUS_TSE << 16)
#define | ERC32_MEC_UART_STATUS_THEB (ERC32_MEC_UART_STATUS_THE << 16)
#define | ERC32_MEC_UART_STATUS_FEB (ERC32_MEC_UART_STATUS_FE << 16)
#define | ERC32_MEC_UART_STATUS_PEB (ERC32_MEC_UART_STATUS_PE << 16)
#define | ERC32_MEC_UART_STATUS_OEB (ERC32_MEC_UART_STATUS_OE << 16)
#define | ERC32_MEC_UART_STATUS_CUB (ERC32_MEC_UART_STATUS_CU << 16)
#define | ERC32_MEC_UART_STATUS_TXEB (ERC32_MEC_UART_STATUS_TXE << 16)
#define | ERC32_Clear_interrupt(_source)
#define | ERC32_Force_interrupt(_source)
#define | ERC32_Is_interrupt_pending(_source) (ERC32_MEC.Interrupt_Pending & (1 << (_source)))
#define | ERC32_Is_interrupt_masked(_source) (ERC32_MEC.Interrupt_Mask & (1 << (_source)))
#define | ERC32_Mask_interrupt(_source)
#define | ERC32_Unmask_interrupt(_source)
#define | ERC32_Disable_interrupt(_source, _previous)
#define | ERC32_Restore_interrupt(_source, _previous)
#define | BSP_Clear_interrupt(_source) ERC32_Clear_interrupt(_source)
#define | BSP_Force_interrupt(_source) ERC32_Force_interrupt(_source)
#define | BSP_Is_interrupt_pending(_source) ERC32_Is_interrupt_pending(_source)
#define | BSP_Is_interrupt_masked(_source) ERC32_Is_interrupt_masked(_source)
#define | BSP_Unmask_interrupt(_source) ERC32_Unmask_interrupt(_source)
#define | BSP_Mask_interrupt(_source) ERC32_Mask_interrupt(_source)
#define | BSP_Disable_interrupt(_source, _previous) ERC32_Disable_interrupt(_source, _prev)
#define | BSP_Restore_interrupt(_source, _previous) ERC32_Restore_interrupt(_source, _previous)
#define | BSP_Cpu_Is_interrupt_masked(_source, _cpu) BSP_Is_interrupt_masked(_source)
#define | BSP_Cpu_Unmask_interrupt(_source, _cpu) BSP_Unmask_interrupt(_source)
#define | BSP_Cpu_Mask_interrupt(_source, _cpu) BSP_Mask_interrupt(_source)
#define | BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) BSP_Disable_interrupt(_source, _prev)
#define | BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) BSP_Cpu_Restore_interrupt(_source, _previous)
#define | ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000001
#define | ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO 0x00000000
#define | ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER 0x00000002
#define | ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING 0x00000004
#define | ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING 0x00000000
#define | ERC32_MEC_TIMER_COUNTER_LOAD_SCALER 0x00000008
#define | ERC32_MEC_TIMER_COUNTER_RELOAD_MASK 0x00000001
#define | ERC32_MEC_TIMER_COUNTER_ENABLE_MASK 0x00000004
#define | ERC32_MEC_TIMER_COUNTER_DEFINED_MASK 0x0000000F
#define | ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000005
#define | ERC32_MEC_Set_General_Purpose_Timer_Control(_value)
#define | ERC32_MEC_Get_General_Purpose_Timer_Control(_value)
#define | ERC32_MEC_Set_Real_Time_Clock_Timer_Control(_value)
#define | ERC32_MEC_Get_Real_Time_Clock_Timer_Control(_value)

## Variables
ERC32_Register_Map | ERC32_MEC
uint32_t | _ERC32_MEC_Timer_Control_Mirror

## Detailed Description

Contains information pertaining to the ERC32.

## Macro Definition Documentation

## ◆ ERC32_Clear_interrupt

#define ERC32_Clear_interrupt | ( |  | _source | ) |

Value:
do { \
ERC32_MEC.Interrupt_Clear = (1 << (_source)); \
} while (0)

## ◆ ERC32_Disable_interrupt

#define ERC32_Disable_interrupt | ( |  | _source,
|  |  | _previous
| ) |  |

Value:
do { \
uint32_t _level; \
uint32_t _mask = 1 << (_source); \
\
_level = sparc_disable_interrupts(); \
(_previous) = ERC32_MEC.Interrupt_Mask; \
ERC32_MEC.Interrupt_Mask = _previous | _mask; \
sparc_enable_interrupts( _level ); \
(_previous) &= _mask; \
} while (0)

## ◆ ERC32_Force_interrupt

#define ERC32_Force_interrupt | ( |  | _source | ) |

Value:
do { \
uint32_t _level; \
\
_level = sparc_disable_interrupts(); \
ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \
ERC32_MEC.Interrupt_Force = (1 << (_source)); \
sparc_enable_interrupts( _level ); \
} while (0)

## ◆ ERC32_Is_MEC_Trap

#define ERC32_Is_MEC_Trap | ( |  | _trap | ) |

Value:
( (_trap) >= ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ) && \
(_trap) <= ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ) )

## ◆ ERC32_Mask_interrupt

#define ERC32_Mask_interrupt | ( |  | _source | ) |

Value:
do { \
uint32_t _level; \
\
_level = sparc_disable_interrupts(); \
ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \
sparc_enable_interrupts( _level ); \
} while (0)

## ◆ ERC32_MEC_Get_General_Purpose_Timer_Control

#define ERC32_MEC_Get_General_Purpose_Timer_Control | ( |  | _value | ) |

Value:
do { \
(_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
} while ( 0 )

## ◆ ERC32_MEC_Get_Real_Time_Clock_Timer_Control

#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control | ( |  | _value | ) |

Value:
do { \
(_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
} while ( 0 )

## ◆ ERC32_MEC_Set_General_Purpose_Timer_Control

#define ERC32_MEC_Set_General_Purpose_Timer_Control | ( |  | _value | ) |

Value:
do { \
uint32_t _level; \
uint32_t _control; \
uint32_t __value; \
\
__value = ((_value) & 0x0f); \
_level = sparc_disable_interrupts(); \
_control = _ERC32_MEC_Timer_Control_Mirror; \
_control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \
_ERC32_MEC_Timer_Control_Mirror = _control | _value; \
_control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \
_control |= __value; \
/* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
ERC32_MEC.Timer_Control = _control; \
sparc_enable_interrupts( _level ); \
} while ( 0 )

## ◆ ERC32_MEC_Set_Real_Time_Clock_Timer_Control

#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control | ( |  | _value | ) |

Value:
do { \
uint32_t _level; \
uint32_t _control; \
uint32_t __value; \
\
__value = ((_value) & 0x0f) << 8; \
_level = sparc_disable_interrupts(); \
_control = _ERC32_MEC_Timer_Control_Mirror; \
_control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \
_ERC32_MEC_Timer_Control_Mirror = _control | __value; \
_control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \
_control |= __value; \
/* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
ERC32_MEC.Timer_Control = _control; \
sparc_enable_interrupts( _level ); \
} while ( 0 )

## ◆ ERC32_Restore_interrupt

#define ERC32_Restore_interrupt | ( |  | _source,
|  |  | _previous
| ) |  |

Value:
do { \
uint32_t _level; \
uint32_t _mask = 1 << (_source); \
\
_level = sparc_disable_interrupts(); \
ERC32_MEC.Interrupt_Mask = \
(ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \
sparc_enable_interrupts( _level ); \
} while (0)

## ◆ ERC32_Unmask_interrupt

#define ERC32_Unmask_interrupt | ( |  | _source | ) |

Value:
do { \
uint32_t _level; \
\
_level = sparc_disable_interrupts(); \
ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \
sparc_enable_interrupts( _level ); \
} while (0)