RTEMS: bsps/arm/atsam/include/libchip/include/sams70/component/component_smc.h Source File

| RTEMS 5.4-rc2

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component_smc.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70_SMC_COMPONENT_
31#define _SAMS70_SMC_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __IO uint32_t SMC_SETUP;
43 __IO uint32_t SMC_PULSE;
44 __IO uint32_t SMC_CYCLE;
45 __IO uint32_t SMC_MODE;
46} SmcCs_number;
48#define SMCCS_NUMBER_NUMBER 4
49typedef struct {
50 SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER];
51 __I uint32_t Reserved1[16];
52 __IO uint32_t SMC_OCMS;
53 __O uint32_t SMC_KEY1;
54 __O uint32_t SMC_KEY2;
55 __I uint32_t Reserved2[22];
56 __IO uint32_t SMC_WPMR;
57 __I uint32_t SMC_WPSR;
58} Smc;
59#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
60/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
61#define SMC_SETUP_NWE_SETUP_Pos 0
62#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos)
63#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
64#define SMC_SETUP_NCS_WR_SETUP_Pos 8
65#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos)
66#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
67#define SMC_SETUP_NRD_SETUP_Pos 16
68#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos)
69#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
70#define SMC_SETUP_NCS_RD_SETUP_Pos 24
71#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos)
72#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
73/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
74#define SMC_PULSE_NWE_PULSE_Pos 0
75#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos)
76#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
77#define SMC_PULSE_NCS_WR_PULSE_Pos 8
78#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos)
79#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
80#define SMC_PULSE_NRD_PULSE_Pos 16
81#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos)
82#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
83#define SMC_PULSE_NCS_RD_PULSE_Pos 24
84#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos)
85#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
86/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
87#define SMC_CYCLE_NWE_CYCLE_Pos 0
88#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos)
89#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
90#define SMC_CYCLE_NRD_CYCLE_Pos 16
91#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos)
92#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
93/* -------- SMC_MODE : (SMC Offset: N/A) SMC MODE Register -------- */
94#define SMC_MODE_READ_MODE (0x1u << 0)
95#define SMC_MODE_WRITE_MODE (0x1u << 1)
96#define SMC_MODE_EXNW_MODE_Pos 4
97#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos)
98#define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos)))
99#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4)
100#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4)
101#define SMC_MODE_EXNW_MODE_READY (0x3u << 4)
102#define SMC_MODE_BAT (0x1u << 8)
103#define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8)
104#define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8)
105#define SMC_MODE_DBW (0x1u << 12)
106#define SMC_MODE_DBW_8_BIT (0x0u << 12)
107#define SMC_MODE_DBW_16_BIT (0x1u << 12)
108#define SMC_MODE_TDF_CYCLES_Pos 16
109#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos)
110#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
111#define SMC_MODE_TDF_MODE (0x1u << 20)
112#define SMC_MODE_PMEN (0x1u << 24)
113#define SMC_MODE_PS_Pos 28
114#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos)
115#define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos)))
116#define SMC_MODE_PS_4_BYTE (0x0u << 28)
117#define SMC_MODE_PS_8_BYTE (0x1u << 28)
118#define SMC_MODE_PS_16_BYTE (0x2u << 28)
119#define SMC_MODE_PS_32_BYTE (0x3u << 28)
120/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */
121#define SMC_OCMS_SMSE (0x1u << 0)
122/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */
123#define SMC_KEY1_KEY1_Pos 0
124#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos)
125#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
126/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */
127#define SMC_KEY2_KEY2_Pos 0
128#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos)
129#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
130/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protection Mode Register -------- */
131#define SMC_WPMR_WPEN (0x1u << 0)
132#define SMC_WPMR_WPKEY_Pos 8
133#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos)
134#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))
135#define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8)
136/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protection Status Register -------- */
137#define SMC_WPSR_WPVS (0x1u << 0)
138#define SMC_WPSR_WPVSRC_Pos 8
139#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos)
142
143
144#endif /* _SAMS70_SMC_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
SmcCs_number
SmcCs_number hardware registers.
Definition: component_smc.h:41
Smc
Definition: component_smc.h:49