RTEMS: bsps/arm/beagle/include/bsp.h Source File

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bsp.h
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1
9/*
10 * Copyright (c) 2012 Claas Ziemke. All rights reserved.
11 *
12 * Claas Ziemke
13 * Kernerstrasse 11
14 * 70182 Stuttgart
15 * Germany
16 * <claas.ziemke@gmx.net>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 *
22 * Modified by Ben Gras <beng@shrike-systems.com> to add lots
23 * of beagleboard/beaglebone definitions, delete lpc32xx specific
24 * ones, and merge with some other header files.
25 */
26
27#ifndef LIBBSP_ARM_BEAGLE_BSP_H
28#define LIBBSP_ARM_BEAGLE_BSP_H
29
40#include <bspopts.h>
41#include <stdint.h>
42#include <bsp/start.h>
43#include <bsp/default-initial-extension.h>
44#include <bsp/beagleboneblack.h>
45
46#include <rtems.h>
47#include <rtems/irq-extension.h>
48
49#include <libcpu/omap3.h>
50#include <libcpu/am335x.h>
51
52#define BSP_FEATURE_IRQ_EXTENSION
53
54/* UART base clock frequency */
55#define UART_CLOCK 48000000
56
57/* Access memory-mapped I/O devices */
58#define mmio_read(a) (*(volatile uint32_t *)(a))
59#define mmio_write(a,v) (*(volatile uint32_t *)(a) = (v))
60#define mmio_set(a,v) mmio_write((a), mmio_read((a)) | (v))
61#define mmio_clear(a,v) mmio_write((a), mmio_read((a)) & ~(v))
62
63#define REG16(x)(*((volatile uint16_t *)(x)))
64#define REG(x)(*((volatile uint32_t *)(x)))
65#define BIT(x)(0x1 << (x))
66// Start and End included
67#define BITS(Start, End) (((1 << (End+1)) - 1) & ~((1 << (Start)) - 1))
68
69#define udelay(u) rtems_task_wake_after(1 + ((u)/rtems_configuration_get_microseconds_per_tick()))
70
71/* Write a uint32_t value to a memory address. */
72static inline void
73write32(uint32_t address, uint32_t value)
74{
75 REG(address) = value;
76}
77
78/* Read an uint32_t from a memory address */
79static inline uint32_t
80read32(uint32_t address)
81{
82 return REG(address);
83}
84
85/* Set a 32 bits value depending on a mask */
86static inline void
87set32(uint32_t address, uint32_t mask, uint32_t value)
88{
89 uint32_t val;
90 val = read32(address);
91 /* clear the bits */
92 val &= ~(mask);
93 /* apply the value using the mask */
94 val |= (value & mask);
95 write32(address, val);
96}
97
98/* Write a uint16_t value to a memory address. */
99static inline void
100write16(uint32_t address, uint16_t value)
101{
102 REG16(address) = value;
103}
104
105/* Read an uint16_t from a memory address */
106static inline uint16_t
107read16(uint32_t address)
108{
109 return REG16(address);
110}
111
112/* Data synchronization barrier */
113static inline void dsb(void)
114{
115 asm volatile("dsb" : : : "memory");
116}
117
118/* Instruction synchronization barrier */
119static inline void isb(void)
120{
121 asm volatile("isb" : : : "memory");
122}
123
124/* flush data cache */
125static inline void flush_data_cache(void)
126{
127 asm volatile(
128 "mov r0, #0\n"
129 "mcr p15, #0, r0, c7, c10, #4\n"
130 : /* No outputs */
131 : /* No inputs */
132 : "r0","memory"
133 );
134}
135
136#define __arch_getb(a) (*(volatile unsigned char *)(a))
137#define __arch_getw(a) (*(volatile unsigned short *)(a))
138#define __arch_getl(a) (*(volatile unsigned int *)(a))
139
140#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
141#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
142#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
143
144#define writeb(v,c) ({ unsigned char __v = v; __arch_putb(__v,c); __v; })
145#define writew(v,c) ({ unsigned short __v = v; __arch_putw(__v,c); __v; })
146#define writel(v,c) ({ unsigned int __v = v; __arch_putl(__v,c); __v; })
147
148#define readb(c) ({ unsigned char __v = __arch_getb(c); __v; })
149#define readw(c) ({ unsigned short __v = __arch_getw(c); __v; })
150#define readl(c) ({ unsigned int __v = __arch_getl(c); __v; })
151
152#define SYSTEM_CLOCK_12 12000000
153#define SYSTEM_CLOCK_13 13000000
154#define SYSTEM_CLOCK_192 19200000
155#define SYSTEM_CLOCK_96 96000000
156
157#if !defined(IS_DM3730) && !defined(IS_AM335X)
158#error Unrecognized BSP configured.
159#endif
160
161#if IS_DM3730
162#define BSP_DEVICEMEM_START 0x48000000
163#define BSP_DEVICEMEM_END 0x5F000000
164#endif
165
166#if IS_AM335X
167#define BSP_DEVICEMEM_START 0x44000000
168#define BSP_DEVICEMEM_END 0x57000000
169#endif
170
171/* per-target uart config */
172#if IS_AM335X
173#define BSP_CONSOLE_UART 1
174#define BSP_CONSOLE_UART_BASE BEAGLE_BASE_UART_1
175#define BSP_CONSOLE_UART_IRQ OMAP3_UART1_IRQ
176#define BEAGLE_BASE_UART_1 0x44E09000
177#define BEAGLE_BASE_UART_2 0x48022000
178#define BEAGLE_BASE_UART_3 0x48024000
179#endif
180
181/* per-target uart config */
182#if IS_DM3730
183#define BSP_CONSOLE_UART 3
184#define BSP_CONSOLE_UART_BASE BEAGLE_BASE_UART_3
185#define BSP_CONSOLE_UART_IRQ OMAP3_UART3_IRQ
186#define BEAGLE_BASE_UART_1 0x4806A000
187#define BEAGLE_BASE_UART_2 0x4806C000
188#define BEAGLE_BASE_UART_3 0x49020000
189#endif
190
191/* GPIO pin config */
192#if IS_AM335X
193#define BSP_GPIO_PIN_COUNT 128
194#define BSP_GPIO_PINS_PER_BANK 32
195#endif
196
197#if IS_DM3730
198#define BSP_GPIO_PIN_COUNT 192
199#define BSP_GPIO_PINS_PER_BANK 32
200#endif
201
202#if BSP_START_COPY_FDT_FROM_U_BOOT
203#define BSP_FDT_IS_SUPPORTED
204#endif
205
206/* i2c stuff */
207 typedef struct {
208 uint32_t rx_or_tx;
209 uint32_t stat;
210 uint32_t ctrl;
211 uint32_t clk_hi;
212 uint32_t clk_lo;
213 uint32_t adr;
214 uint32_t rxfl;
215 uint32_t txfl;
216 uint32_t rxb;
217 uint32_t txb;
218 uint32_t s_tx;
219 uint32_t s_txfl;
220} beagle_i2c;
221
222/* sctlr */
223/* Read System Control Register */
224static inline uint32_t read_sctlr(void)
225{
226 uint32_t ctl;
227
228 asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
229 : [ctl] "=r" (ctl));
230 return ctl;
231}
232
233/* Write System Control Register */
234static inline void write_sctlr(uint32_t ctl)
235{
236 asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
237 : : [ctl] "r" (ctl));
238 isb();
239}
240
241/* Read Auxiliary Control Register */
242static inline uint32_t read_actlr(void)
243{
244 uint32_t ctl;
245
246 asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
247 : [ctl] "=r" (ctl));
248 return ctl;
249}
250
251/* Write Auxiliary Control Register */
252static inline void write_actlr(uint32_t ctl)
253{
254 asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
255 : : [ctl] "r" (ctl));
256 isb();
257}
258
259/* Write Translation Table Base Control Register */
260static inline void write_ttbcr(uint32_t bcr)
261{
262 asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
263 : : [bcr] "r" (bcr));
264
265 isb();
266}
267
268/* Read Domain Access Control Register */
269static inline uint32_t read_dacr(void)
270{
271 uint32_t dacr;
272
273 asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
274 : [dacr] "=r" (dacr));
275
276 return dacr;
277}
278
279
280/* Write Domain Access Control Register */
281static inline void write_dacr(uint32_t dacr)
282{
283 asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
284 : : [dacr] "r" (dacr));
285
286 isb();
287}
288
289static inline void refresh_tlb(void)
290{
291 dsb();
292
293 /* Invalidate entire unified TLB */
294 asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t"
295 : : [zero] "r" (0));
296
297 /* Invalidate all instruction caches to PoU.
298 * Also flushes branch target cache. */
299 asm volatile("mcr p15, 0, %[zero], c7, c5, 0"
300 : : [zero] "r" (0));
301
302 /* Invalidate entire branch predictor array */
303 asm volatile("mcr p15, 0, %[zero], c7, c5, 6"
304 : : [zero] "r" (0)); /* flush BTB */
305
306 dsb();
307 isb();
308}
309
310/* Read Translation Table Base Register 0 */
311static inline uint32_t read_ttbr0(void)
312{
313 uint32_t bar;
314
315 asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
316 : [bar] "=r" (bar));
317
318 return bar & ARM_TTBR_ADDR_MASK;
319}
320
321
322/* Read Translation Table Base Register 0 */
323static inline uint32_t read_ttbr0_unmasked(void)
324{
325 uint32_t bar;
326
327 asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
328 : [bar] "=r" (bar));
329
330 return bar;
331}
332
333/* Write Translation Table Base Register 0 */
334static inline void write_ttbr0(uint32_t bar)
335{
336 dsb();
337 isb();
338 /* In our setup TTBR contains the base address *and* the flags
339 but other pieces of the kernel code expect ttbr to be the
340 base address of the l1 page table. We therefore add the
341 flags here and remove them in the read_ttbr0 */
342 uint32_t v = (bar & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
343 asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
344 : : [bar] "r" (v));
345
346 refresh_tlb();
347}
348
349/* Behaviour on fatal error; default: test-friendly.
350 * set breakpoint to bsp_fatal_extension.
351 */
352/* Enabling BSP_PRESS_KEY_FOR_RESET prevents noninteractive testing */
353/*#define BSP_PRESS_KEY_FOR_RESET 1 */
354#define BSP_PRINT_EXCEPTION_CONTEXT 1
355 /* human-readable exception info */
356#define BSP_RESET_BOARD_AT_EXIT 1
357 /* causes qemu to exit, signaling end of test */
358
364BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void);
365
366/* @} */
367
368#endif /* LIBBSP_ARM_BEAGLE_BSP_H */
beagleboneblack.h
BeagleBone Black BSP definitions.
default-initial-extension.h
DEFAULT_INITIAL_EXTENSION Support.
beagle_setup_mmu_and_cache
BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void)
Beagleboard specific set up of the MMU.
Definition: bspstartmmu.c:39
irq-extension.h
Header file for the Interrupt Manager Extension.
rtems.h
beagle_i2c
Definition: bsp.h:207