RTEMS: The Clock Manager API

| RTEMS 5.4-rc2

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Modules | Typedefs | Enumerations
The Clock Manager API
Board Support Packages » ARM » Intel Cyclone V » Contributed Code

## Modules
| Clock Frequency Control
| Clock Gating Control
| Clock Group Configuration
| Clock Manager Interrupt Management
| Clock Manager Status
| Clock Source Selection
| PLL Bypass Control
| Safe Mode Options

## Typedefs
typedef uint32_t | alt_freq_t
typedef enum ALT_CLK_e | ALT_CLK_t

## Enumerations
enum | ALT_CLK_e { ALT_CLK_IN_PIN_OSC1 , ALT_CLK_IN_PIN_OSC2 , ALT_CLK_F2H_PERIPH_REF , ALT_CLK_F2H_SDRAM_REF , ALT_CLK_IN_PIN_JTAG , ALT_CLK_IN_PIN_ULPI0 , ALT_CLK_IN_PIN_ULPI1 , ALT_CLK_IN_PIN_EMAC0_RX , ALT_CLK_IN_PIN_EMAC1_RX , ALT_CLK_MAIN_PLL , ALT_CLK_PERIPHERAL_PLL , ALT_CLK_SDRAM_PLL , ALT_CLK_OSC1 , ALT_CLK_MAIN_PLL_C0 , ALT_CLK_MAIN_PLL_C1 , ALT_CLK_MAIN_PLL_C2 , ALT_CLK_MAIN_PLL_C3 , ALT_CLK_MAIN_PLL_C4 , ALT_CLK_MAIN_PLL_C5 , ALT_CLK_MPU , ALT_CLK_MPU_L2_RAM , ALT_CLK_MPU_PERIPH , ALT_CLK_L3_MAIN , ALT_CLK_L3_MP , ALT_CLK_L3_SP , ALT_CLK_L4_MAIN , ALT_CLK_L4_MP , ALT_CLK_L4_SP , ALT_CLK_DBG_BASE , ALT_CLK_DBG_AT , ALT_CLK_DBG_TRACE , ALT_CLK_DBG_TIMER , ALT_CLK_DBG , ALT_CLK_MAIN_QSPI , ALT_CLK_MAIN_NAND_SDMMC , ALT_CLK_CFG , ALT_CLK_H2F_USER0 , ALT_CLK_PERIPHERAL_PLL_C0 , ALT_CLK_PERIPHERAL_PLL_C1 , ALT_CLK_PERIPHERAL_PLL_C2 , ALT_CLK_PERIPHERAL_PLL_C3 , ALT_CLK_PERIPHERAL_PLL_C4 , ALT_CLK_PERIPHERAL_PLL_C5 , ALT_CLK_USB_MP , ALT_CLK_SPI_M , ALT_CLK_QSPI , ALT_CLK_NAND_X , ALT_CLK_NAND , ALT_CLK_SDMMC , ALT_CLK_EMAC0 , ALT_CLK_EMAC1 , ALT_CLK_CAN0 , ALT_CLK_CAN1 , ALT_CLK_GPIO_DB , ALT_CLK_H2F_USER1 , ALT_CLK_SDRAM_PLL_C0 , ALT_CLK_SDRAM_PLL_C1 , ALT_CLK_SDRAM_PLL_C2 , ALT_CLK_SDRAM_PLL_C3 , ALT_CLK_SDRAM_PLL_C4 , ALT_CLK_SDRAM_PLL_C5 , ALT_CLK_DDR_DQS , ALT_CLK_DDR_2X_DQS , ALT_CLK_DDR_DQ , ALT_CLK_H2F_USER2 , ALT_CLK_OUT_PIN_EMAC0_TX , ALT_CLK_OUT_PIN_EMAC1_TX , ALT_CLK_OUT_PIN_SDMMC , ALT_CLK_OUT_PIN_I2C0_SCL , ALT_CLK_OUT_PIN_I2C1_SCL , ALT_CLK_OUT_PIN_I2C2_SCL , ALT_CLK_OUT_PIN_I2C3_SCL , ALT_CLK_OUT_PIN_SPIM0 , ALT_CLK_OUT_PIN_SPIM1 , ALT_CLK_OUT_PIN_QSPI , ALT_CLK_UNKNOWN }

## Detailed Description

This module defines the Clock Manager API for accessing, configuring, and controlling the HPS clock resources.

## Typedef Documentation

## ◆ ALT_CLK_t

typedef enum ALT_CLK_e ALT_CLK_t

This type definition enumerates the names of the clock and PLL resources managed by the Clock Manager.

## ◆ alt_freq_t

typedef uint32_t alt_freq_t

This type definition is an opaque type definition for clock frequency values in Hz.

## Enumeration Type Documentation

## ◆ ALT_CLK_e

enum ALT_CLK_e

This type definition enumerates the names of the clock and PLL resources managed by the Clock Manager.

Enumerator
ALT_CLK_IN_PIN_OSC1 | OSC_CLK_1_HPS External oscillator input: Input Pin Clock source to Main PLL Clock source to SDRAM PLL and Peripheral PLL if selected via register write Clock source for clock in safe mode
ALT_CLK_IN_PIN_OSC2 | OSC_CLK_2_HPS External Oscillator input: Input Pin Optional clock source to SDRAM PLL and Peripheral PLL if selected Typically used for Ethernet reference clock
ALT_CLK_IN_PIN_JTAG | JTAG_TCK_HPS Input Pin External HPS JTAG clock input.
ALT_CLK_IN_PIN_ULPI0 | ULPI0_CLK ULPI Clock provided by external USB0 PHY Input Pin
ALT_CLK_IN_PIN_ULPI1 | ULPI1_CLK ULPI Clock provided by external USB1 PHY Input Pin
ALT_CLK_IN_PIN_EMAC0_RX | EMAC0:RX_CLK Rx Reference Clock for EMAC0 Input Pin
ALT_CLK_IN_PIN_EMAC1_RX | EMAC1:RX_CLK Rx Reference Clock for EMAC1 Input Pin
ALT_CLK_MAIN_PLL | main_pll_ref_clkin Main PLL input reference clock, used to designate the Main PLL in PLL clock selections.
ALT_CLK_PERIPHERAL_PLL | periph_pll_ref_clkin Peripheral PLL input reference clock, used to designate the Peripheral PLL in PLL clock selections.
ALT_CLK_SDRAM_PLL | sdram_pll_ref_clkin SDRAM PLL input reference clock, used to designate the SDRAM PLL in PLL clock selections.
ALT_CLK_OSC1 | osc1_clk OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived directly from the osc_clk_1_HPS pin. alias for ALT_CLK_IN_PIN_OSC1
ALT_CLK_MAIN_PLL_C0 | Main PLL C0 Output
ALT_CLK_MAIN_PLL_C1 | Main PLL C1 Output
ALT_CLK_MAIN_PLL_C2 | Main PLL C2 Output
ALT_CLK_MAIN_PLL_C3 | Main PLL C3 Output
ALT_CLK_MAIN_PLL_C4 | Main PLL C4 Output
ALT_CLK_MAIN_PLL_C5 | Main PLL C5 Output
ALT_CLK_MPU | mpu_clk Main PLL C0 Output. Clock for MPU subsystem, including CPU0 and CPU1. Alias for ALT_CLK_MAIN_PLL_C0
ALT_CLK_MPU_L2_RAM | mpu_l2_ram_clk Clock for MPU level 2 (L2) RAM
ALT_CLK_MPU_PERIPH | mpu_periph_clk Clock for MPU snoop control unit (SCU) peripherals, such as the general interrupt controller (GIC)
ALT_CLK_L3_MAIN | main_clk Main PLL C1 Output Alias for ALT_CLK_MAIN_PLL_C1
ALT_CLK_L3_MP | l3_mp_clk Clock for L3 Master Peripheral Switch
ALT_CLK_L3_SP | l3_sp_clk Clock for L3 Slave Peripheral Switch
ALT_CLK_L4_MAIN | l4_main_clk Clock for L4 main bus Clock for DMA Clock for SPI masters
ALT_CLK_L4_MP | l4_mp_clk Clock for L4 master peripherals (MP) bus
ALT_CLK_L4_SP | l4_sp_clk Clock for L4 slave peripherals (SP) bus
ALT_CLK_DBG_BASE | dbg_base_clk Main PLL C2 Output Alias for ALT_CLK_MAIN_PLL_C2
ALT_CLK_DBG_AT | dbg_at_clk Clock for CoreSight debug Advanced Microcontroller Bus Architecture (AMBA) Trace Bus (ATB)
ALT_CLK_DBG_TRACE | dbg_trace_clk Clock for CoreSight debug Trace Port Interface Unit (TPIU)
ALT_CLK_DBG_TIMER | dbg_timer_clk Clock for the trace timestamp generator
ALT_CLK_DBG | dbg_clk Clock for Debug Access Port (DAP) and debug Advanced Peripheral Bus (APB)
ALT_CLK_MAIN_QSPI | main_qspi_clk Main PLL C3 Output. Quad SPI flash internal logic clock. Alias for ALT_CLK_MAIN_PLL_C3
ALT_CLK_MAIN_NAND_SDMMC | main_nand_sdmmc_clk Main PLL C4 Output. Input clock to flash controller clocks block. Alias for ALT_CLK_MAIN_PLL_C4
ALT_CLK_CFG | cfg_clk FPGA manager configuration clock.
ALT_CLK_H2F_USER0 | h2f_user0_clock Clock to FPGA fabric
ALT_CLK_PERIPHERAL_PLL_C0 | Peripheral PLL C0 Output
ALT_CLK_PERIPHERAL_PLL_C1 | Peripheral PLL C1 Output
ALT_CLK_PERIPHERAL_PLL_C2 | Peripheral PLL C2 Output
ALT_CLK_PERIPHERAL_PLL_C3 | Peripheral PLL C3 Output
ALT_CLK_PERIPHERAL_PLL_C4 | Peripheral PLL C4 Output
ALT_CLK_PERIPHERAL_PLL_C5 | Peripheral PLL C5 Output
ALT_CLK_USB_MP | usb_mp_clk Clock for USB
ALT_CLK_SPI_M | spi_m_clk Clock for L4 SPI master bus
ALT_CLK_QSPI | qspi_clk Clock for Quad SPI
ALT_CLK_NAND_X | nand_x_clk NAND flash controller master and slave clock
ALT_CLK_NAND | nand_clk Main clock for NAND flash controller
ALT_CLK_SDMMC | sdmmc_clk Clock for SD/MMC logic input clock
ALT_CLK_EMAC0 | emac0_clk EMAC 0 clock - Peripheral PLL C0 Output Alias for ALT_CLK_PERIPHERAL_PLL_C0
ALT_CLK_EMAC1 | emac1_clk EMAC 1 clock - Peripheral PLL C1 Output Alias for ALT_CLK_PERIPHERAL_PLL_C1
ALT_CLK_CAN0 | can0_clk Controller area network (CAN) controller 0 clock
ALT_CLK_CAN1 | can1_clk Controller area network (CAN) controller 1 clock
ALT_CLK_GPIO_DB | gpio_db_clk Debounce clock for GPIO0, GPIO1, and GPIO2
ALT_CLK_H2F_USER1 | h2f_user1_clock Clock to FPGA fabric - Peripheral PLL C5 Output Alias for ALT_CLK_PERIPHERAL_PLL_C5
ALT_CLK_SDRAM_PLL_C0 | SDRAM PLL C0 Output
ALT_CLK_SDRAM_PLL_C1 | SDRAM PLL C1 Output
ALT_CLK_SDRAM_PLL_C2 | SDRAM PLL C2 Output
ALT_CLK_SDRAM_PLL_C3 | SDRAM PLL C3 Output
ALT_CLK_SDRAM_PLL_C4 | SDRAM PLL C4 Output
ALT_CLK_SDRAM_PLL_C5 | SDRAM PLL C5 Output
ALT_CLK_DDR_DQS | ddr_dqs_clk Clock for MPFE, single-port controller, CSR access, and PHY - SDRAM PLL C0 Output Alias for ALT_CLK_SDRAM_PLL_C0
ALT_CLK_DDR_2X_DQS | ddr_2x_dqs_clk Clock for PHY - SDRAM PLL C1 Output Alias for ALT_CLK_SDRAM_PLL_C1
ALT_CLK_DDR_DQ | ddr_dq_clk Clock for PHY - SDRAM PLL C2 Output Alias for ALT_CLK_SDRAM_PLL_C2
ALT_CLK_H2F_USER2 | h2f_user2_clock Clock to FPGA fabric - SDRAM PLL C5 Output Alias for ALT_CLK_SDRAM_PLL_C5
ALT_CLK_OUT_PIN_EMAC0_TX | EMAC0:TX_CLK Tx Reference Clock for EMAC0 Output Pin
ALT_CLK_OUT_PIN_EMAC1_TX | EMAC1:TX_CLK Tx Reference Clock for EMAC1 Output Pin
ALT_CLK_OUT_PIN_SDMMC | SDMMC:CLK SD/MMC Card Clock Output Pin
ALT_CLK_OUT_PIN_I2C0_SCL | I2C0:SCL I2C Clock for I2C0 Output Pin
ALT_CLK_OUT_PIN_I2C1_SCL | I2C1:SCL I2C Clock for I2C1 Output Pin
ALT_CLK_OUT_PIN_I2C2_SCL | I2C2:SCL I2C Clock for I2C2/2 wire Output Pin
ALT_CLK_OUT_PIN_I2C3_SCL | I2C3:SCL I2C Clock for I2C1/2 wire Output Pin
ALT_CLK_OUT_PIN_SPIM0 | SPIM0:CLK SPI Clock Output Pin
ALT_CLK_OUT_PIN_SPIM1 | SPIM1:CLK SPI Clock Output Pin
ALT_CLK_OUT_PIN_QSPI | QSPI:CLK QSPI Flash Clock Output Pin