RTEMS: cpukit/include/pci/pcireg.h Source File

| RTEMS 5.4-rc2

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pcireg.h
1/*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * New PCI library written from scratch. Defines in this file was taken from
6 * FreeBSD commit f1d6f4778d2044502209708bc167c05f9aa48615.
7 * auto-generated pci_ids.h also reused from RTEMS.
8 * Copyright 2009, Cobham Gaisler AB
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice unmodified, this list of conditions, and the following
15 * disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * $FreeBSD$
32 *
33 */
34
35#ifndef __PCI_REG_H__
36#define __PCI_REG_H__
37
38/*
39 * PCIM_xxx: mask to locate subfield in register
40 * PCIR_xxx: config register offset
41 * PCIC_xxx: device class
42 * PCIS_xxx: device subclass
43 * PCIP_xxx: device programming interface
44 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
45 * PCID_xxx: device ID
46 * PCIY_xxx: capability identification number
47 * PCIZ_xxx: extended capability identification number
48 */
49
50/* some PCI bus constants */
51#define PCI_DOMAINMAX 65535 /* highest supported domain number */
52#define PCI_BUSMAX 255 /* highest supported bus number */
53#define PCI_SLOTMAX 31 /* highest supported slot number */
54#define PCI_FUNCMAX 7 /* highest supported function number */
55#define PCI_REGMAX 255 /* highest supported config register addr. */
56#define PCIE_REGMAX 4095 /* highest supported config register addr. */
57#define PCI_MAXHDRTYPE 2
58
59#define PCIE_ARI_SLOTMAX 0
60#define PCIE_ARI_FUNCMAX 255
61
62#define PCI_RID_BUS_SHIFT 8
63#define PCI_RID_SLOT_SHIFT 3
64#define PCI_RID_FUNC_SHIFT 0
65
66#define PCI_RID(bus, slot, func) \
67 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \
68 (((slot) & PCI_SLOTMAX) << PCI_RID_SLOT_SHIFT) | \
69 (((func) & PCI_FUNCMAX) << PCI_RID_FUNC_SHIFT))
70
71#define PCI_ARI_RID(bus, func) \
72 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \
73 (((func) & PCIE_ARI_FUNCMAX) << PCI_RID_FUNC_SHIFT))
74
75#define PCI_RID2BUS(rid) (((rid) >> PCI_RID_BUS_SHIFT) & PCI_BUSMAX)
76#define PCI_RID2SLOT(rid) (((rid) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX)
77#define PCI_RID2FUNC(rid) (((rid) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX)
78
79#define PCIE_ARI_SLOT(func) (((func) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX)
80#define PCIE_ARI_FUNC(func) (((func) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX)
81
82/* PCI config header registers for all devices */
83
84#define PCIR_DEVVENDOR 0x00
85#define PCIR_VENDOR 0x00
86#define PCIR_DEVICE 0x02
87#define PCIR_COMMAND 0x04
88#define PCIM_CMD_PORTEN 0x0001
89#define PCIM_CMD_MEMEN 0x0002
90#define PCIM_CMD_BUSMASTEREN 0x0004
91#define PCIM_CMD_SPECIALEN 0x0008
92#define PCIM_CMD_MWRICEN 0x0010
93#define PCIM_CMD_PERRESPEN 0x0040
94#define PCIM_CMD_SERRESPEN 0x0100
95#define PCIM_CMD_BACKTOBACK 0x0200
96#define PCIM_CMD_INTxDIS 0x0400
97#define PCIR_STATUS 0x06
98#define PCIM_STATUS_INTxSTATE 0x0008
99#define PCIM_STATUS_CAPPRESENT 0x0010
100#define PCIM_STATUS_66CAPABLE 0x0020
101#define PCIM_STATUS_BACKTOBACK 0x0080
102#define PCIM_STATUS_MDPERR 0x0100
103#define PCIM_STATUS_SEL_FAST 0x0000
104#define PCIM_STATUS_SEL_MEDIMUM 0x0200
105#define PCIM_STATUS_SEL_SLOW 0x0400
106#define PCIM_STATUS_SEL_MASK 0x0600
107#define PCIM_STATUS_STABORT 0x0800
108#define PCIM_STATUS_RTABORT 0x1000
109#define PCIM_STATUS_RMABORT 0x2000
110#define PCIM_STATUS_SERR 0x4000
111#define PCIM_STATUS_PERR 0x8000
112#define PCIR_REVID 0x08
113#define PCIR_PROGIF 0x09
114#define PCIR_SUBCLASS 0x0a
115#define PCIR_CLASS 0x0b
116#define PCIR_CACHELNSZ 0x0c
117#define PCIR_LATTIMER 0x0d
118#define PCIR_HDRTYPE 0x0e
119#define PCIM_HDRTYPE 0x7f
120#define PCIM_HDRTYPE_NORMAL 0x00
121#define PCIM_HDRTYPE_BRIDGE 0x01
122#define PCIM_HDRTYPE_CARDBUS 0x02
123#define PCIM_MFDEV 0x80
124#define PCIR_BIST 0x0f
125
126/* Capability Register Offsets */
127
128#define PCICAP_ID 0x0
129#define PCICAP_NEXTPTR 0x1
130
131/* Capability Identification Numbers */
132
133#define PCIY_PMG 0x01 /* PCI Power Management */
134#define PCIY_AGP 0x02 /* AGP */
135#define PCIY_VPD 0x03 /* Vital Product Data */
136#define PCIY_SLOTID 0x04 /* Slot Identification */
137#define PCIY_MSI 0x05 /* Message Signaled Interrupts */
138#define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */
139#define PCIY_PCIX 0x07 /* PCI-X */
140#define PCIY_HT 0x08 /* HyperTransport */
141#define PCIY_VENDOR 0x09 /* Vendor Unique */
142#define PCIY_DEBUG 0x0a /* Debug port */
143#define PCIY_CRES 0x0b /* CompactPCI central resource control */
144#define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */
145#define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */
146#define PCIY_AGP8X 0x0e /* AGP 8x */
147#define PCIY_SECDEV 0x0f /* Secure Device */
148#define PCIY_EXPRESS 0x10 /* PCI Express */
149#define PCIY_MSIX 0x11 /* MSI-X */
150#define PCIY_SATA 0x12 /* SATA */
151#define PCIY_PCIAF 0x13 /* PCI Advanced Features */
152
153/* Extended Capability Register Fields */
154
155#define PCIR_EXTCAP 0x100
156#define PCIM_EXTCAP_ID 0x0000ffff
157#define PCIM_EXTCAP_VER 0x000f0000
158#define PCIM_EXTCAP_NEXTPTR 0xfff00000
159#define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID)
160#define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16)
161#define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20)
162
163/* Extended Capability Identification Numbers */
164
165#define PCIZ_AER 0x0001 /* Advanced Error Reporting */
166#define PCIZ_VC 0x0002 /* Virtual Channel if MFVC Ext Cap not set */
167#define PCIZ_SERNUM 0x0003 /* Device Serial Number */
168#define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */
169#define PCIZ_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */
170#define PCIZ_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */
171#define PCIZ_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */
172#define PCIZ_MFVC 0x0008 /* Multi-Function Virtual Channel */
173#define PCIZ_VC2 0x0009 /* Virtual Channel if MFVC Ext Cap set */
174#define PCIZ_RCRB 0x000a /* RCRB Header */
175#define PCIZ_VENDOR 0x000b /* Vendor Unique */
176#define PCIZ_CAC 0x000c /* Configuration Access Correction -- obsolete */
177#define PCIZ_ACS 0x000d /* Access Control Services */
178#define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */
179#define PCIZ_ATS 0x000f /* Address Translation Services */
180#define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */
181#define PCIZ_MRIOV 0x0011 /* Multiple Root IO Virtualization */
182#define PCIZ_MULTICAST 0x0012 /* Multicast */
183#define PCIZ_PAGE_REQ 0x0013 /* Page Request */
184#define PCIZ_AMD 0x0014 /* Reserved for AMD */
185#define PCIZ_RESIZE_BAR 0x0015 /* Resizable BAR */
186#define PCIZ_DPA 0x0016 /* Dynamic Power Allocation */
187#define PCIZ_TPH_REQ 0x0017 /* TPH Requester */
188#define PCIZ_LTR 0x0018 /* Latency Tolerance Reporting */
189#define PCIZ_SEC_PCIE 0x0019 /* Secondary PCI Express */
190#define PCIZ_PMUX 0x001a /* Protocol Multiplexing */
191#define PCIZ_PASID 0x001b /* Process Address Space ID */
192#define PCIZ_LN_REQ 0x001c /* LN Requester */
193#define PCIZ_DPC 0x001d /* Downstream Porto Containment */
194#define PCIZ_L1PM 0x001e /* L1 PM Substates */
195
196/* config registers for header type 0 devices */
197
198#define PCIR_BARS 0x10
199#define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
200#define PCIR_MAX_BAR_0 5
201#define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4)
202#define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)
203#define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)
204#define PCIM_BAR_SPACE 0x00000001
205#define PCIM_BAR_MEM_SPACE 0
206#define PCIM_BAR_IO_SPACE 1
207#define PCIM_BAR_MEM_TYPE 0x00000006
208#define PCIM_BAR_MEM_32 0
209#define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */
210#define PCIM_BAR_MEM_64 4
211#define PCIM_BAR_MEM_PREFETCH 0x00000008
212#define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL
213#define PCIM_BAR_IO_RESERVED 0x00000002
214#define PCIM_BAR_IO_BASE 0xfffffffc
215#define PCIR_CIS 0x28
216#define PCIM_CIS_ASI_MASK 0x00000007
217#define PCIM_CIS_ASI_CONFIG 0
218#define PCIM_CIS_ASI_BAR0 1
219#define PCIM_CIS_ASI_BAR1 2
220#define PCIM_CIS_ASI_BAR2 3
221#define PCIM_CIS_ASI_BAR3 4
222#define PCIM_CIS_ASI_BAR4 5
223#define PCIM_CIS_ASI_BAR5 6
224#define PCIM_CIS_ASI_ROM 7
225#define PCIM_CIS_ADDR_MASK 0x0ffffff8
226#define PCIM_CIS_ROM_MASK 0xf0000000
227#define PCIM_CIS_CONFIG_MASK 0xff
228#define PCIR_SUBVEND_0 0x2c
229#define PCIR_SUBDEV_0 0x2e
230#define PCIR_BIOS 0x30
231#define PCIM_BIOS_ENABLE 0x01
232#define PCIM_BIOS_ADDR_MASK 0xfffff800
233#define PCIR_CAP_PTR 0x34
234#define PCIR_INTLINE 0x3c
235#define PCIR_INTPIN 0x3d
236#define PCIR_MINGNT 0x3e
237#define PCIR_MAXLAT 0x3f
238
239/* config registers for header type 1 (PCI-to-PCI bridge) devices */
240
241#define PCIR_MAX_BAR_1 1
242#define PCIR_SECSTAT_1 0x1e
243
244#define PCIR_PRIBUS_1 0x18
245#define PCIR_SECBUS_1 0x19
246#define PCIR_SUBBUS_1 0x1a
247#define PCIR_SECLAT_1 0x1b
248
249#define PCIR_IOBASEL_1 0x1c
250#define PCIR_IOLIMITL_1 0x1d
251#define PCIR_IOBASEH_1 0x30
252#define PCIR_IOLIMITH_1 0x32
253#define PCIM_BRIO_16 0x0
254#define PCIM_BRIO_32 0x1
255#define PCIM_BRIO_MASK 0xf
256
257#define PCIR_MEMBASE_1 0x20
258#define PCIR_MEMLIMIT_1 0x22
259
260#define PCIR_PMBASEL_1 0x24
261#define PCIR_PMLIMITL_1 0x26
262#define PCIR_PMBASEH_1 0x28
263#define PCIR_PMLIMITH_1 0x2c
264#define PCIM_BRPM_32 0x0
265#define PCIM_BRPM_64 0x1
266#define PCIM_BRPM_MASK 0xf
267
268#define PCIR_BIOS_1 0x38
269#define PCIR_BRIDGECTL_1 0x3e
270
271/* config registers for header type 2 (CardBus) devices */
272
273#define PCIR_MAX_BAR_2 0
274#define PCIR_CAP_PTR_2 0x14
275#define PCIR_SECSTAT_2 0x16
276
277#define PCIR_PRIBUS_2 0x18
278#define PCIR_SECBUS_2 0x19
279#define PCIR_SUBBUS_2 0x1a
280#define PCIR_SECLAT_2 0x1b
281
282#define PCIR_MEMBASE0_2 0x1c
283#define PCIR_MEMLIMIT0_2 0x20
284#define PCIR_MEMBASE1_2 0x24
285#define PCIR_MEMLIMIT1_2 0x28
286#define PCIR_IOBASE0_2 0x2c
287#define PCIR_IOLIMIT0_2 0x30
288#define PCIR_IOBASE1_2 0x34
289#define PCIR_IOLIMIT1_2 0x38
290
291#define PCIR_BRIDGECTL_2 0x3e
292
293#define PCIR_SUBVEND_2 0x40
294#define PCIR_SUBDEV_2 0x42
295
296#define PCIR_PCCARDIF_2 0x44
297
298/* PCI device class, subclass and programming interface definitions */
299
300#define PCIC_OLD 0x00
301#define PCIS_OLD_NONVGA 0x00
302#define PCIS_OLD_VGA 0x01
303
304#define PCIC_STORAGE 0x01
305#define PCIS_STORAGE_SCSI 0x00
306#define PCIS_STORAGE_IDE 0x01
307#define PCIP_STORAGE_IDE_MODEPRIM 0x01
308#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02
309#define PCIP_STORAGE_IDE_MODESEC 0x04
310#define PCIP_STORAGE_IDE_PROGINDSEC 0x08
311#define PCIP_STORAGE_IDE_MASTERDEV 0x80
312#define PCIS_STORAGE_FLOPPY 0x02
313#define PCIS_STORAGE_IPI 0x03
314#define PCIS_STORAGE_RAID 0x04
315#define PCIS_STORAGE_ATA_ADMA 0x05
316#define PCIS_STORAGE_SATA 0x06
317#define PCIP_STORAGE_SATA_AHCI_1_0 0x01
318#define PCIS_STORAGE_SAS 0x07
319#define PCIS_STORAGE_NVM 0x08
320#define PCIP_STORAGE_NVM_NVMHCI_1_0 0x01
321#define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0 0x02
322#define PCIS_STORAGE_OTHER 0x80
323
324#define PCIC_NETWORK 0x02
325#define PCIS_NETWORK_ETHERNET 0x00
326#define PCIS_NETWORK_TOKENRING 0x01
327#define PCIS_NETWORK_FDDI 0x02
328#define PCIS_NETWORK_ATM 0x03
329#define PCIS_NETWORK_ISDN 0x04
330#define PCIS_NETWORK_WORLDFIP 0x05
331#define PCIS_NETWORK_PICMG 0x06
332#define PCIS_NETWORK_OTHER 0x80
333
334#define PCIC_DISPLAY 0x03
335#define PCIS_DISPLAY_VGA 0x00
336#define PCIS_DISPLAY_XGA 0x01
337#define PCIS_DISPLAY_3D 0x02
338#define PCIS_DISPLAY_OTHER 0x80
339
340#define PCIC_MULTIMEDIA 0x04
341#define PCIS_MULTIMEDIA_VIDEO 0x00
342#define PCIS_MULTIMEDIA_AUDIO 0x01
343#define PCIS_MULTIMEDIA_TELE 0x02
344#define PCIS_MULTIMEDIA_HDA 0x03
345#define PCIS_MULTIMEDIA_OTHER 0x80
346
347#define PCIC_MEMORY 0x05
348#define PCIS_MEMORY_RAM 0x00
349#define PCIS_MEMORY_FLASH 0x01
350#define PCIS_MEMORY_OTHER 0x80
351
352#define PCIC_BRIDGE 0x06
353#define PCIS_BRIDGE_HOST 0x00
354#define PCIS_BRIDGE_ISA 0x01
355#define PCIS_BRIDGE_EISA 0x02
356#define PCIS_BRIDGE_MCA 0x03
357#define PCIS_BRIDGE_PCI 0x04
358#define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01
359#define PCIS_BRIDGE_PCMCIA 0x05
360#define PCIS_BRIDGE_NUBUS 0x06
361#define PCIS_BRIDGE_CARDBUS 0x07
362#define PCIS_BRIDGE_RACEWAY 0x08
363#define PCIS_BRIDGE_PCI_TRANSPARENT 0x09
364#define PCIS_BRIDGE_INFINIBAND 0x0a
365#define PCIS_BRIDGE_OTHER 0x80
366
367#define PCIC_SIMPLECOMM 0x07
368#define PCIS_SIMPLECOMM_UART 0x00
369#define PCIP_SIMPLECOMM_UART_8250 0x00
370#define PCIP_SIMPLECOMM_UART_16450A 0x01
371#define PCIP_SIMPLECOMM_UART_16550A 0x02
372#define PCIP_SIMPLECOMM_UART_16650A 0x03
373#define PCIP_SIMPLECOMM_UART_16750A 0x04
374#define PCIP_SIMPLECOMM_UART_16850A 0x05
375#define PCIP_SIMPLECOMM_UART_16950A 0x06
376#define PCIS_SIMPLECOMM_PAR 0x01
377#define PCIS_SIMPLECOMM_MULSER 0x02
378#define PCIS_SIMPLECOMM_MODEM 0x03
379#define PCIS_SIMPLECOMM_GPIB 0x04
380#define PCIS_SIMPLECOMM_SMART_CARD 0x05
381#define PCIS_SIMPLECOMM_OTHER 0x80
382
383#define PCIC_BASEPERIPH 0x08
384#define PCIS_BASEPERIPH_PIC 0x00
385#define PCIP_BASEPERIPH_PIC_8259A 0x00
386#define PCIP_BASEPERIPH_PIC_ISA 0x01
387#define PCIP_BASEPERIPH_PIC_EISA 0x02
388#define PCIP_BASEPERIPH_PIC_IO_APIC 0x10
389#define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20
390#define PCIS_BASEPERIPH_DMA 0x01
391#define PCIS_BASEPERIPH_TIMER 0x02
392#define PCIS_BASEPERIPH_RTC 0x03
393#define PCIS_BASEPERIPH_PCIHOT 0x04
394#define PCIS_BASEPERIPH_SDHC 0x05
395#define PCIS_BASEPERIPH_IOMMU 0x06
396#define PCIS_BASEPERIPH_OTHER 0x80
397
398#define PCIC_INPUTDEV 0x09
399#define PCIS_INPUTDEV_KEYBOARD 0x00
400#define PCIS_INPUTDEV_DIGITIZER 0x01
401#define PCIS_INPUTDEV_MOUSE 0x02
402#define PCIS_INPUTDEV_SCANNER 0x03
403#define PCIS_INPUTDEV_GAMEPORT 0x04
404#define PCIS_INPUTDEV_OTHER 0x80
405
406#define PCIC_DOCKING 0x0a
407#define PCIS_DOCKING_GENERIC 0x00
408#define PCIS_DOCKING_OTHER 0x80
409
410#define PCIC_PROCESSOR 0x0b
411#define PCIS_PROCESSOR_386 0x00
412#define PCIS_PROCESSOR_486 0x01
413#define PCIS_PROCESSOR_PENTIUM 0x02
414#define PCIS_PROCESSOR_ALPHA 0x10
415#define PCIS_PROCESSOR_POWERPC 0x20
416#define PCIS_PROCESSOR_MIPS 0x30
417#define PCIS_PROCESSOR_COPROC 0x40
418
419#define PCIC_SERIALBUS 0x0c
420#define PCIS_SERIALBUS_FW 0x00
421#define PCIS_SERIALBUS_ACCESS 0x01
422#define PCIS_SERIALBUS_SSA 0x02
423#define PCIS_SERIALBUS_USB 0x03
424#define PCIP_SERIALBUS_USB_UHCI 0x00
425#define PCIP_SERIALBUS_USB_OHCI 0x10
426#define PCIP_SERIALBUS_USB_EHCI 0x20
427#define PCIP_SERIALBUS_USB_XHCI 0x30
428#define PCIP_SERIALBUS_USB_DEVICE 0xfe
429#define PCIS_SERIALBUS_FC 0x04
430#define PCIS_SERIALBUS_SMBUS 0x05
431#define PCIS_SERIALBUS_INFINIBAND 0x06
432#define PCIS_SERIALBUS_IPMI 0x07
433#define PCIP_SERIALBUS_IPMI_SMIC 0x00
434#define PCIP_SERIALBUS_IPMI_KCS 0x01
435#define PCIP_SERIALBUS_IPMI_BT 0x02
436#define PCIS_SERIALBUS_SERCOS 0x08
437#define PCIS_SERIALBUS_CANBUS 0x09
438
439#define PCIC_WIRELESS 0x0d
440#define PCIS_WIRELESS_IRDA 0x00
441#define PCIS_WIRELESS_IR 0x01
442#define PCIS_WIRELESS_RF 0x10
443#define PCIS_WIRELESS_BLUETOOTH 0x11
444#define PCIS_WIRELESS_BROADBAND 0x12
445#define PCIS_WIRELESS_80211A 0x20
446#define PCIS_WIRELESS_80211B 0x21
447#define PCIS_WIRELESS_OTHER 0x80
448
449#define PCIC_INTELLIIO 0x0e
450#define PCIS_INTELLIIO_I2O 0x00
451
452#define PCIC_SATCOM 0x0f
453#define PCIS_SATCOM_TV 0x01
454#define PCIS_SATCOM_AUDIO 0x02
455#define PCIS_SATCOM_VOICE 0x03
456#define PCIS_SATCOM_DATA 0x04
457
458#define PCIC_CRYPTO 0x10
459#define PCIS_CRYPTO_NETCOMP 0x00
460#define PCIS_CRYPTO_ENTERTAIN 0x10
461#define PCIS_CRYPTO_OTHER 0x80
462
463#define PCIC_DASP 0x11
464#define PCIS_DASP_DPIO 0x00
465#define PCIS_DASP_PERFCNTRS 0x01
466#define PCIS_DASP_COMM_SYNC 0x10
467#define PCIS_DASP_MGMT_CARD 0x20
468#define PCIS_DASP_OTHER 0x80
469
470#define PCIC_OTHER 0xff
471
472/* Bridge Control Values. */
473#define PCIB_BCR_PERR_ENABLE 0x0001
474#define PCIB_BCR_SERR_ENABLE 0x0002
475#define PCIB_BCR_ISA_ENABLE 0x0004
476#define PCIB_BCR_VGA_ENABLE 0x0008
477#define PCIB_BCR_MASTER_ABORT_MODE 0x0020
478#define PCIB_BCR_SECBUS_RESET 0x0040
479#define PCIB_BCR_SECBUS_BACKTOBACK 0x0080
480#define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100
481#define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200
482#define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400
483#define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800
484
485/* PCI power manangement */
486#define PCIR_POWER_CAP 0x2
487#define PCIM_PCAP_SPEC 0x0007
488#define PCIM_PCAP_PMEREQCLK 0x0008
489#define PCIM_PCAP_DEVSPECINIT 0x0020
490#define PCIM_PCAP_AUXPWR_0 0x0000
491#define PCIM_PCAP_AUXPWR_55 0x0040
492#define PCIM_PCAP_AUXPWR_100 0x0080
493#define PCIM_PCAP_AUXPWR_160 0x00c0
494#define PCIM_PCAP_AUXPWR_220 0x0100
495#define PCIM_PCAP_AUXPWR_270 0x0140
496#define PCIM_PCAP_AUXPWR_320 0x0180
497#define PCIM_PCAP_AUXPWR_375 0x01c0
498#define PCIM_PCAP_AUXPWRMASK 0x01c0
499#define PCIM_PCAP_D1SUPP 0x0200
500#define PCIM_PCAP_D2SUPP 0x0400
501#define PCIM_PCAP_D0PME 0x0800
502#define PCIM_PCAP_D1PME 0x1000
503#define PCIM_PCAP_D2PME 0x2000
504#define PCIM_PCAP_D3PME_HOT 0x4000
505#define PCIM_PCAP_D3PME_COLD 0x8000
506
507#define PCIR_POWER_STATUS 0x4
508#define PCIM_PSTAT_D0 0x0000
509#define PCIM_PSTAT_D1 0x0001
510#define PCIM_PSTAT_D2 0x0002
511#define PCIM_PSTAT_D3 0x0003
512#define PCIM_PSTAT_DMASK 0x0003
513#define PCIM_PSTAT_NOSOFTRESET 0x0008
514#define PCIM_PSTAT_PMEENABLE 0x0100
515#define PCIM_PSTAT_D0POWER 0x0000
516#define PCIM_PSTAT_D1POWER 0x0200
517#define PCIM_PSTAT_D2POWER 0x0400
518#define PCIM_PSTAT_D3POWER 0x0600
519#define PCIM_PSTAT_D0HEAT 0x0800
520#define PCIM_PSTAT_D1HEAT 0x0a00
521#define PCIM_PSTAT_D2HEAT 0x0c00
522#define PCIM_PSTAT_D3HEAT 0x0e00
523#define PCIM_PSTAT_DATASELMASK 0x1e00
524#define PCIM_PSTAT_DATAUNKN 0x0000
525#define PCIM_PSTAT_DATADIV10 0x2000
526#define PCIM_PSTAT_DATADIV100 0x4000
527#define PCIM_PSTAT_DATADIV1000 0x6000
528#define PCIM_PSTAT_DATADIVMASK 0x6000
529#define PCIM_PSTAT_PME 0x8000
530
531#define PCIR_POWER_BSE 0x6
532#define PCIM_PMCSR_BSE_D3B3 0x00
533#define PCIM_PMCSR_BSE_D3B2 0x40
534#define PCIM_PMCSR_BSE_BPCCE 0x80
535
536#define PCIR_POWER_DATA 0x7
537
538/* VPD capability registers */
539#define PCIR_VPD_ADDR 0x2
540#define PCIR_VPD_DATA 0x4
541
542/* PCI Message Signalled Interrupts (MSI) */
543#define PCIR_MSI_CTRL 0x2
544#define PCIM_MSICTRL_VECTOR 0x0100
545#define PCIM_MSICTRL_64BIT 0x0080
546#define PCIM_MSICTRL_MME_MASK 0x0070
547#define PCIM_MSICTRL_MME_1 0x0000
548#define PCIM_MSICTRL_MME_2 0x0010
549#define PCIM_MSICTRL_MME_4 0x0020
550#define PCIM_MSICTRL_MME_8 0x0030
551#define PCIM_MSICTRL_MME_16 0x0040
552#define PCIM_MSICTRL_MME_32 0x0050
553#define PCIM_MSICTRL_MMC_MASK 0x000E
554#define PCIM_MSICTRL_MMC_1 0x0000
555#define PCIM_MSICTRL_MMC_2 0x0002
556#define PCIM_MSICTRL_MMC_4 0x0004
557#define PCIM_MSICTRL_MMC_8 0x0006
558#define PCIM_MSICTRL_MMC_16 0x0008
559#define PCIM_MSICTRL_MMC_32 0x000A
560#define PCIM_MSICTRL_MSI_ENABLE 0x0001
561#define PCIR_MSI_ADDR 0x4
562#define PCIR_MSI_ADDR_HIGH 0x8
563#define PCIR_MSI_DATA 0x8
564#define PCIR_MSI_DATA_64BIT 0xc
565#define PCIR_MSI_MASK 0x10
566#define PCIR_MSI_PENDING 0x14
567
568/* PCI-X definitions */
569
570/* For header type 0 devices */
571#define PCIXR_COMMAND 0x2
572#define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */
573#define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
574#define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */
575#define PCIXM_COMMAND_MAX_READ_512 0x0000
576#define PCIXM_COMMAND_MAX_READ_1024 0x0004
577#define PCIXM_COMMAND_MAX_READ_2048 0x0008
578#define PCIXM_COMMAND_MAX_READ_4096 0x000c
579#define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */
580#define PCIXM_COMMAND_MAX_SPLITS_1 0x0000
581#define PCIXM_COMMAND_MAX_SPLITS_2 0x0010
582#define PCIXM_COMMAND_MAX_SPLITS_3 0x0020
583#define PCIXM_COMMAND_MAX_SPLITS_4 0x0030
584#define PCIXM_COMMAND_MAX_SPLITS_8 0x0040
585#define PCIXM_COMMAND_MAX_SPLITS_12 0x0050
586#define PCIXM_COMMAND_MAX_SPLITS_16 0x0060
587#define PCIXM_COMMAND_MAX_SPLITS_32 0x0070
588#define PCIXM_COMMAND_VERSION 0x3000
589#define PCIXR_STATUS 0x4
590#define PCIXM_STATUS_DEVFN 0x000000FF
591#define PCIXM_STATUS_BUS 0x0000FF00
592#define PCIXM_STATUS_64BIT 0x00010000
593#define PCIXM_STATUS_133CAP 0x00020000
594#define PCIXM_STATUS_SC_DISCARDED 0x00040000
595#define PCIXM_STATUS_UNEXP_SC 0x00080000
596#define PCIXM_STATUS_COMPLEX_DEV 0x00100000
597#define PCIXM_STATUS_MAX_READ 0x00600000
598#define PCIXM_STATUS_MAX_READ_512 0x00000000
599#define PCIXM_STATUS_MAX_READ_1024 0x00200000
600#define PCIXM_STATUS_MAX_READ_2048 0x00400000
601#define PCIXM_STATUS_MAX_READ_4096 0x00600000
602#define PCIXM_STATUS_MAX_SPLITS 0x03800000
603#define PCIXM_STATUS_MAX_SPLITS_1 0x00000000
604#define PCIXM_STATUS_MAX_SPLITS_2 0x00800000
605#define PCIXM_STATUS_MAX_SPLITS_3 0x01000000
606#define PCIXM_STATUS_MAX_SPLITS_4 0x01800000
607#define PCIXM_STATUS_MAX_SPLITS_8 0x02000000
608#define PCIXM_STATUS_MAX_SPLITS_12 0x02800000
609#define PCIXM_STATUS_MAX_SPLITS_16 0x03000000
610#define PCIXM_STATUS_MAX_SPLITS_32 0x03800000
611#define PCIXM_STATUS_MAX_CUM_READ 0x1C000000
612#define PCIXM_STATUS_RCVD_SC_ERR 0x20000000
613#define PCIXM_STATUS_266CAP 0x40000000
614#define PCIXM_STATUS_533CAP 0x80000000
615
616/* For header type 1 devices (PCI-X bridges) */
617#define PCIXR_SEC_STATUS 0x2
618#define PCIXM_SEC_STATUS_64BIT 0x0001
619#define PCIXM_SEC_STATUS_133CAP 0x0002
620#define PCIXM_SEC_STATUS_SC_DISC 0x0004
621#define PCIXM_SEC_STATUS_UNEXP_SC 0x0008
622#define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010
623#define PCIXM_SEC_STATUS_SR_DELAYED 0x0020
624#define PCIXM_SEC_STATUS_BUS_MODE 0x03c0
625#define PCIXM_SEC_STATUS_VERSION 0x3000
626#define PCIXM_SEC_STATUS_266CAP 0x4000
627#define PCIXM_SEC_STATUS_533CAP 0x8000
628#define PCIXR_BRIDGE_STATUS 0x4
629#define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF
630#define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00
631#define PCIXM_BRIDGE_STATUS_64BIT 0x00010000
632#define PCIXM_BRIDGE_STATUS_133CAP 0x00020000
633#define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000
634#define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000
635#define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000
636#define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000
637#define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000
638#define PCIXM_BRIDGE_STATUS_266CAP 0x40000000
639#define PCIXM_BRIDGE_STATUS_533CAP 0x80000000
640
641/* HT (HyperTransport) Capability definitions */
642#define PCIR_HT_COMMAND 0x2
643#define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */
644#define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */
645#define PCIM_HTCAP_HOST 0x2000 /* 001xx */
646#define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */
647#define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */
648#define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */
649#define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */
650#define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */
651#define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */
652#define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */
653#define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */
654#define PCIM_HTCAP_VCSET 0xb800 /* 10111 */
655#define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */
656#define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */
657#define PCIM_HTCAP_GEN3 0xd000 /* 11010 */
658#define PCIM_HTCAP_FLE 0xd800 /* 11011 */
659#define PCIM_HTCAP_PM 0xe000 /* 11100 */
660#define PCIM_HTCAP_HIGH_NODE_COUNT 0xe800 /* 11101 */
661
662/* HT MSI Mapping Capability definitions. */
663#define PCIM_HTCMD_MSI_ENABLE 0x0001
664#define PCIM_HTCMD_MSI_FIXED 0x0002
665#define PCIR_HTMSI_ADDRESS_LO 0x4
666#define PCIR_HTMSI_ADDRESS_HI 0x8
667
668/* PCI Vendor capability definitions */
669#define PCIR_VENDOR_LENGTH 0x2
670#define PCIR_VENDOR_DATA 0x3
671
672/* PCI EHCI Debug Port definitions */
673#define PCIR_DEBUG_PORT 0x2
674#define PCIM_DEBUG_PORT_OFFSET 0x1FFF
675#define PCIM_DEBUG_PORT_BAR 0xe000
676
677/* PCI-PCI Bridge Subvendor definitions */
678#define PCIR_SUBVENDCAP_ID 0x4
679
680/* PCI Express definitions */
681#define PCIER_FLAGS 0x2
682#define PCIEM_FLAGS_VERSION 0x000F
683#define PCIEM_FLAGS_TYPE 0x00F0
684#define PCIEM_TYPE_ENDPOINT 0x0000
685#define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010
686#define PCIEM_TYPE_ROOT_PORT 0x0040
687#define PCIEM_TYPE_UPSTREAM_PORT 0x0050
688#define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060
689#define PCIEM_TYPE_PCI_BRIDGE 0x0070
690#define PCIEM_TYPE_PCIE_BRIDGE 0x0080
691#define PCIEM_TYPE_ROOT_INT_EP 0x0090
692#define PCIEM_TYPE_ROOT_EC 0x00a0
693#define PCIEM_FLAGS_SLOT 0x0100
694#define PCIEM_FLAGS_IRQ 0x3e00
695#define PCIER_DEVICE_CAP 0x4
696#define PCIEM_CAP_MAX_PAYLOAD 0x00000007
697#define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018
698#define PCIEM_CAP_EXT_TAG_FIELD 0x00000020
699#define PCIEM_CAP_L0S_LATENCY 0x000001c0
700#define PCIEM_CAP_L1_LATENCY 0x00000e00
701#define PCIEM_CAP_ROLE_ERR_RPT 0x00008000
702#define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000
703#define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000
704#define PCIEM_CAP_FLR 0x10000000
705#define PCIER_DEVICE_CTL 0x8
706#define PCIEM_CTL_COR_ENABLE 0x0001
707#define PCIEM_CTL_NFER_ENABLE 0x0002
708#define PCIEM_CTL_FER_ENABLE 0x0004
709#define PCIEM_CTL_URR_ENABLE 0x0008
710#define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010
711#define PCIEM_CTL_MAX_PAYLOAD 0x00e0
712#define PCIEM_CTL_EXT_TAG_FIELD 0x0100
713#define PCIEM_CTL_PHANTHOM_FUNCS 0x0200
714#define PCIEM_CTL_AUX_POWER_PM 0x0400
715#define PCIEM_CTL_NOSNOOP_ENABLE 0x0800
716#define PCIEM_CTL_MAX_READ_REQUEST 0x7000
717#define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */
718#define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */
719#define PCIER_DEVICE_STA 0xa
720#define PCIEM_STA_CORRECTABLE_ERROR 0x0001
721#define PCIEM_STA_NON_FATAL_ERROR 0x0002
722#define PCIEM_STA_FATAL_ERROR 0x0004
723#define PCIEM_STA_UNSUPPORTED_REQ 0x0008
724#define PCIEM_STA_AUX_POWER 0x0010
725#define PCIEM_STA_TRANSACTION_PND 0x0020
726#define PCIER_LINK_CAP 0xc
727#define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f
728#define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0
729#define PCIEM_LINK_CAP_ASPM 0x00000c00
730#define PCIEM_LINK_CAP_L0S_EXIT 0x00007000
731#define PCIEM_LINK_CAP_L1_EXIT 0x00038000
732#define PCIEM_LINK_CAP_CLOCK_PM 0x00040000
733#define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000
734#define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000
735#define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000
736#define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000
737#define PCIEM_LINK_CAP_PORT 0xff000000
738#define PCIER_LINK_CTL 0x10
739#define PCIEM_LINK_CTL_ASPMC_DIS 0x0000
740#define PCIEM_LINK_CTL_ASPMC_L0S 0x0001
741#define PCIEM_LINK_CTL_ASPMC_L1 0x0002
742#define PCIEM_LINK_CTL_ASPMC 0x0003
743#define PCIEM_LINK_CTL_RCB 0x0008
744#define PCIEM_LINK_CTL_LINK_DIS 0x0010
745#define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020
746#define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040
747#define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080
748#define PCIEM_LINK_CTL_ECPM 0x0100
749#define PCIEM_LINK_CTL_HAWD 0x0200
750#define PCIEM_LINK_CTL_LBMIE 0x0400
751#define PCIEM_LINK_CTL_LABIE 0x0800
752#define PCIER_LINK_STA 0x12
753#define PCIEM_LINK_STA_SPEED 0x000f
754#define PCIEM_LINK_STA_WIDTH 0x03f0
755#define PCIEM_LINK_STA_TRAINING_ERROR 0x0400
756#define PCIEM_LINK_STA_TRAINING 0x0800
757#define PCIEM_LINK_STA_SLOT_CLOCK 0x1000
758#define PCIEM_LINK_STA_DL_ACTIVE 0x2000
759#define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000
760#define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000
761#define PCIER_SLOT_CAP 0x14
762#define PCIEM_SLOT_CAP_APB 0x00000001
763#define PCIEM_SLOT_CAP_PCP 0x00000002
764#define PCIEM_SLOT_CAP_MRLSP 0x00000004
765#define PCIEM_SLOT_CAP_AIP 0x00000008
766#define PCIEM_SLOT_CAP_PIP 0x00000010
767#define PCIEM_SLOT_CAP_HPS 0x00000020
768#define PCIEM_SLOT_CAP_HPC 0x00000040
769#define PCIEM_SLOT_CAP_SPLV 0x00007f80
770#define PCIEM_SLOT_CAP_SPLS 0x00018000
771#define PCIEM_SLOT_CAP_EIP 0x00020000
772#define PCIEM_SLOT_CAP_NCCS 0x00040000
773#define PCIEM_SLOT_CAP_PSN 0xfff80000
774#define PCIER_SLOT_CTL 0x18
775#define PCIEM_SLOT_CTL_ABPE 0x0001
776#define PCIEM_SLOT_CTL_PFDE 0x0002
777#define PCIEM_SLOT_CTL_MRLSCE 0x0004
778#define PCIEM_SLOT_CTL_PDCE 0x0008
779#define PCIEM_SLOT_CTL_CCIE 0x0010
780#define PCIEM_SLOT_CTL_HPIE 0x0020
781#define PCIEM_SLOT_CTL_AIC 0x00c0
782#define PCIEM_SLOT_CTL_PIC 0x0300
783#define PCIEM_SLOT_CTL_PCC 0x0400
784#define PCIEM_SLOT_CTL_EIC 0x0800
785#define PCIEM_SLOT_CTL_DLLSCE 0x1000
786#define PCIER_SLOT_STA 0x1a
787#define PCIEM_SLOT_STA_ABP 0x0001
788#define PCIEM_SLOT_STA_PFD 0x0002
789#define PCIEM_SLOT_STA_MRLSC 0x0004
790#define PCIEM_SLOT_STA_PDC 0x0008
791#define PCIEM_SLOT_STA_CC 0x0010
792#define PCIEM_SLOT_STA_MRLSS 0x0020
793#define PCIEM_SLOT_STA_PDS 0x0040
794#define PCIEM_SLOT_STA_EIS 0x0080
795#define PCIEM_SLOT_STA_DLLSC 0x0100
796#define PCIER_ROOT_CTL 0x1c
797#define PCIEM_ROOT_CTL_SERR_CORR 0x0001
798#define PCIEM_ROOT_CTL_SERR_NONFATAL 0x0002
799#define PCIEM_ROOT_CTL_SERR_FATAL 0x0004
800#define PCIEM_ROOT_CTL_PME 0x0008
801#define PCIEM_ROOT_CTL_CRS_VIS 0x0010
802#define PCIER_ROOT_CAP 0x1e
803#define PCIEM_ROOT_CAP_CRS_VIS 0x0001
804#define PCIER_ROOT_STA 0x20
805#define PCIEM_ROOT_STA_PME_REQID_MASK 0x0000ffff
806#define PCIEM_ROOT_STA_PME_STATUS 0x00010000
807#define PCIEM_ROOT_STA_PME_PEND 0x00020000
808#define PCIER_DEVICE_CAP2 0x24
809#define PCIEM_CAP2_ARI 0x20
810#define PCIER_DEVICE_CTL2 0x28
811#define PCIEM_CTL2_COMP_TIMEOUT_VAL 0x000f
812#define PCIEM_CTL2_COMP_TIMEOUT_DIS 0x0010
813#define PCIEM_CTL2_ARI 0x0020
814#define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040
815#define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080
816#define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100
817#define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200
818#define PCIEM_CTL2_LTR_ENABLE 0x0400
819#define PCIEM_CTL2_OBFF 0x6000
820#define PCIEM_OBFF_DISABLE 0x0000
821#define PCIEM_OBFF_MSGA_ENABLE 0x2000
822#define PCIEM_OBFF_MSGB_ENABLE 0x4000
823#define PCIEM_OBFF_WAKE_ENABLE 0x6000
824#define PCIEM_CTL2_END2END_TLP 0x8000
825#define PCIER_DEVICE_STA2 0x2a
826#define PCIER_LINK_CAP2 0x2c
827#define PCIER_LINK_CTL2 0x30
828#define PCIER_LINK_STA2 0x32
829#define PCIER_SLOT_CAP2 0x34
830#define PCIER_SLOT_CTL2 0x38
831#define PCIER_SLOT_STA2 0x3a
832
833/* MSI-X definitions */
834#define PCIR_MSIX_CTRL 0x2
835#define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000
836#define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000
837#define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF
838#define PCIR_MSIX_TABLE 0x4
839#define PCIR_MSIX_PBA 0x8
840#define PCIM_MSIX_BIR_MASK 0x7
841#define PCIM_MSIX_BIR_BAR_10 0
842#define PCIM_MSIX_BIR_BAR_14 1
843#define PCIM_MSIX_BIR_BAR_18 2
844#define PCIM_MSIX_BIR_BAR_1C 3
845#define PCIM_MSIX_BIR_BAR_20 4
846#define PCIM_MSIX_BIR_BAR_24 5
847#define PCIM_MSIX_VCTRL_MASK 0x1
848
849/* PCI Advanced Features definitions */
850#define PCIR_PCIAF_CAP 0x3
851#define PCIM_PCIAFCAP_TP 0x01
852#define PCIM_PCIAFCAP_FLR 0x02
853#define PCIR_PCIAF_CTRL 0x4
854#define PCIR_PCIAFCTRL_FLR 0x01
855#define PCIR_PCIAF_STATUS 0x5
856#define PCIR_PCIAFSTATUS_TP 0x01
857
858/* Advanced Error Reporting */
859#define PCIR_AER_UC_STATUS 0x04
860#define PCIM_AER_UC_TRAINING_ERROR 0x00000001
861#define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010
862#define PCIM_AER_UC_SURPRISE_LINK_DOWN 0x00000020
863#define PCIM_AER_UC_POISONED_TLP 0x00001000
864#define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000
865#define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000
866#define PCIM_AER_UC_COMPLETER_ABORT 0x00008000
867#define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000
868#define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000
869#define PCIM_AER_UC_MALFORMED_TLP 0x00040000
870#define PCIM_AER_UC_ECRC_ERROR 0x00080000
871#define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000
872#define PCIM_AER_UC_ACS_VIOLATION 0x00200000
873#define PCIM_AER_UC_INTERNAL_ERROR 0x00400000
874#define PCIM_AER_UC_MC_BLOCKED_TLP 0x00800000
875#define PCIM_AER_UC_ATOMIC_EGRESS_BLK 0x01000000
876#define PCIM_AER_UC_TLP_PREFIX_BLOCKED 0x02000000
877#define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */
878#define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */
879#define PCIR_AER_COR_STATUS 0x10
880#define PCIM_AER_COR_RECEIVER_ERROR 0x00000001
881#define PCIM_AER_COR_BAD_TLP 0x00000040
882#define PCIM_AER_COR_BAD_DLLP 0x00000080
883#define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100
884#define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000
885#define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000
886#define PCIM_AER_COR_INTERNAL_ERROR 0x00004000
887#define PCIM_AER_COR_HEADER_LOG_OVFLOW 0x00008000
888#define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */
889#define PCIR_AER_CAP_CONTROL 0x18
890#define PCIM_AER_FIRST_ERROR_PTR 0x0000001f
891#define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020
892#define PCIM_AER_ECRC_GEN_ENABLE 0x00000040
893#define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080
894#define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100
895#define PCIM_AER_MULT_HDR_CAPABLE 0x00000200
896#define PCIM_AER_MULT_HDR_ENABLE 0x00000400
897#define PCIM_AER_TLP_PREFIX_LOG_PRESENT 0x00000800
898#define PCIR_AER_HEADER_LOG 0x1c
899#define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */
900#define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001
901#define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002
902#define PCIM_AER_ROOTERR_F_ENABLE 0x00000004
903#define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */
904#define PCIM_AER_ROOTERR_COR_ERR 0x00000001
905#define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002
906#define PCIM_AER_ROOTERR_UC_ERR 0x00000004
907#define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008
908#define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010
909#define PCIM_AER_ROOTERR_NF_ERR 0x00000020
910#define PCIM_AER_ROOTERR_F_ERR 0x00000040
911#define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000
912#define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */
913#define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */
914#define PCIR_AER_TLP_PREFIX_LOG 0x38 /* Only for TLP prefix functions */
915
916/* Virtual Channel definitions */
917#define PCIR_VC_CAP1 0x04
918#define PCIM_VC_CAP1_EXT_COUNT 0x00000007
919#define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070
920#define PCIR_VC_CAP2 0x08
921#define PCIR_VC_CONTROL 0x0C
922#define PCIR_VC_STATUS 0x0E
923#define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C)
924#define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C)
925#define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C)
926
927/* Serial Number definitions */
928#define PCIR_SERIAL_LOW 0x04
929#define PCIR_SERIAL_HIGH 0x08
930
931#endif /* __PCI_REG_H__*/