RTEMS: bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h Source File

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alt_clock_manager.h
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1
12/******************************************************************************
13*
14* Copyright 2013 Altera Corporation. All Rights Reserved.
15*
16* Redistribution and use in source and binary forms, with or without
17* modification, are permitted provided that the following conditions are met:
18*
19* 1. Redistributions of source code must retain the above copyright notice,
20* this list of conditions and the following disclaimer.
21*
22* 2. Redistributions in binary form must reproduce the above copyright notice,
23* this list of conditions and the following disclaimer in the documentation
24* and/or other materials provided with the distribution.
25*
26* 3. The name of the author may not be used to endorse or promote products
27* derived from this software without specific prior written permission.
28*
29* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
30* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
31* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
32* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
33* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
34* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
38* OF SUCH DAMAGE.
39*
40******************************************************************************/
41
42#ifndef __ALT_CLK_MGR_H__
43#define __ALT_CLK_MGR_H__
44
45#include "hwlib.h"
46#include "alt_clock_group.h"
47
48#ifdef __cplusplus
49extern "C"
50{
51#endif /* __cplusplus */
52
61/******************************************************************************/
66 typedef uint32_t alt_freq_t;
67
68/******************************************************************************/
73 typedef enum ALT_CLK_e
74{
75 /* Clock Input Pins */
76 ALT_CLK_IN_PIN_OSC1,
87 ALT_CLK_IN_PIN_OSC2,
98 /* FPGA Clock Sources External to HPS */
99 ALT_CLK_F2H_PERIPH_REF,
100 /*<! Alternate clock source from FPGA
101 * for HPS Peripheral PLL. */
102
103 ALT_CLK_F2H_SDRAM_REF,
104 /*<! Alternate clock source from FPGA
105 * for HPS SDRAM PLL. */
106
107
108 /* Other Clock Sources External to HPS */
109 ALT_CLK_IN_PIN_JTAG,
115 ALT_CLK_IN_PIN_ULPI0,
122 ALT_CLK_IN_PIN_ULPI1,
129 ALT_CLK_IN_PIN_EMAC0_RX,
135 ALT_CLK_IN_PIN_EMAC1_RX,
142 /* PLLs */
143 ALT_CLK_MAIN_PLL,
150 ALT_CLK_PERIPHERAL_PLL,
158 ALT_CLK_SDRAM_PLL,
165 /* OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived
166 * directly from the osc_clk_1_HPS pin */
167 ALT_CLK_OSC1,
177 /* Main Clock Group - The following clocks are derived from the Main PLL. */
178 ALT_CLK_MAIN_PLL_C0,
181 ALT_CLK_MAIN_PLL_C1,
184 ALT_CLK_MAIN_PLL_C2,
187 ALT_CLK_MAIN_PLL_C3,
190 ALT_CLK_MAIN_PLL_C4,
193 ALT_CLK_MAIN_PLL_C5,
196 ALT_CLK_MPU,
203 ALT_CLK_MPU_L2_RAM,
208 ALT_CLK_MPU_PERIPH,
215 ALT_CLK_L3_MAIN,
221 ALT_CLK_L3_MP,
226 ALT_CLK_L3_SP,
231 ALT_CLK_L4_MAIN,
238 ALT_CLK_L4_MP,
243 ALT_CLK_L4_SP,
248 ALT_CLK_DBG_BASE,
254 ALT_CLK_DBG_AT,
261 ALT_CLK_DBG_TRACE,
267 ALT_CLK_DBG_TIMER,
273 ALT_CLK_DBG,
280 ALT_CLK_MAIN_QSPI,
287 ALT_CLK_MAIN_NAND_SDMMC,
294 ALT_CLK_CFG,
299 ALT_CLK_H2F_USER0,
305 /* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */
306 ALT_CLK_PERIPHERAL_PLL_C0,
309 ALT_CLK_PERIPHERAL_PLL_C1,
312 ALT_CLK_PERIPHERAL_PLL_C2,
315 ALT_CLK_PERIPHERAL_PLL_C3,
318 ALT_CLK_PERIPHERAL_PLL_C4,
321 ALT_CLK_PERIPHERAL_PLL_C5,
324 ALT_CLK_USB_MP,
329 ALT_CLK_SPI_M,
334 ALT_CLK_QSPI,
339 ALT_CLK_NAND_X,
345 ALT_CLK_NAND,
351 ALT_CLK_SDMMC,
356 ALT_CLK_EMAC0,
363 ALT_CLK_EMAC1,
370 ALT_CLK_CAN0,
376 ALT_CLK_CAN1,
382 ALT_CLK_GPIO_DB,
388 ALT_CLK_H2F_USER1,
396 /* SDRAM Clock Group - The following clocks are derived from the SDRAM PLL */
397 ALT_CLK_SDRAM_PLL_C0,
400 ALT_CLK_SDRAM_PLL_C1,
403 ALT_CLK_SDRAM_PLL_C2,
406 ALT_CLK_SDRAM_PLL_C3,
409 ALT_CLK_SDRAM_PLL_C4,
412 ALT_CLK_SDRAM_PLL_C5,
415 ALT_CLK_DDR_DQS,
423 ALT_CLK_DDR_2X_DQS,
429 ALT_CLK_DDR_DQ,
435 ALT_CLK_H2F_USER2,
442 /* Clock Output Pins */
443 ALT_CLK_OUT_PIN_EMAC0_TX,
449 ALT_CLK_OUT_PIN_EMAC1_TX,
455 ALT_CLK_OUT_PIN_SDMMC,
461 ALT_CLK_OUT_PIN_I2C0_SCL,
467 ALT_CLK_OUT_PIN_I2C1_SCL,
473 ALT_CLK_OUT_PIN_I2C2_SCL,
479 ALT_CLK_OUT_PIN_I2C3_SCL,
485 ALT_CLK_OUT_PIN_SPIM0,
491 ALT_CLK_OUT_PIN_SPIM1,
497 ALT_CLK_OUT_PIN_QSPI,
503 ALT_CLK_UNKNOWN
504} ALT_CLK_t;
505
506/******************************************************************************/
514/******************************************************************************/
520 typedef enum ALT_CLK_PLL_LOCK_STATUS_e
521{
522 ALT_MAIN_PLL_LOCK_ACHV = 0x00000001,
527 ALT_PERIPH_PLL_LOCK_ACHV = 0x00000002,
532 ALT_SDR_PLL_LOCK_ACHV = 0x00000004,
537 ALT_MAIN_PLL_LOCK_LOST = 0x00000008,
542 ALT_PERIPH_PLL_LOCK_LOST = 0x00000010,
547 ALT_SDR_PLL_LOCK_LOST = 0x00000020
552} ALT_CLK_PLL_LOCK_STATUS_t;
553
554/******************************************************************************/
573 ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
574
575/******************************************************************************/
585uint32_t alt_clk_lock_status_get(void);
586
587/******************************************************************************/
608 ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll);
609
612/******************************************************************************/
650/******************************************************************************/
655 typedef enum ALT_CLK_SAFE_DOMAIN_e
656{
661 ALT_CLK_DOMAIN_NORMAL,
666 ALT_CLK_DOMAIN_DEBUG
667} ALT_CLK_SAFE_DOMAIN_t;
668
669/******************************************************************************/
679 ALT_STATUS_CODE alt_clk_safe_mode_clear(void);
680
681/******************************************************************************/
691bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain);
692
695/******************************************************************************/
719/******************************************************************************/
732 ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll);
733
734/******************************************************************************/
753 ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll,
754 bool use_input_mux);
755
756/******************************************************************************/
774 ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll);
775
778/******************************************************************************/
823/******************************************************************************/
836 ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk);
837
838/******************************************************************************/
851 ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk);
852
853/******************************************************************************/
865 ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk);
866
869/******************************************************************************/
916/******************************************************************************/
933 ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk);
934
935/******************************************************************************/
955 ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk,
956 ALT_CLK_t ref_clk);
957
960/******************************************************************************/
969/******************************************************************************/
996 ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk,
997 alt_freq_t freq);
998
999/******************************************************************************/
1017 alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk);
1018
1019/******************************************************************************/
1024 typedef struct ALT_CLK_PLL_CFG_s
1025{
1026 ALT_CLK_t ref_clk;
1027 uint32_t mult;
1030 uint32_t div;
1033 uint32_t cntrs[6];
1036 uint32_t pshift[6];
1040} ALT_CLK_PLL_CFG_t;
1041
1042/******************************************************************************/
1056 ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll,
1057 ALT_CLK_PLL_CFG_t* pll_cfg);
1058
1059/******************************************************************************/
1074 ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll,
1075 const ALT_CLK_PLL_CFG_t* pll_cfg);
1076
1077/******************************************************************************/
1095 ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll,
1096 uint32_t* mult,
1097 uint32_t* div);
1098
1099/******************************************************************************/
1116 ALT_STATUS_CODE alt_clk_pll_vco_cfg_set(ALT_CLK_t pll,
1117 uint32_t mult,
1118 uint32_t div);
1119
1120/******************************************************************************/
1138 ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll,
1139 alt_freq_t* freq);
1140
1141/******************************************************************************/
1150uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll);
1151
1152/******************************************************************************/
1182 ALT_STATUS_CODE alt_clk_pll_guard_band_set(ALT_CLK_t pll,
1183 uint32_t guard_band);
1184
1185/******************************************************************************/
1208 ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk,
1209 uint32_t* div);
1210
1211/******************************************************************************/
1236 ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk,
1237 uint32_t div);
1238
1239/******************************************************************************/
1257 ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk,
1258 alt_freq_t* freq);
1259
1262/******************************************************************************/
1307/******************************************************************************/
1329 ALT_STATUS_CODE alt_clk_irq_disable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
1330
1331/******************************************************************************/
1353 ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
1354
1357/******************************************************************************/
1388/******************************************************************************/
1407 ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group,
1408 ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
1409
1410/******************************************************************************/
1429 ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
1430
1431 ALT_STATUS_CODE alt_clk_clkmgr_init(void);
1432
1436#ifdef __cplusplus
1437}
1438
1439#endif /* __cplusplus */
1440#endif /* __ALT_CLK_MGR_H__ */
alt_clock_group.h
ALT_CLK_GRP_t
enum ALT_CLK_GRP_e ALT_CLK_GRP_t
alt_clk_pll_is_bypassed
ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll)
Definition: alt_clock_manager.c:778
alt_clk_pll_bypass_enable
ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux)
Definition: alt_clock_manager.c:660
alt_clk_pll_bypass_disable
ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll)
Definition: alt_clock_manager.c:530
alt_clk_source_set
ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, ALT_CLK_t ref_clk)
Definition: alt_clock_manager.c:1514
alt_clk_source_get
ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk)
Definition: alt_clock_manager.c:1253
alt_clk_divider_get
ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk, uint32_t *div)
Definition: alt_clock_manager.c:2658
alt_clk_pll_cfg_get
ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll, ALT_CLK_PLL_CFG_t *pll_cfg)
Definition: alt_clock_manager.c:1789
ALT_CLK_PLL_CFG_t
struct ALT_CLK_PLL_CFG_s ALT_CLK_PLL_CFG_t
alt_clk_pll_cfg_set
ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll, const ALT_CLK_PLL_CFG_t *pll_cfg)
Definition: alt_clock_manager.c:1931
alt_clk_ext_clk_freq_set
ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk, alt_freq_t freq)
Definition: alt_clock_manager.c:1697
alt_clk_pll_vco_cfg_set
ALT_STATUS_CODE alt_clk_pll_vco_cfg_set(ALT_CLK_t pll, uint32_t mult, uint32_t div)
Definition: alt_clock_manager.c:2354
alt_clk_pll_guard_band_get
uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll)
Definition: alt_clock_manager.c:2596
alt_clk_freq_get
ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, alt_freq_t *freq)
Definition: alt_clock_manager.c:4154
alt_clk_divider_set
ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk, uint32_t div)
Definition: alt_clock_manager.c:3082
alt_clk_pll_vco_cfg_get
ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll, uint32_t *mult, uint32_t *div)
Definition: alt_clock_manager.c:2084
alt_clk_ext_clk_freq_get
alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk)
Definition: alt_clock_manager.c:1762
alt_clk_pll_guard_band_set
ALT_STATUS_CODE alt_clk_pll_guard_band_set(ALT_CLK_t pll, uint32_t guard_band)
Definition: alt_clock_manager.c:2620
alt_clk_pll_vco_freq_get
ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll, alt_freq_t *freq)
Definition: alt_clock_manager.c:2477
alt_clk_clock_disable
ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk)
Definition: alt_clock_manager.c:859
alt_clk_clock_enable
ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk)
Definition: alt_clock_manager.c:972
alt_clk_is_enabled
ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk)
Definition: alt_clock_manager.c:1087
alt_clk_group_cfg_raw_set
ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t *clk_group_raw_cfg)
Definition: alt_clock_manager.c:4999
alt_clk_group_cfg_raw_get
ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group, ALT_CLK_GROUP_RAW_CFG_t *clk_group_raw_cfg)
Definition: alt_clock_manager.c:4875
alt_clk_irq_enable
ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask)
Definition: alt_clock_manager.c:4856
alt_clk_irq_disable
ALT_STATUS_CODE alt_clk_irq_disable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask)
Definition: alt_clock_manager.c:4839
ALT_CLK_SAFE_DOMAIN_t
enum ALT_CLK_SAFE_DOMAIN_e ALT_CLK_SAFE_DOMAIN_t
alt_clk_safe_mode_clear
ALT_STATUS_CODE alt_clk_safe_mode_clear(void)
Definition: alt_clock_manager.c:463
ALT_CLK_SAFE_DOMAIN_e
ALT_CLK_SAFE_DOMAIN_e
Definition: alt_clock_manager.h:656
alt_clk_is_in_safe_mode
bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain)
Definition: alt_clock_manager.c:497
ALT_CLK_DOMAIN_DEBUG
@ ALT_CLK_DOMAIN_DEBUG
Definition: alt_clock_manager.h:666
ALT_CLK_DOMAIN_NORMAL
@ ALT_CLK_DOMAIN_NORMAL
Definition: alt_clock_manager.h:661
ALT_CLK_PLL_LOCK_STATUS_t
enum ALT_CLK_PLL_LOCK_STATUS_e ALT_CLK_PLL_LOCK_STATUS_t
alt_clk_lock_status_clear
ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask)
Definition: alt_clock_manager.c:392
alt_clk_pll_is_locked
ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll)
Definition: alt_clock_manager.c:435
alt_clk_lock_status_get
uint32_t alt_clk_lock_status_get(void)
Definition: alt_clock_manager.c:416
ALT_CLK_PLL_LOCK_STATUS_e
ALT_CLK_PLL_LOCK_STATUS_e
Definition: alt_clock_manager.h:521
ALT_SDR_PLL_LOCK_LOST
@ ALT_SDR_PLL_LOCK_LOST
Definition: alt_clock_manager.h:547
ALT_PERIPH_PLL_LOCK_LOST
@ ALT_PERIPH_PLL_LOCK_LOST
Definition: alt_clock_manager.h:542
ALT_MAIN_PLL_LOCK_ACHV
@ ALT_MAIN_PLL_LOCK_ACHV
Definition: alt_clock_manager.h:522
ALT_SDR_PLL_LOCK_ACHV
@ ALT_SDR_PLL_LOCK_ACHV
Definition: alt_clock_manager.h:532
ALT_PERIPH_PLL_LOCK_ACHV
@ ALT_PERIPH_PLL_LOCK_ACHV
Definition: alt_clock_manager.h:527
ALT_MAIN_PLL_LOCK_LOST
@ ALT_MAIN_PLL_LOCK_LOST
Definition: alt_clock_manager.h:537
ALT_CLK_t
enum ALT_CLK_e ALT_CLK_t
ALT_CLK_e
ALT_CLK_e
Definition: alt_clock_manager.h:74
alt_freq_t
uint32_t alt_freq_t
Definition: alt_clock_manager.h:66
ALT_CLK_IN_PIN_EMAC0_RX
@ ALT_CLK_IN_PIN_EMAC0_RX
Definition: alt_clock_manager.h:129
ALT_CLK_NAND_X
@ ALT_CLK_NAND_X
Definition: alt_clock_manager.h:339
ALT_CLK_CAN0
@ ALT_CLK_CAN0
Definition: alt_clock_manager.h:370
ALT_CLK_OSC1
@ ALT_CLK_OSC1
Definition: alt_clock_manager.h:167
ALT_CLK_SPI_M
@ ALT_CLK_SPI_M
Definition: alt_clock_manager.h:329
ALT_CLK_MAIN_PLL_C5
@ ALT_CLK_MAIN_PLL_C5
Definition: alt_clock_manager.h:193
ALT_CLK_OUT_PIN_SDMMC
@ ALT_CLK_OUT_PIN_SDMMC
Definition: alt_clock_manager.h:455
ALT_CLK_OUT_PIN_I2C1_SCL
@ ALT_CLK_OUT_PIN_I2C1_SCL
Definition: alt_clock_manager.h:467
ALT_CLK_DDR_2X_DQS
@ ALT_CLK_DDR_2X_DQS
Definition: alt_clock_manager.h:423
ALT_CLK_OUT_PIN_EMAC1_TX
@ ALT_CLK_OUT_PIN_EMAC1_TX
Definition: alt_clock_manager.h:449
ALT_CLK_DBG_AT
@ ALT_CLK_DBG_AT
Definition: alt_clock_manager.h:254
ALT_CLK_DBG_TIMER
@ ALT_CLK_DBG_TIMER
Definition: alt_clock_manager.h:267
ALT_CLK_MPU_PERIPH
@ ALT_CLK_MPU_PERIPH
Definition: alt_clock_manager.h:208
ALT_CLK_PERIPHERAL_PLL_C1
@ ALT_CLK_PERIPHERAL_PLL_C1
Definition: alt_clock_manager.h:309
ALT_CLK_SDRAM_PLL_C3
@ ALT_CLK_SDRAM_PLL_C3
Definition: alt_clock_manager.h:406
ALT_CLK_PERIPHERAL_PLL_C2
@ ALT_CLK_PERIPHERAL_PLL_C2
Definition: alt_clock_manager.h:312
ALT_CLK_MAIN_PLL_C3
@ ALT_CLK_MAIN_PLL_C3
Definition: alt_clock_manager.h:187
ALT_CLK_DBG
@ ALT_CLK_DBG
Definition: alt_clock_manager.h:273
ALT_CLK_MAIN_PLL_C4
@ ALT_CLK_MAIN_PLL_C4
Definition: alt_clock_manager.h:190
ALT_CLK_IN_PIN_JTAG
@ ALT_CLK_IN_PIN_JTAG
Definition: alt_clock_manager.h:109
ALT_CLK_OUT_PIN_SPIM0
@ ALT_CLK_OUT_PIN_SPIM0
Definition: alt_clock_manager.h:485
ALT_CLK_PERIPHERAL_PLL_C4
@ ALT_CLK_PERIPHERAL_PLL_C4
Definition: alt_clock_manager.h:318
ALT_CLK_CFG
@ ALT_CLK_CFG
Definition: alt_clock_manager.h:294
ALT_CLK_L3_MP
@ ALT_CLK_L3_MP
Definition: alt_clock_manager.h:221
ALT_CLK_MPU_L2_RAM
@ ALT_CLK_MPU_L2_RAM
Definition: alt_clock_manager.h:203
ALT_CLK_SDRAM_PLL_C5
@ ALT_CLK_SDRAM_PLL_C5
Definition: alt_clock_manager.h:412
ALT_CLK_PERIPHERAL_PLL
@ ALT_CLK_PERIPHERAL_PLL
Definition: alt_clock_manager.h:150
ALT_CLK_QSPI
@ ALT_CLK_QSPI
Definition: alt_clock_manager.h:334
ALT_CLK_SDRAM_PLL_C1
@ ALT_CLK_SDRAM_PLL_C1
Definition: alt_clock_manager.h:400
ALT_CLK_EMAC1
@ ALT_CLK_EMAC1
Definition: alt_clock_manager.h:363
ALT_CLK_MAIN_PLL_C0
@ ALT_CLK_MAIN_PLL_C0
Definition: alt_clock_manager.h:178
ALT_CLK_GPIO_DB
@ ALT_CLK_GPIO_DB
Definition: alt_clock_manager.h:382
ALT_CLK_SDRAM_PLL_C2
@ ALT_CLK_SDRAM_PLL_C2
Definition: alt_clock_manager.h:403
ALT_CLK_L3_SP
@ ALT_CLK_L3_SP
Definition: alt_clock_manager.h:226
ALT_CLK_H2F_USER0
@ ALT_CLK_H2F_USER0
Definition: alt_clock_manager.h:299
ALT_CLK_L3_MAIN
@ ALT_CLK_L3_MAIN
Definition: alt_clock_manager.h:215
ALT_CLK_IN_PIN_ULPI1
@ ALT_CLK_IN_PIN_ULPI1
Definition: alt_clock_manager.h:122
ALT_CLK_MAIN_PLL
@ ALT_CLK_MAIN_PLL
Definition: alt_clock_manager.h:143
ALT_CLK_OUT_PIN_QSPI
@ ALT_CLK_OUT_PIN_QSPI
Definition: alt_clock_manager.h:497
ALT_CLK_H2F_USER2
@ ALT_CLK_H2F_USER2
Definition: alt_clock_manager.h:435
ALT_CLK_SDMMC
@ ALT_CLK_SDMMC
Definition: alt_clock_manager.h:351
ALT_CLK_MAIN_PLL_C2
@ ALT_CLK_MAIN_PLL_C2
Definition: alt_clock_manager.h:184
ALT_CLK_DBG_TRACE
@ ALT_CLK_DBG_TRACE
Definition: alt_clock_manager.h:261
ALT_CLK_IN_PIN_OSC1
@ ALT_CLK_IN_PIN_OSC1
Definition: alt_clock_manager.h:76
ALT_CLK_OUT_PIN_EMAC0_TX
@ ALT_CLK_OUT_PIN_EMAC0_TX
Definition: alt_clock_manager.h:443
ALT_CLK_SDRAM_PLL_C4
@ ALT_CLK_SDRAM_PLL_C4
Definition: alt_clock_manager.h:409
ALT_CLK_OUT_PIN_I2C2_SCL
@ ALT_CLK_OUT_PIN_I2C2_SCL
Definition: alt_clock_manager.h:473
ALT_CLK_DBG_BASE
@ ALT_CLK_DBG_BASE
Definition: alt_clock_manager.h:248
ALT_CLK_PERIPHERAL_PLL_C3
@ ALT_CLK_PERIPHERAL_PLL_C3
Definition: alt_clock_manager.h:315
ALT_CLK_OUT_PIN_SPIM1
@ ALT_CLK_OUT_PIN_SPIM1
Definition: alt_clock_manager.h:491
ALT_CLK_EMAC0
@ ALT_CLK_EMAC0
Definition: alt_clock_manager.h:356
ALT_CLK_SDRAM_PLL
@ ALT_CLK_SDRAM_PLL
Definition: alt_clock_manager.h:158
ALT_CLK_MAIN_NAND_SDMMC
@ ALT_CLK_MAIN_NAND_SDMMC
Definition: alt_clock_manager.h:287
ALT_CLK_MPU
@ ALT_CLK_MPU
Definition: alt_clock_manager.h:196
ALT_CLK_OUT_PIN_I2C3_SCL
@ ALT_CLK_OUT_PIN_I2C3_SCL
Definition: alt_clock_manager.h:479
ALT_CLK_SDRAM_PLL_C0
@ ALT_CLK_SDRAM_PLL_C0
Definition: alt_clock_manager.h:397
ALT_CLK_H2F_USER1
@ ALT_CLK_H2F_USER1
Definition: alt_clock_manager.h:388
ALT_CLK_L4_MP
@ ALT_CLK_L4_MP
Definition: alt_clock_manager.h:238
ALT_CLK_MAIN_QSPI
@ ALT_CLK_MAIN_QSPI
Definition: alt_clock_manager.h:280
ALT_CLK_CAN1
@ ALT_CLK_CAN1
Definition: alt_clock_manager.h:376
ALT_CLK_NAND
@ ALT_CLK_NAND
Definition: alt_clock_manager.h:345
ALT_CLK_OUT_PIN_I2C0_SCL
@ ALT_CLK_OUT_PIN_I2C0_SCL
Definition: alt_clock_manager.h:461
ALT_CLK_L4_MAIN
@ ALT_CLK_L4_MAIN
Definition: alt_clock_manager.h:231
ALT_CLK_IN_PIN_OSC2
@ ALT_CLK_IN_PIN_OSC2
Definition: alt_clock_manager.h:87
ALT_CLK_IN_PIN_EMAC1_RX
@ ALT_CLK_IN_PIN_EMAC1_RX
Definition: alt_clock_manager.h:135
ALT_CLK_L4_SP
@ ALT_CLK_L4_SP
Definition: alt_clock_manager.h:243
ALT_CLK_USB_MP
@ ALT_CLK_USB_MP
Definition: alt_clock_manager.h:324
ALT_CLK_MAIN_PLL_C1
@ ALT_CLK_MAIN_PLL_C1
Definition: alt_clock_manager.h:181
ALT_CLK_PERIPHERAL_PLL_C5
@ ALT_CLK_PERIPHERAL_PLL_C5
Definition: alt_clock_manager.h:321
ALT_CLK_DDR_DQS
@ ALT_CLK_DDR_DQS
Definition: alt_clock_manager.h:415
ALT_CLK_DDR_DQ
@ ALT_CLK_DDR_DQ
Definition: alt_clock_manager.h:429
ALT_CLK_PERIPHERAL_PLL_C0
@ ALT_CLK_PERIPHERAL_PLL_C0
Definition: alt_clock_manager.h:306
ALT_CLK_IN_PIN_ULPI0
@ ALT_CLK_IN_PIN_ULPI0
Definition: alt_clock_manager.h:115
hwlib.h
ALT_STATUS_CODE
int32_t ALT_STATUS_CODE
Definition: hwlib.h:60
ALT_CLK_GROUP_RAW_CFG_s
Definition: alt_clock_group.h:73
ALT_CLK_PLL_CFG_s
Definition: alt_clock_manager.h:1025
ALT_CLK_PLL_CFG_s::cntrs
uint32_t cntrs[6]
Definition: alt_clock_manager.h:1033
ALT_CLK_PLL_CFG_s::pshift
uint32_t pshift[6]
Definition: alt_clock_manager.h:1036
ALT_CLK_PLL_CFG_s::mult
uint32_t mult
Definition: alt_clock_manager.h:1027
ALT_CLK_PLL_CFG_s::div
uint32_t div
Definition: alt_clock_manager.h:1030
ALT_CLK_PLL_CFG_s::ref_clk
ALT_CLK_t ref_clk
Definition: alt_clock_manager.h:1026