RTEMS: bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_qspi.h Source File

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alt_qspi.h
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1
7/******************************************************************************
8*
9* Copyright 2013 Altera Corporation. All Rights Reserved.
10*
11* Redistribution and use in source and binary forms, with or without
12* modification, are permitted provided that the following conditions are met:
13*
14* 1. Redistributions of source code must retain the above copyright notice,
15* this list of conditions and the following disclaimer.
16*
17* 2. Redistributions in binary form must reproduce the above copyright notice,
18* this list of conditions and the following disclaimer in the documentation
19* and/or other materials provided with the distribution.
20*
21* 3. The name of the author may not be used to endorse or promote products
22* derived from this software without specific prior written permission.
23*
24* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
25* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
27* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
28* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
33* OF SUCH DAMAGE.
34*
35******************************************************************************/
36
37/******************************************************************************
38*
39* !!!! Customer Be Aware, Exception!!!
40*
41* 1. Qspi Direct Access Mode is not working!
42*
43* This is because the qspi flash memory installed on our DevKit board, Micro
44* part N25Q00xx, 8 Gb, is not completely compatible with our embedded Synopsis
45* QSPI controller IP. Therefore there is no viable direct access code offered
46* in the lib. All the memory rea/write functionality is offered with indirect
47* access only.
48*
49* Should you install a different flash memory part in your custom board, and
50* wondering wether direct access mode works, please contact with us.
51*
52******************************************************************************/
53
58#ifndef __ALT_QSPI_H__
59#define __ALT_QSPI_H__
60
61#include <bsp/hwlib.h>
62
63#ifdef __cplusplus
64extern "C"
65{
66#endif /* __cplusplus */
67
68/******************************************************************************/
80/******************************************************************************/
89/******************************************************************************/
107 ALT_STATUS_CODE alt_qspi_init(void);
108
109/******************************************************************************/
119 ALT_STATUS_CODE alt_qspi_uninit(void);
120
121/******************************************************************************/
132 ALT_STATUS_CODE alt_qspi_disable(void);
133
134/******************************************************************************/
141 ALT_STATUS_CODE alt_qspi_enable(void);
142
143/******************************************************************************/
157 typedef enum ALT_QSPI_INT_STATUS_e
158{
167 ALT_QSPI_INT_STATUS_MODE_FAIL = (0x1 << 0),
168
177 ALT_QSPI_INT_STATUS_UFL = (0x1 << 1),
178
182 ALT_QSPI_INT_STATUS_IDAC_OP_COMPLETE = (0x1 << 2),
183
188 ALT_QSPI_INT_STATUS_IDAC_OP_REJECT = (0x1 << 3),
189
193 ALT_QSPI_INT_STATUS_WR_PROT_VIOL = (0x1 << 4),
194
199 ALT_QSPI_INT_STATUS_ILL_AHB_ACCESS = (0x1 << 5),
200
204 ALT_QSPI_INT_STATUS_IDAC_WTRMK_TRIG = (0x1 << 6),
205
216 ALT_QSPI_INT_STATUS_RX_OVF = (0x1 << 7),
217
224 ALT_QSPI_INT_STATUS_TX_FIFO_NOT_FULL = (0x1 << 8),
225
232 ALT_QSPI_INT_STATUS_TX_FIFO_FULL = (0x1 << 9),
233
240 ALT_QSPI_INT_STATUS_RX_FIFO_NOT_EMPTY = (0x1 << 10),
241
248 ALT_QSPI_INT_STATUS_RX_FIFO_FULL = (0x1 << 11),
249
254 ALT_QSPI_INT_STATUS_IDAC_RD_FULL = (0x1 << 12)
255
256} ALT_QSPI_INT_STATUS_t;
257
258/******************************************************************************/
271uint32_t alt_qspi_int_status_get(void);
272
273/******************************************************************************/
289 ALT_STATUS_CODE alt_qspi_int_clear(const uint32_t mask);
290
291/******************************************************************************/
316 ALT_STATUS_CODE alt_qspi_int_disable(const uint32_t mask);
317
318/******************************************************************************/
343 ALT_STATUS_CODE alt_qspi_int_enable(const uint32_t mask);
344
345/******************************************************************************/
351bool alt_qspi_is_idle(void);
352
355/******************************************************************************/
383/******************************************************************************/
404 ALT_STATUS_CODE alt_qspi_read(void * dest, uint32_t src, size_t size);
405
406/******************************************************************************/
427 ALT_STATUS_CODE alt_qspi_write(uint32_t dest, const void * src, size_t size);
428
431/******************************************************************************/
461/******************************************************************************/
467 typedef enum ALT_QSPI_MODE_e
468{
469 ALT_QSPI_MODE_SINGLE = 0,
473 ALT_QSPI_MODE_DUAL = 1,
476 ALT_QSPI_MODE_QUAD = 2
479} ALT_QSPI_MODE_t;
480
481/******************************************************************************/
487 typedef enum ALT_QSPI_CS_MODE_e
488{
489 ALT_QSPI_CS_MODE_SINGLE_SELECT = 0,
491 ALT_QSPI_CS_MODE_DECODE = 1
494} ALT_QSPI_CS_MODE_t;
495
496/******************************************************************************/
500 typedef enum ALT_QSPI_BAUD_DIV_e
501{
502 ALT_QSPI_BAUD_DIV_2 = 0x0,
503 ALT_QSPI_BAUD_DIV_4 = 0x1,
504 ALT_QSPI_BAUD_DIV_6 = 0x2,
505 ALT_QSPI_BAUD_DIV_8 = 0x3,
506 ALT_QSPI_BAUD_DIV_10 = 0x4,
507 ALT_QSPI_BAUD_DIV_12 = 0x5,
508 ALT_QSPI_BAUD_DIV_14 = 0x6,
509 ALT_QSPI_BAUD_DIV_16 = 0x7,
510 ALT_QSPI_BAUD_DIV_18 = 0x8,
511 ALT_QSPI_BAUD_DIV_20 = 0x9,
512 ALT_QSPI_BAUD_DIV_22 = 0xA,
513 ALT_QSPI_BAUD_DIV_24 = 0xB,
514 ALT_QSPI_BAUD_DIV_26 = 0xC,
515 ALT_QSPI_BAUD_DIV_28 = 0xD,
516 ALT_QSPI_BAUD_DIV_30 = 0xE,
517 ALT_QSPI_BAUD_DIV_32 = 0xF
518} ALT_QSPI_BAUD_DIV_t;
519
520/******************************************************************************/
527 typedef struct ALT_QSPI_DEV_SIZE_CONFIG_s
528{
529 uint32_t block_size;
534 uint32_t page_size;
539 uint32_t addr_size;
544 uint32_t lower_wrprot_block;
550 uint32_t upper_wrprot_block;
556 bool wrprot_enable;
562} ALT_QSPI_DEV_SIZE_CONFIG_t;
563
564/******************************************************************************/
569 typedef enum ALT_QSPI_CLK_PHASE_e
570{
571 ALT_QSPI_CLK_PHASE_ACTIVE = 0,
574 ALT_QSPI_CLK_PHASE_INACTIVE = 1
577} ALT_QSPI_CLK_PHASE_t;
578
579/******************************************************************************/
583 typedef enum ALT_QSPI_CLK_POLARITY_e
584{
585 ALT_QSPI_CLK_POLARITY_LOW = 0,
588 ALT_QSPI_CLK_POLARITY_HIGH = 1
591} ALT_QSPI_CLK_POLARITY_t;
592
593/******************************************************************************/
602 typedef struct ALT_QSPI_TIMING_CONFIG_s
603{
604 ALT_QSPI_CLK_PHASE_t clk_phase;
609 ALT_QSPI_CLK_POLARITY_t clk_pol;
613 uint32_t cs_da;
621 uint32_t cs_dads;
634 uint32_t cs_eot;
647 uint32_t cs_sot;
659 uint32_t rd_datacap;
673} ALT_QSPI_TIMING_CONFIG_t;
674
675/******************************************************************************/
682 typedef struct ALT_QSPI_DEV_INST_CONFIG_s
683{
684 uint32_t op_code;
687 ALT_QSPI_MODE_t inst_type;
696 ALT_QSPI_MODE_t addr_xfer_type;
705 ALT_QSPI_MODE_t data_xfer_type;
714 uint32_t dummy_cycles;
719} ALT_QSPI_DEV_INST_CONFIG_t;
720
721/******************************************************************************/
727 ALT_QSPI_BAUD_DIV_t alt_qspi_baud_rate_div_get(void);
728
729/******************************************************************************/
742 ALT_STATUS_CODE alt_qspi_baud_rate_div_set(const ALT_QSPI_BAUD_DIV_t baud_rate_div);
743
744/******************************************************************************/
758 ALT_STATUS_CODE alt_qspi_chip_select_config_get(uint32_t* cs, ALT_QSPI_CS_MODE_t* cs_mode);
759
760/******************************************************************************/
789 ALT_STATUS_CODE alt_qspi_chip_select_config_set(const uint32_t cs,
790 const ALT_QSPI_CS_MODE_t cs_mode);
791
792/******************************************************************************/
802 ALT_STATUS_CODE alt_qspi_mode_bit_disable(void);
803
804/******************************************************************************/
814 ALT_STATUS_CODE alt_qspi_mode_bit_enable(void);
815
816/******************************************************************************/
823uint32_t alt_qspi_mode_bit_config_get(void);
824
825/******************************************************************************/
841 ALT_STATUS_CODE alt_qspi_mode_bit_config_set(const uint32_t mode_bits);
842
843/******************************************************************************/
855 ALT_STATUS_CODE alt_qspi_device_size_config_get(ALT_QSPI_DEV_SIZE_CONFIG_t * cfg);
856
857/******************************************************************************/
868 ALT_STATUS_CODE alt_qspi_device_size_config_set(const ALT_QSPI_DEV_SIZE_CONFIG_t * cfg);
869
870/******************************************************************************/
882 ALT_STATUS_CODE alt_qspi_device_read_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg);
883
884/******************************************************************************/
900 ALT_STATUS_CODE alt_qspi_device_read_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg);
901
902/******************************************************************************/
914 ALT_STATUS_CODE alt_qspi_device_write_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg);
915
916/******************************************************************************/
932 ALT_STATUS_CODE alt_qspi_device_write_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg);
933
934/******************************************************************************/
948 ALT_STATUS_CODE alt_qspi_timing_config_get(ALT_QSPI_TIMING_CONFIG_t * cfg);
949
950/******************************************************************************/
971 ALT_STATUS_CODE alt_qspi_timing_config_set(const ALT_QSPI_TIMING_CONFIG_t * cfg);
972
975/******************************************************************************/
1000/******************************************************************************/
1007 ALT_STATUS_CODE alt_qspi_direct_disable(void);
1008
1009/******************************************************************************/
1016 ALT_STATUS_CODE alt_qspi_direct_enable(void);
1017
1018/******************************************************************************/
1027uint32_t alt_qspi_ahb_remap_address_get(void);
1028
1029/******************************************************************************/
1045 ALT_STATUS_CODE alt_qspi_ahb_remap_address_set(const uint32_t ahb_remap_addr);
1046
1047/******************************************************************************/
1058 ALT_STATUS_CODE alt_qspi_ahb_address_remap_disable(void);
1059
1060/******************************************************************************/
1072 ALT_STATUS_CODE alt_qspi_ahb_address_remap_enable(void);
1073
1076/******************************************************************************/
1093/******************************************************************************/
1126 ALT_STATUS_CODE alt_qspi_indirect_read_start(const uint32_t flash_addr,
1127 const size_t num_bytes);
1128
1129/******************************************************************************/
1137 ALT_STATUS_CODE alt_qspi_indirect_read_finish(void);
1138
1139/******************************************************************************/
1146 ALT_STATUS_CODE alt_qspi_indirect_read_cancel(void);
1147
1148/******************************************************************************/
1158uint32_t alt_qspi_indirect_read_fill_level(void);
1159
1160/******************************************************************************/
1171uint32_t alt_qspi_indirect_read_watermark_get(void);
1172
1173/******************************************************************************/
1189 ALT_STATUS_CODE alt_qspi_indirect_read_watermark_set(const uint32_t watermark);
1190
1191/******************************************************************************/
1201bool alt_qspi_indirect_read_is_complete(void);
1202
1203/******************************************************************************/
1238 ALT_STATUS_CODE alt_qspi_indirect_write_start(const uint32_t flash_addr,
1239 const size_t num_bytes);
1240
1241/******************************************************************************/
1249 ALT_STATUS_CODE alt_qspi_indirect_write_finish(void);
1250
1251/******************************************************************************/
1258 ALT_STATUS_CODE alt_qspi_indirect_write_cancel(void);
1259
1260/******************************************************************************/
1270uint32_t alt_qspi_indirect_write_fill_level(void);
1271
1272/******************************************************************************/
1283uint32_t alt_qspi_indirect_write_watermark_get(void);
1284
1285/******************************************************************************/
1301 ALT_STATUS_CODE alt_qspi_indirect_write_watermark_set(const uint32_t watermark);
1302
1303/******************************************************************************/
1315bool alt_qspi_indirect_write_is_complete(void);
1316
1317/******************************************************************************/
1339#define ALT_QSPI_SRAM_FIFO_SIZE (512)
1340
1341/*
1342 * The size of the onboard SRAM in entries. Each entry is word (32-bit) sized.
1343 */
1344#define ALT_QSPI_SRAM_FIFO_ENTRY_COUNT (512 / sizeof(uint32_t))
1345
1346/******************************************************************************/
1367uint32_t alt_qspi_sram_partition_get(void);
1368
1369/******************************************************************************/
1384 ALT_STATUS_CODE alt_qspi_sram_partition_set(const uint32_t read_part_size);
1385
1390/******************************************************************************/
1398/******************************************************************************/
1411 ALT_STATUS_CODE alt_qspi_erase_subsector(const uint32_t addr);
1412
1413/******************************************************************************/
1426 ALT_STATUS_CODE alt_qspi_erase_sector(const uint32_t addr);
1427
1428/******************************************************************************/
1435 ALT_STATUS_CODE alt_qspi_erase_chip(void);
1436
1439/******************************************************************************/
1464/******************************************************************************/
1471 ALT_STATUS_CODE alt_qspi_dma_disable(void);
1472
1473/******************************************************************************/
1483 ALT_STATUS_CODE alt_qspi_dma_enable(void);
1484
1485/******************************************************************************/
1503 ALT_STATUS_CODE alt_qspi_dma_config_get(uint32_t * single_type_sz,
1504 uint32_t * burst_type_sz);
1505
1506/******************************************************************************/
1530 ALT_STATUS_CODE alt_qspi_dma_config_set(const uint32_t single_type_sz,
1531 const uint32_t burst_type_sz);
1532
1533
1538#ifdef __cplusplus
1539}
1540#endif /* __cplusplus */
1541#endif /* __ALT_QSPI_H__ */
alt_qspi_sram_partition_set
ALT_STATUS_CODE alt_qspi_sram_partition_set(const uint32_t read_part_size)
Definition: alt_qspi.c:1947
alt_qspi_sram_partition_get
uint32_t alt_qspi_sram_partition_get(void)
Definition: alt_qspi.c:1937
alt_qspi_disable
ALT_STATUS_CODE alt_qspi_disable(void)
Definition: alt_qspi.c:415
alt_qspi_enable
ALT_STATUS_CODE alt_qspi_enable(void)
Definition: alt_qspi.c:422
alt_qspi_int_status_get
uint32_t alt_qspi_int_status_get(void)
Definition: alt_qspi.c:525
alt_qspi_int_enable
ALT_STATUS_CODE alt_qspi_int_enable(const uint32_t mask)
Definition: alt_qspi.c:565
ALT_QSPI_INT_STATUS_e
ALT_QSPI_INT_STATUS_e
Definition: alt_qspi.h:158
alt_qspi_int_disable
ALT_STATUS_CODE alt_qspi_int_disable(const uint32_t mask)
Definition: alt_qspi.c:546
ALT_QSPI_INT_STATUS_t
enum ALT_QSPI_INT_STATUS_e ALT_QSPI_INT_STATUS_t
alt_qspi_uninit
ALT_STATUS_CODE alt_qspi_uninit(void)
Definition: alt_qspi.c:407
alt_qspi_is_idle
bool alt_qspi_is_idle(void)
Definition: alt_qspi.c:586
alt_qspi_init
ALT_STATUS_CODE alt_qspi_init(void)
Definition: alt_qspi.c:312
alt_qspi_int_clear
ALT_STATUS_CODE alt_qspi_int_clear(const uint32_t mask)
Definition: alt_qspi.c:532
ALT_QSPI_INT_STATUS_ILL_AHB_ACCESS
@ ALT_QSPI_INT_STATUS_ILL_AHB_ACCESS
Definition: alt_qspi.h:199
ALT_QSPI_INT_STATUS_IDAC_WTRMK_TRIG
@ ALT_QSPI_INT_STATUS_IDAC_WTRMK_TRIG
Definition: alt_qspi.h:204
ALT_QSPI_INT_STATUS_IDAC_OP_COMPLETE
@ ALT_QSPI_INT_STATUS_IDAC_OP_COMPLETE
Definition: alt_qspi.h:182
ALT_QSPI_INT_STATUS_TX_FIFO_NOT_FULL
@ ALT_QSPI_INT_STATUS_TX_FIFO_NOT_FULL
Definition: alt_qspi.h:224
ALT_QSPI_INT_STATUS_RX_FIFO_FULL
@ ALT_QSPI_INT_STATUS_RX_FIFO_FULL
Definition: alt_qspi.h:248
ALT_QSPI_INT_STATUS_RX_OVF
@ ALT_QSPI_INT_STATUS_RX_OVF
Definition: alt_qspi.h:216
ALT_QSPI_INT_STATUS_IDAC_OP_REJECT
@ ALT_QSPI_INT_STATUS_IDAC_OP_REJECT
Definition: alt_qspi.h:188
ALT_QSPI_INT_STATUS_IDAC_RD_FULL
@ ALT_QSPI_INT_STATUS_IDAC_RD_FULL
Definition: alt_qspi.h:254
ALT_QSPI_INT_STATUS_TX_FIFO_FULL
@ ALT_QSPI_INT_STATUS_TX_FIFO_FULL
Definition: alt_qspi.h:232
ALT_QSPI_INT_STATUS_WR_PROT_VIOL
@ ALT_QSPI_INT_STATUS_WR_PROT_VIOL
Definition: alt_qspi.h:193
ALT_QSPI_INT_STATUS_UFL
@ ALT_QSPI_INT_STATUS_UFL
Definition: alt_qspi.h:177
ALT_QSPI_INT_STATUS_RX_FIFO_NOT_EMPTY
@ ALT_QSPI_INT_STATUS_RX_FIFO_NOT_EMPTY
Definition: alt_qspi.h:240
ALT_QSPI_INT_STATUS_MODE_FAIL
@ ALT_QSPI_INT_STATUS_MODE_FAIL
Definition: alt_qspi.h:167
alt_qspi_ahb_address_remap_enable
ALT_STATUS_CODE alt_qspi_ahb_address_remap_enable(void)
Definition: alt_qspi.c:1647
alt_qspi_ahb_remap_address_get
uint32_t alt_qspi_ahb_remap_address_get(void)
Definition: alt_qspi.c:1619
alt_qspi_ahb_address_remap_disable
ALT_STATUS_CODE alt_qspi_ahb_address_remap_disable(void)
Definition: alt_qspi.c:1638
alt_qspi_direct_disable
ALT_STATUS_CODE alt_qspi_direct_disable(void)
Definition: alt_qspi.c:1601
alt_qspi_ahb_remap_address_set
ALT_STATUS_CODE alt_qspi_ahb_remap_address_set(const uint32_t ahb_remap_addr)
Definition: alt_qspi.c:1625
alt_qspi_direct_enable
ALT_STATUS_CODE alt_qspi_direct_enable(void)
Definition: alt_qspi.c:1610
ALT_QSPI_CS_MODE_t
enum ALT_QSPI_CS_MODE_e ALT_QSPI_CS_MODE_t
alt_qspi_device_size_config_get
ALT_STATUS_CODE alt_qspi_device_size_config_get(ALT_QSPI_DEV_SIZE_CONFIG_t *cfg)
Definition: alt_qspi.c:1245
ALT_QSPI_CS_MODE_e
ALT_QSPI_CS_MODE_e
Definition: alt_qspi.h:488
alt_qspi_timing_config_set
ALT_STATUS_CODE alt_qspi_timing_config_set(const ALT_QSPI_TIMING_CONFIG_t *cfg)
Definition: alt_qspi.c:1524
alt_qspi_chip_select_config_set
ALT_STATUS_CODE alt_qspi_chip_select_config_set(const uint32_t cs, const ALT_QSPI_CS_MODE_t cs_mode)
Definition: alt_qspi.c:1167
ALT_QSPI_CLK_POLARITY_t
enum ALT_QSPI_CLK_POLARITY_e ALT_QSPI_CLK_POLARITY_t
alt_qspi_baud_rate_div_get
ALT_QSPI_BAUD_DIV_t alt_qspi_baud_rate_div_get(void)
Definition: alt_qspi.c:1134
alt_qspi_chip_select_config_get
ALT_STATUS_CODE alt_qspi_chip_select_config_get(uint32_t *cs, ALT_QSPI_CS_MODE_t *cs_mode)
Definition: alt_qspi.c:1156
ALT_QSPI_CLK_POLARITY_e
ALT_QSPI_CLK_POLARITY_e
Definition: alt_qspi.h:584
ALT_QSPI_BAUD_DIV_t
enum ALT_QSPI_BAUD_DIV_e ALT_QSPI_BAUD_DIV_t
alt_qspi_timing_config_get
ALT_STATUS_CODE alt_qspi_timing_config_get(ALT_QSPI_TIMING_CONFIG_t *cfg)
Definition: alt_qspi.c:1504
ALT_QSPI_CLK_PHASE_t
enum ALT_QSPI_CLK_PHASE_e ALT_QSPI_CLK_PHASE_t
ALT_QSPI_DEV_SIZE_CONFIG_t
struct ALT_QSPI_DEV_SIZE_CONFIG_s ALT_QSPI_DEV_SIZE_CONFIG_t
ALT_QSPI_DEV_INST_CONFIG_t
struct ALT_QSPI_DEV_INST_CONFIG_s ALT_QSPI_DEV_INST_CONFIG_t
alt_qspi_device_size_config_set
ALT_STATUS_CODE alt_qspi_device_size_config_set(const ALT_QSPI_DEV_SIZE_CONFIG_t *cfg)
Definition: alt_qspi.c:1274
alt_qspi_mode_bit_config_get
uint32_t alt_qspi_mode_bit_config_get(void)
Definition: alt_qspi.c:1216
ALT_QSPI_MODE_t
enum ALT_QSPI_MODE_e ALT_QSPI_MODE_t
ALT_QSPI_CLK_PHASE_e
ALT_QSPI_CLK_PHASE_e
Definition: alt_qspi.h:570
ALT_QSPI_MODE_e
ALT_QSPI_MODE_e
Definition: alt_qspi.h:468
alt_qspi_baud_rate_div_set
ALT_STATUS_CODE alt_qspi_baud_rate_div_set(const ALT_QSPI_BAUD_DIV_t baud_rate_div)
Definition: alt_qspi.c:1140
ALT_QSPI_TIMING_CONFIG_t
struct ALT_QSPI_TIMING_CONFIG_s ALT_QSPI_TIMING_CONFIG_t
alt_qspi_device_read_config_get
ALT_STATUS_CODE alt_qspi_device_read_config_get(ALT_QSPI_DEV_INST_CONFIG_t *cfg)
Definition: alt_qspi.c:1325
alt_qspi_mode_bit_disable
ALT_STATUS_CODE alt_qspi_mode_bit_disable(void)
Definition: alt_qspi.c:1198
ALT_QSPI_BAUD_DIV_e
ALT_QSPI_BAUD_DIV_e
Definition: alt_qspi.h:501
alt_qspi_mode_bit_enable
ALT_STATUS_CODE alt_qspi_mode_bit_enable(void)
Definition: alt_qspi.c:1207
alt_qspi_mode_bit_config_set
ALT_STATUS_CODE alt_qspi_mode_bit_config_set(const uint32_t mode_bits)
Definition: alt_qspi.c:1223
alt_qspi_device_read_config_set
ALT_STATUS_CODE alt_qspi_device_read_config_set(const ALT_QSPI_DEV_INST_CONFIG_t *cfg)
Definition: alt_qspi.c:1339
alt_qspi_device_write_config_get
ALT_STATUS_CODE alt_qspi_device_write_config_get(ALT_QSPI_DEV_INST_CONFIG_t *cfg)
Definition: alt_qspi.c:1410
alt_qspi_device_write_config_set
ALT_STATUS_CODE alt_qspi_device_write_config_set(const ALT_QSPI_DEV_INST_CONFIG_t *cfg)
Definition: alt_qspi.c:1427
ALT_QSPI_CS_MODE_SINGLE_SELECT
@ ALT_QSPI_CS_MODE_SINGLE_SELECT
Definition: alt_qspi.h:489
ALT_QSPI_CS_MODE_DECODE
@ ALT_QSPI_CS_MODE_DECODE
Definition: alt_qspi.h:491
ALT_QSPI_CLK_POLARITY_LOW
@ ALT_QSPI_CLK_POLARITY_LOW
Definition: alt_qspi.h:585
ALT_QSPI_CLK_POLARITY_HIGH
@ ALT_QSPI_CLK_POLARITY_HIGH
Definition: alt_qspi.h:588
ALT_QSPI_CLK_PHASE_ACTIVE
@ ALT_QSPI_CLK_PHASE_ACTIVE
Definition: alt_qspi.h:571
ALT_QSPI_CLK_PHASE_INACTIVE
@ ALT_QSPI_CLK_PHASE_INACTIVE
Definition: alt_qspi.h:574
ALT_QSPI_MODE_DUAL
@ ALT_QSPI_MODE_DUAL
Definition: alt_qspi.h:473
ALT_QSPI_MODE_QUAD
@ ALT_QSPI_MODE_QUAD
Definition: alt_qspi.h:476
ALT_QSPI_MODE_SINGLE
@ ALT_QSPI_MODE_SINGLE
Definition: alt_qspi.h:469
ALT_QSPI_BAUD_DIV_8
@ ALT_QSPI_BAUD_DIV_8
Definition: alt_qspi.h:505
ALT_QSPI_BAUD_DIV_12
@ ALT_QSPI_BAUD_DIV_12
Definition: alt_qspi.h:507
ALT_QSPI_BAUD_DIV_26
@ ALT_QSPI_BAUD_DIV_26
Definition: alt_qspi.h:514
ALT_QSPI_BAUD_DIV_10
@ ALT_QSPI_BAUD_DIV_10
Definition: alt_qspi.h:506
ALT_QSPI_BAUD_DIV_6
@ ALT_QSPI_BAUD_DIV_6
Definition: alt_qspi.h:504
ALT_QSPI_BAUD_DIV_28
@ ALT_QSPI_BAUD_DIV_28
Definition: alt_qspi.h:515
ALT_QSPI_BAUD_DIV_20
@ ALT_QSPI_BAUD_DIV_20
Definition: alt_qspi.h:511
ALT_QSPI_BAUD_DIV_30
@ ALT_QSPI_BAUD_DIV_30
Definition: alt_qspi.h:516
ALT_QSPI_BAUD_DIV_14
@ ALT_QSPI_BAUD_DIV_14
Definition: alt_qspi.h:508
ALT_QSPI_BAUD_DIV_32
@ ALT_QSPI_BAUD_DIV_32
Definition: alt_qspi.h:517
ALT_QSPI_BAUD_DIV_18
@ ALT_QSPI_BAUD_DIV_18
Definition: alt_qspi.h:510
ALT_QSPI_BAUD_DIV_2
@ ALT_QSPI_BAUD_DIV_2
Definition: alt_qspi.h:502
ALT_QSPI_BAUD_DIV_22
@ ALT_QSPI_BAUD_DIV_22
Definition: alt_qspi.h:512
ALT_QSPI_BAUD_DIV_16
@ ALT_QSPI_BAUD_DIV_16
Definition: alt_qspi.h:509
ALT_QSPI_BAUD_DIV_4
@ ALT_QSPI_BAUD_DIV_4
Definition: alt_qspi.h:503
ALT_QSPI_BAUD_DIV_24
@ ALT_QSPI_BAUD_DIV_24
Definition: alt_qspi.h:513
alt_qspi_dma_disable
ALT_STATUS_CODE alt_qspi_dma_disable(void)
Definition: alt_qspi.c:2118
alt_qspi_dma_config_set
ALT_STATUS_CODE alt_qspi_dma_config_set(const uint32_t single_type_sz, const uint32_t burst_type_sz)
Definition: alt_qspi.c:2171
alt_qspi_dma_config_get
ALT_STATUS_CODE alt_qspi_dma_config_get(uint32_t *single_type_sz, uint32_t *burst_type_sz)
Definition: alt_qspi.c:2136
alt_qspi_dma_enable
ALT_STATUS_CODE alt_qspi_dma_enable(void)
Definition: alt_qspi.c:2127
alt_qspi_erase_sector
ALT_STATUS_CODE alt_qspi_erase_sector(const uint32_t addr)
Definition: alt_qspi.c:2005
alt_qspi_erase_subsector
ALT_STATUS_CODE alt_qspi_erase_subsector(const uint32_t addr)
Definition: alt_qspi.c:1988
alt_qspi_erase_chip
ALT_STATUS_CODE alt_qspi_erase_chip(void)
Definition: alt_qspi.c:2034
alt_qspi_write
ALT_STATUS_CODE alt_qspi_write(uint32_t dest, const void *src, size_t size)
Definition: alt_qspi.c:809
alt_qspi_read
ALT_STATUS_CODE alt_qspi_read(void *dest, uint32_t src, size_t size)
Definition: alt_qspi.c:694
alt_qspi_indirect_write_watermark_set
ALT_STATUS_CODE alt_qspi_indirect_write_watermark_set(const uint32_t watermark)
Definition: alt_qspi.c:1913
alt_qspi_indirect_read_start
ALT_STATUS_CODE alt_qspi_indirect_read_start(const uint32_t flash_addr, const size_t num_bytes)
Definition: alt_qspi.c:1669
alt_qspi_indirect_write_start
ALT_STATUS_CODE alt_qspi_indirect_write_start(const uint32_t flash_addr, const size_t num_bytes)
Definition: alt_qspi.c:1793
alt_qspi_indirect_read_cancel
ALT_STATUS_CODE alt_qspi_indirect_read_cancel(void)
Definition: alt_qspi.c:1737
alt_qspi_indirect_read_watermark_get
uint32_t alt_qspi_indirect_read_watermark_get(void)
Definition: alt_qspi.c:1754
alt_qspi_indirect_read_is_complete
bool alt_qspi_indirect_read_is_complete(void)
Definition: alt_qspi.c:1774
alt_qspi_indirect_write_finish
ALT_STATUS_CODE alt_qspi_indirect_write_finish(void)
Definition: alt_qspi.c:1869
alt_qspi_indirect_write_watermark_get
uint32_t alt_qspi_indirect_write_watermark_get(void)
Definition: alt_qspi.c:1907
alt_qspi_indirect_read_finish
ALT_STATUS_CODE alt_qspi_indirect_read_finish(void)
Definition: alt_qspi.c:1732
alt_qspi_indirect_read_watermark_set
ALT_STATUS_CODE alt_qspi_indirect_read_watermark_set(const uint32_t watermark)
Definition: alt_qspi.c:1760
alt_qspi_indirect_write_cancel
ALT_STATUS_CODE alt_qspi_indirect_write_cancel(void)
Definition: alt_qspi.c:1878
alt_qspi_indirect_write_fill_level
uint32_t alt_qspi_indirect_write_fill_level(void)
Definition: alt_qspi.c:1899
alt_qspi_indirect_write_is_complete
bool alt_qspi_indirect_write_is_complete(void)
Definition: alt_qspi.c:1927
alt_qspi_indirect_read_fill_level
uint32_t alt_qspi_indirect_read_fill_level(void)
Definition: alt_qspi.c:1746
hwlib.h
ALT_STATUS_CODE
int32_t ALT_STATUS_CODE
Definition: hwlib.h:60
ALT_QSPI_DEV_INST_CONFIG_s
Definition: alt_qspi.h:683
ALT_QSPI_DEV_INST_CONFIG_s::inst_type
ALT_QSPI_MODE_t inst_type
Definition: alt_qspi.h:687
ALT_QSPI_DEV_INST_CONFIG_s::data_xfer_type
ALT_QSPI_MODE_t data_xfer_type
Definition: alt_qspi.h:705
ALT_QSPI_DEV_INST_CONFIG_s::dummy_cycles
uint32_t dummy_cycles
Definition: alt_qspi.h:714
ALT_QSPI_DEV_INST_CONFIG_s::addr_xfer_type
ALT_QSPI_MODE_t addr_xfer_type
Definition: alt_qspi.h:696
ALT_QSPI_DEV_INST_CONFIG_s::op_code
uint32_t op_code
Definition: alt_qspi.h:684
ALT_QSPI_DEV_SIZE_CONFIG_s
Definition: alt_qspi.h:528
ALT_QSPI_DEV_SIZE_CONFIG_s::upper_wrprot_block
uint32_t upper_wrprot_block
Definition: alt_qspi.h:550
ALT_QSPI_DEV_SIZE_CONFIG_s::wrprot_enable
bool wrprot_enable
Definition: alt_qspi.h:556
ALT_QSPI_DEV_SIZE_CONFIG_s::addr_size
uint32_t addr_size
Definition: alt_qspi.h:539
ALT_QSPI_DEV_SIZE_CONFIG_s::page_size
uint32_t page_size
Definition: alt_qspi.h:534
ALT_QSPI_DEV_SIZE_CONFIG_s::lower_wrprot_block
uint32_t lower_wrprot_block
Definition: alt_qspi.h:544
ALT_QSPI_DEV_SIZE_CONFIG_s::block_size
uint32_t block_size
Definition: alt_qspi.h:529
ALT_QSPI_TIMING_CONFIG_s
Definition: alt_qspi.h:603
ALT_QSPI_TIMING_CONFIG_s::cs_da
uint32_t cs_da
Definition: alt_qspi.h:613
ALT_QSPI_TIMING_CONFIG_s::cs_dads
uint32_t cs_dads
Definition: alt_qspi.h:621
ALT_QSPI_TIMING_CONFIG_s::cs_sot
uint32_t cs_sot
Definition: alt_qspi.h:647
ALT_QSPI_TIMING_CONFIG_s::rd_datacap
uint32_t rd_datacap
Definition: alt_qspi.h:659
ALT_QSPI_TIMING_CONFIG_s::clk_pol
ALT_QSPI_CLK_POLARITY_t clk_pol
Definition: alt_qspi.h:609
ALT_QSPI_TIMING_CONFIG_s::clk_phase
ALT_QSPI_CLK_PHASE_t clk_phase
Definition: alt_qspi.h:604
ALT_QSPI_TIMING_CONFIG_s::cs_eot
uint32_t cs_eot
Definition: alt_qspi.h:634