RTEMS: cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h Source File

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cpu.h
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1
10/*
11 * This include file contains information pertaining to the XXX
12 * processor.
13 *
14 * @note This file is part of a porting template that is intended
15 * to be used as the starting point when porting RTEMS to a new
16 * CPU family. The following needs to be done when using this as
17 * the starting point for a new port:
18 *
19 * + Anywhere there is an XXX, it should be replaced
20 * with information about the CPU family being ported to.
21 *
22 * + At the end of each comment section, there is a heading which
23 * says "Port Specific Information:". When porting to RTEMS,
24 * add CPU family specific information in this section
25 */
26
27/*
28 * COPYRIGHT (c) 1989-2008.
29 * On-Line Applications Research Corporation (OAR).
30 *
31 * The license and distribution terms for this file may be
32 * found in the file LICENSE in this distribution or at
33 * http://www.rtems.org/license/LICENSE.
34 */
35
36#ifndef _RTEMS_SCORE_CPU_H
37#define _RTEMS_SCORE_CPU_H
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43#include <rtems/score/basedefs.h>
44#include <rtems/score/no_cpu.h>
45
46/* conditional compilation parameters */
47
59#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
60
70#define CPU_ISR_PASSES_FRAME_POINTER FALSE
71
107#if ( NO_CPU_HAS_FPU == 1 )
108#define CPU_HARDWARE_FP TRUE
109#else
110#define CPU_HARDWARE_FP FALSE
111#endif
112#define CPU_SOFTWARE_FP FALSE
113
138#define CPU_ALL_TASKS_ARE_FP TRUE
139
155#define CPU_IDLE_TASK_IS_FP FALSE
156
186#define CPU_USE_DEFERRED_FP_SWITCH TRUE
187
198#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
199
211#define CPU_STACK_GROWS_UP TRUE
212
218#define CPU_CACHE_LINE_BYTES 32
219
231#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
232
244#define CPU_MODES_INTERRUPT_MASK 0x00000001
245
250#define CPU_MAXIMUM_PROCESSORS 32
251
252/*
253 * Processor defined structures required for cpukit/score.
254 *
255 * Port Specific Information:
256 *
257 * XXX document implementation including references if appropriate
258 */
259
260/* may need to put some structures here. */
261
323typedef struct {
328 uint32_t some_integer_register;
333 uint32_t some_system_register;
334
339 uint32_t stack_pointer;
340
341#ifdef RTEMS_SMP
386 volatile bool is_executing;
387#endif
388} Context_Control;
389
399#define _CPU_Context_Get_SP( _context ) \
400 (_context)->stack_pointer
401
408typedef struct {
410 double some_float_register;
411} Context_Control_fp;
412
420typedef struct {
426 uint32_t special_interrupt_register;
427} CPU_Interrupt_frame;
428
439extern Context_Control_fp _CPU_Null_fp_context;
440
459/*
460 * Nothing prevents the porter from declaring more CPU specific variables.
461 *
462 * Port Specific Information:
463 *
464 * XXX document implementation including references if appropriate
465 */
466
467/* XXX: if needed, put more variables here */
468
481#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
482
492#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
493
504#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
505
516#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
517
524#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
525
536#define CPU_STACK_MINIMUM_SIZE (1024*4)
537
545#define CPU_SIZEOF_POINTER 4
546
558#define CPU_ALIGNMENT 8
559
582#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
583
597#define CPU_STACK_ALIGNMENT 0
598
605#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
606
607/*
608 * ISR handler macros
609 */
610
620#define _CPU_Initialize_vectors()
621
634#define _CPU_ISR_Disable( _isr_cookie ) \
635 { \
636 (_isr_cookie) = 0; /* do something to prevent warnings */ \
637 }
638
652#define _CPU_ISR_Enable( _isr_cookie ) \
653 { \
654 }
655
670#define _CPU_ISR_Flash( _isr_cookie ) \
671 { \
672 }
673
683 RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
684{
685 return false;
686}
687
705#define _CPU_ISR_Set_level( new_level ) \
706 { \
707 }
708
721uint32_t _CPU_ISR_Get_level( void );
722
723/* end of ISR handler macros */
724
725/* Context handler macros */
726
742#define _CPU_Context_Destroy( _the_thread, _the_context ) \
743 { \
744 }
745
783#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
784 _isr, _entry_point, _is_fp, _tls_area ) \
785 { \
786 }
787
803#define _CPU_Context_Restart_self( _the_context ) \
804 _CPU_Context_restore( (_the_context) );
805
824#define _CPU_Context_Initialize_fp( _destination ) \
825 { \
826 *(*(_destination)) = _CPU_Null_fp_context; \
827 }
828
829/* end of Context handler macros */
830
831/* Fatal Error manager macros */
832
842#define _CPU_Fatal_halt( _source, _error ) \
843 { \
844 }
845
846/* end of Fatal Error manager macros */
847
848/* Bitfield handler macros */
849
865#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
866
931#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
932#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
933 { \
934 (_output) = 0; /* do something to prevent warnings */ \
935 }
936#endif
937
940/* end of Bitfield handler macros */
941
951#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
952
953#define _CPU_Priority_Mask( _bit_number ) \
954 ( 1 << (_bit_number) )
955
956#endif
957
972#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
973
974#define _CPU_Priority_bits_index( _priority ) \
975 (_priority)
976
977#endif
978
979/* end of Priority handler macros */
980
981/* functions */
982
990void _CPU_Initialize(void);
991
992typedef void ( *CPU_ISR_raw_handler )( void );
993
1010void _CPU_ISR_install_raw_handler(
1011 uint32_t vector,
1012 CPU_ISR_raw_handler new_handler,
1013 CPU_ISR_raw_handler *old_handler
1014);
1015
1016typedef void ( *CPU_ISR_handler )( uint32_t );
1017
1034void _CPU_ISR_install_vector(
1035 uint32_t vector,
1036 CPU_ISR_handler new_handler,
1037 CPU_ISR_handler *old_handler
1038);
1039
1047void *_CPU_Thread_Idle_body( uintptr_t ignored );
1048
1061void _CPU_Context_switch(
1062 Context_Control *run,
1063 Context_Control *heir
1064);
1065
1080void _CPU_Context_restore(
1081 Context_Control *new_context
1082) RTEMS_NO_RETURN;
1083
1099void _CPU_Context_save_fp(
1100 Context_Control_fp **fp_context_ptr
1101);
1102
1118void _CPU_Context_restore_fp(
1119 Context_Control_fp **fp_context_ptr
1120);
1121
1131typedef struct {
1132 uint32_t processor_state_register;
1133 uint32_t integer_registers [1];
1134 double float_registers [1];
1135} CPU_Exception_frame;
1136
1142void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1143
1181static inline uint32_t CPU_swap_u32(
1182 uint32_t value
1183)
1184{
1185 uint32_t byte1, byte2, byte3, byte4, swapped;
1186
1187 byte4 = (value >> 24) & 0xff;
1188 byte3 = (value >> 16) & 0xff;
1189 byte2 = (value >> 8) & 0xff;
1190 byte1 = value & 0xff;
1191
1192 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1193 return swapped;
1194}
1195
1202#define CPU_swap_u16( value ) \
1203 (((value&0xff) << 8) | ((value >> 8)&0xff))
1204
1210 typedef uint32_t CPU_Counter_ticks;
1211
1217uint32_t _CPU_Counter_frequency( void );
1218
1229CPU_Counter_ticks _CPU_Counter_read( void );
1230
1243static inline CPU_Counter_ticks _CPU_Counter_difference(
1244 CPU_Counter_ticks second,
1245 CPU_Counter_ticks first
1246)
1247{
1248 return second - first;
1249}
1250
1251#ifdef RTEMS_SMP
1265 uint32_t _CPU_SMP_Initialize( void );
1266
1280 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1281
1296 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1297
1308 void _CPU_SMP_Prepare_start_multitasking( void );
1309
1317 static inline uint32_t _CPU_SMP_Get_current_processor( void )
1318 {
1319 return 123;
1320 }
1321
1330 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1331
1343 static inline void _CPU_SMP_Processor_event_broadcast( void )
1344 {
1345 __asm__ volatile ( "" : : : "memory" );
1346 }
1347
1356 static inline void _CPU_SMP_Processor_event_receive( void )
1357 {
1358 __asm__ volatile ( "" : : : "memory" );
1359 }
1360
1366 static inline bool _CPU_Context_Get_is_executing(
1367 const Context_Control *context
1368 )
1369 {
1370 return context->is_executing;
1371 }
1372
1379 static inline void _CPU_Context_Set_is_executing(
1380 Context_Control *context,
1381 bool is_executing
1382 )
1383 {
1384 context->is_executing = is_executing;
1385 }
1386
1388typedef uintptr_t CPU_Uint32ptr;
1389
1390#endif
1391
1392#ifdef __cplusplus
1393}
1394#endif
1395
1396#endif
basedefs.h
Basic Definitions.
_CPU_ISR_install_raw_handler
void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.c:103
RTEMS_NO_RETURN
#define RTEMS_NO_RETURN
Definition: basedefs.h:102
RTEMS_INLINE_ROUTINE
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:66
_CPU_Thread_Idle_body
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
_CPU_Initialize
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
CPU_Uint32ptr
uintptr_t CPU_Uint32ptr
Definition: cpu.h:662
_CPU_ISR_install_vector
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
_CPU_Exception_frame_print
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
_CPU_Counter_frequency
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
_CPU_Context_switch
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
_CPU_Counter_read
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
_CPU_Context_restore_fp
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:904
_CPU_Context_save_fp
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:898
CPU_Exception_frame
The set of registers that specifies the complete processor state.
Definition: cpu.h:629
CPU_Interrupt_frame
Interrupt stack frame (ISF).
Definition: cpu.h:191
Context_Control_fp
SPARC basic context.
Definition: cpu.h:194
Context_Control_fp::some_float_register
double some_float_register
Definition: cpu.h:410
Context_Control
Thread register context.
Definition: cpu.h:194
Context_Control::some_integer_register
uint32_t some_integer_register
Definition: cpu.h:328
Context_Control::some_system_register
uint32_t some_system_register
Definition: cpu.h:333
Context_Control::stack_pointer
uint32_t stack_pointer
Definition: cpu.h:339