RTEMS: bsps/arm/atsam/include/libchip/include/same70/component/component_mcan.h Source File

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component_mcan.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAME70_MCAN_COMPONENT_
31#define _SAME70_MCAN_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41 typedef struct {
42 __I uint32_t Reserved1[2];
43 __IO uint32_t MCAN_CUST;
44 __IO uint32_t MCAN_FBTP;
45 __IO uint32_t MCAN_TEST;
46 __IO uint32_t MCAN_RWD;
47 __IO uint32_t MCAN_CCCR;
48 __IO uint32_t MCAN_BTP;
49 __IO uint32_t MCAN_TSCC;
50 __IO uint32_t MCAN_TSCV;
51 __IO uint32_t MCAN_TOCC;
52 __IO uint32_t MCAN_TOCV;
53 __I uint32_t Reserved2[4];
54 __I uint32_t MCAN_ECR;
55 __I uint32_t MCAN_PSR;
56 __I uint32_t Reserved3[2];
57 __IO uint32_t MCAN_IR;
58 __IO uint32_t MCAN_IE;
59 __IO uint32_t MCAN_ILS;
60 __IO uint32_t MCAN_ILE;
61 __I uint32_t Reserved4[8];
62 __IO uint32_t MCAN_GFC;
63 __IO uint32_t MCAN_SIDFC;
64 __IO uint32_t MCAN_XIDFC;
65 __I uint32_t Reserved5[1];
66 __IO uint32_t MCAN_XIDAM;
67 __I uint32_t MCAN_HPMS;
68 __IO uint32_t MCAN_NDAT1;
69 __IO uint32_t MCAN_NDAT2;
70 __IO uint32_t MCAN_RXF0C;
71 __I uint32_t MCAN_RXF0S;
72 __IO uint32_t MCAN_RXF0A;
73 __IO uint32_t MCAN_RXBC;
74 __IO uint32_t MCAN_RXF1C;
75 __I uint32_t MCAN_RXF1S;
76 __IO uint32_t MCAN_RXF1A;
77 __IO uint32_t MCAN_RXESC;
78 __IO uint32_t MCAN_TXBC;
79 __I uint32_t MCAN_TXFQS;
80 __IO uint32_t MCAN_TXESC;
81 __I uint32_t MCAN_TXBRP;
82 __IO uint32_t MCAN_TXBAR;
83 __IO uint32_t MCAN_TXBCR;
84 __I uint32_t MCAN_TXBTO;
85 __I uint32_t MCAN_TXBCF;
86 __IO uint32_t MCAN_TXBTIE;
87 __IO uint32_t MCAN_TXBCIE;
88 __I uint32_t Reserved6[2];
89 __IO uint32_t MCAN_TXEFC;
90 __I uint32_t MCAN_TXEFS;
91 __IO uint32_t MCAN_TXEFA;
92} Mcan;
93#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
94/* -------- MCAN_CUST : (MCAN Offset: 0x08) Customer Register -------- */
95#define MCAN_CUST_CSV_Pos 0
96#define MCAN_CUST_CSV_Msk (0xffffffffu << MCAN_CUST_CSV_Pos)
97#define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos)))
98/* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */
99#define MCAN_FBTP_FSJW_Pos 0
100#define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos)
101#define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos)))
102#define MCAN_FBTP_FTSEG2_Pos 4
103#define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos)
104#define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos)))
105#define MCAN_FBTP_FTSEG1_Pos 8
106#define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos)
107#define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos)))
108#define MCAN_FBTP_FBRP_Pos 16
109#define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos)
110#define MCAN_FBTP_FBRP(value) ((MCAN_FBTP_FBRP_Msk & ((value) << MCAN_FBTP_FBRP_Pos)))
111#define MCAN_FBTP_TDC (0x1u << 23)
112#define MCAN_FBTP_TDC_DISABLED (0x0u << 23)
113#define MCAN_FBTP_TDC_ENABLED (0x1u << 23)
114#define MCAN_FBTP_TDCO_Pos 24
115#define MCAN_FBTP_TDCO_Msk (0x1fu << MCAN_FBTP_TDCO_Pos)
116#define MCAN_FBTP_TDCO(value) ((MCAN_FBTP_TDCO_Msk & ((value) << MCAN_FBTP_TDCO_Pos)))
117/* -------- MCAN_TEST : (MCAN Offset: 0x10) Test Register -------- */
118#define MCAN_TEST_LBCK (0x1u << 4)
119#define MCAN_TEST_LBCK_DISABLED (0x0u << 4)
120#define MCAN_TEST_LBCK_ENABLED (0x1u << 4)
121#define MCAN_TEST_TX_Pos 5
122#define MCAN_TEST_TX_Msk (0x3u << MCAN_TEST_TX_Pos)
123#define MCAN_TEST_TX(value) ((MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos)))
124#define MCAN_TEST_TX_RESET (0x0u << 5)
125#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (0x1u << 5)
126#define MCAN_TEST_TX_DOMINANT (0x2u << 5)
127#define MCAN_TEST_TX_RECESSIVE (0x3u << 5)
128#define MCAN_TEST_RX (0x1u << 7)
129#define MCAN_TEST_TDCV_Pos 8
130#define MCAN_TEST_TDCV_Msk (0x3fu << MCAN_TEST_TDCV_Pos)
131#define MCAN_TEST_TDCV(value) ((MCAN_TEST_TDCV_Msk & ((value) << MCAN_TEST_TDCV_Pos)))
132/* -------- MCAN_RWD : (MCAN Offset: 0x14) RAM Watchdog Register -------- */
133#define MCAN_RWD_WDC_Pos 0
134#define MCAN_RWD_WDC_Msk (0xffu << MCAN_RWD_WDC_Pos)
135#define MCAN_RWD_WDC(value) ((MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos)))
136#define MCAN_RWD_WDV_Pos 8
137#define MCAN_RWD_WDV_Msk (0xffu << MCAN_RWD_WDV_Pos)
138#define MCAN_RWD_WDV(value) ((MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos)))
139/* -------- MCAN_CCCR : (MCAN Offset: 0x18) CC Control Register -------- */
140#define MCAN_CCCR_INIT (0x1u << 0)
141#define MCAN_CCCR_INIT_DISABLED (0x0u << 0)
142#define MCAN_CCCR_INIT_ENABLED (0x1u << 0)
143#define MCAN_CCCR_CCE (0x1u << 1)
144#define MCAN_CCCR_CCE_PROTECTED (0x0u << 1)
145#define MCAN_CCCR_CCE_CONFIGURABLE (0x1u << 1)
146#define MCAN_CCCR_ASM (0x1u << 2)
147#define MCAN_CCCR_ASM_NORMAL (0x0u << 2)
148#define MCAN_CCCR_ASM_RESTRICTED (0x1u << 2)
149#define MCAN_CCCR_CSA (0x1u << 3)
150#define MCAN_CCCR_CSR (0x1u << 4)
151#define MCAN_CCCR_CSR_NO_CLOCK_STOP (0x0u << 4)
152#define MCAN_CCCR_CSR_CLOCK_STOP (0x1u << 4)
153#define MCAN_CCCR_MON (0x1u << 5)
154#define MCAN_CCCR_MON_DISABLED (0x0u << 5)
155#define MCAN_CCCR_MON_ENABLED (0x1u << 5)
156#define MCAN_CCCR_DAR (0x1u << 6)
157#define MCAN_CCCR_DAR_AUTO_RETX (0x0u << 6)
158#define MCAN_CCCR_DAR_NO_AUTO_RETX (0x1u << 6)
159#define MCAN_CCCR_TEST (0x1u << 7)
160#define MCAN_CCCR_TEST_DISABLED (0x0u << 7)
161#define MCAN_CCCR_TEST_ENABLED (0x1u << 7)
162#define MCAN_CCCR_CME_Pos 8
163#define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos)
164#define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos)))
165#define MCAN_CCCR_CME_ISO11898_1 (0x0u << 8)
166#define MCAN_CCCR_CME_FD (0x1u << 8)
167#define MCAN_CCCR_CMR_Pos 10
168#define MCAN_CCCR_CMR_Msk (0x3u << MCAN_CCCR_CMR_Pos)
169#define MCAN_CCCR_CMR(value) ((MCAN_CCCR_CMR_Msk & ((value) << MCAN_CCCR_CMR_Pos)))
170#define MCAN_CCCR_CMR_NO_CHANGE (0x0u << 10)
171#define MCAN_CCCR_CMR_FD (0x1u << 10)
172#define MCAN_CCCR_CMR_FD_BITRATE_SWITCH (0x2u << 10)
173#define MCAN_CCCR_CMR_ISO11898_1 (0x3u << 10)
174#define MCAN_CCCR_FDO (0x1u << 12)
175#define MCAN_CCCR_FDBS (0x1u << 13)
176#define MCAN_CCCR_TXP (0x1u << 14)
177/* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */
178#define MCAN_BTP_SJW_Pos 0
179#define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos)
180#define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos)))
181#define MCAN_BTP_TSEG2_Pos 4
182#define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos)
183#define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos)))
184#define MCAN_BTP_TSEG1_Pos 8
185#define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos)
186#define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos)))
187#define MCAN_BTP_BRP_Pos 16
188#define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos)
189#define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos)))
190/* -------- MCAN_TSCC : (MCAN Offset: 0x20) Timestamp Counter Configuration Register -------- */
191#define MCAN_TSCC_TSS_Pos 0
192#define MCAN_TSCC_TSS_Msk (0x3u << MCAN_TSCC_TSS_Pos)
193#define MCAN_TSCC_TSS(value) ((MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos)))
194#define MCAN_TSCC_TSS_ALWAYS_0 (0x0u << 0)
195#define MCAN_TSCC_TSS_TCP_INC (0x1u << 0)
196#define MCAN_TSCC_TSS_EXT_TIMESTAMP (0x2u << 0)
197#define MCAN_TSCC_TCP_Pos 16
198#define MCAN_TSCC_TCP_Msk (0xfu << MCAN_TSCC_TCP_Pos)
199#define MCAN_TSCC_TCP(value) ((MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos)))
200/* -------- MCAN_TSCV : (MCAN Offset: 0x24) Timestamp Counter Value Register -------- */
201#define MCAN_TSCV_TSC_Pos 0
202#define MCAN_TSCV_TSC_Msk (0xffffu << MCAN_TSCV_TSC_Pos)
203#define MCAN_TSCV_TSC(value) ((MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos)))
204/* -------- MCAN_TOCC : (MCAN Offset: 0x28) Timeout Counter Configuration Register -------- */
205#define MCAN_TOCC_ETOC (0x1u << 0)
206#define MCAN_TOCC_ETOC_NO_TIMEOUT (0x0u << 0)
207#define MCAN_TOCC_ETOC_TOS_CONTROLLED (0x1u << 0)
208#define MCAN_TOCC_TOS_Pos 1
209#define MCAN_TOCC_TOS_Msk (0x3u << MCAN_TOCC_TOS_Pos)
210#define MCAN_TOCC_TOS(value) ((MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos)))
211#define MCAN_TOCC_TOS_CONTINUOUS (0x0u << 1)
212#define MCAN_TOCC_TOS_TX_EV_TIMEOUT (0x1u << 1)
213#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (0x2u << 1)
214#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (0x3u << 1)
215#define MCAN_TOCC_TOP_Pos 16
216#define MCAN_TOCC_TOP_Msk (0xffffu << MCAN_TOCC_TOP_Pos)
217#define MCAN_TOCC_TOP(value) ((MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos)))
218/* -------- MCAN_TOCV : (MCAN Offset: 0x2C) Timeout Counter Value Register -------- */
219#define MCAN_TOCV_TOC_Pos 0
220#define MCAN_TOCV_TOC_Msk (0xffffu << MCAN_TOCV_TOC_Pos)
221#define MCAN_TOCV_TOC(value) ((MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos)))
222/* -------- MCAN_ECR : (MCAN Offset: 0x40) Error Counter Register -------- */
223#define MCAN_ECR_TEC_Pos 0
224#define MCAN_ECR_TEC_Msk (0xffu << MCAN_ECR_TEC_Pos)
225#define MCAN_ECR_REC_Pos 8
226#define MCAN_ECR_REC_Msk (0x7fu << MCAN_ECR_REC_Pos)
227#define MCAN_ECR_RP (0x1u << 15)
228#define MCAN_ECR_CEL_Pos 16
229#define MCAN_ECR_CEL_Msk (0xffu << MCAN_ECR_CEL_Pos)
230/* -------- MCAN_PSR : (MCAN Offset: 0x44) Protocol Status Register -------- */
231#define MCAN_PSR_LEC_Pos 0
232#define MCAN_PSR_LEC_Msk (0x7u << MCAN_PSR_LEC_Pos)
233#define MCAN_PSR_LEC_NO_ERROR (0x0u << 0)
234#define MCAN_PSR_LEC_STUFF_ERROR (0x1u << 0)
235#define MCAN_PSR_LEC_FORM_ERROR (0x2u << 0)
236#define MCAN_PSR_LEC_ACK_ERROR (0x3u << 0)
237#define MCAN_PSR_LEC_BIT1_ERROR (0x4u << 0)
238#define MCAN_PSR_LEC_BIT0_ERROR (0x5u << 0)
239#define MCAN_PSR_LEC_CRC_ERROR (0x6u << 0)
240#define MCAN_PSR_LEC_NO_CHANGE (0x7u << 0)
241#define MCAN_PSR_ACT_Pos 3
242#define MCAN_PSR_ACT_Msk (0x3u << MCAN_PSR_ACT_Pos)
243#define MCAN_PSR_ACT_SYNCHRONIZING (0x0u << 3)
244#define MCAN_PSR_ACT_IDLE (0x1u << 3)
245#define MCAN_PSR_ACT_RECEIVER (0x2u << 3)
246#define MCAN_PSR_ACT_TRANSMITTER (0x3u << 3)
247#define MCAN_PSR_EP (0x1u << 5)
248#define MCAN_PSR_EW (0x1u << 6)
249#define MCAN_PSR_BO (0x1u << 7)
250#define MCAN_PSR_FLEC_Pos 8
251#define MCAN_PSR_FLEC_Msk (0x7u << MCAN_PSR_FLEC_Pos)
252#define MCAN_PSR_RESI (0x1u << 11)
253#define MCAN_PSR_RBRS (0x1u << 12)
254#define MCAN_PSR_REDL (0x1u << 13)
255/* -------- MCAN_IR : (MCAN Offset: 0x50) Interrupt Register -------- */
256#define MCAN_IR_RF0N (0x1u << 0)
257#define MCAN_IR_RF0W (0x1u << 1)
258#define MCAN_IR_RF0F (0x1u << 2)
259#define MCAN_IR_RF0L (0x1u << 3)
260#define MCAN_IR_RF1N (0x1u << 4)
261#define MCAN_IR_RF1W (0x1u << 5)
262#define MCAN_IR_RF1F (0x1u << 6)
263#define MCAN_IR_RF1L (0x1u << 7)
264#define MCAN_IR_HPM (0x1u << 8)
265#define MCAN_IR_TC (0x1u << 9)
266#define MCAN_IR_TCF (0x1u << 10)
267#define MCAN_IR_TFE (0x1u << 11)
268#define MCAN_IR_TEFN (0x1u << 12)
269#define MCAN_IR_TEFW (0x1u << 13)
270#define MCAN_IR_TEFF (0x1u << 14)
271#define MCAN_IR_TEFL (0x1u << 15)
272#define MCAN_IR_TSW (0x1u << 16)
273#define MCAN_IR_MRAF (0x1u << 17)
274#define MCAN_IR_TOO (0x1u << 18)
275#define MCAN_IR_DRX (0x1u << 19)
276#define MCAN_IR_ELO (0x1u << 22)
277#define MCAN_IR_EP (0x1u << 23)
278#define MCAN_IR_EW (0x1u << 24)
279#define MCAN_IR_BO (0x1u << 25)
280#define MCAN_IR_WDI (0x1u << 26)
281#define MCAN_IR_CRCE (0x1u << 27)
282#define MCAN_IR_BE (0x1u << 28)
283#define MCAN_IR_ACKE (0x1u << 29)
284#define MCAN_IR_FOE (0x1u << 30)
285#define MCAN_IR_STE (0x1u << 31)
286/* -------- MCAN_IE : (MCAN Offset: 0x54) Interrupt Enable Register -------- */
287#define MCAN_IE_RF0NE (0x1u << 0)
288#define MCAN_IE_RF0WE (0x1u << 1)
289#define MCAN_IE_RF0FE (0x1u << 2)
290#define MCAN_IE_RF0LE (0x1u << 3)
291#define MCAN_IE_RF1NE (0x1u << 4)
292#define MCAN_IE_RF1WE (0x1u << 5)
293#define MCAN_IE_RF1FE (0x1u << 6)
294#define MCAN_IE_RF1LE (0x1u << 7)
295#define MCAN_IE_HPME (0x1u << 8)
296#define MCAN_IE_TCE (0x1u << 9)
297#define MCAN_IE_TCFE (0x1u << 10)
298#define MCAN_IE_TFEE (0x1u << 11)
299#define MCAN_IE_TEFNE (0x1u << 12)
300#define MCAN_IE_TEFWE (0x1u << 13)
301#define MCAN_IE_TEFFE (0x1u << 14)
302#define MCAN_IE_TEFLE (0x1u << 15)
303#define MCAN_IE_TSWE (0x1u << 16)
304#define MCAN_IE_MRAFE (0x1u << 17)
305#define MCAN_IE_TOOE (0x1u << 18)
306#define MCAN_IE_DRXE (0x1u << 19)
307#define MCAN_IE_ELOE (0x1u << 22)
308#define MCAN_IE_EPE (0x1u << 23)
309#define MCAN_IE_EWE (0x1u << 24)
310#define MCAN_IE_BOE (0x1u << 25)
311#define MCAN_IE_WDIE (0x1u << 26)
312#define MCAN_IE_CRCEE (0x1u << 27)
313#define MCAN_IE_BEE (0x1u << 28)
314#define MCAN_IE_ACKEE (0x1u << 29)
315#define MCAN_IE_FOEE (0x1u << 30)
316#define MCAN_IE_STEE (0x1u << 31)
317/* -------- MCAN_ILS : (MCAN Offset: 0x58) Interrupt Line Select Register -------- */
318#define MCAN_ILS_RF0NL (0x1u << 0)
319#define MCAN_ILS_RF0WL (0x1u << 1)
320#define MCAN_ILS_RF0FL (0x1u << 2)
321#define MCAN_ILS_RF0LL (0x1u << 3)
322#define MCAN_ILS_RF1NL (0x1u << 4)
323#define MCAN_ILS_RF1WL (0x1u << 5)
324#define MCAN_ILS_RF1FL (0x1u << 6)
325#define MCAN_ILS_RF1LL (0x1u << 7)
326#define MCAN_ILS_HPML (0x1u << 8)
327#define MCAN_ILS_TCL (0x1u << 9)
328#define MCAN_ILS_TCFL (0x1u << 10)
329#define MCAN_ILS_TFEL (0x1u << 11)
330#define MCAN_ILS_TEFNL (0x1u << 12)
331#define MCAN_ILS_TEFWL (0x1u << 13)
332#define MCAN_ILS_TEFFL (0x1u << 14)
333#define MCAN_ILS_TEFLL (0x1u << 15)
334#define MCAN_ILS_TSWL (0x1u << 16)
335#define MCAN_ILS_MRAFL (0x1u << 17)
336#define MCAN_ILS_TOOL (0x1u << 18)
337#define MCAN_ILS_DRXL (0x1u << 19)
338#define MCAN_ILS_ELOL (0x1u << 22)
339#define MCAN_ILS_EPL (0x1u << 23)
340#define MCAN_ILS_EWL (0x1u << 24)
341#define MCAN_ILS_BOL (0x1u << 25)
342#define MCAN_ILS_WDIL (0x1u << 26)
343#define MCAN_ILS_CRCEL (0x1u << 27)
344#define MCAN_ILS_BEL (0x1u << 28)
345#define MCAN_ILS_ACKEL (0x1u << 29)
346#define MCAN_ILS_FOEL (0x1u << 30)
347#define MCAN_ILS_STEL (0x1u << 31)
348/* -------- MCAN_ILE : (MCAN Offset: 0x5C) Interrupt Line Enable Register -------- */
349#define MCAN_ILE_EINT0 (0x1u << 0)
350#define MCAN_ILE_EINT1 (0x1u << 1)
351/* -------- MCAN_GFC : (MCAN Offset: 0x80) Global Filter Configuration Register -------- */
352#define MCAN_GFC_RRFE (0x1u << 0)
353#define MCAN_GFC_RRFE_FILTER (0x0u << 0)
354#define MCAN_GFC_RRFE_REJECT (0x1u << 0)
355#define MCAN_GFC_RRFS (0x1u << 1)
356#define MCAN_GFC_RRFS_FILTER (0x0u << 1)
357#define MCAN_GFC_RRFS_REJECT (0x1u << 1)
358#define MCAN_GFC_ANFE_Pos 2
359#define MCAN_GFC_ANFE_Msk (0x3u << MCAN_GFC_ANFE_Pos)
360#define MCAN_GFC_ANFE(value) ((MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos)))
361#define MCAN_GFC_ANFE_RX_FIFO_0 (0x0u << 2)
362#define MCAN_GFC_ANFE_RX_FIFO_1 (0x1u << 2)
363#define MCAN_GFC_ANFS_Pos 4
364#define MCAN_GFC_ANFS_Msk (0x3u << MCAN_GFC_ANFS_Pos)
365#define MCAN_GFC_ANFS(value) ((MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos)))
366#define MCAN_GFC_ANFS_RX_FIFO_0 (0x0u << 4)
367#define MCAN_GFC_ANFS_RX_FIFO_1 (0x1u << 4)
368/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) Standard ID Filter Configuration Register -------- */
369#define MCAN_SIDFC_FLSSA_Pos 2
370#define MCAN_SIDFC_FLSSA_Msk (0x3fffu << MCAN_SIDFC_FLSSA_Pos)
371#define MCAN_SIDFC_FLSSA(value) ((MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos)))
372#define MCAN_SIDFC_LSS_Pos 16
373#define MCAN_SIDFC_LSS_Msk (0xffu << MCAN_SIDFC_LSS_Pos)
374#define MCAN_SIDFC_LSS(value) ((MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos)))
375/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) Extended ID Filter Configuration Register -------- */
376#define MCAN_XIDFC_FLESA_Pos 2
377#define MCAN_XIDFC_FLESA_Msk (0x3fffu << MCAN_XIDFC_FLESA_Pos)
378#define MCAN_XIDFC_FLESA(value) ((MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos)))
379#define MCAN_XIDFC_LSE_Pos 16
380#define MCAN_XIDFC_LSE_Msk (0x7fu << MCAN_XIDFC_LSE_Pos)
381#define MCAN_XIDFC_LSE(value) ((MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos)))
382/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) Extended ID AND Mask Register -------- */
383#define MCAN_XIDAM_EIDM_Pos 0
384#define MCAN_XIDAM_EIDM_Msk (0x1fffffffu << MCAN_XIDAM_EIDM_Pos)
385#define MCAN_XIDAM_EIDM(value) ((MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos)))
386/* -------- MCAN_HPMS : (MCAN Offset: 0x94) High Priority Message Status Register -------- */
387#define MCAN_HPMS_BIDX_Pos 0
388#define MCAN_HPMS_BIDX_Msk (0x3fu << MCAN_HPMS_BIDX_Pos)
389#define MCAN_HPMS_MSI_Pos 6
390#define MCAN_HPMS_MSI_Msk (0x3u << MCAN_HPMS_MSI_Pos)
391#define MCAN_HPMS_MSI_NO_FIFO_SEL (0x0u << 6)
392#define MCAN_HPMS_MSI_LOST (0x1u << 6)
393#define MCAN_HPMS_MSI_FIFO_0 (0x2u << 6)
394#define MCAN_HPMS_MSI_FIFO_1 (0x3u << 6)
395#define MCAN_HPMS_FIDX_Pos 8
396#define MCAN_HPMS_FIDX_Msk (0x7fu << MCAN_HPMS_FIDX_Pos)
397#define MCAN_HPMS_FLST (0x1u << 15)
398/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) New Data 1 Register -------- */
399#define MCAN_NDAT1_ND0 (0x1u << 0)
400#define MCAN_NDAT1_ND1 (0x1u << 1)
401#define MCAN_NDAT1_ND2 (0x1u << 2)
402#define MCAN_NDAT1_ND3 (0x1u << 3)
403#define MCAN_NDAT1_ND4 (0x1u << 4)
404#define MCAN_NDAT1_ND5 (0x1u << 5)
405#define MCAN_NDAT1_ND6 (0x1u << 6)
406#define MCAN_NDAT1_ND7 (0x1u << 7)
407#define MCAN_NDAT1_ND8 (0x1u << 8)
408#define MCAN_NDAT1_ND9 (0x1u << 9)
409#define MCAN_NDAT1_ND10 (0x1u << 10)
410#define MCAN_NDAT1_ND11 (0x1u << 11)
411#define MCAN_NDAT1_ND12 (0x1u << 12)
412#define MCAN_NDAT1_ND13 (0x1u << 13)
413#define MCAN_NDAT1_ND14 (0x1u << 14)
414#define MCAN_NDAT1_ND15 (0x1u << 15)
415#define MCAN_NDAT1_ND16 (0x1u << 16)
416#define MCAN_NDAT1_ND17 (0x1u << 17)
417#define MCAN_NDAT1_ND18 (0x1u << 18)
418#define MCAN_NDAT1_ND19 (0x1u << 19)
419#define MCAN_NDAT1_ND20 (0x1u << 20)
420#define MCAN_NDAT1_ND21 (0x1u << 21)
421#define MCAN_NDAT1_ND22 (0x1u << 22)
422#define MCAN_NDAT1_ND23 (0x1u << 23)
423#define MCAN_NDAT1_ND24 (0x1u << 24)
424#define MCAN_NDAT1_ND25 (0x1u << 25)
425#define MCAN_NDAT1_ND26 (0x1u << 26)
426#define MCAN_NDAT1_ND27 (0x1u << 27)
427#define MCAN_NDAT1_ND28 (0x1u << 28)
428#define MCAN_NDAT1_ND29 (0x1u << 29)
429#define MCAN_NDAT1_ND30 (0x1u << 30)
430#define MCAN_NDAT1_ND31 (0x1u << 31)
431/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) New Data 2 Register -------- */
432#define MCAN_NDAT2_ND32 (0x1u << 0)
433#define MCAN_NDAT2_ND33 (0x1u << 1)
434#define MCAN_NDAT2_ND34 (0x1u << 2)
435#define MCAN_NDAT2_ND35 (0x1u << 3)
436#define MCAN_NDAT2_ND36 (0x1u << 4)
437#define MCAN_NDAT2_ND37 (0x1u << 5)
438#define MCAN_NDAT2_ND38 (0x1u << 6)
439#define MCAN_NDAT2_ND39 (0x1u << 7)
440#define MCAN_NDAT2_ND40 (0x1u << 8)
441#define MCAN_NDAT2_ND41 (0x1u << 9)
442#define MCAN_NDAT2_ND42 (0x1u << 10)
443#define MCAN_NDAT2_ND43 (0x1u << 11)
444#define MCAN_NDAT2_ND44 (0x1u << 12)
445#define MCAN_NDAT2_ND45 (0x1u << 13)
446#define MCAN_NDAT2_ND46 (0x1u << 14)
447#define MCAN_NDAT2_ND47 (0x1u << 15)
448#define MCAN_NDAT2_ND48 (0x1u << 16)
449#define MCAN_NDAT2_ND49 (0x1u << 17)
450#define MCAN_NDAT2_ND50 (0x1u << 18)
451#define MCAN_NDAT2_ND51 (0x1u << 19)
452#define MCAN_NDAT2_ND52 (0x1u << 20)
453#define MCAN_NDAT2_ND53 (0x1u << 21)
454#define MCAN_NDAT2_ND54 (0x1u << 22)
455#define MCAN_NDAT2_ND55 (0x1u << 23)
456#define MCAN_NDAT2_ND56 (0x1u << 24)
457#define MCAN_NDAT2_ND57 (0x1u << 25)
458#define MCAN_NDAT2_ND58 (0x1u << 26)
459#define MCAN_NDAT2_ND59 (0x1u << 27)
460#define MCAN_NDAT2_ND60 (0x1u << 28)
461#define MCAN_NDAT2_ND61 (0x1u << 29)
462#define MCAN_NDAT2_ND62 (0x1u << 30)
463#define MCAN_NDAT2_ND63 (0x1u << 31)
464/* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register -------- */
465#define MCAN_RXF0C_F0SA_Pos 2
466#define MCAN_RXF0C_F0SA_Msk (0x3fffu << MCAN_RXF0C_F0SA_Pos)
467#define MCAN_RXF0C_F0SA(value) ((MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos)))
468#define MCAN_RXF0C_F0S_Pos 16
469#define MCAN_RXF0C_F0S_Msk (0x7fu << MCAN_RXF0C_F0S_Pos)
470#define MCAN_RXF0C_F0S(value) ((MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos)))
471#define MCAN_RXF0C_F0WM_Pos 24
472#define MCAN_RXF0C_F0WM_Msk (0x7fu << MCAN_RXF0C_F0WM_Pos)
473#define MCAN_RXF0C_F0WM(value) ((MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos)))
474#define MCAN_RXF0C_F0OM (0x1u << 31)
475/* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) Receive FIFO 0 Status Register -------- */
476#define MCAN_RXF0S_F0FL_Pos 0
477#define MCAN_RXF0S_F0FL_Msk (0x7fu << MCAN_RXF0S_F0FL_Pos)
478#define MCAN_RXF0S_F0GI_Pos 8
479#define MCAN_RXF0S_F0GI_Msk (0x3fu << MCAN_RXF0S_F0GI_Pos)
480#define MCAN_RXF0S_F0PI_Pos 16
481#define MCAN_RXF0S_F0PI_Msk (0x3fu << MCAN_RXF0S_F0PI_Pos)
482#define MCAN_RXF0S_F0F (0x1u << 24)
483#define MCAN_RXF0S_RF0L (0x1u << 25)
484/* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register -------- */
485#define MCAN_RXF0A_F0AI_Pos 0
486#define MCAN_RXF0A_F0AI_Msk (0x3fu << MCAN_RXF0A_F0AI_Pos)
487#define MCAN_RXF0A_F0AI(value) ((MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos)))
488/* -------- MCAN_RXBC : (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register -------- */
489#define MCAN_RXBC_RBSA_Pos 2
490#define MCAN_RXBC_RBSA_Msk (0x3fffu << MCAN_RXBC_RBSA_Pos)
491#define MCAN_RXBC_RBSA(value) ((MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos)))
492/* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register -------- */
493#define MCAN_RXF1C_F1SA_Pos 2
494#define MCAN_RXF1C_F1SA_Msk (0x3fffu << MCAN_RXF1C_F1SA_Pos)
495#define MCAN_RXF1C_F1SA(value) ((MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos)))
496#define MCAN_RXF1C_F1S_Pos 16
497#define MCAN_RXF1C_F1S_Msk (0x7fu << MCAN_RXF1C_F1S_Pos)
498#define MCAN_RXF1C_F1S(value) ((MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos)))
499#define MCAN_RXF1C_F1WM_Pos 24
500#define MCAN_RXF1C_F1WM_Msk (0x7fu << MCAN_RXF1C_F1WM_Pos)
501#define MCAN_RXF1C_F1WM(value) ((MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos)))
502#define MCAN_RXF1C_F1OM (0x1u << 31)
503/* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) Receive FIFO 1 Status Register -------- */
504#define MCAN_RXF1S_F1FL_Pos 0
505#define MCAN_RXF1S_F1FL_Msk (0x7fu << MCAN_RXF1S_F1FL_Pos)
506#define MCAN_RXF1S_F1GI_Pos 8
507#define MCAN_RXF1S_F1GI_Msk (0x3fu << MCAN_RXF1S_F1GI_Pos)
508#define MCAN_RXF1S_F1PI_Pos 16
509#define MCAN_RXF1S_F1PI_Msk (0x3fu << MCAN_RXF1S_F1PI_Pos)
510#define MCAN_RXF1S_F1F (0x1u << 24)
511#define MCAN_RXF1S_RF1L (0x1u << 25)
512#define MCAN_RXF1S_DMS_Pos 30
513#define MCAN_RXF1S_DMS_Msk (0x3u << MCAN_RXF1S_DMS_Pos)
514#define MCAN_RXF1S_DMS_IDLE (0x0u << 30)
515#define MCAN_RXF1S_DMS_MSG_A (0x1u << 30)
516#define MCAN_RXF1S_DMS_MSG_AB (0x2u << 30)
517#define MCAN_RXF1S_DMS_MSG_ABC (0x3u << 30)
518/* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register -------- */
519#define MCAN_RXF1A_F1AI_Pos 0
520#define MCAN_RXF1A_F1AI_Msk (0x3fu << MCAN_RXF1A_F1AI_Pos)
521#define MCAN_RXF1A_F1AI(value) ((MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos)))
522/* -------- MCAN_RXESC : (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register -------- */
523#define MCAN_RXESC_F0DS_Pos 0
524#define MCAN_RXESC_F0DS_Msk (0x7u << MCAN_RXESC_F0DS_Pos)
525#define MCAN_RXESC_F0DS(value) ((MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos)))
526#define MCAN_RXESC_F0DS_8_BYTE (0x0u << 0)
527#define MCAN_RXESC_F0DS_12_BYTE (0x1u << 0)
528#define MCAN_RXESC_F0DS_16_BYTE (0x2u << 0)
529#define MCAN_RXESC_F0DS_20_BYTE (0x3u << 0)
530#define MCAN_RXESC_F0DS_24_BYTE (0x4u << 0)
531#define MCAN_RXESC_F0DS_32_BYTE (0x5u << 0)
532#define MCAN_RXESC_F0DS_48_BYTE (0x6u << 0)
533#define MCAN_RXESC_F0DS_64_BYTE (0x7u << 0)
534#define MCAN_RXESC_F1DS_Pos 4
535#define MCAN_RXESC_F1DS_Msk (0x7u << MCAN_RXESC_F1DS_Pos)
536#define MCAN_RXESC_F1DS(value) ((MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos)))
537#define MCAN_RXESC_F1DS_8_BYTE (0x0u << 4)
538#define MCAN_RXESC_F1DS_12_BYTE (0x1u << 4)
539#define MCAN_RXESC_F1DS_16_BYTE (0x2u << 4)
540#define MCAN_RXESC_F1DS_20_BYTE (0x3u << 4)
541#define MCAN_RXESC_F1DS_24_BYTE (0x4u << 4)
542#define MCAN_RXESC_F1DS_32_BYTE (0x5u << 4)
543#define MCAN_RXESC_F1DS_48_BYTE (0x6u << 4)
544#define MCAN_RXESC_F1DS_64_BYTE (0x7u << 4)
545#define MCAN_RXESC_RBDS_Pos 8
546#define MCAN_RXESC_RBDS_Msk (0x7u << MCAN_RXESC_RBDS_Pos)
547#define MCAN_RXESC_RBDS(value) ((MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos)))
548#define MCAN_RXESC_RBDS_8_BYTE (0x0u << 8)
549#define MCAN_RXESC_RBDS_12_BYTE (0x1u << 8)
550#define MCAN_RXESC_RBDS_16_BYTE (0x2u << 8)
551#define MCAN_RXESC_RBDS_20_BYTE (0x3u << 8)
552#define MCAN_RXESC_RBDS_24_BYTE (0x4u << 8)
553#define MCAN_RXESC_RBDS_32_BYTE (0x5u << 8)
554#define MCAN_RXESC_RBDS_48_BYTE (0x6u << 8)
555#define MCAN_RXESC_RBDS_64_BYTE (0x7u << 8)
556/* -------- MCAN_TXBC : (MCAN Offset: 0xC0) Transmit Buffer Configuration Register -------- */
557#define MCAN_TXBC_TBSA_Pos 2
558#define MCAN_TXBC_TBSA_Msk (0x3fffu << MCAN_TXBC_TBSA_Pos)
559#define MCAN_TXBC_TBSA(value) ((MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos)))
560#define MCAN_TXBC_NDTB_Pos 16
561#define MCAN_TXBC_NDTB_Msk (0x3fu << MCAN_TXBC_NDTB_Pos)
562#define MCAN_TXBC_NDTB(value) ((MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos)))
563#define MCAN_TXBC_TFQS_Pos 24
564#define MCAN_TXBC_TFQS_Msk (0x3fu << MCAN_TXBC_TFQS_Pos)
565#define MCAN_TXBC_TFQS(value) ((MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos)))
566#define MCAN_TXBC_TFQM (0x1u << 30)
567/* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register -------- */
568#define MCAN_TXFQS_TFFL_Pos 0
569#define MCAN_TXFQS_TFFL_Msk (0x3fu << MCAN_TXFQS_TFFL_Pos)
570#define MCAN_TXFQS_TFGI_Pos 8
571#define MCAN_TXFQS_TFGI_Msk (0x1fu << MCAN_TXFQS_TFGI_Pos)
572#define MCAN_TXFQS_TFQPI_Pos 16
573#define MCAN_TXFQS_TFQPI_Msk (0x1fu << MCAN_TXFQS_TFQPI_Pos)
574#define MCAN_TXFQS_TFQF (0x1u << 21)
575/* -------- MCAN_TXESC : (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register -------- */
576#define MCAN_TXESC_TBDS_Pos 0
577#define MCAN_TXESC_TBDS_Msk (0x7u << MCAN_TXESC_TBDS_Pos)
578#define MCAN_TXESC_TBDS(value) ((MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos)))
579#define MCAN_TXESC_TBDS_8_BYTE (0x0u << 0)
580#define MCAN_TXESC_TBDS_12_BYTE (0x1u << 0)
581#define MCAN_TXESC_TBDS_16_BYTE (0x2u << 0)
582#define MCAN_TXESC_TBDS_20_BYTE (0x3u << 0)
583#define MCAN_TXESC_TBDS_24_BYTE (0x4u << 0)
584#define MCAN_TXESC_TBDS_32_BYTE (0x5u << 0)
585#define MCAN_TXESC_TBDS_48_BYTE (0x6u << 0)
586#define MCAN_TXESC_TBDS_64_BYTE (0x7u << 0)
587/* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register -------- */
588#define MCAN_TXBRP_TRP0 (0x1u << 0)
589#define MCAN_TXBRP_TRP1 (0x1u << 1)
590#define MCAN_TXBRP_TRP2 (0x1u << 2)
591#define MCAN_TXBRP_TRP3 (0x1u << 3)
592#define MCAN_TXBRP_TRP4 (0x1u << 4)
593#define MCAN_TXBRP_TRP5 (0x1u << 5)
594#define MCAN_TXBRP_TRP6 (0x1u << 6)
595#define MCAN_TXBRP_TRP7 (0x1u << 7)
596#define MCAN_TXBRP_TRP8 (0x1u << 8)
597#define MCAN_TXBRP_TRP9 (0x1u << 9)
598#define MCAN_TXBRP_TRP10 (0x1u << 10)
599#define MCAN_TXBRP_TRP11 (0x1u << 11)
600#define MCAN_TXBRP_TRP12 (0x1u << 12)
601#define MCAN_TXBRP_TRP13 (0x1u << 13)
602#define MCAN_TXBRP_TRP14 (0x1u << 14)
603#define MCAN_TXBRP_TRP15 (0x1u << 15)
604#define MCAN_TXBRP_TRP16 (0x1u << 16)
605#define MCAN_TXBRP_TRP17 (0x1u << 17)
606#define MCAN_TXBRP_TRP18 (0x1u << 18)
607#define MCAN_TXBRP_TRP19 (0x1u << 19)
608#define MCAN_TXBRP_TRP20 (0x1u << 20)
609#define MCAN_TXBRP_TRP21 (0x1u << 21)
610#define MCAN_TXBRP_TRP22 (0x1u << 22)
611#define MCAN_TXBRP_TRP23 (0x1u << 23)
612#define MCAN_TXBRP_TRP24 (0x1u << 24)
613#define MCAN_TXBRP_TRP25 (0x1u << 25)
614#define MCAN_TXBRP_TRP26 (0x1u << 26)
615#define MCAN_TXBRP_TRP27 (0x1u << 27)
616#define MCAN_TXBRP_TRP28 (0x1u << 28)
617#define MCAN_TXBRP_TRP29 (0x1u << 29)
618#define MCAN_TXBRP_TRP30 (0x1u << 30)
619#define MCAN_TXBRP_TRP31 (0x1u << 31)
620/* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) Transmit Buffer Add Request Register -------- */
621#define MCAN_TXBAR_AR0 (0x1u << 0)
622#define MCAN_TXBAR_AR1 (0x1u << 1)
623#define MCAN_TXBAR_AR2 (0x1u << 2)
624#define MCAN_TXBAR_AR3 (0x1u << 3)
625#define MCAN_TXBAR_AR4 (0x1u << 4)
626#define MCAN_TXBAR_AR5 (0x1u << 5)
627#define MCAN_TXBAR_AR6 (0x1u << 6)
628#define MCAN_TXBAR_AR7 (0x1u << 7)
629#define MCAN_TXBAR_AR8 (0x1u << 8)
630#define MCAN_TXBAR_AR9 (0x1u << 9)
631#define MCAN_TXBAR_AR10 (0x1u << 10)
632#define MCAN_TXBAR_AR11 (0x1u << 11)
633#define MCAN_TXBAR_AR12 (0x1u << 12)
634#define MCAN_TXBAR_AR13 (0x1u << 13)
635#define MCAN_TXBAR_AR14 (0x1u << 14)
636#define MCAN_TXBAR_AR15 (0x1u << 15)
637#define MCAN_TXBAR_AR16 (0x1u << 16)
638#define MCAN_TXBAR_AR17 (0x1u << 17)
639#define MCAN_TXBAR_AR18 (0x1u << 18)
640#define MCAN_TXBAR_AR19 (0x1u << 19)
641#define MCAN_TXBAR_AR20 (0x1u << 20)
642#define MCAN_TXBAR_AR21 (0x1u << 21)
643#define MCAN_TXBAR_AR22 (0x1u << 22)
644#define MCAN_TXBAR_AR23 (0x1u << 23)
645#define MCAN_TXBAR_AR24 (0x1u << 24)
646#define MCAN_TXBAR_AR25 (0x1u << 25)
647#define MCAN_TXBAR_AR26 (0x1u << 26)
648#define MCAN_TXBAR_AR27 (0x1u << 27)
649#define MCAN_TXBAR_AR28 (0x1u << 28)
650#define MCAN_TXBAR_AR29 (0x1u << 29)
651#define MCAN_TXBAR_AR30 (0x1u << 30)
652#define MCAN_TXBAR_AR31 (0x1u << 31)
653/* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register -------- */
654#define MCAN_TXBCR_CR0 (0x1u << 0)
655#define MCAN_TXBCR_CR1 (0x1u << 1)
656#define MCAN_TXBCR_CR2 (0x1u << 2)
657#define MCAN_TXBCR_CR3 (0x1u << 3)
658#define MCAN_TXBCR_CR4 (0x1u << 4)
659#define MCAN_TXBCR_CR5 (0x1u << 5)
660#define MCAN_TXBCR_CR6 (0x1u << 6)
661#define MCAN_TXBCR_CR7 (0x1u << 7)
662#define MCAN_TXBCR_CR8 (0x1u << 8)
663#define MCAN_TXBCR_CR9 (0x1u << 9)
664#define MCAN_TXBCR_CR10 (0x1u << 10)
665#define MCAN_TXBCR_CR11 (0x1u << 11)
666#define MCAN_TXBCR_CR12 (0x1u << 12)
667#define MCAN_TXBCR_CR13 (0x1u << 13)
668#define MCAN_TXBCR_CR14 (0x1u << 14)
669#define MCAN_TXBCR_CR15 (0x1u << 15)
670#define MCAN_TXBCR_CR16 (0x1u << 16)
671#define MCAN_TXBCR_CR17 (0x1u << 17)
672#define MCAN_TXBCR_CR18 (0x1u << 18)
673#define MCAN_TXBCR_CR19 (0x1u << 19)
674#define MCAN_TXBCR_CR20 (0x1u << 20)
675#define MCAN_TXBCR_CR21 (0x1u << 21)
676#define MCAN_TXBCR_CR22 (0x1u << 22)
677#define MCAN_TXBCR_CR23 (0x1u << 23)
678#define MCAN_TXBCR_CR24 (0x1u << 24)
679#define MCAN_TXBCR_CR25 (0x1u << 25)
680#define MCAN_TXBCR_CR26 (0x1u << 26)
681#define MCAN_TXBCR_CR27 (0x1u << 27)
682#define MCAN_TXBCR_CR28 (0x1u << 28)
683#define MCAN_TXBCR_CR29 (0x1u << 29)
684#define MCAN_TXBCR_CR30 (0x1u << 30)
685#define MCAN_TXBCR_CR31 (0x1u << 31)
686/* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register -------- */
687#define MCAN_TXBTO_TO0 (0x1u << 0)
688#define MCAN_TXBTO_TO1 (0x1u << 1)
689#define MCAN_TXBTO_TO2 (0x1u << 2)
690#define MCAN_TXBTO_TO3 (0x1u << 3)
691#define MCAN_TXBTO_TO4 (0x1u << 4)
692#define MCAN_TXBTO_TO5 (0x1u << 5)
693#define MCAN_TXBTO_TO6 (0x1u << 6)
694#define MCAN_TXBTO_TO7 (0x1u << 7)
695#define MCAN_TXBTO_TO8 (0x1u << 8)
696#define MCAN_TXBTO_TO9 (0x1u << 9)
697#define MCAN_TXBTO_TO10 (0x1u << 10)
698#define MCAN_TXBTO_TO11 (0x1u << 11)
699#define MCAN_TXBTO_TO12 (0x1u << 12)
700#define MCAN_TXBTO_TO13 (0x1u << 13)
701#define MCAN_TXBTO_TO14 (0x1u << 14)
702#define MCAN_TXBTO_TO15 (0x1u << 15)
703#define MCAN_TXBTO_TO16 (0x1u << 16)
704#define MCAN_TXBTO_TO17 (0x1u << 17)
705#define MCAN_TXBTO_TO18 (0x1u << 18)
706#define MCAN_TXBTO_TO19 (0x1u << 19)
707#define MCAN_TXBTO_TO20 (0x1u << 20)
708#define MCAN_TXBTO_TO21 (0x1u << 21)
709#define MCAN_TXBTO_TO22 (0x1u << 22)
710#define MCAN_TXBTO_TO23 (0x1u << 23)
711#define MCAN_TXBTO_TO24 (0x1u << 24)
712#define MCAN_TXBTO_TO25 (0x1u << 25)
713#define MCAN_TXBTO_TO26 (0x1u << 26)
714#define MCAN_TXBTO_TO27 (0x1u << 27)
715#define MCAN_TXBTO_TO28 (0x1u << 28)
716#define MCAN_TXBTO_TO29 (0x1u << 29)
717#define MCAN_TXBTO_TO30 (0x1u << 30)
718#define MCAN_TXBTO_TO31 (0x1u << 31)
719/* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register -------- */
720#define MCAN_TXBCF_CF0 (0x1u << 0)
721#define MCAN_TXBCF_CF1 (0x1u << 1)
722#define MCAN_TXBCF_CF2 (0x1u << 2)
723#define MCAN_TXBCF_CF3 (0x1u << 3)
724#define MCAN_TXBCF_CF4 (0x1u << 4)
725#define MCAN_TXBCF_CF5 (0x1u << 5)
726#define MCAN_TXBCF_CF6 (0x1u << 6)
727#define MCAN_TXBCF_CF7 (0x1u << 7)
728#define MCAN_TXBCF_CF8 (0x1u << 8)
729#define MCAN_TXBCF_CF9 (0x1u << 9)
730#define MCAN_TXBCF_CF10 (0x1u << 10)
731#define MCAN_TXBCF_CF11 (0x1u << 11)
732#define MCAN_TXBCF_CF12 (0x1u << 12)
733#define MCAN_TXBCF_CF13 (0x1u << 13)
734#define MCAN_TXBCF_CF14 (0x1u << 14)
735#define MCAN_TXBCF_CF15 (0x1u << 15)
736#define MCAN_TXBCF_CF16 (0x1u << 16)
737#define MCAN_TXBCF_CF17 (0x1u << 17)
738#define MCAN_TXBCF_CF18 (0x1u << 18)
739#define MCAN_TXBCF_CF19 (0x1u << 19)
740#define MCAN_TXBCF_CF20 (0x1u << 20)
741#define MCAN_TXBCF_CF21 (0x1u << 21)
742#define MCAN_TXBCF_CF22 (0x1u << 22)
743#define MCAN_TXBCF_CF23 (0x1u << 23)
744#define MCAN_TXBCF_CF24 (0x1u << 24)
745#define MCAN_TXBCF_CF25 (0x1u << 25)
746#define MCAN_TXBCF_CF26 (0x1u << 26)
747#define MCAN_TXBCF_CF27 (0x1u << 27)
748#define MCAN_TXBCF_CF28 (0x1u << 28)
749#define MCAN_TXBCF_CF29 (0x1u << 29)
750#define MCAN_TXBCF_CF30 (0x1u << 30)
751#define MCAN_TXBCF_CF31 (0x1u << 31)
752/* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register -------- */
753#define MCAN_TXBTIE_TIE0 (0x1u << 0)
754#define MCAN_TXBTIE_TIE1 (0x1u << 1)
755#define MCAN_TXBTIE_TIE2 (0x1u << 2)
756#define MCAN_TXBTIE_TIE3 (0x1u << 3)
757#define MCAN_TXBTIE_TIE4 (0x1u << 4)
758#define MCAN_TXBTIE_TIE5 (0x1u << 5)
759#define MCAN_TXBTIE_TIE6 (0x1u << 6)
760#define MCAN_TXBTIE_TIE7 (0x1u << 7)
761#define MCAN_TXBTIE_TIE8 (0x1u << 8)
762#define MCAN_TXBTIE_TIE9 (0x1u << 9)
763#define MCAN_TXBTIE_TIE10 (0x1u << 10)
764#define MCAN_TXBTIE_TIE11 (0x1u << 11)
765#define MCAN_TXBTIE_TIE12 (0x1u << 12)
766#define MCAN_TXBTIE_TIE13 (0x1u << 13)
767#define MCAN_TXBTIE_TIE14 (0x1u << 14)
768#define MCAN_TXBTIE_TIE15 (0x1u << 15)
769#define MCAN_TXBTIE_TIE16 (0x1u << 16)
770#define MCAN_TXBTIE_TIE17 (0x1u << 17)
771#define MCAN_TXBTIE_TIE18 (0x1u << 18)
772#define MCAN_TXBTIE_TIE19 (0x1u << 19)
773#define MCAN_TXBTIE_TIE20 (0x1u << 20)
774#define MCAN_TXBTIE_TIE21 (0x1u << 21)
775#define MCAN_TXBTIE_TIE22 (0x1u << 22)
776#define MCAN_TXBTIE_TIE23 (0x1u << 23)
777#define MCAN_TXBTIE_TIE24 (0x1u << 24)
778#define MCAN_TXBTIE_TIE25 (0x1u << 25)
779#define MCAN_TXBTIE_TIE26 (0x1u << 26)
780#define MCAN_TXBTIE_TIE27 (0x1u << 27)
781#define MCAN_TXBTIE_TIE28 (0x1u << 28)
782#define MCAN_TXBTIE_TIE29 (0x1u << 29)
783#define MCAN_TXBTIE_TIE30 (0x1u << 30)
784#define MCAN_TXBTIE_TIE31 (0x1u << 31)
785/* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */
786#define MCAN_TXBCIE_CFIE0 (0x1u << 0)
787#define MCAN_TXBCIE_CFIE1 (0x1u << 1)
788#define MCAN_TXBCIE_CFIE2 (0x1u << 2)
789#define MCAN_TXBCIE_CFIE3 (0x1u << 3)
790#define MCAN_TXBCIE_CFIE4 (0x1u << 4)
791#define MCAN_TXBCIE_CFIE5 (0x1u << 5)
792#define MCAN_TXBCIE_CFIE6 (0x1u << 6)
793#define MCAN_TXBCIE_CFIE7 (0x1u << 7)
794#define MCAN_TXBCIE_CFIE8 (0x1u << 8)
795#define MCAN_TXBCIE_CFIE9 (0x1u << 9)
796#define MCAN_TXBCIE_CFIE10 (0x1u << 10)
797#define MCAN_TXBCIE_CFIE11 (0x1u << 11)
798#define MCAN_TXBCIE_CFIE12 (0x1u << 12)
799#define MCAN_TXBCIE_CFIE13 (0x1u << 13)
800#define MCAN_TXBCIE_CFIE14 (0x1u << 14)
801#define MCAN_TXBCIE_CFIE15 (0x1u << 15)
802#define MCAN_TXBCIE_CFIE16 (0x1u << 16)
803#define MCAN_TXBCIE_CFIE17 (0x1u << 17)
804#define MCAN_TXBCIE_CFIE18 (0x1u << 18)
805#define MCAN_TXBCIE_CFIE19 (0x1u << 19)
806#define MCAN_TXBCIE_CFIE20 (0x1u << 20)
807#define MCAN_TXBCIE_CFIE21 (0x1u << 21)
808#define MCAN_TXBCIE_CFIE22 (0x1u << 22)
809#define MCAN_TXBCIE_CFIE23 (0x1u << 23)
810#define MCAN_TXBCIE_CFIE24 (0x1u << 24)
811#define MCAN_TXBCIE_CFIE25 (0x1u << 25)
812#define MCAN_TXBCIE_CFIE26 (0x1u << 26)
813#define MCAN_TXBCIE_CFIE27 (0x1u << 27)
814#define MCAN_TXBCIE_CFIE28 (0x1u << 28)
815#define MCAN_TXBCIE_CFIE29 (0x1u << 29)
816#define MCAN_TXBCIE_CFIE30 (0x1u << 30)
817#define MCAN_TXBCIE_CFIE31 (0x1u << 31)
818/* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register -------- */
819#define MCAN_TXEFC_EFSA_Pos 2
820#define MCAN_TXEFC_EFSA_Msk (0x3fffu << MCAN_TXEFC_EFSA_Pos)
821#define MCAN_TXEFC_EFSA(value) ((MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos)))
822#define MCAN_TXEFC_EFS_Pos 16
823#define MCAN_TXEFC_EFS_Msk (0x3fu << MCAN_TXEFC_EFS_Pos)
824#define MCAN_TXEFC_EFS(value) ((MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos)))
825#define MCAN_TXEFC_EFWM_Pos 24
826#define MCAN_TXEFC_EFWM_Msk (0x3fu << MCAN_TXEFC_EFWM_Pos)
827#define MCAN_TXEFC_EFWM(value) ((MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos)))
828/* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) Transmit Event FIFO Status Register -------- */
829#define MCAN_TXEFS_EFFL_Pos 0
830#define MCAN_TXEFS_EFFL_Msk (0x3fu << MCAN_TXEFS_EFFL_Pos)
831#define MCAN_TXEFS_EFGI_Pos 8
832#define MCAN_TXEFS_EFGI_Msk (0x1fu << MCAN_TXEFS_EFGI_Pos)
833#define MCAN_TXEFS_EFPI_Pos 16
834#define MCAN_TXEFS_EFPI_Msk (0x1fu << MCAN_TXEFS_EFPI_Pos)
835#define MCAN_TXEFS_EFF (0x1u << 24)
836#define MCAN_TXEFS_TEFL (0x1u << 25)
837/* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register -------- */
838#define MCAN_TXEFA_EFAI_Pos 0
839#define MCAN_TXEFA_EFAI_Msk (0x1fu << MCAN_TXEFA_EFAI_Pos)
840#define MCAN_TXEFA_EFAI(value) ((MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos)))
841
845#endif /* _SAME70_MCAN_COMPONENT_ */
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Mcan
Mcan hardware registers.
Definition: component_mcan.h:41
Mcan::MCAN_TOCV
__IO uint32_t MCAN_TOCV
(Mcan Offset: 0x2C) Timeout Counter Value Register
Definition: component_mcan.h:52
Mcan::MCAN_TXBCR
__IO uint32_t MCAN_TXBCR
(Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register
Definition: component_mcan.h:83
Mcan::MCAN_TXBTIE
__IO uint32_t MCAN_TXBTIE
(Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register
Definition: component_mcan.h:86
Mcan::MCAN_IE
__IO uint32_t MCAN_IE
(Mcan Offset: 0x54) Interrupt Enable Register
Definition: component_mcan.h:58
Mcan::MCAN_TXBRP
__I uint32_t MCAN_TXBRP
(Mcan Offset: 0xCC) Transmit Buffer Request Pending Register
Definition: component_mcan.h:81
Mcan::MCAN_TXEFC
__IO uint32_t MCAN_TXEFC
(Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register
Definition: component_mcan.h:89
Mcan::MCAN_TXBTO
__I uint32_t MCAN_TXBTO
(Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register
Definition: component_mcan.h:84
Mcan::MCAN_ILS
__IO uint32_t MCAN_ILS
(Mcan Offset: 0x58) Interrupt Line Select Register
Definition: component_mcan.h:59
Mcan::MCAN_RXF1A
__IO uint32_t MCAN_RXF1A
(Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register
Definition: component_mcan.h:76
Mcan::MCAN_TXFQS
__I uint32_t MCAN_TXFQS
(Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register
Definition: component_mcan.h:79
Mcan::MCAN_RXF0A
__IO uint32_t MCAN_RXF0A
(Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register
Definition: component_mcan.h:72
Mcan::MCAN_SIDFC
__IO uint32_t MCAN_SIDFC
(Mcan Offset: 0x84) Standard ID Filter Configuration Register
Definition: component_mcan.h:63
Mcan::MCAN_RXF0C
__IO uint32_t MCAN_RXF0C
(Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register
Definition: component_mcan.h:70
Mcan::MCAN_ECR
__I uint32_t MCAN_ECR
(Mcan Offset: 0x40) Error Counter Register
Definition: component_mcan.h:54
Mcan::MCAN_TXEFS
__I uint32_t MCAN_TXEFS
(Mcan Offset: 0xF4) Transmit Event FIFO Status Register
Definition: component_mcan.h:90
Mcan::MCAN_RXF1S
__I uint32_t MCAN_RXF1S
(Mcan Offset: 0xB4) Receive FIFO 1 Status Register
Definition: component_mcan.h:75
Mcan::MCAN_TOCC
__IO uint32_t MCAN_TOCC
(Mcan Offset: 0x28) Timeout Counter Configuration Register
Definition: component_mcan.h:51
Mcan::MCAN_ILE
__IO uint32_t MCAN_ILE
(Mcan Offset: 0x5C) Interrupt Line Enable Register
Definition: component_mcan.h:60
Mcan::MCAN_XIDAM
__IO uint32_t MCAN_XIDAM
(Mcan Offset: 0x90) Extended ID AND Mask Register
Definition: component_mcan.h:66
Mcan::MCAN_TXBCIE
__IO uint32_t MCAN_TXBCIE
(Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register
Definition: component_mcan.h:87
Mcan::MCAN_RWD
__IO uint32_t MCAN_RWD
(Mcan Offset: 0x14) RAM Watchdog Register
Definition: component_mcan.h:46
Mcan::MCAN_FBTP
__IO uint32_t MCAN_FBTP
(Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register
Definition: component_mcan.h:44
Mcan::MCAN_CUST
__IO uint32_t MCAN_CUST
(Mcan Offset: 0x08) Customer Register
Definition: component_mcan.h:43
Mcan::MCAN_RXBC
__IO uint32_t MCAN_RXBC
(Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register
Definition: component_mcan.h:73
Mcan::MCAN_RXESC
__IO uint32_t MCAN_RXESC
(Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register
Definition: component_mcan.h:77
Mcan::MCAN_TXBC
__IO uint32_t MCAN_TXBC
(Mcan Offset: 0xC0) Transmit Buffer Configuration Register
Definition: component_mcan.h:78
Mcan::MCAN_IR
__IO uint32_t MCAN_IR
(Mcan Offset: 0x50) Interrupt Register
Definition: component_mcan.h:57
Mcan::MCAN_TXBCF
__I uint32_t MCAN_TXBCF
(Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register
Definition: component_mcan.h:85
Mcan::MCAN_TSCV
__IO uint32_t MCAN_TSCV
(Mcan Offset: 0x24) Timestamp Counter Value Register
Definition: component_mcan.h:50
Mcan::MCAN_BTP
__IO uint32_t MCAN_BTP
(Mcan Offset: 0x1C) Bit Timing and Prescaler Register
Definition: component_mcan.h:48
Mcan::MCAN_GFC
__IO uint32_t MCAN_GFC
(Mcan Offset: 0x80) Global Filter Configuration Register
Definition: component_mcan.h:62
Mcan::MCAN_RXF0S
__I uint32_t MCAN_RXF0S
(Mcan Offset: 0xA4) Receive FIFO 0 Status Register
Definition: component_mcan.h:71
Mcan::MCAN_PSR
__I uint32_t MCAN_PSR
(Mcan Offset: 0x44) Protocol Status Register
Definition: component_mcan.h:55
Mcan::MCAN_TXESC
__IO uint32_t MCAN_TXESC
(Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register
Definition: component_mcan.h:80
Mcan::MCAN_TEST
__IO uint32_t MCAN_TEST
(Mcan Offset: 0x10) Test Register
Definition: component_mcan.h:45
Mcan::MCAN_TXBAR
__IO uint32_t MCAN_TXBAR
(Mcan Offset: 0xD0) Transmit Buffer Add Request Register
Definition: component_mcan.h:82
Mcan::MCAN_XIDFC
__IO uint32_t MCAN_XIDFC
(Mcan Offset: 0x88) Extended ID Filter Configuration Register
Definition: component_mcan.h:64
Mcan::MCAN_RXF1C
__IO uint32_t MCAN_RXF1C
(Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register
Definition: component_mcan.h:74
Mcan::MCAN_CCCR
__IO uint32_t MCAN_CCCR
(Mcan Offset: 0x18) CC Control Register
Definition: component_mcan.h:47
Mcan::MCAN_TXEFA
__IO uint32_t MCAN_TXEFA
(Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register
Definition: component_mcan.h:91
Mcan::MCAN_NDAT1
__IO uint32_t MCAN_NDAT1
(Mcan Offset: 0x98) New Data 1 Register
Definition: component_mcan.h:68
Mcan::MCAN_HPMS
__I uint32_t MCAN_HPMS
(Mcan Offset: 0x94) High Priority Message Status Register
Definition: component_mcan.h:67
Mcan::MCAN_NDAT2
__IO uint32_t MCAN_NDAT2
(Mcan Offset: 0x9C) New Data 2 Register
Definition: component_mcan.h:69
Mcan::MCAN_TSCC
__IO uint32_t MCAN_TSCC
(Mcan Offset: 0x20) Timestamp Counter Configuration Register
Definition: component_mcan.h:49