RTEMS: bsps/powerpc/mpc55xxevb/include/mpc55xx/fsl-mpc555x.h Source File

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fsl-mpc555x.h
1/*
2 * Modifications of the original file provided by Freescale are:
3 *
4 * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
5 *
6 * embedded brains GmbH
7 * Obere Lagerstr. 30
8 * 82178 Puchheim
9 * Germany
10 * <info@embedded-brains.de>
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34/**************************************************************************/
35/* FILE NAME: mpc5554.h COPYRIGHT (c) Freescale 2007 */
36/* VERSION: 1.7 All Rights Reserved */
37/* */
38/* DESCRIPTION: */
39/* This file contain all of the register and bit field definitions for */
40/* MPC5554. */
41/*========================================================================*/
42/* UPDATE HISTORY */
43/* REV AUTHOR DATE DESCRIPTION OF CHANGE */
44/* --- ----------- --------- --------------------- */
45/* 0.01 J. Loeliger 03/Mar/03 Initial version of file for MPC5554. */
46/* Based on SoC version 0.7. */
47/* 0.02 J. Loeliger 05/Mar/03 All registers and bit fields now */
48/* defined. */
49/* 0.03 J. Loeliger 05/May/03 Updated to current spec., fixed several*/
50/* bugs and naming/formating issues. */
51/* 0.04 J. Loeliger 16/May/03 More fixes and naming/formating issues.*/
52/* 0.05 J. Loeliger 19/Aug/03 Updated for latest documentation. */
53/* 0.06 J. Loeliger 03/Sep/03 Changed to include motint.h */
54/* Updated many register names. */
55/* 0.07 J. Loeliger 04/Nov/03 Changed to include typedefs.h and more */
56/* register name updates. */
57/* 0.08 J. Loeliger 25/Feb/04 Added MetroWerks #pragmas. */
58/* Updated for user manual 1.0 */
59/* 0.09 J. Loeliger 27/Feb/04 Updated eDMA tcd section and some more */
60/* bit field names to match user's man. */
61/* 0.10 J. Loeliger 01/Apr/04 Fixed register spacing in ADC and eTPU */
62/* 0.11 J. Loeliger 16/Jun/04 Many fixes and updated to user's */
63/* manual, also some testing done. */
64/* 0.12 J. Loeliger 25/Jun/04 Fixed problems in edma and eTPU. */
65/* 0.13 J. Loeliger 16/Jul/04 Fixed mistake in FlexCAN TIMER size and*/
66/* changed eTPU memory defs to start with*/
67/* ETPU_ */
68/* 0.14 J. Loeliger 17/Nov/04 Added ETPU_CODE_RAM definition. */
69/* All code moved to CVS repository. */
70/* Updated copyright to Freescale. */
71/* Added new SCMOFFDATAR register to eTPU*/
72/* Fixed REDCR_A&B bit fields in eTPU. */
73/* Added new DBR bit in CTAR for DSPI. */
74/* 0.15 J. Loeliger 29/Nov/04 Added support for new eTPU util funcs. */
75/* Added bit fields for FlexCAN buffer ID*/
76/* 0.16 J. Loeliger 01/Dec/04 Corrected comments in release 0.16. */
77/* 0.17 J. Loeliger 02/Dec/04 Moved eTPU variable definitions to a */
78/* seperate new file. */
79/* Removed SIU variable the GPIO */
80/* routines do not need it. */
81/* 1.0 G.Emerson 22/Feb/05 No real changes to this file. */
82/* Joint generation with mpc5553.h */
83/* 1.1 G. Emerson 6/Jun/05 Changes to SIU to allow for upward */
84/* expansion of PCR/GPDI/GPDO */
85/* Added #defines for memory sizes etc */
86/* 1.2 G. Emerson 21/Sep/05 PBRIDGES fixes */
87/* 1.3 G. Emerson 03/Jan/06 Pbridge MPCR/PACR/OPACR now generic */
88/* XBAR MPR now generic */
89/* ECSM has FSBMCR on all integrations */
90/* 1.4 G. Emerson 24/Jan/06 Make Pbridges, XBAR, Flash BIU */
91/* integration specific */
92/* 1.5 S. Mathieson 28/Jul/06 Split out unused bit to support build */
93/* process. No real change. */
94/* 1.6 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */
95/* to DPB to align with documentation. */
96/* 1.7 S. Mathieson 26/Feb/07 eDMA TCD format updated to include */
97/* alternate configuration. INTC, */
98/* correction to the number of PSR */
99/* registers. */
100/**************************************************************************/
101/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
102
103#ifndef _MPC5554_H_
104#define _MPC5554_H_
105
106#ifndef ASM
107
108#include <stdint.h>
109
110#include <mpc55xx/regs-edma.h>
111
112#ifdef __cplusplus
113extern "C" {
114#endif
115
116#ifdef __MWERKS__
117#pragma push
118#pragma ANSI_strict off
119#endif
120
121/****************************************************************************/
122/* MODULE : PBRIDGE_A Peripheral Bridge */
123/****************************************************************************/
124 struct PBRIDGE_A_tag {
125 union {
126 uint32_t R;
127 struct {
128 uint32_t MBW0:1;
129 uint32_t MTR0:1;
130 uint32_t MTW0:1;
131 uint32_t MPL0:1;
132 uint32_t MBW1:1;
133 uint32_t MTR1:1;
134 uint32_t MTW1:1;
135 uint32_t MPL1:1;
136 uint32_t MBW2:1;
137 uint32_t MTR2:1;
138 uint32_t MTW2:1;
139 uint32_t MPL2:1;
140 uint32_t MBW3:1;
141 uint32_t MTR3:1;
142 uint32_t MTW3:1;
143 uint32_t MPL3:1;
144
145 uint32_t:4;
146
147 uint32_t:4;
148
149 uint32_t:4;
150
151 uint32_t:4;
152 } B;
153 } MPCR; /* Master Privilege Control Register */
154
155 uint32_t pbridge_a_reserved2[7];
156
157 union {
158 uint32_t R;
159 struct {
160 uint32_t BW0:1;
161 uint32_t SP0:1;
162 uint32_t WP0:1;
163 uint32_t TP0:1;
164 uint32_t:28;
165 } B;
166 } PACR0;
167
168 uint32_t pbridge_a_reserved3[7];
169
170 union {
171 uint32_t R;
172 struct {
173 uint32_t BW0:1;
174 uint32_t SP0:1;
175 uint32_t WP0:1;
176 uint32_t TP0:1;
177 uint32_t BW1:1;
178 uint32_t SP1:1;
179 uint32_t WP1:1;
180 uint32_t TP1:1;
181 uint32_t BW2:1;
182 uint32_t SP2:1;
183 uint32_t WP2:1;
184 uint32_t TP2:1;
185 uint32_t:4;
186 uint32_t BW4:1;
187 uint32_t SP4:1;
188 uint32_t WP4:1;
189 uint32_t TP4:1;
190 uint32_t:12;
191 } B;
192 } OPACR0;
193
194 union {
195 uint32_t R;
196 struct {
197
198 uint32_t BW0:1; /* EMIOS */
199 uint32_t SP0:1;
200 uint32_t WP0:1;
201 uint32_t TP0:1;
202
203 uint32_t:28;
204 } B;
205 } OPACR1;
206
207 union {
208 uint32_t R;
209 struct {
210 uint32_t BW0:1;
211 uint32_t SP0:1;
212 uint32_t WP0:1;
213 uint32_t TP0:1;
214 uint32_t:4;
215 uint32_t BW2:1;
216 uint32_t SP2:1;
217 uint32_t WP2:1;
218 uint32_t TP2:1;
219 uint32_t BW3:1;
220 uint32_t SP3:1;
221 uint32_t WP3:1;
222 uint32_t TP3:1;
223 uint32_t BW4:1;
224 uint32_t SP4:1;
225 uint32_t WP4:1;
226 uint32_t TP4:1;
227 uint32_t:12;
228 } B;
229 } OPACR2;
230
231 };
232
233/****************************************************************************/
234/* MODULE : PBRIDGE_B Peripheral Bridge */
235/****************************************************************************/
236 struct PBRIDGE_B_tag {
237 union {
238 uint32_t R;
239 struct {
240 uint32_t MBW0:1;
241 uint32_t MTR0:1;
242 uint32_t MTW0:1;
243 uint32_t MPL0:1;
244 uint32_t MBW1:1;
245 uint32_t MTR1:1;
246 uint32_t MTW1:1;
247 uint32_t MPL1:1;
248 uint32_t MBW2:1;
249 uint32_t MTR2:1;
250 uint32_t MTW2:1;
251 uint32_t MPL2:1;
252 uint32_t MBW3:1;
253 uint32_t MTR3:1;
254 uint32_t MTW3:1;
255 uint32_t MPL3:1;
256
257 uint32_t:4;
258
259 uint32_t:4;
260
261 uint32_t:4;
262
263 uint32_t:4;
264 } B;
265 } MPCR; /* Master Privilege Control Register */
266
267 uint32_t pbridge_b_reserved2[7];
268
269 union {
270 uint32_t R;
271 struct {
272 uint32_t BW0:1;
273 uint32_t SP0:1;
274 uint32_t WP0:1;
275 uint32_t TP0:1;
276 uint32_t BW1:1;
277 uint32_t SP1:1;
278 uint32_t WP1:1;
279 uint32_t TP1:1;
280 uint32_t:24;
281 } B;
282 } PACR0;
283
284 uint32_t pbridge_b_reserved3;
285
286 union {
287 uint32_t R;
288 struct {
289 uint32_t BW0:1;
290 uint32_t SP0:1;
291 uint32_t WP0:1;
292 uint32_t TP0:1;
293 uint32_t BW1:1;
294 uint32_t SP1:1;
295 uint32_t WP1:1;
296 uint32_t TP1:1;
297 uint32_t BW2:1;
298 uint32_t SP2:1;
299 uint32_t WP2:1;
300 uint32_t TP2:1;
301
302 uint32_t:4;
303
304 uint32_t:16;
305
306 } B;
307 } PACR2;
308
309 uint32_t pbridge_b_reserved4[5];
310
311 union {
312 uint32_t R;
313 struct {
314 uint32_t BW0:1;
315 uint32_t SP0:1;
316 uint32_t WP0:1;
317 uint32_t TP0:1;
318 uint32_t:12;
319
320 uint32_t BW4:1; /* DSPI_A */
321 uint32_t SP4:1;
322 uint32_t WP4:1;
323 uint32_t TP4:1;
324
325 uint32_t BW5:1; /* DSPI_B */
326 uint32_t SP5:1;
327 uint32_t WP5:1;
328 uint32_t TP5:1;
329
330 uint32_t BW6:1;
331 uint32_t SP6:1;
332 uint32_t WP6:1;
333 uint32_t TP6:1;
334 uint32_t BW7:1;
335 uint32_t SP7:1;
336 uint32_t WP7:1;
337 uint32_t TP7:1;
338 } B;
339 } OPACR0;
340
341 union {
342 uint32_t R;
343 struct {
344 uint32_t:16;
345 uint32_t BW4:1;
346 uint32_t SP4:1;
347 uint32_t WP4:1;
348 uint32_t TP4:1;
349
350 uint32_t BW5:1; /* ESCI_B */
351 uint32_t SP5:1;
352 uint32_t WP5:1;
353 uint32_t TP5:1;
354
355 uint32_t:8;
356 } B;
357 } OPACR1;
358
359 union {
360 uint32_t R;
361 struct {
362 uint32_t BW0:1;
363 uint32_t SP0:1;
364 uint32_t WP0:1;
365 uint32_t TP0:1;
366
367 uint32_t BW1:1; /* CAN_B */
368 uint32_t SP1:1;
369 uint32_t WP1:1;
370 uint32_t TP1:1;
371
372 uint32_t BW2:1;
373 uint32_t SP2:1;
374 uint32_t WP2:1;
375 uint32_t TP2:1;
376
377 uint32_t:4;
378
379 uint32_t:4;
380
381 uint32_t:12;
382 } B;
383 } OPACR2;
384
385 union {
386 uint32_t R;
387 struct {
388
389 uint32_t:4;
390
391 uint32_t:24;
392 uint32_t BW7:1;
393 uint32_t SP7:1;
394 uint32_t WP7:1;
395 uint32_t TP7:1;
396 } B;
397 } OPACR3;
398
399 };
400/****************************************************************************/
401/* MODULE : FMPLL */
402/****************************************************************************/
403 struct FMPLL_tag {
404 union FMPLL_SYNCR_tag {
405 uint32_t R;
406 struct {
407 uint32_t:1;
408 uint32_t PREDIV:3;
409 uint32_t MFD:5;
410 uint32_t:1;
411 uint32_t RFD:3;
412 uint32_t LOCEN:1;
413 uint32_t LOLRE:1;
414 uint32_t LOCRE:1;
415 uint32_t DISCLK:1;
416 uint32_t LOLIRQ:1;
417 uint32_t LOCIRQ:1;
418 uint32_t RATE:1;
419 uint32_t DEPTH:2;
420 uint32_t EXP:10;
421 } B;
422 } SYNCR;
423
424 union FMPLL_SYNSR_tag {
425 uint32_t R;
426 struct {
427 uint32_t:22;
428 uint32_t LOLF:1;
429 uint32_t LOC:1;
430 uint32_t MODE:1;
431 uint32_t PLLSEL:1;
432 uint32_t PLLREF:1;
433 uint32_t LOCKS:1;
434 uint32_t LOCK:1;
435 uint32_t LOCF:1;
436 uint32_t CALDONE:1;
437 uint32_t CALPASS:1;
438 } B;
439 } SYNSR;
440
441 };
442/****************************************************************************/
443/* MODULE : External Bus Interface (EBI) */
444/****************************************************************************/
445 struct EBI_CS_tag {
446 union { /* Base Register Bank */
447 uint32_t R;
448 struct {
449 uint32_t BA:17;
450 uint32_t:3;
451 uint32_t PS:1;
452 uint32_t:4;
453 uint32_t BL:1;
454 uint32_t WEBS:1;
455 uint32_t TBDIP:1;
456 uint32_t:2;
457 uint32_t BI:1;
458 uint32_t V:1;
459 } B;
460 } BR;
461
462 union { /* Option Register Bank */
463 uint32_t R;
464 struct {
465 uint32_t AM:17;
466 uint32_t:7;
467 uint32_t SCY:4;
468 uint32_t:1;
469 uint32_t BSCY:2;
470 uint32_t:1;
471 } B;
472 } OR;
473 };
474
475 struct EBI_CAL_CS_tag {
476 uint32_t ebi_cal_cs_reserved [2];
477 };
478
479 struct EBI_tag {
480 union EBI_MCR_tag { /* Module Configuration Register */
481 uint32_t R;
482 struct {
483 uint32_t:5;
484 uint32_t SIZEEN:1;
485 uint32_t SIZE:2;
486 uint32_t:8;
487 uint32_t ACGE:1;
488 uint32_t EXTM:1;
489 uint32_t EARB:1;
490 uint32_t EARP:2;
491 uint32_t:4;
492 uint32_t MDIS:1;
493 uint32_t:5;
494 uint32_t DBM:1;
495 } B;
496 } MCR;
497
498 uint32_t EBI_reserved1;
499
500 union { /* Transfer Error Status Register */
501 uint32_t R;
502 struct {
503 uint32_t:30;
504 uint32_t TEAF:1;
505 uint32_t BMTF:1;
506 } B;
507 } TESR;
508
509 union { /* Bus Monitor Control Register */
510 uint32_t R;
511 struct {
512 uint32_t:16;
513 uint32_t BMT:8;
514 uint32_t BME:1;
515 uint32_t:7;
516 } B;
517 } BMCR;
518
519 struct EBI_CS_tag CS[4];
520
521 uint32_t EBI_reserved2[4];
522
523 struct EBI_CAL_CS_tag CAL_CS[4];
524 };
525/****************************************************************************/
526/* MODULE : FLASH */
527/****************************************************************************/
528 struct FLASH_tag {
529 union { /* Module Configuration Register */
530 uint32_t R;
531 struct {
532 uint32_t:4;
533 uint32_t SIZE:4;
534 uint32_t:1;
535 uint32_t LAS:3;
536 uint32_t:3;
537 uint32_t MAS:1;
538 uint32_t EER:1;
539 uint32_t RWE:1;
540 uint32_t BBEPE:1;
541 uint32_t EPE:1;
542 uint32_t PEAS:1;
543 uint32_t DONE:1;
544 uint32_t PEG:1;
545
546 uint32_t:2;
547
548 uint32_t STOP:1;
549 uint32_t:1;
550 uint32_t PGM:1;
551 uint32_t PSUS:1;
552 uint32_t ERS:1;
553 uint32_t ESUS:1;
554 uint32_t EHV:1;
555 } B;
556 } MCR;
557
558 union LMLR_tag { /* LML Register */
559 uint32_t R;
560 struct {
561 uint32_t LME:1;
562 uint32_t:10;
563 uint32_t SLOCK:1;
564 uint32_t MLOCK:4;
565 uint32_t LLOCK:16;
566 } B;
567 } LMLR;
568
569 union HLR_tag { /* HL Register */
570 uint32_t R;
571 struct {
572 uint32_t HBE:1;
573 uint32_t:3;
574 uint32_t HBLOCK:28;
575 } B;
576 } HLR;
577
578 union SLMLR_tag { /* SLML Register */
579 uint32_t R;
580 struct {
581 uint32_t SLE:1;
582 uint32_t:10;
583 uint32_t SSLOCK:1;
584 uint32_t SMLOCK:4;
585 uint32_t SLLOCK:16;
586 } B;
587 } SLMLR;
588
589 union { /* LMS Register */
590 uint32_t R;
591 struct {
592 uint32_t:12;
593 uint32_t MSEL:4;
594 uint32_t LSEL:16;
595 } B;
596 } LMSR;
597
598 union {
599 uint32_t R;
600 struct {
601 uint32_t:4;
602 uint32_t HBSEL:28;
603 } B;
604 } HSR;
605
606 union {
607 uint32_t R;
608 struct {
609 uint32_t:10;
610 uint32_t ADDR:19;
611 uint32_t:3;
612 } B;
613 } AR;
614
615 union {
616 uint32_t R;
617 struct {
618
619 uint32_t:11;
620
621 uint32_t:1;
622
623 uint32_t M3PFE:1;
624 uint32_t M2PFE:1;
625 uint32_t M1PFE:1;
626 uint32_t M0PFE:1;
627 uint32_t APC:3;
628 uint32_t WWSC:2;
629 uint32_t RWSC:3;
630
631 uint32_t DPFEN:2;
632 uint32_t IPFEN:2;
633
634 uint32_t PFLIM:3;
635 uint32_t BFEN:1;
636 } B;
637 } BIUCR;
638
639 union {
640 uint32_t R;
641 struct {
642
643 uint32_t:22;
644
645 uint32_t:2;
646
647 uint32_t M3AP:2;
648 uint32_t M2AP:2;
649 uint32_t M1AP:2;
650 uint32_t M0AP:2;
651 } B;
652 } BIUAPR;
653 };
654/****************************************************************************/
655/* MODULE : SIU */
656/****************************************************************************/
657 struct SIU_tag {
658 int32_t SIU_reserved0;
659
660 union { /* MCU ID Register */
661 uint32_t R;
662 struct {
663 uint32_t PARTNUM:16;
664 uint32_t MASKNUM:16;
665 } B;
666 } MIDR;
667 int32_t SIU_reserved00;
668
669 union { /* Reset Status Register */
670 uint32_t R;
671 struct {
672 uint32_t PORS:1;
673 uint32_t ERS:1;
674 uint32_t LLRS:1;
675 uint32_t LCRS:1;
676 uint32_t WDRS:1;
677 uint32_t CRS:1;
678 uint32_t:8;
679 uint32_t SSRS:1;
680 uint32_t SERF:1;
681 uint32_t WKPCFG:1;
682 uint32_t:12;
683 uint32_t BOOTCFG:2;
684 uint32_t RGF:1;
685 } B;
686 } RSR;
687
688 union { /* System Reset Control Register */
689 uint32_t R;
690 struct {
691 uint32_t SSR:1;
692 uint32_t SER:1;
693 uint32_t:14;
694 uint32_t CRE:1;
695 uint32_t:15;
696 } B;
697 } SRCR;
698
699 union SIU_EISR_tag { /* External Interrupt Status Register */
700 uint32_t R;
701 struct {
702 uint32_t:16;
703 uint32_t EIF15:1;
704 uint32_t EIF14:1;
705 uint32_t EIF13:1;
706 uint32_t EIF12:1;
707 uint32_t EIF11:1;
708 uint32_t EIF10:1;
709 uint32_t EIF9:1;
710 uint32_t EIF8:1;
711 uint32_t EIF7:1;
712 uint32_t EIF6:1;
713 uint32_t EIF5:1;
714 uint32_t EIF4:1;
715 uint32_t EIF3:1;
716 uint32_t EIF2:1;
717 uint32_t EIF1:1;
718 uint32_t EIF0:1;
719 } B;
720 } EISR;
721
722 union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */
723 uint32_t R;
724 struct {
725 uint32_t:16;
726 uint32_t EIRE15:1;
727 uint32_t EIRE14:1;
728 uint32_t EIRE13:1;
729 uint32_t EIRE12:1;
730 uint32_t EIRE11:1;
731 uint32_t EIRE10:1;
732 uint32_t EIRE9:1;
733 uint32_t EIRE8:1;
734 uint32_t EIRE7:1;
735 uint32_t EIRE6:1;
736 uint32_t EIRE5:1;
737 uint32_t EIRE4:1;
738 uint32_t EIRE3:1;
739 uint32_t EIRE2:1;
740 uint32_t EIRE1:1;
741 uint32_t EIRE0:1;
742 } B;
743 } DIRER;
744
745 union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */
746 uint32_t R;
747 struct {
748 uint32_t:28;
749 uint32_t DIRS3:1;
750 uint32_t DIRS2:1;
751 uint32_t DIRS1:1;
752 uint32_t DIRS0:1;
753 } B;
754 } DIRSR;
755
756 union { /* Overrun Status Register */
757 uint32_t R;
758 struct {
759 uint32_t:16;
760 uint32_t OVF15:1;
761 uint32_t OVF14:1;
762 uint32_t OVF13:1;
763 uint32_t OVF12:1;
764 uint32_t OVF11:1;
765 uint32_t OVF10:1;
766 uint32_t OVF9:1;
767 uint32_t OVF8:1;
768 uint32_t OVF7:1;
769 uint32_t OVF6:1;
770 uint32_t OVF5:1;
771 uint32_t OVF4:1;
772 uint32_t OVF3:1;
773 uint32_t OVF2:1;
774 uint32_t OVF1:1;
775 uint32_t OVF0:1;
776 } B;
777 } OSR;
778
779 union SIU_ORER_tag { /* Overrun Request Enable Register */
780 uint32_t R;
781 struct {
782 uint32_t:16;
783 uint32_t ORE15:1;
784 uint32_t ORE14:1;
785 uint32_t ORE13:1;
786 uint32_t ORE12:1;
787 uint32_t ORE11:1;
788 uint32_t ORE10:1;
789 uint32_t ORE9:1;
790 uint32_t ORE8:1;
791 uint32_t ORE7:1;
792 uint32_t ORE6:1;
793 uint32_t ORE5:1;
794 uint32_t ORE4:1;
795 uint32_t ORE3:1;
796 uint32_t ORE2:1;
797 uint32_t ORE1:1;
798 uint32_t ORE0:1;
799 } B;
800 } ORER;
801
802 union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */
803 uint32_t R;
804 struct {
805 uint32_t:16;
806 uint32_t IREE15:1;
807 uint32_t IREE14:1;
808 uint32_t IREE13:1;
809 uint32_t IREE12:1;
810 uint32_t IREE11:1;
811 uint32_t IREE10:1;
812 uint32_t IREE9:1;
813 uint32_t IREE8:1;
814 uint32_t IREE7:1;
815 uint32_t IREE6:1;
816 uint32_t IREE5:1;
817 uint32_t IREE4:1;
818 uint32_t IREE3:1;
819 uint32_t IREE2:1;
820 uint32_t IREE1:1;
821 uint32_t IREE0:1;
822 } B;
823 } IREER;
824
825 union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */
826 uint32_t R;
827 struct {
828 uint32_t:16;
829 uint32_t IFEE15:1;
830 uint32_t IFEE14:1;
831 uint32_t IFEE13:1;
832 uint32_t IFEE12:1;
833 uint32_t IFEE11:1;
834 uint32_t IFEE10:1;
835 uint32_t IFEE9:1;
836 uint32_t IFEE8:1;
837 uint32_t IFEE7:1;
838 uint32_t IFEE6:1;
839 uint32_t IFEE5:1;
840 uint32_t IFEE4:1;
841 uint32_t IFEE3:1;
842 uint32_t IFEE2:1;
843 uint32_t IFEE1:1;
844 uint32_t IFEE0:1;
845 } B;
846 } IFEER;
847
848 union SIU_IDFR_tag { /* External IRQ Digital Filter Register */
849 uint32_t R;
850 struct {
851 uint32_t:28;
852 uint32_t DFL:4;
853 } B;
854 } IDFR;
855
856 int32_t SIU_reserved1[3];
857
858 union SIU_PCR_tag { /* Pad Configuration Registers */
859 uint16_t R;
860 struct {
861 uint16_t:3;
862 uint16_t PA:3;
863 uint16_t OBE:1;
864 uint16_t IBE:1;
865 uint16_t DSC:2;
866 uint16_t ODE:1;
867 uint16_t HYS:1;
868 uint16_t SRC:2;
869 uint16_t WPE:1;
870 uint16_t WPS:1;
871 } B;
872 } PCR[512];
873
874 int16_t SIU_reserved_0[224];
875
876 union { /* GPIO Pin Data Output Registers */
877 uint8_t R;
878 struct {
879 uint8_t:7;
880 uint8_t PDO:1;
881 } B;
882 } GPDO[256];
883
884 int32_t SIU_reserved_3[64];
885
886 union { /* GPIO Pin Data Input Registers */
887 uint8_t R;
888 struct {
889 uint8_t:7;
890 uint8_t PDI:1;
891 } B;
892 } GPDI[256];
893
894 union { /* IMUX Register */
895 uint32_t R;
896 struct {
897 uint32_t TSEL5:2;
898 uint32_t TSEL4:2;
899 uint32_t TSEL3:2;
900 uint32_t TSEL2:2;
901 uint32_t TSEL1:2;
902 uint32_t TSEL0:2;
903 uint32_t:20;
904 } B;
905 } ETISR;
906
907 union { /* IMUX Register */
908 uint32_t R;
909 struct {
910 uint32_t ESEL15:2;
911 uint32_t ESEL14:2;
912 uint32_t ESEL13:2;
913 uint32_t ESEL12:2;
914 uint32_t ESEL11:2;
915 uint32_t ESEL10:2;
916 uint32_t ESEL9:2;
917 uint32_t ESEL8:2;
918 uint32_t ESEL7:2;
919 uint32_t ESEL6:2;
920 uint32_t ESEL5:2;
921 uint32_t ESEL4:2;
922 uint32_t ESEL3:2;
923 uint32_t ESEL2:2;
924 uint32_t ESEL1:2;
925 uint32_t ESEL0:2;
926 } B;
927 } EIISR;
928
929 union { /* IMUX Register */
930 uint32_t R;
931 struct {
932 uint32_t SINSELA:2;
933 uint32_t SSSELA:2;
934 uint32_t SCKSELA:2;
935 uint32_t TRIGSELA:2;
936 uint32_t SINSELB:2;
937 uint32_t SSSELB:2;
938 uint32_t SCKSELB:2;
939 uint32_t TRIGSELB:2;
940 uint32_t SINSELC:2;
941 uint32_t SSSELC:2;
942 uint32_t SCKSELC:2;
943 uint32_t TRIGSELC:2;
944 uint32_t SINSELD:2;
945 uint32_t SSSELD:2;
946 uint32_t SCKSELD:2;
947 uint32_t TRIGSELD:2;
948 } B;
949 } DISR;
950
951 int32_t SIU_reserved2[29];
952
953 union { /* Chip Configuration Register Register */
954 uint32_t R;
955 struct {
956 uint32_t:14;
957 uint32_t MATCH:1;
958 uint32_t DISNEX:1;
959 uint32_t:16;
960 } B;
961 } CCR;
962
963 union { /* External Clock Configuration Register Register */
964 uint32_t R;
965 struct {
966 uint32_t:18;
967 uint32_t ENGDIV:6;
968 uint32_t:4;
969 uint32_t EBTS:1;
970 uint32_t:1;
971 uint32_t EBDF:2;
972 } B;
973 } ECCR;
974
975 union {
976 uint32_t R;
977 } CARH;
978
979 union {
980 uint32_t R;
981 } CARL;
982
983 union {
984 uint32_t R;
985 } CBRH;
986
987 union {
988 uint32_t R;
989 } CBRL;
990
991 };
992/****************************************************************************/
993/* MODULE : EMIOS */
994/****************************************************************************/
995 struct EMIOS_tag {
996 union EMIOS_MCR_tag {
997 uint32_t R;
998 struct {
999 uint32_t:1;
1000 uint32_t MDIS:1;
1001 uint32_t FRZ:1;
1002 uint32_t GTBE:1;
1003 uint32_t ETB:1;
1004 uint32_t GPREN:1;
1005 uint32_t:6;
1006 uint32_t SRV:4;
1007 uint32_t GPRE:8;
1008 uint32_t:8;
1009 } B;
1010 } MCR; /* Module Configuration Register */
1011
1012 union {
1013 uint32_t R;
1014 struct {
1015 uint32_t:8;
1016 uint32_t F23:1;
1017 uint32_t F22:1;
1018 uint32_t F21:1;
1019 uint32_t F20:1;
1020 uint32_t F19:1;
1021 uint32_t F18:1;
1022 uint32_t F17:1;
1023 uint32_t F16:1;
1024 uint32_t F15:1;
1025 uint32_t F14:1;
1026 uint32_t F13:1;
1027 uint32_t F12:1;
1028 uint32_t F11:1;
1029 uint32_t F10:1;
1030 uint32_t F9:1;
1031 uint32_t F8:1;
1032 uint32_t F7:1;
1033 uint32_t F6:1;
1034 uint32_t F5:1;
1035 uint32_t F4:1;
1036 uint32_t F3:1;
1037 uint32_t F2:1;
1038 uint32_t F1:1;
1039 uint32_t F0:1;
1040 } B;
1041 } GFR; /* Global FLAG Register */
1042
1043 union {
1044 uint32_t R;
1045 struct {
1046 uint32_t:8;
1047 uint32_t OU23:1;
1048 uint32_t OU22:1;
1049 uint32_t OU21:1;
1050 uint32_t OU20:1;
1051 uint32_t OU19:1;
1052 uint32_t OU18:1;
1053 uint32_t OU17:1;
1054 uint32_t OU16:1;
1055 uint32_t OU15:1;
1056 uint32_t OU14:1;
1057 uint32_t OU13:1;
1058 uint32_t OU12:1;
1059 uint32_t OU11:1;
1060 uint32_t OU10:1;
1061 uint32_t OU9:1;
1062 uint32_t OU8:1;
1063 uint32_t OU7:1;
1064 uint32_t OU6:1;
1065 uint32_t OU5:1;
1066 uint32_t OU4:1;
1067 uint32_t OU3:1;
1068 uint32_t OU2:1;
1069 uint32_t OU1:1;
1070 uint32_t OU0:1;
1071 } B;
1072 } OUDR; /* Output Update Disable Register */
1073
1074 uint32_t emios_reserved[5];
1075
1076 struct EMIOS_CH_tag {
1077 union {
1078 uint32_t R; /* Channel A Data Register */
1079 } CADR;
1080
1081 union {
1082 uint32_t R; /* Channel B Data Register */
1083 } CBDR;
1084
1085 union {
1086 uint32_t R; /* Channel Counter Register */
1087 } CCNTR;
1088
1089 union EMIOS_CCR_tag {
1090 uint32_t R;
1091 struct {
1092 uint32_t FREN:1;
1093 uint32_t ODIS:1;
1094 uint32_t ODISSL:2;
1095 uint32_t UCPRE:2;
1096 uint32_t UCPREN:1;
1097 uint32_t DMA:1;
1098 uint32_t:1;
1099 uint32_t IF:4;
1100 uint32_t FCK:1;
1101 uint32_t FEN:1;
1102 uint32_t:3;
1103 uint32_t FORCMA:1;
1104 uint32_t FORCMB:1;
1105 uint32_t:1;
1106 uint32_t BSL:2;
1107 uint32_t EDSEL:1;
1108 uint32_t EDPOL:1;
1109 uint32_t MODE:7;
1110 } B;
1111 } CCR; /* Channel Control Register */
1112
1113 union EMIOS_CSR_tag {
1114 uint32_t R;
1115 struct {
1116 uint32_t OVR:1;
1117 uint32_t:15;
1118 uint32_t OVFL:1;
1119 uint32_t:12;
1120 uint32_t UCIN:1;
1121 uint32_t UCOUT:1;
1122 uint32_t FLAG:1;
1123 } B;
1124 } CSR; /* Channel Status Register */
1125 uint32_t emios_channel_reserved[3];
1126
1127 } CH[24];
1128
1129 };
1130/****************************************************************************/
1131/* MODULE :ETPU */
1132/****************************************************************************/
1133
1134/***************************Configuration Registers**************************/
1135
1136 struct ETPU_tag {
1137 union { /* MODULE CONFIGURATION REGISTER */
1138 uint32_t R;
1139 struct {
1140 uint32_t GEC:1; /* Global Exception Clear */
1141 uint32_t:3;
1142 uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */
1143
1144 uint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */
1145
1146 uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */
1147
1148 uint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */
1149
1150 uint32_t:3;
1151 uint32_t SCMSIZE:5; /* Shared Code Memory size */
1152 uint32_t:5;
1153 uint32_t SCMMISF:1; /* SCM MISC Flag */
1154 uint32_t SCMMISEN:1; /* SCM MISC Enable */
1155 uint32_t:2;
1156 uint32_t VIS:1; /* SCM Visability */
1157 uint32_t:5;
1158 uint32_t GTBE:1; /* Global Time Base Enable */
1159 } B;
1160 } MCR;
1161
1162 union { /* COHERENT DUAL-PARAMETER CONTROL */
1163 uint32_t R;
1164 struct {
1165 uint32_t STS:1; /* Start Status bit */
1166 uint32_t CTBASE:5; /* Channel Transfer Base */
1167 uint32_t PBASE:10; /* Parameter Buffer Base Address */
1168 uint32_t PWIDTH:1; /* Parameter Width */
1169 uint32_t PARAM0:7; /* Channel Parameter 0 */
1170 uint32_t WR:1;
1171 uint32_t PARAM1:7; /* Channel Parameter 1 */
1172 } B;
1173 } CDCR;
1174
1175 uint32_t etpu_reserved1;
1176
1177 union { /* MISC Compare Register */
1178 uint32_t R;
1179 } MISCCMPR;
1180
1181 union { /* SCM off-range Date Register */
1182 uint32_t R;
1183 } SCMOFFDATAR;
1184
1185 union { /* ETPU_A Configuration Register */
1186 uint32_t R;
1187 struct {
1188 uint32_t FEND:1; /* Force END */
1189 uint32_t MDIS:1; /* Low power Stop */
1190 uint32_t:1;
1191 uint32_t STF:1; /* Stop Flag */
1192 uint32_t:4;
1193 uint32_t HLTF:1; /* Halt Mode Flag */
1194 uint32_t:4;
1195 uint32_t FPSCK:3; /* Filter Prescaler Clock Control */
1196 uint32_t CDFC:2;
1197 uint32_t:9;
1198 uint32_t ETB:5; /* Entry Table Base */
1199 } B;
1200 } ECR_A;
1201
1202 union { /* ETPU_B Configuration Register */
1203 uint32_t R;
1204 struct {
1205 uint32_t FEND:1; /* Force END */
1206 uint32_t MDIS:1; /* Low power Stop */
1207 uint32_t:1;
1208 uint32_t STF:1; /* Stop Flag */
1209 uint32_t:4;
1210 uint32_t HLTF:1; /* Halt Mode Flag */
1211 uint32_t:4;
1212 uint32_t FPSCK:3; /* Filter Prescaler Clock Control */
1213 uint32_t CDFC:2;
1214 uint32_t:9;
1215 uint32_t ETB:5; /* Entry Table Base */
1216 } B;
1217 } ECR_B;
1218
1219 uint32_t etpu_reserved4;
1220
1221 union { /* ETPU_A Timebase Configuration Register */
1222 uint32_t R;
1223 struct {
1224 uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
1225 uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
1226 uint32_t:1;
1227 uint32_t AM:1; /* Angle Mode */
1228 uint32_t:3;
1229 uint32_t TCR2P:6; /* TCR2 Prescaler Control */
1230 uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
1231 uint32_t:6;
1232 uint32_t TCR1P:8; /* TCR1 Prescaler Control */
1233 } B;
1234 } TBCR_A;
1235
1236 union { /* ETPU_A TCR1 Visibility Register */
1237 uint32_t R;
1238 } TB1R_A;
1239
1240 union { /* ETPU_A TCR2 Visibility Register */
1241 uint32_t R;
1242 } TB2R_A;
1243
1244 union { /* ETPU_A STAC Configuration Register */
1245 uint32_t R;
1246 struct {
1247 uint32_t REN1:1; /* Resource Enable TCR1 */
1248 uint32_t RSC1:1; /* Resource Control TCR1 */
1249 uint32_t:2;
1250 uint32_t SERVER_ID1:4;
1251 uint32_t:4;
1252 uint32_t SRV1:4; /* Resource Server Slot */
1253 uint32_t REN2:1; /* Resource Enable TCR2 */
1254 uint32_t RSC2:1; /* Resource Control TCR2 */
1255 uint32_t:2;
1256 uint32_t SERVER_ID2:4;
1257 uint32_t:4;
1258 uint32_t SRV2:4; /* Resource Server Slot */
1259 } B;
1260 } REDCR_A;
1261
1262 uint32_t etpu_reserved5[4];
1263
1264 union { /* ETPU_B Timebase Configuration Register */
1265 uint32_t R;
1266 struct {
1267 uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
1268 uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
1269 uint32_t:1;
1270 uint32_t AM:1; /* Angle Mode */
1271 uint32_t:3;
1272 uint32_t TCR2P:6; /* TCR2 Prescaler Control */
1273 uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
1274 uint32_t:6;
1275 uint32_t TCR1P:8; /* TCR1 Prescaler Control */
1276 } B;
1277 } TBCR_B;
1278
1279 union { /* ETPU_B TCR1 Visibility Register */
1280 uint32_t R;
1281 } TB1R_B;
1282
1283 union { /* ETPU_B TCR2 Visibility Register */
1284 uint32_t R;
1285 } TB2R_B;
1286
1287 union { /* ETPU_B STAC Configuration Register */
1288 uint32_t R;
1289 struct {
1290 uint32_t REN1:1; /* Resource Enable TCR1 */
1291 uint32_t RSC1:1; /* Resource Control TCR1 */
1292 uint32_t:2;
1293 uint32_t SERVER_ID1:4;
1294 uint32_t:4;
1295 uint32_t SRV1:4; /* Resource Server Slot */
1296 uint32_t REN2:1; /* Resource Enable TCR2 */
1297 uint32_t RSC2:1; /* Resource Control TCR2 */
1298 uint32_t:2;
1299 uint32_t SERVER_ID2:4;
1300 uint32_t:4;
1301 uint32_t SRV2:4; /* Resource Server Slot */
1302 } B;
1303 } REDCR_B;
1304
1305 uint32_t etpu_reserved7[108];
1306
1307/*****************************Status and Control Registers**************************/
1308
1309 union { /* ETPU_A Channel Interrut Status */
1310 uint32_t R;
1311 struct {
1312 uint32_t CIS31:1; /* Channel 31 Interrut Status */
1313 uint32_t CIS30:1; /* Channel 30 Interrut Status */
1314 uint32_t CIS29:1; /* Channel 29 Interrut Status */
1315 uint32_t CIS28:1; /* Channel 28 Interrut Status */
1316 uint32_t CIS27:1; /* Channel 27 Interrut Status */
1317 uint32_t CIS26:1; /* Channel 26 Interrut Status */
1318 uint32_t CIS25:1; /* Channel 25 Interrut Status */
1319 uint32_t CIS24:1; /* Channel 24 Interrut Status */
1320 uint32_t CIS23:1; /* Channel 23 Interrut Status */
1321 uint32_t CIS22:1; /* Channel 22 Interrut Status */
1322 uint32_t CIS21:1; /* Channel 21 Interrut Status */
1323 uint32_t CIS20:1; /* Channel 20 Interrut Status */
1324 uint32_t CIS19:1; /* Channel 19 Interrut Status */
1325 uint32_t CIS18:1; /* Channel 18 Interrut Status */
1326 uint32_t CIS17:1; /* Channel 17 Interrut Status */
1327 uint32_t CIS16:1; /* Channel 16 Interrut Status */
1328 uint32_t CIS15:1; /* Channel 15 Interrut Status */
1329 uint32_t CIS14:1; /* Channel 14 Interrut Status */
1330 uint32_t CIS13:1; /* Channel 13 Interrut Status */
1331 uint32_t CIS12:1; /* Channel 12 Interrut Status */
1332 uint32_t CIS11:1; /* Channel 11 Interrut Status */
1333 uint32_t CIS10:1; /* Channel 10 Interrut Status */
1334 uint32_t CIS9:1; /* Channel 9 Interrut Status */
1335 uint32_t CIS8:1; /* Channel 8 Interrut Status */
1336 uint32_t CIS7:1; /* Channel 7 Interrut Status */
1337 uint32_t CIS6:1; /* Channel 6 Interrut Status */
1338 uint32_t CIS5:1; /* Channel 5 Interrut Status */
1339 uint32_t CIS4:1; /* Channel 4 Interrut Status */
1340 uint32_t CIS3:1; /* Channel 3 Interrut Status */
1341 uint32_t CIS2:1; /* Channel 2 Interrut Status */
1342 uint32_t CIS1:1; /* Channel 1 Interrut Status */
1343 uint32_t CIS0:1; /* Channel 0 Interrut Status */
1344 } B;
1345 } CISR_A;
1346
1347 union { /* ETPU_B Channel Interruput Status */
1348 uint32_t R;
1349 struct {
1350 uint32_t CIS31:1; /* Channel 31 Interrut Status */
1351 uint32_t CIS30:1; /* Channel 30 Interrut Status */
1352 uint32_t CIS29:1; /* Channel 29 Interrut Status */
1353 uint32_t CIS28:1; /* Channel 28 Interrut Status */
1354 uint32_t CIS27:1; /* Channel 27 Interrut Status */
1355 uint32_t CIS26:1; /* Channel 26 Interrut Status */
1356 uint32_t CIS25:1; /* Channel 25 Interrut Status */
1357 uint32_t CIS24:1; /* Channel 24 Interrut Status */
1358 uint32_t CIS23:1; /* Channel 23 Interrut Status */
1359 uint32_t CIS22:1; /* Channel 22 Interrut Status */
1360 uint32_t CIS21:1; /* Channel 21 Interrut Status */
1361 uint32_t CIS20:1; /* Channel 20 Interrut Status */
1362 uint32_t CIS19:1; /* Channel 19 Interrut Status */
1363 uint32_t CIS18:1; /* Channel 18 Interrut Status */
1364 uint32_t CIS17:1; /* Channel 17 Interrut Status */
1365 uint32_t CIS16:1; /* Channel 16 Interrut Status */
1366 uint32_t CIS15:1; /* Channel 15 Interrut Status */
1367 uint32_t CIS14:1; /* Channel 14 Interrut Status */
1368 uint32_t CIS13:1; /* Channel 13 Interrut Status */
1369 uint32_t CIS12:1; /* Channel 12 Interrut Status */
1370 uint32_t CIS11:1; /* Channel 11 Interrut Status */
1371 uint32_t CIS10:1; /* Channel 10 Interrut Status */
1372 uint32_t CIS9:1; /* Channel 9 Interrut Status */
1373 uint32_t CIS8:1; /* Channel 8 Interrut Status */
1374 uint32_t CIS7:1; /* Channel 7 Interrut Status */
1375 uint32_t CIS6:1; /* Channel 6 Interrut Status */
1376 uint32_t CIS5:1; /* Channel 5 Interrut Status */
1377 uint32_t CIS4:1; /* Channel 4 Interrut Status */
1378 uint32_t CIS3:1; /* Channel 3 Interrut Status */
1379 uint32_t CIS2:1; /* Channel 2 Interrut Status */
1380 uint32_t CIS1:1; /* Channel 1 Interrupt Status */
1381 uint32_t CIS0:1; /* Channel 0 Interrupt Status */
1382 } B;
1383 } CISR_B;
1384
1385 uint32_t etpu_reserved9[2];
1386
1387 union { /* ETPU_A Data Transfer Request Status */
1388 uint32_t R;
1389 struct {
1390 uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
1391 uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
1392 uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
1393 uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
1394 uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
1395 uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
1396 uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
1397 uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
1398 uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
1399 uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
1400 uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
1401 uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
1402 uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
1403 uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
1404 uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
1405 uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
1406 uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
1407 uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
1408 uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
1409 uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
1410 uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
1411 uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
1412 uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
1413 uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
1414 uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
1415 uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
1416 uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
1417 uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
1418 uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
1419 uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
1420 uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
1421 uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
1422 } B;
1423 } CDTRSR_A;
1424
1425 union { /* ETPU_B Data Transfer Request Status */
1426 uint32_t R;
1427 struct {
1428 uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
1429 uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
1430 uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
1431 uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
1432 uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
1433 uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
1434 uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
1435 uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
1436 uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
1437 uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
1438 uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
1439 uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
1440 uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
1441 uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
1442 uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
1443 uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
1444 uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
1445 uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
1446 uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
1447 uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
1448 uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
1449 uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
1450 uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
1451 uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
1452 uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
1453 uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
1454 uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
1455 uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
1456 uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
1457 uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
1458 uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
1459 uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
1460 } B;
1461 } CDTRSR_B;
1462
1463 uint32_t etpu_reserved11[2];
1464
1465 union { /* ETPU_A Interruput Overflow Status */
1466 uint32_t R;
1467 struct {
1468 uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
1469 uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
1470 uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
1471 uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
1472 uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
1473 uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
1474 uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
1475 uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
1476 uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
1477 uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
1478 uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
1479 uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
1480 uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
1481 uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
1482 uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
1483 uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
1484 uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
1485 uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
1486 uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
1487 uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
1488 uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
1489 uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
1490 uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
1491 uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
1492 uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
1493 uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
1494 uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
1495 uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
1496 uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
1497 uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
1498 uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
1499 uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
1500 } B;
1501 } CIOSR_A;
1502
1503 union { /* ETPU_B Interruput Overflow Status */
1504 uint32_t R;
1505 struct {
1506 uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
1507 uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
1508 uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
1509 uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
1510 uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
1511 uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
1512 uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
1513 uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
1514 uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
1515 uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
1516 uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
1517 uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
1518 uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
1519 uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
1520 uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
1521 uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
1522 uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
1523 uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
1524 uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
1525 uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
1526 uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
1527 uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
1528 uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
1529 uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
1530 uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
1531 uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
1532 uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
1533 uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
1534 uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
1535 uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
1536 uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
1537 uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
1538 } B;
1539 } CIOSR_B;
1540
1541 uint32_t etpu_reserved13[2];
1542
1543 union { /* ETPU_A Data Transfer Overflow Status */
1544 uint32_t R;
1545 struct {
1546 uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
1547 uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
1548 uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
1549 uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
1550 uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
1551 uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
1552 uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
1553 uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
1554 uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
1555 uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
1556 uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
1557 uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
1558 uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
1559 uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
1560 uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
1561 uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
1562 uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
1563 uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
1564 uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
1565 uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
1566 uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
1567 uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
1568 uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
1569 uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
1570 uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
1571 uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
1572 uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
1573 uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
1574 uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
1575 uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
1576 uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
1577 uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
1578 } B;
1579 } CDTROSR_A;
1580
1581 union { /* ETPU_B Data Transfer Overflow Status */
1582 uint32_t R;
1583 struct {
1584 uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
1585 uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
1586 uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
1587 uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
1588 uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
1589 uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
1590 uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
1591 uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
1592 uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
1593 uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
1594 uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
1595 uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
1596 uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
1597 uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
1598 uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
1599 uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
1600 uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
1601 uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
1602 uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
1603 uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
1604 uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
1605 uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
1606 uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
1607 uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
1608 uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
1609 uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
1610 uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
1611 uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
1612 uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
1613 uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
1614 uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
1615 uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
1616 } B;
1617 } CDTROSR_B;
1618
1619 uint32_t etpu_reserved15[2];
1620
1621 union { /* ETPU_A Channel Interruput Enable */
1622 uint32_t R;
1623 struct {
1624 uint32_t CIE31:1; /* Channel 31 Interruput Enable */
1625 uint32_t CIE30:1; /* Channel 30 Interruput Enable */
1626 uint32_t CIE29:1; /* Channel 29 Interruput Enable */
1627 uint32_t CIE28:1; /* Channel 28 Interruput Enable */
1628 uint32_t CIE27:1; /* Channel 27 Interruput Enable */
1629 uint32_t CIE26:1; /* Channel 26 Interruput Enable */
1630 uint32_t CIE25:1; /* Channel 25 Interruput Enable */
1631 uint32_t CIE24:1; /* Channel 24 Interruput Enable */
1632 uint32_t CIE23:1; /* Channel 23 Interruput Enable */
1633 uint32_t CIE22:1; /* Channel 22 Interruput Enable */
1634 uint32_t CIE21:1; /* Channel 21 Interruput Enable */
1635 uint32_t CIE20:1; /* Channel 20 Interruput Enable */
1636 uint32_t CIE19:1; /* Channel 19 Interruput Enable */
1637 uint32_t CIE18:1; /* Channel 18 Interruput Enable */
1638 uint32_t CIE17:1; /* Channel 17 Interruput Enable */
1639 uint32_t CIE16:1; /* Channel 16 Interruput Enable */
1640 uint32_t CIE15:1; /* Channel 15 Interruput Enable */
1641 uint32_t CIE14:1; /* Channel 14 Interruput Enable */
1642 uint32_t CIE13:1; /* Channel 13 Interruput Enable */
1643 uint32_t CIE12:1; /* Channel 12 Interruput Enable */
1644 uint32_t CIE11:1; /* Channel 11 Interruput Enable */
1645 uint32_t CIE10:1; /* Channel 10 Interruput Enable */
1646 uint32_t CIE9:1; /* Channel 9 Interruput Enable */
1647 uint32_t CIE8:1; /* Channel 8 Interruput Enable */
1648 uint32_t CIE7:1; /* Channel 7 Interruput Enable */
1649 uint32_t CIE6:1; /* Channel 6 Interruput Enable */
1650 uint32_t CIE5:1; /* Channel 5 Interruput Enable */
1651 uint32_t CIE4:1; /* Channel 4 Interruput Enable */
1652 uint32_t CIE3:1; /* Channel 3 Interruput Enable */
1653 uint32_t CIE2:1; /* Channel 2 Interruput Enable */
1654 uint32_t CIE1:1; /* Channel 1 Interruput Enable */
1655 uint32_t CIE0:1; /* Channel 0 Interruput Enable */
1656 } B;
1657 } CIER_A;
1658
1659 union { /* ETPU_B Channel Interruput Enable */
1660 uint32_t R;
1661 struct {
1662 uint32_t CIE31:1; /* Channel 31 Interruput Enable */
1663 uint32_t CIE30:1; /* Channel 30 Interruput Enable */
1664 uint32_t CIE29:1; /* Channel 29 Interruput Enable */
1665 uint32_t CIE28:1; /* Channel 28 Interruput Enable */
1666 uint32_t CIE27:1; /* Channel 27 Interruput Enable */
1667 uint32_t CIE26:1; /* Channel 26 Interruput Enable */
1668 uint32_t CIE25:1; /* Channel 25 Interruput Enable */
1669 uint32_t CIE24:1; /* Channel 24 Interruput Enable */
1670 uint32_t CIE23:1; /* Channel 23 Interruput Enable */
1671 uint32_t CIE22:1; /* Channel 22 Interruput Enable */
1672 uint32_t CIE21:1; /* Channel 21 Interruput Enable */
1673 uint32_t CIE20:1; /* Channel 20 Interruput Enable */
1674 uint32_t CIE19:1; /* Channel 19 Interruput Enable */
1675 uint32_t CIE18:1; /* Channel 18 Interruput Enable */
1676 uint32_t CIE17:1; /* Channel 17 Interruput Enable */
1677 uint32_t CIE16:1; /* Channel 16 Interruput Enable */
1678 uint32_t CIE15:1; /* Channel 15 Interruput Enable */
1679 uint32_t CIE14:1; /* Channel 14 Interruput Enable */
1680 uint32_t CIE13:1; /* Channel 13 Interruput Enable */
1681 uint32_t CIE12:1; /* Channel 12 Interruput Enable */
1682 uint32_t CIE11:1; /* Channel 11 Interruput Enable */
1683 uint32_t CIE10:1; /* Channel 10 Interruput Enable */
1684 uint32_t CIE9:1; /* Channel 9 Interruput Enable */
1685 uint32_t CIE8:1; /* Channel 8 Interruput Enable */
1686 uint32_t CIE7:1; /* Channel 7 Interruput Enable */
1687 uint32_t CIE6:1; /* Channel 6 Interruput Enable */
1688 uint32_t CIE5:1; /* Channel 5 Interruput Enable */
1689 uint32_t CIE4:1; /* Channel 4 Interruput Enable */
1690 uint32_t CIE3:1; /* Channel 3 Interruput Enable */
1691 uint32_t CIE2:1; /* Channel 2 Interruput Enable */
1692 uint32_t CIE1:1; /* Channel 1 Interruput Enable */
1693 uint32_t CIE0:1; /* Channel 0 Interruput Enable */
1694 } B;
1695 } CIER_B;
1696
1697 uint32_t etpu_reserved17[2];
1698
1699 union { /* ETPU_A Channel Data Transfer Request Enable */
1700 uint32_t R;
1701 struct {
1702 uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
1703 uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
1704 uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
1705 uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
1706 uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
1707 uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
1708 uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
1709 uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
1710 uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
1711 uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
1712 uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
1713 uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
1714 uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
1715 uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
1716 uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
1717 uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
1718 uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
1719 uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
1720 uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
1721 uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
1722 uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
1723 uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
1724 uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
1725 uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
1726 uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
1727 uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
1728 uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
1729 uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
1730 uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
1731 uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
1732 uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
1733 uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
1734 } B;
1735 } CDTRER_A;
1736
1737 union { /* ETPU_B Channel Data Transfer Request Enable */
1738 uint32_t R;
1739 struct {
1740 uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
1741 uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
1742 uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
1743 uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
1744 uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
1745 uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
1746 uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
1747 uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
1748 uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
1749 uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
1750 uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
1751 uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
1752 uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
1753 uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
1754 uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
1755 uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
1756 uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
1757 uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
1758 uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
1759 uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
1760 uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
1761 uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
1762 uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
1763 uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
1764 uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
1765 uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
1766 uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
1767 uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
1768 uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
1769 uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
1770 uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
1771 uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
1772 } B;
1773 } CDTRER_B;
1774
1775 uint32_t etpu_reserved20[10];
1776 union { /* ETPU_A Channel Pending Service Status */
1777 uint32_t R;
1778 struct {
1779 uint32_t SR31:1; /* Channel 31 Pending Service Status */
1780 uint32_t SR30:1; /* Channel 30 Pending Service Status */
1781 uint32_t SR29:1; /* Channel 29 Pending Service Status */
1782 uint32_t SR28:1; /* Channel 28 Pending Service Status */
1783 uint32_t SR27:1; /* Channel 27 Pending Service Status */
1784 uint32_t SR26:1; /* Channel 26 Pending Service Status */
1785 uint32_t SR25:1; /* Channel 25 Pending Service Status */
1786 uint32_t SR24:1; /* Channel 24 Pending Service Status */
1787 uint32_t SR23:1; /* Channel 23 Pending Service Status */
1788 uint32_t SR22:1; /* Channel 22 Pending Service Status */
1789 uint32_t SR21:1; /* Channel 21 Pending Service Status */
1790 uint32_t SR20:1; /* Channel 20 Pending Service Status */
1791 uint32_t SR19:1; /* Channel 19 Pending Service Status */
1792 uint32_t SR18:1; /* Channel 18 Pending Service Status */
1793 uint32_t SR17:1; /* Channel 17 Pending Service Status */
1794 uint32_t SR16:1; /* Channel 16 Pending Service Status */
1795 uint32_t SR15:1; /* Channel 15 Pending Service Status */
1796 uint32_t SR14:1; /* Channel 14 Pending Service Status */
1797 uint32_t SR13:1; /* Channel 13 Pending Service Status */
1798 uint32_t SR12:1; /* Channel 12 Pending Service Status */
1799 uint32_t SR11:1; /* Channel 11 Pending Service Status */
1800 uint32_t SR10:1; /* Channel 10 Pending Service Status */
1801 uint32_t SR9:1; /* Channel 9 Pending Service Status */
1802 uint32_t SR8:1; /* Channel 8 Pending Service Status */
1803 uint32_t SR7:1; /* Channel 7 Pending Service Status */
1804 uint32_t SR6:1; /* Channel 6 Pending Service Status */
1805 uint32_t SR5:1; /* Channel 5 Pending Service Status */
1806 uint32_t SR4:1; /* Channel 4 Pending Service Status */
1807 uint32_t SR3:1; /* Channel 3 Pending Service Status */
1808 uint32_t SR2:1; /* Channel 2 Pending Service Status */
1809 uint32_t SR1:1; /* Channel 1 Pending Service Status */
1810 uint32_t SR0:1; /* Channel 0 Pending Service Status */
1811 } B;
1812 } CPSSR_A;
1813
1814 union { /* ETPU_B Channel Pending Service Status */
1815 uint32_t R;
1816 struct {
1817 uint32_t SR31:1; /* Channel 31 Pending Service Status */
1818 uint32_t SR30:1; /* Channel 30 Pending Service Status */
1819 uint32_t SR29:1; /* Channel 29 Pending Service Status */
1820 uint32_t SR28:1; /* Channel 28 Pending Service Status */
1821 uint32_t SR27:1; /* Channel 27 Pending Service Status */
1822 uint32_t SR26:1; /* Channel 26 Pending Service Status */
1823 uint32_t SR25:1; /* Channel 25 Pending Service Status */
1824 uint32_t SR24:1; /* Channel 24 Pending Service Status */
1825 uint32_t SR23:1; /* Channel 23 Pending Service Status */
1826 uint32_t SR22:1; /* Channel 22 Pending Service Status */
1827 uint32_t SR21:1; /* Channel 21 Pending Service Status */
1828 uint32_t SR20:1; /* Channel 20 Pending Service Status */
1829 uint32_t SR19:1; /* Channel 19 Pending Service Status */
1830 uint32_t SR18:1; /* Channel 18 Pending Service Status */
1831 uint32_t SR17:1; /* Channel 17 Pending Service Status */
1832 uint32_t SR16:1; /* Channel 16 Pending Service Status */
1833 uint32_t SR15:1; /* Channel 15 Pending Service Status */
1834 uint32_t SR14:1; /* Channel 14 Pending Service Status */
1835 uint32_t SR13:1; /* Channel 13 Pending Service Status */
1836 uint32_t SR12:1; /* Channel 12 Pending Service Status */
1837 uint32_t SR11:1; /* Channel 11 Pending Service Status */
1838 uint32_t SR10:1; /* Channel 10 Pending Service Status */
1839 uint32_t SR9:1; /* Channel 9 Pending Service Status */
1840 uint32_t SR8:1; /* Channel 8 Pending Service Status */
1841 uint32_t SR7:1; /* Channel 7 Pending Service Status */
1842 uint32_t SR6:1; /* Channel 6 Pending Service Status */
1843 uint32_t SR5:1; /* Channel 5 Pending Service Status */
1844 uint32_t SR4:1; /* Channel 4 Pending Service Status */
1845 uint32_t SR3:1; /* Channel 3 Pending Service Status */
1846 uint32_t SR2:1; /* Channel 2 Pending Service Status */
1847 uint32_t SR1:1; /* Channel 1 Pending Service Status */
1848 uint32_t SR0:1; /* Channel 0 Pending Service Status */
1849 } B;
1850 } CPSSR_B;
1851
1852 uint32_t etpu_reserved20a[2];
1853
1854 union { /* ETPU_A Channel Service Status */
1855 uint32_t R;
1856 struct {
1857 uint32_t SS31:1; /* Channel 31 Service Status */
1858 uint32_t SS30:1; /* Channel 30 Service Status */
1859 uint32_t SS29:1; /* Channel 29 Service Status */
1860 uint32_t SS28:1; /* Channel 28 Service Status */
1861 uint32_t SS27:1; /* Channel 27 Service Status */
1862 uint32_t SS26:1; /* Channel 26 Service Status */
1863 uint32_t SS25:1; /* Channel 25 Service Status */
1864 uint32_t SS24:1; /* Channel 24 Service Status */
1865 uint32_t SS23:1; /* Channel 23 Service Status */
1866 uint32_t SS22:1; /* Channel 22 Service Status */
1867 uint32_t SS21:1; /* Channel 21 Service Status */
1868 uint32_t SS20:1; /* Channel 20 Service Status */
1869 uint32_t SS19:1; /* Channel 19 Service Status */
1870 uint32_t SS18:1; /* Channel 18 Service Status */
1871 uint32_t SS17:1; /* Channel 17 Service Status */
1872 uint32_t SS16:1; /* Channel 16 Service Status */
1873 uint32_t SS15:1; /* Channel 15 Service Status */
1874 uint32_t SS14:1; /* Channel 14 Service Status */
1875 uint32_t SS13:1; /* Channel 13 Service Status */
1876 uint32_t SS12:1; /* Channel 12 Service Status */
1877 uint32_t SS11:1; /* Channel 11 Service Status */
1878 uint32_t SS10:1; /* Channel 10 Service Status */
1879 uint32_t SS9:1; /* Channel 9 Service Status */
1880 uint32_t SS8:1; /* Channel 8 Service Status */
1881 uint32_t SS7:1; /* Channel 7 Service Status */
1882 uint32_t SS6:1; /* Channel 6 Service Status */
1883 uint32_t SS5:1; /* Channel 5 Service Status */
1884 uint32_t SS4:1; /* Channel 4 Service Status */
1885 uint32_t SS3:1; /* Channel 3 Service Status */
1886 uint32_t SS2:1; /* Channel 2 Service Status */
1887 uint32_t SS1:1; /* Channel 1 Service Status */
1888 uint32_t SS0:1; /* Channel 0 Service Status */
1889 } B;
1890 } CSSR_A;
1891
1892 union { /* ETPU_B Channel Service Status */
1893 uint32_t R;
1894 struct {
1895 uint32_t SS31:1; /* Channel 31 Service Status */
1896 uint32_t SS30:1; /* Channel 30 Service Status */
1897 uint32_t SS29:1; /* Channel 29 Service Status */
1898 uint32_t SS28:1; /* Channel 28 Service Status */
1899 uint32_t SS27:1; /* Channel 27 Service Status */
1900 uint32_t SS26:1; /* Channel 26 Service Status */
1901 uint32_t SS25:1; /* Channel 25 Service Status */
1902 uint32_t SS24:1; /* Channel 24 Service Status */
1903 uint32_t SS23:1; /* Channel 23 Service Status */
1904 uint32_t SS22:1; /* Channel 22 Service Status */
1905 uint32_t SS21:1; /* Channel 21 Service Status */
1906 uint32_t SS20:1; /* Channel 20 Service Status */
1907 uint32_t SS19:1; /* Channel 19 Service Status */
1908 uint32_t SS18:1; /* Channel 18 Service Status */
1909 uint32_t SS17:1; /* Channel 17 Service Status */
1910 uint32_t SS16:1; /* Channel 16 Service Status */
1911 uint32_t SS15:1; /* Channel 15 Service Status */
1912 uint32_t SS14:1; /* Channel 14 Service Status */
1913 uint32_t SS13:1; /* Channel 13 Service Status */
1914 uint32_t SS12:1; /* Channel 12 Service Status */
1915 uint32_t SS11:1; /* Channel 11 Service Status */
1916 uint32_t SS10:1; /* Channel 10 Service Status */
1917 uint32_t SS9:1; /* Channel 9 Service Status */
1918 uint32_t SS8:1; /* Channel 8 Service Status */
1919 uint32_t SS7:1; /* Channel 7 Service Status */
1920 uint32_t SS6:1; /* Channel 6 Service Status */
1921 uint32_t SS5:1; /* Channel 5 Service Status */
1922 uint32_t SS4:1; /* Channel 4 Service Status */
1923 uint32_t SS3:1; /* Channel 3 Service Status */
1924 uint32_t SS2:1; /* Channel 2 Service Status */
1925 uint32_t SS1:1; /* Channel 1 Service Status */
1926 uint32_t SS0:1; /* Channel 0 Service Status */
1927 } B;
1928 } CSSR_B;
1929
1930 uint32_t etpu_reserved23[90];
1931
1932/*****************************Channels********************************/
1933
1934 struct {
1935 union {
1936 uint32_t R; /* Channel Configuration Register */
1937 struct {
1938 uint32_t CIE:1; /* Channel Interruput Enable */
1939 uint32_t DTRE:1; /* Data Transfer Request Enable */
1940 uint32_t CPR:2; /* Channel Priority */
1941 uint32_t:3;
1942 uint32_t ETCS:1; /* Entry Table Condition Select */
1943 uint32_t:3;
1944 uint32_t CFS:5; /* Channel Function Select */
1945 uint32_t ODIS:1; /* Output disable */
1946 uint32_t OPOL:1; /* output polarity */
1947 uint32_t:3;
1948 uint32_t CPBA:11; /* Channel Parameter Base Address */
1949 } B;
1950 } CR;
1951 union {
1952 uint32_t R; /* Channel Status Control Register */
1953 struct {
1954 uint32_t CIS:1; /* Channel Interruput Status */
1955 uint32_t CIOS:1; /* Channel Interruput Overflow Status */
1956 uint32_t:6;
1957 uint32_t DTRS:1; /* Data Transfer Status */
1958 uint32_t DTROS:1; /* Data Transfer Overflow Status */
1959 uint32_t:6;
1960 uint32_t IPS:1; /* Input Pin State */
1961 uint32_t OPS:1; /* Output Pin State */
1962 uint32_t OBE:1; /* Output Buffer Enable */
1963 uint32_t:11;
1964 uint32_t FM1:1; /* Function mode */
1965 uint32_t FM0:1; /* Function mode */
1966 } B;
1967 } SCR;
1968 union {
1969 uint32_t R; /* Channel Host Service Request Register */
1970 struct {
1971 uint32_t:29; /* Host Service Request */
1972 uint32_t HSR:3;
1973 } B;
1974 } HSRR;
1975 uint32_t etpu_reserved23;
1976 } CHAN[127];
1977
1978 };
1979/****************************************************************************/
1980/* MODULE : XBAR CrossBar */
1981/****************************************************************************/
1982 struct XBAR_tag {
1983 union {
1984 uint32_t R;
1985 struct {
1986 uint32_t:4;
1987
1988 uint32_t:4;
1989
1990 uint32_t:4;
1991
1992 uint32_t:4;
1993
1994 uint32_t:4;
1995
1996 uint32_t:1;
1997 uint32_t MSTR2:3;
1998 uint32_t:1;
1999 uint32_t MSTR1:3;
2000 uint32_t:1;
2001 uint32_t MSTR0:3;
2002 } B;
2003 } MPR0; /* Master Priority Register for Slave Port 0 */
2004
2005 uint32_t xbar_reserved1[3];
2006
2007 union {
2008 uint32_t R;
2009 struct {
2010 uint32_t RO:1;
2011 uint32_t:21;
2012 uint32_t ARB:2;
2013 uint32_t:2;
2014 uint32_t PCTL:2;
2015 uint32_t:1;
2016 uint32_t PARK:3;
2017 } B;
2018 } SGPCR0; /* General Purpose Control Register for Slave Port 0 */
2019
2020 uint32_t xbar_reserved2[59];
2021
2022 union {
2023 uint32_t R;
2024 struct {
2025 uint32_t:4;
2026
2027 uint32_t:4;
2028
2029 uint32_t:4;
2030
2031 uint32_t:4;
2032
2033 uint32_t:4;
2034
2035 uint32_t:1;
2036 uint32_t MSTR2:3;
2037 uint32_t:1;
2038 uint32_t MSTR1:3;
2039 uint32_t:1;
2040 uint32_t MSTR0:3;
2041 } B;
2042 } MPR1; /* Master Priority Register for Slave Port 1 */
2043
2044 uint32_t xbar_reserved3[3];
2045
2046 union {
2047 uint32_t R;
2048 struct {
2049 uint32_t RO:1;
2050 uint32_t:21;
2051 uint32_t ARB:2;
2052 uint32_t:2;
2053 uint32_t PCTL:2;
2054 uint32_t:1;
2055 uint32_t PARK:3;
2056 } B;
2057 } SGPCR1; /* General Purpose Control Register for Slave Port 1 */
2058
2059 uint32_t xbar_reserved4[123];
2060
2061 union {
2062 uint32_t R;
2063 struct {
2064 uint32_t:4;
2065
2066 uint32_t:4;
2067
2068 uint32_t:4;
2069
2070 uint32_t:4;
2071
2072 uint32_t:4;
2073
2074 uint32_t:1;
2075 uint32_t MSTR2:3;
2076 uint32_t:1;
2077 uint32_t MSTR1:3;
2078 uint32_t:1;
2079 uint32_t MSTR0:3;
2080 } B;
2081 } MPR3; /* Master Priority Register for Slave Port 3 */
2082
2083 uint32_t xbar_reserved5[3];
2084
2085 union {
2086 uint32_t R;
2087 struct {
2088 uint32_t RO:1;
2089 uint32_t:21;
2090 uint32_t ARB:2;
2091 uint32_t:2;
2092 uint32_t PCTL:2;
2093 uint32_t:1;
2094 uint32_t PARK:3;
2095 } B;
2096 } SGPCR3; /* General Purpose Control Register for Slave Port 3 */
2097 uint32_t xbar_reserved6[187];
2098
2099 union {
2100 uint32_t R;
2101 struct {
2102 uint32_t:4;
2103
2104 uint32_t:4;
2105
2106 uint32_t:4;
2107
2108 uint32_t:4;
2109
2110 uint32_t:4;
2111
2112 uint32_t:1;
2113 uint32_t MSTR2:3;
2114 uint32_t:1;
2115 uint32_t MSTR1:3;
2116 uint32_t:1;
2117 uint32_t MSTR0:3;
2118 } B;
2119 } MPR6; /* Master Priority Register for Slave Port 6 */
2120
2121 uint32_t xbar_reserved7[3];
2122
2123 union {
2124 uint32_t R;
2125 struct {
2126 uint32_t RO:1;
2127 uint32_t:21;
2128 uint32_t ARB:2;
2129 uint32_t:2;
2130 uint32_t PCTL:2;
2131 uint32_t:1;
2132 uint32_t PARK:3;
2133 } B;
2134 } SGPCR6; /* General Purpose Control Register for Slave Port 6 */
2135
2136 uint32_t xbar_reserved8[59];
2137
2138 union {
2139 uint32_t R;
2140 struct {
2141 uint32_t:4;
2142
2143 uint32_t:4;
2144
2145 uint32_t:4;
2146
2147 uint32_t:4;
2148
2149 uint32_t:4;
2150
2151 uint32_t:1;
2152 uint32_t MSTR2:3;
2153 uint32_t:1;
2154 uint32_t MSTR1:3;
2155 uint32_t:1;
2156 uint32_t MSTR0:3;
2157 } B;
2158 } MPR7; /* Master Priority Register for Slave Port 7 */
2159
2160 uint32_t xbar_reserved9[3];
2161
2162 union {
2163 uint32_t R;
2164 struct {
2165 uint32_t RO:1;
2166 uint32_t:21;
2167 uint32_t ARB:2;
2168 uint32_t:2;
2169 uint32_t PCTL:2;
2170 uint32_t:1;
2171 uint32_t PARK:3;
2172 } B;
2173 } SGPCR7; /* General Purpose Control Register for Slave Port 7 */
2174
2175 };
2176/****************************************************************************/
2177/* MODULE : ECSM */
2178/****************************************************************************/
2179 struct ECSM_tag {
2180
2181 uint32_t ecsm_reserved1[5];
2182
2183 uint16_t ecsm_reserved2;
2184
2185 union {
2186 uint16_t R;
2187 } SWTCR; //Software Watchdog Timer Control
2188
2189 uint8_t ecsm_reserved3[3];
2190
2191 union {
2192 uint8_t R;
2193 } SWTSR; //SWT Service Register
2194
2195 uint8_t ecsm_reserved4[3];
2196
2197 union {
2198 uint8_t R;
2199 } SWTIR; //SWT Interrupt Register
2200
2201 uint32_t ecsm_reserved5a[1];
2202 uint32_t ecsm_reserved5b[1];
2203
2204 uint32_t ecsm_reserved5c[6];
2205
2206 uint8_t ecsm_reserved6[3];
2207
2208 union {
2209 uint8_t R;
2210 struct {
2211 uint8_t:6;
2212 uint8_t ERNCR:1;
2213 uint8_t EFNCR:1;
2214 } B;
2215 } ECR; //ECC Configuration Register
2216
2217 uint8_t mcm_reserved8[3];
2218
2219 union {
2220 uint8_t R;
2221 struct {
2222 uint8_t:6;
2223 uint8_t RNCE:1;
2224 uint8_t FNCE:1;
2225 } B;
2226 } ESR; //ECC Status Register
2227
2228 uint16_t ecsm_reserved9;
2229
2230 union {
2231 uint16_t R;
2232 struct {
2233 uint16_t:6;
2234 uint16_t FRCNCI:1;
2235 uint16_t FR1NCI:1;
2236 uint16_t:1;
2237 uint16_t ERRBIT:7;
2238 } B;
2239 } EEGR; //ECC Error Generation Register
2240
2241 uint32_t ecsm_reserved10;
2242
2243 union {
2244 uint32_t R;
2245 struct {
2246 uint32_t FEAR:32;
2247 } B;
2248 } FEAR; //Flash ECC Address Register
2249
2250 uint16_t ecsm_reserved11;
2251
2252 union {
2253 uint8_t R;
2254 struct {
2255 uint8_t:4;
2256 uint8_t FEMR:4;
2257 } B;
2258 } FEMR; //Flash ECC Master Register
2259
2260 union {
2261 uint8_t R;
2262 struct {
2263 uint8_t WRITE:1;
2264 uint8_t SIZE:3;
2265 uint8_t PROT0:1;
2266 uint8_t PROT1:1;
2267 uint8_t PROT2:1;
2268 uint8_t PROT3:1;
2269 } B;
2270 } FEAT; //Flash ECC Attributes Register
2271
2272 union {
2273 uint32_t R;
2274 struct {
2275 uint32_t FEDH:32;
2276 } B;
2277 } FEDRH; //Flash ECC Data High Register
2278
2279 union {
2280 uint32_t R;
2281 struct {
2282 uint32_t FEDL:32;
2283 } B;
2284 } FEDRL; //Flash ECC Data Low Register
2285
2286 union {
2287 uint32_t R;
2288 struct {
2289 uint32_t REAR:32;
2290 } B;
2291 } REAR; //RAM ECC Address
2292
2293 uint8_t ecsm_reserved12[2];
2294
2295 union {
2296 uint8_t R;
2297 struct {
2298 uint8_t:4;
2299 uint8_t REMR:4;
2300 } B;
2301 } REMR; //RAM ECC Master
2302
2303 union {
2304 uint8_t R;
2305 struct {
2306 uint8_t WRITE:1;
2307 uint8_t SIZE:3;
2308 uint8_t PROT0:1;
2309 uint8_t PROT1:1;
2310 uint8_t PROT2:1;
2311 uint8_t PROT3:1;
2312 } B;
2313 } REAT; // RAM ECC Attributes Register
2314
2315 union {
2316 uint32_t R;
2317 struct {
2318 uint32_t REDH:32;
2319 } B;
2320 } REDRH; //RAM ECC Data High Register
2321
2322 union {
2323 uint32_t R;
2324 struct {
2325 uint32_t REDL:32;
2326 } B;
2327 } REDRL; //RAMECC Data Low Register
2328
2329 };
2330/****************************************************************************/
2331/* MODULE : INTC */
2332/****************************************************************************/
2333 struct INTC_tag {
2334 union {
2335 uint32_t R;
2336 struct {
2337 uint32_t:26;
2338 uint32_t VTES:1;
2339 uint32_t:4;
2340 uint32_t HVEN:1;
2341 } B;
2342 } MCR; /* Module Configuration Register */
2343
2344 int32_t INTC_reserved00;
2345
2346 union {
2347 uint32_t R;
2348 struct {
2349 uint32_t:28;
2350 uint32_t PRI:4;
2351 } B;
2352 } CPR; /* Current Priority Register */
2353
2354 uint32_t intc_reserved1;
2355
2356 union {
2357 uint32_t R;
2358 struct {
2359 uint32_t VTBA:21;
2360 uint32_t INTVEC:9;
2361 uint32_t:2;
2362 } B;
2363 } IACKR; /* Interrupt Acknowledge Register */
2364
2365 uint32_t intc_reserved2;
2366
2367 union {
2368 uint32_t R;
2369 struct {
2370 uint32_t:32;
2371 } B;
2372 } EOIR; /* End of Interrupt Register */
2373
2374 uint32_t intc_reserved3;
2375
2376 union {
2377 uint8_t R;
2378 struct {
2379 uint8_t:6;
2380 uint8_t SET:1;
2381 uint8_t CLR:1;
2382 } B;
2383 } SSCIR[8]; /* Software Set/Clear Interruput Register */
2384
2385 uint32_t intc_reserved4[6];
2386
2387 union {
2388 uint8_t R;
2389 struct {
2390 uint8_t:4;
2391 uint8_t PRI:4;
2392 } B;
2393 } PSR[358]; /* Software Set/Clear Interrupt Register */
2394
2395 };
2396/****************************************************************************/
2397/* MODULE : EQADC */
2398/****************************************************************************/
2399 struct EQADC_tag {
2400 union {
2401 uint32_t R;
2402 struct {
2403 uint32_t:27;
2404 uint32_t ESSIE:2;
2405 uint32_t:1;
2406 uint32_t DBG:2;
2407 } B;
2408 } MCR; /* Module Configuration Register */
2409
2410 int32_t EQADC_reserved00;
2411
2412 union {
2413 uint32_t R;
2414 struct {
2415 uint32_t:6;
2416 uint32_t NMF:26;
2417 } B;
2418 } NMSFR; /* Null Message Send Format Register */
2419
2420 union {
2421 uint32_t R;
2422 struct {
2423 uint32_t:28;
2424 uint32_t DFL:4;
2425 } B;
2426 } ETDFR; /* External Trigger Digital Filter Register */
2427
2428 union {
2429 uint32_t R;
2430 struct {
2431 uint32_t CFPUSH:32;
2432 } B;
2433 } CFPR[6]; /* CFIFO Push Registers */
2434
2435 uint32_t eqadc_reserved1;
2436
2437 uint32_t eqadc_reserved2;
2438
2439 union {
2440 uint32_t R;
2441 struct {
2442 uint32_t:16;
2443 uint32_t RFPOP:16;
2444 } B;
2445 } RFPR[6]; /* Result FIFO Pop Registers */
2446
2447 uint32_t eqadc_reserved3;
2448
2449 uint32_t eqadc_reserved4;
2450
2451 union EQADC_CFCR_tag {
2452 uint16_t R;
2453 struct {
2454 uint16_t:5;
2455 uint16_t SSE:1;
2456 uint16_t CFINV:1;
2457 uint16_t:1;
2458 uint16_t MODE:4;
2459 uint16_t:4;
2460 } B;
2461 } CFCR[6]; /* CFIFO Control Registers */
2462
2463 uint32_t eqadc_reserved5;
2464
2465 union EQADC_IDCR_tag {
2466 uint16_t R;
2467 struct {
2468 uint16_t NCIE:1;
2469 uint16_t TORIE:1;
2470 uint16_t PIE:1;
2471 uint16_t EOQIE:1;
2472 uint16_t CFUIE:1;
2473 uint16_t:1;
2474 uint16_t CFFE:1;
2475 uint16_t CFFS:1;
2476 uint16_t:4;
2477 uint16_t RFOIE:1;
2478 uint16_t:1;
2479 uint16_t RFDE:1;
2480 uint16_t RFDS:1;
2481 } B;
2482 } IDCR[6]; /* Interrupt and DMA Control Registers */
2483
2484 uint32_t eqadc_reserved6;
2485
2486 union EQADC_FISR_tag {
2487 uint32_t R;
2488 struct {
2489 uint32_t NCF:1;
2490 uint32_t TORF:1;
2491 uint32_t PF:1;
2492 uint32_t EOQF:1;
2493 uint32_t CFUF:1;
2494 uint32_t SSS:1;
2495 uint32_t CFFF:1;
2496 uint32_t:5;
2497 uint32_t RFOF:1;
2498 uint32_t:1;
2499 uint32_t RFDF:1;
2500 uint32_t:1;
2501 uint32_t CFCTR:4;
2502 uint32_t TNXTPTR:4;
2503 uint32_t RFCTR:4;
2504 uint32_t POPNXTPTR:4;
2505 } B;
2506 } FISR[6]; /* FIFO and Interrupt Status Registers */
2507
2508 uint32_t eqadc_reserved7;
2509
2510 uint32_t eqadc_reserved8;
2511
2512 union {
2513 uint16_t R;
2514 struct {
2515 uint16_t:5;
2516 uint16_t TCCF:11;
2517 } B;
2518 } CFTCR[6]; /* CFIFO Transfer Counter Registers */
2519
2520 uint32_t eqadc_reserved9;
2521
2522 union {
2523 uint32_t R;
2524 struct {
2525 uint32_t CFS0:2;
2526 uint32_t CFS1:2;
2527 uint32_t CFS2:2;
2528 uint32_t CFS3:2;
2529 uint32_t CFS4:2;
2530 uint32_t CFS5:2;
2531 uint32_t:5;
2532 uint32_t LCFTCB0:4;
2533 uint32_t TC_LCFTCB0:11;
2534 } B;
2535 } CFSSR0; /* CFIFO Status Register 0 */
2536
2537 union {
2538 uint32_t R;
2539 struct {
2540 uint32_t CFS0:2;
2541 uint32_t CFS1:2;
2542 uint32_t CFS2:2;
2543 uint32_t CFS3:2;
2544 uint32_t CFS4:2;
2545 uint32_t CFS5:2;
2546 uint32_t:5;
2547 uint32_t LCFTCB1:4;
2548 uint32_t TC_LCFTCB1:11;
2549 } B;
2550 } CFSSR1; /* CFIFO Status Register 1 */
2551
2552 union {
2553 uint32_t R;
2554 struct {
2555 uint32_t CFS0:2;
2556 uint32_t CFS1:2;
2557 uint32_t CFS2:2;
2558 uint32_t CFS3:2;
2559 uint32_t CFS4:2;
2560 uint32_t CFS5:2;
2561 uint32_t:4;
2562 uint32_t ECBNI:1;
2563 uint32_t LCFTSSI:4;
2564 uint32_t TC_LCFTSSI:11;
2565 } B;
2566 } CFSSR2; /* CFIFO Status Register 2 */
2567
2568 union {
2569 uint32_t R;
2570 struct {
2571 uint32_t CFS0:2;
2572 uint32_t CFS1:2;
2573 uint32_t CFS2:2;
2574 uint32_t CFS3:2;
2575 uint32_t CFS4:2;
2576 uint32_t CFS5:2;
2577 uint32_t:20;
2578 } B;
2579 } CFSR;
2580
2581 uint32_t eqadc_reserved11;
2582
2583 union {
2584 uint32_t R;
2585 struct {
2586 uint32_t:21;
2587 uint32_t MDT:3;
2588 uint32_t:4;
2589 uint32_t BR:4;
2590 } B;
2591 } SSICR; /* SSI Control Register */
2592
2593 union {
2594 uint32_t R;
2595 struct {
2596 uint32_t RDV:1;
2597 uint32_t:5;
2598 uint32_t RDATA:26;
2599 } B;
2600 } SSIRDR; /* SSI Recieve Data Register */
2601
2602 uint32_t eqadc_reserved12[17];
2603
2604 struct {
2605 union {
2606 uint32_t R;
2607 struct {
2608 uint32_t:32;
2609 } B;
2610 } R[4];
2611
2612 uint32_t eqadc_reserved13[12];
2613
2614 } CF[6];
2615
2616 uint32_t eqadc_reserved14[32];
2617
2618 struct {
2619 union {
2620 uint32_t R;
2621 struct {
2622 uint32_t:32;
2623 } B;
2624 } R[4];
2625
2626 uint32_t eqadc_reserved15[12];
2627
2628 } RF[6];
2629
2630 };
2631
2632/* Message Formats for On-Chip ADC Operation
2633 */
2634 union EQADC_CONVERSION_COMMAND_tag {
2635 uint32_t R;
2636 struct {
2637 uint32_t EOQ:1;
2638 uint32_t PAUSE:1;
2639 uint32_t:3;
2640 uint32_t EB:1;
2641 uint32_t BN:1;
2642 uint32_t CAL:1;
2643 uint32_t MESSAGE_TAG:4;
2644 uint32_t LST:2;
2645 uint32_t TSR:1;
2646 uint32_t FMT:1;
2647 uint32_t CHANNEL_NUMBER:8;
2648 uint32_t:8;
2649 } B;
2650}; /* Conversion command */
2651
2652 union EQADC_WRITE_CONFIGURATION_COMMAND_tag {
2653 uint32_t R;
2654 struct {
2655 uint32_t EOQ:1;
2656 uint32_t PAUSE:1;
2657 uint32_t:3;
2658 uint32_t EB:1;
2659 uint32_t BN:1;
2660 uint32_t RW:1;
2661 uint32_t VALUE:16;
2662 uint32_t ADDR:8;
2663 } B;
2664}; /* Write configuration command */
2665
2666/****************************************************************************/
2667/* MODULE : DSPI */
2668/****************************************************************************/
2669 struct DSPI_tag {
2670 union DSPI_MCR_tag {
2671 uint32_t R;
2672 struct {
2673 uint32_t MSTR:1;
2674 uint32_t CONT_SCKE:1;
2675 uint32_t DCONF:2;
2676 uint32_t FRZ:1;
2677 uint32_t MTFE:1;
2678 uint32_t PCSSE:1;
2679 uint32_t ROOE:1;
2680 uint32_t:2;
2681 uint32_t PCSIS5:1;
2682 uint32_t PCSIS4:1;
2683 uint32_t PCSIS3:1;
2684 uint32_t PCSIS2:1;
2685 uint32_t PCSIS1:1;
2686 uint32_t PCSIS0:1;
2687 uint32_t DOZE:1;
2688 uint32_t MDIS:1;
2689 uint32_t DIS_TXF:1;
2690 uint32_t DIS_RXF:1;
2691 uint32_t CLR_TXF:1;
2692 uint32_t CLR_RXF:1;
2693 uint32_t SMPL_PT:2;
2694 uint32_t:7;
2695 uint32_t HALT:1;
2696 } B;
2697 } MCR; /* Module Configuration Register */
2698
2699 uint32_t dspi_reserved1;
2700
2701 union {
2702 uint32_t R;
2703 struct {
2704 uint32_t TCNT:16;
2705 uint32_t:16;
2706 } B;
2707 } TCR;
2708
2709 union DSPI_CTAR_tag {
2710 uint32_t R;
2711 struct {
2712 uint32_t DBR:1;
2713 uint32_t FMSZ:4;
2714 uint32_t CPOL:1;
2715 uint32_t CPHA:1;
2716 uint32_t LSBFE:1;
2717 uint32_t PCSSCK:2;
2718 uint32_t PASC:2;
2719 uint32_t PDT:2;
2720 uint32_t PBR:2;
2721 uint32_t CSSCK:4;
2722 uint32_t ASC:4;
2723 uint32_t DT:4;
2724 uint32_t BR:4;
2725 } B;
2726 } CTAR[8]; /* Clock and Transfer Attributes Registers */
2727
2728 union DSPI_SR_tag {
2729 uint32_t R;
2730 struct {
2731 uint32_t TCF:1;
2732 uint32_t TXRXS:1;
2733 uint32_t:1;
2734 uint32_t EOQF:1;
2735 uint32_t TFUF:1;
2736 uint32_t:1;
2737 uint32_t TFFF:1;
2738 uint32_t:5;
2739 uint32_t RFOF:1;
2740 uint32_t:1;
2741 uint32_t RFDF:1;
2742 uint32_t:1;
2743 uint32_t TXCTR:4;
2744 uint32_t TXNXTPTR:4;
2745 uint32_t RXCTR:4;
2746 uint32_t POPNXTPTR:4;
2747 } B;
2748 } SR; /* Status Register */
2749
2750 union DSPI_RSER_tag {
2751 uint32_t R;
2752 struct {
2753 uint32_t TCFRE:1;
2754 uint32_t:2;
2755 uint32_t EOQFRE:1;
2756 uint32_t TFUFRE:1;
2757 uint32_t:1;
2758 uint32_t TFFFRE:1;
2759 uint32_t TFFFDIRS:1;
2760 uint32_t:4;
2761 uint32_t RFOFRE:1;
2762 uint32_t:1;
2763 uint32_t RFDFRE:1;
2764 uint32_t RFDFDIRS:1;
2765 uint32_t:16;
2766 } B;
2767 } RSER; /* DMA/Interrupt Request Select and Enable Register */
2768
2769 union DSPI_PUSHR_tag {
2770 uint32_t R;
2771 struct {
2772 uint32_t CONT:1;
2773 uint32_t CTAS:3;
2774 uint32_t EOQ:1;
2775 uint32_t CTCNT:1;
2776 uint32_t:4;
2777 uint32_t PCS5:1;
2778 uint32_t PCS4:1;
2779 uint32_t PCS3:1;
2780 uint32_t PCS2:1;
2781 uint32_t PCS1:1;
2782 uint32_t PCS0:1;
2783 uint32_t TXDATA:16;
2784 } B;
2785 } PUSHR; /* PUSH TX FIFO Register */
2786
2787 union DSPI_POPR_tag {
2788 uint32_t R;
2789 struct {
2790 uint32_t:16;
2791 uint32_t RXDATA:16;
2792 } B;
2793 } POPR; /* POP RX FIFO Register */
2794
2795 union {
2796 uint32_t R;
2797 struct {
2798 uint32_t TXCMD:16;
2799 uint32_t TXDATA:16;
2800 } B;
2801 } TXFR[4]; /* Transmit FIFO Registers */
2802
2803 uint32_t DSPI_reserved_txf[12];
2804
2805 union {
2806 uint32_t R;
2807 struct {
2808 uint32_t:16;
2809 uint32_t RXDATA:16;
2810 } B;
2811 } RXFR[4]; /* Transmit FIFO Registers */
2812
2813 uint32_t DSPI_reserved_rxf[12];
2814
2815 union {
2816 uint32_t R;
2817 struct {
2818 uint32_t MTOE:1;
2819 uint32_t:1;
2820 uint32_t MTOCNT:6;
2821 uint32_t:4;
2822 uint32_t TXSS:1;
2823 uint32_t TPOL:1;
2824 uint32_t TRRE:1;
2825 uint32_t CID:1;
2826 uint32_t DCONT:1;
2827 uint32_t DSICTAS:3;
2828 uint32_t:6;
2829 uint32_t DPCS5:1;
2830 uint32_t DPCS4:1;
2831 uint32_t DPCS3:1;
2832 uint32_t DPCS2:1;
2833 uint32_t DPCS1:1;
2834 uint32_t DPCS0:1;
2835 } B;
2836 } DSICR; /* DSI Configuration Register */
2837
2838 union {
2839 uint32_t R;
2840 struct {
2841 uint32_t:16;
2842 uint32_t SER_DATA:16;
2843 } B;
2844 } SDR; /* DSI Serialization Data Register */
2845
2846 union {
2847 uint32_t R;
2848 struct {
2849 uint32_t:16;
2850 uint32_t ASER_DATA:16;
2851 } B;
2852 } ASDR; /* DSI Alternate Serialization Data Register */
2853
2854 union {
2855 uint32_t R;
2856 struct {
2857 uint32_t:16;
2858 uint32_t COMP_DATA:16;
2859 } B;
2860 } COMPR; /* DSI Transmit Comparison Register */
2861
2862 union {
2863 uint32_t R;
2864 struct {
2865 uint32_t:16;
2866 uint32_t DESER_DATA:16;
2867 } B;
2868 } DDR; /* DSI deserialization Data Register */
2869
2870 };
2871/****************************************************************************/
2872/* MODULE : eSCI */
2873/****************************************************************************/
2874 struct ESCI_tag {
2875 union ESCI_CR1_tag {
2876 uint32_t R;
2877 struct {
2878 uint32_t:3;
2879 uint32_t SBR:13;
2880 uint32_t LOOPS:1;
2881 uint32_t SCISDOZ:1;
2882 uint32_t RSRC:1;
2883 uint32_t M:1;
2884 uint32_t WAKE:1;
2885 uint32_t ILT:1;
2886 uint32_t PE:1;
2887 uint32_t PT:1;
2888 uint32_t TIE:1;
2889 uint32_t TCIE:1;
2890 uint32_t RIE:1;
2891 uint32_t ILIE:1;
2892 uint32_t TE:1;
2893 uint32_t RE:1;
2894 uint32_t RWU:1;
2895 uint32_t SBK:1;
2896 } B;
2897 } CR1; /* Control Register 1 */
2898
2899 union ESCI_CR2_tag {
2900 uint16_t R;
2901 struct {
2902 uint16_t MDIS:1;
2903 uint16_t FBR:1;
2904 uint16_t BSTP:1;
2905 uint16_t IEBERR:1;
2906 uint16_t RXDMA:1;
2907 uint16_t TXDMA:1;
2908 uint16_t BRK13:1;
2909 uint16_t:1;
2910 uint16_t BESM13:1;
2911 uint16_t SBSTP:1;
2912 uint16_t:2;
2913 uint16_t ORIE:1;
2914 uint16_t NFIE:1;
2915 uint16_t FEIE:1;
2916 uint16_t PFIE:1;
2917 } B;
2918 } CR2; /* Control Register 2 */
2919
2920 union ESCI_DR_tag {
2921 uint16_t R;
2922 struct {
2923 uint16_t R8:1;
2924 uint16_t T8:1;
2925 uint16_t:6;
2926 uint8_t D;
2927 } B;
2928 } DR; /* Data Register */
2929
2930 union ESCI_SR_tag {
2931 uint32_t R;
2932 struct {
2933 uint32_t TDRE:1;
2934 uint32_t TC:1;
2935 uint32_t RDRF:1;
2936 uint32_t IDLE:1;
2937 uint32_t OR:1;
2938 uint32_t NF:1;
2939 uint32_t FE:1;
2940 uint32_t PF:1;
2941 uint32_t:3;
2942 uint32_t BERR:1;
2943 uint32_t:3;
2944 uint32_t RAF:1;
2945 uint32_t RXRDY:1;
2946 uint32_t TXRDY:1;
2947 uint32_t LWAKE:1;
2948 uint32_t STO:1;
2949 uint32_t PBERR:1;
2950 uint32_t CERR:1;
2951 uint32_t CKERR:1;
2952 uint32_t FRC:1;
2953 uint32_t:7;
2954 uint32_t OVFL:1;
2955 } B;
2956 } SR; /* Status Register */
2957
2958 union {
2959 uint32_t R;
2960 struct {
2961 uint32_t LRES:1;
2962 uint32_t WU:1;
2963 uint32_t WUD0:1;
2964 uint32_t WUD1:1;
2965 uint32_t LDBG:1;
2966 uint32_t DSF:1;
2967 uint32_t PRTY:1;
2968 uint32_t LIN:1;
2969 uint32_t RXIE:1;
2970 uint32_t TXIE:1;
2971 uint32_t WUIE:1;
2972 uint32_t STIE:1;
2973 uint32_t PBIE:1;
2974 uint32_t CIE:1;
2975 uint32_t CKIE:1;
2976 uint32_t FCIE:1;
2977 uint32_t:7;
2978 uint32_t OFIE:1;
2979 uint32_t:8;
2980 } B;
2981 } LCR; /* LIN Control Register */
2982
2983 union {
2984 uint32_t R;
2985 } LTR; /* LIN Transmit Register */
2986
2987 union {
2988 uint32_t R;
2989 } LRR; /* LIN Recieve Register */
2990
2991 union {
2992 uint32_t R;
2993 } LPR; /* LIN CRC Polynom Register */
2994
2995 };
2996/****************************************************************************/
2997/* MODULE : FlexCAN */
2998/****************************************************************************/
2999 struct FLEXCAN2_tag {
3000 union {
3001 uint32_t R;
3002 struct {
3003 uint32_t MDIS:1;
3004 uint32_t FRZ:1;
3005 uint32_t:1;
3006 uint32_t HALT:1;
3007 uint32_t NOTRDY:1;
3008 uint32_t:1;
3009 uint32_t SOFTRST:1;
3010 uint32_t FRZACK:1;
3011 uint32_t:1;
3012 uint32_t:1;
3013
3014 uint32_t:1;
3015
3016 uint32_t MDISACK:1;
3017 uint32_t:1;
3018 uint32_t:1;
3019
3020 uint32_t:12;
3021
3022 uint32_t MAXMB:6;
3023 } B;
3024 } MCR; /* Module Configuration Register */
3025
3026 union {
3027 uint32_t R;
3028 struct {
3029 uint32_t PRESDIV:8;
3030 uint32_t RJW:2;
3031 uint32_t PSEG1:3;
3032 uint32_t PSEG2:3;
3033 uint32_t BOFFMSK:1;
3034 uint32_t ERRMSK:1;
3035 uint32_t CLKSRC:1;
3036 uint32_t LPB:1;
3037
3038 uint32_t:4;
3039
3040 uint32_t SMP:1;
3041 uint32_t BOFFREC:1;
3042 uint32_t TSYN:1;
3043 uint32_t LBUF:1;
3044 uint32_t LOM:1;
3045 uint32_t PROPSEG:3;
3046 } B;
3047 } CR; /* Control Register */
3048
3049 union {
3050 uint32_t R;
3051 } TIMER; /* Free Running Timer */
3052 int32_t FLEXCAN_reserved00;
3053
3054 union {
3055 uint32_t R;
3056 struct {
3057 uint32_t:3;
3058 uint32_t MI:29;
3059 } B;
3060 } RXGMASK; /* RX Global Mask */
3061
3062 union {
3063 uint32_t R;
3064 struct {
3065 uint32_t:3;
3066 uint32_t MI:29;
3067 } B;
3068 } RX14MASK; /* RX 14 Mask */
3069
3070 union {
3071 uint32_t R;
3072 struct {
3073 uint32_t:3;
3074 uint32_t MI:29;
3075 } B;
3076 } RX15MASK; /* RX 15 Mask */
3077
3078 union {
3079 uint32_t R;
3080 struct {
3081 uint32_t:16;
3082 uint32_t RXECNT:8;
3083 uint32_t TXECNT:8;
3084 } B;
3085 } ECR; /* Error Counter Register */
3086
3087 union {
3088 uint32_t R;
3089 struct {
3090 uint32_t:14;
3091
3092 uint32_t:2;
3093
3094 uint32_t BIT1ERR:1;
3095 uint32_t BIT0ERR:1;
3096 uint32_t ACKERR:1;
3097 uint32_t CRCERR:1;
3098 uint32_t FRMERR:1;
3099 uint32_t STFERR:1;
3100 uint32_t TXWRN:1;
3101 uint32_t RXWRN:1;
3102 uint32_t IDLE:1;
3103 uint32_t TXRX:1;
3104 uint32_t FLTCONF:2;
3105 uint32_t:1;
3106 uint32_t BOFFINT:1;
3107 uint32_t ERRINT:1;
3108 uint32_t:1;
3109 } B;
3110 } ESR; /* Error and Status Register */
3111
3112 union {
3113 uint32_t R;
3114 struct {
3115 uint32_t BUF63M:1;
3116 uint32_t BUF62M:1;
3117 uint32_t BUF61M:1;
3118 uint32_t BUF60M:1;
3119 uint32_t BUF59M:1;
3120 uint32_t BUF58M:1;
3121 uint32_t BUF57M:1;
3122 uint32_t BUF56M:1;
3123 uint32_t BUF55M:1;
3124 uint32_t BUF54M:1;
3125 uint32_t BUF53M:1;
3126 uint32_t BUF52M:1;
3127 uint32_t BUF51M:1;
3128 uint32_t BUF50M:1;
3129 uint32_t BUF49M:1;
3130 uint32_t BUF48M:1;
3131 uint32_t BUF47M:1;
3132 uint32_t BUF46M:1;
3133 uint32_t BUF45M:1;
3134 uint32_t BUF44M:1;
3135 uint32_t BUF43M:1;
3136 uint32_t BUF42M:1;
3137 uint32_t BUF41M:1;
3138 uint32_t BUF40M:1;
3139 uint32_t BUF39M:1;
3140 uint32_t BUF38M:1;
3141 uint32_t BUF37M:1;
3142 uint32_t BUF36M:1;
3143 uint32_t BUF35M:1;
3144 uint32_t BUF34M:1;
3145 uint32_t BUF33M:1;
3146 uint32_t BUF32M:1;
3147 } B;
3148 } IMRH; /* Interruput Masks Register */
3149
3150 union {
3151 uint32_t R;
3152 struct {
3153 uint32_t BUF31M:1;
3154 uint32_t BUF30M:1;
3155 uint32_t BUF29M:1;
3156 uint32_t BUF28M:1;
3157 uint32_t BUF27M:1;
3158 uint32_t BUF26M:1;
3159 uint32_t BUF25M:1;
3160 uint32_t BUF24M:1;
3161 uint32_t BUF23M:1;
3162 uint32_t BUF22M:1;
3163 uint32_t BUF21M:1;
3164 uint32_t BUF20M:1;
3165 uint32_t BUF19M:1;
3166 uint32_t BUF18M:1;
3167 uint32_t BUF17M:1;
3168 uint32_t BUF16M:1;
3169 uint32_t BUF15M:1;
3170 uint32_t BUF14M:1;
3171 uint32_t BUF13M:1;
3172 uint32_t BUF12M:1;
3173 uint32_t BUF11M:1;
3174 uint32_t BUF10M:1;
3175 uint32_t BUF09M:1;
3176 uint32_t BUF08M:1;
3177 uint32_t BUF07M:1;
3178 uint32_t BUF06M:1;
3179 uint32_t BUF05M:1;
3180 uint32_t BUF04M:1;
3181 uint32_t BUF03M:1;
3182 uint32_t BUF02M:1;
3183 uint32_t BUF01M:1;
3184 uint32_t BUF00M:1;
3185 } B;
3186 } IMRL; /* Interruput Masks Register */
3187
3188 union {
3189 uint32_t R;
3190 struct {
3191 uint32_t BUF63I:1;
3192 uint32_t BUF62I:1;
3193 uint32_t BUF61I:1;
3194 uint32_t BUF60I:1;
3195 uint32_t BUF59I:1;
3196 uint32_t BUF58I:1;
3197 uint32_t BUF57I:1;
3198 uint32_t BUF56I:1;
3199 uint32_t BUF55I:1;
3200 uint32_t BUF54I:1;
3201 uint32_t BUF53I:1;
3202 uint32_t BUF52I:1;
3203 uint32_t BUF51I:1;
3204 uint32_t BUF50I:1;
3205 uint32_t BUF49I:1;
3206 uint32_t BUF48I:1;
3207 uint32_t BUF47I:1;
3208 uint32_t BUF46I:1;
3209 uint32_t BUF45I:1;
3210 uint32_t BUF44I:1;
3211 uint32_t BUF43I:1;
3212 uint32_t BUF42I:1;
3213 uint32_t BUF41I:1;
3214 uint32_t BUF40I:1;
3215 uint32_t BUF39I:1;
3216 uint32_t BUF38I:1;
3217 uint32_t BUF37I:1;
3218 uint32_t BUF36I:1;
3219 uint32_t BUF35I:1;
3220 uint32_t BUF34I:1;
3221 uint32_t BUF33I:1;
3222 uint32_t BUF32I:1;
3223 } B;
3224 } IFRH; /* Interruput Flag Register */
3225
3226 union {
3227 uint32_t R;
3228 struct {
3229 uint32_t BUF31I:1;
3230 uint32_t BUF30I:1;
3231 uint32_t BUF29I:1;
3232 uint32_t BUF28I:1;
3233 uint32_t BUF27I:1;
3234 uint32_t BUF26I:1;
3235 uint32_t BUF25I:1;
3236 uint32_t BUF24I:1;
3237 uint32_t BUF23I:1;
3238 uint32_t BUF22I:1;
3239 uint32_t BUF21I:1;
3240 uint32_t BUF20I:1;
3241 uint32_t BUF19I:1;
3242 uint32_t BUF18I:1;
3243 uint32_t BUF17I:1;
3244 uint32_t BUF16I:1;
3245 uint32_t BUF15I:1;
3246 uint32_t BUF14I:1;
3247 uint32_t BUF13I:1;
3248 uint32_t BUF12I:1;
3249 uint32_t BUF11I:1;
3250 uint32_t BUF10I:1;
3251 uint32_t BUF09I:1;
3252 uint32_t BUF08I:1;
3253 uint32_t BUF07I:1;
3254 uint32_t BUF06I:1;
3255 uint32_t BUF05I:1;
3256 uint32_t BUF04I:1;
3257 uint32_t BUF03I:1;
3258 uint32_t BUF02I:1;
3259 uint32_t BUF01I:1;
3260 uint32_t BUF00I:1;
3261 } B;
3262 } IFRL; /* Interruput Flag Register */
3263
3264 uint32_t flexcan2_reserved2[19];
3265
3266 struct canbuf_t {
3267 union {
3268 uint32_t R;
3269 struct {
3270 uint32_t:4;
3271 uint32_t CODE:4;
3272 uint32_t:1;
3273 uint32_t SRR:1;
3274 uint32_t IDE:1;
3275 uint32_t RTR:1;
3276 uint32_t LENGTH:4;
3277 uint32_t TIMESTAMP:16;
3278 } B;
3279 } CS;
3280
3281 union {
3282 uint32_t R;
3283 struct {
3284 uint32_t:3;
3285 uint32_t STD_ID:11;
3286 uint32_t EXT_ID:18;
3287 } B;
3288 } ID;
3289
3290 union {
3291 uint8_t B[8]; /* Data buffer in Bytes (8 bits) */
3292 uint16_t H[4]; /* Data buffer in Half-words (16 bits) */
3293 uint32_t W[2]; /* Data buffer in words (32 bits) */
3294 uint32_t R[2]; /* Data buffer in words (32 bits) */
3295 } DATA;
3296
3297 } BUF[64];
3298 };
3299
3300/* Define memories */
3301
3302#define SRAM_START 0x40000000
3303#define SRAM_SIZE 0x10000
3304#define SRAM_END 0x4000FFFF
3305
3306#define FLASH_START 0x0
3307#define FLASH_SIZE 0x200000
3308#define FLASH_END 0x1FFFFF
3309
3310/* Define instances of modules */
3311#define PBRIDGE_A (*(volatile struct PBRIDGE_A_tag *) 0xC3F00000)
3312#define FMPLL (*(volatile struct FMPLL_tag *) 0xC3F80000)
3313#define EBI (*(volatile struct EBI_tag *) 0xC3F84000)
3314#define FLASH (*(volatile struct FLASH_tag *) 0xC3F88000)
3315#define SIU (*(volatile struct SIU_tag *) 0xC3F90000)
3316
3317#define EMIOS (*(volatile struct EMIOS_tag *) 0xC3FA0000)
3318#define ETPU (*(volatile struct ETPU_tag *) 0xC3FC0000)
3319#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000)
3320#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000)
3321#define ETPU_DATA_RAM_END 0xC3FC8BFC
3322#define CODE_RAM (*( uint32_t *) 0xC3FD0000)
3323#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000)
3324
3325#define PBRIDGE_B (*(volatile struct PBRIDGE_B_tag *) 0xFFF00000)
3326#define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000)
3327#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000)
3328#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000)
3329#define INTC (*(volatile struct INTC_tag *) 0xFFF48000)
3330
3331#define EQADC (*(volatile struct EQADC_tag *) 0xFFF80000)
3332
3333#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000)
3334#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000)
3335#define DSPI_C (*(volatile struct DSPI_tag *) 0xFFF98000)
3336#define DSPI_D (*(volatile struct DSPI_tag *) 0xFFF9C000)
3337
3338#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFB0000)
3339#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFB4000)
3340
3341#define CAN_A (*(volatile struct FLEXCAN2_tag *) 0xFFFC0000)
3342#define CAN_B (*(volatile struct FLEXCAN2_tag *) 0xFFFC4000)
3343#define CAN_C (*(volatile struct FLEXCAN2_tag *) 0xFFFC8000)
3344
3345#ifdef __MWERKS__
3346#pragma pop
3347#endif
3348
3349#ifdef __cplusplus
3350}
3351#endif
3352#endif /* ASM */
3353#endif /* ifdef _MPC5554_H */
3354/*********************************************************************
3355 *
3356 * Copyright:
3357 * Freescale Semiconductor, INC. All Rights Reserved.
3358 * You are hereby granted a copyright license to use, modify, and
3359 * distribute the SOFTWARE so long as this entire notice is
3360 * retained without alteration in any modified and/or redistributed
3361 * versions, and that such modified versions are clearly identified
3362 * as such. No licenses are granted by implication, estoppel or
3363 * otherwise under any patents or trademarks of Freescale
3364 * Semiconductor, Inc. This software is provided on an "AS IS"
3365 * basis and without warranty.
3366 *
3367 * To the maximum extent permitted by applicable law, Freescale
3368 * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
3369 * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
3370 * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
3371 * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
3372 * AND ANY ACCOMPANYING WRITTEN MATERIALS.
3373 *
3374 * To the maximum extent permitted by applicable law, IN NO EVENT
3375 * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
3376 * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
3377 * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
3378 * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
3379 *
3380 * Freescale Semiconductor assumes no responsibility for the
3381 * maintenance and support of this software
3382 *
3383 ********************************************************************/
regs-edma.h
DSPI_tag
Definition: fsl-mpc551x.h:244
EBI_CAL_CS_tag
Definition: fsl-mpc551x.h:479
EBI_CS_tag
Definition: fsl-mpc551x.h:447
EBI_tag
Definition: fsl-mpc551x.h:483
ECSM_tag
Definition: fsl-mpc555x.h:2179
EMIOS_tag
Definition: fsl-mpc551x.h:531
EQADC_tag
Definition: fsl-mpc551x.h:716
ESCI_tag
Definition: fsl-mpc551x.h:899
ETPU_tag
Definition: fsl-mpc555x.h:1136
FLASH_tag
Definition: fsl-mpc551x.h:1027
FLEXCAN2_tag::canbuf_t
Definition: fsl-mpc555x.h:3266
FLEXCAN2_tag
Definition: fsl-mpc555x.h:2999
FMPLL_tag
Definition: fsl-mpc551x.h:1484
INTC_tag
Definition: fsl-mpc551x.h:1603
PBRIDGE_A_tag
Definition: fsl-mpc555x.h:124
PBRIDGE_B_tag
Definition: fsl-mpc555x.h:236
SIU_tag
Definition: fsl-mpc551x.h:2221
XBAR_tag
Definition: fsl-mpc555x.h:1982
DSPI_CTAR_tag
Definition: fsl-mpc564xL.h:16586
DSPI_MCR_tag
Definition: fsl-mpc564xL.h:16541
DSPI_POPR_tag
Definition: fsl-mpc564xL.h:16698
DSPI_PUSHR_tag
Definition: fsl-mpc564xL.h:16678
DSPI_RSER_tag
Definition: fsl-mpc564xL.h:16627
DSPI_SR_tag
Definition: fsl-mpc564xL.h:16605
EQADC_CONVERSION_COMMAND_tag
Definition: fsl-mpc555x.h:2634
EQADC_WRITE_CONFIGURATION_COMMAND_tag
Definition: fsl-mpc555x.h:2652
EQADC_tag::EQADC_CFCR_tag
Definition: fsl-mpc555x.h:2451
EQADC_tag::EQADC_FISR_tag
Definition: fsl-mpc555x.h:2486
EQADC_tag::EQADC_IDCR_tag
Definition: fsl-mpc555x.h:2465
FMPLL_tag::FMPLL_SYNCR_tag
Definition: fsl-mpc555x.h:404
FMPLL_tag::FMPLL_SYNSR_tag
Definition: fsl-mpc551x.h:1488
SIU_PCR_tag
Definition: fsl-mpc564xL.h:966