RTEMS: bsps/arm/smdk2410/include/s3c2410.h Source File

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s3c2410.h
1/************************************************
2 * NAME : s3c2410.h
3 * Version : 3.7.2002
4 *
5 * Based on 24x.h for the Samsung Development Board
6 ************************************************/
7
8#ifndef S3C2410_H_
9#define S3C2410_H_
10
11/* to be used in assembly code */
12#define rINTOFFSET_ADDR 0x4A000014
13/* Memory control */
14#define rBWSCON (*(volatile unsigned *)0x48000000)
15#define rBANKCON0 (*(volatile unsigned *)0x48000004)
16#define rBANKCON1 (*(volatile unsigned *)0x48000008)
17#define rBANKCON2 (*(volatile unsigned *)0x4800000C)
18#define rBANKCON3 (*(volatile unsigned *)0x48000010)
19#define rBANKCON4 (*(volatile unsigned *)0x48000014)
20#define rBANKCON5 (*(volatile unsigned *)0x48000018)
21#define rBANKCON6 (*(volatile unsigned *)0x4800001C)
22#define rBANKCON7 (*(volatile unsigned *)0x48000020)
23#define rREFRESH (*(volatile unsigned *)0x48000024)
24#define rBANKSIZE (*(volatile unsigned *)0x48000028)
25#define rMRSRB6 (*(volatile unsigned *)0x4800002C)
26#define rMRSRB7 (*(volatile unsigned *)0x48000030)
27
28/* USB Host Controller */
29#define rHcRevision (*(volatile unsigned *)0x49000000)
30#define rHcControl (*(volatile unsigned *)0x49000004)
31#define rHcCommonStatus (*(volatile unsigned *)0x49000008)
32#define rHcInterruptStatus (*(volatile unsigned *)0x4900000C)
33#define rHcInterruptEnable (*(volatile unsigned *)0x49000010)
34#define rHcInterruptDisable (*(volatile unsigned *)0x49000014)
35#define rHcHCCA (*(volatile unsigned *)0x49000018)
36#define rHcPeriodCuttendED (*(volatile unsigned *)0x4900001C)
37#define rHcControlHeadED (*(volatile unsigned *)0x49000020)
38#define rHcControlCurrentED (*(volatile unsigned *)0x49000024)
39#define rHcBulkHeadED (*(volatile unsigned *)0x49000028)
40#define rHcBuldCurrentED (*(volatile unsigned *)0x4900002C)
41#define rHcDoneHead (*(volatile unsigned *)0x49000030)
42#define rHcRmInterval (*(volatile unsigned *)0x49000034)
43#define rHcFmRemaining (*(volatile unsigned *)0x49000038)
44#define rHcFmNumber (*(volatile unsigned *)0x4900003C)
45#define rHcPeriodicStart (*(volatile unsigned *)0x49000040)
46#define rHcLSThreshold (*(volatile unsigned *)0x49000044)
47#define rHcRhDescriptorA (*(volatile unsigned *)0x49000048)
48#define rHcRhDescriptorB (*(volatile unsigned *)0x4900004C)
49#define rHcRhStatus (*(volatile unsigned *)0x49000050)
50#define rHcRhPortStatus1 (*(volatile unsigned *)0x49000054)
51#define rHcRhPortStatus2 (*(volatile unsigned *)0x49000058)
52
53/* INTERRUPT */
54#define rSRCPND (*(volatile unsigned *)0x4A000000)
55#define rINTMOD (*(volatile unsigned *)0x4A000004)
56#define rINTMSK (*(volatile unsigned *)0x4A000008)
57#define rPRIORITY (*(volatile unsigned *)0x4A00000C)
58#define rINTPND (*(volatile unsigned *)0x4A000010)
59#define rINTOFFSET (*(volatile unsigned *)0x4A000014)
60#define rSUBSRCPND (*(volatile unsigned *)0x4A000018)
61#define rINTSUBMSK (*(volatile unsigned *)0x4A00001c)
62
63
64/* DMA */
65#define rDISRC0 (*(volatile unsigned *)0x4B000000)
66#define rDISRCC0 (*(volatile unsigned *)0x4B000004)
67#define rDIDST0 (*(volatile unsigned *)0x4B000008)
68#define rDIDSTC0 (*(volatile unsigned *)0x4B00000C)
69#define rDCON0 (*(volatile unsigned *)0x4B000010)
70#define rDSTAT0 (*(volatile unsigned *)0x4B000014)
71#define rDCSRC0 (*(volatile unsigned *)0x4B000018)
72#define rDCDST0 (*(volatile unsigned *)0x4B00001C)
73#define rDMASKTRIG0 (*(volatile unsigned *)0x4B000020)
74#define rDISRC1 (*(volatile unsigned *)0x4B000040)
75#define rDISRCC1 (*(volatile unsigned *)0x4B000044)
76#define rDIDST1 (*(volatile unsigned *)0x4B000048)
77#define rDIDSTC1 (*(volatile unsigned *)0x4B00004C)
78#define rDCON1 (*(volatile unsigned *)0x4B000050)
79#define rDSTAT1 (*(volatile unsigned *)0x4B000054)
80#define rDCSRC1 (*(volatile unsigned *)0x4B000058)
81#define rDCDST1 (*(volatile unsigned *)0x4B00005C)
82#define rDMASKTRIG1 (*(volatile unsigned *)0x4B000060)
83#define rDISRC2 (*(volatile unsigned *)0x4B000080)
84#define rDISRCC2 (*(volatile unsigned *)0x4B000084)
85#define rDIDST2 (*(volatile unsigned *)0x4B000088)
86#define rDIDSTC2 (*(volatile unsigned *)0x4B00008C)
87#define rDCON2 (*(volatile unsigned *)0x4B000090)
88#define rDSTAT2 (*(volatile unsigned *)0x4B000094)
89#define rDCSRC2 (*(volatile unsigned *)0x4B000098)
90#define rDCDST2 (*(volatile unsigned *)0x4B00009C)
91#define rDMASKTRIG2 (*(volatile unsigned *)0x4B0000A0)
92#define rDISRC3 (*(volatile unsigned *)0x4B0000C0)
93#define rDISRCC3 (*(volatile unsigned *)0x4B0000C4)
94#define rDIDST3 (*(volatile unsigned *)0x4B0000C8)
95#define rDIDSTC3 (*(volatile unsigned *)0x4B0000CC)
96#define rDCON3 (*(volatile unsigned *)0x4B0000D0)
97#define rDSTAT3 (*(volatile unsigned *)0x4B0000D4)
98#define rDCSRC3 (*(volatile unsigned *)0x4B0000D8)
99#define rDCDST3 (*(volatile unsigned *)0x4B0000DC)
100#define rDMASKTRIG3 (*(volatile unsigned *)0x4B0000E0)
101
102
103/* CLOCK & POWER MANAGEMENT */
104#define rLOCKTIME (*(volatile unsigned *)0x4C000000)
105#define rMPLLCON (*(volatile unsigned *)0x4C000004)
106#define rUPLLCON (*(volatile unsigned *)0x4C000008)
107#define rCLKCON (*(volatile unsigned *)0x4C00000C)
108#define rCLKSLOW (*(volatile unsigned *)0x4C000010)
109#define rCLKDIVN (*(volatile unsigned *)0x4C000014)
110
111
112/* LCD CONTROLLER */
113#define rLCDCON1 (*(volatile unsigned *)0x4D000000)
114#define rLCDCON2 (*(volatile unsigned *)0x4D000004)
115#define rLCDCON3 (*(volatile unsigned *)0x4D000008)
116#define rLCDCON4 (*(volatile unsigned *)0x4D00000C)
117#define rLCDCON5 (*(volatile unsigned *)0x4D000010)
118#define rLCDSADDR1 (*(volatile unsigned *)0x4D000014)
119#define rLCDSADDR2 (*(volatile unsigned *)0x4D000018)
120#define rLCDSADDR3 (*(volatile unsigned *)0x4D00001C)
121#define rREDLUT (*(volatile unsigned *)0x4D000020)
122#define rGREENLUT (*(volatile unsigned *)0x4D000024)
123#define rBLUELUT (*(volatile unsigned *)0x4D000028)
124#define rREDLUT (*(volatile unsigned *)0x4D000020)
125#define rGREENLUT (*(volatile unsigned *)0x4D000024)
126#define rBLUELUT (*(volatile unsigned *)0x4D000028)
127#define rDITHMODE (*(volatile unsigned *)0x4D00004C)
128#define rTPAL (*(volatile unsigned *)0x4D000050)
129#define rLCDINTPND (*(volatile unsigned *)0x4D000054)
130#define rLCDSRCPND (*(volatile unsigned *)0x4D000058)
131#define rLCDINTMSK (*(volatile unsigned *)0x4D00005C)
132#define rTCONSEL (*(volatile unsigned *)0x4D000060)
133#define PALETTE 0x4d000400
134
135/* NAND Flash */
136#define rNFCONF (*(volatile unsigned *)0x4E000000)
137#define rNFCMD (*(volatile unsigned *)0x4E000004)
138#define rNFADDR (*(volatile unsigned *)0x4E000008)
139#define rNFDATA (*(volatile unsigned *)0x4E00000C)
140#define rNFSTAT (*(volatile unsigned *)0x4E000010)
141#define rNFECC (*(volatile unsigned *)0x4E000014)
142
143/* UART */
144#define rULCON0 (*(volatile unsigned char *)0x50000000)
145#define rUCON0 (*(volatile unsigned short *)0x50000004)
146#define rUFCON0 (*(volatile unsigned char *)0x50000008)
147#define rUMCON0 (*(volatile unsigned char *)0x5000000C)
148#define rUTRSTAT0 (*(volatile unsigned char *)0x50000010)
149#define rUERSTAT0 (*(volatile unsigned char *)0x50000014)
150#define rUFSTAT0 (*(volatile unsigned short *)0x50000018)
151#define rUMSTAT0 (*(volatile unsigned char *)0x5000001C)
152#define rUBRDIV0 (*(volatile unsigned short *)0x50000028)
153
154#define rULCON1 (*(volatile unsigned char *)0x50004000)
155#define rUCON1 (*(volatile unsigned short *)0x50004004)
156#define rUFCON1 (*(volatile unsigned char *)0x50004008)
157#define rUMCON1 (*(volatile unsigned char *)0x5000400C)
158#define rUTRSTAT1 (*(volatile unsigned char *)0x50004010)
159#define rUERSTAT1 (*(volatile unsigned char *)0x50004014)
160#define rUFSTAT1 (*(volatile unsigned short *)0x50004018)
161#define rUMSTAT1 (*(volatile unsigned char *)0x5000401C)
162#define rUBRDIV1 (*(volatile unsigned short *)0x50004028)
163
164#define rULCON2 (*(volatile unsigned char *)0x50008000)
165#define rUCON2 (*(volatile unsigned short *)0x50008004)
166#define rUFCON2 (*(volatile unsigned char *)0x50008008)
167#define rUTRSTAT2 (*(volatile unsigned char *)0x50008010)
168#define rUERSTAT2 (*(volatile unsigned char *)0x50008014)
169#define rUFSTAT2 (*(volatile unsigned short *)0x50008018)
170#define rUBRDIV2 (*(volatile unsigned short *)0x50008028)
171
172#ifdef __BIG_ENDIAN
173#define rUTXH0 (*(volatile unsigned char *)0x50000023)
174#define rURXH0 (*(volatile unsigned char *)0x50000027)
175#define rUTXH1 (*(volatile unsigned char *)0x50004023)
176#define rURXH1 (*(volatile unsigned char *)0x50004027)
177#define rUTXH2 (*(volatile unsigned char *)0x50008023)
178#define rURXH2 (*(volatile unsigned char *)0x50008027)
179
180#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
181#define RdURXH0() (*(volatile unsigned char *)0x50000027)
182#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
183#define RdURXH1() (*(volatile unsigned char *)0x50004027)
184#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
185#define RdURXH2() (*(volatile unsigned char *)0x50008027)
186
187#define UTXH0 (0x50000020+3) /* byte_access address by DMA */
188#define URXH0 (0x50000024+3)
189#define UTXH1 (0x50004020+3)
190#define URXH1 (0x50004024+3)
191#define UTXH2 (0x50008020+3)
192#define URXH2 (0x50008024+3)
193
194#else /* Little Endian */
195#define rUTXH0 (*(volatile unsigned char *)0x50000020)
196#define rURXH0 (*(volatile unsigned char *)0x50000024)
197#define rUTXH1 (*(volatile unsigned char *)0x50004020)
198#define rURXH1 (*(volatile unsigned char *)0x50004024)
199#define rUTXH2 (*(volatile unsigned char *)0x50008020)
200#define rURXH2 (*(volatile unsigned char *)0x50008024)
201
202#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
203#define RdURXH0() (*(volatile unsigned char *)0x50000024)
204#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
205#define RdURXH1() (*(volatile unsigned char *)0x50004024)
206#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
207#define RdURXH2() (*(volatile unsigned char *)0x50008024)
208
209#define UTXH0 (0x50000020)
210#define URXH0 (0x50000024)
211#define UTXH1 (0x50004020)
212#define URXH1 (0x50004024)
213#define UTXH2 (0x50008020)
214#define URXH2 (0x50008024)
215#endif
216
217
218/* PWM TIMER */
219#define rTCFG0 (*(volatile unsigned *)0x51000000)
220#define rTCFG1 (*(volatile unsigned *)0x51000004)
221#define rTCON (*(volatile unsigned *)0x51000008)
222#define rTCNTB0 (*(volatile unsigned *)0x5100000C)
223#define rTCMPB0 (*(volatile unsigned *)0x51000010)
224#define rTCNTO0 (*(volatile unsigned *)0x51000014)
225#define rTCNTB1 (*(volatile unsigned *)0x51000018)
226#define rTCMPB1 (*(volatile unsigned *)0x5100001C)
227#define rTCNTO1 (*(volatile unsigned *)0x51000020)
228#define rTCNTB2 (*(volatile unsigned *)0x51000024)
229#define rTCMPB2 (*(volatile unsigned *)0x51000028)
230#define rTCNTO2 (*(volatile unsigned *)0x5100002C)
231#define rTCNTB3 (*(volatile unsigned *)0x51000030)
232#define rTCMPB3 (*(volatile unsigned *)0x51000034)
233#define rTCNTO3 (*(volatile unsigned *)0x51000038)
234#define rTCNTB4 (*(volatile unsigned *)0x5100003C)
235#define rTCNTO4 (*(volatile unsigned *)0x51000040)
236
237
238/* USB DEVICE */
239#ifdef __BIG_ENDIAN
240#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address
241#define rPWR_REG (*(volatile unsigned char *)0x52000147) //Power management
242#define rEP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear
243#define rUSB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear
244#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable
245#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016f)
246#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte
247#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte
248#define rINDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index
249#define rMAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet
250#define rEP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status
251#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status
252#define rIN_CSR2_REG (*(volatile unsigned char *)0x5200018b)
253#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status
254#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000197)
255#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count
256#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f)
257#define rEP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO
258#define rEP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO
259#define rEP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO
260#define rEP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO
261#define rEP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO
262#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control
263#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter
264#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter
265#define rEP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter
266#define rEP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213)
267#define rEP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217)
268#define rEP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control
269#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter
270#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter
271#define rEP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter
272#define rEP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b)
273#define rEP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f)
274#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control
275#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter
276#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter
277#define rEP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter
278#define rEP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253)
279#define rEP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257)
280#define rEP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control
281#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter
282#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter
283#define rEP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter
284#define rEP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b)
285#define rEP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f)
286
287#else // Little Endian
288#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address
289#define rPWR_REG (*(volatile unsigned char *)0x52000144) //Power management
290#define rEP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear
291#define rUSB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear
292#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable
293#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016c)
294#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte
295#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte
296#define rINDEX_REG (*(volatile unsigned char *)0x52000178) //Register index
297#define rMAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet
298#define rEP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status
299#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status
300#define rIN_CSR2_REG (*(volatile unsigned char *)0x52000188)
301#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status
302#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000194)
303#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count
304#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c)
305#define rEP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO
306#define rEP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO
307#define rEP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO
308#define rEP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO
309#define rEP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO
310#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control
311#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter
312#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter
313#define rEP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter
314#define rEP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210)
315#define rEP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214)
316#define rEP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control
317#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter
318#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter
319#define rEP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter
320#define rEP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228)
321#define rEP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c)
322#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control
323#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter
324#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter
325#define rEP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter
326#define rEP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250)
327#define rEP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254)
328#define rEP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control
329#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter
330#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter
331#define rEP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter
332#define rEP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268)
333#define rEP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c)
334#endif // __BIG_ENDIAN
335
336/* WATCH DOG TIMER */
337#define rWTCON (*(volatile unsigned *)0x53000000)
338#define rWTDAT (*(volatile unsigned *)0x53000004)
339#define rWTCNT (*(volatile unsigned *)0x53000008)
340
341
342/* IIC */
343#define rIICCON (*(volatile unsigned *)0x54000000)
344#define rIICSTAT (*(volatile unsigned *)0x54000004)
345#define rIICADD (*(volatile unsigned *)0x54000008)
346#define rIICDS (*(volatile unsigned *)0x5400000C)
347
348
349/* IIS */
350#define rIISCON (*(volatile unsigned *)0x55000000)
351#define rIISMOD (*(volatile unsigned *)0x55000004)
352#define rIISPSR (*(volatile unsigned *)0x55000008)
353#define rIISFIFCON (*(volatile unsigned *)0x5500000C)
354
355#ifdef __BIG_ENDIAN
356#define IISFIFO ((volatile unsigned short *)0x55000012)
357
358#else /* Little Endian */
359#define IISFIFO ((volatile unsigned short *)0x55000010)
360#endif
361
362
363/* I/O PORT */
364#define rGPACON (*(volatile unsigned *)0x56000000) //Port A control
365#define rGPADAT (*(volatile unsigned *)0x56000004) //Port A data
366
367#define rGPBCON (*(volatile unsigned *)0x56000010) //Port B control
368#define rGPBDAT (*(volatile unsigned *)0x56000014) //Port B data
369#define rGPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B
370
371#define rGPCCON (*(volatile unsigned *)0x56000020) //Port C control
372#define rGPCDAT (*(volatile unsigned *)0x56000024) //Port C data
373#define rGPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C
374
375#define rGPDCON (*(volatile unsigned *)0x56000030) //Port D control
376#define rGPDDAT (*(volatile unsigned *)0x56000034) //Port D data
377#define rGPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D
378
379#define rGPECON (*(volatile unsigned *)0x56000040) //Port E control
380#define rGPEDAT (*(volatile unsigned *)0x56000044) //Port E data
381#define rGPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E
382
383#define rGPFCON (*(volatile unsigned *)0x56000050) //Port F control
384#define rGPFDAT (*(volatile unsigned *)0x56000054) //Port F data
385#define rGPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F
386
387#define rGPGCON (*(volatile unsigned *)0x56000060) //Port G control
388#define rGPGDAT (*(volatile unsigned *)0x56000064) //Port G data
389#define rGPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G
390
391#define rGPHCON (*(volatile unsigned *)0x56000070) //Port H control
392#define rGPHDAT (*(volatile unsigned *)0x56000074) //Port H data
393#define rGPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H
394
395#define rMISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control
396#define rDCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control
397#define rEXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control register 0
398#define rEXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control register 1
399#define rEXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control register 2
400#define rEINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved
401#define rEINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved
402#define rEINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control register 2
403#define rEINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control register 3
404#define rEINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask
405#define rEINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending
406#define rGSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status
407#define rGSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32440000)
408
409/* RTC */
410#ifdef __BIG_ENDIAN
411#define rRTCCON (*(volatile unsigned char *)0x57000043) //RTC control
412#define rTICNT (*(volatile unsigned char *)0x57000047) //Tick time count
413#define rRTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control
414#define rALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second
415#define rALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute
416#define rALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour
417#define rALMDATE (*(volatile unsigned char *)0x57000063) //Alarm date //edited by junon
418#define rALMMON (*(volatile unsigned char *)0x57000067) //Alarm month
419#define rALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year
420#define rRTCRST (*(volatile unsigned char *)0x5700006f) //RTC round reset
421#define rBCDSEC (*(volatile unsigned char *)0x57000073) //BCD second
422#define rBCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute
423#define rBCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour
424#define rBCDDATE (*(volatile unsigned char *)0x5700007f) //BCD date //edited by junon
425#define rBCDDAY (*(volatile unsigned char *)0x57000083) //BCD day //edited by junon
426#define rBCDMON (*(volatile unsigned char *)0x57000087) //BCD month
427#define rBCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year
428
429#else //Little Endian
430#define rRTCCON (*(volatile unsigned char *)0x57000040) //RTC control
431#define rTICNT (*(volatile unsigned char *)0x57000044) //Tick time count
432#define rRTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control
433#define rALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second
434#define rALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute
435#define rALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour
436#define rALMDATE (*(volatile unsigned char *)0x57000060) //Alarm date // edited by junon
437#define rALMMON (*(volatile unsigned char *)0x57000064) //Alarm month
438#define rALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year
439#define rRTCRST (*(volatile unsigned char *)0x5700006c) //RTC round reset
440#define rBCDSEC (*(volatile unsigned char *)0x57000070) //BCD second
441#define rBCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute
442#define rBCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour
443#define rBCDDATE (*(volatile unsigned char *)0x5700007c) //BCD date //edited by junon
444#define rBCDDAY (*(volatile unsigned char *)0x57000080) //BCD day //edited by junon
445#define rBCDMON (*(volatile unsigned char *)0x57000084) //BCD month
446#define rBCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year
447#endif //RTC
448
449
450/* ADC */
451#define rADCCON (*(volatile unsigned *)0x58000000)
452#define rADCTSC (*(volatile unsigned *)0x58000004)
453#define rADCDLY (*(volatile unsigned *)0x58000008)
454#define rADCDAT0 (*(volatile unsigned *)0x5800000c)
455#define rADCDAT1 (*(volatile unsigned *)0x58000010)
456
457
458/* SPI */
459#define rSPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control
460#define rSPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status
461#define rSPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control
462#define rSPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud rate prescaler
463#define rSPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data
464#define rSPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data
465
466#define rSPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control
467#define rSPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status
468#define rSPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control
469#define rSPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud rate prescaler
470#define rSPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data
471#define rSPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data
472
473/* SD interface */
474#define rSDICON (*(volatile unsigned *)0x5a000000) //SDI control
475#define rSDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud rate prescaler
476#define rSDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument
477#define rSDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control
478#define rSDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status
479#define rSDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI response 0
480#define rSDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI response 1
481#define rSDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI response 2
482#define rSDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI response 3
483#define rSDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer
484#define rSDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size
485#define rSDIDATCON (*(volatile unsigned *)0x5a00002c) //SDI data control
486#define rSDIDATCNT (*(volatile unsigned *)0x5a000030) //SDI data remain counter
487#define rSDIDATSTA (*(volatile unsigned *)0x5a000034) //SDI data status
488#define rSDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status
489#define rSDIIMSK (*(volatile unsigned *)0x5a000040) //SDI interrupt mask. edited for 2440A
490
491#ifdef __BIG_ENDIAN
492#define rSDIDAT (*(volatile unsigned *)0x5a00003F) //SDI data
493#define SDIDAT 0x5a00003F
494#else // Little Endian
495#define rSDIDAT (*(volatile unsigned *)0x5a00003C) //SDI data
496#define SDIDAT 0x5a00003C
497#endif //SD Interface
498
499
500#define _ISR_STARTADDRESS rtems_vector_table
501/* ISR */
502#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
503#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
504#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
505#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC))
506#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
507#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
508#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
509#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C))
510
511#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
512#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
513#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
514#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C))
515#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
516#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
517#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3C))
518#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
519#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44))
520#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
521#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C))
522#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
523#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
524#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
525#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5C))
526#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60))
527#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
528#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
529#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C))
530#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
531#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74))
532#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78))
533#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7C))
534#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
535#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
536#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C))
537#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
538#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
539#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
540#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0))
541
542
543/* PENDING BIT */
544#define BIT_EINT0 (0x1)
545#define BIT_EINT1 (0x1<<1)
546#define BIT_EINT2 (0x1<<2)
547#define BIT_EINT3 (0x1<<3)
548#define BIT_EINT4_7 (0x1<<4)
549#define BIT_EINT8_23 (0x1<<5)
550#define BIT_BAT_FLT (0x1<<7)
551#define BIT_TICK (0x1<<8)
552#define BIT_WDT (0x1<<9)
553#define BIT_TIMER0 (0x1<<10)
554#define BIT_TIMER1 (0x1<<11)
555#define BIT_TIMER2 (0x1<<12)
556#define BIT_TIMER3 (0x1<<13)
557#define BIT_TIMER4 (0x1<<14)
558#define BIT_UART2 (0x1<<15)
559#define BIT_LCD (0x1<<16)
560#define BIT_DMA0 (0x1<<17)
561#define BIT_DMA1 (0x1<<18)
562#define BIT_DMA2 (0x1<<19)
563#define BIT_DMA3 (0x1<<20)
564#define BIT_SDI (0x1<<21)
565#define BIT_SPI0 (0x1<<22)
566#define BIT_UART1 (0x1<<23)
567#define BIT_USBD (0x1<<25)
568#define BIT_USBH (0x1<<26)
569#define BIT_IIC (0x1<<27)
570#define BIT_UART0 (0x1<<28)
571#define BIT_SPI1 (0x1<<29)
572#define BIT_RTC (0x1<<30)
573#define BIT_ADC (0x1<<31)
574#define BIT_ALLMSK (0xFFFFFFFF)
575
576#define ClearPending(bit) {\
577 rSRCPND = bit;\
578 rINTPND = bit;\
579 rINTPND;\
580 }
581/* Wait until rINTPND is changed for the case that the ISR is very short. */
582#ifndef ASM
583/* Typedefs */
584typedef union {
585 struct _reg {
586 unsigned SM_BIT:1; /* Enters STOP mode. This bit isn't be */
587 /* cleared automatically. */
588 unsigned Reserved:1; /* SL_IDLE mode option. This bit isn't cleared */
589 /* automatically. To enter SL_IDLE mode, */
590 /* CLKCON register has to be 0xe. */
591 unsigned IDLE_BIT:1; /* Enters IDLE mode. This bit isn't be cleared */
592 /* automatically. */
593 unsigned POWER_OFF:1;
594 unsigned NAND_flash:1;
595 unsigned LCDC:1; /* Controls HCLK into LCDC block */
596 unsigned USB_host:1; /* Controls HCLK into USB host block */
597 unsigned USB_device:1; /* Controls PCLK into USB device block */
598 unsigned PWMTIMER:1; /* Controls PCLK into PWMTIMER block */
599 unsigned SDI:1; /* Controls PCLK into MMC interface block */
600 unsigned UART0:1; /* Controls PCLK into UART0 block */
601 unsigned UART1:1; /* Controls PCLK into UART1 block */
602 unsigned UART2:1; /* Controls PCLK into UART1 block */
603 unsigned GPIO:1; /* Controls PCLK into GPIO block */
604 unsigned RTC:1; /* Controls PCLK into RTC control block. Even if */
605 /* this bit is cleared to 0, RTC timer is alive. */
606 unsigned ADC:1; /* Controls PCLK into ADC block */
607 unsigned IIC:1; /* Controls PCLK into IIC block */
608 unsigned IIS:1; /* Controls PCLK into IIS block */
609 unsigned SPI:1; /* Controls PCLK into SPI block */
610 } reg;
611 unsigned long all;
612} CLKCON;
613
614typedef union
615{
616 struct {
617 unsigned ENVID:1; /* LCD video output and the logic 1=enable/0=disable. */
618 unsigned BPPMODE:4; /* 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, */
619 /* 1110 = 16 bpp TFT skipmode */
620 unsigned PNRMODE:2; /* TFT: 3 */
621 unsigned MMODE:1; /* This bit determines the toggle rate of the VM. */
622 /* 0 = Each Frame, 1 = The rate defined by the MVAL */
623 unsigned CLKVAL:10; /* TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1) */
624 unsigned LINECNT:10; /* (read only) These bits provide the status of the */
625 /* line counter. Down count from LINEVAL to 0 */
626 } reg;
627 unsigned long all;
628} LCDCON1;
629
630typedef union {
631 struct {
632 unsigned VSPW:6; /* TFT: Vertical sync pulse width determines the */
633 /* VSYNC pulse's high level width by counting the */
634 /* number of inactive lines. */
635 unsigned VFPD:8; /* TFT: Vertical front porch is the number of */
636 /* inactive lines at the end of a frame, before */
637 /* vertical synchronization period. */
638 unsigned LINEVAL:10; /* TFT/STN: These bits determine the vertical size */
639 /* of LCD panel. */
640 unsigned VBPD:8; /* TFT: Vertical back porch is the number of inactive */
641 /* lines at the start of a frame, after */
642 /* vertical synchronization period. */
643 } reg;
644 unsigned long all;
645} LCDCON2;
646
647typedef union {
648 struct {
649 unsigned HFPD:8; /* TFT: Horizontal front porch is the number of */
650 /* VCLK periods between the end of active data */
651 /* and the rising edge of HSYNC. */
652 unsigned HOZVAL:11; /* TFT/STN: These bits determine the horizontal */
653 /* size of LCD panel. 2n bytes. */
654 unsigned HBPD:7; /* TFT: Horizontal back porch is the number of VCLK */
655 /* periods between the falling edge of HSYNC and */
656 /* the start of active data. */
657 } reg;
658 unsigned long all;
659} LCDCON3;
660
661typedef union {
662 struct {
663 unsigned HSPW:8; /* TFT: Horizontal sync pulse width determines the */
664 /* HSYNC pulse's high level width by counting the */
665 /* number of the VCLK. */
666 unsigned MVAL:8; /* STN: */
667 } reg;
668 unsigned long all;
669} LCDCON4;
670
671typedef union {
672 struct {
673 unsigned HWSWP:1; /* STN/TFT: Half-Word swap control bit. */
674 /* 0 = Swap Disable 1 = Swap Enable */
675 unsigned BSWP:1; /* STN/TFT: Byte swap control bit. */
676 /* 0 = Swap Disable 1 = Swap Enable */
677 unsigned ENLEND:1; /* TFT: LEND output signal enable/disable. */
678 /* 0 = Disable LEND signal. */
679 /* 1 = Enable LEND signal */
680 unsigned PWREN:1;
681 unsigned INVLEND:1;/* TFT: This bit indicates the LEND signal */
682 /* polarity. 0 = normal 1 = inverted */
683 unsigned INVPWREN:1;
684 unsigned INVVDEN:1; /* TFT: This bit indicates the VDEN signal */
685 /* polarity. */
686 /* 0 = normal 1 = inverted */
687 unsigned INVVD:1; /* STN/TFT: This bit indicates the VD (video data) */
688 /* pulse polarity. 0 = Normal. */
689 /* 1 = VD is inverted. */
690 unsigned INVVFRAME:1; /* STN/TFT: This bit indicates the VFRAME/VSYNC */
691 /* pulse polarity. 0 = normal 1 = inverted */
692 unsigned INVVLINE:1; /* STN/TFT: This bit indicates the VLINE/HSYNC */
693 /* pulse polarity. 0 = normal 1 = inverted */
694 unsigned INVVCLK:1; /* STN/TFT: This bit controls the polarity of the */
695 /* VCLK active edge. 0 = The video data is */
696 /* fetched at VCLK falling edge. 1 = The video */
697 /* data is fetched at VCLK rising edge */
698 unsigned FRM565:1;
699 unsigned BPP24BL:1;
700 unsigned HSTATUS:2; /* TFT: Horizontal Status (Read only) */
701 /* 00 = HSYNC */
702 /* 01 = BACK Porch. */
703 /* 10 = ACTIVE */
704 /* 11 = FRONT Porch */
705 unsigned _VSTATUS:2; /* TFT: Vertical Status (Read only). */
706 /* 00 = VSYNC */
707 /* 01 = BACK Porch. */
708 /* 10 = ACTIVE */
709 /* 11 = FRONT Porch */
710 unsigned RESERVED:16;
711 } reg;
712 unsigned long all;
713} LCDCON5;
714
715typedef union {
716 struct {
717 unsigned LCDBASEU:21; /* For single-scan LCD: These bits indicate */
718 /* A[21:1] of the start address of the LCD */
719 /* frame buffer. */
720 unsigned LCDBANK:9; /* A[28:22] */
721 } reg;
722 unsigned long all;
723} LCDSADDR1;
724
725typedef union {
726 struct {
727 unsigned LCDBASEL:21; /* For single scan LCD: These bits indicate A[21:1]*/
728 /* of the end address of the LCD frame buffer. */
729 /* LCDBASEL = ((the fame end address) >>1) + 1 */
730 /* = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) */
731 } reg;
732 unsigned long all;
733} LCDSADDR2;
734
735typedef union {
736 struct {
737 unsigned PAGEWIDTH:11; /* Virtual screen page width(the number of half */
738 /* words) This value defines the width of the */
739 /* view port in the frame */
740 unsigned OFFSIZE:11; /* Virtual screen offset size(the number of half */
741 /* words) This value defines the difference */
742 /* between the address of the last half word */
743 /* displayed on the previous LCD line and the */
744 /* address of the first half word to be */
745 /* displayed in the new LCD line. */
746 } reg;
747 unsigned long all;
748} LCDSADDR3;
749
750/*
751 *
752 */
753
754typedef union {
755 struct {
756 unsigned IISIFENA:1; /* IIS interface enable (start) */
757 unsigned IISPSENA:1; /* IIS prescaler enable */
758 unsigned RXCHIDLE:1; /* Receive channel idle command */
759 unsigned TXCHIDLE:1; /* Transmit channel idle command */
760 unsigned RXDMAENA:1; /* Receive DMA service request enable */
761 unsigned TXDMAENA:1; /* Transmit DMA service request enable */
762 unsigned RXFIFORDY:1; /* Receive FIFO ready flag (read only) */
763 unsigned TXFIFORDY:1; /* Transmit FIFO ready flag (read only) */
764 unsigned LRINDEX:1; /* Left/right channel index (read only) */
765 } reg;
766 unsigned long all;
767} IISCON;
768
769typedef union {
770 struct {
771 unsigned SBCLKFS:2; /* Serial bit clock frequency select */
772 unsigned MCLKFS:1; /* Master clock frequency select */
773 unsigned SDBITS:1; /* Serial data bit per channel */
774 unsigned SIFMT:1; /* Serial interface format */
775 unsigned ACTLEVCH:1; /* Active level pf left/right channel */
776 unsigned TXRXMODE:2; /* Transmit/receive mode select */
777 unsigned MODE:1; /* Master/slave mode select */
778 } reg;
779 unsigned long all;
780} IISMOD;
781
782typedef union {
783 struct {
784 unsigned PSB:5; /* Prescaler control B */
785 unsigned PSA:5; /* Prescaler control A */
786 } reg;
787 unsigned long all;
788} IISPSR;
789
790typedef union {
791 struct {
792 unsigned RXFIFOCNT:6; /* (read only) */
793 unsigned TXFIFOCNT:6; /* (read only) */
794 unsigned RXFIFOENA:1; /* */
795 unsigned TXFIFOENA:1; /* */
796 unsigned RXFIFOMODE:1; /* */
797 unsigned TXFIFOMODE:1; /* */
798 } reg;
799 unsigned long all;
800} IISSFIFCON;
801
802typedef union {
803 struct {
804 unsigned FENTRY:16; /* */
805 } reg;
806 unsigned long all;
807} IISSFIF;
808#endif //ASM
809
810#define LCD_WIDTH 240
811#define LCD_HEIGHT 320
812#define LCD_ASPECT ((float)(LCD_WIDTH/LCD_HEIGHT))
813
814#define SMDK2410_KEY_SELECT 512
815#define SMDK2410_KEY_START 256
816#define SMDK2410_KEY_A 64
817#define SMDK2410_KEY_B 32
818#define SMDK2410_KEY_L 16
819#define SMDK2410_KEY_R 128
820#define SMDK2410_KEY_UP 8
821#define SMDK2410_KEY_DOWN 2
822#define SMDK2410_KEY_LEFT 1
823#define SMDK2410_KEY_RIGHT 4
824
825#endif /*S3C2410_H_*/
CLKCON
Definition: s3c2400.h:434
IISCON
Definition: s3c2400.h:605
IISMOD
Definition: s3c2400.h:620
IISPSR
Definition: s3c2400.h:633
IISSFIFCON
Definition: s3c2400.h:641
IISSFIF
Definition: s3c2400.h:653
LCDCON1
Definition: s3c2400.h:462
LCDCON2
Definition: s3c2400.h:477
LCDCON3
Definition: s3c2400.h:494
LCDCON4
Definition: s3c2400.h:508
LCDCON5
Definition: s3c2400.h:521
LCDSADDR1
Definition: s3c2400.h:566
LCDSADDR2
Definition: s3c2400.h:576
LCDSADDR3
Definition: s3c2400.h:586