RTEMS: bsps/arm/atsam/include/libchip/include/same70/component/component_tc.h Source File

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component_tc.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAME70_TC_COMPONENT_
31#define _SAME70_TC_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41 typedef struct {
42 __O uint32_t TC_CCR;
43 __IO uint32_t TC_CMR;
44 __IO uint32_t TC_SMMR;
45 __I uint32_t TC_RAB;
46 __I uint32_t TC_CV;
47 __IO uint32_t TC_RA;
48 __IO uint32_t TC_RB;
49 __IO uint32_t TC_RC;
50 __I uint32_t TC_SR;
51 __O uint32_t TC_IER;
52 __O uint32_t TC_IDR;
53 __I uint32_t TC_IMR;
54 __IO uint32_t TC_EMR;
55 __I uint32_t Reserved1[3];
56} TcChannel;
58#define TCCHANNEL_NUMBER 3
59 typedef struct {
60 TcChannel TC_CHANNEL[TCCHANNEL_NUMBER];
61 __O uint32_t TC_BCR;
62 __IO uint32_t TC_BMR;
63 __O uint32_t TC_QIER;
64 __O uint32_t TC_QIDR;
65 __I uint32_t TC_QIMR;
66 __I uint32_t TC_QISR;
67 __IO uint32_t TC_FMR;
68 __I uint32_t Reserved1[2];
69 __IO uint32_t TC_WPMR;
70} Tc;
71#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
72/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
73#define TC_CCR_CLKEN (0x1u << 0)
74#define TC_CCR_CLKDIS (0x1u << 1)
75#define TC_CCR_SWTRG (0x1u << 2)
76/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
77#define TC_CMR_TCCLKS_Pos 0
78#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos)
79#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos)))
80#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0)
81#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0)
82#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0)
83#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0)
84#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0)
85#define TC_CMR_TCCLKS_XC0 (0x5u << 0)
86#define TC_CMR_TCCLKS_XC1 (0x6u << 0)
87#define TC_CMR_TCCLKS_XC2 (0x7u << 0)
88#define TC_CMR_CLKI (0x1u << 3)
89#define TC_CMR_BURST_Pos 4
90#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos)
91#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos)))
92#define TC_CMR_BURST_NONE (0x0u << 4)
93#define TC_CMR_BURST_XC0 (0x1u << 4)
94#define TC_CMR_BURST_XC1 (0x2u << 4)
95#define TC_CMR_BURST_XC2 (0x3u << 4)
96#define TC_CMR_LDBSTOP (0x1u << 6)
97#define TC_CMR_LDBDIS (0x1u << 7)
98#define TC_CMR_ETRGEDG_Pos 8
99#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos)
100#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos)))
101#define TC_CMR_ETRGEDG_NONE (0x0u << 8)
102#define TC_CMR_ETRGEDG_RISING (0x1u << 8)
103#define TC_CMR_ETRGEDG_FALLING (0x2u << 8)
104#define TC_CMR_ETRGEDG_EDGE (0x3u << 8)
105#define TC_CMR_ABETRG (0x1u << 10)
106#define TC_CMR_CPCTRG (0x1u << 14)
107#define TC_CMR_WAVE (0x1u << 15)
108#define TC_CMR_LDRA_Pos 16
109#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos)
110#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos)))
111#define TC_CMR_LDRA_NONE (0x0u << 16)
112#define TC_CMR_LDRA_RISING (0x1u << 16)
113#define TC_CMR_LDRA_FALLING (0x2u << 16)
114#define TC_CMR_LDRA_EDGE (0x3u << 16)
115#define TC_CMR_LDRB_Pos 18
116#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos)
117#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos)))
118#define TC_CMR_LDRB_NONE (0x0u << 18)
119#define TC_CMR_LDRB_RISING (0x1u << 18)
120#define TC_CMR_LDRB_FALLING (0x2u << 18)
121#define TC_CMR_LDRB_EDGE (0x3u << 18)
122#define TC_CMR_SBSMPLR_Pos 20
123#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos)
124#define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos)))
125#define TC_CMR_SBSMPLR_ONE (0x0u << 20)
126#define TC_CMR_SBSMPLR_HALF (0x1u << 20)
127#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20)
128#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20)
129#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20)
130#define TC_CMR_CPCSTOP (0x1u << 6)
131#define TC_CMR_CPCDIS (0x1u << 7)
132#define TC_CMR_EEVTEDG_Pos 8
133#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos)
134#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos)))
135#define TC_CMR_EEVTEDG_NONE (0x0u << 8)
136#define TC_CMR_EEVTEDG_RISING (0x1u << 8)
137#define TC_CMR_EEVTEDG_FALLING (0x2u << 8)
138#define TC_CMR_EEVTEDG_EDGE (0x3u << 8)
139#define TC_CMR_EEVT_Pos 10
140#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos)
141#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos)))
142#define TC_CMR_EEVT_TIOB (0x0u << 10)
143#define TC_CMR_EEVT_XC0 (0x1u << 10)
144#define TC_CMR_EEVT_XC1 (0x2u << 10)
145#define TC_CMR_EEVT_XC2 (0x3u << 10)
146#define TC_CMR_ENETRG (0x1u << 12)
147#define TC_CMR_WAVSEL_Pos 13
148#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos)
149#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos)))
150#define TC_CMR_WAVSEL_UP (0x0u << 13)
151#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13)
152#define TC_CMR_WAVSEL_UP_RC (0x2u << 13)
153#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13)
154#define TC_CMR_ACPA_Pos 16
155#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos)
156#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos)))
157#define TC_CMR_ACPA_NONE (0x0u << 16)
158#define TC_CMR_ACPA_SET (0x1u << 16)
159#define TC_CMR_ACPA_CLEAR (0x2u << 16)
160#define TC_CMR_ACPA_TOGGLE (0x3u << 16)
161#define TC_CMR_ACPC_Pos 18
162#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos)
163#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos)))
164#define TC_CMR_ACPC_NONE (0x0u << 18)
165#define TC_CMR_ACPC_SET (0x1u << 18)
166#define TC_CMR_ACPC_CLEAR (0x2u << 18)
167#define TC_CMR_ACPC_TOGGLE (0x3u << 18)
168#define TC_CMR_AEEVT_Pos 20
169#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos)
170#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos)))
171#define TC_CMR_AEEVT_NONE (0x0u << 20)
172#define TC_CMR_AEEVT_SET (0x1u << 20)
173#define TC_CMR_AEEVT_CLEAR (0x2u << 20)
174#define TC_CMR_AEEVT_TOGGLE (0x3u << 20)
175#define TC_CMR_ASWTRG_Pos 22
176#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos)
177#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos)))
178#define TC_CMR_ASWTRG_NONE (0x0u << 22)
179#define TC_CMR_ASWTRG_SET (0x1u << 22)
180#define TC_CMR_ASWTRG_CLEAR (0x2u << 22)
181#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22)
182#define TC_CMR_BCPB_Pos 24
183#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos)
184#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos)))
185#define TC_CMR_BCPB_NONE (0x0u << 24)
186#define TC_CMR_BCPB_SET (0x1u << 24)
187#define TC_CMR_BCPB_CLEAR (0x2u << 24)
188#define TC_CMR_BCPB_TOGGLE (0x3u << 24)
189#define TC_CMR_BCPC_Pos 26
190#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos)
191#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos)))
192#define TC_CMR_BCPC_NONE (0x0u << 26)
193#define TC_CMR_BCPC_SET (0x1u << 26)
194#define TC_CMR_BCPC_CLEAR (0x2u << 26)
195#define TC_CMR_BCPC_TOGGLE (0x3u << 26)
196#define TC_CMR_BEEVT_Pos 28
197#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos)
198#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos)))
199#define TC_CMR_BEEVT_NONE (0x0u << 28)
200#define TC_CMR_BEEVT_SET (0x1u << 28)
201#define TC_CMR_BEEVT_CLEAR (0x2u << 28)
202#define TC_CMR_BEEVT_TOGGLE (0x3u << 28)
203#define TC_CMR_BSWTRG_Pos 30
204#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos)
205#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos)))
206#define TC_CMR_BSWTRG_NONE (0x0u << 30)
207#define TC_CMR_BSWTRG_SET (0x1u << 30)
208#define TC_CMR_BSWTRG_CLEAR (0x2u << 30)
209#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30)
210/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
211#define TC_SMMR_GCEN (0x1u << 0)
212#define TC_SMMR_DOWN (0x1u << 1)
213/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */
214#define TC_RAB_RAB_Pos 0
215#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos)
216/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
217#define TC_CV_CV_Pos 0
218#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos)
219/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
220#define TC_RA_RA_Pos 0
221#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos)
222#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
223/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
224#define TC_RB_RB_Pos 0
225#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos)
226#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
227/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
228#define TC_RC_RC_Pos 0
229#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos)
230#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
231/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
232#define TC_SR_COVFS (0x1u << 0)
233#define TC_SR_LOVRS (0x1u << 1)
234#define TC_SR_CPAS (0x1u << 2)
235#define TC_SR_CPBS (0x1u << 3)
236#define TC_SR_CPCS (0x1u << 4)
237#define TC_SR_LDRAS (0x1u << 5)
238#define TC_SR_LDRBS (0x1u << 6)
239#define TC_SR_ETRGS (0x1u << 7)
240#define TC_SR_CLKSTA (0x1u << 16)
241#define TC_SR_MTIOA (0x1u << 17)
242#define TC_SR_MTIOB (0x1u << 18)
243/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
244#define TC_IER_COVFS (0x1u << 0)
245#define TC_IER_LOVRS (0x1u << 1)
246#define TC_IER_CPAS (0x1u << 2)
247#define TC_IER_CPBS (0x1u << 3)
248#define TC_IER_CPCS (0x1u << 4)
249#define TC_IER_LDRAS (0x1u << 5)
250#define TC_IER_LDRBS (0x1u << 6)
251#define TC_IER_ETRGS (0x1u << 7)
252/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
253#define TC_IDR_COVFS (0x1u << 0)
254#define TC_IDR_LOVRS (0x1u << 1)
255#define TC_IDR_CPAS (0x1u << 2)
256#define TC_IDR_CPBS (0x1u << 3)
257#define TC_IDR_CPCS (0x1u << 4)
258#define TC_IDR_LDRAS (0x1u << 5)
259#define TC_IDR_LDRBS (0x1u << 6)
260#define TC_IDR_ETRGS (0x1u << 7)
261/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
262#define TC_IMR_COVFS (0x1u << 0)
263#define TC_IMR_LOVRS (0x1u << 1)
264#define TC_IMR_CPAS (0x1u << 2)
265#define TC_IMR_CPBS (0x1u << 3)
266#define TC_IMR_CPCS (0x1u << 4)
267#define TC_IMR_LDRAS (0x1u << 5)
268#define TC_IMR_LDRBS (0x1u << 6)
269#define TC_IMR_ETRGS (0x1u << 7)
270/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */
271#define TC_EMR_TRIGSRCA_Pos 0
272#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos)
273#define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos)))
274#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0)
275#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0)
276#define TC_EMR_TRIGSRCB_Pos 4
277#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos)
278#define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos)))
279#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4)
280#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4)
281#define TC_EMR_NODIVCLK (0x1u << 8)
282/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
283#define TC_BCR_SYNC (0x1u << 0)
284/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
285#define TC_BMR_TC0XC0S_Pos 0
286#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos)
287#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos)))
288#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0)
289#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0)
290#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0)
291#define TC_BMR_TC1XC1S_Pos 2
292#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos)
293#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos)))
294#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2)
295#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2)
296#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2)
297#define TC_BMR_TC2XC2S_Pos 4
298#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos)
299#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos)))
300#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4)
301#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4)
302#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4)
303#define TC_BMR_QDEN (0x1u << 8)
304#define TC_BMR_POSEN (0x1u << 9)
305#define TC_BMR_SPEEDEN (0x1u << 10)
306#define TC_BMR_QDTRANS (0x1u << 11)
307#define TC_BMR_EDGPHA (0x1u << 12)
308#define TC_BMR_INVA (0x1u << 13)
309#define TC_BMR_INVB (0x1u << 14)
310#define TC_BMR_INVIDX (0x1u << 15)
311#define TC_BMR_SWAP (0x1u << 16)
312#define TC_BMR_IDXPHB (0x1u << 17)
313#define TC_BMR_MAXFILT_Pos 20
314#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos)
315#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
316/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
317#define TC_QIER_IDX (0x1u << 0)
318#define TC_QIER_DIRCHG (0x1u << 1)
319#define TC_QIER_QERR (0x1u << 2)
320/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
321#define TC_QIDR_IDX (0x1u << 0)
322#define TC_QIDR_DIRCHG (0x1u << 1)
323#define TC_QIDR_QERR (0x1u << 2)
324/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
325#define TC_QIMR_IDX (0x1u << 0)
326#define TC_QIMR_DIRCHG (0x1u << 1)
327#define TC_QIMR_QERR (0x1u << 2)
328/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
329#define TC_QISR_IDX (0x1u << 0)
330#define TC_QISR_DIRCHG (0x1u << 1)
331#define TC_QISR_QERR (0x1u << 2)
332#define TC_QISR_DIR (0x1u << 8)
333/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
334#define TC_FMR_ENCF0 (0x1u << 0)
335#define TC_FMR_ENCF1 (0x1u << 1)
336/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */
337#define TC_WPMR_WPEN (0x1u << 0)
338#define TC_WPMR_WPKEY_Pos 8
339#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos)
340#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
341#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8)
344
345
346#endif /* _SAME70_TC_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
TcChannel
TcChannel hardware registers.
Definition: component_tc.h:41
TcChannel::TC_IER
__O uint32_t TC_IER
(TcChannel Offset: 0x24) Interrupt Enable Register
Definition: component_tc.h:51
TcChannel::TC_RA
__IO uint32_t TC_RA
(TcChannel Offset: 0x14) Register A
Definition: component_tc.h:47
TcChannel::TC_RAB
__I uint32_t TC_RAB
(TcChannel Offset: 0xC) Register AB
Definition: component_tc.h:45
TcChannel::TC_RB
__IO uint32_t TC_RB
(TcChannel Offset: 0x18) Register B
Definition: component_tc.h:48
TcChannel::TC_SMMR
__IO uint32_t TC_SMMR
(TcChannel Offset: 0x8) Stepper Motor Mode Register
Definition: component_tc.h:44
TcChannel::TC_SR
__I uint32_t TC_SR
(TcChannel Offset: 0x20) Status Register
Definition: component_tc.h:50
TcChannel::TC_RC
__IO uint32_t TC_RC
(TcChannel Offset: 0x1C) Register C
Definition: component_tc.h:49
TcChannel::TC_IDR
__O uint32_t TC_IDR
(TcChannel Offset: 0x28) Interrupt Disable Register
Definition: component_tc.h:52
TcChannel::TC_CCR
__O uint32_t TC_CCR
(TcChannel Offset: 0x0) Channel Control Register
Definition: component_tc.h:42
TcChannel::TC_IMR
__I uint32_t TC_IMR
(TcChannel Offset: 0x2C) Interrupt Mask Register
Definition: component_tc.h:53
TcChannel::TC_CMR
__IO uint32_t TC_CMR
(TcChannel Offset: 0x4) Channel Mode Register
Definition: component_tc.h:43
TcChannel::TC_EMR
__IO uint32_t TC_EMR
(TcChannel Offset: 0x30) Extended Mode Register
Definition: component_tc.h:54
TcChannel::TC_CV
__I uint32_t TC_CV
(TcChannel Offset: 0x10) Counter Value
Definition: component_tc.h:46
Tc
Definition: component_tc.h:59
Tc::TC_FMR
__IO uint32_t TC_FMR
(Tc Offset: 0xD8) Fault Mode Register
Definition: component_tc.h:67
Tc::TC_QIDR
__O uint32_t TC_QIDR
(Tc Offset: 0xCC) QDEC Interrupt Disable Register
Definition: component_tc.h:64
Tc::TC_BMR
__IO uint32_t TC_BMR
(Tc Offset: 0xC4) Block Mode Register
Definition: component_tc.h:62
Tc::TC_QIMR
__I uint32_t TC_QIMR
(Tc Offset: 0xD0) QDEC Interrupt Mask Register
Definition: component_tc.h:65
Tc::TC_WPMR
__IO uint32_t TC_WPMR
(Tc Offset: 0xE4) Write Protection Mode Register
Definition: component_tc.h:69
Tc::TC_BCR
__O uint32_t TC_BCR
(Tc Offset: 0xC0) Block Control Register
Definition: component_tc.h:61
Tc::TC_QIER
__O uint32_t TC_QIER
(Tc Offset: 0xC8) QDEC Interrupt Enable Register
Definition: component_tc.h:63
Tc::TC_QISR
__I uint32_t TC_QISR
(Tc Offset: 0xD4) QDEC Interrupt Status Register
Definition: component_tc.h:66