RTEMS: bsps/arm/atsam/include/libchip/include/sams70/component/component_matrix.h Source File

| RTEMS 5.4-rc2

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component_matrix.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70_MATRIX_COMPONENT_
31#define _SAMS70_MATRIX_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __IO uint32_t MATRIX_MCFG0;
43 __IO uint32_t MATRIX_MCFG1;
44 __IO uint32_t MATRIX_MCFG2;
45 __IO uint32_t MATRIX_MCFG3;
46 __IO uint32_t MATRIX_MCFG4;
47 __IO uint32_t MATRIX_MCFG5;
48 __IO uint32_t MATRIX_MCFG6;
49 __I uint32_t Reserved1[1];
50 __IO uint32_t MATRIX_MCFG8;
51 __I uint32_t Reserved2[7];
52 __IO uint32_t MATRIX_SCFG[9];
53 __I uint32_t Reserved3[7];
54 __IO uint32_t MATRIX_PRAS0;
55 __IO uint32_t MATRIX_PRBS0;
56 __IO uint32_t MATRIX_PRAS1;
57 __IO uint32_t MATRIX_PRBS1;
58 __IO uint32_t MATRIX_PRAS2;
59 __IO uint32_t MATRIX_PRBS2;
60 __IO uint32_t MATRIX_PRAS3;
61 __IO uint32_t MATRIX_PRBS3;
62 __IO uint32_t MATRIX_PRAS4;
63 __IO uint32_t MATRIX_PRBS4;
64 __IO uint32_t MATRIX_PRAS5;
65 __IO uint32_t MATRIX_PRBS5;
66 __IO uint32_t MATRIX_PRAS6;
67 __IO uint32_t MATRIX_PRBS6;
68 __IO uint32_t MATRIX_PRAS7;
69 __IO uint32_t MATRIX_PRBS7;
70 __IO uint32_t MATRIX_PRAS8;
71 __IO uint32_t MATRIX_PRBS8;
72 __I uint32_t Reserved4[14];
73 __IO uint32_t MATRIX_MRCR;
74 __I uint32_t Reserved5[4];
75 __IO uint32_t CCFG_SYSIO;
76 __I uint32_t Reserved6[3];
77 __IO uint32_t CCFG_SMCNFCS;
78 __I uint32_t Reserved7[47];
79 __IO uint32_t MATRIX_WPMR;
80 __I uint32_t MATRIX_WPSR;
81} Matrix;
82#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
83/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */
84#define MATRIX_MCFG0_ULBT_Pos 0
85#define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos)
86#define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos)))
87#define MATRIX_MCFG0_ULBT_UNLTD_LENGTH (0x0u << 0)
88#define MATRIX_MCFG0_ULBT_SINGLE_ACCESS (0x1u << 0)
89#define MATRIX_MCFG0_ULBT_4BEAT_BURST (0x2u << 0)
90#define MATRIX_MCFG0_ULBT_8BEAT_BURST (0x3u << 0)
91#define MATRIX_MCFG0_ULBT_16BEAT_BURST (0x4u << 0)
92#define MATRIX_MCFG0_ULBT_32BEAT_BURST (0x5u << 0)
93#define MATRIX_MCFG0_ULBT_64BEAT_BURST (0x6u << 0)
94#define MATRIX_MCFG0_ULBT_128BEAT_BURST (0x7u << 0)
95/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */
96#define MATRIX_MCFG1_ULBT_Pos 0
97#define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos)
98#define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos)))
99#define MATRIX_MCFG1_ULBT_UNLTD_LENGTH (0x0u << 0)
100#define MATRIX_MCFG1_ULBT_SINGLE_ACCESS (0x1u << 0)
101#define MATRIX_MCFG1_ULBT_4BEAT_BURST (0x2u << 0)
102#define MATRIX_MCFG1_ULBT_8BEAT_BURST (0x3u << 0)
103#define MATRIX_MCFG1_ULBT_16BEAT_BURST (0x4u << 0)
104#define MATRIX_MCFG1_ULBT_32BEAT_BURST (0x5u << 0)
105#define MATRIX_MCFG1_ULBT_64BEAT_BURST (0x6u << 0)
106#define MATRIX_MCFG1_ULBT_128BEAT_BURST (0x7u << 0)
107/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */
108#define MATRIX_MCFG2_ULBT_Pos 0
109#define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos)
110#define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos)))
111#define MATRIX_MCFG2_ULBT_UNLTD_LENGTH (0x0u << 0)
112#define MATRIX_MCFG2_ULBT_SINGLE_ACCESS (0x1u << 0)
113#define MATRIX_MCFG2_ULBT_4BEAT_BURST (0x2u << 0)
114#define MATRIX_MCFG2_ULBT_8BEAT_BURST (0x3u << 0)
115#define MATRIX_MCFG2_ULBT_16BEAT_BURST (0x4u << 0)
116#define MATRIX_MCFG2_ULBT_32BEAT_BURST (0x5u << 0)
117#define MATRIX_MCFG2_ULBT_64BEAT_BURST (0x6u << 0)
118#define MATRIX_MCFG2_ULBT_128BEAT_BURST (0x7u << 0)
119/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */
120#define MATRIX_MCFG3_ULBT_Pos 0
121#define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos)
122#define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos)))
123#define MATRIX_MCFG3_ULBT_UNLTD_LENGTH (0x0u << 0)
124#define MATRIX_MCFG3_ULBT_SINGLE_ACCESS (0x1u << 0)
125#define MATRIX_MCFG3_ULBT_4BEAT_BURST (0x2u << 0)
126#define MATRIX_MCFG3_ULBT_8BEAT_BURST (0x3u << 0)
127#define MATRIX_MCFG3_ULBT_16BEAT_BURST (0x4u << 0)
128#define MATRIX_MCFG3_ULBT_32BEAT_BURST (0x5u << 0)
129#define MATRIX_MCFG3_ULBT_64BEAT_BURST (0x6u << 0)
130#define MATRIX_MCFG3_ULBT_128BEAT_BURST (0x7u << 0)
131/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */
132#define MATRIX_MCFG4_ULBT_Pos 0
133#define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos)
134#define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos)))
135#define MATRIX_MCFG4_ULBT_UNLTD_LENGTH (0x0u << 0)
136#define MATRIX_MCFG4_ULBT_SINGLE_ACCESS (0x1u << 0)
137#define MATRIX_MCFG4_ULBT_4BEAT_BURST (0x2u << 0)
138#define MATRIX_MCFG4_ULBT_8BEAT_BURST (0x3u << 0)
139#define MATRIX_MCFG4_ULBT_16BEAT_BURST (0x4u << 0)
140#define MATRIX_MCFG4_ULBT_32BEAT_BURST (0x5u << 0)
141#define MATRIX_MCFG4_ULBT_64BEAT_BURST (0x6u << 0)
142#define MATRIX_MCFG4_ULBT_128BEAT_BURST (0x7u << 0)
143/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */
144#define MATRIX_MCFG5_ULBT_Pos 0
145#define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos)
146#define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos)))
147#define MATRIX_MCFG5_ULBT_UNLTD_LENGTH (0x0u << 0)
148#define MATRIX_MCFG5_ULBT_SINGLE_ACCESS (0x1u << 0)
149#define MATRIX_MCFG5_ULBT_4BEAT_BURST (0x2u << 0)
150#define MATRIX_MCFG5_ULBT_8BEAT_BURST (0x3u << 0)
151#define MATRIX_MCFG5_ULBT_16BEAT_BURST (0x4u << 0)
152#define MATRIX_MCFG5_ULBT_32BEAT_BURST (0x5u << 0)
153#define MATRIX_MCFG5_ULBT_64BEAT_BURST (0x6u << 0)
154#define MATRIX_MCFG5_ULBT_128BEAT_BURST (0x7u << 0)
155/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */
156#define MATRIX_MCFG6_ULBT_Pos 0
157#define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos)
158#define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos)))
159#define MATRIX_MCFG6_ULBT_UNLTD_LENGTH (0x0u << 0)
160#define MATRIX_MCFG6_ULBT_SINGLE_ACCESS (0x1u << 0)
161#define MATRIX_MCFG6_ULBT_4BEAT_BURST (0x2u << 0)
162#define MATRIX_MCFG6_ULBT_8BEAT_BURST (0x3u << 0)
163#define MATRIX_MCFG6_ULBT_16BEAT_BURST (0x4u << 0)
164#define MATRIX_MCFG6_ULBT_32BEAT_BURST (0x5u << 0)
165#define MATRIX_MCFG6_ULBT_64BEAT_BURST (0x6u << 0)
166#define MATRIX_MCFG6_ULBT_128BEAT_BURST (0x7u << 0)
167/* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */
168#define MATRIX_MCFG8_ULBT_Pos 0
169#define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos)
170#define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos)))
171#define MATRIX_MCFG8_ULBT_UNLTD_LENGTH (0x0u << 0)
172#define MATRIX_MCFG8_ULBT_SINGLE_ACCESS (0x1u << 0)
173#define MATRIX_MCFG8_ULBT_4BEAT_BURST (0x2u << 0)
174#define MATRIX_MCFG8_ULBT_8BEAT_BURST (0x3u << 0)
175#define MATRIX_MCFG8_ULBT_16BEAT_BURST (0x4u << 0)
176#define MATRIX_MCFG8_ULBT_32BEAT_BURST (0x5u << 0)
177#define MATRIX_MCFG8_ULBT_64BEAT_BURST (0x6u << 0)
178#define MATRIX_MCFG8_ULBT_128BEAT_BURST (0x7u << 0)
179/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
180#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
181#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos)
182#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
183#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
184#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos)
185#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
186#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16)
187#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16)
188#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16)
189#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
190#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos)
191#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
192/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
193#define MATRIX_PRAS0_M0PR_Pos 0
194#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos)
195#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
196#define MATRIX_PRAS0_M1PR_Pos 4
197#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos)
198#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
199#define MATRIX_PRAS0_M2PR_Pos 8
200#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos)
201#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
202#define MATRIX_PRAS0_M3PR_Pos 12
203#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos)
204#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
205#define MATRIX_PRAS0_M4PR_Pos 16
206#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos)
207#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
208#define MATRIX_PRAS0_M5PR_Pos 20
209#define MATRIX_PRAS0_M5PR_Msk (0x3u << MATRIX_PRAS0_M5PR_Pos)
210#define MATRIX_PRAS0_M5PR(value) ((MATRIX_PRAS0_M5PR_Msk & ((value) << MATRIX_PRAS0_M5PR_Pos)))
211#define MATRIX_PRAS0_M6PR_Pos 24
212#define MATRIX_PRAS0_M6PR_Msk (0x3u << MATRIX_PRAS0_M6PR_Pos)
213#define MATRIX_PRAS0_M6PR(value) ((MATRIX_PRAS0_M6PR_Msk & ((value) << MATRIX_PRAS0_M6PR_Pos)))
214/* -------- MATRIX_PRBS0 : (MATRIX Offset: 0x0084) Priority Register B for Slave 0 -------- */
215#define MATRIX_PRBS0_M8PR_Pos 0
216#define MATRIX_PRBS0_M8PR_Msk (0x3u << MATRIX_PRBS0_M8PR_Pos)
217#define MATRIX_PRBS0_M8PR(value) ((MATRIX_PRBS0_M8PR_Msk & ((value) << MATRIX_PRBS0_M8PR_Pos)))
218/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
219#define MATRIX_PRAS1_M0PR_Pos 0
220#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos)
221#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
222#define MATRIX_PRAS1_M1PR_Pos 4
223#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos)
224#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
225#define MATRIX_PRAS1_M2PR_Pos 8
226#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos)
227#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
228#define MATRIX_PRAS1_M3PR_Pos 12
229#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos)
230#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
231#define MATRIX_PRAS1_M4PR_Pos 16
232#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos)
233#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
234#define MATRIX_PRAS1_M5PR_Pos 20
235#define MATRIX_PRAS1_M5PR_Msk (0x3u << MATRIX_PRAS1_M5PR_Pos)
236#define MATRIX_PRAS1_M5PR(value) ((MATRIX_PRAS1_M5PR_Msk & ((value) << MATRIX_PRAS1_M5PR_Pos)))
237#define MATRIX_PRAS1_M6PR_Pos 24
238#define MATRIX_PRAS1_M6PR_Msk (0x3u << MATRIX_PRAS1_M6PR_Pos)
239#define MATRIX_PRAS1_M6PR(value) ((MATRIX_PRAS1_M6PR_Msk & ((value) << MATRIX_PRAS1_M6PR_Pos)))
240/* -------- MATRIX_PRBS1 : (MATRIX Offset: 0x008C) Priority Register B for Slave 1 -------- */
241#define MATRIX_PRBS1_M8PR_Pos 0
242#define MATRIX_PRBS1_M8PR_Msk (0x3u << MATRIX_PRBS1_M8PR_Pos)
243#define MATRIX_PRBS1_M8PR(value) ((MATRIX_PRBS1_M8PR_Msk & ((value) << MATRIX_PRBS1_M8PR_Pos)))
244/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
245#define MATRIX_PRAS2_M0PR_Pos 0
246#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos)
247#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
248#define MATRIX_PRAS2_M1PR_Pos 4
249#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos)
250#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
251#define MATRIX_PRAS2_M2PR_Pos 8
252#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos)
253#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
254#define MATRIX_PRAS2_M3PR_Pos 12
255#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos)
256#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
257#define MATRIX_PRAS2_M4PR_Pos 16
258#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos)
259#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
260#define MATRIX_PRAS2_M5PR_Pos 20
261#define MATRIX_PRAS2_M5PR_Msk (0x3u << MATRIX_PRAS2_M5PR_Pos)
262#define MATRIX_PRAS2_M5PR(value) ((MATRIX_PRAS2_M5PR_Msk & ((value) << MATRIX_PRAS2_M5PR_Pos)))
263#define MATRIX_PRAS2_M6PR_Pos 24
264#define MATRIX_PRAS2_M6PR_Msk (0x3u << MATRIX_PRAS2_M6PR_Pos)
265#define MATRIX_PRAS2_M6PR(value) ((MATRIX_PRAS2_M6PR_Msk & ((value) << MATRIX_PRAS2_M6PR_Pos)))
266/* -------- MATRIX_PRBS2 : (MATRIX Offset: 0x0094) Priority Register B for Slave 2 -------- */
267#define MATRIX_PRBS2_M8PR_Pos 0
268#define MATRIX_PRBS2_M8PR_Msk (0x3u << MATRIX_PRBS2_M8PR_Pos)
269#define MATRIX_PRBS2_M8PR(value) ((MATRIX_PRBS2_M8PR_Msk & ((value) << MATRIX_PRBS2_M8PR_Pos)))
270/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
271#define MATRIX_PRAS3_M0PR_Pos 0
272#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos)
273#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
274#define MATRIX_PRAS3_M1PR_Pos 4
275#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos)
276#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
277#define MATRIX_PRAS3_M2PR_Pos 8
278#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos)
279#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
280#define MATRIX_PRAS3_M3PR_Pos 12
281#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos)
282#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
283#define MATRIX_PRAS3_M4PR_Pos 16
284#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos)
285#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
286#define MATRIX_PRAS3_M5PR_Pos 20
287#define MATRIX_PRAS3_M5PR_Msk (0x3u << MATRIX_PRAS3_M5PR_Pos)
288#define MATRIX_PRAS3_M5PR(value) ((MATRIX_PRAS3_M5PR_Msk & ((value) << MATRIX_PRAS3_M5PR_Pos)))
289#define MATRIX_PRAS3_M6PR_Pos 24
290#define MATRIX_PRAS3_M6PR_Msk (0x3u << MATRIX_PRAS3_M6PR_Pos)
291#define MATRIX_PRAS3_M6PR(value) ((MATRIX_PRAS3_M6PR_Msk & ((value) << MATRIX_PRAS3_M6PR_Pos)))
292/* -------- MATRIX_PRBS3 : (MATRIX Offset: 0x009C) Priority Register B for Slave 3 -------- */
293#define MATRIX_PRBS3_M8PR_Pos 0
294#define MATRIX_PRBS3_M8PR_Msk (0x3u << MATRIX_PRBS3_M8PR_Pos)
295#define MATRIX_PRBS3_M8PR(value) ((MATRIX_PRBS3_M8PR_Msk & ((value) << MATRIX_PRBS3_M8PR_Pos)))
296/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
297#define MATRIX_PRAS4_M0PR_Pos 0
298#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos)
299#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
300#define MATRIX_PRAS4_M1PR_Pos 4
301#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos)
302#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
303#define MATRIX_PRAS4_M2PR_Pos 8
304#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos)
305#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
306#define MATRIX_PRAS4_M3PR_Pos 12
307#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos)
308#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
309#define MATRIX_PRAS4_M4PR_Pos 16
310#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos)
311#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
312#define MATRIX_PRAS4_M5PR_Pos 20
313#define MATRIX_PRAS4_M5PR_Msk (0x3u << MATRIX_PRAS4_M5PR_Pos)
314#define MATRIX_PRAS4_M5PR(value) ((MATRIX_PRAS4_M5PR_Msk & ((value) << MATRIX_PRAS4_M5PR_Pos)))
315#define MATRIX_PRAS4_M6PR_Pos 24
316#define MATRIX_PRAS4_M6PR_Msk (0x3u << MATRIX_PRAS4_M6PR_Pos)
317#define MATRIX_PRAS4_M6PR(value) ((MATRIX_PRAS4_M6PR_Msk & ((value) << MATRIX_PRAS4_M6PR_Pos)))
318/* -------- MATRIX_PRBS4 : (MATRIX Offset: 0x00A4) Priority Register B for Slave 4 -------- */
319#define MATRIX_PRBS4_M8PR_Pos 0
320#define MATRIX_PRBS4_M8PR_Msk (0x3u << MATRIX_PRBS4_M8PR_Pos)
321#define MATRIX_PRBS4_M8PR(value) ((MATRIX_PRBS4_M8PR_Msk & ((value) << MATRIX_PRBS4_M8PR_Pos)))
322/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */
323#define MATRIX_PRAS5_M0PR_Pos 0
324#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos)
325#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos)))
326#define MATRIX_PRAS5_M1PR_Pos 4
327#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos)
328#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos)))
329#define MATRIX_PRAS5_M2PR_Pos 8
330#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos)
331#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos)))
332#define MATRIX_PRAS5_M3PR_Pos 12
333#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos)
334#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos)))
335#define MATRIX_PRAS5_M4PR_Pos 16
336#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos)
337#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos)))
338#define MATRIX_PRAS5_M5PR_Pos 20
339#define MATRIX_PRAS5_M5PR_Msk (0x3u << MATRIX_PRAS5_M5PR_Pos)
340#define MATRIX_PRAS5_M5PR(value) ((MATRIX_PRAS5_M5PR_Msk & ((value) << MATRIX_PRAS5_M5PR_Pos)))
341#define MATRIX_PRAS5_M6PR_Pos 24
342#define MATRIX_PRAS5_M6PR_Msk (0x3u << MATRIX_PRAS5_M6PR_Pos)
343#define MATRIX_PRAS5_M6PR(value) ((MATRIX_PRAS5_M6PR_Msk & ((value) << MATRIX_PRAS5_M6PR_Pos)))
344/* -------- MATRIX_PRBS5 : (MATRIX Offset: 0x00AC) Priority Register B for Slave 5 -------- */
345#define MATRIX_PRBS5_M8PR_Pos 0
346#define MATRIX_PRBS5_M8PR_Msk (0x3u << MATRIX_PRBS5_M8PR_Pos)
347#define MATRIX_PRBS5_M8PR(value) ((MATRIX_PRBS5_M8PR_Msk & ((value) << MATRIX_PRBS5_M8PR_Pos)))
348/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */
349#define MATRIX_PRAS6_M0PR_Pos 0
350#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos)
351#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos)))
352#define MATRIX_PRAS6_M1PR_Pos 4
353#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos)
354#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos)))
355#define MATRIX_PRAS6_M2PR_Pos 8
356#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos)
357#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos)))
358#define MATRIX_PRAS6_M3PR_Pos 12
359#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos)
360#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos)))
361#define MATRIX_PRAS6_M4PR_Pos 16
362#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos)
363#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos)))
364#define MATRIX_PRAS6_M5PR_Pos 20
365#define MATRIX_PRAS6_M5PR_Msk (0x3u << MATRIX_PRAS6_M5PR_Pos)
366#define MATRIX_PRAS6_M5PR(value) ((MATRIX_PRAS6_M5PR_Msk & ((value) << MATRIX_PRAS6_M5PR_Pos)))
367#define MATRIX_PRAS6_M6PR_Pos 24
368#define MATRIX_PRAS6_M6PR_Msk (0x3u << MATRIX_PRAS6_M6PR_Pos)
369#define MATRIX_PRAS6_M6PR(value) ((MATRIX_PRAS6_M6PR_Msk & ((value) << MATRIX_PRAS6_M6PR_Pos)))
370/* -------- MATRIX_PRBS6 : (MATRIX Offset: 0x00B4) Priority Register B for Slave 6 -------- */
371#define MATRIX_PRBS6_M8PR_Pos 0
372#define MATRIX_PRBS6_M8PR_Msk (0x3u << MATRIX_PRBS6_M8PR_Pos)
373#define MATRIX_PRBS6_M8PR(value) ((MATRIX_PRBS6_M8PR_Msk & ((value) << MATRIX_PRBS6_M8PR_Pos)))
374/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */
375#define MATRIX_PRAS7_M0PR_Pos 0
376#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos)
377#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos)))
378#define MATRIX_PRAS7_M1PR_Pos 4
379#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos)
380#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos)))
381#define MATRIX_PRAS7_M2PR_Pos 8
382#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos)
383#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos)))
384#define MATRIX_PRAS7_M3PR_Pos 12
385#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos)
386#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos)))
387#define MATRIX_PRAS7_M4PR_Pos 16
388#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos)
389#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos)))
390#define MATRIX_PRAS7_M5PR_Pos 20
391#define MATRIX_PRAS7_M5PR_Msk (0x3u << MATRIX_PRAS7_M5PR_Pos)
392#define MATRIX_PRAS7_M5PR(value) ((MATRIX_PRAS7_M5PR_Msk & ((value) << MATRIX_PRAS7_M5PR_Pos)))
393#define MATRIX_PRAS7_M6PR_Pos 24
394#define MATRIX_PRAS7_M6PR_Msk (0x3u << MATRIX_PRAS7_M6PR_Pos)
395#define MATRIX_PRAS7_M6PR(value) ((MATRIX_PRAS7_M6PR_Msk & ((value) << MATRIX_PRAS7_M6PR_Pos)))
396/* -------- MATRIX_PRBS7 : (MATRIX Offset: 0x00BC) Priority Register B for Slave 7 -------- */
397#define MATRIX_PRBS7_M8PR_Pos 0
398#define MATRIX_PRBS7_M8PR_Msk (0x3u << MATRIX_PRBS7_M8PR_Pos)
399#define MATRIX_PRBS7_M8PR(value) ((MATRIX_PRBS7_M8PR_Msk & ((value) << MATRIX_PRBS7_M8PR_Pos)))
400/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */
401#define MATRIX_PRAS8_M0PR_Pos 0
402#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos)
403#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos)))
404#define MATRIX_PRAS8_M1PR_Pos 4
405#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos)
406#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos)))
407#define MATRIX_PRAS8_M2PR_Pos 8
408#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos)
409#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos)))
410#define MATRIX_PRAS8_M3PR_Pos 12
411#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos)
412#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos)))
413#define MATRIX_PRAS8_M4PR_Pos 16
414#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos)
415#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos)))
416#define MATRIX_PRAS8_M5PR_Pos 20
417#define MATRIX_PRAS8_M5PR_Msk (0x3u << MATRIX_PRAS8_M5PR_Pos)
418#define MATRIX_PRAS8_M5PR(value) ((MATRIX_PRAS8_M5PR_Msk & ((value) << MATRIX_PRAS8_M5PR_Pos)))
419#define MATRIX_PRAS8_M6PR_Pos 24
420#define MATRIX_PRAS8_M6PR_Msk (0x3u << MATRIX_PRAS8_M6PR_Pos)
421#define MATRIX_PRAS8_M6PR(value) ((MATRIX_PRAS8_M6PR_Msk & ((value) << MATRIX_PRAS8_M6PR_Pos)))
422/* -------- MATRIX_PRBS8 : (MATRIX Offset: 0x00C4) Priority Register B for Slave 8 -------- */
423#define MATRIX_PRBS8_M8PR_Pos 0
424#define MATRIX_PRBS8_M8PR_Msk (0x3u << MATRIX_PRBS8_M8PR_Pos)
425#define MATRIX_PRBS8_M8PR(value) ((MATRIX_PRBS8_M8PR_Msk & ((value) << MATRIX_PRBS8_M8PR_Pos)))
426/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
427#define MATRIX_MRCR_RCB0 (0x1u << 0)
428#define MATRIX_MRCR_RCB1 (0x1u << 1)
429#define MATRIX_MRCR_RCB2 (0x1u << 2)
430#define MATRIX_MRCR_RCB3 (0x1u << 3)
431#define MATRIX_MRCR_RCB4 (0x1u << 4)
432#define MATRIX_MRCR_RCB5 (0x1u << 5)
433#define MATRIX_MRCR_RCB6 (0x1u << 6)
434#define MATRIX_MRCR_RCB8 (0x1u << 8)
435/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration Register -------- */
436#define CCFG_SYSIO_SYSIO4 (0x1u << 4)
437#define CCFG_SYSIO_SYSIO5 (0x1u << 5)
438#define CCFG_SYSIO_SYSIO6 (0x1u << 6)
439#define CCFG_SYSIO_SYSIO7 (0x1u << 7)
440#define CCFG_SYSIO_SYSIO12 (0x1u << 12)
441/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */
442#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0)
443#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1)
444#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2)
445#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3)
446#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4)
447/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */
448#define MATRIX_WPMR_WPEN (0x1u << 0)
449#define MATRIX_WPMR_WPKEY_Pos 8
450#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos)
451#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
452#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8)
453/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */
454#define MATRIX_WPSR_WPVS (0x1u << 0)
455#define MATRIX_WPSR_WPVSRC_Pos 8
456#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos)
459
460
461#endif /* _SAMS70_MATRIX_COMPONENT_ */
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Matrix
Matrix hardware registers.
Definition: component_matrix.h:47
Matrix::MATRIX_PRAS2
__IO uint32_t MATRIX_PRAS2
(Matrix Offset: 0x0090) Priority Register A for Slave 2
Definition: component_matrix.h:58
Matrix::MATRIX_PRAS7
__IO uint32_t MATRIX_PRAS7
(Matrix Offset: 0x00B8) Priority Register A for Slave 7
Definition: component_matrix.h:68
Matrix::MATRIX_PRBS5
__IO uint32_t MATRIX_PRBS5
(Matrix Offset: 0x00AC) Priority Register B for Slave 5
Definition: component_matrix.h:65
Matrix::MATRIX_PRAS0
__IO uint32_t MATRIX_PRAS0
(Matrix Offset: 0x0080) Priority Register A for Slave 0
Definition: component_matrix.h:54
Matrix::MATRIX_PRBS3
__IO uint32_t MATRIX_PRBS3
(Matrix Offset: 0x009C) Priority Register B for Slave 3
Definition: component_matrix.h:61
Matrix::MATRIX_PRBS0
__IO uint32_t MATRIX_PRBS0
(Matrix Offset: 0x0084) Priority Register B for Slave 0
Definition: component_matrix.h:55
Matrix::MATRIX_PRBS6
__IO uint32_t MATRIX_PRBS6
(Matrix Offset: 0x00B4) Priority Register B for Slave 6
Definition: component_matrix.h:67
Matrix::MATRIX_PRAS6
__IO uint32_t MATRIX_PRAS6
(Matrix Offset: 0x00B0) Priority Register A for Slave 6
Definition: component_matrix.h:66
Matrix::MATRIX_PRBS2
__IO uint32_t MATRIX_PRBS2
(Matrix Offset: 0x0094) Priority Register B for Slave 2
Definition: component_matrix.h:59
Matrix::MATRIX_PRBS8
__IO uint32_t MATRIX_PRBS8
(Matrix Offset: 0x00C4) Priority Register B for Slave 8
Definition: component_matrix.h:71
Matrix::MATRIX_PRAS1
__IO uint32_t MATRIX_PRAS1
(Matrix Offset: 0x0088) Priority Register A for Slave 1
Definition: component_matrix.h:56
Matrix::MATRIX_PRBS4
__IO uint32_t MATRIX_PRBS4
(Matrix Offset: 0x00A4) Priority Register B for Slave 4
Definition: component_matrix.h:63
Matrix::MATRIX_PRAS8
__IO uint32_t MATRIX_PRAS8
(Matrix Offset: 0x00C0) Priority Register A for Slave 8
Definition: component_matrix.h:70
Matrix::MATRIX_PRBS1
__IO uint32_t MATRIX_PRBS1
(Matrix Offset: 0x008C) Priority Register B for Slave 1
Definition: component_matrix.h:57
Matrix::MATRIX_PRAS4
__IO uint32_t MATRIX_PRAS4
(Matrix Offset: 0x00A0) Priority Register A for Slave 4
Definition: component_matrix.h:62
Matrix::MATRIX_PRBS7
__IO uint32_t MATRIX_PRBS7
(Matrix Offset: 0x00BC) Priority Register B for Slave 7
Definition: component_matrix.h:69
Matrix::MATRIX_PRAS5
__IO uint32_t MATRIX_PRAS5
(Matrix Offset: 0x00A8) Priority Register A for Slave 5
Definition: component_matrix.h:64
Matrix::MATRIX_PRAS3
__IO uint32_t MATRIX_PRAS3
(Matrix Offset: 0x0098) Priority Register A for Slave 3
Definition: component_matrix.h:60