RTEMS: bsps/arm/atsam/include/libchip/include/same70/component/component_uart.h Source File

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component_uart.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAME70_UART_COMPONENT_
31#define _SAME70_UART_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41 typedef struct {
42 __O uint32_t UART_CR;
43 __IO uint32_t UART_MR;
44 __O uint32_t UART_IER;
45 __O uint32_t UART_IDR;
46 __I uint32_t UART_IMR;
47 __I uint32_t UART_SR;
48 __I uint32_t UART_RHR;
49 __O uint32_t UART_THR;
50 __IO uint32_t UART_BRGR;
51 __IO uint32_t UART_CMPR;
52 __I uint32_t Reserved1[47];
53 __IO uint32_t UART_WPMR;
54} Uart;
55#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
56/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
57#define UART_CR_RSTRX (0x1u << 2)
58#define UART_CR_RSTTX (0x1u << 3)
59#define UART_CR_RXEN (0x1u << 4)
60#define UART_CR_RXDIS (0x1u << 5)
61#define UART_CR_TXEN (0x1u << 6)
62#define UART_CR_TXDIS (0x1u << 7)
63#define UART_CR_RSTSTA (0x1u << 8)
64#define UART_CR_REQCLR (0x1u << 12)
65/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
66#define UART_MR_FILTER (0x1u << 4)
67#define UART_MR_FILTER_DISABLED (0x0u << 4)
68#define UART_MR_FILTER_ENABLED (0x1u << 4)
69#define UART_MR_PAR_Pos 9
70#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos)
71#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos)))
72#define UART_MR_PAR_EVEN (0x0u << 9)
73#define UART_MR_PAR_ODD (0x1u << 9)
74#define UART_MR_PAR_SPACE (0x2u << 9)
75#define UART_MR_PAR_MARK (0x3u << 9)
76#define UART_MR_PAR_NO (0x4u << 9)
77#define UART_MR_BRSRCCK (0x1u << 12)
78#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12)
79#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12)
80#define UART_MR_CHMODE_Pos 14
81#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos)
82#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos)))
83#define UART_MR_CHMODE_NORMAL (0x0u << 14)
84#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14)
85#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14)
86#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14)
87/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
88#define UART_IER_RXRDY (0x1u << 0)
89#define UART_IER_TXRDY (0x1u << 1)
90#define UART_IER_OVRE (0x1u << 5)
91#define UART_IER_FRAME (0x1u << 6)
92#define UART_IER_PARE (0x1u << 7)
93#define UART_IER_TXEMPTY (0x1u << 9)
94#define UART_IER_CMP (0x1u << 15)
95/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
96#define UART_IDR_RXRDY (0x1u << 0)
97#define UART_IDR_TXRDY (0x1u << 1)
98#define UART_IDR_OVRE (0x1u << 5)
99#define UART_IDR_FRAME (0x1u << 6)
100#define UART_IDR_PARE (0x1u << 7)
101#define UART_IDR_TXEMPTY (0x1u << 9)
102#define UART_IDR_CMP (0x1u << 15)
103/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
104#define UART_IMR_RXRDY (0x1u << 0)
105#define UART_IMR_TXRDY (0x1u << 1)
106#define UART_IMR_OVRE (0x1u << 5)
107#define UART_IMR_FRAME (0x1u << 6)
108#define UART_IMR_PARE (0x1u << 7)
109#define UART_IMR_TXEMPTY (0x1u << 9)
110#define UART_IMR_CMP (0x1u << 15)
111/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
112#define UART_SR_RXRDY (0x1u << 0)
113#define UART_SR_TXRDY (0x1u << 1)
114#define UART_SR_OVRE (0x1u << 5)
115#define UART_SR_FRAME (0x1u << 6)
116#define UART_SR_PARE (0x1u << 7)
117#define UART_SR_TXEMPTY (0x1u << 9)
118#define UART_SR_CMP (0x1u << 15)
119/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
120#define UART_RHR_RXCHR_Pos 0
121#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos)
122/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
123#define UART_THR_TXCHR_Pos 0
124#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos)
125#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
126/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
127#define UART_BRGR_CD_Pos 0
128#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos)
129#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
130/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */
131#define UART_CMPR_VAL1_Pos 0
132#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos)
133#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos)))
134#define UART_CMPR_CMPMODE (0x1u << 12)
135#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12)
136#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12)
137#define UART_CMPR_CMPPAR (0x1u << 14)
138#define UART_CMPR_VAL2_Pos 16
139#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos)
140#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos)))
141/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */
142#define UART_WPMR_WPEN (0x1u << 0)
143#define UART_WPMR_WPKEY_Pos 8
144#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos)
145#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos)))
146#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8)
149
150
151#endif /* _SAME70_UART_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Uart
Uart hardware registers.
Definition: component_uart.h:41
Uart::UART_IMR
__I uint32_t UART_IMR
(Uart Offset: 0x0010) Interrupt Mask Register
Definition: component_uart.h:46
Uart::UART_IER
__O uint32_t UART_IER
(Uart Offset: 0x0008) Interrupt Enable Register
Definition: component_uart.h:44
Uart::UART_SR
__I uint32_t UART_SR
(Uart Offset: 0x0014) Status Register
Definition: component_uart.h:47
Uart::UART_RHR
__I uint32_t UART_RHR
(Uart Offset: 0x0018) Receive Holding Register
Definition: component_uart.h:48
Uart::UART_MR
__IO uint32_t UART_MR
(Uart Offset: 0x0004) Mode Register
Definition: component_uart.h:43
Uart::UART_WPMR
__IO uint32_t UART_WPMR
(Uart Offset: 0x00E4) Write Protection Mode Register
Definition: component_uart.h:53
Uart::UART_CMPR
__IO uint32_t UART_CMPR
(Uart Offset: 0x0024) Comparison Register
Definition: component_uart.h:51
Uart::UART_IDR
__O uint32_t UART_IDR
(Uart Offset: 0x000C) Interrupt Disable Register
Definition: component_uart.h:45
Uart::UART_THR
__O uint32_t UART_THR
(Uart Offset: 0x001C) Transmit Holding Register
Definition: component_uart.h:49
Uart::UART_CR
__O uint32_t UART_CR
(Uart Offset: 0x0000) Control Register
Definition: component_uart.h:42
Uart::UART_BRGR
__IO uint32_t UART_BRGR
(Uart Offset: 0x0020) Baud Rate Generator Register
Definition: component_uart.h:50