RTEMS: bsps/powerpc/include/libcpu/mmu.h Source File

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mmu.h
1/*
2 * mmu.h
3 *
4 * PowerPC memory management structures
5 *
6 * It is a stripped down version of linux ppc file...
7 *
8 * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
9 * Canon Centre Recherche France.
10 *
11 * The license and distribution terms for this file may be
12 * found in the file LICENSE in this distribution or at
13 * http://www.rtems.org/license/LICENSE.
14 */
15
16#ifndef _LIBCPU_MMU_H
17#define _LIBCPU_MMU_H
18
19#ifndef ASM
20/* Hardware Page Table Entry */
21 typedef struct _PTE {
22 unsigned long v:1; /* Entry is valid */
23 unsigned long vsid:24; /* Virtual segment identifier */
24 unsigned long h:1; /* Hash algorithm indicator */
25 unsigned long api:6; /* Abbreviated page index */
26 unsigned long rpn:20; /* Real (physical) page number */
27 unsigned long :3; /* Unused */
28 unsigned long r:1; /* Referenced */
29 unsigned long c:1; /* Changed */
30 unsigned long w:1; /* Write-thru cache mode */
31 unsigned long i:1; /* Cache inhibited */
32 unsigned long m:1; /* Memory coherence */
33 unsigned long g:1; /* Guarded */
34 unsigned long :1; /* Unused */
35 unsigned long pp:2; /* Page protection */
36} PTE;
37
38/* Values for PP (assumes Ks=0, Kp=1) */
39#define PP_RWXX 0 /* Supervisor read/write, User none */
40#define PP_RWRX 1 /* Supervisor read/write, User read */
41#define PP_RWRW 2 /* Supervisor read/write, User read/write */
42#define PP_RXRX 3 /* Supervisor read, User read */
43
44/* Segment Register */
45 typedef struct _SEGREG {
46 unsigned long t:1; /* Normal or I/O type */
47 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
48 unsigned long kp:1; /* User 'key' (normally 1) */
49 unsigned long n:1; /* No-execute */
50 unsigned long :4; /* Unused */
51 unsigned long vsid:24; /* Virtual Segment Identifier */
52} SEGREG;
53
54/* Block Address Translation (BAT) Registers */
55 typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
56 unsigned long bepi:15; /* Effective page index (virtual address) */
57 unsigned long :8; /* unused */
58 unsigned long w:1;
59 unsigned long i:1; /* Cache inhibit */
60 unsigned long m:1; /* Memory coherence */
61 unsigned long ks:1; /* Supervisor key (normally 0) */
62 unsigned long kp:1; /* User key (normally 1) */
63 unsigned long pp:2; /* Page access protections */
64} P601_BATU;
65
66 typedef struct _BATU { /* Upper part of BAT (all except 601) */
67 unsigned long bepi:15; /* Effective page index (virtual address) */
68 unsigned long :4; /* Unused */
69 unsigned long bl:11; /* Block size mask */
70 unsigned long vs:1; /* Supervisor valid */
71 unsigned long vp:1; /* User valid */
72} BATU;
73
74 typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
75 unsigned long brpn:15; /* Real page index (physical address) */
76 unsigned long :10; /* Unused */
77 unsigned long v:1; /* Valid bit */
78 unsigned long bl:6; /* Block size mask */
79} P601_BATL;
80
81 typedef struct _BATL { /* Lower part of BAT (all except 601) */
82 unsigned long brpn:15; /* Real page index (physical address) */
83 unsigned long :10; /* Unused */
84 unsigned long w:1; /* Write-thru cache */
85 unsigned long i:1; /* Cache inhibit */
86 unsigned long m:1; /* Memory coherence */
87 unsigned long g:1; /* Guarded (MBZ in IBAT) */
88 unsigned long :1; /* Unused */
89 unsigned long pp:2; /* Page access protections */
90} BATL;
91
92 typedef struct _BAT {
93 BATU batu; /* Upper register */
94 BATL batl; /* Lower register */
95} BAT;
96
97 typedef struct _P601_BAT {
98 P601_BATU batu; /* Upper register */
99 P601_BATL batl; /* Lower register */
100} P601_BAT;
101
102/* Block size masks */
103#define BL_128K 0x000
104#define BL_256K 0x001
105#define BL_512K 0x003
106#define BL_1M 0x007
107#define BL_2M 0x00F
108#define BL_4M 0x01F
109#define BL_8M 0x03F
110#define BL_16M 0x07F
111#define BL_32M 0x0FF
112#define BL_64M 0x1FF
113#define BL_128M 0x3FF
114#define BL_256M 0x7FF
115
116/* BAT Access Protection */
117#define BPP_XX 0x00 /* No access */
118#define BPP_RX 0x01 /* Read only */
119#define BPP_RW 0x02 /* Read/write */
120
121/*
122 * Simulated two-level MMU. This structure is used by the kernel
123 * to keep track of MMU mappings and is used to update/maintain
124 * the hardware HASH table which is really a cache of mappings.
125 *
126 * The simulated structures mimic the hardware available on other
127 * platforms, notably the 80x86 and 680x0.
128 */
129
130 typedef struct _pte {
131 unsigned long page_num:20;
132 unsigned long flags:12; /* Page flags (some unused bits) */
133} pte;
134
135#define PD_SHIFT (10+12) /* Page directory */
136#define PD_MASK 0x03FF
137#define PT_SHIFT (12) /* Page Table */
138#define PT_MASK 0x03FF
139#define PG_SHIFT (12) /* Page Entry */
140
141
142/* MMU context */
143
144 typedef struct _MMU_context {
145 SEGREG segs[16]; /* Segment registers */
146 pte **pmap; /* Two-level page-map structure */
147} MMU_context;
148
149/* Used to set up SDR1 register */
150#define HASH_TABLE_SIZE_64K 0x00010000
151#define HASH_TABLE_SIZE_128K 0x00020000
152#define HASH_TABLE_SIZE_256K 0x00040000
153#define HASH_TABLE_SIZE_512K 0x00080000
154#define HASH_TABLE_SIZE_1M 0x00100000
155#define HASH_TABLE_SIZE_2M 0x00200000
156#define HASH_TABLE_SIZE_4M 0x00400000
157#define HASH_TABLE_MASK_64K 0x000
158#define HASH_TABLE_MASK_128K 0x001
159#define HASH_TABLE_MASK_256K 0x003
160#define HASH_TABLE_MASK_512K 0x007
161#define HASH_TABLE_MASK_1M 0x00F
162#define HASH_TABLE_MASK_2M 0x01F
163#define HASH_TABLE_MASK_4M 0x03F
164
165/* invalidate a TLB entry */
166static inline void _tlbie(unsigned long va)
167{
168 asm volatile ("tlbie %0" : : "r"(va));
169}
170
171extern void _tlbia(void); /* invalidate all TLB entries */
172#endif /* ASM */
173
174/* Control/status registers for the MPC8xx.
175 * A write operation to these registers causes serialized access.
176 * During software tablewalk, the registers used perform mask/shift-add
177 * operations when written/read. A TLB entry is created when the Mx_RPN
178 * is written, and the contents of several registers are used to
179 * create the entry.
180 */
181#define MI_CTR 784 /* Instruction TLB control register */
182#define MI_GPM 0x80000000 /* Set domain manager mode */
183#define MI_PPM 0x40000000 /* Set subpage protection */
184#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
185#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
186#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
187#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
188#define MI_RESETVAL 0x00000000 /* Value of register at reset */
189
190/* These are the Ks and Kp from the PowerPC books. For proper operation,
191 * Ks = 0, Kp = 1.
192 */
193#define MI_AP 786
194#define MI_Ks 0x80000000 /* Should not be set */
195#define MI_Kp 0x40000000 /* Should always be set */
196
197/* The effective page number register. When read, contains the information
198 * about the last instruction TLB miss. When MI_RPN is written, bits in
199 * this register are used to create the TLB entry.
200 */
201#define MI_EPN 787
202#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
203#define MI_EVALID 0x00000200 /* Entry is valid */
204#define MI_ASIDMASK 0x0000000f /* ASID match value */
205 /* Reset value is undefined */
206
207/* A "level 1" or "segment" or whatever you want to call it register.
208 * For the instruction TLB, it contains bits that get loaded into the
209 * TLB entry when the MI_RPN is written.
210 */
211#define MI_TWC 789
212#define MI_APG 0x000001e0 /* Access protection group (0) */
213#define MI_GUARDED 0x00000010 /* Guarded storage */
214#define MI_PSMASK 0x0000000c /* Mask of page size bits */
215#define MI_PS8MEG 0x0000000c /* 8M page size */
216#define MI_PS512K 0x00000004 /* 512K page size */
217#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
218#define MI_SVALID 0x00000001 /* Segment entry is valid */
219 /* Reset value is undefined */
220
221/* Real page number. Defined by the pte. Writing this register
222 * causes a TLB entry to be created for the instruction TLB, using
223 * additional information from the MI_EPN, and MI_TWC registers.
224 */
225#define MI_RPN 790
226
227/* Define an RPN value for mapping kernel memory to large virtual
228 * pages for boot initialization. This has real page number of 0,
229 * large page size, shared page, cache enabled, and valid.
230 * Also mark all subpages valid and write access.
231 */
232#define MI_BOOTINIT 0x000001fd
233
234#define MD_CTR 792 /* Data TLB control register */
235#define MD_GPM 0x80000000 /* Set domain manager mode */
236#define MD_PPM 0x40000000 /* Set subpage protection */
237#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
238#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
239#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
240#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
241#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
242#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
243#define MD_RESETVAL 0x04000000 /* Value of register at reset */
244
245#define M_CASID 793 /* Address space ID (context) to match */
246#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
247
248
249/* These are the Ks and Kp from the PowerPC books. For proper operation,
250 * Ks = 0, Kp = 1.
251 */
252#define MD_AP 794
253#define MD_Ks 0x80000000 /* Should not be set */
254#define MD_Kp 0x40000000 /* Should always be set */
255
256/* The effective page number register. When read, contains the information
257 * about the last instruction TLB miss. When MD_RPN is written, bits in
258 * this register are used to create the TLB entry.
259 */
260#define MD_EPN 795
261#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
262#define MD_EVALID 0x00000200 /* Entry is valid */
263#define MD_ASIDMASK 0x0000000f /* ASID match value */
264 /* Reset value is undefined */
265
266/* The pointer to the base address of the first level page table.
267 * During a software tablewalk, reading this register provides the address
268 * of the entry associated with MD_EPN.
269 */
270#define M_TWB 796
271#define M_L1TB 0xfffff000 /* Level 1 table base address */
272#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
273 /* Reset value is undefined */
274
275/* A "level 1" or "segment" or whatever you want to call it register.
276 * For the data TLB, it contains bits that get loaded into the TLB entry
277 * when the MD_RPN is written. It is also provides the hardware assist
278 * for finding the PTE address during software tablewalk.
279 */
280#define MD_TWC 797
281#define MD_L2TB 0xfffff000 /* Level 2 table base address */
282#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
283#define MD_APG 0x000001e0 /* Access protection group (0) */
284#define MD_GUARDED 0x00000010 /* Guarded storage */
285#define MD_PSMASK 0x0000000c /* Mask of page size bits */
286#define MD_PS8MEG 0x0000000c /* 8M page size */
287#define MD_PS512K 0x00000004 /* 512K page size */
288#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
289#define MD_WT 0x00000002 /* Use writethrough page attribute */
290#define MD_SVALID 0x00000001 /* Segment entry is valid */
291 /* Reset value is undefined */
292
293
294/* Real page number. Defined by the pte. Writing this register
295 * causes a TLB entry to be created for the data TLB, using
296 * additional information from the MD_EPN, and MD_TWC registers.
297 */
298#define MD_RPN 798
299
300/* This is a temporary storage register that could be used to save
301 * a processor working register during a tablewalk.
302 */
303#define M_TW 799
304#endif /* _LIBCPU_MMU_H */
_BATL
Definition: mmu.h:81
_BATU
Definition: mmu.h:66
_BAT
Definition: mmu.h:92
_MMU_context
Definition: mmu.h:144
_P601_BATL
Definition: mmu.h:74
_P601_BATU
Definition: mmu.h:55
_P601_BAT
Definition: mmu.h:97
_PTE
Definition: mmu.h:21
_SEGREG
Definition: mmu.h:45
_pte
Definition: mmu.h:130