RTEMS 5.3
bf533.h
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1
15/*
16 * COPYRIGHT (c) 2006.
17 * Atos Automacao Industrial LTDA.
18 * modified by Alain Schaefer <alain.schaefer@easc.ch>
19 * and Antonio Giovanini <antonio@atos.com.br>
20 *
21 * The license and distribution terms for this file may be
22 * found in the file LICENSE in this distribution or at
23 * http://www.rtems.org/license/LICENSE.
24 *
25 */
26
27#ifndef _RTEMS_BFIN_533_H
28#define _RTEMS_BFIN_533_H
29
30#include <rtems/bfin/bfin.h>
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
36
37/* Clock and System Control Chapter 8 */
38#define PLL_CTL 0xFFC00000L
39#define PLL_DIV 0xFFC00004L
40#define VR_CTL 0xFFC00008L
41#define PLL_STAT 0xFFC0000CL
42#define PLL_LOCKCNT 0xFFC00010L
43#define SWRST 0xFFC00100L
44#define SYSCR 0xFFC00104L
45
46/* SPI Controller Chapter 10 */
47#define SPI_CTL 0xFFC00500L
48#define SPI_FLG 0xFFC00504L
49#define SPI_STAT 0xFFC00508L
50#define SPI_TDBR 0xFFC0050CL
51#define SPI_RDBR 0xFFC00510L
52#define SPI_BAUD 0xFFC00514L
53#define SPI_SHADOW 0xFFC00518L
54
55/* SPORT0 Controller */
56#define SPORT0_TCR1 0xFFC00800L
57#define SPORT0_TCR2 0xFFC00804L
58#define SPORT0_TCLKDIV 0xFFC00808L
59#define SPORT0_TFSDIV 0xFFC0080CL
60#define SPORT0_TX 0xFFC00810L
61#define SPORT0_RX 0xFFC00818L
62#define SPORT0_RCR1 0xFFC00820L
63#define SPORT0_RCR2 0xFFC00824L
64#define SPORT0_RCLKDIV 0xFFC00828L
65#define SPORT0_RFSDIV 0xFFC0082CL
66#define SPORT0_STAT 0xFFC00830L
67#define SPORT0_CHNL 0xFFC00834L
68#define SPORT0_MCMC1 0xFFC00838L
69#define SPORT0_MCMC2 0xFFC0083CL
70#define SPORT0_MTCS0 0xFFC00840L
71#define SPORT0_MTCS1 0xFFC00844L
72#define SPORT0_MTCS2 0xFFC00848L
73#define SPORT0_MTCS3 0xFFC0084CL
74#define SPORT0_MRCS0 0xFFC00850L
75#define SPORT0_MRCS1 0xFFC00854L
76#define SPORT0_MRCS2 0xFFC00858L
77#define SPORT0_MRCS3 0xFFC0085CL
78
79/* Parallel Peripheral Interface (PPI) Chapter 11 */
80
81#define PPI_CONTROL 0xFFC01000L
82#define PPI_STATUS 0xFFC01004L
83#define PPI_COUNT 0xFFC01008L
84#define PPI_DELAY 0xFFC0100CL
85#define PPI_FRAME 0xFFC01010L
86
87/********* PPI MASKS ***********/
88/* PPI_CONTROL Masks */
89#define PORT_EN 0x00000001
90#define PORT_DIR 0x00000002
91#define XFR_TYPE 0x0000000C
92#define PORT_CFG 0x00000030
93#define FLD_SEL 0x00000040
94#define PACK_EN 0x00000080
95#define DMA32 0x00000100
96#define SKIP_EN 0x00000200
97#define SKIP_EO 0x00000400
98#define DLENGTH 0x00003800
99#define DLEN_8 0x0
100#define DLEN(x) (((x-9) & 0x07) << 11)
101#define POL 0x0000C000
102
103/* PPI_STATUS Masks */
104#define FLD 0x00000400
105#define FT_ERR 0x00000800
106#define OVR 0x00001000
107#define UNDR 0x00002000
108#define ERR_DET 0x00004000
109#define ERR_NCOR 0x00008000
110
111/* SPORT1 Controller Chapter 12 */
112#define SPORT1_TCR1 0xFFC00900L
113#define SPORT1_TCR2 0xFFC00904L
114#define SPORT1_TCLKDIV 0xFFC00908L
115#define SPORT1_TFSDIV 0xFFC0090CL
116#define SPORT1_TX 0xFFC00910L
117#define SPORT1_RX 0xFFC00918L
118#define SPORT1_RCR1 0xFFC00920L
119#define SPORT1_RCR2 0xFFC00924L
120#define SPORT1_RCLKDIV 0xFFC00928L
121#define SPORT1_RFSDIV 0xFFC0092CL
122#define SPORT1_STAT 0xFFC00930L
123#define SPORT1_CHNL 0xFFC00934L
124#define SPORT1_MCMC1 0xFFC00938L
125#define SPORT1_MCMC2 0xFFC0093CL
126#define SPORT1_MTCS0 0xFFC00940L
127#define SPORT1_MTCS1 0xFFC00944L
128#define SPORT1_MTCS2 0xFFC00948L
129#define SPORT1_MTCS3 0xFFC0094CL
130#define SPORT1_MRCS0 0xFFC00950L
131#define SPORT1_MRCS1 0xFFC00954L
132#define SPORT1_MRCS2 0xFFC00958L
133#define SPORT1_MRCS3 0xFFC0095CL
134
135/* SPORTx_TCR1 Masks */
136#define TSPEN 0x0001
137#define ITCLK 0x0002
138#define TDTYPE 0x000C
139#define TLSBIT 0x0010
140#define ITFS 0x0200
141#define TFSR 0x0400
142#define DITFS 0x0800
143#define LTFS 0x1000
144#define LATFS 0x2000
145#define TCKFE 0x4000
146
147/* SPORTx_TCR2 Masks */
148#define SLEN 0x001F
149#define TXSE 0x0100
150#define TSFSE 0x0200
151#define TRFST 0x0400
152
153/* SPORTx_RCR1 Masks */
154#define RSPEN 0x0001
155#define IRCLK 0x0002
156#define RDTYPE 0x000C
157#define RULAW 0x0008
158#define RALAW 0x000C
159#define RLSBIT 0x0010
160#define IRFS 0x0200
161#define RFSR 0x0400
162#define LRFS 0x1000
163#define LARFS 0x2000
164#define RCKFE 0x4000
165
166/* SPORTx_RCR2 Masks */
167#define SLEN 0x001F
168#define RXSE 0x0100
169#define RSFSE 0x0200
170#define RRFST 0x0400
171
172/* SPORTx_STAT Masks */
173#define RXNE 0x0001
174#define RUVF 0x0002
175#define ROVF 0x0004
176#define TXF 0x0008
177#define TUVF 0x0010
178#define TOVF 0x0020
179#define TXHRE 0x0040
180
181/* SPORTx_MCMC1 Masks */
182#define WSIZE 0x0000F000
183#define WOFF 0x000003FF
184
185/* SPORTx_MCMC2 Masks */
186#define MCCRM 0x00000003
187#define MCDTXPE 0x00000004
188#define MCDRXPE 0x00000008
189#define MCMEN 0x00000010
190#define FSDR 0x00000080
191#define MFD 0x0000F000
192
193/* UART Controller Chapter 13 */
194#define UART_THR 0xFFC00400L
195#define UART_RBR 0xFFC00400L
196#define UART_DLL 0xFFC00400L
197#define UART_IER 0xFFC00404L
198#define UART_DLH 0xFFC00404L
199#define UART_IIR 0xFFC00408L
200#define UART_LCR 0xFFC0040CL
201#define UART_MCR 0xFFC00410L
202#define UART_LSR 0xFFC00414L
203#define UART_SCR 0xFFC0041CL
204#define UART_GCTL 0xFFC00424L
205
206/*
207 * UART CONTROLLER MASKS
208 */
209
210/* UART_LCR */
211#define DLAB 0x80
212#define SB 0x40
213#define STP 0x20
214#define EPS 0x10
215#define PEN 0x08
216#define STB 0x04
217#define WLS(x) ((x-5) & 0x03)
218
219#define DLAB_P 0x07
220#define SB_P 0x06
221#define STP_P 0x05
222#define EPS_P 0x04
223#define PEN_P 0x03
224#define STB_P 0x02
225#define WLS_P1 0x01
226#define WLS_P0 0x00
227
228/* UART_MCR */
229#define LOOP_ENA 0x10
230#define LOOP_ENA_P 0x04
231
232/* UART_LSR */
233#define TEMT 0x40
234#define THRE 0x20
235#define BI 0x10
236#define FE 0x08
237#define PE 0x04
238#define OE 0x02
239#define DR 0x01
240
241#define TEMP_P 0x06
242#define THRE_P 0x05
243#define BI_P 0x04
244#define FE_P 0x03
245#define PE_P 0x02
246#define OE_P 0x01
247#define DR_P 0x00
248
249/* UART_IER */
250#define ELSI 0x04
251#define ETBEI 0x02
252#define ERBFI 0x01
253
254#define ELSI_P 0x02
255#define ETBEI_P 0x01
256#define ERBFI_P 0x00
257
258/* UART_IIR */
259#define STATUS(x) ((x << 1) & 0x06)
260#define NINT 0x01
261#define STATUS_P1 0x02
262#define STATUS_P0 0x01
263#define NINT_P 0x00
264
265/* UART_GCTL */
266#define FFE 0x20
267#define FPE 0x10
268#define RPOLC 0x08
269#define TPOLC 0x04
270#define IREN 0x02
271#define UCEN 0x01
272
273#define FFE_P 0x05
274#define FPE_P 0x04
275#define RPOLC_P 0x03
276#define TPOLC_P 0x02
277#define IREN_P 0x01
278#define UCEN_P 0x00
279
280/* General Purpose IO Chapter 14*/
281#define FIO_FLAG_D 0xFFC00700L
282#define FIO_FLAG_C 0xFFC00704L
283#define FIO_FLAG_S 0xFFC00708L
284#define FIO_FLAG_T 0xFFC0070CL
285#define FIO_MASKA_D 0xFFC00710L
286#define FIO_MASKA_C 0xFFC00714L
287#define FIO_MASKA_S 0xFFC00718L
288#define FIO_MASKA_T 0xFFC0071CL
289#define FIO_MASKB_D 0xFFC00720L
290#define FIO_MASKB_C 0xFFC00724L
291#define FIO_MASKB_S 0xFFC00728L
292#define FIO_MASKB_T 0xFFC0072CL
293#define FIO_DIR 0xFFC00730L
294#define FIO_POLAR 0xFFC00734L
295#define FIO_EDGE 0xFFC00738L
296#define FIO_BOTH 0xFFC0073CL
297#define FIO_INEN 0xFFC00740L
298
299/* General Purpose IO Masks */
300#define PF0 0x0001
301#define PF1 0x0002
302#define PF2 0x0004
303#define PF3 0x0008
304#define PF4 0x0010
305#define PF5 0x0020
306#define PF6 0x0040
307#define PF7 0x0080
308#define PF8 0x0100
309#define PF9 0x0200
310#define PF10 0x0400
311#define PF11 0x0800
312#define PF12 0x1000
313#define PF13 0x2000
314#define PF14 0x4000
315#define PF15 0x8000
316
317
318/* TIMER 0, 1, 2 Chapter 15 */
319#define TIMER0_CONFIG 0xFFC00600L
320#define TIMER0_COUNTER 0xFFC00604L
321#define TIMER0_PERIOD 0xFFC00608L
322#define TIMER0_WIDTH 0xFFC0060CL
323
324#define TIMER1_CONFIG 0xFFC00610L
325#define TIMER1_COUNTER 0xFFC00614L
326#define TIMER1_PERIOD 0xFFC00618L
327#define TIMER1_WIDTH 0xFFC0061CL
328
329#define TIMER2_CONFIG 0xFFC00620L
330#define TIMER2_COUNTER 0xFFC00624L
331#define TIMER2_PERIOD 0xFFC00628L
332#define TIMER2_WIDTH 0xFFC0062CL
333
334/*
335 * These are defined in bsps/bfin/include/bf52x.h. Ensure those definitions
336 * are consistent with our expectations.
337#define TIMER_ENABLE 0xFFC00640L
338#define TIMER_DISABLE 0xFFC00644L
339#define TIMER_STATUS 0xFFC00648L
340*/
341#if ((TIMER_ENABLE != 0xFFC00640L) || \
342 (TIMER_DISABLE != 0xFFC00644L) || \
343 (TIMER_STATUS != 0xFFC00648L))
344#error "Timer register addresses are inconsistent"
345#endif
346
347/* Real Time Clock Chapter 16 */
348#define RTC_STAT 0xFFC00300L
349#define RTC_ICTL 0xFFC00304L
350#define RTC_ISTAT 0xFFC00308L
351#define RTC_SWCNT 0xFFC0030CL
352#define RTC_ALARM 0xFFC00310L
353#define RTC_FAST 0xFFC00314L
354#define RTC_PREN 0xFFC00314L
355
356/* RTC_FAST Mask (RTC_PREN Mask) */
357#define ENABLE_PRESCALE 0x00000001
358#define PREN 0x00000001
359
360/* Asynchronous Memory Controller EBUI, Chapter 17*/
361#define EBIU_AMGCTL 0xFFC00A00L
362#define EBIU_AMBCTL0 0xFFC00A04L
363#define EBIU_AMBCTL1 0xFFC00A08L
364
365/* SDRAM Controller External Bus Interface Unit */
366
367#define EBIU_SDGCTL 0xFFC00A10L
368#define EBIU_SDBCTL 0xFFC00A14L
369#define EBIU_SDRRC 0xFFC00A18L
370#define EBIU_SDSTAT 0xFFC00A1CL
371
372
373
374
375/* DCPLB_DATA and ICPLB_DATA Registers */
376/*** Bit Positions */
377#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
378#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */
379#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */
380/*** Masks */
381#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
382#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */
383#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */
384#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
385#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
386#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
387#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
388#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */
389#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */
390/*** ICPLB_DATA only */
391#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */
392/*** DCPLB_DATA only */
393#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */
394#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */
395#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
396#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */
397 /* 1= allocate cache lines on write-through writes. */
398#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
399
400
401#ifdef __cplusplus
402}
403#endif
404
405#endif /* _RTEMS_SCORE_BFIN_H */
Macros for MMR register common to all Blackfin Processors.