ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u Union Reference

#include <alt_clock_group.h>

Data Fields
union {
ALT_CLKMGR_MAINPLL_t   fld
ALT_CLKMGR_MAINPLL_raw_t   raw
}	mainpllgrp
union {
ALT_CLKMGR_PERPLL_t   fld
ALT_CLKMGR_PERPLL_raw_t   raw
}	perpllgrp
union {
ALT_CLKMGR_SDRPLL_t   fld
ALT_CLKMGR_SDRPLL_raw_t   raw
}	sdrpllgrp

Detailed Description

This union holds the register values for configuration of the set of possible clock groups on the SoC FPGA. The clkgrpsel discriminator identifies the valid clock group union data member.

Field Documentation

fld [1/3]

ALT_CLKMGR_MAINPLL_t ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u::fld

Field access.

fld [2/3]

ALT_CLKMGR_PERPLL_t ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u::fld

Field access.

fld [3/3]

ALT_CLKMGR_SDRPLL_t ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u::fld

Field access.

union { ... } ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u::mainpllgrp

Clock group configuration for Main PLL group.

union { ... } ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u::perpllgrp

Clock group configuration for Peripheral PLL group.

raw [1/3]

ALT_CLKMGR_MAINPLL_raw_t ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u::raw

Raw access.

raw [2/3]

ALT_CLKMGR_PERPLL_raw_t ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u::raw

Raw access.

raw [3/3]

ALT_CLKMGR_SDRPLL_raw_t ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u::raw

Raw access.

union { ... } ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u::sdrpllgrp

Clock group configuration for SDRAM PLL group.

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The documentation for this union was generated from the following file:

• bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h