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RTEMS
5.1
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17 #define TWI_CLKDIV_OFFSET 0x0000 18 #define TWI_CONTROL_OFFSET 0x0004 19 #define TWI_SLAVE_CTL_OFFSET 0x0008 20 #define TWI_SLAVE_STAT_OFFSET 0x000c 21 #define TWI_SLAVE_ADDR_OFFSET 0x0010 22 #define TWI_MASTER_CTL_OFFSET 0x0014 23 #define TWI_MASTER_STAT_OFFSET 0x0018 24 #define TWI_MASTER_ADDR_OFFSET 0x001c 25 #define TWI_INT_STAT_OFFSET 0x0020 26 #define TWI_INT_MASK_OFFSET 0x0024 27 #define TWI_FIFO_CTL_OFFSET 0x0028 28 #define TWI_FIFO_STAT_OFFSET 0x002c 29 #define TWI_XMT_DATA8_OFFSET 0x0080 30 #define TWI_XMT_DATA16_OFFSET 0x0084 31 #define TWI_RCV_DATA8_OFFSET 0x0088 32 #define TWI_RCV_DATA16_OFFSET 0x008c 37 #define TWI_CLKDIV_CLKHI_MASK 0xff00 38 #define TWI_CLKDIV_CLKHI_SHIFT 8 39 #define TWI_CLKDIV_CLKLOW_MASK 0x00ff 40 #define TWI_CLKDIV_CLKLOW_SHIFT 0 42 #define TWI_CONTROL_SCCB 0x0200 43 #define TWI_CONTROL_TWI_ENA 0x0080 44 #define TWI_CONTROL_PRESCALE_MASK 0x007f 45 #define TWI_CONTROL_PRESCALE_SHIFT 0 47 #define TWI_SLAVE_CTL_GEN 0x0010 48 #define TWI_SLAVE_CTL_NAK 0x0008 49 #define TWI_SLAVE_CTL_STDVAL 0x0004 50 #define TWI_SLAVE_CTL_SEN 0x0001 52 #define TWI_SLAVE_STAT_GCALL 0x0002 53 #define TWI_SLAVE_STAT_SDIR 0x0001 55 #define TWI_SLAVE_ADDR_SADDR_MASK 0x007f 56 #define TWI_SLAVE_ADDR_SADDR_SHIFT 0 58 #define TWI_MASTER_CTL_SCLOVR 0x8000 59 #define TWI_MASTER_CTL_SDAOVR 0x4000 60 #define TWI_MASTER_CTL_DCNT_MASK 0x3fc0 61 #define TWI_MASTER_CTL_DCNT_SHIFT 6 62 #define TWI_MASTER_CTL_RSTART 0x0020 63 #define TWI_MASTER_CTL_STOP 0x0010 64 #define TWI_MASTER_CTL_FAST 0x0008 65 #define TWI_MASTER_CTL_MDIR 0x0004 66 #define TWI_MASTER_CTL_MEN 0x0001 68 #define TWI_MASTER_STAT_BUSBUSY 0x0100 69 #define TWI_MASTER_STAT_SCLSEN 0x0080 70 #define TWI_MASTER_STAT_SDASEN 0x0040 71 #define TWI_MASTER_STAT_BUFWRERR 0x0020 72 #define TWI_MASTER_STAT_BUFRDERR 0x0010 73 #define TWI_MASTER_STAT_DNAK 0x0008 74 #define TWI_MASTER_STAT_ANAK 0x0004 75 #define TWI_MASTER_STAT_LOSTARB 0x0002 76 #define TWI_MASTER_STAT_MPROG 0x0001 78 #define TWI_MASTER_ADDR_MADDR_MASK 0x007f 79 #define TWI_MASTER_ADDR_MADDR_SHIFT 0 81 #define TWI_INT_STAT_RCVSERV 0x0080 82 #define TWI_INT_STAT_XMTSERV 0x0040 83 #define TWI_INT_STAT_MERR 0x0020 84 #define TWI_INT_STAT_MCOMP 0x0010 85 #define TWI_INT_STAT_SOVF 0x0008 86 #define TWI_INT_STAT_SERR 0x0004 87 #define TWI_INT_STAT_SCOMP 0x0002 88 #define TWI_INT_STAT_SINIT 0x0001 90 #define TWI_INT_MASK_RCVSERVM 0x0080 91 #define TWI_INT_MASK_XMTSERVM 0x0040 92 #define TWI_INT_MASK_MERRM 0x0020 93 #define TWI_INT_MASK_MCOMPM 0x0010 94 #define TWI_INT_MASK_SOVFM 0x0008 95 #define TWI_INT_MASK_SERRM 0x0004 96 #define TWI_INT_MASK_SCOMPM 0x0002 97 #define TWI_INT_MASK_SINITM 0x0001 99 #define TWI_FIFO_CTL_RCVINTLEN 0x0008 100 #define TWI_FIFO_CTL_XMTINTLEN 0x0004 101 #define TWI_FIFO_CTL_RCVFLUSH 0x0002 102 #define TWI_FIFO_CTL_XMTFLUSH 0x0001 104 #define TWI_FIFO_STAT_RCVSTAT_MASK 0x000c 105 #define TWI_FIFO_STAT_RCVSTAT_EMPTY 0x0000 106 #define TWI_FIFO_STAT_RCVSTAT_SHIFT 2 107 #define TWI_FIFO_STAT_XMTSTAT_MASK 0x0003 108 #define TWI_FIFO_STAT_XMTSTAT_FULL 0x0003 109 #define TWI_FIFO_STAT_XMTSTAT_SHIFT 0 111 #define TWI_XMT_DATA8_XMTDATA8_MASK 0x00ff 112 #define TWI_XMT_DATA8_XMTDATA8_SHIFT 0 114 #define TWI_RCV_DATA8_RCVDATA8_MASK 0x00ff 115 #define TWI_RCV_DATA8_RCVDATA8_SHIFT 0
1.8.15