RTEMS  5.1
tsmac.h
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1 
7 /*
8  * This file contains definitions for LatticeMico32 TSMAC (Tri-Speed MAC)
9  *
10  * COPYRIGHT (c) 1989-1999.
11  * On-Line Applications Research Corporation (OAR).
12  *
13  * The license and distribution terms for this file may be
14  * found in the file LICENSE in this distribution or at
15  * http://www.rtems.org/license/LICENSE.
16  *
17  * Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008,
18  * Micro-Research Finland Oy
19  */
20 
28 #ifndef _BSPTSMAC_H
29 #define _BSPTSMAC_H
30 
31 /* FIFO Registers */
32 
33 #define LM32_TSMAC_RX_LEN_FIFO (0x000)
34 #define LM32_TSMAC_RX_DATA_FIFO (0x004)
35 #define LM32_TSMAC_TX_LEN_FIFO (0x008)
36 #define LM32_TSMAC_TX_DATA_FIFO (0x00C)
37 
38 /* Control and Status Registers */
39 
40 #define LM32_TSMAC_VERID (0x100)
41 #define LM32_TSMAC_INTR_SRC (0x104)
42 #define INTR_RX_SMRY (0x00020000)
43 #define INTR_TX_SMRY (0x00010000)
44 #define INTR_RX_FIFO_FULL (0x00001000)
45 #define INTR_RX_ERROR (0x00000800)
46 #define INTR_RX_FIFO_ERROR (0x00000400)
47 #define INTR_RX_FIFO_ALMOST_FULL (0x00000200)
48 #define INTR_RX_PKT_RDY (0x00000100)
49 #define INTR_TX_FIFO_FULL (0x00000010)
50 #define INTR_TX_DISCFRM (0x00000008)
51 #define INTR_TX_FIFO_ALMOST_EMPTY (0x00000004)
52 #define INTR_TX_FIFO_ALMOST_FULL (0x00000002)
53 #define INTR_TX_PKT_SENT (0x00000001)
54 #define LM32_TSMAC_INTR_ENB (0x108)
55 #define INTR_ENB (0x00040000)
56 #define LM32_TSMAC_RX_STATUS (0x10C)
57 #define STAT_RX_FIFO_FULL (0x00000010)
58 #define STAT_RX_ERROR (0x00000008)
59 #define STAT_RX_FIFO_ERROR (0x00000004)
60 #define STAT_RX_FIFO_ALMOST_FULL (0x00000002)
61 #define STAT_RX_PKT_RDY (0x00000001)
62 #define LM32_TSMAC_TX_STATUS (0x110)
63 #define STAT_TX_FIFO_FULL (0x00000010)
64 #define STAT_TX_DISCFRM (0x00000008)
65 #define STAT_TX_FIFO_ALMOST_EMPTY (0x00000004)
66 #define STAT_TX_FIFO_ALMOST_FULL (0x00000002)
67 #define STAT_TX_PKT_SENT (0x00000001)
68 #define LM32_TSMAC_RX_FRAMES_CNT (0x114)
69 #define LM32_TSMAC_TX_FRAMES_CNT (0x118)
70 #define LM32_TSMAC_RX_FIFO_TH (0x11C)
71 #define LM32_TSMAC_TX_FIFO_TH (0x120)
72 #define LM32_TSMAC_SYS_CTL (0x124)
73 #define SYS_CTL_TX_FIFO_FLUSH (0x00000010)
74 #define SYS_CTL_RX_FIFO_FLUSH (0x00000008)
75 #define SYS_CTL_TX_SNDPAUSREQ (0x00000004)
76 #define SYS_CTL_TX_FIFOCTRL (0x00000002)
77 #define SYS_CTL_IGNORE_NEXT_PKT (0x00000001)
78 #define LM32_TSMAC_PAUSE_TMR (0x128)
79 
80 /* Tri-Speed MAC Registers */
81 
82 #define LM32_TSMAC_MAC_REGS_DATA (0x200)
83 #define LM32_TSMAC_MAC_REGS_ADDR_RW (0x204)
84 #define REGS_ADDR_WRITE (0x80000000)
85 #define LM32_TSMAC_MODE_BYTE0 (0x000)
86 #define MODE_TX_EN (1<<3)
87 #define MODE_RX_EN (1<<2)
88 #define MODE_FC_EN (1<<1)
89 #define MODE_GBIT_EN (1<<0)
90 #define LM32_TSMAC_TX_RX_CTL_BYTE0 (0x002)
91 #define TX_RX_CTL_RECEIVE_SHORT (1<<8)
92 #define TX_RX_CTL_RECEIVE_BRDCST (1<<7)
93 #define TX_RX_CTL_DIS_RTRY (1<<6)
94 #define TX_RX_CTL_HDEN (1<<5)
95 #define TX_RX_CTL_RECEIVE_MLTCST (1<<4)
96 #define TX_RX_CTL_RECEIVE_PAUSE (1<<3)
97 #define TX_RX_CTL_TX_DIS_FCS (1<<2)
98 #define TX_RX_CTL_DISCARD_FCS (1<<1)
99 #define TX_RX_CTL_PRMS (1<<0)
100 #define LM32_TSMAC_MAX_PKT_SIZE_BYTE0 (0x004)
101 #define LM32_TSMAC_IPG_VAL_BYTE0 (0x008)
102 #define LM32_TSMAC_MAC_ADDR_0_BYTE0 (0x00A)
103 #define LM32_TSMAC_MAC_ADDR_1_BYTE0 (0x00C)
104 #define LM32_TSMAC_MAC_ADDR_2_BYTE0 (0x00E)
105 #define LM32_TSMAC_TX_RX_STS_BYTE0 (0x012)
106 #define TX_RX_STS_RX_IDLE (1<<10)
107 #define TX_RX_STS_TAGGED_FRAME (1<<9)
108 #define TX_RX_STS_BRDCST_FRAME (1<<8)
109 #define TX_RX_STS_MULTCST_FRAME (1<<7)
110 #define TX_RX_STS_IPG_SHRINK (1<<6)
111 #define TX_RX_STS_SHORT_FRAME (1<<5)
112 #define TX_RX_STS_LONG_FRAME (1<<4)
113 #define TX_RX_STS_ERROR_FRAME (1<<3)
114 #define TX_RX_STS_CRC (1<<2)
115 #define TX_RX_STS_PAUSE_FRAME (1<<1)
116 #define TX_RX_STS_TX_IDLE (1<<0)
117 #define LM32_TSMAC_GMII_MNG_CTL_BYTE0 (0x014)
118 #define GMII_MNG_CTL_CMD_FIN (1<<14)
119 #define GMII_MNG_CTL_READ_PHYREG (0)
120 #define GMII_MNG_CTL_WRITE_PHYREG (1<<13)
121 #define GMII_MNG_CTL_PHY_ADD_MASK (0x001f)
122 #define GMII_MNG_CTL_PHY_ADD_SHIFT (8)
123 #define GMII_MNG_CTL_REG_ADD_MASK (0x001f)
124 #define GMII_MNG_CTL_REG_ADD_SHIFT (0)
125 #define LM32_TSMAC_GMII_MNG_DAT_BYTE0 (0x016)
126 #define LM32_TSMAC_MLT_TAB_0_BYTE0 (0x022)
127 #define LM32_TSMAC_MLT_TAB_1_BYTE0 (0x024)
128 #define LM32_TSMAC_MLT_TAB_2_BYTE0 (0x026)
129 #define LM32_TSMAC_MLT_TAB_3_BYTE0 (0x028)
130 #define LM32_TSMAC_MLT_TAB_4_BYTE0 (0x02A)
131 #define LM32_TSMAC_MLT_TAB_5_BYTE0 (0x02C)
132 #define LM32_TSMAC_MLT_TAB_6_BYTE0 (0x02E)
133 #define LM32_TSMAC_MLT_TAB_7_BYTE0 (0x030)
134 #define LM32_TSMAC_VLAN_TAG_BYTE0 (0x032)
135 #define LM32_TSMAC_PAUS_OP_BYTE0 (0x034)
136 
137 /* Receive Statistics Counters */
138 
139 #define LM32_TSMAC_RX_PKT_IGNR_CNT (0x300)
140 #define LM32_TSMAC_RX_LEN_CHK_ERR_CNT (0x304)
141 #define LM32_TSMAC_RX_LNG_FRM_CNT (0x308)
142 #define LM32_TSMAC_RX_SHRT_FRM_CNT (0x30C)
143 #define LM32_TSMAC_RX_IPG_VIOL_CNT (0x310)
144 #define LM32_TSMAC_RX_CRC_ERR_CNT (0x314)
145 #define LM32_TSMAC_RX_OK_PKT_CNT (0x318)
146 #define LM32_TSMAC_RX_CTL_FRM_CNT (0x31C)
147 #define LM32_TSMAC_RX_PAUSE_FRM_CNT (0x320)
148 #define LM32_TSMAC_RX_MULTICAST_CNT (0x324)
149 #define LM32_TSMAC_RX_BRDCAST_CNT (0x328)
150 #define LM32_TSMAC_RX_VLAN_TAG_CNT (0x32C)
151 #define LM32_TSMAC_RX_PRE_SHRINK_CNT (0x330)
152 #define LM32_TSMAC_RX_DRIB_NIB_CNT (0x334)
153 #define LM32_TSMAC_RX_UNSUP_OPCD_CNT (0x338)
154 #define LM32_TSMAC_RX_BYTE_CNT (0x33C)
155 
156 /* Transmit Statistics Counters */
157 
158 #define LM32_TSMAC_TX_UNICAST_CNT (0x400)
159 #define LM32_TSMAC_TX_PAUSE_FRM_CNT (0x404)
160 #define LM32_TSMAC_TX_MULTICAST_CNT (0x408)
161 #define LM32_TSMAC_TX_BRDCAST_CNT (0x40C)
162 #define LM32_TSMAC_TX_VLAN_TAG_CNT (0x410)
163 #define LM32_TSMAC_TX_BAD_FCS_CNT (0x414)
164 #define LM32_TSMAC_TX_JUMBO_CNT (0x418)
165 #define LM32_TSMAC_TX_BYTE_CNT (0x41C)
166 
167 #ifdef CPU_U32_FIX
168 void ipalign(struct mbuf *m);
169 #endif
170 
171 #endif /* _BSPTSMAC_H */
172 
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