RTEMS  5.1
stm32f4xxxx_tim.h
1 /*
2  * Copyright (c) 2013 Chris Nott. All rights reserved.
3  *
4  * Virtual Logic
5  * 21-25 King St.
6  * Rockdale NSW 2216
7  * Australia
8  * <rtems@vl.com.au>
9  *
10  * The license and distribution terms for this file may be
11  * found in the file LICENSE in this distribution or at
12  * http://www.rtems.org/license/LICENSE.
13  */
14 
15 #ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H
16 #define LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H
17 
18 #include <bsp/utility.h>
19 
20 struct stm32f4_tim_s {
21  uint16_t cr1; // Control register 1
22 #define STM32F4_TIMER_CR1_CKD_DIV 0x0300
23 #define STM32F4_TIMER_CR1_CKD_DIV1 0x0000
24 #define STM32F4_TIMER_CR1_CKD_DIV2 0x0100
25 #define STM32F4_TIMER_CR1_CKD_DIV3 0x0200
26 #define STM32F4_TIMER_CR1_ARPE BSP_BIT16(7)
27 #define STM32F4_TIMER_CR1_CMS 0x0060
28 #define STM32F4_TIMER_CR1_CMS_EDGE 0x0000
29 #define STM32F4_TIMER_CR1_CMS_CENTER1 0x0020
30 #define STM32F4_TIMER_CR1_CMS_CENTER2 0x0040
31 #define STM32F4_TIMER_CR1_CMS_CENTER3 0x0060
32 #define STM32F4_TIMER_CR1_DIR BSP_BIT16(4)
33 #define STM32F4_TIMER_CR1_DIR_UP 0x0000
34 #define STM32F4_TIMER_CR1_DIR_DOWN 0x0010
35 #define STM32F4_TIMER_CR1_DIR_OPM 0x0008
36 #define STM32F4_TIMER_CR1_DIR_OPM_CONT 0x0000
37 #define STM32F4_TIMER_CR1_DIR_OPM_STOP 0x0008
38 #define STM32F4_TIMER_CR1_DIR_URS 0x0004
39 #define STM32F4_TIMER_CR1_DIR_UDIS 0x0002
40 #define STM32F4_TIMER_CR1_DIR_UDIS_EN 0x0000
41 #define STM32F4_TIMER_CR1_DIR_UDIS_DIS 0x0002
42 #define STM32F4_TIMER_CR1_CEN 0x0001
43  uint16_t reserved_02;
44  uint16_t cr2; // Control register 2
45  uint16_t reserved_06;
46  uint16_t smcr; // Slave mode control register
47  uint16_t reserved_0a;
48  uint16_t dier; // DMA / interrupt enable register
49 #define STM32F4_TIMER_DIER_TDE BSP_BIT16(14) // Trigger DMA request enable
50 #define STM32F4_TIMER_DIER_CC4DE BSP_BIT16(12) // Capture/compare 4 DMA request enable
51 #define STM32F4_TIMER_DIER_CC3DE BSP_BIT16(11) // Capture/compare 3 DMA request enable
52 #define STM32F4_TIMER_DIER_CC2DE BSP_BIT16(10) // Capture/compare 2 DMA request enable
53 #define STM32F4_TIMER_DIER_CC1DE BSP_BIT16(9) // Capture/compare 1 DMA request enable
54 #define STM32F4_TIMER_DIER_UDE BSP_BIT16(8) // Update DMA request enable
55 #define STM32F4_TIMER_DIER_TIE BSP_BIT16(6) // Trigger interrupt enable
56 #define STM32F4_TIMER_DIER_CC4IE BSP_BIT16(4) // Capture/compare 4 interrupt request enable
57 #define STM32F4_TIMER_DIER_CC3IE BSP_BIT16(3) // Capture/compare 3 interrupt request enable
58 #define STM32F4_TIMER_DIER_CC2IE BSP_BIT16(2) // Capture/compare 2 interrupt request enable
59 #define STM32F4_TIMER_DIER_CC1IE BSP_BIT16(1) // Capture/compare 1 interrupt request enable
60 #define STM32F4_TIMER_DIER_UIE BSP_BIT16(0) // Update interrupt request enable
61 
62  uint16_t reserved_0e;
63  uint16_t sr; // Status register
64 #define STM32F4_TIMER_SR_CC4OF BSP_BIT16(12) // Capture/compare 4 overcapture flag
65 #define STM32F4_TIMER_SR_CC3OF BSP_BIT16(11) // Capture/compare 3 overcapture flag
66 #define STM32F4_TIMER_SR_CC2OF BSP_BIT16(10) // Capture/compare 2 overcapture flag
67 #define STM32F4_TIMER_SR_CC1OF BSP_BIT16(9) // Capture/compare 1 overcapture flag
68 #define STM32F4_TIMER_SR_TIF BSP_BIT16(6) // Trigger interrupt flag
69 #define STM32F4_TIMER_SR_CC4IF BSP_BIT16(4) // Capture/compare 4 interrupt flag
70 #define STM32F4_TIMER_SR_CC3IF BSP_BIT16(3) // Capture/compare 3 interrupt flag
71 #define STM32F4_TIMER_SR_CC2IF BSP_BIT16(2) // Capture/compare 2 interrupt flag
72 #define STM32F4_TIMER_SR_CC1IF BSP_BIT16(1) // Capture/compare 1 interrupt flag
73 #define STM32F4_TIMER_SR_UIF BSP_BIT16(0) // Update interrupt flag
74  uint16_t reserved_12;
75  uint16_t egr; // Event generation register
76 #define STM32F4_TIMER_EGR_TG BSP_BIT16(6) // Trigger event
77 #define STM32F4_TIMER_EGR_CC4G BSP_BIT16(4) // Capture/compare 4 event
78 #define STM32F4_TIMER_EGR_CC3G BSP_BIT16(3) // Capture/compare 3 generation)
79 #define STM32F4_TIMER_EGR_CC2G BSP_BIT16(2) // Capture/compare 2 generation)
80 #define STM32F4_TIMER_EGR_CC1G BSP_BIT16(1) // Capture/compare 1 generation)
81 #define STM32F4_TIMER_EGR_UG BSP_BIT16(0) // Update event
82  uint16_t reserved_16;
83  uint16_t ccmr1; // Capture / compare mode register 1
84 #define STM32F4_TIMER_CCMR1_OC2CE BSP_BIT16(15) // Output compare 2 clear enable
85 #define STM32F4_TIMER_CCMR1_OC2M(val) BSP_FLD16(val, 12, 14)
86 #define STM32F4_TIMER_CCMR1_OC2M_GET(reg) BSP_FLD16GET(reg, 12, 14)
87 #define STM32F4_TIMER_CCMR1_OC2M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14)
88 #define STM32F4_TIMER_CCMR1_OC2M_FROZEN STM32F4_TIMER_CCMR1_OC2M(0)
89 #define STM32F4_TIMER_CCMR1_OC2M_ACTIVE STM32F4_TIMER_CCMR1_OC2M(1)
90 #define STM32F4_TIMER_CCMR1_OC2M_INACTIVE STM32F4_TIMER_CCMR1_OC2M(2)
91 #define STM32F4_TIMER_CCMR1_OC2M_TOGGLE STM32F4_TIMER_CCMR1_OC2M(3)
92 #define STM32F4_TIMER_CCMR1_OC2M_FORCE_LOW STM32F4_TIMER_CCMR1_OC2M(4)
93 #define STM32F4_TIMER_CCMR1_OC2M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC2M(5)
94 #define STM32F4_TIMER_CCMR1_OC2M_PWM1 STM32F4_TIMER_CCMR1_OC2M(6)
95 #define STM32F4_TIMER_CCMR1_OC2M_PWM2 STM32F4_TIMER_CCMR1_OC2M(7)
96 #define STM32F4_TIMER_CCMR1_OC2PE BSP_BIT16(11) // Output compare 2 preload enable
97 #define STM32F4_TIMER_CCMR1_OC2FE BSP_BIT16(10) // Output compare 2 fast enable
98 #define STM32F4_TIMER_CCMR1_CC2S(val) BSP_FLD16(val, 8, 9)
99 #define STM32F4_TIMER_CCMR1_CC2S_GET(reg) BSP_FLD16GET(reg, 8, 9)
100 #define STM32F4_TIMER_CCMR1_CC2S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9)
101 #define STM32F4_TIMER_CCMR1_CC2S_OUTPUT STM32F4_TIMER_CCMR1_OC2S(0)
102 #define STM32F4_TIMER_CCMR1_CC2S_TI2 STM32F4_TIMER_CCMR1_OC2S(1)
103 #define STM32F4_TIMER_CCMR1_CC2S_TI1 STM32F4_TIMER_CCMR1_OC2S(2)
104 #define STM32F4_TIMER_CCMR1_CC2S_TRC STM32F4_TIMER_CCMR1_OC2S(3)
105 #define STM32F4_TIMER_CCMR1_OC1CE BSP_BIT16(7) // Output compare 1 clear enable
106 #define STM32F4_TIMER_CCMR1_OC1M(val) BSP_FLD16(val, 4, 6)
107 #define STM32F4_TIMER_CCMR1_OC1M_GET(reg) BSP_FLD16GET(reg, 4, 6)
108 #define STM32F4_TIMER_CCMR1_OC1M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6)
109 #define STM32F4_TIMER_CCMR1_OC1M_FROZEN STM32F4_TIMER_CCMR1_OC1M(0)
110 #define STM32F4_TIMER_CCMR1_OC1M_ACTIVE STM32F4_TIMER_CCMR1_OC1M(1)
111 #define STM32F4_TIMER_CCMR1_OC1M_INACTIVE STM32F4_TIMER_CCMR1_OC1M(2)
112 #define STM32F4_TIMER_CCMR1_OC1M_TOGGLE STM32F4_TIMER_CCMR1_OC1M(3)
113 #define STM32F4_TIMER_CCMR1_OC1M_FORCE_LOW STM32F4_TIMER_CCMR1_OC1M(4)
114 #define STM32F4_TIMER_CCMR1_OC1M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC1M(5)
115 #define STM32F4_TIMER_CCMR1_OC1M_PWM1 STM32F4_TIMER_CCMR1_OC1M(6)
116 #define STM32F4_TIMER_CCMR1_OC1M_PWM2 STM32F4_TIMER_CCMR1_OC1M(7)
117 #define STM32F4_TIMER_CCMR1_OC1PE BSP_BIT16(3) // Output compare 1 preload enable
118 #define STM32F4_TIMER_CCMR1_OC1FE BSP_BIT16(2) // Output compare 1 fast enable
119 #define STM32F4_TIMER_CCMR1_CC1S(val) BSP_FLD16(val, 0, 1)
120 #define STM32F4_TIMER_CCMR1_CC1S_GET(reg) BSP_FLD16GET(reg, 0, 1)
121 #define STM32F4_TIMER_CCMR1_CC1S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1)
122 #define STM32F4_TIMER_CCMR1_CC1S_OUTPUT STM32F4_TIMER_CCMR1_OC1S(0)
123 #define STM32F4_TIMER_CCMR1_CC1S_TI2 STM32F4_TIMER_CCMR1_OC1S(1)
124 #define STM32F4_TIMER_CCMR1_CC1S_TI1 STM32F4_TIMER_CCMR1_OC1S(2)
125 #define STM32F4_TIMER_CCMR1_CC1S_TRC STM32F4_TIMER_CCMR1_OC1S(3)
126  uint16_t reserved_1a;
127  uint16_t ccmr2; // Capture / compare mode register 2
128 #define STM32F4_TIMER_CCMR2_OC4CE BSP_BIT16(15) // Output compare 4 clear enable
129 #define STM32F4_TIMER_CCMR2_OC4M(val) BSP_FLD16(val, 12, 14)
130 #define STM32F4_TIMER_CCMR2_OC4M_GET(reg) BSP_FLD16GET(reg, 12, 14)
131 #define STM32F4_TIMER_CCMR2_OC4M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14)
132 #define STM32F4_TIMER_CCMR2_OC4M_FROZEN STM32F4_TIMER_CCMR2_OC4M(0)
133 #define STM32F4_TIMER_CCMR2_OC4M_ACTIVE STM32F4_TIMER_CCMR2_OC4M(1)
134 #define STM32F4_TIMER_CCMR2_OC4M_INACTIVE STM32F4_TIMER_CCMR2_OC4M(2)
135 #define STM32F4_TIMER_CCMR2_OC4M_TOGGLE STM32F4_TIMER_CCMR2_OC4M(3)
136 #define STM32F4_TIMER_CCMR2_OC4M_FORCE_LOW STM32F4_TIMER_CCMR2_OC4M(4)
137 #define STM32F4_TIMER_CCMR2_OC4M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC4M(5)
138 #define STM32F4_TIMER_CCMR2_OC4M_PWM1 STM32F4_TIMER_CCMR2_OC4M(6)
139 #define STM32F4_TIMER_CCMR2_OC4M_PWM2 STM32F4_TIMER_CCMR2_OC4M(7)
140 #define STM32F4_TIMER_CCMR2_OC4PE BSP_BIT16(11) // Output compare 4 preload enable
141 #define STM32F4_TIMER_CCMR2_OC4FE BSP_BIT16(10) // Output compare 4 fast enable
142 #define STM32F4_TIMER_CCMR2_CC4S(val) BSP_FLD16(val, 8, 9)
143 #define STM32F4_TIMER_CCMR2_CC4S_GET(reg) BSP_FLD16GET(reg, 8, 9)
144 #define STM32F4_TIMER_CCMR2_CC4S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9)
145 #define STM32F4_TIMER_CCMR2_CC4S_OUTPUT STM32F4_TIMER_CCMR2_OC4S(0)
146 #define STM32F4_TIMER_CCMR2_CC4S_TI2 STM32F4_TIMER_CCMR2_OC4S(1)
147 #define STM32F4_TIMER_CCMR2_CC4S_TI1 STM32F4_TIMER_CCMR2_OC4S(2)
148 #define STM32F4_TIMER_CCMR2_CC4S_TRC STM32F4_TIMER_CCMR2_OC4S(3)
149 #define STM32F4_TIMER_CCMR2_OC3CE BSP_BIT16(7) // Output compare 3 clear enable
150 #define STM32F4_TIMER_CCMR2_OC3M(val) BSP_FLD16(val, 4, 6)
151 #define STM32F4_TIMER_CCMR2_OC3M_GET(reg) BSP_FLD16GET(reg, 4, 6)
152 #define STM32F4_TIMER_CCMR2_OC3M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6)
153 #define STM32F4_TIMER_CCMR2_OC3M_FROZEN STM32F4_TIMER_CCMR2_OC3M(0)
154 #define STM32F4_TIMER_CCMR2_OC3M_ACTIVE STM32F4_TIMER_CCMR2_OC3M(1)
155 #define STM32F4_TIMER_CCMR2_OC3M_INACTIVE STM32F4_TIMER_CCMR2_OC3M(2)
156 #define STM32F4_TIMER_CCMR2_OC3M_TOGGLE STM32F4_TIMER_CCMR2_OC3M(3)
157 #define STM32F4_TIMER_CCMR2_OC3M_FORCE_LOW STM32F4_TIMER_CCMR2_OC3M(4)
158 #define STM32F4_TIMER_CCMR2_OC3M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC3M(5)
159 #define STM32F4_TIMER_CCMR2_OC3M_PWM1 STM32F4_TIMER_CCMR2_OC3M(6)
160 #define STM32F4_TIMER_CCMR2_OC3M_PWM2 STM32F4_TIMER_CCMR2_OC3M(7)
161 #define STM32F4_TIMER_CCMR2_OC3PE BSP_BIT16(3) // Output compare 3 preload enable
162 #define STM32F4_TIMER_CCMR2_OC3FE BSP_BIT16(2) // Output compare 3 fast enable
163 #define STM32F4_TIMER_CCMR2_CC3S(val) BSP_FLD16(val, 0, 1)
164 #define STM32F4_TIMER_CCMR2_CC3S_GET(reg) BSP_FLD16GET(reg, 0, 1)
165 #define STM32F4_TIMER_CCMR2_CC3S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1)
166 #define STM32F4_TIMER_CCMR2_CC3S_OUTPUT STM32F4_TIMER_CCMR2_OC3S(0)
167 #define STM32F4_TIMER_CCMR2_CC3S_TI2 STM32F4_TIMER_CCMR2_OC3S(1)
168 #define STM32F4_TIMER_CCMR2_CC3S_TI1 STM32F4_TIMER_CCMR2_OC3S(2)
169 #define STM32F4_TIMER_CCMR2_CC3S_TRC STM32F4_TIMER_CCMR2_OC3S(3)
170  uint16_t reserved_1e;
171  uint16_t ccer; // Capture / compare enable register
172 #define STM32F4_TIMER_CCER_CC4NP BSP_BIT16(15) // Capture / compare 4 output polarity
173 #define STM32F4_TIMER_CCER_CC4P BSP_BIT16(13) // Capture / compare 4 output polarity
174 #define STM32F4_TIMER_CCER_CC4E BSP_BIT16(12) // Capture / compare 4 output enable
175 #define STM32F4_TIMER_CCER_CC3NP BSP_BIT16(11) // Capture / compare 3 output polarity
176 #define STM32F4_TIMER_CCER_CC3P BSP_BIT16(9) // Capture / compare 3 output polarity
177 #define STM32F4_TIMER_CCER_CC3E BSP_BIT16(8) // Capture / compare 3 output enable
178 #define STM32F4_TIMER_CCER_CC2NP BSP_BIT16(7) // Capture / compare 2 output polarity
179 #define STM32F4_TIMER_CCER_CC2P BSP_BIT16(5) // Capture / compare 2 output polarity
180 #define STM32F4_TIMER_CCER_CC2E BSP_BIT16(4) // Capture / compare 2 output enable
181 #define STM32F4_TIMER_CCER_CC1NP BSP_BIT16(3) // Capture / compare 1 output polarity
182 #define STM32F4_TIMER_CCER_CC1P BSP_BIT16(1) // Capture / compare 1 output polarity
183 #define STM32F4_TIMER_CCER_CC1E BSP_BIT16(0) // Capture / compare 1 output enable
184  uint16_t reserved_22;
185  uint32_t cnt; // Counter register
186 #define STM32F4_TIMER_DR(val) BSP_FLD32(val, 0, 31)
187 #define STM32F4_TIMER_DR_GET(reg) BSP_FLD32GET(reg, 0, 31)
188 #define STM32F4_TIMER_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
189  uint16_t psc; // Prescalar
190  uint16_t reserved_2a;
191  uint32_t arr; // Auto-reload register
192  uint16_t rcr; // Repetition counter register
193  uint16_t rserved_32;
194  uint32_t ccr[4];// Capture / compare registers
195  uint16_t bdtr; // Break and dead-time register
196  uint16_t reserved_46;
197  uint16_t dcr; // DMA control register
198  uint16_t reserved_4a;
199  uint16_t dmar; // DMA address for full transfer
200  uint16_t reserved_4e;
201  uint16_t or; // Option register
202  uint16_t reserved_52;
203 } __attribute__ ((packed));
204 typedef struct stm32f4_tim_s stm32f4_tim;
205 
206 #endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H */
stm32f4_tim_s
Definition: stm32f4xxxx_tim.h:20
utility.h
Utility macros.
__attribute__
typedef __attribute__
Disable IRQ Interrupts.
Definition: cmsis_gcc.h:69
Generated by   doxygen 1.8.15