RTEMS  5.1
spr.h
1 /*
2  * spr.h -- Access to special purpose registers.
3  *
4  * Copyright (C) 1998 Gabriel Paubert, paubert@iram.es
5  *
6  * Modified to compile in RTEMS development environment
7  * by Eric Valette
8  *
9  * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
10  *
11  * The license and distribution terms for this file may be
12  * found in the file LICENSE in this distribution or at
13  * http://www.rtems.org/license/LICENSE.
14  *
15  */
16 
17 
18 #ifndef _LIBCPU_SPR_H
19 #define _LIBCPU_SPR_H
20 
22 
23 #define __MFSPR(reg, val) \
24  __asm__ __volatile__("mfspr %0,"#reg : "=r" (val))
25 
26 #define __MTSPR(val, reg) \
27  __asm__ __volatile__("mtspr "#reg",%0" : : "r" (val))
28 
29 
30 #define SPR_RW(reg) \
31 static inline unsigned long _read_##reg(void) \
32 {\
33  unsigned long val;\
34  __MFSPR(reg, val);\
35  return val;\
36 }\
37 static inline void _write_##reg(unsigned long val)\
38 {\
39  __MTSPR(val,reg);\
40  return;\
41 }
42 
43 #define SPR_RO(reg) \
44 static inline unsigned long _read_##reg(void) \
45 {\
46  unsigned long val;\
47  __MFSPR(reg,val);\
48  return val;\
49 }
50 
51 static inline unsigned long _read_MSR(void)
52 {
53  unsigned long val;
54  asm volatile("mfmsr %0" : "=r" (val));
55  return val;
56 }
57 
58 static inline void _write_MSR(unsigned long val)
59 {
60  asm volatile("mtmsr %0" : : "r" (val));
61  return;
62 }
63 
64 static inline unsigned long _read_SR(void * va)
65 {
66  unsigned long val;
67  asm volatile("mfsrin %0,%1" : "=r" (val): "r" (va));
68  return val;
69 }
70 
71 static inline void _write_SR(unsigned long val, void * va)
72 {
73  asm volatile("mtsrin %0,%1" : : "r"(val), "r" (va): "memory");
74  return;
75 }
76 
77 
78 #endif