RTEMS  5.1
spictrl.h
1 /*
2  * SPICTRL SPI Driver interface.
3  *
4  * COPYRIGHT (c) 2009.
5  * Cobham Gaisler AB.
6  *
7  * The license and distribution terms for this file may be
8  * found in the file LICENSE in this distribution or at
9  * http://www.rtems.org/license/LICENSE.
10  */
11 
12 #ifndef __SPICTRL_H__
13 #define __SPICTRL_H__
14 
15 #ifdef __cplusplus
16 extern "C" {
17 #endif
18 
19 extern void spictrl_register_drv (void);
20 
21 /*** REGISTER LAYOUT ***/
22 struct spictrl_regs {
23  volatile unsigned int capability; /* 0x00 */
24  volatile unsigned int resv[7]; /* 0x04 */
25  volatile unsigned int mode; /* 0x20 */
26  volatile unsigned int event; /* 0x24 */
27  volatile unsigned int mask; /* 0x28 */
28  volatile unsigned int command; /* 0x2c */
29  volatile unsigned int tx; /* 0x30 */
30  volatile unsigned int rx; /* 0x34 */
31  volatile unsigned int slvsel; /* 0x38 */
32  volatile unsigned int am_slvsel; /* 0x3c */
33  volatile unsigned int am_cfg; /* 0x40 */
34  volatile unsigned int am_period; /* 0x44 */
35  int reserved0[2];
36  volatile unsigned int am_mask[4]; /* 0x50-0x5C */
37  int reserved1[(0x200-0x60)/4];
38  volatile unsigned int am_tx[128]; /* 0x200-0x3FC */
39  volatile unsigned int am_rx[128]; /* 0x400-0x5FC */
40 };
41 
42 /* -- About automated periodic transfer mode --
43  *
44  * Core must support this feature.
45  *
46  * The SPI core must be configured in periodic mode before
47  * writing the data into the transfer FIFO which will be used
48  * mutiple times in different transfers, it will also make
49  * the receive FIFO to be updated.
50  *
51  * In periodic mode the following sequence is performed,
52  * 1. start()
53  * 2. ioctl(CONFIG, &config) - Enable periodic mode
54  * 3. set_address()
55  * 4. write() - Fills TX FIFO, this has some constraints
56  * 5. ioctl(START) - Starts the periodic transmission of the TX FIFO
57  * 6. read() - Read one response of the tranistted data. It will
58  * hang until data is available. If hanging is not an
59  * options use ioctl(STATUS)
60  * 7. go back to 6.
61  *
62  * 8. ioctl(STOP) - Stop to set up a new periodic or normal transfer
63  * 9. stop()
64  *
65  * Note that the the read length must equal the total write length.
66  */
67 
68 /* Custom SPICTRL driver ioctl commands */
69 #define SPICTRL_IOCTL_PERIOD_START 5000 /* Start automated periodic transfer mode */
70 #define SPICTRL_IOCTL_PERIOD_STOP 5001 /* Stop to SPI core from doing periodic transfers */
71 #define SPICTRL_IOCTL_CONFIG 5002 /* Configure Periodic transfer mode (before calling write() and START) */
72 #define SPICTRL_IOCTL_STATUS 5003 /* Get status */
73 
74 #define SPICTRL_IOCTL_PERIOD_READ 5005 /* Write transmit registers and mask register
75  * (only in automatic periodic mode)
76  * Note that it is probably prefferred to read
77  * the received words using the read() using
78  * operations instead.
79  */
80 #define SPICTRL_IOCTL_PERIOD_WRITE 5006 /* Read receive registers and mask register
81  * (only in automatic periodic mode) */
82 #define SPICTRL_IOCTL_REGS 5007 /* Get SPICTRL Register */
83 
84 /* SPICTRL_IOCTL_CONFIG argument */
86  int clock_gap; /* Clock GAP between */
87  unsigned int flags; /* Normal mode flags */
88  int periodic_mode; /* 1=Enables Automated periodic transfers if supported by hardware */
89  unsigned int period; /* Number of clocks between automated transfers are started */
90  unsigned int period_flags; /* Options */
91  unsigned int period_slvsel; /* Slave Select when transfer is not active, default is 0xffffffff */
92 };
93 #define SPICTRL_FLAGS_TAC 0x10
94 
95 #define SPICTRL_PERIOD_FLAGS_ERPT 0x80 /* Trigger start-period from external signal */
96 #define SPICTRL_PERIOD_FLAGS_SEQ 0x40
97 #define SPICTRL_PERIOD_FLAGS_STRICT 0x20
98 #define SPICTRL_PERIOD_FLAGS_OVTB 0x10
99 #define SPICTRL_PERIOD_FLAGS_OVDB 0x08
100 #define SPICTRL_PERIOD_FLAGS_ASEL 0x04
101 #define SPICTRL_PERIOD_FLAGS_EACT 0x01
102 
103 /* SPICTRL_IOCTL_PERIOD_READ and SPICTRL_IOCTL_PERIOD_WRITE Argument data structure
104  *
105  * Note that the order of reading the mask registers are different for read/write
106  * operation. See options notes.
107  */
109  int options; /* READ: bit0=Read Mask Registers into masks[].
110  * bit1=Read Receive registers according to masks[]
111  * (after reading masks).
112  *
113  * WRITE: bit0=Update Mask accoring to masks[].
114  * bit1=Update Transmit registers according to masks[].
115  * (before reading masks)
116  */
117  unsigned int masks[4];
118 
119  void *data; /* Data read sequentially according to masks[] bit. */
120 };
121 
122 #ifdef __cplusplus
123 }
124 #endif
125 
126 #endif
Definition: spictrl.h:22
Definition: spictrl.h:108
Definition: spictrl.h:85