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RTEMS
5.1
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17 #define SPI_CTL_OFFSET 0x0000 18 #define SPI_FLG_OFFSET 0x0004 19 #define SPI_STAT_OFFSET 0x0008 20 #define SPI_TDBR_OFFSET 0x000c 21 #define SPI_RDBR_OFFSET 0x0010 22 #define SPI_BAUD_OFFSET 0x0014 23 #define SPI_SHADOW_OFFSET 0x0018 28 #define SPI_CTL_SPE 0x4000 29 #define SPI_CTL_WOM 0x2000 30 #define SPI_CTL_MSTR 0x1000 31 #define SPI_CTL_CPOL 0x0800 32 #define SPI_CTL_CPHA 0x0400 33 #define SPI_CTL_LSBF 0x0200 34 #define SPI_CTL_SIZE 0x0100 35 #define SPI_CTL_EMISO 0x0020 36 #define SPI_CTL_PSSE 0x0010 37 #define SPI_CTL_GM 0x0008 38 #define SPI_CTL_SZ 0x0004 39 #define SPI_CTL_TIMOD_MASK 0x0003 40 #define SPI_CTL_TIMOD_RDBR 0x0000 41 #define SPI_CTL_TIMOD_TDBR 0x0001 42 #define SPI_CTL_TIMOD_DMA_RDBR 0x0002 43 #define SPI_CTL_TIMOD_DMA_TDBR 0x0003 45 #define SPI_FLG_FLG7 0x8000 46 #define SPI_FLG_FLG6 0x4000 47 #define SPI_FLG_FLG5 0x2000 48 #define SPI_FLG_FLG4 0x1000 49 #define SPI_FLG_FLG3 0x0800 50 #define SPI_FLG_FLG2 0x0400 51 #define SPI_FLG_FLG1 0x0200 52 #define SPI_FLG_FLS7 0x0080 53 #define SPI_FLG_FLS6 0x0040 54 #define SPI_FLG_FLS5 0x0020 55 #define SPI_FLG_FLS4 0x0010 56 #define SPI_FLG_FLS3 0x0008 57 #define SPI_FLG_FLS2 0x0004 58 #define SPI_FLG_FLS1 0x0002 60 #define SPI_STAT_TXCOL 0x0040 61 #define SPI_STAT_RXS 0x0020 62 #define SPI_STAT_RBSY 0x0010 63 #define SPI_STAT_TXS 0x0008 64 #define SPI_STAT_TXE 0x0004 65 #define SPI_STAT_MODF 0x0002 66 #define SPI_STAT_SPIF 0x0001