RTEMS  5.1
sdramc.h
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29 
36 // ---------------------------------------------------------------------------
37 // SDRAM
38 // ---------------------------------------------------------------------------
40 #define EBI_SDRAMC_ADDR (0x70000000u)
41 
43 #define BOARD_SDRAM_BUSWIDTH 16
44 
45 
46 typedef struct _SSdramc_config {
47  uint32_t dwColumnBits; // Number of Column Bits
48  uint32_t dwRowBits; // Number of Row Bits
49  uint32_t dwBanks; // Number of Banks
50  uint32_t dwCAS; // CAS Latency
51  uint32_t dwDataBusWidth; // Data Bus Width
52  uint32_t dwWriteRecoveryDelay; // Write Recovery Delay
53  uint32_t dwRowCycleDelay_RowRefreshCycle; // Row Cycle Delay and Row Refresh Cycle
54  uint32_t dwRowPrechargeDelay; // Row Precharge Delay
55  uint32_t dwRowColumnDelay; // Row to Column Delay
56  uint32_t dwActivePrechargeDelay; // Active to Precharge Delay
57  uint32_t dwExitSelfRefreshActiveDelay; // Exit Self Refresh to Active Delay
58  uint32_t dwBK1; // bk1 addr
59 
61 
62 typedef struct _SSdramc_Memory {
63  SSdramc_config cfg;
64 
66 
67 extern void SDRAMC_Configure(SSdramc_Memory *pMemory,
68  uint32_t dwClockFrequency);
Definition: sdramc.h:62
void SDRAMC_Configure(SSdramc_Memory *pMemory, uint32_t dwClockFrequency)
Configure and initialize the SDRAM controller.
Definition: sdramc.c:106
Definition: sdramc.h:46