RTEMS  5.1
samv71n21.h
1 /* ---------------------------------------------------------------------------- */
2 /* Atmel Microcontroller Software Support */
3 /* SAM Software Package License */
4 /* ---------------------------------------------------------------------------- */
5 /* Copyright (c) 2015, Atmel Corporation */
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29 
30 #ifndef _SAMV71N21_
31 #define _SAMV71N21_
32 
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
47 #include <stdint.h>
48 #endif
49 
50 /* ************************************************************************** */
51 /* CMSIS DEFINITIONS FOR SAMV71N21 */
52 /* ************************************************************************** */
55 
57 typedef enum IRQn
58 {
59 /****** Cortex-M7 Processor Exceptions Numbers ******************************/
63  BusFault_IRQn = -11,
65  SVCall_IRQn = -5,
67  PendSV_IRQn = -2,
68  SysTick_IRQn = -1,
69 /****** SAMV71N21 specific Interrupt Numbers *********************************/
70 
71  SUPC_IRQn = 0,
72  RSTC_IRQn = 1,
73  RTC_IRQn = 2,
74  RTT_IRQn = 3,
75  WDT_IRQn = 4,
76  PMC_IRQn = 5,
77  EFC_IRQn = 6,
78  UART0_IRQn = 7,
79  UART1_IRQn = 8,
80  PIOA_IRQn = 10,
81  PIOB_IRQn = 11,
82  USART0_IRQn = 13,
83  USART1_IRQn = 14,
84  USART2_IRQn = 15,
85  PIOD_IRQn = 16,
86  HSMCI_IRQn = 18,
87  TWIHS0_IRQn = 19,
88  TWIHS1_IRQn = 20,
89  SPI0_IRQn = 21,
90  SSC_IRQn = 22,
91  TC0_IRQn = 23,
92  TC1_IRQn = 24,
93  TC2_IRQn = 25,
94  AFEC0_IRQn = 29,
95  DACC_IRQn = 30,
96  PWM0_IRQn = 31,
97  ICM_IRQn = 32,
98  ACC_IRQn = 33,
99  USBHS_IRQn = 34,
100  MCAN0_IRQn = 35,
101  MCAN1_IRQn = 37,
102  GMAC_IRQn = 39,
103  AFEC1_IRQn = 40,
104  TWIHS2_IRQn = 41,
105  SPI1_IRQn = 42,
106  QSPI_IRQn = 43,
107  UART2_IRQn = 44,
108  UART3_IRQn = 45,
109  UART4_IRQn = 46,
110  TC9_IRQn = 50,
111  TC10_IRQn = 51,
112  TC11_IRQn = 52,
113  MLB_IRQn = 53,
114  AES_IRQn = 56,
115  TRNG_IRQn = 57,
116  XDMAC_IRQn = 58,
117  ISI_IRQn = 59,
118  PWM1_IRQn = 60,
119  RSWDT_IRQn = 63,
122 } IRQn_Type;
123 
124 typedef struct _DeviceVectors
125 {
126  /* Stack pointer */
127  void* pvStack;
128 
129  /* Cortex-M handlers */
130  void* pfnReset_Handler;
131  void* pfnNMI_Handler;
132  void* pfnHardFault_Handler;
133  void* pfnMemManage_Handler;
134  void* pfnBusFault_Handler;
135  void* pfnUsageFault_Handler;
136  void* pfnReserved1_Handler;
137  void* pfnReserved2_Handler;
138  void* pfnReserved3_Handler;
139  void* pfnReserved4_Handler;
140  void* pfnSVC_Handler;
141  void* pfnDebugMon_Handler;
142  void* pfnReserved5_Handler;
143  void* pfnPendSV_Handler;
144  void* pfnSysTick_Handler;
145 
146  /* Peripheral handlers */
147  void* pfnSUPC_Handler; /* 0 Supply Controller */
148  void* pfnRSTC_Handler; /* 1 Reset Controller */
149  void* pfnRTC_Handler; /* 2 Real Time Clock */
150  void* pfnRTT_Handler; /* 3 Real Time Timer */
151  void* pfnWDT_Handler; /* 4 Watchdog Timer */
152  void* pfnPMC_Handler; /* 5 Power Management Controller */
153  void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
154  void* pfnUART0_Handler; /* 7 UART 0 */
155  void* pfnUART1_Handler; /* 8 UART 1 */
156  void* pvReserved9;
157  void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
158  void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
159  void* pvReserved12;
160  void* pfnUSART0_Handler; /* 13 USART 0 */
161  void* pfnUSART1_Handler; /* 14 USART 1 */
162  void* pfnUSART2_Handler; /* 15 USART 2 */
163  void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
164  void* pvReserved17;
165  void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
166  void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
167  void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
168  void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
169  void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
170  void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
171  void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
172  void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
173  void* pvReserved26;
174  void* pvReserved27;
175  void* pvReserved28;
176  void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
177  void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
178  void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
179  void* pfnICM_Handler; /* 32 Integrity Check Monitor */
180  void* pfnACC_Handler; /* 33 Analog Comparator */
181  void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
182  void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */
183  void* pvReserved36;
184  void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */
185  void* pvReserved38;
186  void* pfnGMAC_Handler; /* 39 Ethernet MAC */
187  void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
188  void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
189  void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
190  void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
191  void* pfnUART2_Handler; /* 44 UART 2 */
192  void* pfnUART3_Handler; /* 45 UART 3 */
193  void* pfnUART4_Handler; /* 46 UART 4 */
194  void* pvReserved47;
195  void* pvReserved48;
196  void* pvReserved49;
197  void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
198  void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
199  void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
200  void* pfnMLB_Handler; /* 53 MediaLB */
201  void* pvReserved54;
202  void* pvReserved55;
203  void* pfnAES_Handler; /* 56 AES */
204  void* pfnTRNG_Handler; /* 57 True Random Generator */
205  void* pfnXDMAC_Handler; /* 58 DMA */
206  void* pfnISI_Handler; /* 59 Camera Interface */
207  void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
208  void* pvReserved61;
209  void* pvReserved62;
210  void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
211 } DeviceVectors;
212 
213 /* Cortex-M7 core handlers */
214 void Reset_Handler ( void );
215 void NMI_Handler ( void );
216 void HardFault_Handler ( void );
217 void MemManage_Handler ( void );
218 void BusFault_Handler ( void );
219 void UsageFault_Handler ( void );
220 void SVC_Handler ( void );
221 void DebugMon_Handler ( void );
222 void PendSV_Handler ( void );
223 void SysTick_Handler ( void );
224 
225 /* Peripherals handlers */
226 void ACC_Handler ( void );
227 void AES_Handler ( void );
228 void AFEC0_Handler ( void );
229 void AFEC1_Handler ( void );
230 void DACC_Handler ( void );
231 void EFC_Handler ( void );
232 void GMAC_Handler ( void );
233 void HSMCI_Handler ( void );
234 void ICM_Handler ( void );
235 void ISI_Handler ( void );
236 void MCAN0_Handler ( void );
237 void MCAN1_Handler ( void );
238 void MLB_Handler ( void );
239 void PIOA_Handler ( void );
240 void PIOB_Handler ( void );
241 void PIOD_Handler ( void );
242 void PMC_Handler ( void );
243 void PWM0_Handler ( void );
244 void PWM1_Handler ( void );
245 void QSPI_Handler ( void );
246 void RSTC_Handler ( void );
247 void RSWDT_Handler ( void );
248 void RTC_Handler ( void );
249 void RTT_Handler ( void );
250 void SPI0_Handler ( void );
251 void SPI1_Handler ( void );
252 void SSC_Handler ( void );
253 void SUPC_Handler ( void );
254 void TC0_Handler ( void );
255 void TC1_Handler ( void );
256 void TC2_Handler ( void );
257 void TC9_Handler ( void );
258 void TC10_Handler ( void );
259 void TC11_Handler ( void );
260 void TRNG_Handler ( void );
261 void TWIHS0_Handler ( void );
262 void TWIHS1_Handler ( void );
263 void TWIHS2_Handler ( void );
264 void UART0_Handler ( void );
265 void UART1_Handler ( void );
266 void UART2_Handler ( void );
267 void UART3_Handler ( void );
268 void UART4_Handler ( void );
269 void USART0_Handler ( void );
270 void USART1_Handler ( void );
271 void USART2_Handler ( void );
272 void USBHS_Handler ( void );
273 void WDT_Handler ( void );
274 void XDMAC_Handler ( void );
275 
280 #define __CM7_REV 0x0000
281 #define __MPU_PRESENT 1
282 #define __NVIC_PRIO_BITS 3
283 #define __FPU_PRESENT 1
284 #define __FPU_DP 1
285 #define __ICACHE_PRESENT 1
286 #define __DCACHE_PRESENT 1
287 #define __DTCM_PRESENT 1
288 #define __ITCM_PRESENT 1
289 #define __Vendor_SysTickConfig 0
291 /*
292  * \brief CMSIS includes
293  */
294 
295 #include <core_cm7.h>
296 #if !defined DONT_USE_CMSIS_INIT
297 #include "system_samv71.h"
298 #endif /* DONT_USE_CMSIS_INIT */
299 
302 /* ************************************************************************** */
304 /* ************************************************************************** */
307 
308 #include "component/component_acc.h"
309 #include "component/component_aes.h"
310 #include "component/component_afec.h"
311 #include "component/component_chipid.h"
312 #include "component/component_dacc.h"
313 #include "component/component_efc.h"
314 #include "component/component_gmac.h"
315 #include "component/component_gpbr.h"
316 #include "component/component_hsmci.h"
317 #include "component/component_icm.h"
318 #include "component/component_isi.h"
319 #include "component/component_matrix.h"
320 #include "component/component_mcan.h"
321 #include "component/component_mlb.h"
322 #include "component/component_pio.h"
323 #include "component/component_pmc.h"
324 #include "component/component_pwm.h"
325 #include "component/component_qspi.h"
326 #include "component/component_rstc.h"
327 #include "component/component_rswdt.h"
328 #include "component/component_rtc.h"
329 #include "component/component_rtt.h"
330 #include "component/component_spi.h"
331 #include "component/component_ssc.h"
332 #include "component/component_supc.h"
333 #include "component/component_tc.h"
334 #include "component/component_trng.h"
335 #include "component/component_twihs.h"
336 #include "component/component_uart.h"
337 #include "component/component_usart.h"
338 #include "component/component_usbhs.h"
339 #include "component/component_utmi.h"
340 #include "component/component_wdt.h"
341 #include "component/component_xdmac.h"
344 #ifndef __rtems__
345 /* ************************************************************************** */
346 /* REGISTER ACCESS DEFINITIONS FOR SAMV71N21 */
347 /* ************************************************************************** */
350 
351 #include "instance/instance_hsmci.h"
352 #include "instance/instance_ssc.h"
353 #include "instance/instance_spi0.h"
354 #include "instance/instance_tc0.h"
355 #include "instance/instance_twihs0.h"
356 #include "instance/instance_twihs1.h"
357 #include "instance/instance_pwm0.h"
358 #include "instance/instance_usart0.h"
359 #include "instance/instance_usart1.h"
360 #include "instance/instance_usart2.h"
361 #include "instance/instance_mcan0.h"
362 #include "instance/instance_mcan1.h"
363 #include "instance/instance_usbhs.h"
364 #include "instance/instance_afec0.h"
365 #include "instance/instance_dacc.h"
366 #include "instance/instance_acc.h"
367 #include "instance/instance_icm.h"
368 #include "instance/instance_isi.h"
369 #include "instance/instance_gmac.h"
370 #include "instance/instance_tc3.h"
371 #include "instance/instance_spi1.h"
372 #include "instance/instance_pwm1.h"
373 #include "instance/instance_twihs2.h"
374 #include "instance/instance_afec1.h"
375 #include "instance/instance_mlb.h"
376 #include "instance/instance_aes.h"
377 #include "instance/instance_trng.h"
378 #include "instance/instance_xdmac.h"
379 #include "instance/instance_qspi.h"
380 #include "instance/instance_matrix.h"
381 #include "instance/instance_utmi.h"
382 #include "instance/instance_pmc.h"
383 #include "instance/instance_uart0.h"
384 #include "instance/instance_chipid.h"
385 #include "instance/instance_uart1.h"
386 #include "instance/instance_efc.h"
387 #include "instance/instance_pioa.h"
388 #include "instance/instance_piob.h"
389 #include "instance/instance_piod.h"
390 #include "instance/instance_rstc.h"
391 #include "instance/instance_supc.h"
392 #include "instance/instance_rtt.h"
393 #include "instance/instance_wdt.h"
394 #include "instance/instance_rtc.h"
395 #include "instance/instance_gpbr.h"
396 #include "instance/instance_rswdt.h"
397 #include "instance/instance_uart2.h"
398 #include "instance/instance_uart3.h"
399 #include "instance/instance_uart4.h"
401 #endif /* __rtems__ */
402 
403 /* ************************************************************************** */
404 /* PERIPHERAL ID DEFINITIONS FOR SAMV71N21 */
405 /* ************************************************************************** */
408 
409 #define ID_SUPC ( 0)
410 #define ID_RSTC ( 1)
411 #define ID_RTC ( 2)
412 #define ID_RTT ( 3)
413 #define ID_WDT ( 4)
414 #define ID_PMC ( 5)
415 #define ID_EFC ( 6)
416 #define ID_UART0 ( 7)
417 #define ID_UART1 ( 8)
418 #define ID_PIOA (10)
419 #define ID_PIOB (11)
420 #define ID_USART0 (13)
421 #define ID_USART1 (14)
422 #define ID_USART2 (15)
423 #define ID_PIOD (16)
424 #define ID_HSMCI (18)
425 #define ID_TWIHS0 (19)
426 #define ID_TWIHS1 (20)
427 #define ID_SPI0 (21)
428 #define ID_SSC (22)
429 #define ID_TC0 (23)
430 #define ID_TC1 (24)
431 #define ID_TC2 (25)
432 #define ID_AFEC0 (29)
433 #define ID_DACC (30)
434 #define ID_PWM0 (31)
435 #define ID_ICM (32)
436 #define ID_ACC (33)
437 #define ID_USBHS (34)
438 #define ID_MCAN0 (35)
439 #define ID_MCAN1 (37)
440 #define ID_GMAC (39)
441 #define ID_AFEC1 (40)
442 #define ID_TWIHS2 (41)
443 #define ID_SPI1 (42)
444 #define ID_QSPI (43)
445 #define ID_UART2 (44)
446 #define ID_UART3 (45)
447 #define ID_UART4 (46)
448 #define ID_TC9 (50)
449 #define ID_TC10 (51)
450 #define ID_TC11 (52)
451 #define ID_MLB (53)
452 #define ID_AES (56)
453 #define ID_TRNG (57)
454 #define ID_XDMAC (58)
455 #define ID_ISI (59)
456 #define ID_PWM1 (60)
457 #define ID_RSWDT (63)
459 #define ID_PERIPH_COUNT (64)
461 
462 /* ************************************************************************** */
463 /* BASE ADDRESS DEFINITIONS FOR SAMV71N21 */
464 /* ************************************************************************** */
467 
468 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
469 #define HSMCI (0x40000000U)
470 #define SSC (0x40004000U)
471 #define SPI0 (0x40008000U)
472 #define TC0 (0x4000C000U)
473 #define TWIHS0 (0x40018000U)
474 #define TWIHS1 (0x4001C000U)
475 #define PWM0 (0x40020000U)
476 #define USART0 (0x40024000U)
477 #define USART1 (0x40028000U)
478 #define USART2 (0x4002C000U)
479 #define MCAN0 (0x40030000U)
480 #define MCAN1 (0x40034000U)
481 #define USBHS (0x40038000U)
482 #define AFEC0 (0x4003C000U)
483 #define DACC (0x40040000U)
484 #define ACC (0x40044000U)
485 #define ICM (0x40048000U)
486 #define ISI (0x4004C000U)
487 #define GMAC (0x40050000U)
488 #define TC3 (0x40054000U)
489 #define SPI1 (0x40058000U)
490 #define PWM1 (0x4005C000U)
491 #define TWIHS2 (0x40060000U)
492 #define AFEC1 (0x40064000U)
493 #define MLB (0x40068000U)
494 #define AES (0x4006C000U)
495 #define TRNG (0x40070000U)
496 #define XDMAC (0x40078000U)
497 #define QSPI (0x4007C000U)
498 #define MATRIX (0x40088000U)
499 #define UTMI (0x400E0400U)
500 #define PMC (0x400E0600U)
501 #define UART0 (0x400E0800U)
502 #define CHIPID (0x400E0940U)
503 #define UART1 (0x400E0A00U)
504 #define EFC (0x400E0C00U)
505 #define PIOA (0x400E0E00U)
506 #define PIOB (0x400E1000U)
507 #define PIOD (0x400E1400U)
508 #define RSTC (0x400E1800U)
509 #define SUPC (0x400E1810U)
510 #define RTT (0x400E1830U)
511 #define WDT (0x400E1850U)
512 #define RTC (0x400E1860U)
513 #define GPBR (0x400E1890U)
514 #define RSWDT (0x400E1900U)
515 #define UART2 (0x400E1A00U)
516 #define UART3 (0x400E1C00U)
517 #define UART4 (0x400E1E00U)
518 #else
519 #define HSMCI ((Hsmci *)0x40000000U)
520 #define SSC ((Ssc *)0x40004000U)
521 #define SPI0 ((Spi *)0x40008000U)
522 #define TC0 ((Tc *)0x4000C000U)
523 #define TWIHS0 ((Twihs *)0x40018000U)
524 #define TWIHS1 ((Twihs *)0x4001C000U)
525 #define PWM0 ((Pwm *)0x40020000U)
526 #define USART0 ((Usart *)0x40024000U)
527 #define USART1 ((Usart *)0x40028000U)
528 #define USART2 ((Usart *)0x4002C000U)
529 #define MCAN0 ((Mcan *)0x40030000U)
530 #define MCAN1 ((Mcan *)0x40034000U)
531 #define USBHS ((Usbhs *)0x40038000U)
532 #define AFEC0 ((Afec *)0x4003C000U)
533 #define DACC ((Dacc *)0x40040000U)
534 #define ACC ((Acc *)0x40044000U)
535 #define ICM ((Icm *)0x40048000U)
536 #define ISI ((Isi *)0x4004C000U)
537 #define GMAC ((Gmac *)0x40050000U)
538 #define TC3 ((Tc *)0x40054000U)
539 #define SPI1 ((Spi *)0x40058000U)
540 #define PWM1 ((Pwm *)0x4005C000U)
541 #define TWIHS2 ((Twihs *)0x40060000U)
542 #define AFEC1 ((Afec *)0x40064000U)
543 #define MLB ((Mlb *)0x40068000U)
544 #define AES ((Aes *)0x4006C000U)
545 #define TRNG ((Trng *)0x40070000U)
546 #define XDMAC ((Xdmac *)0x40078000U)
547 #define QSPI ((Qspi *)0x4007C000U)
548 #define MATRIX ((Matrix *)0x40088000U)
549 #define UTMI ((Utmi *)0x400E0400U)
550 #define PMC ((Pmc *)0x400E0600U)
551 #define UART0 ((Uart *)0x400E0800U)
552 #define CHIPID ((Chipid *)0x400E0940U)
553 #define UART1 ((Uart *)0x400E0A00U)
554 #define EFC ((Efc *)0x400E0C00U)
555 #define PIOA ((Pio *)0x400E0E00U)
556 #define PIOB ((Pio *)0x400E1000U)
557 #define PIOD ((Pio *)0x400E1400U)
558 #define RSTC ((Rstc *)0x400E1800U)
559 #define SUPC ((Supc *)0x400E1810U)
560 #define RTT ((Rtt *)0x400E1830U)
561 #define WDT ((Wdt *)0x400E1850U)
562 #define RTC ((Rtc *)0x400E1860U)
563 #define GPBR ((Gpbr *)0x400E1890U)
564 #define RSWDT ((Rswdt *)0x400E1900U)
565 #define UART2 ((Uart *)0x400E1A00U)
566 #define UART3 ((Uart *)0x400E1C00U)
567 #define UART4 ((Uart *)0x400E1E00U)
568 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
569 
571 /* ************************************************************************** */
572 /* PIO DEFINITIONS FOR SAMV71N21 */
573 /* ************************************************************************** */
576 
577 #include "pio/pio_samv71n21.h"
580 /* ************************************************************************** */
581 /* MEMORY MAPPING DEFINITIONS FOR SAMV71N21 */
582 /* ************************************************************************** */
583 
584 #define IFLASH_SIZE (0x200000u)
585 #define IFLASH_PAGE_SIZE (512u)
586 #define IFLASH_LOCK_REGION_SIZE (8192u)
587 #define IFLASH_NB_OF_PAGES (4096u)
588 #define IFLASH_NB_OF_LOCK_BITS (128u)
589 #define IRAM_SIZE (0x60000u)
590 
591 #define QSPIMEM_ADDR (0x80000000u)
592 #define AXIMX_ADDR (0xA0000000u)
593 #define ITCM_ADDR (0x00000000u)
594 #define IFLASH_ADDR (0x00400000u)
595 #define IROM_ADDR (0x00800000u)
596 #define DTCM_ADDR (0x20000000u)
597 #define IRAM_ADDR (0x20400000u)
598 #define EBI_CS0_ADDR (0x60000000u)
599 #define EBI_CS1_ADDR (0x61000000u)
600 #define EBI_CS2_ADDR (0x62000000u)
601 #define EBI_CS3_ADDR (0x63000000u)
602 #define SDRAM_CS_ADDR (0x70000000u)
604 /* ************************************************************************** */
605 /* MISCELLANEOUS DEFINITIONS FOR SAMV71N21 */
606 /* ************************************************************************** */
607 
608 #define CHIP_JTAGID (0x05B3D03FUL)
609 #define CHIP_CIDR (0xA1220E00UL)
610 #define CHIP_EXID (0x00000001UL)
611 
612 /* ************************************************************************** */
613 /* ELECTRICAL DEFINITIONS FOR SAMV71N21 */
614 /* ************************************************************************** */
615 
616 /* %ATMEL_ELECTRICAL% */
617 
618 /* Device characteristics */
619 #define CHIP_FREQ_SLCK_RC_MIN (20000UL)
620 #define CHIP_FREQ_SLCK_RC (32000UL)
621 #define CHIP_FREQ_SLCK_RC_MAX (44000UL)
622 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
623 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
624 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
625 #define CHIP_FREQ_CPU_MAX (120000000UL)
626 #define CHIP_FREQ_XTAL_32K (32768UL)
627 #define CHIP_FREQ_XTAL_12M (12000000UL)
628 
629 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
630 #define CHIP_FREQ_FWS_0 (20000000UL)
631 #define CHIP_FREQ_FWS_1 (40000000UL)
632 #define CHIP_FREQ_FWS_2 (60000000UL)
633 #define CHIP_FREQ_FWS_3 (80000000UL)
634 #define CHIP_FREQ_FWS_4 (100000000UL)
635 #define CHIP_FREQ_FWS_5 (123000000UL)
637 #ifdef __cplusplus
638 }
639 #endif
640 
643 #endif /* _SAMV71N21_ */
Definition: samv71n21.h:82
void BusFault_Handler(void)
Default BusFault interrupt handler.
Definition: exceptions.c:193
Definition: samv71n21.h:78
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Definition: samv71n21.h:71
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
Definition: samv71n21.h:66
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Definition: samv71n21.h:104
Definition: same70j19.h:121
Definition: samv71n21.h:73
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Definition: samv71n21.h:109
enum IRQn IRQn_Type
Definition: samv71n21.h:77
Definition: samv71n21.h:116
void HardFault_Handler(void)
Default HardFault interrupt handler.
Definition: exceptions.c:168
void UsageFault_Handler(void)
Default UsageFault interrupt handler.
Definition: exceptions.c:207
Definition: samv71n21.h:83
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Definition: samv71n21.h:115
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Definition: samv71n21.h:67
void MemManage_Handler(void)
Default MemManage interrupt handler.
Definition: exceptions.c:180
Definition: samv71n21.h:60
Definition: samv71n21.h:118
Definition: samv71n21.h:103
Definition: samv71n21.h:63
IRQn
Definition: same70j19.h:57
Definition: samv71n21.h:87
void NMI_Handler(void)
Default NMI interrupt handler.
Definition: exceptions.c:53
Definition: samv71n21.h:102
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