samv71n21.h

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/*                  Atmel Microcontroller Software Support                      */
/*                       SAM Software Package License                           */
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/* Copyright (c) 2015, Atmel Corporation                                        */
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#ifndef _SAMV71N21_
#define _SAMV71N21_


#ifdef __cplusplus
 extern "C" {
#endif

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
#endif

/* ************************************************************************** */
/*   CMSIS DEFINITIONS FOR SAMV71N21 */
/* ************************************************************************** */

typedef enum IRQn
{
/******  Cortex-M7 Processor Exceptions Numbers ******************************/
  NonMaskableInt_IRQn   = -14, 
  HardFault_IRQn        = -13, 
  MemoryManagement_IRQn = -12, 
  BusFault_IRQn         = -11, 
  UsageFault_IRQn       = -10, 
  SVCall_IRQn           = -5,  
  DebugMonitor_IRQn     = -4,  
  PendSV_IRQn           = -2,  
  SysTick_IRQn          = -1,  
/******  SAMV71N21 specific Interrupt Numbers *********************************/

  SUPC_IRQn            =  0, 
  RSTC_IRQn            =  1, 
  RTC_IRQn             =  2, 
  RTT_IRQn             =  3, 
  WDT_IRQn             =  4, 
  PMC_IRQn             =  5, 
  EFC_IRQn             =  6, 
  UART0_IRQn           =  7, 
  UART1_IRQn           =  8, 
  PIOA_IRQn            = 10, 
  PIOB_IRQn            = 11, 
  USART0_IRQn          = 13, 
  USART1_IRQn          = 14, 
  USART2_IRQn          = 15, 
  PIOD_IRQn            = 16, 
  HSMCI_IRQn           = 18, 
  TWIHS0_IRQn          = 19, 
  TWIHS1_IRQn          = 20, 
  SPI0_IRQn            = 21, 
  SSC_IRQn             = 22, 
  TC0_IRQn             = 23, 
  TC1_IRQn             = 24, 
  TC2_IRQn             = 25, 
  AFEC0_IRQn           = 29, 
  DACC_IRQn            = 30, 
  PWM0_IRQn            = 31, 
  ICM_IRQn             = 32, 
  ACC_IRQn             = 33, 
  USBHS_IRQn           = 34, 
  MCAN0_IRQn           = 35, 
  MCAN1_IRQn           = 37, 
  GMAC_IRQn            = 39, 
  AFEC1_IRQn           = 40, 
  TWIHS2_IRQn          = 41, 
  SPI1_IRQn            = 42, 
  QSPI_IRQn            = 43, 
  UART2_IRQn           = 44, 
  UART3_IRQn           = 45, 
  UART4_IRQn           = 46, 
  TC9_IRQn             = 50, 
  TC10_IRQn            = 51, 
  TC11_IRQn            = 52, 
  MLB_IRQn             = 53, 
  AES_IRQn             = 56, 
  TRNG_IRQn            = 57, 
  XDMAC_IRQn           = 58, 
  ISI_IRQn             = 59, 
  PWM1_IRQn            = 60, 
  RSWDT_IRQn           = 63, 
  PERIPH_COUNT_IRQn    = 64  
} IRQn_Type;

typedef struct _DeviceVectors
{
  /* Stack pointer */
  void* pvStack;

  /* Cortex-M handlers */
  void* pfnReset_Handler;
  void* pfnNMI_Handler;
  void* pfnHardFault_Handler;
  void* pfnMemManage_Handler;
  void* pfnBusFault_Handler;
  void* pfnUsageFault_Handler;
  void* pfnReserved1_Handler;
  void* pfnReserved2_Handler;
  void* pfnReserved3_Handler;
  void* pfnReserved4_Handler;
  void* pfnSVC_Handler;
  void* pfnDebugMon_Handler;
  void* pfnReserved5_Handler;
  void* pfnPendSV_Handler;
  void* pfnSysTick_Handler;

  /* Peripheral handlers */
  void* pfnSUPC_Handler;   /*  0 Supply Controller */
  void* pfnRSTC_Handler;   /*  1 Reset Controller */
  void* pfnRTC_Handler;    /*  2 Real Time Clock */
  void* pfnRTT_Handler;    /*  3 Real Time Timer */
  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
  void* pfnPMC_Handler;    /*  5 Power Management Controller */
  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
  void* pfnUART0_Handler;  /*  7 UART 0 */
  void* pfnUART1_Handler;  /*  8 UART 1 */
  void* pvReserved9;
  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A */
  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
  void* pvReserved12;
  void* pfnUSART0_Handler; /* 13 USART 0 */
  void* pfnUSART1_Handler; /* 14 USART 1 */
  void* pfnUSART2_Handler; /* 15 USART 2 */
  void* pfnPIOD_Handler;   /* 16 Parallel I/O Controller D */
  void* pvReserved17;
  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
  void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
  void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
  void* pfnSPI0_Handler;   /* 21 Serial Peripheral Interface 0 */
  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controller */
  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
  void* pvReserved26;
  void* pvReserved27;
  void* pvReserved28;
  void* pfnAFEC0_Handler;  /* 29 Analog Front End 0 */
  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
  void* pfnPWM0_Handler;   /* 31 Pulse Width Modulation 0 */
  void* pfnICM_Handler;    /* 32 Integrity Check Monitor */
  void* pfnACC_Handler;    /* 33 Analog Comparator */
  void* pfnUSBHS_Handler;  /* 34 USB Host / Device Controller */
  void* pfnMCAN0_Handler;  /* 35 MCAN Controller 0 */
  void* pvReserved36;
  void* pfnMCAN1_Handler;  /* 37 MCAN Controller 1 */
  void* pvReserved38;
  void* pfnGMAC_Handler;   /* 39 Ethernet MAC */
  void* pfnAFEC1_Handler;  /* 40 Analog Front End 1 */
  void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
  void* pfnSPI1_Handler;   /* 42 Serial Peripheral Interface 1 */
  void* pfnQSPI_Handler;   /* 43 Quad I/O Serial Peripheral Interface */
  void* pfnUART2_Handler;  /* 44 UART 2 */
  void* pfnUART3_Handler;  /* 45 UART 3 */
  void* pfnUART4_Handler;  /* 46 UART 4 */
  void* pvReserved47;
  void* pvReserved48;
  void* pvReserved49;
  void* pfnTC9_Handler;    /* 50 Timer/Counter 9 */
  void* pfnTC10_Handler;   /* 51 Timer/Counter 10 */
  void* pfnTC11_Handler;   /* 52 Timer/Counter 11 */
  void* pfnMLB_Handler;    /* 53 MediaLB */
  void* pvReserved54;
  void* pvReserved55;
  void* pfnAES_Handler;    /* 56 AES */
  void* pfnTRNG_Handler;   /* 57 True Random Generator */
  void* pfnXDMAC_Handler;  /* 58 DMA */
  void* pfnISI_Handler;    /* 59 Camera Interface */
  void* pfnPWM1_Handler;   /* 60 Pulse Width Modulation 1 */
  void* pvReserved61;
  void* pvReserved62;
  void* pfnRSWDT_Handler;  /* 63 Reinforced Secure Watchdog Timer */
} DeviceVectors;

/* Cortex-M7 core handlers */
void Reset_Handler      ( void );
void NMI_Handler        ( void );
void HardFault_Handler  ( void );
void MemManage_Handler  ( void );
void BusFault_Handler   ( void );
void UsageFault_Handler ( void );
void SVC_Handler        ( void );
void DebugMon_Handler   ( void );
void PendSV_Handler     ( void );
void SysTick_Handler    ( void );

/* Peripherals handlers */
void ACC_Handler        ( void );
void AES_Handler        ( void );
void AFEC0_Handler      ( void );
void AFEC1_Handler      ( void );
void DACC_Handler       ( void );
void EFC_Handler        ( void );
void GMAC_Handler       ( void );
void HSMCI_Handler      ( void );
void ICM_Handler        ( void );
void ISI_Handler        ( void );
void MCAN0_Handler      ( void );
void MCAN1_Handler      ( void );
void MLB_Handler        ( void );
void PIOA_Handler       ( void );
void PIOB_Handler       ( void );
void PIOD_Handler       ( void );
void PMC_Handler        ( void );
void PWM0_Handler       ( void );
void PWM1_Handler       ( void );
void QSPI_Handler       ( void );
void RSTC_Handler       ( void );
void RSWDT_Handler      ( void );
void RTC_Handler        ( void );
void RTT_Handler        ( void );
void SPI0_Handler       ( void );
void SPI1_Handler       ( void );
void SSC_Handler        ( void );
void SUPC_Handler       ( void );
void TC0_Handler        ( void );
void TC1_Handler        ( void );
void TC2_Handler        ( void );
void TC9_Handler        ( void );
void TC10_Handler       ( void );
void TC11_Handler       ( void );
void TRNG_Handler       ( void );
void TWIHS0_Handler     ( void );
void TWIHS1_Handler     ( void );
void TWIHS2_Handler     ( void );
void UART0_Handler      ( void );
void UART1_Handler      ( void );
void UART2_Handler      ( void );
void UART3_Handler      ( void );
void UART4_Handler      ( void );
void USART0_Handler     ( void );
void USART1_Handler     ( void );
void USART2_Handler     ( void );
void USBHS_Handler      ( void );
void WDT_Handler        ( void );
void XDMAC_Handler      ( void );

#define __CM7_REV              0x0000 
#define __MPU_PRESENT          1      
#define __NVIC_PRIO_BITS       3      
#define __FPU_PRESENT          1      
#define __FPU_DP               1      
#define __ICACHE_PRESENT       1      
#define __DCACHE_PRESENT       1      
#define __DTCM_PRESENT         1      
#define __ITCM_PRESENT         1      
#define __Vendor_SysTickConfig 0      
/*
 * \brief CMSIS includes
 */

#include <core_cm7.h>
#if !defined DONT_USE_CMSIS_INIT
#include "system_samv71.h"
#endif /* DONT_USE_CMSIS_INIT */

/* ************************************************************************** */
/* ************************************************************************** */

#include "component/component_acc.h"
#include "component/component_aes.h"
#include "component/component_afec.h"
#include "component/component_chipid.h"
#include "component/component_dacc.h"
#include "component/component_efc.h"
#include "component/component_gmac.h"
#include "component/component_gpbr.h"
#include "component/component_hsmci.h"
#include "component/component_icm.h"
#include "component/component_isi.h"
#include "component/component_matrix.h"
#include "component/component_mcan.h"
#include "component/component_mlb.h"
#include "component/component_pio.h"
#include "component/component_pmc.h"
#include "component/component_pwm.h"
#include "component/component_qspi.h"
#include "component/component_rstc.h"
#include "component/component_rswdt.h"
#include "component/component_rtc.h"
#include "component/component_rtt.h"
#include "component/component_spi.h"
#include "component/component_ssc.h"
#include "component/component_supc.h"
#include "component/component_tc.h"
#include "component/component_trng.h"
#include "component/component_twihs.h"
#include "component/component_uart.h"
#include "component/component_usart.h"
#include "component/component_usbhs.h"
#include "component/component_utmi.h"
#include "component/component_wdt.h"
#include "component/component_xdmac.h"
#ifndef __rtems__
/* ************************************************************************** */
/*   REGISTER ACCESS DEFINITIONS FOR SAMV71N21 */
/* ************************************************************************** */

#include "instance/instance_hsmci.h"
#include "instance/instance_ssc.h"
#include "instance/instance_spi0.h"
#include "instance/instance_tc0.h"
#include "instance/instance_twihs0.h"
#include "instance/instance_twihs1.h"
#include "instance/instance_pwm0.h"
#include "instance/instance_usart0.h"
#include "instance/instance_usart1.h"
#include "instance/instance_usart2.h"
#include "instance/instance_mcan0.h"
#include "instance/instance_mcan1.h"
#include "instance/instance_usbhs.h"
#include "instance/instance_afec0.h"
#include "instance/instance_dacc.h"
#include "instance/instance_acc.h"
#include "instance/instance_icm.h"
#include "instance/instance_isi.h"
#include "instance/instance_gmac.h"
#include "instance/instance_tc3.h"
#include "instance/instance_spi1.h"
#include "instance/instance_pwm1.h"
#include "instance/instance_twihs2.h"
#include "instance/instance_afec1.h"
#include "instance/instance_mlb.h"
#include "instance/instance_aes.h"
#include "instance/instance_trng.h"
#include "instance/instance_xdmac.h"
#include "instance/instance_qspi.h"
#include "instance/instance_matrix.h"
#include "instance/instance_utmi.h"
#include "instance/instance_pmc.h"
#include "instance/instance_uart0.h"
#include "instance/instance_chipid.h"
#include "instance/instance_uart1.h"
#include "instance/instance_efc.h"
#include "instance/instance_pioa.h"
#include "instance/instance_piob.h"
#include "instance/instance_piod.h"
#include "instance/instance_rstc.h"
#include "instance/instance_supc.h"
#include "instance/instance_rtt.h"
#include "instance/instance_wdt.h"
#include "instance/instance_rtc.h"
#include "instance/instance_gpbr.h"
#include "instance/instance_rswdt.h"
#include "instance/instance_uart2.h"
#include "instance/instance_uart3.h"
#include "instance/instance_uart4.h"
#endif /* __rtems__ */

/* ************************************************************************** */
/*   PERIPHERAL ID DEFINITIONS FOR SAMV71N21 */
/* ************************************************************************** */

#define ID_SUPC   ( 0) 
#define ID_RSTC   ( 1) 
#define ID_RTC    ( 2) 
#define ID_RTT    ( 3) 
#define ID_WDT    ( 4) 
#define ID_PMC    ( 5) 
#define ID_EFC    ( 6) 
#define ID_UART0  ( 7) 
#define ID_UART1  ( 8) 
#define ID_PIOA   (10) 
#define ID_PIOB   (11) 
#define ID_USART0 (13) 
#define ID_USART1 (14) 
#define ID_USART2 (15) 
#define ID_PIOD   (16) 
#define ID_HSMCI  (18) 
#define ID_TWIHS0 (19) 
#define ID_TWIHS1 (20) 
#define ID_SPI0   (21) 
#define ID_SSC    (22) 
#define ID_TC0    (23) 
#define ID_TC1    (24) 
#define ID_TC2    (25) 
#define ID_AFEC0  (29) 
#define ID_DACC   (30) 
#define ID_PWM0   (31) 
#define ID_ICM    (32) 
#define ID_ACC    (33) 
#define ID_USBHS  (34) 
#define ID_MCAN0  (35) 
#define ID_MCAN1  (37) 
#define ID_GMAC   (39) 
#define ID_AFEC1  (40) 
#define ID_TWIHS2 (41) 
#define ID_SPI1   (42) 
#define ID_QSPI   (43) 
#define ID_UART2  (44) 
#define ID_UART3  (45) 
#define ID_UART4  (46) 
#define ID_TC9    (50) 
#define ID_TC10   (51) 
#define ID_TC11   (52) 
#define ID_MLB    (53) 
#define ID_AES    (56) 
#define ID_TRNG   (57) 
#define ID_XDMAC  (58) 
#define ID_ISI    (59) 
#define ID_PWM1   (60) 
#define ID_RSWDT  (63) 
#define ID_PERIPH_COUNT (64) 

/* ************************************************************************** */
/*   BASE ADDRESS DEFINITIONS FOR SAMV71N21 */
/* ************************************************************************** */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define HSMCI  (0x40000000U) 
#define SSC    (0x40004000U) 
#define SPI0   (0x40008000U) 
#define TC0    (0x4000C000U) 
#define TWIHS0 (0x40018000U) 
#define TWIHS1 (0x4001C000U) 
#define PWM0   (0x40020000U) 
#define USART0 (0x40024000U) 
#define USART1 (0x40028000U) 
#define USART2 (0x4002C000U) 
#define MCAN0  (0x40030000U) 
#define MCAN1  (0x40034000U) 
#define USBHS  (0x40038000U) 
#define AFEC0  (0x4003C000U) 
#define DACC   (0x40040000U) 
#define ACC    (0x40044000U) 
#define ICM    (0x40048000U) 
#define ISI    (0x4004C000U) 
#define GMAC   (0x40050000U) 
#define TC3    (0x40054000U) 
#define SPI1   (0x40058000U) 
#define PWM1   (0x4005C000U) 
#define TWIHS2 (0x40060000U) 
#define AFEC1  (0x40064000U) 
#define MLB    (0x40068000U) 
#define AES    (0x4006C000U) 
#define TRNG   (0x40070000U) 
#define XDMAC  (0x40078000U) 
#define QSPI   (0x4007C000U) 
#define MATRIX (0x40088000U) 
#define UTMI   (0x400E0400U) 
#define PMC    (0x400E0600U) 
#define UART0  (0x400E0800U) 
#define CHIPID (0x400E0940U) 
#define UART1  (0x400E0A00U) 
#define EFC    (0x400E0C00U) 
#define PIOA   (0x400E0E00U) 
#define PIOB   (0x400E1000U) 
#define PIOD   (0x400E1400U) 
#define RSTC   (0x400E1800U) 
#define SUPC   (0x400E1810U) 
#define RTT    (0x400E1830U) 
#define WDT    (0x400E1850U) 
#define RTC    (0x400E1860U) 
#define GPBR   (0x400E1890U) 
#define RSWDT  (0x400E1900U) 
#define UART2  (0x400E1A00U) 
#define UART3  (0x400E1C00U) 
#define UART4  (0x400E1E00U) 
#else
#define HSMCI  ((Hsmci  *)0x40000000U) 
#define SSC    ((Ssc    *)0x40004000U) 
#define SPI0   ((Spi    *)0x40008000U) 
#define TC0    ((Tc     *)0x4000C000U) 
#define TWIHS0 ((Twihs  *)0x40018000U) 
#define TWIHS1 ((Twihs  *)0x4001C000U) 
#define PWM0   ((Pwm    *)0x40020000U) 
#define USART0 ((Usart  *)0x40024000U) 
#define USART1 ((Usart  *)0x40028000U) 
#define USART2 ((Usart  *)0x4002C000U) 
#define MCAN0  ((Mcan   *)0x40030000U) 
#define MCAN1  ((Mcan   *)0x40034000U) 
#define USBHS  ((Usbhs  *)0x40038000U) 
#define AFEC0  ((Afec   *)0x4003C000U) 
#define DACC   ((Dacc   *)0x40040000U) 
#define ACC    ((Acc    *)0x40044000U) 
#define ICM    ((Icm    *)0x40048000U) 
#define ISI    ((Isi    *)0x4004C000U) 
#define GMAC   ((Gmac   *)0x40050000U) 
#define TC3    ((Tc     *)0x40054000U) 
#define SPI1   ((Spi    *)0x40058000U) 
#define PWM1   ((Pwm    *)0x4005C000U) 
#define TWIHS2 ((Twihs  *)0x40060000U) 
#define AFEC1  ((Afec   *)0x40064000U) 
#define MLB    ((Mlb    *)0x40068000U) 
#define AES    ((Aes    *)0x4006C000U) 
#define TRNG   ((Trng   *)0x40070000U) 
#define XDMAC  ((Xdmac  *)0x40078000U) 
#define QSPI   ((Qspi   *)0x4007C000U) 
#define MATRIX ((Matrix *)0x40088000U) 
#define UTMI   ((Utmi   *)0x400E0400U) 
#define PMC    ((Pmc    *)0x400E0600U) 
#define UART0  ((Uart   *)0x400E0800U) 
#define CHIPID ((Chipid *)0x400E0940U) 
#define UART1  ((Uart   *)0x400E0A00U) 
#define EFC    ((Efc    *)0x400E0C00U) 
#define PIOA   ((Pio    *)0x400E0E00U) 
#define PIOB   ((Pio    *)0x400E1000U) 
#define PIOD   ((Pio    *)0x400E1400U) 
#define RSTC   ((Rstc   *)0x400E1800U) 
#define SUPC   ((Supc   *)0x400E1810U) 
#define RTT    ((Rtt    *)0x400E1830U) 
#define WDT    ((Wdt    *)0x400E1850U) 
#define RTC    ((Rtc    *)0x400E1860U) 
#define GPBR   ((Gpbr   *)0x400E1890U) 
#define RSWDT  ((Rswdt  *)0x400E1900U) 
#define UART2  ((Uart   *)0x400E1A00U) 
#define UART3  ((Uart   *)0x400E1C00U) 
#define UART4  ((Uart   *)0x400E1E00U) 
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* ************************************************************************** */
/*   PIO DEFINITIONS FOR SAMV71N21 */
/* ************************************************************************** */

#include "pio/pio_samv71n21.h"
/* ************************************************************************** */
/*   MEMORY MAPPING DEFINITIONS FOR SAMV71N21 */
/* ************************************************************************** */

#define IFLASH_SIZE             (0x200000u)
#define IFLASH_PAGE_SIZE        (512u)
#define IFLASH_LOCK_REGION_SIZE (8192u)
#define IFLASH_NB_OF_PAGES      (4096u)
#define IFLASH_NB_OF_LOCK_BITS  (128u)
#define IRAM_SIZE               (0x60000u)

#define QSPIMEM_ADDR  (0x80000000u) 
#define AXIMX_ADDR    (0xA0000000u) 
#define ITCM_ADDR     (0x00000000u) 
#define IFLASH_ADDR   (0x00400000u) 
#define IROM_ADDR     (0x00800000u) 
#define DTCM_ADDR     (0x20000000u) 
#define IRAM_ADDR     (0x20400000u) 
#define EBI_CS0_ADDR  (0x60000000u) 
#define EBI_CS1_ADDR  (0x61000000u) 
#define EBI_CS2_ADDR  (0x62000000u) 
#define EBI_CS3_ADDR  (0x63000000u) 
#define SDRAM_CS_ADDR (0x70000000u) 
/* ************************************************************************** */
/*   MISCELLANEOUS DEFINITIONS FOR SAMV71N21 */
/* ************************************************************************** */

#define CHIP_JTAGID (0x05B3D03FUL)
#define CHIP_CIDR   (0xA1220E00UL)
#define CHIP_EXID   (0x00000001UL)

/* ************************************************************************** */
/*   ELECTRICAL DEFINITIONS FOR SAMV71N21 */
/* ************************************************************************** */

/* %ATMEL_ELECTRICAL% */

/* Device characteristics */
#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
#define CHIP_FREQ_SLCK_RC               (32000UL)
#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
#define CHIP_FREQ_CPU_MAX               (120000000UL)
#define CHIP_FREQ_XTAL_32K              (32768UL)
#define CHIP_FREQ_XTAL_12M              (12000000UL)

/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
#define CHIP_FREQ_FWS_0                 (20000000UL)  
#define CHIP_FREQ_FWS_1                 (40000000UL)  
#define CHIP_FREQ_FWS_2                 (60000000UL)  
#define CHIP_FREQ_FWS_3                 (80000000UL)  
#define CHIP_FREQ_FWS_4                 (100000000UL) 
#define CHIP_FREQ_FWS_5                 (123000000UL) 
#ifdef __cplusplus
}
#endif

#endif /* _SAMV71N21_ */