component_uart.h

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#ifndef _SAMV71_UART_COMPONENT_
#define _SAMV71_UART_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  __O  uint32_t UART_CR;       
  __IO uint32_t UART_MR;       
  __O  uint32_t UART_IER;      
  __O  uint32_t UART_IDR;      
  __I  uint32_t UART_IMR;      
  __I  uint32_t UART_SR;       
  __I  uint32_t UART_RHR;      
  __O  uint32_t UART_THR;      
  __IO uint32_t UART_BRGR;     
  __IO uint32_t UART_CMPR;     
  __I  uint32_t Reserved1[47];
  __IO uint32_t UART_WPMR;     
  __I  uint32_t Reserved2[5];
  __I  uint32_t UART_VERSION;  
} Uart;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
#define UART_CR_RSTRX (0x1u << 2) 
#define UART_CR_RSTTX (0x1u << 3) 
#define UART_CR_RXEN (0x1u << 4) 
#define UART_CR_RXDIS (0x1u << 5) 
#define UART_CR_TXEN (0x1u << 6) 
#define UART_CR_TXDIS (0x1u << 7) 
#define UART_CR_RSTSTA (0x1u << 8) 
#define UART_CR_REQCLR (0x1u << 12) 
#define UART_CR_DBGE (0x1u << 15) 
/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
#define UART_MR_FILTER (0x1u << 4) 
#define   UART_MR_FILTER_DISABLED (0x0u << 4) 
#define   UART_MR_FILTER_ENABLED (0x1u << 4) 
#define UART_MR_PAR_Pos 9
#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) 
#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos)))
#define   UART_MR_PAR_EVEN (0x0u << 9) 
#define   UART_MR_PAR_ODD (0x1u << 9) 
#define   UART_MR_PAR_SPACE (0x2u << 9) 
#define   UART_MR_PAR_MARK (0x3u << 9) 
#define   UART_MR_PAR_NO (0x4u << 9) 
#define UART_MR_BRSRCCK (0x1u << 12) 
#define   UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) 
#define   UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) 
#define UART_MR_CHMODE_Pos 14
#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) 
#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos)))
#define   UART_MR_CHMODE_NORMAL (0x0u << 14) 
#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) 
#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) 
#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) 
/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
#define UART_IER_RXRDY (0x1u << 0) 
#define UART_IER_TXRDY (0x1u << 1) 
#define UART_IER_OVRE (0x1u << 5) 
#define UART_IER_FRAME (0x1u << 6) 
#define UART_IER_PARE (0x1u << 7) 
#define UART_IER_TXEMPTY (0x1u << 9) 
#define UART_IER_CMP (0x1u << 15) 
/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
#define UART_IDR_RXRDY (0x1u << 0) 
#define UART_IDR_TXRDY (0x1u << 1) 
#define UART_IDR_OVRE (0x1u << 5) 
#define UART_IDR_FRAME (0x1u << 6) 
#define UART_IDR_PARE (0x1u << 7) 
#define UART_IDR_TXEMPTY (0x1u << 9) 
#define UART_IDR_CMP (0x1u << 15) 
/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
#define UART_IMR_RXRDY (0x1u << 0) 
#define UART_IMR_TXRDY (0x1u << 1) 
#define UART_IMR_OVRE (0x1u << 5) 
#define UART_IMR_FRAME (0x1u << 6) 
#define UART_IMR_PARE (0x1u << 7) 
#define UART_IMR_TXEMPTY (0x1u << 9) 
#define UART_IMR_CMP (0x1u << 15) 
/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
#define UART_SR_RXRDY (0x1u << 0) 
#define UART_SR_TXRDY (0x1u << 1) 
#define UART_SR_OVRE (0x1u << 5) 
#define UART_SR_FRAME (0x1u << 6) 
#define UART_SR_PARE (0x1u << 7) 
#define UART_SR_TXEMPTY (0x1u << 9) 
#define UART_SR_CMP (0x1u << 15) 
#define UART_SR_SWES (0x1u << 21) 
#define UART_SR_CLKREQ (0x1u << 22) 
#define UART_SR_WKUPREQ (0x1u << 23) 
/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
#define UART_RHR_RXCHR_Pos 0
#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) 
/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
#define UART_THR_TXCHR_Pos 0
#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) 
#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
#define UART_BRGR_CD_Pos 0
#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) 
#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */
#define UART_CMPR_VAL1_Pos 0
#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) 
#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos)))
#define UART_CMPR_CMPMODE (0x1u << 12) 
#define   UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) 
#define   UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) 
#define UART_CMPR_CMPPAR (0x1u << 14) 
#define UART_CMPR_VAL2_Pos 16
#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) 
#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos)))
/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */
#define UART_WPMR_WPEN (0x1u << 0) 
#define UART_WPMR_WPKEY_Pos 8
#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) 
#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos)))
#define   UART_WPMR_WPKEY_PASSWD (0x554152u << 8) 
/* -------- UART_VERSION : (UART Offset: 0x00FC) Version Register -------- */
#define UART_VERSION_VERSION_Pos 0
#define UART_VERSION_VERSION_Msk (0xfffu << UART_VERSION_VERSION_Pos) 
#define UART_VERSION_MFN_Pos 16
#define UART_VERSION_MFN_Msk (0x7u << UART_VERSION_MFN_Pos) 


#endif /* _SAMV71_UART_COMPONENT_ */