RTEMS  5.1
component_spi.h
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2 /* Atmel Microcontroller Software Support */
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29 
30 #ifndef _SAMV71_SPI_COMPONENT_
31 #define _SAMV71_SPI_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  __O uint32_t SPI_CR;
43  __IO uint32_t SPI_MR;
44  __I uint32_t SPI_RDR;
45  __O uint32_t SPI_TDR;
46  __I uint32_t SPI_SR;
47  __O uint32_t SPI_IER;
48  __O uint32_t SPI_IDR;
49  __I uint32_t SPI_IMR;
50  __I uint32_t Reserved1[4];
51  __IO uint32_t SPI_CSR[4];
52  __I uint32_t Reserved2[41];
53  __IO uint32_t SPI_WPMR;
54  __I uint32_t SPI_WPSR;
55  __I uint32_t Reserved3[4];
56  __I uint32_t SPI_VERSION;
57 } Spi;
58 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
59 /* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
60 #define SPI_CR_SPIEN (0x1u << 0)
61 #define SPI_CR_SPIDIS (0x1u << 1)
62 #define SPI_CR_SWRST (0x1u << 7)
63 #define SPI_CR_LASTXFER (0x1u << 24)
64 /* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
65 #define SPI_MR_MSTR (0x1u << 0)
66 #define SPI_MR_PS (0x1u << 1)
67 #define SPI_MR_PCSDEC (0x1u << 2)
68 #define SPI_MR_MODFDIS (0x1u << 4)
69 #define SPI_MR_WDRBT (0x1u << 5)
70 #define SPI_MR_LLB (0x1u << 7)
71 #define SPI_MR_PCS_Pos 16
72 #define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos)
73 #define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
74 #define SPI_MR_DLYBCS_Pos 24
75 #define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos)
76 #define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
77 /* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
78 #define SPI_RDR_RD_Pos 0
79 #define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos)
80 #define SPI_RDR_PCS_Pos 16
81 #define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos)
82 /* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
83 #define SPI_TDR_TD_Pos 0
84 #define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos)
85 #define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
86 #define SPI_TDR_PCS_Pos 16
87 #define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos)
88 #define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
89 #define SPI_TDR_LASTXFER (0x1u << 24)
90 /* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
91 #define SPI_SR_RDRF (0x1u << 0)
92 #define SPI_SR_TDRE (0x1u << 1)
93 #define SPI_SR_MODF (0x1u << 2)
94 #define SPI_SR_OVRES (0x1u << 3)
95 #define SPI_SR_NSSR (0x1u << 8)
96 #define SPI_SR_TXEMPTY (0x1u << 9)
97 #define SPI_SR_UNDES (0x1u << 10)
98 #define SPI_SR_SPIENS (0x1u << 16)
99 /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
100 #define SPI_IER_RDRF (0x1u << 0)
101 #define SPI_IER_TDRE (0x1u << 1)
102 #define SPI_IER_MODF (0x1u << 2)
103 #define SPI_IER_OVRES (0x1u << 3)
104 #define SPI_IER_NSSR (0x1u << 8)
105 #define SPI_IER_TXEMPTY (0x1u << 9)
106 #define SPI_IER_UNDES (0x1u << 10)
107 /* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
108 #define SPI_IDR_RDRF (0x1u << 0)
109 #define SPI_IDR_TDRE (0x1u << 1)
110 #define SPI_IDR_MODF (0x1u << 2)
111 #define SPI_IDR_OVRES (0x1u << 3)
112 #define SPI_IDR_NSSR (0x1u << 8)
113 #define SPI_IDR_TXEMPTY (0x1u << 9)
114 #define SPI_IDR_UNDES (0x1u << 10)
115 /* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
116 #define SPI_IMR_RDRF (0x1u << 0)
117 #define SPI_IMR_TDRE (0x1u << 1)
118 #define SPI_IMR_MODF (0x1u << 2)
119 #define SPI_IMR_OVRES (0x1u << 3)
120 #define SPI_IMR_NSSR (0x1u << 8)
121 #define SPI_IMR_TXEMPTY (0x1u << 9)
122 #define SPI_IMR_UNDES (0x1u << 10)
123 /* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
124 #define SPI_CSR_CPOL (0x1u << 0)
125 #define SPI_CSR_NCPHA (0x1u << 1)
126 #define SPI_CSR_CSNAAT (0x1u << 2)
127 #define SPI_CSR_CSAAT (0x1u << 3)
128 #define SPI_CSR_BITS_Pos 4
129 #define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos)
130 #define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos)))
131 #define SPI_CSR_BITS_8_BIT (0x0u << 4)
132 #define SPI_CSR_BITS_9_BIT (0x1u << 4)
133 #define SPI_CSR_BITS_10_BIT (0x2u << 4)
134 #define SPI_CSR_BITS_11_BIT (0x3u << 4)
135 #define SPI_CSR_BITS_12_BIT (0x4u << 4)
136 #define SPI_CSR_BITS_13_BIT (0x5u << 4)
137 #define SPI_CSR_BITS_14_BIT (0x6u << 4)
138 #define SPI_CSR_BITS_15_BIT (0x7u << 4)
139 #define SPI_CSR_BITS_16_BIT (0x8u << 4)
140 #define SPI_CSR_SCBR_Pos 8
141 #define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos)
142 #define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
143 #define SPI_CSR_DLYBS_Pos 16
144 #define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos)
145 #define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
146 #define SPI_CSR_DLYBCT_Pos 24
147 #define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos)
148 #define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
149 /* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */
150 #define SPI_WPMR_WPEN (0x1u << 0)
151 #define SPI_WPMR_WPKEY_Pos 8
152 #define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos)
153 #define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
154 #define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8)
155 /* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
156 #define SPI_WPSR_WPVS (0x1u << 0)
157 #define SPI_WPSR_WPVSRC_Pos 8
158 #define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos)
159 /* -------- SPI_VERSION : (SPI Offset: 0xFC) Version Register -------- */
160 #define SPI_VERSION_VERSION_Pos 0
161 #define SPI_VERSION_VERSION_Msk (0xfffu << SPI_VERSION_VERSION_Pos)
162 #define SPI_VERSION_MFN_Pos 16
163 #define SPI_VERSION_MFN_Msk (0x7u << SPI_VERSION_MFN_Pos)
166 
167 
168 #endif /* _SAMV71_SPI_COMPONENT_ */
__IO
#define __IO
Definition: core_cm7.h:287
__O
#define __O
Definition: core_cm7.h:286
Spi
Spi hardware registers.
Definition: component_spi.h:41
__I
#define __I
Definition: core_cm7.h:284
Spi::SPI_VERSION
__I uint32_t SPI_VERSION
(Spi Offset: 0xFC) Version Register
Definition: component_spi.h:56
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