RTEMS  5.1
component_rtc.h
1 /* ---------------------------------------------------------------------------- */
2 /* Atmel Microcontroller Software Support */
3 /* SAM Software Package License */
4 /* ---------------------------------------------------------------------------- */
5 /* Copyright (c) 2015, Atmel Corporation */
6 /* */
7 /* All rights reserved. */
8 /* */
9 /* Redistribution and use in source and binary forms, with or without */
10 /* modification, are permitted provided that the following condition is met: */
11 /* */
12 /* - Redistributions of source code must retain the above copyright notice, */
13 /* this list of conditions and the disclaimer below. */
14 /* */
15 /* Atmel's name may not be used to endorse or promote products derived from */
16 /* this software without specific prior written permission. */
17 /* */
18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28 /* ---------------------------------------------------------------------------- */
29 
30 #ifndef _SAMV71_RTC_COMPONENT_
31 #define _SAMV71_RTC_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  __IO uint32_t RTC_CR;
43  __IO uint32_t RTC_MR;
44  __IO uint32_t RTC_TIMR;
45  __IO uint32_t RTC_CALR;
46  __IO uint32_t RTC_TIMALR;
47  __IO uint32_t RTC_CALALR;
48  __I uint32_t RTC_SR;
49  __O uint32_t RTC_SCCR;
50  __O uint32_t RTC_IER;
51  __O uint32_t RTC_IDR;
52  __I uint32_t RTC_IMR;
53  __I uint32_t RTC_VER;
54  __I uint32_t Reserved1[45];
55  __IO uint32_t RTC_WPMR;
56  __I uint32_t Reserved2[5];
57  __I uint32_t RTC_VERSION;
58 } Rtc;
59 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
60 /* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
61 #define RTC_CR_UPDTIM (0x1u << 0)
62 #define RTC_CR_UPDCAL (0x1u << 1)
63 #define RTC_CR_TIMEVSEL_Pos 8
64 #define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos)
65 #define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos)))
66 #define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8)
67 #define RTC_CR_TIMEVSEL_HOUR (0x1u << 8)
68 #define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8)
69 #define RTC_CR_TIMEVSEL_NOON (0x3u << 8)
70 #define RTC_CR_CALEVSEL_Pos 16
71 #define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos)
72 #define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos)))
73 #define RTC_CR_CALEVSEL_WEEK (0x0u << 16)
74 #define RTC_CR_CALEVSEL_MONTH (0x1u << 16)
75 #define RTC_CR_CALEVSEL_YEAR (0x2u << 16)
76 /* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
77 #define RTC_MR_HRMOD (0x1u << 0)
78 #define RTC_MR_PERSIAN (0x1u << 1)
79 #define RTC_MR_NEGPPM (0x1u << 4)
80 #define RTC_MR_CORRECTION_Pos 8
81 #define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos)
82 #define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))
83 #define RTC_MR_HIGHPPM (0x1u << 15)
84 #define RTC_MR_OUT0_Pos 16
85 #define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos)
86 #define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos)))
87 #define RTC_MR_OUT0_NO_WAVE (0x0u << 16)
88 #define RTC_MR_OUT0_FREQ1HZ (0x1u << 16)
89 #define RTC_MR_OUT0_FREQ32HZ (0x2u << 16)
90 #define RTC_MR_OUT0_FREQ64HZ (0x3u << 16)
91 #define RTC_MR_OUT0_FREQ512HZ (0x4u << 16)
92 #define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16)
93 #define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16)
94 #define RTC_MR_OUT0_PROG_PULSE (0x7u << 16)
95 #define RTC_MR_OUT1_Pos 20
96 #define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos)
97 #define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos)))
98 #define RTC_MR_OUT1_NO_WAVE (0x0u << 20)
99 #define RTC_MR_OUT1_FREQ1HZ (0x1u << 20)
100 #define RTC_MR_OUT1_FREQ32HZ (0x2u << 20)
101 #define RTC_MR_OUT1_FREQ64HZ (0x3u << 20)
102 #define RTC_MR_OUT1_FREQ512HZ (0x4u << 20)
103 #define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20)
104 #define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20)
105 #define RTC_MR_OUT1_PROG_PULSE (0x7u << 20)
106 #define RTC_MR_THIGH_Pos 24
107 #define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos)
108 #define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos)))
109 #define RTC_MR_THIGH_H_31MS (0x0u << 24)
110 #define RTC_MR_THIGH_H_16MS (0x1u << 24)
111 #define RTC_MR_THIGH_H_4MS (0x2u << 24)
112 #define RTC_MR_THIGH_H_976US (0x3u << 24)
113 #define RTC_MR_THIGH_H_488US (0x4u << 24)
114 #define RTC_MR_THIGH_H_122US (0x5u << 24)
115 #define RTC_MR_THIGH_H_30US (0x6u << 24)
116 #define RTC_MR_THIGH_H_15US (0x7u << 24)
117 #define RTC_MR_TPERIOD_Pos 28
118 #define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos)
119 #define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos)))
120 #define RTC_MR_TPERIOD_P_1S (0x0u << 28)
121 #define RTC_MR_TPERIOD_P_500MS (0x1u << 28)
122 #define RTC_MR_TPERIOD_P_250MS (0x2u << 28)
123 #define RTC_MR_TPERIOD_P_125MS (0x3u << 28)
124 /* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
125 #define RTC_TIMR_SEC_Pos 0
126 #define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos)
127 #define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
128 #define RTC_TIMR_MIN_Pos 8
129 #define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos)
130 #define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
131 #define RTC_TIMR_HOUR_Pos 16
132 #define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos)
133 #define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
134 #define RTC_TIMR_AMPM (0x1u << 22)
135 /* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
136 #define RTC_CALR_CENT_Pos 0
137 #define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos)
138 #define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
139 #define RTC_CALR_YEAR_Pos 8
140 #define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos)
141 #define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
142 #define RTC_CALR_MONTH_Pos 16
143 #define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos)
144 #define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
145 #define RTC_CALR_DAY_Pos 21
146 #define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos)
147 #define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
148 #define RTC_CALR_DATE_Pos 24
149 #define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos)
150 #define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
151 /* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
152 #define RTC_TIMALR_SEC_Pos 0
153 #define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos)
154 #define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
155 #define RTC_TIMALR_SECEN (0x1u << 7)
156 #define RTC_TIMALR_MIN_Pos 8
157 #define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos)
158 #define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
159 #define RTC_TIMALR_MINEN (0x1u << 15)
160 #define RTC_TIMALR_HOUR_Pos 16
161 #define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos)
162 #define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
163 #define RTC_TIMALR_AMPM (0x1u << 22)
164 #define RTC_TIMALR_HOUREN (0x1u << 23)
165 /* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
166 #define RTC_CALALR_MONTH_Pos 16
167 #define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos)
168 #define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
169 #define RTC_CALALR_MTHEN (0x1u << 23)
170 #define RTC_CALALR_DATE_Pos 24
171 #define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos)
172 #define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
173 #define RTC_CALALR_DATEEN (0x1u << 31)
174 /* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
175 #define RTC_SR_ACKUPD (0x1u << 0)
176 #define RTC_SR_ACKUPD_FREERUN (0x0u << 0)
177 #define RTC_SR_ACKUPD_UPDATE (0x1u << 0)
178 #define RTC_SR_ALARM (0x1u << 1)
179 #define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1)
180 #define RTC_SR_ALARM_ALARMEVENT (0x1u << 1)
181 #define RTC_SR_SEC (0x1u << 2)
182 #define RTC_SR_SEC_NO_SECEVENT (0x0u << 2)
183 #define RTC_SR_SEC_SECEVENT (0x1u << 2)
184 #define RTC_SR_TIMEV (0x1u << 3)
185 #define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3)
186 #define RTC_SR_TIMEV_TIMEVENT (0x1u << 3)
187 #define RTC_SR_CALEV (0x1u << 4)
188 #define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4)
189 #define RTC_SR_CALEV_CALEVENT (0x1u << 4)
190 #define RTC_SR_TDERR (0x1u << 5)
191 #define RTC_SR_TDERR_CORRECT (0x0u << 5)
192 #define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5)
193 /* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
194 #define RTC_SCCR_ACKCLR (0x1u << 0)
195 #define RTC_SCCR_ALRCLR (0x1u << 1)
196 #define RTC_SCCR_SECCLR (0x1u << 2)
197 #define RTC_SCCR_TIMCLR (0x1u << 3)
198 #define RTC_SCCR_CALCLR (0x1u << 4)
199 #define RTC_SCCR_TDERRCLR (0x1u << 5)
200 /* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
201 #define RTC_IER_ACKEN (0x1u << 0)
202 #define RTC_IER_ALREN (0x1u << 1)
203 #define RTC_IER_SECEN (0x1u << 2)
204 #define RTC_IER_TIMEN (0x1u << 3)
205 #define RTC_IER_CALEN (0x1u << 4)
206 #define RTC_IER_TDERREN (0x1u << 5)
207 /* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
208 #define RTC_IDR_ACKDIS (0x1u << 0)
209 #define RTC_IDR_ALRDIS (0x1u << 1)
210 #define RTC_IDR_SECDIS (0x1u << 2)
211 #define RTC_IDR_TIMDIS (0x1u << 3)
212 #define RTC_IDR_CALDIS (0x1u << 4)
213 #define RTC_IDR_TDERRDIS (0x1u << 5)
214 /* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
215 #define RTC_IMR_ACK (0x1u << 0)
216 #define RTC_IMR_ALR (0x1u << 1)
217 #define RTC_IMR_SEC (0x1u << 2)
218 #define RTC_IMR_TIM (0x1u << 3)
219 #define RTC_IMR_CAL (0x1u << 4)
220 #define RTC_IMR_TDERR (0x1u << 5)
221 /* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
222 #define RTC_VER_NVTIM (0x1u << 0)
223 #define RTC_VER_NVCAL (0x1u << 1)
224 #define RTC_VER_NVTIMALR (0x1u << 2)
225 #define RTC_VER_NVCALALR (0x1u << 3)
226 /* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */
227 #define RTC_WPMR_WPEN (0x1u << 0)
228 #define RTC_WPMR_WPKEY_Pos 8
229 #define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos)
230 #define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
231 #define RTC_WPMR_WPKEY_PASSWD (0x525443u << 8)
232 /* -------- RTC_VERSION : (RTC Offset: 0xFC) Version Register -------- */
233 #define RTC_VERSION_VERSION_Pos 0
234 #define RTC_VERSION_VERSION_Msk (0xfffu << RTC_VERSION_VERSION_Pos)
235 #define RTC_VERSION_MFN_Pos 16
236 #define RTC_VERSION_MFN_Msk (0x7u << RTC_VERSION_MFN_Pos)
239 
240 
241 #endif /* _SAMV71_RTC_COMPONENT_ */
__IO
#define __IO
Definition: core_cm7.h:287
__O
#define __O
Definition: core_cm7.h:286
Rtc::RTC_VERSION
__I uint32_t RTC_VERSION
(Rtc Offset: 0xFC) Version Register
Definition: component_rtc.h:57
__I
#define __I
Definition: core_cm7.h:284
Rtc
Rtc hardware registers.
Definition: component_rtc.h:41
Generated by   doxygen 1.8.15