RTEMS  5.1
component_qspi.h
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2 /* Atmel Microcontroller Software Support */
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29 
30 #ifndef _SAMV71_QSPI_COMPONENT_
31 #define _SAMV71_QSPI_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  __O uint32_t QSPI_CR;
43  __IO uint32_t QSPI_MR;
44  __I uint32_t QSPI_RDR;
45  __O uint32_t QSPI_TDR;
46  __I uint32_t QSPI_SR;
47  __O uint32_t QSPI_IER;
48  __O uint32_t QSPI_IDR;
49  __I uint32_t QSPI_IMR;
50  __IO uint32_t QSPI_SCR;
51  __I uint32_t Reserved1[3];
52  __IO uint32_t QSPI_IAR;
53  __IO uint32_t QSPI_ICR;
54  __IO uint32_t QSPI_IFR;
55  __I uint32_t Reserved2[1];
56  __IO uint32_t QSPI_SMR;
57  __O uint32_t QSPI_SKR;
58  __I uint32_t Reserved3[39];
59  __IO uint32_t QSPI_WPMR;
60  __I uint32_t QSPI_WPSR;
61  __I uint32_t Reserved4[4];
62  __I uint32_t QSPI_VERSION;
63 } Qspi;
64 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
65 /* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */
66 #define QSPI_CR_QSPIEN (0x1u << 0)
67 #define QSPI_CR_QSPIDIS (0x1u << 1)
68 #define QSPI_CR_SWRST (0x1u << 7)
69 #define QSPI_CR_LASTXFER (0x1u << 24)
70 /* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */
71 #define QSPI_MR_SMM (0x1u << 0)
72 #define QSPI_MR_SMM_SPI (0x0u << 0)
73 #define QSPI_MR_SMM_MEMORY (0x1u << 0)
74 #define QSPI_MR_LLB (0x1u << 1)
75 #define QSPI_MR_LLB_DISABLED (0x0u << 1)
76 #define QSPI_MR_LLB_ENABLED (0x1u << 1)
77 #define QSPI_MR_WDRBT (0x1u << 2)
78 #define QSPI_MR_WDRBT_DISABLED (0x0u << 2)
79 #define QSPI_MR_WDRBT_ENABLED (0x1u << 2)
80 #define QSPI_MR_CSMODE_Pos 4
81 #define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos)
82 #define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos)))
83 #define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4)
84 #define QSPI_MR_CSMODE_LASTXFER (0x1u << 4)
85 #define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4)
86 #define QSPI_MR_NBBITS_Pos 8
87 #define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos)
88 #define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos)))
89 #define QSPI_MR_NBBITS_8_BIT (0x0u << 8)
90 #define QSPI_MR_NBBITS_16_BIT (0x8u << 8)
91 #define QSPI_MR_DLYBCT_Pos 16
92 #define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos)
93 #define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos)))
94 #define QSPI_MR_DLYCS_Pos 24
95 #define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos)
96 #define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos)))
97 /* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */
98 #define QSPI_RDR_RD_Pos 0
99 #define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos)
100 /* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */
101 #define QSPI_TDR_TD_Pos 0
102 #define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos)
103 #define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos)))
104 /* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */
105 #define QSPI_SR_RDRF (0x1u << 0)
106 #define QSPI_SR_TDRE (0x1u << 1)
107 #define QSPI_SR_TXEMPTY (0x1u << 2)
108 #define QSPI_SR_OVRES (0x1u << 3)
109 #define QSPI_SR_CSR (0x1u << 8)
110 #define QSPI_SR_CSS (0x1u << 9)
111 #define QSPI_SR_INSTRE (0x1u << 10)
112 #define QSPI_SR_QSPIENS (0x1u << 24)
113 /* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */
114 #define QSPI_IER_RDRF (0x1u << 0)
115 #define QSPI_IER_TDRE (0x1u << 1)
116 #define QSPI_IER_TXEMPTY (0x1u << 2)
117 #define QSPI_IER_OVRES (0x1u << 3)
118 #define QSPI_IER_CSR (0x1u << 8)
119 #define QSPI_IER_CSS (0x1u << 9)
120 #define QSPI_IER_INSTRE (0x1u << 10)
121 /* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */
122 #define QSPI_IDR_RDRF (0x1u << 0)
123 #define QSPI_IDR_TDRE (0x1u << 1)
124 #define QSPI_IDR_TXEMPTY (0x1u << 2)
125 #define QSPI_IDR_OVRES (0x1u << 3)
126 #define QSPI_IDR_CSR (0x1u << 8)
127 #define QSPI_IDR_CSS (0x1u << 9)
128 #define QSPI_IDR_INSTRE (0x1u << 10)
129 /* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */
130 #define QSPI_IMR_RDRF (0x1u << 0)
131 #define QSPI_IMR_TDRE (0x1u << 1)
132 #define QSPI_IMR_TXEMPTY (0x1u << 2)
133 #define QSPI_IMR_OVRES (0x1u << 3)
134 #define QSPI_IMR_CSR (0x1u << 8)
135 #define QSPI_IMR_CSS (0x1u << 9)
136 #define QSPI_IMR_INSTRE (0x1u << 10)
137 /* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */
138 #define QSPI_SCR_CPOL (0x1u << 0)
139 #define QSPI_SCR_CPHA (0x1u << 1)
140 #define QSPI_SCR_SCBR_Pos 8
141 #define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos)
142 #define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos)))
143 #define QSPI_SCR_DLYBS_Pos 16
144 #define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos)
145 #define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos)))
146 /* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */
147 #define QSPI_IAR_ADDR_Pos 0
148 #define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos)
149 #define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos)))
150 /* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */
151 #define QSPI_ICR_INST_Pos 0
152 #define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos)
153 #define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos)))
154 #define QSPI_ICR_OPT_Pos 16
155 #define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos)
156 #define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos)))
157 /* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */
158 #define QSPI_IFR_WIDTH_Pos 0
159 #define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos)
160 #define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos)))
161 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0)
162 #define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0)
163 #define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0)
164 #define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0)
165 #define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0)
166 #define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0)
167 #define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0)
168 #define QSPI_IFR_INSTEN (0x1u << 4)
169 #define QSPI_IFR_ADDREN (0x1u << 5)
170 #define QSPI_IFR_OPTEN (0x1u << 6)
171 #define QSPI_IFR_DATAEN (0x1u << 7)
172 #define QSPI_IFR_OPTL_Pos 8
173 #define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos)
174 #define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos)))
175 #define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8)
176 #define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8)
177 #define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8)
178 #define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8)
179 #define QSPI_IFR_ADDRL (0x1u << 10)
180 #define QSPI_IFR_ADDRL_24_BIT (0x0u << 10)
181 #define QSPI_IFR_ADDRL_32_BIT (0x1u << 10)
182 #define QSPI_IFR_TFRTYP_Pos 12
183 #define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos)
184 #define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos)))
185 #define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12)
186 #define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12)
187 #define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12)
188 #define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12)
189 #define QSPI_IFR_CRM (0x1u << 14)
190 #define QSPI_IFR_CRM_DISABLED (0x0u << 14)
191 #define QSPI_IFR_CRM_ENABLED (0x1u << 14)
192 #define QSPI_IFR_NBDUM_Pos 16
193 #define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos)
194 #define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos)))
195 /* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */
196 #define QSPI_SMR_SCREN (0x1u << 0)
197 #define QSPI_SMR_SCREN_DISABLED (0x0u << 0)
198 #define QSPI_SMR_SCREN_ENABLED (0x1u << 0)
199 #define QSPI_SMR_RVDIS (0x1u << 1)
200 /* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */
201 #define QSPI_SKR_USRK_Pos 0
202 #define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos)
203 #define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos)))
204 /* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */
205 #define QSPI_WPMR_WPEN (0x1u << 0)
206 #define QSPI_WPMR_WPKEY_Pos 8
207 #define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos)
208 #define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos)))
209 #define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8)
210 /* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */
211 #define QSPI_WPSR_WPVS (0x1u << 0)
212 #define QSPI_WPSR_WPVSRC_Pos 8
213 #define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos)
214 /* -------- QSPI_VERSION : (QSPI Offset: 0x00FC) Version Register -------- */
215 #define QSPI_VERSION_VERSION_Pos 0
216 #define QSPI_VERSION_VERSION_Msk (0xfffu << QSPI_VERSION_VERSION_Pos)
217 #define QSPI_VERSION_MFN_Pos 16
218 #define QSPI_VERSION_MFN_Msk (0x7u << QSPI_VERSION_MFN_Pos)
221 
222 
223 #endif /* _SAMV71_QSPI_COMPONENT_ */
Qspi::QSPI_VERSION
__I uint32_t QSPI_VERSION
(Qspi Offset: 0x00FC) Version Register
Definition: component_qspi.h:62
__IO
#define __IO
Definition: core_cm7.h:287
__O
#define __O
Definition: core_cm7.h:286
Qspi
Qspi hardware registers.
Definition: component_qspi.h:41
__I
#define __I
Definition: core_cm7.h:284
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