RTEMS  5.1
component_pwm.h
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2 /* Atmel Microcontroller Software Support */
3 /* SAM Software Package License */
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29 
30 #ifndef _SAMV71_PWM_COMPONENT_
31 #define _SAMV71_PWM_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  __IO uint32_t PWM_CMR;
43  __IO uint32_t PWM_CDTY;
44  __O uint32_t PWM_CDTYUPD;
45  __IO uint32_t PWM_CPRD;
46  __O uint32_t PWM_CPRDUPD;
47  __I uint32_t PWM_CCNT;
48  __IO uint32_t PWM_DT;
49  __O uint32_t PWM_DTUPD;
50 } PwmCh_num;
52 typedef struct {
53  __IO uint32_t PWM_CMPV;
54  __O uint32_t PWM_CMPVUPD;
55  __IO uint32_t PWM_CMPM;
56  __O uint32_t PWM_CMPMUPD;
57 } PwmCmp;
59 #define PWMCMP_NUMBER 8
60 #define PWMCH_NUM_NUMBER 4
61 typedef struct {
62  __IO uint32_t PWM_CLK;
63  __O uint32_t PWM_ENA;
64  __O uint32_t PWM_DIS;
65  __I uint32_t PWM_SR;
66  __O uint32_t PWM_IER1;
67  __O uint32_t PWM_IDR1;
68  __I uint32_t PWM_IMR1;
69  __I uint32_t PWM_ISR1;
70  __IO uint32_t PWM_SCM;
71  __O uint32_t PWM_DMAR;
72  __IO uint32_t PWM_SCUC;
73  __IO uint32_t PWM_SCUP;
74  __O uint32_t PWM_SCUPUPD;
75  __O uint32_t PWM_IER2;
76  __O uint32_t PWM_IDR2;
77  __I uint32_t PWM_IMR2;
78  __I uint32_t PWM_ISR2;
79  __IO uint32_t PWM_OOV;
80  __IO uint32_t PWM_OS;
81  __O uint32_t PWM_OSS;
82  __O uint32_t PWM_OSC;
83  __O uint32_t PWM_OSSUPD;
84  __O uint32_t PWM_OSCUPD;
85  __IO uint32_t PWM_FMR;
86  __I uint32_t PWM_FSR;
87  __O uint32_t PWM_FCR;
88  __IO uint32_t PWM_FPV1;
89  __IO uint32_t PWM_FPE;
90  __I uint32_t Reserved1[3];
91  __IO uint32_t PWM_ELMR[2];
92  __I uint32_t Reserved2[7];
93  __IO uint32_t PWM_SSPR;
94  __O uint32_t PWM_SSPUP;
95  __I uint32_t Reserved3[2];
96  __IO uint32_t PWM_SMMR;
97  __I uint32_t Reserved4[3];
98  __IO uint32_t PWM_FPV2;
99  __I uint32_t Reserved5[8];
100  __O uint32_t PWM_WPCR;
101  __I uint32_t PWM_WPSR;
102  __I uint32_t Reserved6[4];
103  __I uint32_t PWM_VERSION;
104  __I uint32_t Reserved7[12];
105  PwmCmp PWM_CMP[PWMCMP_NUMBER];
106  __I uint32_t Reserved8[20];
107  PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER];
108  __I uint32_t Reserved9[96];
109  __O uint32_t PWM_CMUPD0;
110  __I uint32_t Reserved10[7];
111  __O uint32_t PWM_CMUPD1;
112  __I uint32_t Reserved11[2];
113  __IO uint32_t PWM_ETRG1;
114  __IO uint32_t PWM_LEBR1;
115  __I uint32_t Reserved12[3];
116  __O uint32_t PWM_CMUPD2;
117  __I uint32_t Reserved13[2];
118  __IO uint32_t PWM_ETRG2;
119  __IO uint32_t PWM_LEBR2;
120  __I uint32_t Reserved14[3];
121  __O uint32_t PWM_CMUPD3;
122 } Pwm;
123 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
124 /* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
125 #define PWM_CLK_DIVA_Pos 0
126 #define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos)
127 #define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
128 #define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0)
129 #define PWM_CLK_DIVA_PREA (0x1u << 0)
130 #define PWM_CLK_PREA_Pos 8
131 #define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos)
132 #define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
133 #define PWM_CLK_PREA_CLK (0x0u << 8)
134 #define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8)
135 #define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8)
136 #define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8)
137 #define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8)
138 #define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8)
139 #define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8)
140 #define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8)
141 #define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8)
142 #define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8)
143 #define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8)
144 #define PWM_CLK_DIVB_Pos 16
145 #define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos)
146 #define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
147 #define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16)
148 #define PWM_CLK_DIVB_PREB (0x1u << 16)
149 #define PWM_CLK_PREB_Pos 24
150 #define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos)
151 #define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
152 #define PWM_CLK_PREB_CLK (0x0u << 24)
153 #define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24)
154 #define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24)
155 #define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24)
156 #define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24)
157 #define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24)
158 #define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24)
159 #define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24)
160 #define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24)
161 #define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24)
162 #define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24)
163 /* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
164 #define PWM_ENA_CHID0 (0x1u << 0)
165 #define PWM_ENA_CHID1 (0x1u << 1)
166 #define PWM_ENA_CHID2 (0x1u << 2)
167 #define PWM_ENA_CHID3 (0x1u << 3)
168 /* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
169 #define PWM_DIS_CHID0 (0x1u << 0)
170 #define PWM_DIS_CHID1 (0x1u << 1)
171 #define PWM_DIS_CHID2 (0x1u << 2)
172 #define PWM_DIS_CHID3 (0x1u << 3)
173 /* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
174 #define PWM_SR_CHID0 (0x1u << 0)
175 #define PWM_SR_CHID1 (0x1u << 1)
176 #define PWM_SR_CHID2 (0x1u << 2)
177 #define PWM_SR_CHID3 (0x1u << 3)
178 /* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
179 #define PWM_IER1_CHID0 (0x1u << 0)
180 #define PWM_IER1_CHID1 (0x1u << 1)
181 #define PWM_IER1_CHID2 (0x1u << 2)
182 #define PWM_IER1_CHID3 (0x1u << 3)
183 #define PWM_IER1_FCHID0 (0x1u << 16)
184 #define PWM_IER1_FCHID1 (0x1u << 17)
185 #define PWM_IER1_FCHID2 (0x1u << 18)
186 #define PWM_IER1_FCHID3 (0x1u << 19)
187 /* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
188 #define PWM_IDR1_CHID0 (0x1u << 0)
189 #define PWM_IDR1_CHID1 (0x1u << 1)
190 #define PWM_IDR1_CHID2 (0x1u << 2)
191 #define PWM_IDR1_CHID3 (0x1u << 3)
192 #define PWM_IDR1_FCHID0 (0x1u << 16)
193 #define PWM_IDR1_FCHID1 (0x1u << 17)
194 #define PWM_IDR1_FCHID2 (0x1u << 18)
195 #define PWM_IDR1_FCHID3 (0x1u << 19)
196 /* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
197 #define PWM_IMR1_CHID0 (0x1u << 0)
198 #define PWM_IMR1_CHID1 (0x1u << 1)
199 #define PWM_IMR1_CHID2 (0x1u << 2)
200 #define PWM_IMR1_CHID3 (0x1u << 3)
201 #define PWM_IMR1_FCHID0 (0x1u << 16)
202 #define PWM_IMR1_FCHID1 (0x1u << 17)
203 #define PWM_IMR1_FCHID2 (0x1u << 18)
204 #define PWM_IMR1_FCHID3 (0x1u << 19)
205 /* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
206 #define PWM_ISR1_CHID0 (0x1u << 0)
207 #define PWM_ISR1_CHID1 (0x1u << 1)
208 #define PWM_ISR1_CHID2 (0x1u << 2)
209 #define PWM_ISR1_CHID3 (0x1u << 3)
210 #define PWM_ISR1_FCHID0 (0x1u << 16)
211 #define PWM_ISR1_FCHID1 (0x1u << 17)
212 #define PWM_ISR1_FCHID2 (0x1u << 18)
213 #define PWM_ISR1_FCHID3 (0x1u << 19)
214 /* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
215 #define PWM_SCM_SYNC0 (0x1u << 0)
216 #define PWM_SCM_SYNC1 (0x1u << 1)
217 #define PWM_SCM_SYNC2 (0x1u << 2)
218 #define PWM_SCM_SYNC3 (0x1u << 3)
219 #define PWM_SCM_UPDM_Pos 16
220 #define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos)
221 #define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos)))
222 #define PWM_SCM_UPDM_MODE0 (0x0u << 16)
223 #define PWM_SCM_UPDM_MODE1 (0x1u << 16)
224 #define PWM_SCM_UPDM_MODE2 (0x2u << 16)
225 #define PWM_SCM_PTRM (0x1u << 20)
226 #define PWM_SCM_PTRCS_Pos 21
227 #define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos)
228 #define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
229 /* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */
230 #define PWM_DMAR_DMADUTY_Pos 0
231 #define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos)
232 #define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos)))
233 /* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
234 #define PWM_SCUC_UPDULOCK (0x1u << 0)
235 /* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
236 #define PWM_SCUP_UPR_Pos 0
237 #define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos)
238 #define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
239 #define PWM_SCUP_UPRCNT_Pos 4
240 #define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos)
241 #define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
242 /* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
243 #define PWM_SCUPUPD_UPRUPD_Pos 0
244 #define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos)
245 #define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
246 /* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
247 #define PWM_IER2_WRDY (0x1u << 0)
248 #define PWM_IER2_UNRE (0x1u << 3)
249 #define PWM_IER2_CMPM0 (0x1u << 8)
250 #define PWM_IER2_CMPM1 (0x1u << 9)
251 #define PWM_IER2_CMPM2 (0x1u << 10)
252 #define PWM_IER2_CMPM3 (0x1u << 11)
253 #define PWM_IER2_CMPM4 (0x1u << 12)
254 #define PWM_IER2_CMPM5 (0x1u << 13)
255 #define PWM_IER2_CMPM6 (0x1u << 14)
256 #define PWM_IER2_CMPM7 (0x1u << 15)
257 #define PWM_IER2_CMPU0 (0x1u << 16)
258 #define PWM_IER2_CMPU1 (0x1u << 17)
259 #define PWM_IER2_CMPU2 (0x1u << 18)
260 #define PWM_IER2_CMPU3 (0x1u << 19)
261 #define PWM_IER2_CMPU4 (0x1u << 20)
262 #define PWM_IER2_CMPU5 (0x1u << 21)
263 #define PWM_IER2_CMPU6 (0x1u << 22)
264 #define PWM_IER2_CMPU7 (0x1u << 23)
265 /* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
266 #define PWM_IDR2_WRDY (0x1u << 0)
267 #define PWM_IDR2_UNRE (0x1u << 3)
268 #define PWM_IDR2_CMPM0 (0x1u << 8)
269 #define PWM_IDR2_CMPM1 (0x1u << 9)
270 #define PWM_IDR2_CMPM2 (0x1u << 10)
271 #define PWM_IDR2_CMPM3 (0x1u << 11)
272 #define PWM_IDR2_CMPM4 (0x1u << 12)
273 #define PWM_IDR2_CMPM5 (0x1u << 13)
274 #define PWM_IDR2_CMPM6 (0x1u << 14)
275 #define PWM_IDR2_CMPM7 (0x1u << 15)
276 #define PWM_IDR2_CMPU0 (0x1u << 16)
277 #define PWM_IDR2_CMPU1 (0x1u << 17)
278 #define PWM_IDR2_CMPU2 (0x1u << 18)
279 #define PWM_IDR2_CMPU3 (0x1u << 19)
280 #define PWM_IDR2_CMPU4 (0x1u << 20)
281 #define PWM_IDR2_CMPU5 (0x1u << 21)
282 #define PWM_IDR2_CMPU6 (0x1u << 22)
283 #define PWM_IDR2_CMPU7 (0x1u << 23)
284 /* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
285 #define PWM_IMR2_WRDY (0x1u << 0)
286 #define PWM_IMR2_UNRE (0x1u << 3)
287 #define PWM_IMR2_CMPM0 (0x1u << 8)
288 #define PWM_IMR2_CMPM1 (0x1u << 9)
289 #define PWM_IMR2_CMPM2 (0x1u << 10)
290 #define PWM_IMR2_CMPM3 (0x1u << 11)
291 #define PWM_IMR2_CMPM4 (0x1u << 12)
292 #define PWM_IMR2_CMPM5 (0x1u << 13)
293 #define PWM_IMR2_CMPM6 (0x1u << 14)
294 #define PWM_IMR2_CMPM7 (0x1u << 15)
295 #define PWM_IMR2_CMPU0 (0x1u << 16)
296 #define PWM_IMR2_CMPU1 (0x1u << 17)
297 #define PWM_IMR2_CMPU2 (0x1u << 18)
298 #define PWM_IMR2_CMPU3 (0x1u << 19)
299 #define PWM_IMR2_CMPU4 (0x1u << 20)
300 #define PWM_IMR2_CMPU5 (0x1u << 21)
301 #define PWM_IMR2_CMPU6 (0x1u << 22)
302 #define PWM_IMR2_CMPU7 (0x1u << 23)
303 /* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
304 #define PWM_ISR2_WRDY (0x1u << 0)
305 #define PWM_ISR2_UNRE (0x1u << 3)
306 #define PWM_ISR2_CMPM0 (0x1u << 8)
307 #define PWM_ISR2_CMPM1 (0x1u << 9)
308 #define PWM_ISR2_CMPM2 (0x1u << 10)
309 #define PWM_ISR2_CMPM3 (0x1u << 11)
310 #define PWM_ISR2_CMPM4 (0x1u << 12)
311 #define PWM_ISR2_CMPM5 (0x1u << 13)
312 #define PWM_ISR2_CMPM6 (0x1u << 14)
313 #define PWM_ISR2_CMPM7 (0x1u << 15)
314 #define PWM_ISR2_CMPU0 (0x1u << 16)
315 #define PWM_ISR2_CMPU1 (0x1u << 17)
316 #define PWM_ISR2_CMPU2 (0x1u << 18)
317 #define PWM_ISR2_CMPU3 (0x1u << 19)
318 #define PWM_ISR2_CMPU4 (0x1u << 20)
319 #define PWM_ISR2_CMPU5 (0x1u << 21)
320 #define PWM_ISR2_CMPU6 (0x1u << 22)
321 #define PWM_ISR2_CMPU7 (0x1u << 23)
322 /* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
323 #define PWM_OOV_OOVH0 (0x1u << 0)
324 #define PWM_OOV_OOVH1 (0x1u << 1)
325 #define PWM_OOV_OOVH2 (0x1u << 2)
326 #define PWM_OOV_OOVH3 (0x1u << 3)
327 #define PWM_OOV_OOVL0 (0x1u << 16)
328 #define PWM_OOV_OOVL1 (0x1u << 17)
329 #define PWM_OOV_OOVL2 (0x1u << 18)
330 #define PWM_OOV_OOVL3 (0x1u << 19)
331 /* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
332 #define PWM_OS_OSH0 (0x1u << 0)
333 #define PWM_OS_OSH1 (0x1u << 1)
334 #define PWM_OS_OSH2 (0x1u << 2)
335 #define PWM_OS_OSH3 (0x1u << 3)
336 #define PWM_OS_OSL0 (0x1u << 16)
337 #define PWM_OS_OSL1 (0x1u << 17)
338 #define PWM_OS_OSL2 (0x1u << 18)
339 #define PWM_OS_OSL3 (0x1u << 19)
340 /* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
341 #define PWM_OSS_OSSH0 (0x1u << 0)
342 #define PWM_OSS_OSSH1 (0x1u << 1)
343 #define PWM_OSS_OSSH2 (0x1u << 2)
344 #define PWM_OSS_OSSH3 (0x1u << 3)
345 #define PWM_OSS_OSSL0 (0x1u << 16)
346 #define PWM_OSS_OSSL1 (0x1u << 17)
347 #define PWM_OSS_OSSL2 (0x1u << 18)
348 #define PWM_OSS_OSSL3 (0x1u << 19)
349 /* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
350 #define PWM_OSC_OSCH0 (0x1u << 0)
351 #define PWM_OSC_OSCH1 (0x1u << 1)
352 #define PWM_OSC_OSCH2 (0x1u << 2)
353 #define PWM_OSC_OSCH3 (0x1u << 3)
354 #define PWM_OSC_OSCL0 (0x1u << 16)
355 #define PWM_OSC_OSCL1 (0x1u << 17)
356 #define PWM_OSC_OSCL2 (0x1u << 18)
357 #define PWM_OSC_OSCL3 (0x1u << 19)
358 /* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
359 #define PWM_OSSUPD_OSSUPH0 (0x1u << 0)
360 #define PWM_OSSUPD_OSSUPH1 (0x1u << 1)
361 #define PWM_OSSUPD_OSSUPH2 (0x1u << 2)
362 #define PWM_OSSUPD_OSSUPH3 (0x1u << 3)
363 #define PWM_OSSUPD_OSSUPL0 (0x1u << 16)
364 #define PWM_OSSUPD_OSSUPL1 (0x1u << 17)
365 #define PWM_OSSUPD_OSSUPL2 (0x1u << 18)
366 #define PWM_OSSUPD_OSSUPL3 (0x1u << 19)
367 /* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
368 #define PWM_OSCUPD_OSCUPH0 (0x1u << 0)
369 #define PWM_OSCUPD_OSCUPH1 (0x1u << 1)
370 #define PWM_OSCUPD_OSCUPH2 (0x1u << 2)
371 #define PWM_OSCUPD_OSCUPH3 (0x1u << 3)
372 #define PWM_OSCUPD_OSCUPL0 (0x1u << 16)
373 #define PWM_OSCUPD_OSCUPL1 (0x1u << 17)
374 #define PWM_OSCUPD_OSCUPL2 (0x1u << 18)
375 #define PWM_OSCUPD_OSCUPL3 (0x1u << 19)
376 /* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
377 #define PWM_FMR_FPOL_Pos 0
378 #define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos)
379 #define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
380 #define PWM_FMR_FMOD_Pos 8
381 #define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos)
382 #define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
383 #define PWM_FMR_FFIL_Pos 16
384 #define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos)
385 #define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
386 /* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
387 #define PWM_FSR_FIV_Pos 0
388 #define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos)
389 #define PWM_FSR_FS_Pos 8
390 #define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos)
391 /* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
392 #define PWM_FCR_FCLR_Pos 0
393 #define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos)
394 #define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
395 /* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */
396 #define PWM_FPV1_FPVH0 (0x1u << 0)
397 #define PWM_FPV1_FPVH1 (0x1u << 1)
398 #define PWM_FPV1_FPVH2 (0x1u << 2)
399 #define PWM_FPV1_FPVH3 (0x1u << 3)
400 #define PWM_FPV1_FPVL0 (0x1u << 16)
401 #define PWM_FPV1_FPVL1 (0x1u << 17)
402 #define PWM_FPV1_FPVL2 (0x1u << 18)
403 #define PWM_FPV1_FPVL3 (0x1u << 19)
404 /* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
405 #define PWM_FPE_FPE0_Pos 0
406 #define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos)
407 #define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
408 #define PWM_FPE_FPE1_Pos 8
409 #define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos)
410 #define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
411 #define PWM_FPE_FPE2_Pos 16
412 #define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos)
413 #define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
414 #define PWM_FPE_FPE3_Pos 24
415 #define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos)
416 #define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
417 /* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
418 #define PWM_ELMR_CSEL0 (0x1u << 0)
419 #define PWM_ELMR_CSEL1 (0x1u << 1)
420 #define PWM_ELMR_CSEL2 (0x1u << 2)
421 #define PWM_ELMR_CSEL3 (0x1u << 3)
422 #define PWM_ELMR_CSEL4 (0x1u << 4)
423 #define PWM_ELMR_CSEL5 (0x1u << 5)
424 #define PWM_ELMR_CSEL6 (0x1u << 6)
425 #define PWM_ELMR_CSEL7 (0x1u << 7)
426 /* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */
427 #define PWM_SSPR_SPRD_Pos 0
428 #define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos)
429 #define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos)))
430 #define PWM_SSPR_SPRDM (0x1u << 24)
431 /* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */
432 #define PWM_SSPUP_SPRDUP_Pos 0
433 #define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos)
434 #define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos)))
435 /* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
436 #define PWM_SMMR_GCEN0 (0x1u << 0)
437 #define PWM_SMMR_GCEN1 (0x1u << 1)
438 #define PWM_SMMR_DOWN0 (0x1u << 16)
439 #define PWM_SMMR_DOWN1 (0x1u << 17)
440 /* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */
441 #define PWM_FPV2_FPZH0 (0x1u << 0)
442 #define PWM_FPV2_FPZH1 (0x1u << 1)
443 #define PWM_FPV2_FPZH2 (0x1u << 2)
444 #define PWM_FPV2_FPZH3 (0x1u << 3)
445 #define PWM_FPV2_FPZL0 (0x1u << 16)
446 #define PWM_FPV2_FPZL1 (0x1u << 17)
447 #define PWM_FPV2_FPZL2 (0x1u << 18)
448 #define PWM_FPV2_FPZL3 (0x1u << 19)
449 /* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */
450 #define PWM_WPCR_WPCMD_Pos 0
451 #define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos)
452 #define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
453 #define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0)
454 #define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0)
455 #define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0)
456 #define PWM_WPCR_WPRG0 (0x1u << 2)
457 #define PWM_WPCR_WPRG1 (0x1u << 3)
458 #define PWM_WPCR_WPRG2 (0x1u << 4)
459 #define PWM_WPCR_WPRG3 (0x1u << 5)
460 #define PWM_WPCR_WPRG4 (0x1u << 6)
461 #define PWM_WPCR_WPRG5 (0x1u << 7)
462 #define PWM_WPCR_WPKEY_Pos 8
463 #define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos)
464 #define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
465 #define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8)
466 /* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */
467 #define PWM_WPSR_WPSWS0 (0x1u << 0)
468 #define PWM_WPSR_WPSWS1 (0x1u << 1)
469 #define PWM_WPSR_WPSWS2 (0x1u << 2)
470 #define PWM_WPSR_WPSWS3 (0x1u << 3)
471 #define PWM_WPSR_WPSWS4 (0x1u << 4)
472 #define PWM_WPSR_WPSWS5 (0x1u << 5)
473 #define PWM_WPSR_WPVS (0x1u << 7)
474 #define PWM_WPSR_WPHWS0 (0x1u << 8)
475 #define PWM_WPSR_WPHWS1 (0x1u << 9)
476 #define PWM_WPSR_WPHWS2 (0x1u << 10)
477 #define PWM_WPSR_WPHWS3 (0x1u << 11)
478 #define PWM_WPSR_WPHWS4 (0x1u << 12)
479 #define PWM_WPSR_WPHWS5 (0x1u << 13)
480 #define PWM_WPSR_WPVSRC_Pos 16
481 #define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos)
482 /* -------- PWM_VERSION : (PWM Offset: 0xFC) Version Register -------- */
483 #define PWM_VERSION_VERSION_Pos 0
484 #define PWM_VERSION_VERSION_Msk (0xfffu << PWM_VERSION_VERSION_Pos)
485 #define PWM_VERSION_MFN_Pos 16
486 #define PWM_VERSION_MFN_Msk (0x7u << PWM_VERSION_MFN_Pos)
487 /* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
488 #define PWM_CMPV_CV_Pos 0
489 #define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos)
490 #define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
491 #define PWM_CMPV_CVM (0x1u << 24)
492 /* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
493 #define PWM_CMPVUPD_CVUPD_Pos 0
494 #define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos)
495 #define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
496 #define PWM_CMPVUPD_CVMUPD (0x1u << 24)
497 /* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
498 #define PWM_CMPM_CEN (0x1u << 0)
499 #define PWM_CMPM_CTR_Pos 4
500 #define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos)
501 #define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
502 #define PWM_CMPM_CPR_Pos 8
503 #define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos)
504 #define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
505 #define PWM_CMPM_CPRCNT_Pos 12
506 #define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos)
507 #define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
508 #define PWM_CMPM_CUPR_Pos 16
509 #define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos)
510 #define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
511 #define PWM_CMPM_CUPRCNT_Pos 20
512 #define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos)
513 #define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
514 /* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
515 #define PWM_CMPMUPD_CENUPD (0x1u << 0)
516 #define PWM_CMPMUPD_CTRUPD_Pos 4
517 #define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos)
518 #define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
519 #define PWM_CMPMUPD_CPRUPD_Pos 8
520 #define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos)
521 #define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
522 #define PWM_CMPMUPD_CUPRUPD_Pos 16
523 #define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos)
524 #define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
525 /* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
526 #define PWM_CMR_CPRE_Pos 0
527 #define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos)
528 #define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos)))
529 #define PWM_CMR_CPRE_MCK (0x0u << 0)
530 #define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0)
531 #define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0)
532 #define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0)
533 #define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0)
534 #define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0)
535 #define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0)
536 #define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0)
537 #define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0)
538 #define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0)
539 #define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0)
540 #define PWM_CMR_CPRE_CLKA (0xBu << 0)
541 #define PWM_CMR_CPRE_CLKB (0xCu << 0)
542 #define PWM_CMR_CALG (0x1u << 8)
543 #define PWM_CMR_CPOL (0x1u << 9)
544 #define PWM_CMR_CES (0x1u << 10)
545 #define PWM_CMR_UPDS (0x1u << 11)
546 #define PWM_CMR_DPOLI (0x1u << 12)
547 #define PWM_CMR_TCTS (0x1u << 13)
548 #define PWM_CMR_DTE (0x1u << 16)
549 #define PWM_CMR_DTHI (0x1u << 17)
550 #define PWM_CMR_DTLI (0x1u << 18)
551 #define PWM_CMR_PPM (0x1u << 19)
552 /* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
553 #define PWM_CDTY_CDTY_Pos 0
554 #define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos)
555 #define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
556 /* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
557 #define PWM_CDTYUPD_CDTYUPD_Pos 0
558 #define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos)
559 #define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
560 /* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
561 #define PWM_CPRD_CPRD_Pos 0
562 #define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos)
563 #define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
564 /* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
565 #define PWM_CPRDUPD_CPRDUPD_Pos 0
566 #define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos)
567 #define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
568 /* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
569 #define PWM_CCNT_CNT_Pos 0
570 #define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos)
571 /* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
572 #define PWM_DT_DTH_Pos 0
573 #define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos)
574 #define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
575 #define PWM_DT_DTL_Pos 16
576 #define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos)
577 #define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
578 /* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
579 #define PWM_DTUPD_DTHUPD_Pos 0
580 #define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos)
581 #define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
582 #define PWM_DTUPD_DTLUPD_Pos 16
583 #define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos)
584 #define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
585 /* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */
586 #define PWM_CMUPD0_CPOLUP (0x1u << 9)
587 #define PWM_CMUPD0_CPOLINVUP (0x1u << 13)
588 /* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */
589 #define PWM_CMUPD1_CPOLUP (0x1u << 9)
590 #define PWM_CMUPD1_CPOLINVUP (0x1u << 13)
591 /* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */
592 #define PWM_ETRG1_MAXCNT_Pos 0
593 #define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos)
594 #define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos)))
595 #define PWM_ETRG1_TRGMODE_Pos 24
596 #define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos)
597 #define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos)))
598 #define PWM_ETRG1_TRGMODE_OFF (0x0u << 24)
599 #define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24)
600 #define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24)
601 #define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24)
602 #define PWM_ETRG1_TRGEDGE (0x1u << 28)
603 #define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28)
604 #define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28)
605 #define PWM_ETRG1_TRGFILT (0x1u << 29)
606 #define PWM_ETRG1_TRGSRC (0x1u << 30)
607 #define PWM_ETRG1_RFEN (0x1u << 31)
608 /* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */
609 #define PWM_LEBR1_LEBDELAY_Pos 0
610 #define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos)
611 #define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos)))
612 #define PWM_LEBR1_PWMLFEN (0x1u << 16)
613 #define PWM_LEBR1_PWMLREN (0x1u << 17)
614 #define PWM_LEBR1_PWMHFEN (0x1u << 18)
615 #define PWM_LEBR1_PWMHREN (0x1u << 19)
616 /* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */
617 #define PWM_CMUPD2_CPOLUP (0x1u << 9)
618 #define PWM_CMUPD2_CPOLINVUP (0x1u << 13)
619 /* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */
620 #define PWM_ETRG2_MAXCNT_Pos 0
621 #define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos)
622 #define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos)))
623 #define PWM_ETRG2_TRGMODE_Pos 24
624 #define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos)
625 #define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos)))
626 #define PWM_ETRG2_TRGMODE_OFF (0x0u << 24)
627 #define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24)
628 #define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24)
629 #define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24)
630 #define PWM_ETRG2_TRGEDGE (0x1u << 28)
631 #define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28)
632 #define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28)
633 #define PWM_ETRG2_TRGFILT (0x1u << 29)
634 #define PWM_ETRG2_TRGSRC (0x1u << 30)
635 #define PWM_ETRG2_RFEN (0x1u << 31)
636 /* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */
637 #define PWM_LEBR2_LEBDELAY_Pos 0
638 #define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos)
639 #define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos)))
640 #define PWM_LEBR2_PWMLFEN (0x1u << 16)
641 #define PWM_LEBR2_PWMLREN (0x1u << 17)
642 #define PWM_LEBR2_PWMHFEN (0x1u << 18)
643 #define PWM_LEBR2_PWMHREN (0x1u << 19)
644 /* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */
645 #define PWM_CMUPD3_CPOLUP (0x1u << 9)
646 #define PWM_CMUPD3_CPOLINVUP (0x1u << 13)
649 
650 
651 #endif /* _SAMV71_PWM_COMPONENT_ */
Pwm
Definition: component_pwm.h:61
__IO
#define __IO
Definition: core_cm7.h:287
__O
#define __O
Definition: core_cm7.h:286
PWMCH_NUM_NUMBER
#define PWMCH_NUM_NUMBER
Pwm hardware registers.
Definition: component_pwm.h:52
Pwm::PWM_VERSION
__I uint32_t PWM_VERSION
(Pwm Offset: 0xFC) Version Register
Definition: component_pwm.h:103
PWMCMP_NUMBER
#define PWMCMP_NUMBER
Pwm hardware registers.
Definition: component_pwm.h:59
PwmCmp
PwmCmp hardware registers.
Definition: component_pwm.h:52
PwmCh_num
PwmCh_num hardware registers.
Definition: component_pwm.h:41
__I
#define __I
Definition: core_cm7.h:284
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