RTEMS  5.1
component_pmc.h
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2 /* Atmel Microcontroller Software Support */
3 /* SAM Software Package License */
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29 
30 #ifndef _SAMV71_PMC_COMPONENT_
31 #define _SAMV71_PMC_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  __O uint32_t PMC_SCER;
43  __O uint32_t PMC_SCDR;
44  __I uint32_t PMC_SCSR;
45  __I uint32_t Reserved1[1];
46  __O uint32_t PMC_PCER0;
47  __O uint32_t PMC_PCDR0;
48  __I uint32_t PMC_PCSR0;
49  __IO uint32_t CKGR_UCKR;
50  __IO uint32_t CKGR_MOR;
51  __IO uint32_t CKGR_MCFR;
52  __IO uint32_t CKGR_PLLAR;
53  __I uint32_t Reserved2[1];
54  __IO uint32_t PMC_MCKR;
55  __I uint32_t Reserved3[1];
56  __IO uint32_t PMC_USB;
57  __I uint32_t Reserved4[1];
58  __IO uint32_t PMC_PCK[7];
59  __I uint32_t Reserved5[1];
60  __O uint32_t PMC_IER;
61  __O uint32_t PMC_IDR;
62  __I uint32_t PMC_SR;
63  __I uint32_t PMC_IMR;
64  __IO uint32_t PMC_FSMR;
65  __IO uint32_t PMC_FSPR;
66  __O uint32_t PMC_FOCR;
67  __I uint32_t Reserved6[26];
68  __IO uint32_t PMC_WPMR;
69  __I uint32_t PMC_WPSR;
70  __I uint32_t Reserved7[4];
71  __I uint32_t PMC_VERSION;
72  __O uint32_t PMC_PCER1;
73  __O uint32_t PMC_PCDR1;
74  __I uint32_t PMC_PCSR1;
75  __IO uint32_t PMC_PCR;
76  __IO uint32_t PMC_OCR;
77  __O uint32_t PMC_SLPWK_ER0;
78  __O uint32_t PMC_SLPWK_DR0;
79  __I uint32_t PMC_SLPWK_SR0;
80  __I uint32_t PMC_SLPWK_ASR0;
81  __I uint32_t Reserved8[3];
82  __IO uint32_t PMC_PMMR;
83  __O uint32_t PMC_SLPWK_ER1;
84  __O uint32_t PMC_SLPWK_DR1;
85  __I uint32_t PMC_SLPWK_SR1;
86  __I uint32_t PMC_SLPWK_ASR1;
87  __I uint32_t PMC_SLPWK_AIPR;
88 } Pmc;
89 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
90 /* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
91 #define PMC_SCER_USBCLK (0x1u << 5)
92 #define PMC_SCER_PCK0 (0x1u << 8)
93 #define PMC_SCER_PCK1 (0x1u << 9)
94 #define PMC_SCER_PCK2 (0x1u << 10)
95 #define PMC_SCER_PCK3 (0x1u << 11)
96 #define PMC_SCER_PCK4 (0x1u << 12)
97 #define PMC_SCER_PCK5 (0x1u << 13)
98 #define PMC_SCER_PCK6 (0x1u << 14)
99 /* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
100 #define PMC_SCDR_USBCLK (0x1u << 5)
101 #define PMC_SCDR_PCK0 (0x1u << 8)
102 #define PMC_SCDR_PCK1 (0x1u << 9)
103 #define PMC_SCDR_PCK2 (0x1u << 10)
104 #define PMC_SCDR_PCK3 (0x1u << 11)
105 #define PMC_SCDR_PCK4 (0x1u << 12)
106 #define PMC_SCDR_PCK5 (0x1u << 13)
107 #define PMC_SCDR_PCK6 (0x1u << 14)
108 /* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
109 #define PMC_SCSR_USBCLK (0x1u << 5)
110 #define PMC_SCSR_PCK0 (0x1u << 8)
111 #define PMC_SCSR_PCK1 (0x1u << 9)
112 #define PMC_SCSR_PCK2 (0x1u << 10)
113 #define PMC_SCSR_PCK3 (0x1u << 11)
114 #define PMC_SCSR_PCK4 (0x1u << 12)
115 #define PMC_SCSR_PCK5 (0x1u << 13)
116 #define PMC_SCSR_PCK6 (0x1u << 14)
117 /* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
118 #define PMC_PCER0_PID7 (0x1u << 7)
119 #define PMC_PCER0_PID8 (0x1u << 8)
120 #define PMC_PCER0_PID9 (0x1u << 9)
121 #define PMC_PCER0_PID10 (0x1u << 10)
122 #define PMC_PCER0_PID11 (0x1u << 11)
123 #define PMC_PCER0_PID12 (0x1u << 12)
124 #define PMC_PCER0_PID13 (0x1u << 13)
125 #define PMC_PCER0_PID14 (0x1u << 14)
126 #define PMC_PCER0_PID15 (0x1u << 15)
127 #define PMC_PCER0_PID16 (0x1u << 16)
128 #define PMC_PCER0_PID17 (0x1u << 17)
129 #define PMC_PCER0_PID18 (0x1u << 18)
130 #define PMC_PCER0_PID19 (0x1u << 19)
131 #define PMC_PCER0_PID20 (0x1u << 20)
132 #define PMC_PCER0_PID21 (0x1u << 21)
133 #define PMC_PCER0_PID22 (0x1u << 22)
134 #define PMC_PCER0_PID23 (0x1u << 23)
135 #define PMC_PCER0_PID24 (0x1u << 24)
136 #define PMC_PCER0_PID25 (0x1u << 25)
137 #define PMC_PCER0_PID26 (0x1u << 26)
138 #define PMC_PCER0_PID27 (0x1u << 27)
139 #define PMC_PCER0_PID28 (0x1u << 28)
140 #define PMC_PCER0_PID29 (0x1u << 29)
141 #define PMC_PCER0_PID30 (0x1u << 30)
142 #define PMC_PCER0_PID31 (0x1u << 31)
143 /* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
144 #define PMC_PCDR0_PID7 (0x1u << 7)
145 #define PMC_PCDR0_PID8 (0x1u << 8)
146 #define PMC_PCDR0_PID9 (0x1u << 9)
147 #define PMC_PCDR0_PID10 (0x1u << 10)
148 #define PMC_PCDR0_PID11 (0x1u << 11)
149 #define PMC_PCDR0_PID12 (0x1u << 12)
150 #define PMC_PCDR0_PID13 (0x1u << 13)
151 #define PMC_PCDR0_PID14 (0x1u << 14)
152 #define PMC_PCDR0_PID15 (0x1u << 15)
153 #define PMC_PCDR0_PID16 (0x1u << 16)
154 #define PMC_PCDR0_PID17 (0x1u << 17)
155 #define PMC_PCDR0_PID18 (0x1u << 18)
156 #define PMC_PCDR0_PID19 (0x1u << 19)
157 #define PMC_PCDR0_PID20 (0x1u << 20)
158 #define PMC_PCDR0_PID21 (0x1u << 21)
159 #define PMC_PCDR0_PID22 (0x1u << 22)
160 #define PMC_PCDR0_PID23 (0x1u << 23)
161 #define PMC_PCDR0_PID24 (0x1u << 24)
162 #define PMC_PCDR0_PID25 (0x1u << 25)
163 #define PMC_PCDR0_PID26 (0x1u << 26)
164 #define PMC_PCDR0_PID27 (0x1u << 27)
165 #define PMC_PCDR0_PID28 (0x1u << 28)
166 #define PMC_PCDR0_PID29 (0x1u << 29)
167 #define PMC_PCDR0_PID30 (0x1u << 30)
168 #define PMC_PCDR0_PID31 (0x1u << 31)
169 /* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
170 #define PMC_PCSR0_PID7 (0x1u << 7)
171 #define PMC_PCSR0_PID8 (0x1u << 8)
172 #define PMC_PCSR0_PID9 (0x1u << 9)
173 #define PMC_PCSR0_PID10 (0x1u << 10)
174 #define PMC_PCSR0_PID11 (0x1u << 11)
175 #define PMC_PCSR0_PID12 (0x1u << 12)
176 #define PMC_PCSR0_PID13 (0x1u << 13)
177 #define PMC_PCSR0_PID14 (0x1u << 14)
178 #define PMC_PCSR0_PID15 (0x1u << 15)
179 #define PMC_PCSR0_PID16 (0x1u << 16)
180 #define PMC_PCSR0_PID17 (0x1u << 17)
181 #define PMC_PCSR0_PID18 (0x1u << 18)
182 #define PMC_PCSR0_PID19 (0x1u << 19)
183 #define PMC_PCSR0_PID20 (0x1u << 20)
184 #define PMC_PCSR0_PID21 (0x1u << 21)
185 #define PMC_PCSR0_PID22 (0x1u << 22)
186 #define PMC_PCSR0_PID23 (0x1u << 23)
187 #define PMC_PCSR0_PID24 (0x1u << 24)
188 #define PMC_PCSR0_PID25 (0x1u << 25)
189 #define PMC_PCSR0_PID26 (0x1u << 26)
190 #define PMC_PCSR0_PID27 (0x1u << 27)
191 #define PMC_PCSR0_PID28 (0x1u << 28)
192 #define PMC_PCSR0_PID29 (0x1u << 29)
193 #define PMC_PCSR0_PID30 (0x1u << 30)
194 #define PMC_PCSR0_PID31 (0x1u << 31)
195 /* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
196 #define CKGR_UCKR_UPLLEN (0x1u << 16)
197 #define CKGR_UCKR_UPLLCOUNT_Pos 20
198 #define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos)
199 #define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
200 /* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
201 #define CKGR_MOR_MOSCXTEN (0x1u << 0)
202 #define CKGR_MOR_MOSCXTBY (0x1u << 1)
203 #define CKGR_MOR_WAITMODE (0x1u << 2)
204 #define CKGR_MOR_MOSCRCEN (0x1u << 3)
205 #define CKGR_MOR_MOSCRCF_Pos 4
206 #define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos)
207 #define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos)))
208 #define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4)
209 #define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4)
210 #define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4)
211 #define CKGR_MOR_MOSCXTST_Pos 8
212 #define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos)
213 #define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
214 #define CKGR_MOR_KEY_Pos 16
215 #define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos)
216 #define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
217 #define CKGR_MOR_KEY_PASSWD (0x37u << 16)
218 #define CKGR_MOR_MOSCSEL (0x1u << 24)
219 #define CKGR_MOR_CFDEN (0x1u << 25)
220 #define CKGR_MOR_XT32KFME (0x1u << 26)
221 /* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
222 #define CKGR_MCFR_MAINF_Pos 0
223 #define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos)
224 #define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))
225 #define CKGR_MCFR_MAINFRDY (0x1u << 16)
226 #define CKGR_MCFR_RCMEAS (0x1u << 20)
227 #define CKGR_MCFR_CCSS (0x1u << 24)
228 /* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
229 #define CKGR_PLLAR_DIVA_Pos 0
230 #define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos)
231 #define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
232 #define CKGR_PLLAR_DIVA_0 (0x0u << 0)
233 #define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0)
234 #define CKGR_PLLAR_PLLACOUNT_Pos 8
235 #define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos)
236 #define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
237 #define CKGR_PLLAR_MULA_Pos 16
238 #define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos)
239 #define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
240 #define CKGR_PLLAR_ONE (0x1u << 29)
241 /* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
242 #define PMC_MCKR_CSS_Pos 0
243 #define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos)
244 #define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)))
245 #define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0)
246 #define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0)
247 #define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0)
248 #define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0)
249 #define PMC_MCKR_PRES_Pos 4
250 #define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos)
251 #define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)))
252 #define PMC_MCKR_PRES_CLK_1 (0x0u << 4)
253 #define PMC_MCKR_PRES_CLK_2 (0x1u << 4)
254 #define PMC_MCKR_PRES_CLK_4 (0x2u << 4)
255 #define PMC_MCKR_PRES_CLK_8 (0x3u << 4)
256 #define PMC_MCKR_PRES_CLK_16 (0x4u << 4)
257 #define PMC_MCKR_PRES_CLK_32 (0x5u << 4)
258 #define PMC_MCKR_PRES_CLK_64 (0x6u << 4)
259 #define PMC_MCKR_PRES_CLK_3 (0x7u << 4)
260 #define PMC_MCKR_MDIV_Pos 8
261 #define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos)
262 #define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos)))
263 #define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8)
264 #define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8)
265 #define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8)
266 #define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8)
267 #define PMC_MCKR_UPLLDIV2 (0x1u << 13)
268 /* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
269 #define PMC_USB_USBS (0x1u << 0)
270 #define PMC_USB_USBDIV_Pos 8
271 #define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos)
272 #define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
273 /* -------- PMC_PCK[7] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
274 #define PMC_PCK_CSS_Pos 0
275 #define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos)
276 #define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)))
277 #define PMC_PCK_CSS_SLOW_CLK (0x0u << 0)
278 #define PMC_PCK_CSS_MAIN_CLK (0x1u << 0)
279 #define PMC_PCK_CSS_PLLA_CLK (0x2u << 0)
280 #define PMC_PCK_CSS_UPLL_CLK (0x3u << 0)
281 #define PMC_PCK_CSS_MCK (0x4u << 0)
282 #define PMC_PCK_PRES_Pos 4
283 #define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos)
284 #define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))
285 /* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
286 #define PMC_IER_MOSCXTS (0x1u << 0)
287 #define PMC_IER_LOCKA (0x1u << 1)
288 #define PMC_IER_MCKRDY (0x1u << 3)
289 #define PMC_IER_LOCKU (0x1u << 6)
290 #define PMC_IER_PCKRDY0 (0x1u << 8)
291 #define PMC_IER_PCKRDY1 (0x1u << 9)
292 #define PMC_IER_PCKRDY2 (0x1u << 10)
293 #define PMC_IER_PCKRDY3 (0x1u << 11)
294 #define PMC_IER_PCKRDY4 (0x1u << 12)
295 #define PMC_IER_PCKRDY5 (0x1u << 13)
296 #define PMC_IER_PCKRDY6 (0x1u << 14)
297 #define PMC_IER_MOSCSELS (0x1u << 16)
298 #define PMC_IER_MOSCRCS (0x1u << 17)
299 #define PMC_IER_CFDEV (0x1u << 18)
300 #define PMC_IER_XT32KERR (0x1u << 21)
301 /* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
302 #define PMC_IDR_MOSCXTS (0x1u << 0)
303 #define PMC_IDR_LOCKA (0x1u << 1)
304 #define PMC_IDR_MCKRDY (0x1u << 3)
305 #define PMC_IDR_LOCKU (0x1u << 6)
306 #define PMC_IDR_PCKRDY0 (0x1u << 8)
307 #define PMC_IDR_PCKRDY1 (0x1u << 9)
308 #define PMC_IDR_PCKRDY2 (0x1u << 10)
309 #define PMC_IDR_PCKRDY3 (0x1u << 11)
310 #define PMC_IDR_PCKRDY4 (0x1u << 12)
311 #define PMC_IDR_PCKRDY5 (0x1u << 13)
312 #define PMC_IDR_PCKRDY6 (0x1u << 14)
313 #define PMC_IDR_MOSCSELS (0x1u << 16)
314 #define PMC_IDR_MOSCRCS (0x1u << 17)
315 #define PMC_IDR_CFDEV (0x1u << 18)
316 #define PMC_IDR_XT32KERR (0x1u << 21)
317 /* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
318 #define PMC_SR_MOSCXTS (0x1u << 0)
319 #define PMC_SR_LOCKA (0x1u << 1)
320 #define PMC_SR_MCKRDY (0x1u << 3)
321 #define PMC_SR_LOCKU (0x1u << 6)
322 #define PMC_SR_OSCSELS (0x1u << 7)
323 #define PMC_SR_PCKRDY0 (0x1u << 8)
324 #define PMC_SR_PCKRDY1 (0x1u << 9)
325 #define PMC_SR_PCKRDY2 (0x1u << 10)
326 #define PMC_SR_PCKRDY3 (0x1u << 11)
327 #define PMC_SR_PCKRDY4 (0x1u << 12)
328 #define PMC_SR_PCKRDY5 (0x1u << 13)
329 #define PMC_SR_PCKRDY6 (0x1u << 14)
330 #define PMC_SR_MOSCSELS (0x1u << 16)
331 #define PMC_SR_MOSCRCS (0x1u << 17)
332 #define PMC_SR_CFDEV (0x1u << 18)
333 #define PMC_SR_CFDS (0x1u << 19)
334 #define PMC_SR_FOS (0x1u << 20)
335 #define PMC_SR_XT32KERR (0x1u << 21)
336 /* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
337 #define PMC_IMR_MOSCXTS (0x1u << 0)
338 #define PMC_IMR_LOCKA (0x1u << 1)
339 #define PMC_IMR_MCKRDY (0x1u << 3)
340 #define PMC_IMR_LOCKU (0x1u << 6)
341 #define PMC_IMR_PCKRDY0 (0x1u << 8)
342 #define PMC_IMR_PCKRDY1 (0x1u << 9)
343 #define PMC_IMR_PCKRDY2 (0x1u << 10)
344 #define PMC_IMR_PCKRDY3 (0x1u << 11)
345 #define PMC_IMR_PCKRDY4 (0x1u << 12)
346 #define PMC_IMR_PCKRDY5 (0x1u << 13)
347 #define PMC_IMR_PCKRDY6 (0x1u << 14)
348 #define PMC_IMR_MOSCSELS (0x1u << 16)
349 #define PMC_IMR_MOSCRCS (0x1u << 17)
350 #define PMC_IMR_CFDEV (0x1u << 18)
351 #define PMC_IMR_XT32KERR (0x1u << 21)
352 /* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
353 #define PMC_FSMR_FSTT0 (0x1u << 0)
354 #define PMC_FSMR_FSTT1 (0x1u << 1)
355 #define PMC_FSMR_FSTT2 (0x1u << 2)
356 #define PMC_FSMR_FSTT3 (0x1u << 3)
357 #define PMC_FSMR_FSTT4 (0x1u << 4)
358 #define PMC_FSMR_FSTT5 (0x1u << 5)
359 #define PMC_FSMR_FSTT6 (0x1u << 6)
360 #define PMC_FSMR_FSTT7 (0x1u << 7)
361 #define PMC_FSMR_FSTT8 (0x1u << 8)
362 #define PMC_FSMR_FSTT9 (0x1u << 9)
363 #define PMC_FSMR_FSTT10 (0x1u << 10)
364 #define PMC_FSMR_FSTT11 (0x1u << 11)
365 #define PMC_FSMR_FSTT12 (0x1u << 12)
366 #define PMC_FSMR_FSTT13 (0x1u << 13)
367 #define PMC_FSMR_FSTT14 (0x1u << 14)
368 #define PMC_FSMR_FSTT15 (0x1u << 15)
369 #define PMC_FSMR_RTTAL (0x1u << 16)
370 #define PMC_FSMR_RTCAL (0x1u << 17)
371 #define PMC_FSMR_USBAL (0x1u << 18)
372 #define PMC_FSMR_LPM (0x1u << 20)
373 #define PMC_FSMR_FLPM_Pos 21
374 #define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos)
375 #define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos)))
376 #define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21)
377 #define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21)
378 #define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21)
379 #define PMC_FSMR_FFLPM (0x1u << 23)
380 /* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
381 #define PMC_FSPR_FSTP0 (0x1u << 0)
382 #define PMC_FSPR_FSTP1 (0x1u << 1)
383 #define PMC_FSPR_FSTP2 (0x1u << 2)
384 #define PMC_FSPR_FSTP3 (0x1u << 3)
385 #define PMC_FSPR_FSTP4 (0x1u << 4)
386 #define PMC_FSPR_FSTP5 (0x1u << 5)
387 #define PMC_FSPR_FSTP6 (0x1u << 6)
388 #define PMC_FSPR_FSTP7 (0x1u << 7)
389 #define PMC_FSPR_FSTP8 (0x1u << 8)
390 #define PMC_FSPR_FSTP9 (0x1u << 9)
391 #define PMC_FSPR_FSTP10 (0x1u << 10)
392 #define PMC_FSPR_FSTP11 (0x1u << 11)
393 #define PMC_FSPR_FSTP12 (0x1u << 12)
394 #define PMC_FSPR_FSTP13 (0x1u << 13)
395 #define PMC_FSPR_FSTP14 (0x1u << 14)
396 #define PMC_FSPR_FSTP15 (0x1u << 15)
397 /* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
398 #define PMC_FOCR_FOCLR (0x1u << 0)
399 /* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */
400 #define PMC_WPMR_WPEN (0x1u << 0)
401 #define PMC_WPMR_WPKEY_Pos 8
402 #define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos)
403 #define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
404 #define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8)
405 /* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */
406 #define PMC_WPSR_WPVS (0x1u << 0)
407 #define PMC_WPSR_WPVSRC_Pos 8
408 #define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos)
409 /* -------- PMC_VERSION : (PMC Offset: 0x00FC) Version Register -------- */
410 #define PMC_VERSION_VERSION_Pos 0
411 #define PMC_VERSION_VERSION_Msk (0xfffu << PMC_VERSION_VERSION_Pos)
412 #define PMC_VERSION_MFN_Pos 16
413 #define PMC_VERSION_MFN_Msk (0x7u << PMC_VERSION_MFN_Pos)
414 /* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
415 #define PMC_PCER1_PID32 (0x1u << 0)
416 #define PMC_PCER1_PID33 (0x1u << 1)
417 #define PMC_PCER1_PID34 (0x1u << 2)
418 #define PMC_PCER1_PID35 (0x1u << 3)
419 #define PMC_PCER1_PID37 (0x1u << 5)
420 #define PMC_PCER1_PID39 (0x1u << 7)
421 #define PMC_PCER1_PID40 (0x1u << 8)
422 #define PMC_PCER1_PID41 (0x1u << 9)
423 #define PMC_PCER1_PID42 (0x1u << 10)
424 #define PMC_PCER1_PID43 (0x1u << 11)
425 #define PMC_PCER1_PID44 (0x1u << 12)
426 #define PMC_PCER1_PID45 (0x1u << 13)
427 #define PMC_PCER1_PID46 (0x1u << 14)
428 #define PMC_PCER1_PID47 (0x1u << 15)
429 #define PMC_PCER1_PID48 (0x1u << 16)
430 #define PMC_PCER1_PID49 (0x1u << 17)
431 #define PMC_PCER1_PID50 (0x1u << 18)
432 #define PMC_PCER1_PID51 (0x1u << 19)
433 #define PMC_PCER1_PID52 (0x1u << 20)
434 #define PMC_PCER1_PID53 (0x1u << 21)
435 #define PMC_PCER1_PID56 (0x1u << 24)
436 #define PMC_PCER1_PID57 (0x1u << 25)
437 #define PMC_PCER1_PID58 (0x1u << 26)
438 #define PMC_PCER1_PID59 (0x1u << 27)
439 #define PMC_PCER1_PID60 (0x1u << 28)
440 /* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
441 #define PMC_PCDR1_PID32 (0x1u << 0)
442 #define PMC_PCDR1_PID33 (0x1u << 1)
443 #define PMC_PCDR1_PID34 (0x1u << 2)
444 #define PMC_PCDR1_PID35 (0x1u << 3)
445 #define PMC_PCDR1_PID37 (0x1u << 5)
446 #define PMC_PCDR1_PID39 (0x1u << 7)
447 #define PMC_PCDR1_PID40 (0x1u << 8)
448 #define PMC_PCDR1_PID41 (0x1u << 9)
449 #define PMC_PCDR1_PID42 (0x1u << 10)
450 #define PMC_PCDR1_PID43 (0x1u << 11)
451 #define PMC_PCDR1_PID44 (0x1u << 12)
452 #define PMC_PCDR1_PID45 (0x1u << 13)
453 #define PMC_PCDR1_PID46 (0x1u << 14)
454 #define PMC_PCDR1_PID47 (0x1u << 15)
455 #define PMC_PCDR1_PID48 (0x1u << 16)
456 #define PMC_PCDR1_PID49 (0x1u << 17)
457 #define PMC_PCDR1_PID50 (0x1u << 18)
458 #define PMC_PCDR1_PID51 (0x1u << 19)
459 #define PMC_PCDR1_PID52 (0x1u << 20)
460 #define PMC_PCDR1_PID53 (0x1u << 21)
461 #define PMC_PCDR1_PID56 (0x1u << 24)
462 #define PMC_PCDR1_PID57 (0x1u << 25)
463 #define PMC_PCDR1_PID58 (0x1u << 26)
464 #define PMC_PCDR1_PID59 (0x1u << 27)
465 #define PMC_PCDR1_PID60 (0x1u << 28)
466 /* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
467 #define PMC_PCSR1_PID32 (0x1u << 0)
468 #define PMC_PCSR1_PID33 (0x1u << 1)
469 #define PMC_PCSR1_PID34 (0x1u << 2)
470 #define PMC_PCSR1_PID35 (0x1u << 3)
471 #define PMC_PCSR1_PID37 (0x1u << 5)
472 #define PMC_PCSR1_PID39 (0x1u << 7)
473 #define PMC_PCSR1_PID40 (0x1u << 8)
474 #define PMC_PCSR1_PID41 (0x1u << 9)
475 #define PMC_PCSR1_PID42 (0x1u << 10)
476 #define PMC_PCSR1_PID43 (0x1u << 11)
477 #define PMC_PCSR1_PID44 (0x1u << 12)
478 #define PMC_PCSR1_PID45 (0x1u << 13)
479 #define PMC_PCSR1_PID46 (0x1u << 14)
480 #define PMC_PCSR1_PID47 (0x1u << 15)
481 #define PMC_PCSR1_PID48 (0x1u << 16)
482 #define PMC_PCSR1_PID49 (0x1u << 17)
483 #define PMC_PCSR1_PID50 (0x1u << 18)
484 #define PMC_PCSR1_PID51 (0x1u << 19)
485 #define PMC_PCSR1_PID52 (0x1u << 20)
486 #define PMC_PCSR1_PID53 (0x1u << 21)
487 #define PMC_PCSR1_PID56 (0x1u << 24)
488 #define PMC_PCSR1_PID57 (0x1u << 25)
489 #define PMC_PCSR1_PID58 (0x1u << 26)
490 #define PMC_PCSR1_PID59 (0x1u << 27)
491 #define PMC_PCSR1_PID60 (0x1u << 28)
492 /* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */
493 #define PMC_PCR_PID_Pos 0
494 #define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos)
495 #define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))
496 #define PMC_PCR_CMD (0x1u << 12)
497 #define PMC_PCR_EN (0x1u << 28)
498 /* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
499 #define PMC_OCR_CAL4_Pos 0
500 #define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos)
501 #define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))
502 #define PMC_OCR_SEL4 (0x1u << 7)
503 #define PMC_OCR_CAL8_Pos 8
504 #define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos)
505 #define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
506 #define PMC_OCR_SEL8 (0x1u << 15)
507 #define PMC_OCR_CAL12_Pos 16
508 #define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos)
509 #define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))
510 #define PMC_OCR_SEL12 (0x1u << 23)
511 /* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */
512 #define PMC_SLPWK_ER0_PID7 (0x1u << 7)
513 #define PMC_SLPWK_ER0_PID8 (0x1u << 8)
514 #define PMC_SLPWK_ER0_PID9 (0x1u << 9)
515 #define PMC_SLPWK_ER0_PID10 (0x1u << 10)
516 #define PMC_SLPWK_ER0_PID11 (0x1u << 11)
517 #define PMC_SLPWK_ER0_PID12 (0x1u << 12)
518 #define PMC_SLPWK_ER0_PID13 (0x1u << 13)
519 #define PMC_SLPWK_ER0_PID14 (0x1u << 14)
520 #define PMC_SLPWK_ER0_PID15 (0x1u << 15)
521 #define PMC_SLPWK_ER0_PID16 (0x1u << 16)
522 #define PMC_SLPWK_ER0_PID17 (0x1u << 17)
523 #define PMC_SLPWK_ER0_PID18 (0x1u << 18)
524 #define PMC_SLPWK_ER0_PID19 (0x1u << 19)
525 #define PMC_SLPWK_ER0_PID20 (0x1u << 20)
526 #define PMC_SLPWK_ER0_PID21 (0x1u << 21)
527 #define PMC_SLPWK_ER0_PID22 (0x1u << 22)
528 #define PMC_SLPWK_ER0_PID23 (0x1u << 23)
529 #define PMC_SLPWK_ER0_PID24 (0x1u << 24)
530 #define PMC_SLPWK_ER0_PID25 (0x1u << 25)
531 #define PMC_SLPWK_ER0_PID26 (0x1u << 26)
532 #define PMC_SLPWK_ER0_PID27 (0x1u << 27)
533 #define PMC_SLPWK_ER0_PID28 (0x1u << 28)
534 #define PMC_SLPWK_ER0_PID29 (0x1u << 29)
535 #define PMC_SLPWK_ER0_PID30 (0x1u << 30)
536 #define PMC_SLPWK_ER0_PID31 (0x1u << 31)
537 /* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */
538 #define PMC_SLPWK_DR0_PID7 (0x1u << 7)
539 #define PMC_SLPWK_DR0_PID8 (0x1u << 8)
540 #define PMC_SLPWK_DR0_PID9 (0x1u << 9)
541 #define PMC_SLPWK_DR0_PID10 (0x1u << 10)
542 #define PMC_SLPWK_DR0_PID11 (0x1u << 11)
543 #define PMC_SLPWK_DR0_PID12 (0x1u << 12)
544 #define PMC_SLPWK_DR0_PID13 (0x1u << 13)
545 #define PMC_SLPWK_DR0_PID14 (0x1u << 14)
546 #define PMC_SLPWK_DR0_PID15 (0x1u << 15)
547 #define PMC_SLPWK_DR0_PID16 (0x1u << 16)
548 #define PMC_SLPWK_DR0_PID17 (0x1u << 17)
549 #define PMC_SLPWK_DR0_PID18 (0x1u << 18)
550 #define PMC_SLPWK_DR0_PID19 (0x1u << 19)
551 #define PMC_SLPWK_DR0_PID20 (0x1u << 20)
552 #define PMC_SLPWK_DR0_PID21 (0x1u << 21)
553 #define PMC_SLPWK_DR0_PID22 (0x1u << 22)
554 #define PMC_SLPWK_DR0_PID23 (0x1u << 23)
555 #define PMC_SLPWK_DR0_PID24 (0x1u << 24)
556 #define PMC_SLPWK_DR0_PID25 (0x1u << 25)
557 #define PMC_SLPWK_DR0_PID26 (0x1u << 26)
558 #define PMC_SLPWK_DR0_PID27 (0x1u << 27)
559 #define PMC_SLPWK_DR0_PID28 (0x1u << 28)
560 #define PMC_SLPWK_DR0_PID29 (0x1u << 29)
561 #define PMC_SLPWK_DR0_PID30 (0x1u << 30)
562 #define PMC_SLPWK_DR0_PID31 (0x1u << 31)
563 /* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */
564 #define PMC_SLPWK_SR0_PID7 (0x1u << 7)
565 #define PMC_SLPWK_SR0_PID8 (0x1u << 8)
566 #define PMC_SLPWK_SR0_PID9 (0x1u << 9)
567 #define PMC_SLPWK_SR0_PID10 (0x1u << 10)
568 #define PMC_SLPWK_SR0_PID11 (0x1u << 11)
569 #define PMC_SLPWK_SR0_PID12 (0x1u << 12)
570 #define PMC_SLPWK_SR0_PID13 (0x1u << 13)
571 #define PMC_SLPWK_SR0_PID14 (0x1u << 14)
572 #define PMC_SLPWK_SR0_PID15 (0x1u << 15)
573 #define PMC_SLPWK_SR0_PID16 (0x1u << 16)
574 #define PMC_SLPWK_SR0_PID17 (0x1u << 17)
575 #define PMC_SLPWK_SR0_PID18 (0x1u << 18)
576 #define PMC_SLPWK_SR0_PID19 (0x1u << 19)
577 #define PMC_SLPWK_SR0_PID20 (0x1u << 20)
578 #define PMC_SLPWK_SR0_PID21 (0x1u << 21)
579 #define PMC_SLPWK_SR0_PID22 (0x1u << 22)
580 #define PMC_SLPWK_SR0_PID23 (0x1u << 23)
581 #define PMC_SLPWK_SR0_PID24 (0x1u << 24)
582 #define PMC_SLPWK_SR0_PID25 (0x1u << 25)
583 #define PMC_SLPWK_SR0_PID26 (0x1u << 26)
584 #define PMC_SLPWK_SR0_PID27 (0x1u << 27)
585 #define PMC_SLPWK_SR0_PID28 (0x1u << 28)
586 #define PMC_SLPWK_SR0_PID29 (0x1u << 29)
587 #define PMC_SLPWK_SR0_PID30 (0x1u << 30)
588 #define PMC_SLPWK_SR0_PID31 (0x1u << 31)
589 /* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */
590 #define PMC_SLPWK_ASR0_PID7 (0x1u << 7)
591 #define PMC_SLPWK_ASR0_PID8 (0x1u << 8)
592 #define PMC_SLPWK_ASR0_PID9 (0x1u << 9)
593 #define PMC_SLPWK_ASR0_PID10 (0x1u << 10)
594 #define PMC_SLPWK_ASR0_PID11 (0x1u << 11)
595 #define PMC_SLPWK_ASR0_PID12 (0x1u << 12)
596 #define PMC_SLPWK_ASR0_PID13 (0x1u << 13)
597 #define PMC_SLPWK_ASR0_PID14 (0x1u << 14)
598 #define PMC_SLPWK_ASR0_PID15 (0x1u << 15)
599 #define PMC_SLPWK_ASR0_PID16 (0x1u << 16)
600 #define PMC_SLPWK_ASR0_PID17 (0x1u << 17)
601 #define PMC_SLPWK_ASR0_PID18 (0x1u << 18)
602 #define PMC_SLPWK_ASR0_PID19 (0x1u << 19)
603 #define PMC_SLPWK_ASR0_PID20 (0x1u << 20)
604 #define PMC_SLPWK_ASR0_PID21 (0x1u << 21)
605 #define PMC_SLPWK_ASR0_PID22 (0x1u << 22)
606 #define PMC_SLPWK_ASR0_PID23 (0x1u << 23)
607 #define PMC_SLPWK_ASR0_PID24 (0x1u << 24)
608 #define PMC_SLPWK_ASR0_PID25 (0x1u << 25)
609 #define PMC_SLPWK_ASR0_PID26 (0x1u << 26)
610 #define PMC_SLPWK_ASR0_PID27 (0x1u << 27)
611 #define PMC_SLPWK_ASR0_PID28 (0x1u << 28)
612 #define PMC_SLPWK_ASR0_PID29 (0x1u << 29)
613 #define PMC_SLPWK_ASR0_PID30 (0x1u << 30)
614 #define PMC_SLPWK_ASR0_PID31 (0x1u << 31)
615 /* -------- PMC_PMMR : (PMC Offset: 0x0130) PLL Maximum Multiplier Value Register -------- */
616 #define PMC_PMMR_PLLA_MMAX_Pos 0
617 #define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos)
618 #define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos)))
619 /* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */
620 #define PMC_SLPWK_ER1_PID32 (0x1u << 0)
621 #define PMC_SLPWK_ER1_PID33 (0x1u << 1)
622 #define PMC_SLPWK_ER1_PID34 (0x1u << 2)
623 #define PMC_SLPWK_ER1_PID35 (0x1u << 3)
624 #define PMC_SLPWK_ER1_PID37 (0x1u << 5)
625 #define PMC_SLPWK_ER1_PID39 (0x1u << 7)
626 #define PMC_SLPWK_ER1_PID40 (0x1u << 8)
627 #define PMC_SLPWK_ER1_PID41 (0x1u << 9)
628 #define PMC_SLPWK_ER1_PID42 (0x1u << 10)
629 #define PMC_SLPWK_ER1_PID43 (0x1u << 11)
630 #define PMC_SLPWK_ER1_PID44 (0x1u << 12)
631 #define PMC_SLPWK_ER1_PID45 (0x1u << 13)
632 #define PMC_SLPWK_ER1_PID46 (0x1u << 14)
633 #define PMC_SLPWK_ER1_PID47 (0x1u << 15)
634 #define PMC_SLPWK_ER1_PID48 (0x1u << 16)
635 #define PMC_SLPWK_ER1_PID49 (0x1u << 17)
636 #define PMC_SLPWK_ER1_PID50 (0x1u << 18)
637 #define PMC_SLPWK_ER1_PID51 (0x1u << 19)
638 #define PMC_SLPWK_ER1_PID52 (0x1u << 20)
639 #define PMC_SLPWK_ER1_PID53 (0x1u << 21)
640 #define PMC_SLPWK_ER1_PID56 (0x1u << 24)
641 #define PMC_SLPWK_ER1_PID57 (0x1u << 25)
642 #define PMC_SLPWK_ER1_PID58 (0x1u << 26)
643 #define PMC_SLPWK_ER1_PID59 (0x1u << 27)
644 #define PMC_SLPWK_ER1_PID60 (0x1u << 28)
645 /* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */
646 #define PMC_SLPWK_DR1_PID32 (0x1u << 0)
647 #define PMC_SLPWK_DR1_PID33 (0x1u << 1)
648 #define PMC_SLPWK_DR1_PID34 (0x1u << 2)
649 #define PMC_SLPWK_DR1_PID35 (0x1u << 3)
650 #define PMC_SLPWK_DR1_PID37 (0x1u << 5)
651 #define PMC_SLPWK_DR1_PID39 (0x1u << 7)
652 #define PMC_SLPWK_DR1_PID40 (0x1u << 8)
653 #define PMC_SLPWK_DR1_PID41 (0x1u << 9)
654 #define PMC_SLPWK_DR1_PID42 (0x1u << 10)
655 #define PMC_SLPWK_DR1_PID43 (0x1u << 11)
656 #define PMC_SLPWK_DR1_PID44 (0x1u << 12)
657 #define PMC_SLPWK_DR1_PID45 (0x1u << 13)
658 #define PMC_SLPWK_DR1_PID46 (0x1u << 14)
659 #define PMC_SLPWK_DR1_PID47 (0x1u << 15)
660 #define PMC_SLPWK_DR1_PID48 (0x1u << 16)
661 #define PMC_SLPWK_DR1_PID49 (0x1u << 17)
662 #define PMC_SLPWK_DR1_PID50 (0x1u << 18)
663 #define PMC_SLPWK_DR1_PID51 (0x1u << 19)
664 #define PMC_SLPWK_DR1_PID52 (0x1u << 20)
665 #define PMC_SLPWK_DR1_PID53 (0x1u << 21)
666 #define PMC_SLPWK_DR1_PID56 (0x1u << 24)
667 #define PMC_SLPWK_DR1_PID57 (0x1u << 25)
668 #define PMC_SLPWK_DR1_PID58 (0x1u << 26)
669 #define PMC_SLPWK_DR1_PID59 (0x1u << 27)
670 #define PMC_SLPWK_DR1_PID60 (0x1u << 28)
671 /* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */
672 #define PMC_SLPWK_SR1_PID32 (0x1u << 0)
673 #define PMC_SLPWK_SR1_PID33 (0x1u << 1)
674 #define PMC_SLPWK_SR1_PID34 (0x1u << 2)
675 #define PMC_SLPWK_SR1_PID35 (0x1u << 3)
676 #define PMC_SLPWK_SR1_PID37 (0x1u << 5)
677 #define PMC_SLPWK_SR1_PID39 (0x1u << 7)
678 #define PMC_SLPWK_SR1_PID40 (0x1u << 8)
679 #define PMC_SLPWK_SR1_PID41 (0x1u << 9)
680 #define PMC_SLPWK_SR1_PID42 (0x1u << 10)
681 #define PMC_SLPWK_SR1_PID43 (0x1u << 11)
682 #define PMC_SLPWK_SR1_PID44 (0x1u << 12)
683 #define PMC_SLPWK_SR1_PID45 (0x1u << 13)
684 #define PMC_SLPWK_SR1_PID46 (0x1u << 14)
685 #define PMC_SLPWK_SR1_PID47 (0x1u << 15)
686 #define PMC_SLPWK_SR1_PID48 (0x1u << 16)
687 #define PMC_SLPWK_SR1_PID49 (0x1u << 17)
688 #define PMC_SLPWK_SR1_PID50 (0x1u << 18)
689 #define PMC_SLPWK_SR1_PID51 (0x1u << 19)
690 #define PMC_SLPWK_SR1_PID52 (0x1u << 20)
691 #define PMC_SLPWK_SR1_PID53 (0x1u << 21)
692 #define PMC_SLPWK_SR1_PID56 (0x1u << 24)
693 #define PMC_SLPWK_SR1_PID57 (0x1u << 25)
694 #define PMC_SLPWK_SR1_PID58 (0x1u << 26)
695 #define PMC_SLPWK_SR1_PID59 (0x1u << 27)
696 #define PMC_SLPWK_SR1_PID60 (0x1u << 28)
697 /* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */
698 #define PMC_SLPWK_ASR1_PID32 (0x1u << 0)
699 #define PMC_SLPWK_ASR1_PID33 (0x1u << 1)
700 #define PMC_SLPWK_ASR1_PID34 (0x1u << 2)
701 #define PMC_SLPWK_ASR1_PID35 (0x1u << 3)
702 #define PMC_SLPWK_ASR1_PID37 (0x1u << 5)
703 #define PMC_SLPWK_ASR1_PID39 (0x1u << 7)
704 #define PMC_SLPWK_ASR1_PID40 (0x1u << 8)
705 #define PMC_SLPWK_ASR1_PID41 (0x1u << 9)
706 #define PMC_SLPWK_ASR1_PID42 (0x1u << 10)
707 #define PMC_SLPWK_ASR1_PID43 (0x1u << 11)
708 #define PMC_SLPWK_ASR1_PID44 (0x1u << 12)
709 #define PMC_SLPWK_ASR1_PID45 (0x1u << 13)
710 #define PMC_SLPWK_ASR1_PID46 (0x1u << 14)
711 #define PMC_SLPWK_ASR1_PID47 (0x1u << 15)
712 #define PMC_SLPWK_ASR1_PID48 (0x1u << 16)
713 #define PMC_SLPWK_ASR1_PID49 (0x1u << 17)
714 #define PMC_SLPWK_ASR1_PID50 (0x1u << 18)
715 #define PMC_SLPWK_ASR1_PID51 (0x1u << 19)
716 #define PMC_SLPWK_ASR1_PID52 (0x1u << 20)
717 #define PMC_SLPWK_ASR1_PID53 (0x1u << 21)
718 #define PMC_SLPWK_ASR1_PID56 (0x1u << 24)
719 #define PMC_SLPWK_ASR1_PID57 (0x1u << 25)
720 #define PMC_SLPWK_ASR1_PID58 (0x1u << 26)
721 #define PMC_SLPWK_ASR1_PID59 (0x1u << 27)
722 #define PMC_SLPWK_ASR1_PID60 (0x1u << 28)
723 /* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */
724 #define PMC_SLPWK_AIPR_AIP (0x1u << 0)
727 
728 
729 #endif /* _SAMV71_PMC_COMPONENT_ */
__IO
#define __IO
Definition: core_cm7.h:287
__O
#define __O
Definition: core_cm7.h:286
Pmc::PMC_VERSION
__I uint32_t PMC_VERSION
(Pmc Offset: 0x00FC) Version Register
Definition: component_pmc.h:71
Pmc
Pmc hardware registers.
Definition: component_pmc.h:41
__I
#define __I
Definition: core_cm7.h:284
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