RTEMS  5.1
component_mcan.h
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2 /* Atmel Microcontroller Software Support */
3 /* SAM Software Package License */
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29 
30 #ifndef _SAMV71_MCAN_COMPONENT_
31 #define _SAMV71_MCAN_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  __I uint32_t MCAN_CREL;
43  __I uint32_t MCAN_ENDN;
44  __IO uint32_t MCAN_CUST;
45  __IO uint32_t MCAN_FBTP;
46  __IO uint32_t MCAN_TEST;
47  __IO uint32_t MCAN_RWD;
48  __IO uint32_t MCAN_CCCR;
49  __IO uint32_t MCAN_BTP;
50  __IO uint32_t MCAN_TSCC;
51  __IO uint32_t MCAN_TSCV;
52  __IO uint32_t MCAN_TOCC;
53  __IO uint32_t MCAN_TOCV;
54  __I uint32_t Reserved1[4];
55  __I uint32_t MCAN_ECR;
56  __I uint32_t MCAN_PSR;
57  __I uint32_t Reserved2[2];
58  __IO uint32_t MCAN_IR;
59  __IO uint32_t MCAN_IE;
60  __IO uint32_t MCAN_ILS;
61  __IO uint32_t MCAN_ILE;
62  __I uint32_t Reserved3[8];
63  __IO uint32_t MCAN_GFC;
64  __IO uint32_t MCAN_SIDFC;
65  __IO uint32_t MCAN_XIDFC;
66  __I uint32_t Reserved4[1];
67  __IO uint32_t MCAN_XIDAM;
68  __I uint32_t MCAN_HPMS;
69  __IO uint32_t MCAN_NDAT1;
70  __IO uint32_t MCAN_NDAT2;
71  __IO uint32_t MCAN_RXF0C;
72  __I uint32_t MCAN_RXF0S;
73  __IO uint32_t MCAN_RXF0A;
74  __IO uint32_t MCAN_RXBC;
75  __IO uint32_t MCAN_RXF1C;
76  __I uint32_t MCAN_RXF1S;
77  __IO uint32_t MCAN_RXF1A;
78  __IO uint32_t MCAN_RXESC;
79  __IO uint32_t MCAN_TXBC;
80  __I uint32_t MCAN_TXFQS;
81  __IO uint32_t MCAN_TXESC;
82  __I uint32_t MCAN_TXBRP;
83  __IO uint32_t MCAN_TXBAR;
84  __IO uint32_t MCAN_TXBCR;
85  __I uint32_t MCAN_TXBTO;
86  __I uint32_t MCAN_TXBCF;
87  __IO uint32_t MCAN_TXBTIE;
88  __IO uint32_t MCAN_TXBCIE;
89  __I uint32_t Reserved5[2];
90  __IO uint32_t MCAN_TXEFC;
91  __I uint32_t MCAN_TXEFS;
92  __IO uint32_t MCAN_TXEFA;
93 } Mcan;
94 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
95 /* -------- MCAN_CREL : (MCAN Offset: 0x00) Core Release Register -------- */
96 #define MCAN_CREL_DAY_Pos 0
97 #define MCAN_CREL_DAY_Msk (0xffu << MCAN_CREL_DAY_Pos)
98 #define MCAN_CREL_MON_Pos 8
99 #define MCAN_CREL_MON_Msk (0xffu << MCAN_CREL_MON_Pos)
100 #define MCAN_CREL_YEAR_Pos 16
101 #define MCAN_CREL_YEAR_Msk (0xfu << MCAN_CREL_YEAR_Pos)
102 #define MCAN_CREL_SUBSTEP_Pos 20
103 #define MCAN_CREL_SUBSTEP_Msk (0xfu << MCAN_CREL_SUBSTEP_Pos)
104 #define MCAN_CREL_STEP_Pos 24
105 #define MCAN_CREL_STEP_Msk (0xfu << MCAN_CREL_STEP_Pos)
106 #define MCAN_CREL_REL_Pos 28
107 #define MCAN_CREL_REL_Msk (0xfu << MCAN_CREL_REL_Pos)
108 /* -------- MCAN_ENDN : (MCAN Offset: 0x04) Endian Register -------- */
109 #define MCAN_ENDN_ETV_Pos 0
110 #define MCAN_ENDN_ETV_Msk (0xffffffffu << MCAN_ENDN_ETV_Pos)
111 /* -------- MCAN_CUST : (MCAN Offset: 0x08) Customer Register -------- */
112 #define MCAN_CUST_CSV_Pos 0
113 #define MCAN_CUST_CSV_Msk (0xffffffffu << MCAN_CUST_CSV_Pos)
114 #define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos)))
115 /* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */
116 #define MCAN_FBTP_FSJW_Pos 0
117 #define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos)
118 #define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos)))
119 #define MCAN_FBTP_FTSEG2_Pos 4
120 #define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos)
121 #define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos)))
122 #define MCAN_FBTP_FTSEG1_Pos 8
123 #define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos)
124 #define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos)))
125 #define MCAN_FBTP_FBRP_Pos 16
126 #define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos)
127 #define MCAN_FBTP_FBRP(value) ((MCAN_FBTP_FBRP_Msk & ((value) << MCAN_FBTP_FBRP_Pos)))
128 #define MCAN_FBTP_TDC (0x1u << 23)
129 #define MCAN_FBTP_TDC_DISABLED (0x0u << 23)
130 #define MCAN_FBTP_TDC_ENABLED (0x1u << 23)
131 #define MCAN_FBTP_TDCO_Pos 24
132 #define MCAN_FBTP_TDCO_Msk (0x1fu << MCAN_FBTP_TDCO_Pos)
133 #define MCAN_FBTP_TDCO(value) ((MCAN_FBTP_TDCO_Msk & ((value) << MCAN_FBTP_TDCO_Pos)))
134 /* -------- MCAN_TEST : (MCAN Offset: 0x10) Test Register -------- */
135 #define MCAN_TEST_LBCK (0x1u << 4)
136 #define MCAN_TEST_LBCK_DISABLED (0x0u << 4)
137 #define MCAN_TEST_LBCK_ENABLED (0x1u << 4)
138 #define MCAN_TEST_TX_Pos 5
139 #define MCAN_TEST_TX_Msk (0x3u << MCAN_TEST_TX_Pos)
140 #define MCAN_TEST_TX(value) ((MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos)))
141 #define MCAN_TEST_TX_RESET (0x0u << 5)
142 #define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (0x1u << 5)
143 #define MCAN_TEST_TX_DOMINANT (0x2u << 5)
144 #define MCAN_TEST_TX_RECESSIVE (0x3u << 5)
145 #define MCAN_TEST_RX (0x1u << 7)
146 #define MCAN_TEST_TDCV_Pos 8
147 #define MCAN_TEST_TDCV_Msk (0x3fu << MCAN_TEST_TDCV_Pos)
148 #define MCAN_TEST_TDCV(value) ((MCAN_TEST_TDCV_Msk & ((value) << MCAN_TEST_TDCV_Pos)))
149 /* -------- MCAN_RWD : (MCAN Offset: 0x14) RAM Watchdog Register -------- */
150 #define MCAN_RWD_WDC_Pos 0
151 #define MCAN_RWD_WDC_Msk (0xffu << MCAN_RWD_WDC_Pos)
152 #define MCAN_RWD_WDC(value) ((MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos)))
153 #define MCAN_RWD_WDV_Pos 8
154 #define MCAN_RWD_WDV_Msk (0xffu << MCAN_RWD_WDV_Pos)
155 #define MCAN_RWD_WDV(value) ((MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos)))
156 /* -------- MCAN_CCCR : (MCAN Offset: 0x18) CC Control Register -------- */
157 #define MCAN_CCCR_INIT (0x1u << 0)
158 #define MCAN_CCCR_INIT_DISABLED (0x0u << 0)
159 #define MCAN_CCCR_INIT_ENABLED (0x1u << 0)
160 #define MCAN_CCCR_CCE (0x1u << 1)
161 #define MCAN_CCCR_CCE_PROTECTED (0x0u << 1)
162 #define MCAN_CCCR_CCE_CONFIGURABLE (0x1u << 1)
163 #define MCAN_CCCR_ASM (0x1u << 2)
164 #define MCAN_CCCR_ASM_NORMAL (0x0u << 2)
165 #define MCAN_CCCR_ASM_RESTRICTED (0x1u << 2)
166 #define MCAN_CCCR_CSA (0x1u << 3)
167 #define MCAN_CCCR_CSR (0x1u << 4)
168 #define MCAN_CCCR_CSR_NO_CLOCK_STOP (0x0u << 4)
169 #define MCAN_CCCR_CSR_CLOCK_STOP (0x1u << 4)
170 #define MCAN_CCCR_MON (0x1u << 5)
171 #define MCAN_CCCR_MON_DISABLED (0x0u << 5)
172 #define MCAN_CCCR_MON_ENABLED (0x1u << 5)
173 #define MCAN_CCCR_DAR (0x1u << 6)
174 #define MCAN_CCCR_DAR_AUTO_RETX (0x0u << 6)
175 #define MCAN_CCCR_DAR_NO_AUTO_RETX (0x1u << 6)
176 #define MCAN_CCCR_TEST (0x1u << 7)
177 #define MCAN_CCCR_TEST_DISABLED (0x0u << 7)
178 #define MCAN_CCCR_TEST_ENABLED (0x1u << 7)
179 #define MCAN_CCCR_CME_Pos 8
180 #define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos)
181 #define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos)))
182 #define MCAN_CCCR_CME_ISO11898_1 (0x0u << 8)
183 #define MCAN_CCCR_CME_FD (0x1u << 8)
184 #define MCAN_CCCR_CMR_Pos 10
185 #define MCAN_CCCR_CMR_Msk (0x3u << MCAN_CCCR_CMR_Pos)
186 #define MCAN_CCCR_CMR(value) ((MCAN_CCCR_CMR_Msk & ((value) << MCAN_CCCR_CMR_Pos)))
187 #define MCAN_CCCR_CMR_NO_CHANGE (0x0u << 10)
188 #define MCAN_CCCR_CMR_FD (0x1u << 10)
189 #define MCAN_CCCR_CMR_FD_BITRATE_SWITCH (0x2u << 10)
190 #define MCAN_CCCR_CMR_ISO11898_1 (0x3u << 10)
191 #define MCAN_CCCR_FDO (0x1u << 12)
192 #define MCAN_CCCR_FDBS (0x1u << 13)
193 #define MCAN_CCCR_TXP (0x1u << 14)
194 /* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */
195 #define MCAN_BTP_SJW_Pos 0
196 #define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos)
197 #define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos)))
198 #define MCAN_BTP_TSEG2_Pos 4
199 #define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos)
200 #define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos)))
201 #define MCAN_BTP_TSEG1_Pos 8
202 #define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos)
203 #define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos)))
204 #define MCAN_BTP_BRP_Pos 16
205 #define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos)
206 #define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos)))
207 /* -------- MCAN_TSCC : (MCAN Offset: 0x20) Timestamp Counter Configuration Register -------- */
208 #define MCAN_TSCC_TSS_Pos 0
209 #define MCAN_TSCC_TSS_Msk (0x3u << MCAN_TSCC_TSS_Pos)
210 #define MCAN_TSCC_TSS(value) ((MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos)))
211 #define MCAN_TSCC_TSS_ALWAYS_0 (0x0u << 0)
212 #define MCAN_TSCC_TSS_TCP_INC (0x1u << 0)
213 #define MCAN_TSCC_TSS_EXT_TIMESTAMP (0x2u << 0)
214 #define MCAN_TSCC_TCP_Pos 16
215 #define MCAN_TSCC_TCP_Msk (0xfu << MCAN_TSCC_TCP_Pos)
216 #define MCAN_TSCC_TCP(value) ((MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos)))
217 /* -------- MCAN_TSCV : (MCAN Offset: 0x24) Timestamp Counter Value Register -------- */
218 #define MCAN_TSCV_TSC_Pos 0
219 #define MCAN_TSCV_TSC_Msk (0xffffu << MCAN_TSCV_TSC_Pos)
220 #define MCAN_TSCV_TSC(value) ((MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos)))
221 /* -------- MCAN_TOCC : (MCAN Offset: 0x28) Timeout Counter Configuration Register -------- */
222 #define MCAN_TOCC_ETOC (0x1u << 0)
223 #define MCAN_TOCC_ETOC_NO_TIMEOUT (0x0u << 0)
224 #define MCAN_TOCC_ETOC_TOS_CONTROLLED (0x1u << 0)
225 #define MCAN_TOCC_TOS_Pos 1
226 #define MCAN_TOCC_TOS_Msk (0x3u << MCAN_TOCC_TOS_Pos)
227 #define MCAN_TOCC_TOS(value) ((MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos)))
228 #define MCAN_TOCC_TOS_CONTINUOUS (0x0u << 1)
229 #define MCAN_TOCC_TOS_TX_EV_TIMEOUT (0x1u << 1)
230 #define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (0x2u << 1)
231 #define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (0x3u << 1)
232 #define MCAN_TOCC_TOP_Pos 16
233 #define MCAN_TOCC_TOP_Msk (0xffffu << MCAN_TOCC_TOP_Pos)
234 #define MCAN_TOCC_TOP(value) ((MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos)))
235 /* -------- MCAN_TOCV : (MCAN Offset: 0x2C) Timeout Counter Value Register -------- */
236 #define MCAN_TOCV_TOC_Pos 0
237 #define MCAN_TOCV_TOC_Msk (0xffffu << MCAN_TOCV_TOC_Pos)
238 #define MCAN_TOCV_TOC(value) ((MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos)))
239 /* -------- MCAN_ECR : (MCAN Offset: 0x40) Error Counter Register -------- */
240 #define MCAN_ECR_TEC_Pos 0
241 #define MCAN_ECR_TEC_Msk (0xffu << MCAN_ECR_TEC_Pos)
242 #define MCAN_ECR_REC_Pos 8
243 #define MCAN_ECR_REC_Msk (0x7fu << MCAN_ECR_REC_Pos)
244 #define MCAN_ECR_RP (0x1u << 15)
245 #define MCAN_ECR_CEL_Pos 16
246 #define MCAN_ECR_CEL_Msk (0xffu << MCAN_ECR_CEL_Pos)
247 /* -------- MCAN_PSR : (MCAN Offset: 0x44) Protocol Status Register -------- */
248 #define MCAN_PSR_LEC_Pos 0
249 #define MCAN_PSR_LEC_Msk (0x7u << MCAN_PSR_LEC_Pos)
250 #define MCAN_PSR_LEC_NO_ERROR (0x0u << 0)
251 #define MCAN_PSR_LEC_STUFF_ERROR (0x1u << 0)
252 #define MCAN_PSR_LEC_FORM_ERROR (0x2u << 0)
253 #define MCAN_PSR_LEC_ACK_ERROR (0x3u << 0)
254 #define MCAN_PSR_LEC_BIT1_ERROR (0x4u << 0)
255 #define MCAN_PSR_LEC_BIT0_ERROR (0x5u << 0)
256 #define MCAN_PSR_LEC_CRC_ERROR (0x6u << 0)
257 #define MCAN_PSR_LEC_NO_CHANGE (0x7u << 0)
258 #define MCAN_PSR_ACT_Pos 3
259 #define MCAN_PSR_ACT_Msk (0x3u << MCAN_PSR_ACT_Pos)
260 #define MCAN_PSR_ACT_SYNCHRONIZING (0x0u << 3)
261 #define MCAN_PSR_ACT_IDLE (0x1u << 3)
262 #define MCAN_PSR_ACT_RECEIVER (0x2u << 3)
263 #define MCAN_PSR_ACT_TRANSMITTER (0x3u << 3)
264 #define MCAN_PSR_EP (0x1u << 5)
265 #define MCAN_PSR_EW (0x1u << 6)
266 #define MCAN_PSR_BO (0x1u << 7)
267 #define MCAN_PSR_FLEC_Pos 8
268 #define MCAN_PSR_FLEC_Msk (0x7u << MCAN_PSR_FLEC_Pos)
269 #define MCAN_PSR_RESI (0x1u << 11)
270 #define MCAN_PSR_RBRS (0x1u << 12)
271 #define MCAN_PSR_REDL (0x1u << 13)
272 /* -------- MCAN_IR : (MCAN Offset: 0x50) Interrupt Register -------- */
273 #define MCAN_IR_RF0N (0x1u << 0)
274 #define MCAN_IR_RF0W (0x1u << 1)
275 #define MCAN_IR_RF0F (0x1u << 2)
276 #define MCAN_IR_RF0L (0x1u << 3)
277 #define MCAN_IR_RF1N (0x1u << 4)
278 #define MCAN_IR_RF1W (0x1u << 5)
279 #define MCAN_IR_RF1F (0x1u << 6)
280 #define MCAN_IR_RF1L (0x1u << 7)
281 #define MCAN_IR_HPM (0x1u << 8)
282 #define MCAN_IR_TC (0x1u << 9)
283 #define MCAN_IR_TCF (0x1u << 10)
284 #define MCAN_IR_TFE (0x1u << 11)
285 #define MCAN_IR_TEFN (0x1u << 12)
286 #define MCAN_IR_TEFW (0x1u << 13)
287 #define MCAN_IR_TEFF (0x1u << 14)
288 #define MCAN_IR_TEFL (0x1u << 15)
289 #define MCAN_IR_TSW (0x1u << 16)
290 #define MCAN_IR_MRAF (0x1u << 17)
291 #define MCAN_IR_TOO (0x1u << 18)
292 #define MCAN_IR_DRX (0x1u << 19)
293 #define MCAN_IR_BEC (0x1u << 20)
294 #define MCAN_IR_BEU (0x1u << 21)
295 #define MCAN_IR_ELO (0x1u << 22)
296 #define MCAN_IR_EP (0x1u << 23)
297 #define MCAN_IR_EW (0x1u << 24)
298 #define MCAN_IR_BO (0x1u << 25)
299 #define MCAN_IR_WDI (0x1u << 26)
300 #define MCAN_IR_CRCE (0x1u << 27)
301 #define MCAN_IR_BE (0x1u << 28)
302 #define MCAN_IR_ACKE (0x1u << 29)
303 #define MCAN_IR_FOE (0x1u << 30)
304 #define MCAN_IR_STE (0x1u << 31)
305 /* -------- MCAN_IE : (MCAN Offset: 0x54) Interrupt Enable Register -------- */
306 #define MCAN_IE_RF0NE (0x1u << 0)
307 #define MCAN_IE_RF0WE (0x1u << 1)
308 #define MCAN_IE_RF0FE (0x1u << 2)
309 #define MCAN_IE_RF0LE (0x1u << 3)
310 #define MCAN_IE_RF1NE (0x1u << 4)
311 #define MCAN_IE_RF1WE (0x1u << 5)
312 #define MCAN_IE_RF1FE (0x1u << 6)
313 #define MCAN_IE_RF1LE (0x1u << 7)
314 #define MCAN_IE_HPME (0x1u << 8)
315 #define MCAN_IE_TCE (0x1u << 9)
316 #define MCAN_IE_TCFE (0x1u << 10)
317 #define MCAN_IE_TFEE (0x1u << 11)
318 #define MCAN_IE_TEFNE (0x1u << 12)
319 #define MCAN_IE_TEFWE (0x1u << 13)
320 #define MCAN_IE_TEFFE (0x1u << 14)
321 #define MCAN_IE_TEFLE (0x1u << 15)
322 #define MCAN_IE_TSWE (0x1u << 16)
323 #define MCAN_IE_MRAFE (0x1u << 17)
324 #define MCAN_IE_TOOE (0x1u << 18)
325 #define MCAN_IE_DRXE (0x1u << 19)
326 #define MCAN_IE_BECE (0x1u << 20)
327 #define MCAN_IE_BEUE (0x1u << 21)
328 #define MCAN_IE_ELOE (0x1u << 22)
329 #define MCAN_IE_EPE (0x1u << 23)
330 #define MCAN_IE_EWE (0x1u << 24)
331 #define MCAN_IE_BOE (0x1u << 25)
332 #define MCAN_IE_WDIE (0x1u << 26)
333 #define MCAN_IE_CRCEE (0x1u << 27)
334 #define MCAN_IE_BEE (0x1u << 28)
335 #define MCAN_IE_ACKEE (0x1u << 29)
336 #define MCAN_IE_FOEE (0x1u << 30)
337 #define MCAN_IE_STEE (0x1u << 31)
338 /* -------- MCAN_ILS : (MCAN Offset: 0x58) Interrupt Line Select Register -------- */
339 #define MCAN_ILS_RF0NL (0x1u << 0)
340 #define MCAN_ILS_RF0WL (0x1u << 1)
341 #define MCAN_ILS_RF0FL (0x1u << 2)
342 #define MCAN_ILS_RF0LL (0x1u << 3)
343 #define MCAN_ILS_RF1NL (0x1u << 4)
344 #define MCAN_ILS_RF1WL (0x1u << 5)
345 #define MCAN_ILS_RF1FL (0x1u << 6)
346 #define MCAN_ILS_RF1LL (0x1u << 7)
347 #define MCAN_ILS_HPML (0x1u << 8)
348 #define MCAN_ILS_TCL (0x1u << 9)
349 #define MCAN_ILS_TCFL (0x1u << 10)
350 #define MCAN_ILS_TFEL (0x1u << 11)
351 #define MCAN_ILS_TEFNL (0x1u << 12)
352 #define MCAN_ILS_TEFWL (0x1u << 13)
353 #define MCAN_ILS_TEFFL (0x1u << 14)
354 #define MCAN_ILS_TEFLL (0x1u << 15)
355 #define MCAN_ILS_TSWL (0x1u << 16)
356 #define MCAN_ILS_MRAFL (0x1u << 17)
357 #define MCAN_ILS_TOOL (0x1u << 18)
358 #define MCAN_ILS_DRXL (0x1u << 19)
359 #define MCAN_ILS_BECL (0x1u << 20)
360 #define MCAN_ILS_BEUL (0x1u << 21)
361 #define MCAN_ILS_ELOL (0x1u << 22)
362 #define MCAN_ILS_EPL (0x1u << 23)
363 #define MCAN_ILS_EWL (0x1u << 24)
364 #define MCAN_ILS_BOL (0x1u << 25)
365 #define MCAN_ILS_WDIL (0x1u << 26)
366 #define MCAN_ILS_CRCEL (0x1u << 27)
367 #define MCAN_ILS_BEL (0x1u << 28)
368 #define MCAN_ILS_ACKEL (0x1u << 29)
369 #define MCAN_ILS_FOEL (0x1u << 30)
370 #define MCAN_ILS_STEL (0x1u << 31)
371 /* -------- MCAN_ILE : (MCAN Offset: 0x5C) Interrupt Line Enable Register -------- */
372 #define MCAN_ILE_EINT0 (0x1u << 0)
373 #define MCAN_ILE_EINT1 (0x1u << 1)
374 /* -------- MCAN_GFC : (MCAN Offset: 0x80) Global Filter Configuration Register -------- */
375 #define MCAN_GFC_RRFE (0x1u << 0)
376 #define MCAN_GFC_RRFE_FILTER (0x0u << 0)
377 #define MCAN_GFC_RRFE_REJECT (0x1u << 0)
378 #define MCAN_GFC_RRFS (0x1u << 1)
379 #define MCAN_GFC_RRFS_FILTER (0x0u << 1)
380 #define MCAN_GFC_RRFS_REJECT (0x1u << 1)
381 #define MCAN_GFC_ANFE_Pos 2
382 #define MCAN_GFC_ANFE_Msk (0x3u << MCAN_GFC_ANFE_Pos)
383 #define MCAN_GFC_ANFE(value) ((MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos)))
384 #define MCAN_GFC_ANFE_RX_FIFO_0 (0x0u << 2)
385 #define MCAN_GFC_ANFE_RX_FIFO_1 (0x1u << 2)
386 #define MCAN_GFC_ANFS_Pos 4
387 #define MCAN_GFC_ANFS_Msk (0x3u << MCAN_GFC_ANFS_Pos)
388 #define MCAN_GFC_ANFS(value) ((MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos)))
389 #define MCAN_GFC_ANFS_RX_FIFO_0 (0x0u << 4)
390 #define MCAN_GFC_ANFS_RX_FIFO_1 (0x1u << 4)
391 /* -------- MCAN_SIDFC : (MCAN Offset: 0x84) Standard ID Filter Configuration Register -------- */
392 #define MCAN_SIDFC_FLSSA_Pos 2
393 #define MCAN_SIDFC_FLSSA_Msk (0x3fffu << MCAN_SIDFC_FLSSA_Pos)
394 #define MCAN_SIDFC_FLSSA(value) ((MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos)))
395 #define MCAN_SIDFC_LSS_Pos 16
396 #define MCAN_SIDFC_LSS_Msk (0xffu << MCAN_SIDFC_LSS_Pos)
397 #define MCAN_SIDFC_LSS(value) ((MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos)))
398 /* -------- MCAN_XIDFC : (MCAN Offset: 0x88) Extended ID Filter Configuration Register -------- */
399 #define MCAN_XIDFC_FLESA_Pos 2
400 #define MCAN_XIDFC_FLESA_Msk (0x3fffu << MCAN_XIDFC_FLESA_Pos)
401 #define MCAN_XIDFC_FLESA(value) ((MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos)))
402 #define MCAN_XIDFC_LSE_Pos 16
403 #define MCAN_XIDFC_LSE_Msk (0x7fu << MCAN_XIDFC_LSE_Pos)
404 #define MCAN_XIDFC_LSE(value) ((MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos)))
405 /* -------- MCAN_XIDAM : (MCAN Offset: 0x90) Extended ID AND Mask Register -------- */
406 #define MCAN_XIDAM_EIDM_Pos 0
407 #define MCAN_XIDAM_EIDM_Msk (0x1fffffffu << MCAN_XIDAM_EIDM_Pos)
408 #define MCAN_XIDAM_EIDM(value) ((MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos)))
409 /* -------- MCAN_HPMS : (MCAN Offset: 0x94) High Priority Message Status Register -------- */
410 #define MCAN_HPMS_BIDX_Pos 0
411 #define MCAN_HPMS_BIDX_Msk (0x3fu << MCAN_HPMS_BIDX_Pos)
412 #define MCAN_HPMS_MSI_Pos 6
413 #define MCAN_HPMS_MSI_Msk (0x3u << MCAN_HPMS_MSI_Pos)
414 #define MCAN_HPMS_MSI_NO_FIFO_SEL (0x0u << 6)
415 #define MCAN_HPMS_MSI_LOST (0x1u << 6)
416 #define MCAN_HPMS_MSI_FIFO_0 (0x2u << 6)
417 #define MCAN_HPMS_MSI_FIFO_1 (0x3u << 6)
418 #define MCAN_HPMS_FIDX_Pos 8
419 #define MCAN_HPMS_FIDX_Msk (0x7fu << MCAN_HPMS_FIDX_Pos)
420 #define MCAN_HPMS_FLST (0x1u << 15)
421 /* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) New Data 1 Register -------- */
422 #define MCAN_NDAT1_ND0 (0x1u << 0)
423 #define MCAN_NDAT1_ND1 (0x1u << 1)
424 #define MCAN_NDAT1_ND2 (0x1u << 2)
425 #define MCAN_NDAT1_ND3 (0x1u << 3)
426 #define MCAN_NDAT1_ND4 (0x1u << 4)
427 #define MCAN_NDAT1_ND5 (0x1u << 5)
428 #define MCAN_NDAT1_ND6 (0x1u << 6)
429 #define MCAN_NDAT1_ND7 (0x1u << 7)
430 #define MCAN_NDAT1_ND8 (0x1u << 8)
431 #define MCAN_NDAT1_ND9 (0x1u << 9)
432 #define MCAN_NDAT1_ND10 (0x1u << 10)
433 #define MCAN_NDAT1_ND11 (0x1u << 11)
434 #define MCAN_NDAT1_ND12 (0x1u << 12)
435 #define MCAN_NDAT1_ND13 (0x1u << 13)
436 #define MCAN_NDAT1_ND14 (0x1u << 14)
437 #define MCAN_NDAT1_ND15 (0x1u << 15)
438 #define MCAN_NDAT1_ND16 (0x1u << 16)
439 #define MCAN_NDAT1_ND17 (0x1u << 17)
440 #define MCAN_NDAT1_ND18 (0x1u << 18)
441 #define MCAN_NDAT1_ND19 (0x1u << 19)
442 #define MCAN_NDAT1_ND20 (0x1u << 20)
443 #define MCAN_NDAT1_ND21 (0x1u << 21)
444 #define MCAN_NDAT1_ND22 (0x1u << 22)
445 #define MCAN_NDAT1_ND23 (0x1u << 23)
446 #define MCAN_NDAT1_ND24 (0x1u << 24)
447 #define MCAN_NDAT1_ND25 (0x1u << 25)
448 #define MCAN_NDAT1_ND26 (0x1u << 26)
449 #define MCAN_NDAT1_ND27 (0x1u << 27)
450 #define MCAN_NDAT1_ND28 (0x1u << 28)
451 #define MCAN_NDAT1_ND29 (0x1u << 29)
452 #define MCAN_NDAT1_ND30 (0x1u << 30)
453 #define MCAN_NDAT1_ND31 (0x1u << 31)
454 /* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) New Data 2 Register -------- */
455 #define MCAN_NDAT2_ND32 (0x1u << 0)
456 #define MCAN_NDAT2_ND33 (0x1u << 1)
457 #define MCAN_NDAT2_ND34 (0x1u << 2)
458 #define MCAN_NDAT2_ND35 (0x1u << 3)
459 #define MCAN_NDAT2_ND36 (0x1u << 4)
460 #define MCAN_NDAT2_ND37 (0x1u << 5)
461 #define MCAN_NDAT2_ND38 (0x1u << 6)
462 #define MCAN_NDAT2_ND39 (0x1u << 7)
463 #define MCAN_NDAT2_ND40 (0x1u << 8)
464 #define MCAN_NDAT2_ND41 (0x1u << 9)
465 #define MCAN_NDAT2_ND42 (0x1u << 10)
466 #define MCAN_NDAT2_ND43 (0x1u << 11)
467 #define MCAN_NDAT2_ND44 (0x1u << 12)
468 #define MCAN_NDAT2_ND45 (0x1u << 13)
469 #define MCAN_NDAT2_ND46 (0x1u << 14)
470 #define MCAN_NDAT2_ND47 (0x1u << 15)
471 #define MCAN_NDAT2_ND48 (0x1u << 16)
472 #define MCAN_NDAT2_ND49 (0x1u << 17)
473 #define MCAN_NDAT2_ND50 (0x1u << 18)
474 #define MCAN_NDAT2_ND51 (0x1u << 19)
475 #define MCAN_NDAT2_ND52 (0x1u << 20)
476 #define MCAN_NDAT2_ND53 (0x1u << 21)
477 #define MCAN_NDAT2_ND54 (0x1u << 22)
478 #define MCAN_NDAT2_ND55 (0x1u << 23)
479 #define MCAN_NDAT2_ND56 (0x1u << 24)
480 #define MCAN_NDAT2_ND57 (0x1u << 25)
481 #define MCAN_NDAT2_ND58 (0x1u << 26)
482 #define MCAN_NDAT2_ND59 (0x1u << 27)
483 #define MCAN_NDAT2_ND60 (0x1u << 28)
484 #define MCAN_NDAT2_ND61 (0x1u << 29)
485 #define MCAN_NDAT2_ND62 (0x1u << 30)
486 #define MCAN_NDAT2_ND63 (0x1u << 31)
487 /* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register -------- */
488 #define MCAN_RXF0C_F0SA_Pos 2
489 #define MCAN_RXF0C_F0SA_Msk (0x3fffu << MCAN_RXF0C_F0SA_Pos)
490 #define MCAN_RXF0C_F0SA(value) ((MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos)))
491 #define MCAN_RXF0C_F0S_Pos 16
492 #define MCAN_RXF0C_F0S_Msk (0x7fu << MCAN_RXF0C_F0S_Pos)
493 #define MCAN_RXF0C_F0S(value) ((MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos)))
494 #define MCAN_RXF0C_F0WM_Pos 24
495 #define MCAN_RXF0C_F0WM_Msk (0x7fu << MCAN_RXF0C_F0WM_Pos)
496 #define MCAN_RXF0C_F0WM(value) ((MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos)))
497 #define MCAN_RXF0C_F0OM (0x1u << 31)
498 /* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) Receive FIFO 0 Status Register -------- */
499 #define MCAN_RXF0S_F0FL_Pos 0
500 #define MCAN_RXF0S_F0FL_Msk (0x7fu << MCAN_RXF0S_F0FL_Pos)
501 #define MCAN_RXF0S_F0GI_Pos 8
502 #define MCAN_RXF0S_F0GI_Msk (0x3fu << MCAN_RXF0S_F0GI_Pos)
503 #define MCAN_RXF0S_F0PI_Pos 16
504 #define MCAN_RXF0S_F0PI_Msk (0x3fu << MCAN_RXF0S_F0PI_Pos)
505 #define MCAN_RXF0S_F0F (0x1u << 24)
506 #define MCAN_RXF0S_RF0L (0x1u << 25)
507 /* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register -------- */
508 #define MCAN_RXF0A_F0AI_Pos 0
509 #define MCAN_RXF0A_F0AI_Msk (0x3fu << MCAN_RXF0A_F0AI_Pos)
510 #define MCAN_RXF0A_F0AI(value) ((MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos)))
511 /* -------- MCAN_RXBC : (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register -------- */
512 #define MCAN_RXBC_RBSA_Pos 2
513 #define MCAN_RXBC_RBSA_Msk (0x3fffu << MCAN_RXBC_RBSA_Pos)
514 #define MCAN_RXBC_RBSA(value) ((MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos)))
515 /* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register -------- */
516 #define MCAN_RXF1C_F1SA_Pos 2
517 #define MCAN_RXF1C_F1SA_Msk (0x3fffu << MCAN_RXF1C_F1SA_Pos)
518 #define MCAN_RXF1C_F1SA(value) ((MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos)))
519 #define MCAN_RXF1C_F1S_Pos 16
520 #define MCAN_RXF1C_F1S_Msk (0x7fu << MCAN_RXF1C_F1S_Pos)
521 #define MCAN_RXF1C_F1S(value) ((MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos)))
522 #define MCAN_RXF1C_F1WM_Pos 24
523 #define MCAN_RXF1C_F1WM_Msk (0x7fu << MCAN_RXF1C_F1WM_Pos)
524 #define MCAN_RXF1C_F1WM(value) ((MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos)))
525 #define MCAN_RXF1C_F1OM (0x1u << 31)
526 /* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) Receive FIFO 1 Status Register -------- */
527 #define MCAN_RXF1S_F1FL_Pos 0
528 #define MCAN_RXF1S_F1FL_Msk (0x7fu << MCAN_RXF1S_F1FL_Pos)
529 #define MCAN_RXF1S_F1GI_Pos 8
530 #define MCAN_RXF1S_F1GI_Msk (0x3fu << MCAN_RXF1S_F1GI_Pos)
531 #define MCAN_RXF1S_F1PI_Pos 16
532 #define MCAN_RXF1S_F1PI_Msk (0x3fu << MCAN_RXF1S_F1PI_Pos)
533 #define MCAN_RXF1S_F1F (0x1u << 24)
534 #define MCAN_RXF1S_RF1L (0x1u << 25)
535 #define MCAN_RXF1S_DMS_Pos 30
536 #define MCAN_RXF1S_DMS_Msk (0x3u << MCAN_RXF1S_DMS_Pos)
537 #define MCAN_RXF1S_DMS_IDLE (0x0u << 30)
538 #define MCAN_RXF1S_DMS_MSG_A (0x1u << 30)
539 #define MCAN_RXF1S_DMS_MSG_AB (0x2u << 30)
540 #define MCAN_RXF1S_DMS_MSG_ABC (0x3u << 30)
541 /* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register -------- */
542 #define MCAN_RXF1A_F1AI_Pos 0
543 #define MCAN_RXF1A_F1AI_Msk (0x3fu << MCAN_RXF1A_F1AI_Pos)
544 #define MCAN_RXF1A_F1AI(value) ((MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos)))
545 /* -------- MCAN_RXESC : (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register -------- */
546 #define MCAN_RXESC_F0DS_Pos 0
547 #define MCAN_RXESC_F0DS_Msk (0x7u << MCAN_RXESC_F0DS_Pos)
548 #define MCAN_RXESC_F0DS(value) ((MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos)))
549 #define MCAN_RXESC_F0DS_8_BYTE (0x0u << 0)
550 #define MCAN_RXESC_F0DS_12_BYTE (0x1u << 0)
551 #define MCAN_RXESC_F0DS_16_BYTE (0x2u << 0)
552 #define MCAN_RXESC_F0DS_20_BYTE (0x3u << 0)
553 #define MCAN_RXESC_F0DS_24_BYTE (0x4u << 0)
554 #define MCAN_RXESC_F0DS_32_BYTE (0x5u << 0)
555 #define MCAN_RXESC_F0DS_48_BYTE (0x6u << 0)
556 #define MCAN_RXESC_F0DS_64_BYTE (0x7u << 0)
557 #define MCAN_RXESC_F1DS_Pos 4
558 #define MCAN_RXESC_F1DS_Msk (0x7u << MCAN_RXESC_F1DS_Pos)
559 #define MCAN_RXESC_F1DS(value) ((MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos)))
560 #define MCAN_RXESC_F1DS_8_BYTE (0x0u << 4)
561 #define MCAN_RXESC_F1DS_12_BYTE (0x1u << 4)
562 #define MCAN_RXESC_F1DS_16_BYTE (0x2u << 4)
563 #define MCAN_RXESC_F1DS_20_BYTE (0x3u << 4)
564 #define MCAN_RXESC_F1DS_24_BYTE (0x4u << 4)
565 #define MCAN_RXESC_F1DS_32_BYTE (0x5u << 4)
566 #define MCAN_RXESC_F1DS_48_BYTE (0x6u << 4)
567 #define MCAN_RXESC_F1DS_64_BYTE (0x7u << 4)
568 #define MCAN_RXESC_RBDS_Pos 8
569 #define MCAN_RXESC_RBDS_Msk (0x7u << MCAN_RXESC_RBDS_Pos)
570 #define MCAN_RXESC_RBDS(value) ((MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos)))
571 #define MCAN_RXESC_RBDS_8_BYTE (0x0u << 8)
572 #define MCAN_RXESC_RBDS_12_BYTE (0x1u << 8)
573 #define MCAN_RXESC_RBDS_16_BYTE (0x2u << 8)
574 #define MCAN_RXESC_RBDS_20_BYTE (0x3u << 8)
575 #define MCAN_RXESC_RBDS_24_BYTE (0x4u << 8)
576 #define MCAN_RXESC_RBDS_32_BYTE (0x5u << 8)
577 #define MCAN_RXESC_RBDS_48_BYTE (0x6u << 8)
578 #define MCAN_RXESC_RBDS_64_BYTE (0x7u << 8)
579 /* -------- MCAN_TXBC : (MCAN Offset: 0xC0) Transmit Buffer Configuration Register -------- */
580 #define MCAN_TXBC_TBSA_Pos 2
581 #define MCAN_TXBC_TBSA_Msk (0x3fffu << MCAN_TXBC_TBSA_Pos)
582 #define MCAN_TXBC_TBSA(value) ((MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos)))
583 #define MCAN_TXBC_NDTB_Pos 16
584 #define MCAN_TXBC_NDTB_Msk (0x3fu << MCAN_TXBC_NDTB_Pos)
585 #define MCAN_TXBC_NDTB(value) ((MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos)))
586 #define MCAN_TXBC_TFQS_Pos 24
587 #define MCAN_TXBC_TFQS_Msk (0x3fu << MCAN_TXBC_TFQS_Pos)
588 #define MCAN_TXBC_TFQS(value) ((MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos)))
589 #define MCAN_TXBC_TFQM (0x1u << 30)
590 /* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register -------- */
591 #define MCAN_TXFQS_TFFL_Pos 0
592 #define MCAN_TXFQS_TFFL_Msk (0x3fu << MCAN_TXFQS_TFFL_Pos)
593 #define MCAN_TXFQS_TFGI_Pos 8
594 #define MCAN_TXFQS_TFGI_Msk (0x1fu << MCAN_TXFQS_TFGI_Pos)
595 #define MCAN_TXFQS_TFQPI_Pos 16
596 #define MCAN_TXFQS_TFQPI_Msk (0x1fu << MCAN_TXFQS_TFQPI_Pos)
597 #define MCAN_TXFQS_TFQF (0x1u << 21)
598 /* -------- MCAN_TXESC : (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register -------- */
599 #define MCAN_TXESC_TBDS_Pos 0
600 #define MCAN_TXESC_TBDS_Msk (0x7u << MCAN_TXESC_TBDS_Pos)
601 #define MCAN_TXESC_TBDS(value) ((MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos)))
602 #define MCAN_TXESC_TBDS_8_BYTE (0x0u << 0)
603 #define MCAN_TXESC_TBDS_12_BYTE (0x1u << 0)
604 #define MCAN_TXESC_TBDS_16_BYTE (0x2u << 0)
605 #define MCAN_TXESC_TBDS_20_BYTE (0x3u << 0)
606 #define MCAN_TXESC_TBDS_24_BYTE (0x4u << 0)
607 #define MCAN_TXESC_TBDS_32_BYTE (0x5u << 0)
608 #define MCAN_TXESC_TBDS_48_BYTE (0x6u << 0)
609 #define MCAN_TXESC_TBDS_64_BYTE (0x7u << 0)
610 /* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register -------- */
611 #define MCAN_TXBRP_TRP0 (0x1u << 0)
612 #define MCAN_TXBRP_TRP1 (0x1u << 1)
613 #define MCAN_TXBRP_TRP2 (0x1u << 2)
614 #define MCAN_TXBRP_TRP3 (0x1u << 3)
615 #define MCAN_TXBRP_TRP4 (0x1u << 4)
616 #define MCAN_TXBRP_TRP5 (0x1u << 5)
617 #define MCAN_TXBRP_TRP6 (0x1u << 6)
618 #define MCAN_TXBRP_TRP7 (0x1u << 7)
619 #define MCAN_TXBRP_TRP8 (0x1u << 8)
620 #define MCAN_TXBRP_TRP9 (0x1u << 9)
621 #define MCAN_TXBRP_TRP10 (0x1u << 10)
622 #define MCAN_TXBRP_TRP11 (0x1u << 11)
623 #define MCAN_TXBRP_TRP12 (0x1u << 12)
624 #define MCAN_TXBRP_TRP13 (0x1u << 13)
625 #define MCAN_TXBRP_TRP14 (0x1u << 14)
626 #define MCAN_TXBRP_TRP15 (0x1u << 15)
627 #define MCAN_TXBRP_TRP16 (0x1u << 16)
628 #define MCAN_TXBRP_TRP17 (0x1u << 17)
629 #define MCAN_TXBRP_TRP18 (0x1u << 18)
630 #define MCAN_TXBRP_TRP19 (0x1u << 19)
631 #define MCAN_TXBRP_TRP20 (0x1u << 20)
632 #define MCAN_TXBRP_TRP21 (0x1u << 21)
633 #define MCAN_TXBRP_TRP22 (0x1u << 22)
634 #define MCAN_TXBRP_TRP23 (0x1u << 23)
635 #define MCAN_TXBRP_TRP24 (0x1u << 24)
636 #define MCAN_TXBRP_TRP25 (0x1u << 25)
637 #define MCAN_TXBRP_TRP26 (0x1u << 26)
638 #define MCAN_TXBRP_TRP27 (0x1u << 27)
639 #define MCAN_TXBRP_TRP28 (0x1u << 28)
640 #define MCAN_TXBRP_TRP29 (0x1u << 29)
641 #define MCAN_TXBRP_TRP30 (0x1u << 30)
642 #define MCAN_TXBRP_TRP31 (0x1u << 31)
643 /* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) Transmit Buffer Add Request Register -------- */
644 #define MCAN_TXBAR_AR0 (0x1u << 0)
645 #define MCAN_TXBAR_AR1 (0x1u << 1)
646 #define MCAN_TXBAR_AR2 (0x1u << 2)
647 #define MCAN_TXBAR_AR3 (0x1u << 3)
648 #define MCAN_TXBAR_AR4 (0x1u << 4)
649 #define MCAN_TXBAR_AR5 (0x1u << 5)
650 #define MCAN_TXBAR_AR6 (0x1u << 6)
651 #define MCAN_TXBAR_AR7 (0x1u << 7)
652 #define MCAN_TXBAR_AR8 (0x1u << 8)
653 #define MCAN_TXBAR_AR9 (0x1u << 9)
654 #define MCAN_TXBAR_AR10 (0x1u << 10)
655 #define MCAN_TXBAR_AR11 (0x1u << 11)
656 #define MCAN_TXBAR_AR12 (0x1u << 12)
657 #define MCAN_TXBAR_AR13 (0x1u << 13)
658 #define MCAN_TXBAR_AR14 (0x1u << 14)
659 #define MCAN_TXBAR_AR15 (0x1u << 15)
660 #define MCAN_TXBAR_AR16 (0x1u << 16)
661 #define MCAN_TXBAR_AR17 (0x1u << 17)
662 #define MCAN_TXBAR_AR18 (0x1u << 18)
663 #define MCAN_TXBAR_AR19 (0x1u << 19)
664 #define MCAN_TXBAR_AR20 (0x1u << 20)
665 #define MCAN_TXBAR_AR21 (0x1u << 21)
666 #define MCAN_TXBAR_AR22 (0x1u << 22)
667 #define MCAN_TXBAR_AR23 (0x1u << 23)
668 #define MCAN_TXBAR_AR24 (0x1u << 24)
669 #define MCAN_TXBAR_AR25 (0x1u << 25)
670 #define MCAN_TXBAR_AR26 (0x1u << 26)
671 #define MCAN_TXBAR_AR27 (0x1u << 27)
672 #define MCAN_TXBAR_AR28 (0x1u << 28)
673 #define MCAN_TXBAR_AR29 (0x1u << 29)
674 #define MCAN_TXBAR_AR30 (0x1u << 30)
675 #define MCAN_TXBAR_AR31 (0x1u << 31)
676 /* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register -------- */
677 #define MCAN_TXBCR_CR0 (0x1u << 0)
678 #define MCAN_TXBCR_CR1 (0x1u << 1)
679 #define MCAN_TXBCR_CR2 (0x1u << 2)
680 #define MCAN_TXBCR_CR3 (0x1u << 3)
681 #define MCAN_TXBCR_CR4 (0x1u << 4)
682 #define MCAN_TXBCR_CR5 (0x1u << 5)
683 #define MCAN_TXBCR_CR6 (0x1u << 6)
684 #define MCAN_TXBCR_CR7 (0x1u << 7)
685 #define MCAN_TXBCR_CR8 (0x1u << 8)
686 #define MCAN_TXBCR_CR9 (0x1u << 9)
687 #define MCAN_TXBCR_CR10 (0x1u << 10)
688 #define MCAN_TXBCR_CR11 (0x1u << 11)
689 #define MCAN_TXBCR_CR12 (0x1u << 12)
690 #define MCAN_TXBCR_CR13 (0x1u << 13)
691 #define MCAN_TXBCR_CR14 (0x1u << 14)
692 #define MCAN_TXBCR_CR15 (0x1u << 15)
693 #define MCAN_TXBCR_CR16 (0x1u << 16)
694 #define MCAN_TXBCR_CR17 (0x1u << 17)
695 #define MCAN_TXBCR_CR18 (0x1u << 18)
696 #define MCAN_TXBCR_CR19 (0x1u << 19)
697 #define MCAN_TXBCR_CR20 (0x1u << 20)
698 #define MCAN_TXBCR_CR21 (0x1u << 21)
699 #define MCAN_TXBCR_CR22 (0x1u << 22)
700 #define MCAN_TXBCR_CR23 (0x1u << 23)
701 #define MCAN_TXBCR_CR24 (0x1u << 24)
702 #define MCAN_TXBCR_CR25 (0x1u << 25)
703 #define MCAN_TXBCR_CR26 (0x1u << 26)
704 #define MCAN_TXBCR_CR27 (0x1u << 27)
705 #define MCAN_TXBCR_CR28 (0x1u << 28)
706 #define MCAN_TXBCR_CR29 (0x1u << 29)
707 #define MCAN_TXBCR_CR30 (0x1u << 30)
708 #define MCAN_TXBCR_CR31 (0x1u << 31)
709 /* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register -------- */
710 #define MCAN_TXBTO_TO0 (0x1u << 0)
711 #define MCAN_TXBTO_TO1 (0x1u << 1)
712 #define MCAN_TXBTO_TO2 (0x1u << 2)
713 #define MCAN_TXBTO_TO3 (0x1u << 3)
714 #define MCAN_TXBTO_TO4 (0x1u << 4)
715 #define MCAN_TXBTO_TO5 (0x1u << 5)
716 #define MCAN_TXBTO_TO6 (0x1u << 6)
717 #define MCAN_TXBTO_TO7 (0x1u << 7)
718 #define MCAN_TXBTO_TO8 (0x1u << 8)
719 #define MCAN_TXBTO_TO9 (0x1u << 9)
720 #define MCAN_TXBTO_TO10 (0x1u << 10)
721 #define MCAN_TXBTO_TO11 (0x1u << 11)
722 #define MCAN_TXBTO_TO12 (0x1u << 12)
723 #define MCAN_TXBTO_TO13 (0x1u << 13)
724 #define MCAN_TXBTO_TO14 (0x1u << 14)
725 #define MCAN_TXBTO_TO15 (0x1u << 15)
726 #define MCAN_TXBTO_TO16 (0x1u << 16)
727 #define MCAN_TXBTO_TO17 (0x1u << 17)
728 #define MCAN_TXBTO_TO18 (0x1u << 18)
729 #define MCAN_TXBTO_TO19 (0x1u << 19)
730 #define MCAN_TXBTO_TO20 (0x1u << 20)
731 #define MCAN_TXBTO_TO21 (0x1u << 21)
732 #define MCAN_TXBTO_TO22 (0x1u << 22)
733 #define MCAN_TXBTO_TO23 (0x1u << 23)
734 #define MCAN_TXBTO_TO24 (0x1u << 24)
735 #define MCAN_TXBTO_TO25 (0x1u << 25)
736 #define MCAN_TXBTO_TO26 (0x1u << 26)
737 #define MCAN_TXBTO_TO27 (0x1u << 27)
738 #define MCAN_TXBTO_TO28 (0x1u << 28)
739 #define MCAN_TXBTO_TO29 (0x1u << 29)
740 #define MCAN_TXBTO_TO30 (0x1u << 30)
741 #define MCAN_TXBTO_TO31 (0x1u << 31)
742 /* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register -------- */
743 #define MCAN_TXBCF_CF0 (0x1u << 0)
744 #define MCAN_TXBCF_CF1 (0x1u << 1)
745 #define MCAN_TXBCF_CF2 (0x1u << 2)
746 #define MCAN_TXBCF_CF3 (0x1u << 3)
747 #define MCAN_TXBCF_CF4 (0x1u << 4)
748 #define MCAN_TXBCF_CF5 (0x1u << 5)
749 #define MCAN_TXBCF_CF6 (0x1u << 6)
750 #define MCAN_TXBCF_CF7 (0x1u << 7)
751 #define MCAN_TXBCF_CF8 (0x1u << 8)
752 #define MCAN_TXBCF_CF9 (0x1u << 9)
753 #define MCAN_TXBCF_CF10 (0x1u << 10)
754 #define MCAN_TXBCF_CF11 (0x1u << 11)
755 #define MCAN_TXBCF_CF12 (0x1u << 12)
756 #define MCAN_TXBCF_CF13 (0x1u << 13)
757 #define MCAN_TXBCF_CF14 (0x1u << 14)
758 #define MCAN_TXBCF_CF15 (0x1u << 15)
759 #define MCAN_TXBCF_CF16 (0x1u << 16)
760 #define MCAN_TXBCF_CF17 (0x1u << 17)
761 #define MCAN_TXBCF_CF18 (0x1u << 18)
762 #define MCAN_TXBCF_CF19 (0x1u << 19)
763 #define MCAN_TXBCF_CF20 (0x1u << 20)
764 #define MCAN_TXBCF_CF21 (0x1u << 21)
765 #define MCAN_TXBCF_CF22 (0x1u << 22)
766 #define MCAN_TXBCF_CF23 (0x1u << 23)
767 #define MCAN_TXBCF_CF24 (0x1u << 24)
768 #define MCAN_TXBCF_CF25 (0x1u << 25)
769 #define MCAN_TXBCF_CF26 (0x1u << 26)
770 #define MCAN_TXBCF_CF27 (0x1u << 27)
771 #define MCAN_TXBCF_CF28 (0x1u << 28)
772 #define MCAN_TXBCF_CF29 (0x1u << 29)
773 #define MCAN_TXBCF_CF30 (0x1u << 30)
774 #define MCAN_TXBCF_CF31 (0x1u << 31)
775 /* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register -------- */
776 #define MCAN_TXBTIE_TIE0 (0x1u << 0)
777 #define MCAN_TXBTIE_TIE1 (0x1u << 1)
778 #define MCAN_TXBTIE_TIE2 (0x1u << 2)
779 #define MCAN_TXBTIE_TIE3 (0x1u << 3)
780 #define MCAN_TXBTIE_TIE4 (0x1u << 4)
781 #define MCAN_TXBTIE_TIE5 (0x1u << 5)
782 #define MCAN_TXBTIE_TIE6 (0x1u << 6)
783 #define MCAN_TXBTIE_TIE7 (0x1u << 7)
784 #define MCAN_TXBTIE_TIE8 (0x1u << 8)
785 #define MCAN_TXBTIE_TIE9 (0x1u << 9)
786 #define MCAN_TXBTIE_TIE10 (0x1u << 10)
787 #define MCAN_TXBTIE_TIE11 (0x1u << 11)
788 #define MCAN_TXBTIE_TIE12 (0x1u << 12)
789 #define MCAN_TXBTIE_TIE13 (0x1u << 13)
790 #define MCAN_TXBTIE_TIE14 (0x1u << 14)
791 #define MCAN_TXBTIE_TIE15 (0x1u << 15)
792 #define MCAN_TXBTIE_TIE16 (0x1u << 16)
793 #define MCAN_TXBTIE_TIE17 (0x1u << 17)
794 #define MCAN_TXBTIE_TIE18 (0x1u << 18)
795 #define MCAN_TXBTIE_TIE19 (0x1u << 19)
796 #define MCAN_TXBTIE_TIE20 (0x1u << 20)
797 #define MCAN_TXBTIE_TIE21 (0x1u << 21)
798 #define MCAN_TXBTIE_TIE22 (0x1u << 22)
799 #define MCAN_TXBTIE_TIE23 (0x1u << 23)
800 #define MCAN_TXBTIE_TIE24 (0x1u << 24)
801 #define MCAN_TXBTIE_TIE25 (0x1u << 25)
802 #define MCAN_TXBTIE_TIE26 (0x1u << 26)
803 #define MCAN_TXBTIE_TIE27 (0x1u << 27)
804 #define MCAN_TXBTIE_TIE28 (0x1u << 28)
805 #define MCAN_TXBTIE_TIE29 (0x1u << 29)
806 #define MCAN_TXBTIE_TIE30 (0x1u << 30)
807 #define MCAN_TXBTIE_TIE31 (0x1u << 31)
808 /* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */
809 #define MCAN_TXBCIE_CFIE0 (0x1u << 0)
810 #define MCAN_TXBCIE_CFIE1 (0x1u << 1)
811 #define MCAN_TXBCIE_CFIE2 (0x1u << 2)
812 #define MCAN_TXBCIE_CFIE3 (0x1u << 3)
813 #define MCAN_TXBCIE_CFIE4 (0x1u << 4)
814 #define MCAN_TXBCIE_CFIE5 (0x1u << 5)
815 #define MCAN_TXBCIE_CFIE6 (0x1u << 6)
816 #define MCAN_TXBCIE_CFIE7 (0x1u << 7)
817 #define MCAN_TXBCIE_CFIE8 (0x1u << 8)
818 #define MCAN_TXBCIE_CFIE9 (0x1u << 9)
819 #define MCAN_TXBCIE_CFIE10 (0x1u << 10)
820 #define MCAN_TXBCIE_CFIE11 (0x1u << 11)
821 #define MCAN_TXBCIE_CFIE12 (0x1u << 12)
822 #define MCAN_TXBCIE_CFIE13 (0x1u << 13)
823 #define MCAN_TXBCIE_CFIE14 (0x1u << 14)
824 #define MCAN_TXBCIE_CFIE15 (0x1u << 15)
825 #define MCAN_TXBCIE_CFIE16 (0x1u << 16)
826 #define MCAN_TXBCIE_CFIE17 (0x1u << 17)
827 #define MCAN_TXBCIE_CFIE18 (0x1u << 18)
828 #define MCAN_TXBCIE_CFIE19 (0x1u << 19)
829 #define MCAN_TXBCIE_CFIE20 (0x1u << 20)
830 #define MCAN_TXBCIE_CFIE21 (0x1u << 21)
831 #define MCAN_TXBCIE_CFIE22 (0x1u << 22)
832 #define MCAN_TXBCIE_CFIE23 (0x1u << 23)
833 #define MCAN_TXBCIE_CFIE24 (0x1u << 24)
834 #define MCAN_TXBCIE_CFIE25 (0x1u << 25)
835 #define MCAN_TXBCIE_CFIE26 (0x1u << 26)
836 #define MCAN_TXBCIE_CFIE27 (0x1u << 27)
837 #define MCAN_TXBCIE_CFIE28 (0x1u << 28)
838 #define MCAN_TXBCIE_CFIE29 (0x1u << 29)
839 #define MCAN_TXBCIE_CFIE30 (0x1u << 30)
840 #define MCAN_TXBCIE_CFIE31 (0x1u << 31)
841 /* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register -------- */
842 #define MCAN_TXEFC_EFSA_Pos 2
843 #define MCAN_TXEFC_EFSA_Msk (0x3fffu << MCAN_TXEFC_EFSA_Pos)
844 #define MCAN_TXEFC_EFSA(value) ((MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos)))
845 #define MCAN_TXEFC_EFS_Pos 16
846 #define MCAN_TXEFC_EFS_Msk (0x3fu << MCAN_TXEFC_EFS_Pos)
847 #define MCAN_TXEFC_EFS(value) ((MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos)))
848 #define MCAN_TXEFC_EFWM_Pos 24
849 #define MCAN_TXEFC_EFWM_Msk (0x3fu << MCAN_TXEFC_EFWM_Pos)
850 #define MCAN_TXEFC_EFWM(value) ((MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos)))
851 /* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) Transmit Event FIFO Status Register -------- */
852 #define MCAN_TXEFS_EFFL_Pos 0
853 #define MCAN_TXEFS_EFFL_Msk (0x3fu << MCAN_TXEFS_EFFL_Pos)
854 #define MCAN_TXEFS_EFGI_Pos 8
855 #define MCAN_TXEFS_EFGI_Msk (0x1fu << MCAN_TXEFS_EFGI_Pos)
856 #define MCAN_TXEFS_EFPI_Pos 16
857 #define MCAN_TXEFS_EFPI_Msk (0x1fu << MCAN_TXEFS_EFPI_Pos)
858 #define MCAN_TXEFS_EFF (0x1u << 24)
859 #define MCAN_TXEFS_TEFL (0x1u << 25)
860 /* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register -------- */
861 #define MCAN_TXEFA_EFAI_Pos 0
862 #define MCAN_TXEFA_EFAI_Msk (0x1fu << MCAN_TXEFA_EFAI_Pos)
863 #define MCAN_TXEFA_EFAI(value) ((MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos)))
864 
868 #endif /* _SAMV71_MCAN_COMPONENT_ */
Mcan::MCAN_CREL
__I uint32_t MCAN_CREL
(Mcan Offset: 0x00) Core Release Register
Definition: component_mcan.h:42
__IO
#define __IO
Definition: core_cm7.h:287
Mcan
Mcan hardware registers.
Definition: component_mcan.h:41
Mcan::MCAN_ENDN
__I uint32_t MCAN_ENDN
(Mcan Offset: 0x04) Endian Register
Definition: component_mcan.h:43
__I
#define __I
Definition: core_cm7.h:284
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