RTEMS  5.1
component_chipid.h
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29 
30 #ifndef _SAMV71_CHIPID_COMPONENT_
31 #define _SAMV71_CHIPID_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  __I uint32_t CHIPID_CIDR;
43  __I uint32_t CHIPID_EXID;
44 } Chipid;
45 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
46 /* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
47 #define CHIPID_CIDR_VERSION_Pos 0
48 #define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos)
49 #define CHIPID_CIDR_EPROC_Pos 5
50 #define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos)
51 #define CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5)
52 #define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5)
53 #define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5)
54 #define CHIPID_CIDR_EPROC_CM3 (0x3u << 5)
55 #define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5)
56 #define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5)
57 #define CHIPID_CIDR_EPROC_CA5 (0x6u << 5)
58 #define CHIPID_CIDR_EPROC_CM4 (0x7u << 5)
59 #define CHIPID_CIDR_NVPSIZ_Pos 8
60 #define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos)
61 #define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8)
62 #define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8)
63 #define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8)
64 #define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8)
65 #define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8)
66 #define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8)
67 #define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8)
68 #define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8)
69 #define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8)
70 #define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8)
71 #define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8)
72 #define CHIPID_CIDR_NVPSIZ2_Pos 12
73 #define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos)
74 #define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12)
75 #define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12)
76 #define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12)
77 #define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12)
78 #define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12)
79 #define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12)
80 #define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12)
81 #define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12)
82 #define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12)
83 #define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12)
84 #define CHIPID_CIDR_SRAMSIZ_Pos 16
85 #define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos)
86 #define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16)
87 #define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16)
88 #define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16)
89 #define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16)
90 #define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16)
91 #define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16)
92 #define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16)
93 #define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16)
94 #define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16)
95 #define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16)
96 #define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16)
97 #define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16)
98 #define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16)
99 #define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16)
100 #define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16)
101 #define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16)
102 #define CHIPID_CIDR_ARCH_Pos 20
103 #define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos)
104 #define CHIPID_CIDR_ARCH_SAME70 (0x10u << 20)
105 #define CHIPID_CIDR_ARCH_SAMS70 (0x11u << 20)
106 #define CHIPID_CIDR_ARCH_SAMV71 (0x12u << 20)
107 #define CHIPID_CIDR_ARCH_SAMV70 (0x13u << 20)
108 #define CHIPID_CIDR_NVPTYP_Pos 28
109 #define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos)
110 #define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28)
111 #define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28)
112 #define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28)
113 #define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28)
114 #define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28)
115 #define CHIPID_CIDR_EXT (0x1u << 31)
116 /* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
117 #define CHIPID_EXID_EXID_Pos 0
118 #define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos)
121 
122 
123 #endif /* _SAMV71_CHIPID_COMPONENT_ */
Chipid
Chipid hardware registers.
Definition: component_chipid.h:41
__I
#define __I
Definition: core_cm7.h:284
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