RTEMS  5.1
component_usbhs.h
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29 
30 #ifndef _SAMS70_USBHS_COMPONENT_
31 #define _SAMS70_USBHS_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  __IO uint32_t USBHS_DEVDMANXTDSC;
43  __IO uint32_t USBHS_DEVDMAADDRESS;
44  __IO uint32_t USBHS_DEVDMACONTROL;
45  __IO uint32_t USBHS_DEVDMASTATUS;
46 } UsbhsDevdma;
48 typedef struct {
49  __IO uint32_t USBHS_HSTDMANXTDSC;
50  __IO uint32_t USBHS_HSTDMAADDRESS;
51  __IO uint32_t USBHS_HSTDMACONTROL;
52  __IO uint32_t USBHS_HSTDMASTATUS;
53 } UsbhsHstdma;
55 #define USBHSDEVDMA_NUMBER 7
56 #define USBHSHSTDMA_NUMBER 7
57 typedef struct {
58  __IO uint32_t USBHS_DEVCTRL;
59  __I uint32_t USBHS_DEVISR;
60  __O uint32_t USBHS_DEVICR;
61  __O uint32_t USBHS_DEVIFR;
62  __I uint32_t USBHS_DEVIMR;
63  __O uint32_t USBHS_DEVIDR;
64  __O uint32_t USBHS_DEVIER;
65  __IO uint32_t USBHS_DEVEPT;
66  __I uint32_t USBHS_DEVFNUM;
67  __I uint32_t Reserved1[55];
68  __IO uint32_t USBHS_DEVEPTCFG[10];
69  __I uint32_t Reserved2[2];
70  __I uint32_t USBHS_DEVEPTISR[10];
71  __I uint32_t Reserved3[2];
72  __O uint32_t USBHS_DEVEPTICR[10];
73  __I uint32_t Reserved4[2];
74  __O uint32_t USBHS_DEVEPTIFR[10];
75  __I uint32_t Reserved5[2];
76  __I uint32_t USBHS_DEVEPTIMR[10];
77  __I uint32_t Reserved6[2];
78  __O uint32_t USBHS_DEVEPTIER[10];
79  __I uint32_t Reserved7[2];
80  __O uint32_t USBHS_DEVEPTIDR[10];
81  __I uint32_t Reserved8[50];
82  UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER];
83  __I uint32_t Reserved9[32];
84  __IO uint32_t USBHS_HSTCTRL;
85  __I uint32_t USBHS_HSTISR;
86  __O uint32_t USBHS_HSTICR;
87  __O uint32_t USBHS_HSTIFR;
88  __I uint32_t USBHS_HSTIMR;
89  __O uint32_t USBHS_HSTIDR;
90  __O uint32_t USBHS_HSTIER;
91  __IO uint32_t USBHS_HSTPIP;
92  __IO uint32_t USBHS_HSTFNUM;
93  __IO uint32_t USBHS_HSTADDR1;
94  __IO uint32_t USBHS_HSTADDR2;
95  __IO uint32_t USBHS_HSTADDR3;
96  __I uint32_t Reserved10[52];
97  __IO uint32_t USBHS_HSTPIPCFG[10];
98  __I uint32_t Reserved11[2];
99  __I uint32_t USBHS_HSTPIPISR[10];
100  __I uint32_t Reserved12[2];
101  __O uint32_t USBHS_HSTPIPICR[10];
102  __I uint32_t Reserved13[2];
103  __O uint32_t USBHS_HSTPIPIFR[10];
104  __I uint32_t Reserved14[2];
105  __I uint32_t USBHS_HSTPIPIMR[10];
106  __I uint32_t Reserved15[2];
107  __O uint32_t USBHS_HSTPIPIER[10];
108  __I uint32_t Reserved16[2];
109  __O uint32_t USBHS_HSTPIPIDR[10];
110  __I uint32_t Reserved17[2];
111  __IO uint32_t USBHS_HSTPIPINRQ[10];
112  __I uint32_t Reserved18[2];
113  __IO uint32_t USBHS_HSTPIPERR[10];
114  __I uint32_t Reserved19[26];
115  UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER];
116  __I uint32_t Reserved20[32];
117  __IO uint32_t USBHS_CTRL;
118  __I uint32_t USBHS_SR;
119  __O uint32_t USBHS_SCR;
120  __O uint32_t USBHS_SFR;
121 } Usbhs;
122 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
123 /* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */
124 #define USBHS_DEVCTRL_UADD_Pos 0
125 #define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos)
126 #define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos)))
127 #define USBHS_DEVCTRL_ADDEN (0x1u << 7)
128 #define USBHS_DEVCTRL_DETACH (0x1u << 8)
129 #define USBHS_DEVCTRL_RMWKUP (0x1u << 9)
130 #define USBHS_DEVCTRL_SPDCONF_Pos 10
131 #define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos)
132 #define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos)))
133 #define USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10)
134 #define USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10)
135 #define USBHS_DEVCTRL_LS (0x1u << 12)
136 #define USBHS_DEVCTRL_TSTJ (0x1u << 13)
137 #define USBHS_DEVCTRL_TSTK (0x1u << 14)
138 #define USBHS_DEVCTRL_TSTPCKT (0x1u << 15)
139 #define USBHS_DEVCTRL_OPMODE2 (0x1u << 16)
140 /* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */
141 #define USBHS_DEVISR_SUSP (0x1u << 0)
142 #define USBHS_DEVISR_MSOF (0x1u << 1)
143 #define USBHS_DEVISR_SOF (0x1u << 2)
144 #define USBHS_DEVISR_EORST (0x1u << 3)
145 #define USBHS_DEVISR_WAKEUP (0x1u << 4)
146 #define USBHS_DEVISR_EORSM (0x1u << 5)
147 #define USBHS_DEVISR_UPRSM (0x1u << 6)
148 #define USBHS_DEVISR_PEP_0 (0x1u << 12)
149 #define USBHS_DEVISR_PEP_1 (0x1u << 13)
150 #define USBHS_DEVISR_PEP_2 (0x1u << 14)
151 #define USBHS_DEVISR_PEP_3 (0x1u << 15)
152 #define USBHS_DEVISR_PEP_4 (0x1u << 16)
153 #define USBHS_DEVISR_PEP_5 (0x1u << 17)
154 #define USBHS_DEVISR_PEP_6 (0x1u << 18)
155 #define USBHS_DEVISR_PEP_7 (0x1u << 19)
156 #define USBHS_DEVISR_PEP_8 (0x1u << 20)
157 #define USBHS_DEVISR_PEP_9 (0x1u << 21)
158 #define USBHS_DEVISR_PEP_10 (0x1u << 22)
159 #define USBHS_DEVISR_PEP_11 (0x1u << 23)
160 #define USBHS_DEVISR_DMA_1 (0x1u << 25)
161 #define USBHS_DEVISR_DMA_2 (0x1u << 26)
162 #define USBHS_DEVISR_DMA_3 (0x1u << 27)
163 #define USBHS_DEVISR_DMA_4 (0x1u << 28)
164 #define USBHS_DEVISR_DMA_5 (0x1u << 29)
165 #define USBHS_DEVISR_DMA_6 (0x1u << 30)
166 #define USBHS_DEVISR_DMA_7 (0x1u << 31)
167 /* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */
168 #define USBHS_DEVICR_SUSPC (0x1u << 0)
169 #define USBHS_DEVICR_MSOFC (0x1u << 1)
170 #define USBHS_DEVICR_SOFC (0x1u << 2)
171 #define USBHS_DEVICR_EORSTC (0x1u << 3)
172 #define USBHS_DEVICR_WAKEUPC (0x1u << 4)
173 #define USBHS_DEVICR_EORSMC (0x1u << 5)
174 #define USBHS_DEVICR_UPRSMC (0x1u << 6)
175 /* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */
176 #define USBHS_DEVIFR_SUSPS (0x1u << 0)
177 #define USBHS_DEVIFR_MSOFS (0x1u << 1)
178 #define USBHS_DEVIFR_SOFS (0x1u << 2)
179 #define USBHS_DEVIFR_EORSTS (0x1u << 3)
180 #define USBHS_DEVIFR_WAKEUPS (0x1u << 4)
181 #define USBHS_DEVIFR_EORSMS (0x1u << 5)
182 #define USBHS_DEVIFR_UPRSMS (0x1u << 6)
183 #define USBHS_DEVIFR_DMA_1 (0x1u << 25)
184 #define USBHS_DEVIFR_DMA_2 (0x1u << 26)
185 #define USBHS_DEVIFR_DMA_3 (0x1u << 27)
186 #define USBHS_DEVIFR_DMA_4 (0x1u << 28)
187 #define USBHS_DEVIFR_DMA_5 (0x1u << 29)
188 #define USBHS_DEVIFR_DMA_6 (0x1u << 30)
189 #define USBHS_DEVIFR_DMA_7 (0x1u << 31)
190 /* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */
191 #define USBHS_DEVIMR_SUSPE (0x1u << 0)
192 #define USBHS_DEVIMR_MSOFE (0x1u << 1)
193 #define USBHS_DEVIMR_SOFE (0x1u << 2)
194 #define USBHS_DEVIMR_EORSTE (0x1u << 3)
195 #define USBHS_DEVIMR_WAKEUPE (0x1u << 4)
196 #define USBHS_DEVIMR_EORSME (0x1u << 5)
197 #define USBHS_DEVIMR_UPRSME (0x1u << 6)
198 #define USBHS_DEVIMR_PEP_0 (0x1u << 12)
199 #define USBHS_DEVIMR_PEP_1 (0x1u << 13)
200 #define USBHS_DEVIMR_PEP_2 (0x1u << 14)
201 #define USBHS_DEVIMR_PEP_3 (0x1u << 15)
202 #define USBHS_DEVIMR_PEP_4 (0x1u << 16)
203 #define USBHS_DEVIMR_PEP_5 (0x1u << 17)
204 #define USBHS_DEVIMR_PEP_6 (0x1u << 18)
205 #define USBHS_DEVIMR_PEP_7 (0x1u << 19)
206 #define USBHS_DEVIMR_PEP_8 (0x1u << 20)
207 #define USBHS_DEVIMR_PEP_9 (0x1u << 21)
208 #define USBHS_DEVIMR_PEP_10 (0x1u << 22)
209 #define USBHS_DEVIMR_PEP_11 (0x1u << 23)
210 #define USBHS_DEVIMR_DMA_1 (0x1u << 25)
211 #define USBHS_DEVIMR_DMA_2 (0x1u << 26)
212 #define USBHS_DEVIMR_DMA_3 (0x1u << 27)
213 #define USBHS_DEVIMR_DMA_4 (0x1u << 28)
214 #define USBHS_DEVIMR_DMA_5 (0x1u << 29)
215 #define USBHS_DEVIMR_DMA_6 (0x1u << 30)
216 #define USBHS_DEVIMR_DMA_7 (0x1u << 31)
217 /* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */
218 #define USBHS_DEVIDR_SUSPEC (0x1u << 0)
219 #define USBHS_DEVIDR_MSOFEC (0x1u << 1)
220 #define USBHS_DEVIDR_SOFEC (0x1u << 2)
221 #define USBHS_DEVIDR_EORSTEC (0x1u << 3)
222 #define USBHS_DEVIDR_WAKEUPEC (0x1u << 4)
223 #define USBHS_DEVIDR_EORSMEC (0x1u << 5)
224 #define USBHS_DEVIDR_UPRSMEC (0x1u << 6)
225 #define USBHS_DEVIDR_PEP_0 (0x1u << 12)
226 #define USBHS_DEVIDR_PEP_1 (0x1u << 13)
227 #define USBHS_DEVIDR_PEP_2 (0x1u << 14)
228 #define USBHS_DEVIDR_PEP_3 (0x1u << 15)
229 #define USBHS_DEVIDR_PEP_4 (0x1u << 16)
230 #define USBHS_DEVIDR_PEP_5 (0x1u << 17)
231 #define USBHS_DEVIDR_PEP_6 (0x1u << 18)
232 #define USBHS_DEVIDR_PEP_7 (0x1u << 19)
233 #define USBHS_DEVIDR_PEP_8 (0x1u << 20)
234 #define USBHS_DEVIDR_PEP_9 (0x1u << 21)
235 #define USBHS_DEVIDR_PEP_10 (0x1u << 22)
236 #define USBHS_DEVIDR_PEP_11 (0x1u << 23)
237 #define USBHS_DEVIDR_DMA_1 (0x1u << 25)
238 #define USBHS_DEVIDR_DMA_2 (0x1u << 26)
239 #define USBHS_DEVIDR_DMA_3 (0x1u << 27)
240 #define USBHS_DEVIDR_DMA_4 (0x1u << 28)
241 #define USBHS_DEVIDR_DMA_5 (0x1u << 29)
242 #define USBHS_DEVIDR_DMA_6 (0x1u << 30)
243 #define USBHS_DEVIDR_DMA_7 (0x1u << 31)
244 /* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */
245 #define USBHS_DEVIER_SUSPES (0x1u << 0)
246 #define USBHS_DEVIER_MSOFES (0x1u << 1)
247 #define USBHS_DEVIER_SOFES (0x1u << 2)
248 #define USBHS_DEVIER_EORSTES (0x1u << 3)
249 #define USBHS_DEVIER_WAKEUPES (0x1u << 4)
250 #define USBHS_DEVIER_EORSMES (0x1u << 5)
251 #define USBHS_DEVIER_UPRSMES (0x1u << 6)
252 #define USBHS_DEVIER_PEP_0 (0x1u << 12)
253 #define USBHS_DEVIER_PEP_1 (0x1u << 13)
254 #define USBHS_DEVIER_PEP_2 (0x1u << 14)
255 #define USBHS_DEVIER_PEP_3 (0x1u << 15)
256 #define USBHS_DEVIER_PEP_4 (0x1u << 16)
257 #define USBHS_DEVIER_PEP_5 (0x1u << 17)
258 #define USBHS_DEVIER_PEP_6 (0x1u << 18)
259 #define USBHS_DEVIER_PEP_7 (0x1u << 19)
260 #define USBHS_DEVIER_PEP_8 (0x1u << 20)
261 #define USBHS_DEVIER_PEP_9 (0x1u << 21)
262 #define USBHS_DEVIER_PEP_10 (0x1u << 22)
263 #define USBHS_DEVIER_PEP_11 (0x1u << 23)
264 #define USBHS_DEVIER_DMA_1 (0x1u << 25)
265 #define USBHS_DEVIER_DMA_2 (0x1u << 26)
266 #define USBHS_DEVIER_DMA_3 (0x1u << 27)
267 #define USBHS_DEVIER_DMA_4 (0x1u << 28)
268 #define USBHS_DEVIER_DMA_5 (0x1u << 29)
269 #define USBHS_DEVIER_DMA_6 (0x1u << 30)
270 #define USBHS_DEVIER_DMA_7 (0x1u << 31)
271 /* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */
272 #define USBHS_DEVEPT_EPEN0 (0x1u << 0)
273 #define USBHS_DEVEPT_EPEN1 (0x1u << 1)
274 #define USBHS_DEVEPT_EPEN2 (0x1u << 2)
275 #define USBHS_DEVEPT_EPEN3 (0x1u << 3)
276 #define USBHS_DEVEPT_EPEN4 (0x1u << 4)
277 #define USBHS_DEVEPT_EPEN5 (0x1u << 5)
278 #define USBHS_DEVEPT_EPEN6 (0x1u << 6)
279 #define USBHS_DEVEPT_EPEN7 (0x1u << 7)
280 #define USBHS_DEVEPT_EPEN8 (0x1u << 8)
281 #define USBHS_DEVEPT_EPRST0 (0x1u << 16)
282 #define USBHS_DEVEPT_EPRST1 (0x1u << 17)
283 #define USBHS_DEVEPT_EPRST2 (0x1u << 18)
284 #define USBHS_DEVEPT_EPRST3 (0x1u << 19)
285 #define USBHS_DEVEPT_EPRST4 (0x1u << 20)
286 #define USBHS_DEVEPT_EPRST5 (0x1u << 21)
287 #define USBHS_DEVEPT_EPRST6 (0x1u << 22)
288 #define USBHS_DEVEPT_EPRST7 (0x1u << 23)
289 #define USBHS_DEVEPT_EPRST8 (0x1u << 24)
290 /* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */
291 #define USBHS_DEVFNUM_MFNUM_Pos 0
292 #define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos)
293 #define USBHS_DEVFNUM_FNUM_Pos 3
294 #define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos)
295 #define USBHS_DEVFNUM_FNCERR (0x1u << 15)
296 /* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */
297 #define USBHS_DEVEPTCFG_ALLOC (0x1u << 1)
298 #define USBHS_DEVEPTCFG_EPBK_Pos 2
299 #define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos)
300 #define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos)))
301 #define USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2)
302 #define USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2)
303 #define USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2)
304 #define USBHS_DEVEPTCFG_EPSIZE_Pos 4
305 #define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos)
306 #define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos)))
307 #define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4)
308 #define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4)
309 #define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4)
310 #define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4)
311 #define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4)
312 #define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4)
313 #define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4)
314 #define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4)
315 #define USBHS_DEVEPTCFG_EPDIR (0x1u << 8)
316 #define USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8)
317 #define USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8)
318 #define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9)
319 #define USBHS_DEVEPTCFG_EPTYPE_Pos 11
320 #define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos)
321 #define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos)))
322 #define USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11)
323 #define USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11)
324 #define USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11)
325 #define USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11)
326 #define USBHS_DEVEPTCFG_NBTRANS_Pos 13
327 #define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos)
328 #define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos)))
329 #define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13)
330 #define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13)
331 #define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13)
332 #define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13)
333 /* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */
334 #define USBHS_DEVEPTISR_TXINI (0x1u << 0)
335 #define USBHS_DEVEPTISR_RXOUTI (0x1u << 1)
336 #define USBHS_DEVEPTISR_RXSTPI (0x1u << 2)
337 #define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3)
338 #define USBHS_DEVEPTISR_NAKINI (0x1u << 4)
339 #define USBHS_DEVEPTISR_OVERFI (0x1u << 5)
340 #define USBHS_DEVEPTISR_STALLEDI (0x1u << 6)
341 #define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7)
342 #define USBHS_DEVEPTISR_DTSEQ_Pos 8
343 #define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos)
344 #define USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8)
345 #define USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8)
346 #define USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8)
347 #define USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8)
348 #define USBHS_DEVEPTISR_NBUSYBK_Pos 12
349 #define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos)
350 #define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12)
351 #define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12)
352 #define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12)
353 #define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12)
354 #define USBHS_DEVEPTISR_CURRBK_Pos 14
355 #define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos)
356 #define USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14)
357 #define USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14)
358 #define USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14)
359 #define USBHS_DEVEPTISR_RWALL (0x1u << 16)
360 #define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17)
361 #define USBHS_DEVEPTISR_CFGOK (0x1u << 18)
362 #define USBHS_DEVEPTISR_BYCT_Pos 20
363 #define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos)
364 #define USBHS_DEVEPTISR_UNDERFI (0x1u << 2)
365 #define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3)
366 #define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4)
367 #define USBHS_DEVEPTISR_CRCERRI (0x1u << 6)
368 #define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10)
369 /* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */
370 #define USBHS_DEVEPTICR_TXINIC (0x1u << 0)
371 #define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1)
372 #define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2)
373 #define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3)
374 #define USBHS_DEVEPTICR_NAKINIC (0x1u << 4)
375 #define USBHS_DEVEPTICR_OVERFIC (0x1u << 5)
376 #define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6)
377 #define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7)
378 #define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2)
379 #define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3)
380 #define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4)
381 #define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6)
382 /* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */
383 #define USBHS_DEVEPTIFR_TXINIS (0x1u << 0)
384 #define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1)
385 #define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2)
386 #define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3)
387 #define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4)
388 #define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5)
389 #define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6)
390 #define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7)
391 #define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12)
392 #define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2)
393 #define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3)
394 #define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4)
395 #define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6)
396 /* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */
397 #define USBHS_DEVEPTIMR_TXINE (0x1u << 0)
398 #define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1)
399 #define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2)
400 #define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3)
401 #define USBHS_DEVEPTIMR_NAKINE (0x1u << 4)
402 #define USBHS_DEVEPTIMR_OVERFE (0x1u << 5)
403 #define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6)
404 #define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7)
405 #define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12)
406 #define USBHS_DEVEPTIMR_KILLBK (0x1u << 13)
407 #define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14)
408 #define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16)
409 #define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17)
410 #define USBHS_DEVEPTIMR_RSTDT (0x1u << 18)
411 #define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19)
412 #define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2)
413 #define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3)
414 #define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4)
415 #define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6)
416 #define USBHS_DEVEPTIMR_MDATAE (0x1u << 8)
417 #define USBHS_DEVEPTIMR_DATAXE (0x1u << 9)
418 #define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10)
419 /* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */
420 #define USBHS_DEVEPTIER_TXINES (0x1u << 0)
421 #define USBHS_DEVEPTIER_RXOUTES (0x1u << 1)
422 #define USBHS_DEVEPTIER_RXSTPES (0x1u << 2)
423 #define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3)
424 #define USBHS_DEVEPTIER_NAKINES (0x1u << 4)
425 #define USBHS_DEVEPTIER_OVERFES (0x1u << 5)
426 #define USBHS_DEVEPTIER_STALLEDES (0x1u << 6)
427 #define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7)
428 #define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12)
429 #define USBHS_DEVEPTIER_KILLBKS (0x1u << 13)
430 #define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14)
431 #define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16)
432 #define USBHS_DEVEPTIER_NYETDISS (0x1u << 17)
433 #define USBHS_DEVEPTIER_RSTDTS (0x1u << 18)
434 #define USBHS_DEVEPTIER_STALLRQS (0x1u << 19)
435 #define USBHS_DEVEPTIER_UNDERFES (0x1u << 2)
436 #define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3)
437 #define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4)
438 #define USBHS_DEVEPTIER_CRCERRES (0x1u << 6)
439 #define USBHS_DEVEPTIER_MDATAES (0x1u << 8)
440 #define USBHS_DEVEPTIER_DATAXES (0x1u << 9)
441 #define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10)
442 /* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */
443 #define USBHS_DEVEPTIDR_TXINEC (0x1u << 0)
444 #define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1)
445 #define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2)
446 #define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3)
447 #define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4)
448 #define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5)
449 #define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6)
450 #define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7)
451 #define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12)
452 #define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14)
453 #define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16)
454 #define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17)
455 #define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19)
456 #define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2)
457 #define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3)
458 #define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4)
459 #define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6)
460 #define USBHS_DEVEPTIDR_MDATEC (0x1u << 8)
461 #define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9)
462 #define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10)
463 /* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */
464 #define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0
465 #define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)
466 #define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)))
467 /* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */
468 #define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0
469 #define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)
470 #define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)))
471 /* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */
472 #define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0)
473 #define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1)
474 #define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2)
475 #define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3)
476 #define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4)
477 #define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5)
478 #define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6)
479 #define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7)
480 #define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16
481 #define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)
482 #define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)))
483 /* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */
484 #define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0)
485 #define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1)
486 #define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4)
487 #define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5)
488 #define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6)
489 #define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16
490 #define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)
491 #define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)))
492 /* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */
493 #define USBHS_HSTCTRL_SOFE (0x1u << 8)
494 #define USBHS_HSTCTRL_RESET (0x1u << 9)
495 #define USBHS_HSTCTRL_RESUME (0x1u << 10)
496 #define USBHS_HSTCTRL_SPDCONF_Pos 12
497 #define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos)
498 #define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos)))
499 #define USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12)
500 #define USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12)
501 /* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */
502 #define USBHS_HSTISR_DCONNI (0x1u << 0)
503 #define USBHS_HSTISR_DDISCI (0x1u << 1)
504 #define USBHS_HSTISR_RSTI (0x1u << 2)
505 #define USBHS_HSTISR_RSMEDI (0x1u << 3)
506 #define USBHS_HSTISR_RXRSMI (0x1u << 4)
507 #define USBHS_HSTISR_HSOFI (0x1u << 5)
508 #define USBHS_HSTISR_HWUPI (0x1u << 6)
509 #define USBHS_HSTISR_PEP_0 (0x1u << 8)
510 #define USBHS_HSTISR_PEP_1 (0x1u << 9)
511 #define USBHS_HSTISR_PEP_2 (0x1u << 10)
512 #define USBHS_HSTISR_PEP_3 (0x1u << 11)
513 #define USBHS_HSTISR_PEP_4 (0x1u << 12)
514 #define USBHS_HSTISR_PEP_5 (0x1u << 13)
515 #define USBHS_HSTISR_PEP_6 (0x1u << 14)
516 #define USBHS_HSTISR_PEP_7 (0x1u << 15)
517 #define USBHS_HSTISR_PEP_8 (0x1u << 16)
518 #define USBHS_HSTISR_PEP_9 (0x1u << 17)
519 #define USBHS_HSTISR_PEP_10 (0x1u << 18)
520 #define USBHS_HSTISR_PEP_11 (0x1u << 19)
521 #define USBHS_HSTISR_DMA_1 (0x1u << 25)
522 #define USBHS_HSTISR_DMA_2 (0x1u << 26)
523 #define USBHS_HSTISR_DMA_3 (0x1u << 27)
524 #define USBHS_HSTISR_DMA_4 (0x1u << 28)
525 #define USBHS_HSTISR_DMA_5 (0x1u << 29)
526 #define USBHS_HSTISR_DMA_6 (0x1u << 30)
527 #define USBHS_HSTISR_DMA_7 (0x1u << 31)
528 /* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */
529 #define USBHS_HSTICR_DCONNIC (0x1u << 0)
530 #define USBHS_HSTICR_DDISCIC (0x1u << 1)
531 #define USBHS_HSTICR_RSTIC (0x1u << 2)
532 #define USBHS_HSTICR_RSMEDIC (0x1u << 3)
533 #define USBHS_HSTICR_RXRSMIC (0x1u << 4)
534 #define USBHS_HSTICR_HSOFIC (0x1u << 5)
535 #define USBHS_HSTICR_HWUPIC (0x1u << 6)
536 /* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */
537 #define USBHS_HSTIFR_DCONNIS (0x1u << 0)
538 #define USBHS_HSTIFR_DDISCIS (0x1u << 1)
539 #define USBHS_HSTIFR_RSTIS (0x1u << 2)
540 #define USBHS_HSTIFR_RSMEDIS (0x1u << 3)
541 #define USBHS_HSTIFR_RXRSMIS (0x1u << 4)
542 #define USBHS_HSTIFR_HSOFIS (0x1u << 5)
543 #define USBHS_HSTIFR_HWUPIS (0x1u << 6)
544 #define USBHS_HSTIFR_DMA_1 (0x1u << 25)
545 #define USBHS_HSTIFR_DMA_2 (0x1u << 26)
546 #define USBHS_HSTIFR_DMA_3 (0x1u << 27)
547 #define USBHS_HSTIFR_DMA_4 (0x1u << 28)
548 #define USBHS_HSTIFR_DMA_5 (0x1u << 29)
549 #define USBHS_HSTIFR_DMA_6 (0x1u << 30)
550 #define USBHS_HSTIFR_DMA_7 (0x1u << 31)
551 /* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */
552 #define USBHS_HSTIMR_DCONNIE (0x1u << 0)
553 #define USBHS_HSTIMR_DDISCIE (0x1u << 1)
554 #define USBHS_HSTIMR_RSTIE (0x1u << 2)
555 #define USBHS_HSTIMR_RSMEDIE (0x1u << 3)
556 #define USBHS_HSTIMR_RXRSMIE (0x1u << 4)
557 #define USBHS_HSTIMR_HSOFIE (0x1u << 5)
558 #define USBHS_HSTIMR_HWUPIE (0x1u << 6)
559 #define USBHS_HSTIMR_PEP_0 (0x1u << 8)
560 #define USBHS_HSTIMR_PEP_1 (0x1u << 9)
561 #define USBHS_HSTIMR_PEP_2 (0x1u << 10)
562 #define USBHS_HSTIMR_PEP_3 (0x1u << 11)
563 #define USBHS_HSTIMR_PEP_4 (0x1u << 12)
564 #define USBHS_HSTIMR_PEP_5 (0x1u << 13)
565 #define USBHS_HSTIMR_PEP_6 (0x1u << 14)
566 #define USBHS_HSTIMR_PEP_7 (0x1u << 15)
567 #define USBHS_HSTIMR_PEP_8 (0x1u << 16)
568 #define USBHS_HSTIMR_PEP_9 (0x1u << 17)
569 #define USBHS_HSTIMR_PEP_10 (0x1u << 18)
570 #define USBHS_HSTIMR_PEP_11 (0x1u << 19)
571 #define USBHS_HSTIMR_DMA_1 (0x1u << 25)
572 #define USBHS_HSTIMR_DMA_2 (0x1u << 26)
573 #define USBHS_HSTIMR_DMA_3 (0x1u << 27)
574 #define USBHS_HSTIMR_DMA_4 (0x1u << 28)
575 #define USBHS_HSTIMR_DMA_5 (0x1u << 29)
576 #define USBHS_HSTIMR_DMA_6 (0x1u << 30)
577 #define USBHS_HSTIMR_DMA_7 (0x1u << 31)
578 /* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */
579 #define USBHS_HSTIDR_DCONNIEC (0x1u << 0)
580 #define USBHS_HSTIDR_DDISCIEC (0x1u << 1)
581 #define USBHS_HSTIDR_RSTIEC (0x1u << 2)
582 #define USBHS_HSTIDR_RSMEDIEC (0x1u << 3)
583 #define USBHS_HSTIDR_RXRSMIEC (0x1u << 4)
584 #define USBHS_HSTIDR_HSOFIEC (0x1u << 5)
585 #define USBHS_HSTIDR_HWUPIEC (0x1u << 6)
586 #define USBHS_HSTIDR_PEP_0 (0x1u << 8)
587 #define USBHS_HSTIDR_PEP_1 (0x1u << 9)
588 #define USBHS_HSTIDR_PEP_2 (0x1u << 10)
589 #define USBHS_HSTIDR_PEP_3 (0x1u << 11)
590 #define USBHS_HSTIDR_PEP_4 (0x1u << 12)
591 #define USBHS_HSTIDR_PEP_5 (0x1u << 13)
592 #define USBHS_HSTIDR_PEP_6 (0x1u << 14)
593 #define USBHS_HSTIDR_PEP_7 (0x1u << 15)
594 #define USBHS_HSTIDR_PEP_8 (0x1u << 16)
595 #define USBHS_HSTIDR_PEP_9 (0x1u << 17)
596 #define USBHS_HSTIDR_PEP_10 (0x1u << 18)
597 #define USBHS_HSTIDR_PEP_11 (0x1u << 19)
598 #define USBHS_HSTIDR_DMA_1 (0x1u << 25)
599 #define USBHS_HSTIDR_DMA_2 (0x1u << 26)
600 #define USBHS_HSTIDR_DMA_3 (0x1u << 27)
601 #define USBHS_HSTIDR_DMA_4 (0x1u << 28)
602 #define USBHS_HSTIDR_DMA_5 (0x1u << 29)
603 #define USBHS_HSTIDR_DMA_6 (0x1u << 30)
604 #define USBHS_HSTIDR_DMA_7 (0x1u << 31)
605 /* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */
606 #define USBHS_HSTIER_DCONNIES (0x1u << 0)
607 #define USBHS_HSTIER_DDISCIES (0x1u << 1)
608 #define USBHS_HSTIER_RSTIES (0x1u << 2)
609 #define USBHS_HSTIER_RSMEDIES (0x1u << 3)
610 #define USBHS_HSTIER_RXRSMIES (0x1u << 4)
611 #define USBHS_HSTIER_HSOFIES (0x1u << 5)
612 #define USBHS_HSTIER_HWUPIES (0x1u << 6)
613 #define USBHS_HSTIER_PEP_0 (0x1u << 8)
614 #define USBHS_HSTIER_PEP_1 (0x1u << 9)
615 #define USBHS_HSTIER_PEP_2 (0x1u << 10)
616 #define USBHS_HSTIER_PEP_3 (0x1u << 11)
617 #define USBHS_HSTIER_PEP_4 (0x1u << 12)
618 #define USBHS_HSTIER_PEP_5 (0x1u << 13)
619 #define USBHS_HSTIER_PEP_6 (0x1u << 14)
620 #define USBHS_HSTIER_PEP_7 (0x1u << 15)
621 #define USBHS_HSTIER_PEP_8 (0x1u << 16)
622 #define USBHS_HSTIER_PEP_9 (0x1u << 17)
623 #define USBHS_HSTIER_PEP_10 (0x1u << 18)
624 #define USBHS_HSTIER_PEP_11 (0x1u << 19)
625 #define USBHS_HSTIER_DMA_1 (0x1u << 25)
626 #define USBHS_HSTIER_DMA_2 (0x1u << 26)
627 #define USBHS_HSTIER_DMA_3 (0x1u << 27)
628 #define USBHS_HSTIER_DMA_4 (0x1u << 28)
629 #define USBHS_HSTIER_DMA_5 (0x1u << 29)
630 #define USBHS_HSTIER_DMA_6 (0x1u << 30)
631 #define USBHS_HSTIER_DMA_7 (0x1u << 31)
632 /* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */
633 #define USBHS_HSTPIP_PEN0 (0x1u << 0)
634 #define USBHS_HSTPIP_PEN1 (0x1u << 1)
635 #define USBHS_HSTPIP_PEN2 (0x1u << 2)
636 #define USBHS_HSTPIP_PEN3 (0x1u << 3)
637 #define USBHS_HSTPIP_PEN4 (0x1u << 4)
638 #define USBHS_HSTPIP_PEN5 (0x1u << 5)
639 #define USBHS_HSTPIP_PEN6 (0x1u << 6)
640 #define USBHS_HSTPIP_PEN7 (0x1u << 7)
641 #define USBHS_HSTPIP_PEN8 (0x1u << 8)
642 #define USBHS_HSTPIP_PRST0 (0x1u << 16)
643 #define USBHS_HSTPIP_PRST1 (0x1u << 17)
644 #define USBHS_HSTPIP_PRST2 (0x1u << 18)
645 #define USBHS_HSTPIP_PRST3 (0x1u << 19)
646 #define USBHS_HSTPIP_PRST4 (0x1u << 20)
647 #define USBHS_HSTPIP_PRST5 (0x1u << 21)
648 #define USBHS_HSTPIP_PRST6 (0x1u << 22)
649 #define USBHS_HSTPIP_PRST7 (0x1u << 23)
650 #define USBHS_HSTPIP_PRST8 (0x1u << 24)
651 /* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */
652 #define USBHS_HSTFNUM_MFNUM_Pos 0
653 #define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos)
654 #define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos)))
655 #define USBHS_HSTFNUM_FNUM_Pos 3
656 #define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos)
657 #define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos)))
658 #define USBHS_HSTFNUM_FLENHIGH_Pos 16
659 #define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos)
660 #define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos)))
661 /* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */
662 #define USBHS_HSTADDR1_HSTADDRP0_Pos 0
663 #define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos)
664 #define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos)))
665 #define USBHS_HSTADDR1_HSTADDRP1_Pos 8
666 #define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos)
667 #define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos)))
668 #define USBHS_HSTADDR1_HSTADDRP2_Pos 16
669 #define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos)
670 #define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos)))
671 #define USBHS_HSTADDR1_HSTADDRP3_Pos 24
672 #define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos)
673 #define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos)))
674 /* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */
675 #define USBHS_HSTADDR2_HSTADDRP4_Pos 0
676 #define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos)
677 #define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos)))
678 #define USBHS_HSTADDR2_HSTADDRP5_Pos 8
679 #define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos)
680 #define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos)))
681 #define USBHS_HSTADDR2_HSTADDRP6_Pos 16
682 #define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos)
683 #define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos)))
684 #define USBHS_HSTADDR2_HSTADDRP7_Pos 24
685 #define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos)
686 #define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos)))
687 /* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */
688 #define USBHS_HSTADDR3_HSTADDRP8_Pos 0
689 #define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos)
690 #define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos)))
691 #define USBHS_HSTADDR3_HSTADDRP9_Pos 8
692 #define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos)
693 #define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos)))
694 /* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */
695 #define USBHS_HSTPIPCFG_ALLOC (0x1u << 1)
696 #define USBHS_HSTPIPCFG_PBK_Pos 2
697 #define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos)
698 #define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos)))
699 #define USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2)
700 #define USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2)
701 #define USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2)
702 #define USBHS_HSTPIPCFG_PSIZE_Pos 4
703 #define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos)
704 #define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos)))
705 #define USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4)
706 #define USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4)
707 #define USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4)
708 #define USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4)
709 #define USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4)
710 #define USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4)
711 #define USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4)
712 #define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4)
713 #define USBHS_HSTPIPCFG_PTOKEN_Pos 8
714 #define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos)
715 #define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos)))
716 #define USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8)
717 #define USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8)
718 #define USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8)
719 #define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10)
720 #define USBHS_HSTPIPCFG_PTYPE_Pos 12
721 #define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos)
722 #define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos)))
723 #define USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12)
724 #define USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12)
725 #define USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12)
726 #define USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12)
727 #define USBHS_HSTPIPCFG_PEPNUM_Pos 16
728 #define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos)
729 #define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos)))
730 #define USBHS_HSTPIPCFG_INTFRQ_Pos 24
731 #define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos)
732 #define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos)))
733 #define USBHS_HSTPIPCFG_PINGEN (0x1u << 20)
734 #define USBHS_HSTPIPCFG_BINTERVAL_Pos 24
735 #define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos)
736 #define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos)))
737 /* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */
738 #define USBHS_HSTPIPISR_RXINI (0x1u << 0)
739 #define USBHS_HSTPIPISR_TXOUTI (0x1u << 1)
740 #define USBHS_HSTPIPISR_TXSTPI (0x1u << 2)
741 #define USBHS_HSTPIPISR_PERRI (0x1u << 3)
742 #define USBHS_HSTPIPISR_NAKEDI (0x1u << 4)
743 #define USBHS_HSTPIPISR_OVERFI (0x1u << 5)
744 #define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6)
745 #define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7)
746 #define USBHS_HSTPIPISR_DTSEQ_Pos 8
747 #define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos)
748 #define USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8)
749 #define USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8)
750 #define USBHS_HSTPIPISR_NBUSYBK_Pos 12
751 #define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos)
752 #define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12)
753 #define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12)
754 #define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12)
755 #define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12)
756 #define USBHS_HSTPIPISR_CURRBK_Pos 14
757 #define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos)
758 #define USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14)
759 #define USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14)
760 #define USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14)
761 #define USBHS_HSTPIPISR_RWALL (0x1u << 16)
762 #define USBHS_HSTPIPISR_CFGOK (0x1u << 18)
763 #define USBHS_HSTPIPISR_PBYCT_Pos 20
764 #define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos)
765 #define USBHS_HSTPIPISR_UNDERFI (0x1u << 2)
766 #define USBHS_HSTPIPISR_CRCERRI (0x1u << 6)
767 /* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */
768 #define USBHS_HSTPIPICR_RXINIC (0x1u << 0)
769 #define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1)
770 #define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2)
771 #define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4)
772 #define USBHS_HSTPIPICR_OVERFIC (0x1u << 5)
773 #define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6)
774 #define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7)
775 #define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2)
776 #define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6)
777 /* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */
778 #define USBHS_HSTPIPIFR_RXINIS (0x1u << 0)
779 #define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1)
780 #define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2)
781 #define USBHS_HSTPIPIFR_PERRIS (0x1u << 3)
782 #define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4)
783 #define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5)
784 #define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6)
785 #define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7)
786 #define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12)
787 #define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2)
788 #define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6)
789 /* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */
790 #define USBHS_HSTPIPIMR_RXINE (0x1u << 0)
791 #define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1)
792 #define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2)
793 #define USBHS_HSTPIPIMR_PERRE (0x1u << 3)
794 #define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4)
795 #define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5)
796 #define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6)
797 #define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7)
798 #define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12)
799 #define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14)
800 #define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16)
801 #define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17)
802 #define USBHS_HSTPIPIMR_RSTDT (0x1u << 18)
803 #define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2)
804 #define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6)
805 /* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */
806 #define USBHS_HSTPIPIER_RXINES (0x1u << 0)
807 #define USBHS_HSTPIPIER_TXOUTES (0x1u << 1)
808 #define USBHS_HSTPIPIER_TXSTPES (0x1u << 2)
809 #define USBHS_HSTPIPIER_PERRES (0x1u << 3)
810 #define USBHS_HSTPIPIER_NAKEDES (0x1u << 4)
811 #define USBHS_HSTPIPIER_OVERFIES (0x1u << 5)
812 #define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6)
813 #define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7)
814 #define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12)
815 #define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16)
816 #define USBHS_HSTPIPIER_PFREEZES (0x1u << 17)
817 #define USBHS_HSTPIPIER_RSTDTS (0x1u << 18)
818 #define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2)
819 #define USBHS_HSTPIPIER_CRCERRES (0x1u << 6)
820 /* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */
821 #define USBHS_HSTPIPIDR_RXINEC (0x1u << 0)
822 #define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1)
823 #define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2)
824 #define USBHS_HSTPIPIDR_PERREC (0x1u << 3)
825 #define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4)
826 #define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5)
827 #define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6)
828 #define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7)
829 #define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12)
830 #define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14)
831 #define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16)
832 #define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17)
833 #define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2)
834 #define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6)
835 /* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */
836 #define USBHS_HSTPIPINRQ_INRQ_Pos 0
837 #define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos)
838 #define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos)))
839 #define USBHS_HSTPIPINRQ_INMODE (0x1u << 8)
840 /* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */
841 #define USBHS_HSTPIPERR_DATATGL (0x1u << 0)
842 #define USBHS_HSTPIPERR_DATAPID (0x1u << 1)
843 #define USBHS_HSTPIPERR_PID (0x1u << 2)
844 #define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3)
845 #define USBHS_HSTPIPERR_CRC16 (0x1u << 4)
846 #define USBHS_HSTPIPERR_COUNTER_Pos 5
847 #define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos)
848 #define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos)))
849 /* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */
850 #define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0
851 #define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)
852 #define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)))
853 /* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */
854 #define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0
855 #define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)
856 #define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)))
857 /* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */
858 #define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0)
859 #define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1)
860 #define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2)
861 #define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3)
862 #define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4)
863 #define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5)
864 #define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6)
865 #define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7)
866 #define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16
867 #define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)
868 #define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)))
869 /* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */
870 #define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0)
871 #define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1)
872 #define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4)
873 #define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5)
874 #define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6)
875 #define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16
876 #define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)
877 #define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)))
878 /* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */
879 #define USBHS_CTRL_RDERRE (0x1u << 4)
880 #define USBHS_CTRL_VBUSHWC (0x1u << 8)
881 #define USBHS_CTRL_FRZCLK (0x1u << 14)
882 #define USBHS_CTRL_USBE (0x1u << 15)
883 #define USBHS_CTRL_UIMOD (0x1u << 25)
884 #define USBHS_CTRL_UIMOD_HOST (0x0u << 25)
885 #define USBHS_CTRL_UIMOD_DEVICE (0x1u << 25)
886 /* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */
887 #define USBHS_SR_RDERRI (0x1u << 4)
888 #define USBHS_SR_VBUSRQ (0x1u << 9)
889 #define USBHS_SR_SPEED_Pos 12
890 #define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos)
891 #define USBHS_SR_SPEED_FULL_SPEED (0x0u << 12)
892 #define USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12)
893 #define USBHS_SR_SPEED_LOW_SPEED (0x2u << 12)
894 #define USBHS_SR_CLKUSABLE (0x1u << 14)
895 /* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */
896 #define USBHS_SCR_RDERRIC (0x1u << 4)
897 #define USBHS_SCR_VBUSRQC (0x1u << 9)
898 /* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */
899 #define USBHS_SFR_RDERRIS (0x1u << 4)
900 #define USBHS_SFR_VBUSRQS (0x1u << 9)
903 
904 
905 #endif /* _SAMS70_USBHS_COMPONENT_ */
__IO
#define __IO
Definition: core_cm7.h:287
__O
#define __O
Definition: core_cm7.h:286
Usbhs
Definition: component_usbhs.h:57
UsbhsHstdma
UsbhsHstdma hardware registers.
Definition: component_usbhs.h:48
USBHSDEVDMA_NUMBER
#define USBHSDEVDMA_NUMBER
Usbhs hardware registers.
Definition: component_usbhs.h:55
__I
#define __I
Definition: core_cm7.h:284
UsbhsDevdma
UsbhsDevdma hardware registers.
Definition: component_usbhs.h:41
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