RTEMS  5.1
component_rswdt.h
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29 
30 #ifndef _SAME70_RSWDT_COMPONENT_
31 #define _SAME70_RSWDT_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  __O uint32_t RSWDT_CR;
43  __IO uint32_t RSWDT_MR;
44  __I uint32_t RSWDT_SR;
45 } Rswdt;
46 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
47 /* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */
48 #define RSWDT_CR_WDRSTT (0x1u << 0)
49 #define RSWDT_CR_KEY_Pos 24
50 #define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos)
51 #define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos)))
52 #define RSWDT_CR_KEY_PASSWD (0xC4u << 24)
53 /* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */
54 #define RSWDT_MR_WDV_Pos 0
55 #define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos)
56 #define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos)))
57 #define RSWDT_MR_WDFIEN (0x1u << 12)
58 #define RSWDT_MR_WDRSTEN (0x1u << 13)
59 #define RSWDT_MR_WDRPROC (0x1u << 14)
60 #define RSWDT_MR_WDDIS (0x1u << 15)
61 #define RSWDT_MR_ALLONES_Pos 16
62 #define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos)
63 #define RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos)))
64 #define RSWDT_MR_WDDBGHLT (0x1u << 28)
65 #define RSWDT_MR_WDIDLEHLT (0x1u << 29)
66 /* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */
67 #define RSWDT_SR_WDUNF (0x1u << 0)
70 
71 
72 #endif /* _SAME70_RSWDT_COMPONENT_ */
#define __IO
Definition: core_cm7.h:287
#define __O
Definition: core_cm7.h:286
__IO uint32_t RSWDT_MR
(Rswdt Offset: 0x04) Mode Register
Definition: component_rswdt.h:43
Rswdt hardware registers.
Definition: component_rswdt.h:41
__I uint32_t RSWDT_SR
(Rswdt Offset: 0x08) Status Register
Definition: component_rswdt.h:44
__O uint32_t RSWDT_CR
(Rswdt Offset: 0x00) Control Register
Definition: component_rswdt.h:42
#define __I
Definition: core_cm7.h:284