RTEMS  5.1
component_gmac.h
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2 /* Atmel Microcontroller Software Support */
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29 
30 #ifndef _SAME70_GMAC_COMPONENT_
31 #define _SAME70_GMAC_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  __IO uint32_t GMAC_SAB;
43  __IO uint32_t GMAC_SAT;
44 } GmacSa;
45 
47 typedef struct {
48  __IO uint32_t GMAC_ST2COM0;
49  __IO uint32_t GMAC_ST2COM1;
50 } GmacSt2Compare;
51 
53 #define GMACSA_NUMBER 4
54 #define GMACST2COMPARE_NUMBER 24
55 typedef struct {
56  __IO uint32_t GMAC_NCR;
57  __IO uint32_t GMAC_NCFGR;
58  __I uint32_t GMAC_NSR;
59  __IO uint32_t GMAC_UR;
60  __IO uint32_t GMAC_DCFGR;
61  __IO uint32_t GMAC_TSR;
62  __IO uint32_t GMAC_RBQB;
63  __IO uint32_t GMAC_TBQB;
64  __IO uint32_t GMAC_RSR;
65  __I uint32_t GMAC_ISR;
66  __O uint32_t GMAC_IER;
67  __O uint32_t GMAC_IDR;
68  __IO uint32_t GMAC_IMR;
69  __IO uint32_t GMAC_MAN;
70  __I uint32_t GMAC_RPQ;
71  __IO uint32_t GMAC_TPQ;
72  __IO uint32_t GMAC_TPSF;
73  __IO uint32_t GMAC_RPSF;
74  __IO uint32_t GMAC_RJFML;
75  __I uint32_t Reserved1[13];
76  __IO uint32_t GMAC_HRB;
77  __IO uint32_t GMAC_HRT;
78  GmacSa GMAC_SA[GMACSA_NUMBER];
79  __IO uint32_t GMAC_TIDM1;
80  __IO uint32_t GMAC_TIDM2;
81  __IO uint32_t GMAC_TIDM3;
82  __IO uint32_t GMAC_TIDM4;
83  __IO uint32_t GMAC_WOL;
84  __IO uint32_t GMAC_IPGS;
85  __IO uint32_t GMAC_SVLAN;
86  __IO uint32_t GMAC_TPFCP;
87  __IO uint32_t GMAC_SAMB1;
88  __IO uint32_t GMAC_SAMT1;
89  __I uint32_t Reserved2[3];
90  __IO uint32_t GMAC_NSC;
91  __IO uint32_t GMAC_SCL;
92  __IO uint32_t GMAC_SCH;
93  __I uint32_t GMAC_EFTSH;
94  __I uint32_t GMAC_EFRSH;
95  __I uint32_t GMAC_PEFTSH;
96  __I uint32_t GMAC_PEFRSH;
97  __I uint32_t Reserved3[2];
98  __I uint32_t GMAC_OTLO;
99  __I uint32_t GMAC_OTHI;
100  __I uint32_t GMAC_FT;
101  __I uint32_t GMAC_BCFT;
102  __I uint32_t GMAC_MFT;
103  __I uint32_t GMAC_PFT;
104  __I uint32_t GMAC_BFT64;
105  __I uint32_t GMAC_TBFT127;
106  __I uint32_t GMAC_TBFT255;
107  __I uint32_t GMAC_TBFT511;
108  __I uint32_t GMAC_TBFT1023;
109  __I uint32_t GMAC_TBFT1518;
110  __I uint32_t GMAC_GTBFT1518;
111  __I uint32_t GMAC_TUR;
112  __I uint32_t GMAC_SCF;
113  __I uint32_t GMAC_MCF;
114  __I uint32_t GMAC_EC;
115  __I uint32_t GMAC_LC;
116  __I uint32_t GMAC_DTF;
117  __I uint32_t GMAC_CSE;
118  __I uint32_t GMAC_ORLO;
119  __I uint32_t GMAC_ORHI;
120  __I uint32_t GMAC_FR;
121  __I uint32_t GMAC_BCFR;
122  __I uint32_t GMAC_MFR;
123  __I uint32_t GMAC_PFR;
124  __I uint32_t GMAC_BFR64;
125  __I uint32_t GMAC_TBFR127;
126  __I uint32_t GMAC_TBFR255;
127  __I uint32_t GMAC_TBFR511;
128  __I uint32_t GMAC_TBFR1023;
129  __I uint32_t GMAC_TBFR1518;
130  __I uint32_t GMAC_TMXBFR;
131  __I uint32_t GMAC_UFR;
132  __I uint32_t GMAC_OFR;
133  __I uint32_t GMAC_JR;
134  __I uint32_t GMAC_FCSE;
135  __I uint32_t GMAC_LFFE;
136  __I uint32_t GMAC_RSE;
137  __I uint32_t GMAC_AE;
138  __I uint32_t GMAC_RRE;
139  __I uint32_t GMAC_ROE;
140  __I uint32_t GMAC_IHCE;
141  __I uint32_t GMAC_TCE;
142  __I uint32_t GMAC_UCE;
143  __I uint32_t Reserved4[2];
144  __IO uint32_t GMAC_TISUBN;
145  __IO uint32_t GMAC_TSH;
146  __I uint32_t Reserved5[3];
147  __IO uint32_t GMAC_TSL;
148  __IO uint32_t GMAC_TN;
149  __O uint32_t GMAC_TA;
150  __IO uint32_t GMAC_TI;
151  __I uint32_t GMAC_EFTSL;
152  __I uint32_t GMAC_EFTN;
153  __I uint32_t GMAC_EFRSL;
154  __I uint32_t GMAC_EFRN;
155  __I uint32_t GMAC_PEFTSL;
156  __I uint32_t GMAC_PEFTN;
157  __I uint32_t GMAC_PEFRSL;
158  __I uint32_t GMAC_PEFRN;
159  __I uint32_t Reserved6[128];
160  __I uint32_t GMAC_ISRPQ[2];
161  __I uint32_t Reserved7[14];
162  __IO uint32_t GMAC_TBQBAPQ[2];
163  __I uint32_t Reserved8[14];
164  __IO uint32_t GMAC_RBQBAPQ[2];
165  __I uint32_t Reserved9[6];
166  __IO uint32_t GMAC_RBSRPQ[2];
167  __I uint32_t Reserved10[5];
168  __IO uint32_t GMAC_CBSCR;
169  __IO uint32_t GMAC_CBSISQA;
170  __IO uint32_t GMAC_CBSISQB;
171  __I uint32_t Reserved11[14];
172  __IO uint32_t GMAC_ST1RPQ[4];
173  __I uint32_t Reserved12[12];
174  __IO uint32_t GMAC_ST2RPQ[8];
175  __I uint32_t Reserved13[12];
176  __I uint32_t Reserved14[28];
177  __O uint32_t GMAC_IERPQ[2];
178  __I uint32_t Reserved15[6];
179  __O uint32_t GMAC_IDRPQ[2];
180  __I uint32_t Reserved16[6];
181  __IO uint32_t GMAC_IMRPQ[2];
182  __I uint32_t Reserved17[38];
183  __IO uint32_t GMAC_ST2ER[4];
184  __I uint32_t Reserved18[4];
185  __IO GmacSt2Compare GMAC_ST2COMP[GMACST2COMPARE_NUMBER];
186 } Gmac;
187 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
188 /* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */
189 #define GMAC_NCR_LBL (0x1u << 1)
190 #define GMAC_NCR_RXEN (0x1u << 2)
191 #define GMAC_NCR_TXEN (0x1u << 3)
192 #define GMAC_NCR_MPE (0x1u << 4)
193 #define GMAC_NCR_CLRSTAT (0x1u << 5)
194 #define GMAC_NCR_INCSTAT (0x1u << 6)
195 #define GMAC_NCR_WESTAT (0x1u << 7)
196 #define GMAC_NCR_BP (0x1u << 8)
197 #define GMAC_NCR_TSTART (0x1u << 9)
198 #define GMAC_NCR_THALT (0x1u << 10)
199 #define GMAC_NCR_TXPF (0x1u << 11)
200 #define GMAC_NCR_TXZQPF (0x1u << 12)
201 #define GMAC_NCR_SRTSM (0x1u << 15)
202 #define GMAC_NCR_ENPBPR (0x1u << 16)
203 #define GMAC_NCR_TXPBPF (0x1u << 17)
204 #define GMAC_NCR_FNP (0x1u << 18)
205 /* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */
206 #define GMAC_NCFGR_SPD (0x1u << 0)
207 #define GMAC_NCFGR_FD (0x1u << 1)
208 #define GMAC_NCFGR_DNVLAN (0x1u << 2)
209 #define GMAC_NCFGR_JFRAME (0x1u << 3)
210 #define GMAC_NCFGR_CAF (0x1u << 4)
211 #define GMAC_NCFGR_NBC (0x1u << 5)
212 #define GMAC_NCFGR_MTIHEN (0x1u << 6)
213 #define GMAC_NCFGR_UNIHEN (0x1u << 7)
214 #define GMAC_NCFGR_MAXFS (0x1u << 8)
215 #define GMAC_NCFGR_RTY (0x1u << 12)
216 #define GMAC_NCFGR_PEN (0x1u << 13)
217 #define GMAC_NCFGR_RXBUFO_Pos 14
218 #define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos)
219 #define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos)))
220 #define GMAC_NCFGR_LFERD (0x1u << 16)
221 #define GMAC_NCFGR_RFCS (0x1u << 17)
222 #define GMAC_NCFGR_CLK_Pos 18
223 #define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos)
224 #define GMAC_NCFGR_CLK(value) ((GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos)))
225 #define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18)
226 #define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18)
227 #define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18)
228 #define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18)
229 #define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18)
230 #define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18)
231 #define GMAC_NCFGR_DBW_Pos 21
232 #define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos)
233 #define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos)))
234 #define GMAC_NCFGR_DCPF (0x1u << 23)
235 #define GMAC_NCFGR_RXCOEN (0x1u << 24)
236 #define GMAC_NCFGR_EFRHD (0x1u << 25)
237 #define GMAC_NCFGR_IRXFCS (0x1u << 26)
238 #define GMAC_NCFGR_IPGSEN (0x1u << 28)
239 #define GMAC_NCFGR_RXBP (0x1u << 29)
240 #define GMAC_NCFGR_IRXER (0x1u << 30)
241 /* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */
242 #define GMAC_NSR_MDIO (0x1u << 1)
243 #define GMAC_NSR_IDLE (0x1u << 2)
244 /* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */
245 #define GMAC_UR_RMII (0x1u << 0)
246 /* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */
247 #define GMAC_DCFGR_FBLDO_Pos 0
248 #define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos)
249 #define GMAC_DCFGR_FBLDO(value) ((GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos)))
250 #define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0)
251 #define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0)
252 #define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0)
253 #define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0)
254 #define GMAC_DCFGR_ESMA (0x1u << 6)
255 #define GMAC_DCFGR_ESPA (0x1u << 7)
256 #define GMAC_DCFGR_RXBMS_Pos 8
257 #define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos)
258 #define GMAC_DCFGR_RXBMS(value) ((GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos)))
259 #define GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8)
260 #define GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8)
261 #define GMAC_DCFGR_RXBMS_HALF (0x2u << 8)
262 #define GMAC_DCFGR_RXBMS_FULL (0x3u << 8)
263 #define GMAC_DCFGR_TXPBMS (0x1u << 10)
264 #define GMAC_DCFGR_TXCOEN (0x1u << 11)
265 #define GMAC_DCFGR_DRBS_Pos 16
266 #define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos)
267 #define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos)))
268 #define GMAC_DCFGR_DDRP (0x1u << 24)
269 /* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */
270 #define GMAC_TSR_UBR (0x1u << 0)
271 #define GMAC_TSR_COL (0x1u << 1)
272 #define GMAC_TSR_RLE (0x1u << 2)
273 #define GMAC_TSR_TXGO (0x1u << 3)
274 #define GMAC_TSR_TFC (0x1u << 4)
275 #define GMAC_TSR_TXCOMP (0x1u << 5)
276 #define GMAC_TSR_HRESP (0x1u << 8)
277 /* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address Register -------- */
278 #define GMAC_RBQB_ADDR_Pos 2
279 #define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos)
280 #define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos)))
281 /* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address Register -------- */
282 #define GMAC_TBQB_ADDR_Pos 2
283 #define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos)
284 #define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos)))
285 /* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */
286 #define GMAC_RSR_BNA (0x1u << 0)
287 #define GMAC_RSR_REC (0x1u << 1)
288 #define GMAC_RSR_RXOVR (0x1u << 2)
289 #define GMAC_RSR_HNO (0x1u << 3)
290 /* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */
291 #define GMAC_ISR_MFS (0x1u << 0)
292 #define GMAC_ISR_RCOMP (0x1u << 1)
293 #define GMAC_ISR_RXUBR (0x1u << 2)
294 #define GMAC_ISR_TXUBR (0x1u << 3)
295 #define GMAC_ISR_TUR (0x1u << 4)
296 #define GMAC_ISR_RLEX (0x1u << 5)
297 #define GMAC_ISR_TFC (0x1u << 6)
298 #define GMAC_ISR_TCOMP (0x1u << 7)
299 #define GMAC_ISR_ROVR (0x1u << 10)
300 #define GMAC_ISR_HRESP (0x1u << 11)
301 #define GMAC_ISR_PFNZ (0x1u << 12)
302 #define GMAC_ISR_PTZ (0x1u << 13)
303 #define GMAC_ISR_PFTR (0x1u << 14)
304 #define GMAC_ISR_DRQFR (0x1u << 18)
305 #define GMAC_ISR_SFR (0x1u << 19)
306 #define GMAC_ISR_DRQFT (0x1u << 20)
307 #define GMAC_ISR_SFT (0x1u << 21)
308 #define GMAC_ISR_PDRQFR (0x1u << 22)
309 #define GMAC_ISR_PDRSFR (0x1u << 23)
310 #define GMAC_ISR_PDRQFT (0x1u << 24)
311 #define GMAC_ISR_PDRSFT (0x1u << 25)
312 #define GMAC_ISR_SRI (0x1u << 26)
313 #define GMAC_ISR_WOL (0x1u << 28)
314 #define GMAC_ISR_TSU (0x1u << 29)
315 /* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */
316 #define GMAC_IER_MFS (0x1u << 0)
317 #define GMAC_IER_RCOMP (0x1u << 1)
318 #define GMAC_IER_RXUBR (0x1u << 2)
319 #define GMAC_IER_TXUBR (0x1u << 3)
320 #define GMAC_IER_TUR (0x1u << 4)
321 #define GMAC_IER_RLEX (0x1u << 5)
322 #define GMAC_IER_TFC (0x1u << 6)
323 #define GMAC_IER_TCOMP (0x1u << 7)
324 #define GMAC_IER_ROVR (0x1u << 10)
325 #define GMAC_IER_HRESP (0x1u << 11)
326 #define GMAC_IER_PFNZ (0x1u << 12)
327 #define GMAC_IER_PTZ (0x1u << 13)
328 #define GMAC_IER_PFTR (0x1u << 14)
329 #define GMAC_IER_EXINT (0x1u << 15)
330 #define GMAC_IER_DRQFR (0x1u << 18)
331 #define GMAC_IER_SFR (0x1u << 19)
332 #define GMAC_IER_DRQFT (0x1u << 20)
333 #define GMAC_IER_SFT (0x1u << 21)
334 #define GMAC_IER_PDRQFR (0x1u << 22)
335 #define GMAC_IER_PDRSFR (0x1u << 23)
336 #define GMAC_IER_PDRQFT (0x1u << 24)
337 #define GMAC_IER_PDRSFT (0x1u << 25)
338 #define GMAC_IER_SRI (0x1u << 26)
339 #define GMAC_IER_WOL (0x1u << 28)
340 /* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */
341 #define GMAC_IDR_MFS (0x1u << 0)
342 #define GMAC_IDR_RCOMP (0x1u << 1)
343 #define GMAC_IDR_RXUBR (0x1u << 2)
344 #define GMAC_IDR_TXUBR (0x1u << 3)
345 #define GMAC_IDR_TUR (0x1u << 4)
346 #define GMAC_IDR_RLEX (0x1u << 5)
347 #define GMAC_IDR_TFC (0x1u << 6)
348 #define GMAC_IDR_TCOMP (0x1u << 7)
349 #define GMAC_IDR_ROVR (0x1u << 10)
350 #define GMAC_IDR_HRESP (0x1u << 11)
351 #define GMAC_IDR_PFNZ (0x1u << 12)
352 #define GMAC_IDR_PTZ (0x1u << 13)
353 #define GMAC_IDR_PFTR (0x1u << 14)
354 #define GMAC_IDR_EXINT (0x1u << 15)
355 #define GMAC_IDR_DRQFR (0x1u << 18)
356 #define GMAC_IDR_SFR (0x1u << 19)
357 #define GMAC_IDR_DRQFT (0x1u << 20)
358 #define GMAC_IDR_SFT (0x1u << 21)
359 #define GMAC_IDR_PDRQFR (0x1u << 22)
360 #define GMAC_IDR_PDRSFR (0x1u << 23)
361 #define GMAC_IDR_PDRQFT (0x1u << 24)
362 #define GMAC_IDR_PDRSFT (0x1u << 25)
363 #define GMAC_IDR_SRI (0x1u << 26)
364 #define GMAC_IDR_WOL (0x1u << 28)
365 /* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */
366 #define GMAC_IMR_MFS (0x1u << 0)
367 #define GMAC_IMR_RCOMP (0x1u << 1)
368 #define GMAC_IMR_RXUBR (0x1u << 2)
369 #define GMAC_IMR_TXUBR (0x1u << 3)
370 #define GMAC_IMR_TUR (0x1u << 4)
371 #define GMAC_IMR_RLEX (0x1u << 5)
372 #define GMAC_IMR_TFC (0x1u << 6)
373 #define GMAC_IMR_TCOMP (0x1u << 7)
374 #define GMAC_IMR_ROVR (0x1u << 10)
375 #define GMAC_IMR_HRESP (0x1u << 11)
376 #define GMAC_IMR_PFNZ (0x1u << 12)
377 #define GMAC_IMR_PTZ (0x1u << 13)
378 #define GMAC_IMR_PFTR (0x1u << 14)
379 #define GMAC_IMR_EXINT (0x1u << 15)
380 #define GMAC_IMR_DRQFR (0x1u << 18)
381 #define GMAC_IMR_SFR (0x1u << 19)
382 #define GMAC_IMR_DRQFT (0x1u << 20)
383 #define GMAC_IMR_SFT (0x1u << 21)
384 #define GMAC_IMR_PDRQFR (0x1u << 22)
385 #define GMAC_IMR_PDRSFR (0x1u << 23)
386 #define GMAC_IMR_PDRQFT (0x1u << 24)
387 #define GMAC_IMR_PDRSFT (0x1u << 25)
388 /* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */
389 #define GMAC_MAN_DATA_Pos 0
390 #define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos)
391 #define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos)))
392 #define GMAC_MAN_WTN_Pos 16
393 #define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos)
394 #define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos)))
395 #define GMAC_MAN_REGA_Pos 18
396 #define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos)
397 #define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos)))
398 #define GMAC_MAN_PHYA_Pos 23
399 #define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos)
400 #define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos)))
401 #define GMAC_MAN_OP_Pos 28
402 #define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos)
403 #define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos)))
404 #define GMAC_MAN_CLTTO (0x1u << 30)
405 #define GMAC_MAN_WZO (0x1u << 31)
406 /* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */
407 #define GMAC_RPQ_RPQ_Pos 0
408 #define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos)
409 /* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */
410 #define GMAC_TPQ_TPQ_Pos 0
411 #define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos)
412 #define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos)))
413 /* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */
414 #define GMAC_TPSF_TPB1ADR_Pos 0
415 #define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos)
416 #define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos)))
417 #define GMAC_TPSF_ENTXP (0x1u << 31)
418 /* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */
419 #define GMAC_RPSF_RPB1ADR_Pos 0
420 #define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos)
421 #define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos)))
422 #define GMAC_RPSF_ENRXP (0x1u << 31)
423 /* -------- GMAC_RJFML : (GMAC Offset: 0x048) RX Jumbo Frame Max Length Register -------- */
424 #define GMAC_RJFML_FML_Pos 0
425 #define GMAC_RJFML_FML_Msk (0x3fffu << GMAC_RJFML_FML_Pos)
426 #define GMAC_RJFML_FML(value) ((GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos)))
427 /* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom -------- */
428 #define GMAC_HRB_ADDR_Pos 0
429 #define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos)
430 #define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos)))
431 /* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top -------- */
432 #define GMAC_HRT_ADDR_Pos 0
433 #define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos)
434 #define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos)))
435 /* -------- GMAC_SAB : (GMAC Offset: N/A) Specific Address 1 Bottom Register -------- */
436 #define GMAC_SAB_ADDR_Pos 0
437 #define GMAC_SAB_ADDR_Msk (0xffffffffu << GMAC_SAB_ADDR_Pos)
438 #define GMAC_SAB_ADDR(value) ((GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos)))
439 /* -------- GMAC_SAT : (GMAC Offset: N/A) Specific Address 1 Top Register -------- */
440 #define GMAC_SAT_ADDR_Pos 0
441 #define GMAC_SAT_ADDR_Msk (0xffffu << GMAC_SAT_ADDR_Pos)
442 #define GMAC_SAT_ADDR(value) ((GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos)))
443 /* -------- GMAC_TIDM1 : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */
444 #define GMAC_TIDM1_TID_Pos 0
445 #define GMAC_TIDM1_TID_Msk (0xffffu << GMAC_TIDM1_TID_Pos)
446 #define GMAC_TIDM1_TID(value) ((GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos)))
447 #define GMAC_TIDM1_ENID1 (0x1u << 31)
448 /* -------- GMAC_TIDM2 : (GMAC Offset: 0x0AC) Type ID Match 2 Register -------- */
449 #define GMAC_TIDM2_TID_Pos 0
450 #define GMAC_TIDM2_TID_Msk (0xffffu << GMAC_TIDM2_TID_Pos)
451 #define GMAC_TIDM2_TID(value) ((GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos)))
452 #define GMAC_TIDM2_ENID2 (0x1u << 31)
453 /* -------- GMAC_TIDM3 : (GMAC Offset: 0x0B0) Type ID Match 3 Register -------- */
454 #define GMAC_TIDM3_TID_Pos 0
455 #define GMAC_TIDM3_TID_Msk (0xffffu << GMAC_TIDM3_TID_Pos)
456 #define GMAC_TIDM3_TID(value) ((GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos)))
457 #define GMAC_TIDM3_ENID3 (0x1u << 31)
458 /* -------- GMAC_TIDM4 : (GMAC Offset: 0x0B4) Type ID Match 4 Register -------- */
459 #define GMAC_TIDM4_TID_Pos 0
460 #define GMAC_TIDM4_TID_Msk (0xffffu << GMAC_TIDM4_TID_Pos)
461 #define GMAC_TIDM4_TID(value) ((GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos)))
462 #define GMAC_TIDM4_ENID4 (0x1u << 31)
463 /* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */
464 #define GMAC_WOL_IP_Pos 0
465 #define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos)
466 #define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos)))
467 #define GMAC_WOL_MAG (0x1u << 16)
468 #define GMAC_WOL_ARP (0x1u << 17)
469 #define GMAC_WOL_SA1 (0x1u << 18)
470 #define GMAC_WOL_MTI (0x1u << 19)
471 /* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */
472 #define GMAC_IPGS_FL_Pos 0
473 #define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos)
474 #define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos)))
475 /* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */
476 #define GMAC_SVLAN_VLAN_TYPE_Pos 0
477 #define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos)
478 #define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos)))
479 #define GMAC_SVLAN_ESVLAN (0x1u << 31)
480 /* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */
481 #define GMAC_TPFCP_PEV_Pos 0
482 #define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos)
483 #define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos)))
484 #define GMAC_TPFCP_PQ_Pos 8
485 #define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos)
486 #define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos)))
487 /* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom Register -------- */
488 #define GMAC_SAMB1_ADDR_Pos 0
489 #define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos)
490 #define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos)))
491 /* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top Register -------- */
492 #define GMAC_SAMT1_ADDR_Pos 0
493 #define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos)
494 #define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos)))
495 /* -------- GMAC_NSC : (GMAC Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register -------- */
496 #define GMAC_NSC_NANOSEC_Pos 0
497 #define GMAC_NSC_NANOSEC_Msk (0x3fffffu << GMAC_NSC_NANOSEC_Pos)
498 #define GMAC_NSC_NANOSEC(value) ((GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos)))
499 /* -------- GMAC_SCL : (GMAC Offset: 0x0E0) 1588 Timer Second Comparison Low Register -------- */
500 #define GMAC_SCL_SEC_Pos 0
501 #define GMAC_SCL_SEC_Msk (0xffffffffu << GMAC_SCL_SEC_Pos)
502 #define GMAC_SCL_SEC(value) ((GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos)))
503 /* -------- GMAC_SCH : (GMAC Offset: 0x0E4) 1588 Timer Second Comparison High Register -------- */
504 #define GMAC_SCH_SEC_Pos 0
505 #define GMAC_SCH_SEC_Msk (0xffffu << GMAC_SCH_SEC_Pos)
506 #define GMAC_SCH_SEC(value) ((GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos)))
507 /* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register -------- */
508 #define GMAC_EFTSH_RUD_Pos 0
509 #define GMAC_EFTSH_RUD_Msk (0xffffu << GMAC_EFTSH_RUD_Pos)
510 /* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) PTP Event Frame Received Seconds High Register -------- */
511 #define GMAC_EFRSH_RUD_Pos 0
512 #define GMAC_EFRSH_RUD_Msk (0xffffu << GMAC_EFRSH_RUD_Pos)
513 /* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register -------- */
514 #define GMAC_PEFTSH_RUD_Pos 0
515 #define GMAC_PEFTSH_RUD_Msk (0xffffu << GMAC_PEFTSH_RUD_Pos)
516 /* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register -------- */
517 #define GMAC_PEFRSH_RUD_Pos 0
518 #define GMAC_PEFRSH_RUD_Msk (0xffffu << GMAC_PEFRSH_RUD_Pos)
519 /* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted Low Register -------- */
520 #define GMAC_OTLO_TXO_Pos 0
521 #define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos)
522 /* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted High Register -------- */
523 #define GMAC_OTHI_TXO_Pos 0
524 #define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos)
525 /* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */
526 #define GMAC_FT_FTX_Pos 0
527 #define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos)
528 /* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */
529 #define GMAC_BCFT_BFTX_Pos 0
530 #define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos)
531 /* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */
532 #define GMAC_MFT_MFTX_Pos 0
533 #define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos)
534 /* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */
535 #define GMAC_PFT_PFTX_Pos 0
536 #define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos)
537 /* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */
538 #define GMAC_BFT64_NFTX_Pos 0
539 #define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos)
540 /* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */
541 #define GMAC_TBFT127_NFTX_Pos 0
542 #define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos)
543 /* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */
544 #define GMAC_TBFT255_NFTX_Pos 0
545 #define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos)
546 /* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */
547 #define GMAC_TBFT511_NFTX_Pos 0
548 #define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos)
549 /* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */
550 #define GMAC_TBFT1023_NFTX_Pos 0
551 #define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos)
552 /* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */
553 #define GMAC_TBFT1518_NFTX_Pos 0
554 #define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos)
555 /* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */
556 #define GMAC_GTBFT1518_NFTX_Pos 0
557 #define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos)
558 /* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Underruns Register -------- */
559 #define GMAC_TUR_TXUNR_Pos 0
560 #define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos)
561 /* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */
562 #define GMAC_SCF_SCOL_Pos 0
563 #define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos)
564 /* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */
565 #define GMAC_MCF_MCOL_Pos 0
566 #define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos)
567 /* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */
568 #define GMAC_EC_XCOL_Pos 0
569 #define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos)
570 /* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */
571 #define GMAC_LC_LCOL_Pos 0
572 #define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos)
573 /* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */
574 #define GMAC_DTF_DEFT_Pos 0
575 #define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos)
576 /* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */
577 #define GMAC_CSE_CSR_Pos 0
578 #define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos)
579 /* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received Low Received Register -------- */
580 #define GMAC_ORLO_RXO_Pos 0
581 #define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos)
582 /* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received High Received Register -------- */
583 #define GMAC_ORHI_RXO_Pos 0
584 #define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos)
585 /* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */
586 #define GMAC_FR_FRX_Pos 0
587 #define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos)
588 /* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */
589 #define GMAC_BCFR_BFRX_Pos 0
590 #define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos)
591 /* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */
592 #define GMAC_MFR_MFRX_Pos 0
593 #define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos)
594 /* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */
595 #define GMAC_PFR_PFRX_Pos 0
596 #define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos)
597 /* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */
598 #define GMAC_BFR64_NFRX_Pos 0
599 #define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos)
600 /* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */
601 #define GMAC_TBFR127_NFRX_Pos 0
602 #define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos)
603 /* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */
604 #define GMAC_TBFR255_NFRX_Pos 0
605 #define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos)
606 /* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511 Byte Frames Received Register -------- */
607 #define GMAC_TBFR511_NFRX_Pos 0
608 #define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos)
609 /* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */
610 #define GMAC_TBFR1023_NFRX_Pos 0
611 #define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos)
612 /* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */
613 #define GMAC_TBFR1518_NFRX_Pos 0
614 #define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos)
615 /* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */
616 #define GMAC_TMXBFR_NFRX_Pos 0
617 #define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos)
618 /* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */
619 #define GMAC_UFR_UFRX_Pos 0
620 #define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos)
621 /* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */
622 #define GMAC_OFR_OFRX_Pos 0
623 #define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos)
624 /* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */
625 #define GMAC_JR_JRX_Pos 0
626 #define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos)
627 /* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */
628 #define GMAC_FCSE_FCKR_Pos 0
629 #define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos)
630 /* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */
631 #define GMAC_LFFE_LFER_Pos 0
632 #define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos)
633 /* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */
634 #define GMAC_RSE_RXSE_Pos 0
635 #define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos)
636 /* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */
637 #define GMAC_AE_AER_Pos 0
638 #define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos)
639 /* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */
640 #define GMAC_RRE_RXRER_Pos 0
641 #define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos)
642 /* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */
643 #define GMAC_ROE_RXOVR_Pos 0
644 #define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos)
645 /* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */
646 #define GMAC_IHCE_HCKER_Pos 0
647 #define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos)
648 /* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */
649 #define GMAC_TCE_TCKER_Pos 0
650 #define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos)
651 /* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */
652 #define GMAC_UCE_UCKER_Pos 0
653 #define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos)
654 /* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register -------- */
655 #define GMAC_TISUBN_LSBTIR_Pos 0
656 #define GMAC_TISUBN_LSBTIR_Msk (0xffffu << GMAC_TISUBN_LSBTIR_Pos)
657 #define GMAC_TISUBN_LSBTIR(value) ((GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos)))
658 /* -------- GMAC_TSH : (GMAC Offset: 0x1C0) 1588 Timer Seconds High Register -------- */
659 #define GMAC_TSH_TCS_Pos 0
660 #define GMAC_TSH_TCS_Msk (0xffffu << GMAC_TSH_TCS_Pos)
661 #define GMAC_TSH_TCS(value) ((GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos)))
662 /* -------- GMAC_TSL : (GMAC Offset: 0x1D0) 1588 Timer Seconds Low Register -------- */
663 #define GMAC_TSL_TCS_Pos 0
664 #define GMAC_TSL_TCS_Msk (0xffffffffu << GMAC_TSL_TCS_Pos)
665 #define GMAC_TSL_TCS(value) ((GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos)))
666 /* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */
667 #define GMAC_TN_TNS_Pos 0
668 #define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos)
669 #define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos)))
670 /* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */
671 #define GMAC_TA_ITDT_Pos 0
672 #define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos)
673 #define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos)))
674 #define GMAC_TA_ADJ (0x1u << 31)
675 /* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */
676 #define GMAC_TI_CNS_Pos 0
677 #define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos)
678 #define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos)))
679 #define GMAC_TI_ACNS_Pos 8
680 #define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos)
681 #define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos)))
682 #define GMAC_TI_NIT_Pos 16
683 #define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos)
684 #define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos)))
685 /* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register -------- */
686 #define GMAC_EFTSL_RUD_Pos 0
687 #define GMAC_EFTSL_RUD_Msk (0xffffffffu << GMAC_EFTSL_RUD_Pos)
688 /* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register -------- */
689 #define GMAC_EFTN_RUD_Pos 0
690 #define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos)
691 /* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds Low Register -------- */
692 #define GMAC_EFRSL_RUD_Pos 0
693 #define GMAC_EFRSL_RUD_Msk (0xffffffffu << GMAC_EFRSL_RUD_Pos)
694 /* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register -------- */
695 #define GMAC_EFRN_RUD_Pos 0
696 #define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos)
697 /* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register -------- */
698 #define GMAC_PEFTSL_RUD_Pos 0
699 #define GMAC_PEFTSL_RUD_Msk (0xffffffffu << GMAC_PEFTSL_RUD_Pos)
700 /* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */
701 #define GMAC_PEFTN_RUD_Pos 0
702 #define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos)
703 /* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register -------- */
704 #define GMAC_PEFRSL_RUD_Pos 0
705 #define GMAC_PEFRSL_RUD_Msk (0xffffffffu << GMAC_PEFRSL_RUD_Pos)
706 /* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register -------- */
707 #define GMAC_PEFRN_RUD_Pos 0
708 #define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos)
709 /* -------- GMAC_ISRPQ[2] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) -------- */
710 #define GMAC_ISRPQ_RCOMP (0x1u << 1)
711 #define GMAC_ISRPQ_RXUBR (0x1u << 2)
712 #define GMAC_ISRPQ_RLEX (0x1u << 5)
713 #define GMAC_ISRPQ_TFC (0x1u << 6)
714 #define GMAC_ISRPQ_TCOMP (0x1u << 7)
715 #define GMAC_ISRPQ_ROVR (0x1u << 10)
716 #define GMAC_ISRPQ_HRESP (0x1u << 11)
717 /* -------- GMAC_TBQBAPQ[2] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) -------- */
718 #define GMAC_TBQBAPQ_TXBQBA_Pos 2
719 #define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fffffffu << GMAC_TBQBAPQ_TXBQBA_Pos)
720 #define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos)))
721 /* -------- GMAC_RBQBAPQ[2] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) -------- */
722 #define GMAC_RBQBAPQ_RXBQBA_Pos 2
723 #define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fffffffu << GMAC_RBQBAPQ_RXBQBA_Pos)
724 #define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos)))
725 /* -------- GMAC_RBSRPQ[2] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) -------- */
726 #define GMAC_RBSRPQ_RBS_Pos 0
727 #define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos)
728 #define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos)))
729 /* -------- GMAC_CBSCR : (GMAC Offset: 0x4BC) Credit-Based Shaping Control Register -------- */
730 #define GMAC_CBSCR_QBE (0x1u << 0)
731 #define GMAC_CBSCR_QAE (0x1u << 1)
732 /* -------- GMAC_CBSISQA : (GMAC Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A -------- */
733 #define GMAC_CBSISQA_IS_Pos 0
734 #define GMAC_CBSISQA_IS_Msk (0xffffffffu << GMAC_CBSISQA_IS_Pos)
735 #define GMAC_CBSISQA_IS(value) ((GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos)))
736 /* -------- GMAC_CBSISQB : (GMAC Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B -------- */
737 #define GMAC_CBSISQB_IS_Pos 0
738 #define GMAC_CBSISQB_IS_Msk (0xffffffffu << GMAC_CBSISQB_IS_Pos)
739 #define GMAC_CBSISQB_IS(value) ((GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos)))
740 /* -------- GMAC_ST1RPQ[4] : (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) -------- */
741 #define GMAC_ST1RPQ_QNB_Pos 0
742 #define GMAC_ST1RPQ_QNB_Msk (0x7u << GMAC_ST1RPQ_QNB_Pos)
743 #define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos)))
744 #define GMAC_ST1RPQ_DSTCM_Pos 4
745 #define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos)
746 #define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos)))
747 #define GMAC_ST1RPQ_UDPM_Pos 12
748 #define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos)
749 #define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos)))
750 #define GMAC_ST1RPQ_DSTCE (0x1u << 28)
751 #define GMAC_ST1RPQ_UDPE (0x1u << 29)
752 /* -------- GMAC_ST2RPQ[8] : (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) -------- */
753 #define GMAC_ST2RPQ_QNB_Pos 0
754 #define GMAC_ST2RPQ_QNB_Msk (0x7u << GMAC_ST2RPQ_QNB_Pos)
755 #define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos)))
756 #define GMAC_ST2RPQ_VLANP_Pos 4
757 #define GMAC_ST2RPQ_VLANP_Msk (0x7u << GMAC_ST2RPQ_VLANP_Pos)
758 #define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos)))
759 #define GMAC_ST2RPQ_VLANE (0x1u << 8)
760 #define GMAC_ST2RPQ_I2ETH_Pos 9
761 #define GMAC_ST2RPQ_I2ETH_Msk (0x7u << GMAC_ST2RPQ_I2ETH_Pos)
762 #define GMAC_ST2RPQ_I2ETH(value) ((GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos)))
763 #define GMAC_ST2RPQ_ETHE (0x1u << 12)
764 #define GMAC_ST2RPQ_COMPA_Pos 13
765 #define GMAC_ST2RPQ_COMPA_Msk (0x1fu << GMAC_ST2RPQ_COMPA_Pos)
766 #define GMAC_ST2RPQ_COMPA(value) ((GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos)))
767 #define GMAC_ST2RPQ_COMPAE (0x1u << 18)
768 #define GMAC_ST2RPQ_COMPB_Pos 19
769 #define GMAC_ST2RPQ_COMPB_Msk (0x1fu << GMAC_ST2RPQ_COMPB_Pos)
770 #define GMAC_ST2RPQ_COMPB(value) ((GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos)))
771 #define GMAC_ST2RPQ_COMPBE (0x1u << 24)
772 #define GMAC_ST2RPQ_COMPC_Pos 25
773 #define GMAC_ST2RPQ_COMPC_Msk (0x1fu << GMAC_ST2RPQ_COMPC_Pos)
774 #define GMAC_ST2RPQ_COMPC(value) ((GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos)))
775 #define GMAC_ST2RPQ_COMPCE (0x1u << 30)
776 /* -------- GMAC_IERPQ[2] : (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) -------- */
777 #define GMAC_IERPQ_RCOMP (0x1u << 1)
778 #define GMAC_IERPQ_RXUBR (0x1u << 2)
779 #define GMAC_IERPQ_RLEX (0x1u << 5)
780 #define GMAC_IERPQ_TFC (0x1u << 6)
781 #define GMAC_IERPQ_TCOMP (0x1u << 7)
782 #define GMAC_IERPQ_ROVR (0x1u << 10)
783 #define GMAC_IERPQ_HRESP (0x1u << 11)
784 /* -------- GMAC_IDRPQ[2] : (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) -------- */
785 #define GMAC_IDRPQ_RCOMP (0x1u << 1)
786 #define GMAC_IDRPQ_RXUBR (0x1u << 2)
787 #define GMAC_IDRPQ_RLEX (0x1u << 5)
788 #define GMAC_IDRPQ_TFC (0x1u << 6)
789 #define GMAC_IDRPQ_TCOMP (0x1u << 7)
790 #define GMAC_IDRPQ_ROVR (0x1u << 10)
791 #define GMAC_IDRPQ_HRESP (0x1u << 11)
792 /* -------- GMAC_IMRPQ[2] : (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) -------- */
793 #define GMAC_IMRPQ_RCOMP (0x1u << 1)
794 #define GMAC_IMRPQ_RXUBR (0x1u << 2)
795 #define GMAC_IMRPQ_RLEX (0x1u << 5)
796 #define GMAC_IMRPQ_AHB (0x1u << 6)
797 #define GMAC_IMRPQ_TCOMP (0x1u << 7)
798 #define GMAC_IMRPQ_ROVR (0x1u << 10)
799 #define GMAC_IMRPQ_HRESP (0x1u << 11)
800 /* -------- GMAC_ST2ER[4] : (GMAC Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) -------- */
801 #define GMAC_ST2ER_COMPVAL_Pos 0
802 #define GMAC_ST2ER_COMPVAL_Msk (0xffffu << GMAC_ST2ER_COMPVAL_Pos)
803 #define GMAC_ST2ER_COMPVAL(value) ((GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos)))
804 /* -------- GMAC_ST2CW00 : (GMAC Offset: 0x700) Screening Type 2 Compare Word 0 Register (index = 0) -------- */
805 #define GMAC_ST2CW00_MASKVAL_Pos 0
806 #define GMAC_ST2CW00_MASKVAL_Msk (0xffffu << GMAC_ST2CW00_MASKVAL_Pos)
807 #define GMAC_ST2CW00_MASKVAL(value) ((GMAC_ST2CW00_MASKVAL_Msk & ((value) << GMAC_ST2CW00_MASKVAL_Pos)))
808 #define GMAC_ST2CW00_COMPVAL_Pos 16
809 #define GMAC_ST2CW00_COMPVAL_Msk (0xffffu << GMAC_ST2CW00_COMPVAL_Pos)
810 #define GMAC_ST2CW00_COMPVAL(value) ((GMAC_ST2CW00_COMPVAL_Msk & ((value) << GMAC_ST2CW00_COMPVAL_Pos)))
811 /* -------- GMAC_ST2CW10 : (GMAC Offset: 0x704) Screening Type 2 Compare Word 1 Register (index = 0) -------- */
812 #define GMAC_ST2CW10_OFFSVAL_Pos 0
813 #define GMAC_ST2CW10_OFFSVAL_Msk (0x7fu << GMAC_ST2CW10_OFFSVAL_Pos)
814 #define GMAC_ST2CW10_OFFSVAL(value) ((GMAC_ST2CW10_OFFSVAL_Msk & ((value) << GMAC_ST2CW10_OFFSVAL_Pos)))
815 #define GMAC_ST2CW10_OFFSSTRT_Pos 7
816 #define GMAC_ST2CW10_OFFSSTRT_Msk (0x3u << GMAC_ST2CW10_OFFSSTRT_Pos)
817 #define GMAC_ST2CW10_OFFSSTRT(value) ((GMAC_ST2CW10_OFFSSTRT_Msk & ((value) << GMAC_ST2CW10_OFFSSTRT_Pos)))
818 #define GMAC_ST2CW10_OFFSSTRT_FRAMESTART (0x0u << 7)
819 #define GMAC_ST2CW10_OFFSSTRT_ETHERTYPE (0x1u << 7)
820 #define GMAC_ST2CW10_OFFSSTRT_IP (0x2u << 7)
821 #define GMAC_ST2CW10_OFFSSTRT_TCP_UDP (0x3u << 7)
822 /* -------- GMAC_ST2CW01 : (GMAC Offset: 0x708) Screening Type 2 Compare Word 0 Register (index = 1) -------- */
823 #define GMAC_ST2CW01_MASKVAL_Pos 0
824 #define GMAC_ST2CW01_MASKVAL_Msk (0xffffu << GMAC_ST2CW01_MASKVAL_Pos)
825 #define GMAC_ST2CW01_MASKVAL(value) ((GMAC_ST2CW01_MASKVAL_Msk & ((value) << GMAC_ST2CW01_MASKVAL_Pos)))
826 #define GMAC_ST2CW01_COMPVAL_Pos 16
827 #define GMAC_ST2CW01_COMPVAL_Msk (0xffffu << GMAC_ST2CW01_COMPVAL_Pos)
828 #define GMAC_ST2CW01_COMPVAL(value) ((GMAC_ST2CW01_COMPVAL_Msk & ((value) << GMAC_ST2CW01_COMPVAL_Pos)))
829 /* -------- GMAC_ST2CW11 : (GMAC Offset: 0x70C) Screening Type 2 Compare Word 1 Register (index = 1) -------- */
830 #define GMAC_ST2CW11_OFFSVAL_Pos 0
831 #define GMAC_ST2CW11_OFFSVAL_Msk (0x7fu << GMAC_ST2CW11_OFFSVAL_Pos)
832 #define GMAC_ST2CW11_OFFSVAL(value) ((GMAC_ST2CW11_OFFSVAL_Msk & ((value) << GMAC_ST2CW11_OFFSVAL_Pos)))
833 #define GMAC_ST2CW11_OFFSSTRT_Pos 7
834 #define GMAC_ST2CW11_OFFSSTRT_Msk (0x3u << GMAC_ST2CW11_OFFSSTRT_Pos)
835 #define GMAC_ST2CW11_OFFSSTRT(value) ((GMAC_ST2CW11_OFFSSTRT_Msk & ((value) << GMAC_ST2CW11_OFFSSTRT_Pos)))
836 #define GMAC_ST2CW11_OFFSSTRT_FRAMESTART (0x0u << 7)
837 #define GMAC_ST2CW11_OFFSSTRT_ETHERTYPE (0x1u << 7)
838 #define GMAC_ST2CW11_OFFSSTRT_IP (0x2u << 7)
839 #define GMAC_ST2CW11_OFFSSTRT_TCP_UDP (0x3u << 7)
840 /* -------- GMAC_ST2CW02 : (GMAC Offset: 0x710) Screening Type 2 Compare Word 0 Register (index = 2) -------- */
841 #define GMAC_ST2CW02_MASKVAL_Pos 0
842 #define GMAC_ST2CW02_MASKVAL_Msk (0xffffu << GMAC_ST2CW02_MASKVAL_Pos)
843 #define GMAC_ST2CW02_MASKVAL(value) ((GMAC_ST2CW02_MASKVAL_Msk & ((value) << GMAC_ST2CW02_MASKVAL_Pos)))
844 #define GMAC_ST2CW02_COMPVAL_Pos 16
845 #define GMAC_ST2CW02_COMPVAL_Msk (0xffffu << GMAC_ST2CW02_COMPVAL_Pos)
846 #define GMAC_ST2CW02_COMPVAL(value) ((GMAC_ST2CW02_COMPVAL_Msk & ((value) << GMAC_ST2CW02_COMPVAL_Pos)))
847 /* -------- GMAC_ST2CW12 : (GMAC Offset: 0x714) Screening Type 2 Compare Word 1 Register (index = 2) -------- */
848 #define GMAC_ST2CW12_OFFSVAL_Pos 0
849 #define GMAC_ST2CW12_OFFSVAL_Msk (0x7fu << GMAC_ST2CW12_OFFSVAL_Pos)
850 #define GMAC_ST2CW12_OFFSVAL(value) ((GMAC_ST2CW12_OFFSVAL_Msk & ((value) << GMAC_ST2CW12_OFFSVAL_Pos)))
851 #define GMAC_ST2CW12_OFFSSTRT_Pos 7
852 #define GMAC_ST2CW12_OFFSSTRT_Msk (0x3u << GMAC_ST2CW12_OFFSSTRT_Pos)
853 #define GMAC_ST2CW12_OFFSSTRT(value) ((GMAC_ST2CW12_OFFSSTRT_Msk & ((value) << GMAC_ST2CW12_OFFSSTRT_Pos)))
854 #define GMAC_ST2CW12_OFFSSTRT_FRAMESTART (0x0u << 7)
855 #define GMAC_ST2CW12_OFFSSTRT_ETHERTYPE (0x1u << 7)
856 #define GMAC_ST2CW12_OFFSSTRT_IP (0x2u << 7)
857 #define GMAC_ST2CW12_OFFSSTRT_TCP_UDP (0x3u << 7)
858 /* -------- GMAC_ST2CW03 : (GMAC Offset: 0x718) Screening Type 2 Compare Word 0 Register (index = 3) -------- */
859 #define GMAC_ST2CW03_MASKVAL_Pos 0
860 #define GMAC_ST2CW03_MASKVAL_Msk (0xffffu << GMAC_ST2CW03_MASKVAL_Pos)
861 #define GMAC_ST2CW03_MASKVAL(value) ((GMAC_ST2CW03_MASKVAL_Msk & ((value) << GMAC_ST2CW03_MASKVAL_Pos)))
862 #define GMAC_ST2CW03_COMPVAL_Pos 16
863 #define GMAC_ST2CW03_COMPVAL_Msk (0xffffu << GMAC_ST2CW03_COMPVAL_Pos)
864 #define GMAC_ST2CW03_COMPVAL(value) ((GMAC_ST2CW03_COMPVAL_Msk & ((value) << GMAC_ST2CW03_COMPVAL_Pos)))
865 /* -------- GMAC_ST2CW13 : (GMAC Offset: 0x71C) Screening Type 2 Compare Word 1 Register (index = 3) -------- */
866 #define GMAC_ST2CW13_OFFSVAL_Pos 0
867 #define GMAC_ST2CW13_OFFSVAL_Msk (0x7fu << GMAC_ST2CW13_OFFSVAL_Pos)
868 #define GMAC_ST2CW13_OFFSVAL(value) ((GMAC_ST2CW13_OFFSVAL_Msk & ((value) << GMAC_ST2CW13_OFFSVAL_Pos)))
869 #define GMAC_ST2CW13_OFFSSTRT_Pos 7
870 #define GMAC_ST2CW13_OFFSSTRT_Msk (0x3u << GMAC_ST2CW13_OFFSSTRT_Pos)
871 #define GMAC_ST2CW13_OFFSSTRT(value) ((GMAC_ST2CW13_OFFSSTRT_Msk & ((value) << GMAC_ST2CW13_OFFSSTRT_Pos)))
872 #define GMAC_ST2CW13_OFFSSTRT_FRAMESTART (0x0u << 7)
873 #define GMAC_ST2CW13_OFFSSTRT_ETHERTYPE (0x1u << 7)
874 #define GMAC_ST2CW13_OFFSSTRT_IP (0x2u << 7)
875 #define GMAC_ST2CW13_OFFSSTRT_TCP_UDP (0x3u << 7)
876 /* -------- GMAC_ST2CW04 : (GMAC Offset: 0x720) Screening Type 2 Compare Word 0 Register (index = 4) -------- */
877 #define GMAC_ST2CW04_MASKVAL_Pos 0
878 #define GMAC_ST2CW04_MASKVAL_Msk (0xffffu << GMAC_ST2CW04_MASKVAL_Pos)
879 #define GMAC_ST2CW04_MASKVAL(value) ((GMAC_ST2CW04_MASKVAL_Msk & ((value) << GMAC_ST2CW04_MASKVAL_Pos)))
880 #define GMAC_ST2CW04_COMPVAL_Pos 16
881 #define GMAC_ST2CW04_COMPVAL_Msk (0xffffu << GMAC_ST2CW04_COMPVAL_Pos)
882 #define GMAC_ST2CW04_COMPVAL(value) ((GMAC_ST2CW04_COMPVAL_Msk & ((value) << GMAC_ST2CW04_COMPVAL_Pos)))
883 /* -------- GMAC_ST2CW14 : (GMAC Offset: 0x724) Screening Type 2 Compare Word 1 Register (index = 4) -------- */
884 #define GMAC_ST2CW14_OFFSVAL_Pos 0
885 #define GMAC_ST2CW14_OFFSVAL_Msk (0x7fu << GMAC_ST2CW14_OFFSVAL_Pos)
886 #define GMAC_ST2CW14_OFFSVAL(value) ((GMAC_ST2CW14_OFFSVAL_Msk & ((value) << GMAC_ST2CW14_OFFSVAL_Pos)))
887 #define GMAC_ST2CW14_OFFSSTRT_Pos 7
888 #define GMAC_ST2CW14_OFFSSTRT_Msk (0x3u << GMAC_ST2CW14_OFFSSTRT_Pos)
889 #define GMAC_ST2CW14_OFFSSTRT(value) ((GMAC_ST2CW14_OFFSSTRT_Msk & ((value) << GMAC_ST2CW14_OFFSSTRT_Pos)))
890 #define GMAC_ST2CW14_OFFSSTRT_FRAMESTART (0x0u << 7)
891 #define GMAC_ST2CW14_OFFSSTRT_ETHERTYPE (0x1u << 7)
892 #define GMAC_ST2CW14_OFFSSTRT_IP (0x2u << 7)
893 #define GMAC_ST2CW14_OFFSSTRT_TCP_UDP (0x3u << 7)
894 /* -------- GMAC_ST2CW05 : (GMAC Offset: 0x728) Screening Type 2 Compare Word 0 Register (index = 5) -------- */
895 #define GMAC_ST2CW05_MASKVAL_Pos 0
896 #define GMAC_ST2CW05_MASKVAL_Msk (0xffffu << GMAC_ST2CW05_MASKVAL_Pos)
897 #define GMAC_ST2CW05_MASKVAL(value) ((GMAC_ST2CW05_MASKVAL_Msk & ((value) << GMAC_ST2CW05_MASKVAL_Pos)))
898 #define GMAC_ST2CW05_COMPVAL_Pos 16
899 #define GMAC_ST2CW05_COMPVAL_Msk (0xffffu << GMAC_ST2CW05_COMPVAL_Pos)
900 #define GMAC_ST2CW05_COMPVAL(value) ((GMAC_ST2CW05_COMPVAL_Msk & ((value) << GMAC_ST2CW05_COMPVAL_Pos)))
901 /* -------- GMAC_ST2CW15 : (GMAC Offset: 0x72C) Screening Type 2 Compare Word 1 Register (index = 5) -------- */
902 #define GMAC_ST2CW15_OFFSVAL_Pos 0
903 #define GMAC_ST2CW15_OFFSVAL_Msk (0x7fu << GMAC_ST2CW15_OFFSVAL_Pos)
904 #define GMAC_ST2CW15_OFFSVAL(value) ((GMAC_ST2CW15_OFFSVAL_Msk & ((value) << GMAC_ST2CW15_OFFSVAL_Pos)))
905 #define GMAC_ST2CW15_OFFSSTRT_Pos 7
906 #define GMAC_ST2CW15_OFFSSTRT_Msk (0x3u << GMAC_ST2CW15_OFFSSTRT_Pos)
907 #define GMAC_ST2CW15_OFFSSTRT(value) ((GMAC_ST2CW15_OFFSSTRT_Msk & ((value) << GMAC_ST2CW15_OFFSSTRT_Pos)))
908 #define GMAC_ST2CW15_OFFSSTRT_FRAMESTART (0x0u << 7)
909 #define GMAC_ST2CW15_OFFSSTRT_ETHERTYPE (0x1u << 7)
910 #define GMAC_ST2CW15_OFFSSTRT_IP (0x2u << 7)
911 #define GMAC_ST2CW15_OFFSSTRT_TCP_UDP (0x3u << 7)
912 /* -------- GMAC_ST2CW06 : (GMAC Offset: 0x730) Screening Type 2 Compare Word 0 Register (index = 6) -------- */
913 #define GMAC_ST2CW06_MASKVAL_Pos 0
914 #define GMAC_ST2CW06_MASKVAL_Msk (0xffffu << GMAC_ST2CW06_MASKVAL_Pos)
915 #define GMAC_ST2CW06_MASKVAL(value) ((GMAC_ST2CW06_MASKVAL_Msk & ((value) << GMAC_ST2CW06_MASKVAL_Pos)))
916 #define GMAC_ST2CW06_COMPVAL_Pos 16
917 #define GMAC_ST2CW06_COMPVAL_Msk (0xffffu << GMAC_ST2CW06_COMPVAL_Pos)
918 #define GMAC_ST2CW06_COMPVAL(value) ((GMAC_ST2CW06_COMPVAL_Msk & ((value) << GMAC_ST2CW06_COMPVAL_Pos)))
919 /* -------- GMAC_ST2CW16 : (GMAC Offset: 0x734) Screening Type 2 Compare Word 1 Register (index = 6) -------- */
920 #define GMAC_ST2CW16_OFFSVAL_Pos 0
921 #define GMAC_ST2CW16_OFFSVAL_Msk (0x7fu << GMAC_ST2CW16_OFFSVAL_Pos)
922 #define GMAC_ST2CW16_OFFSVAL(value) ((GMAC_ST2CW16_OFFSVAL_Msk & ((value) << GMAC_ST2CW16_OFFSVAL_Pos)))
923 #define GMAC_ST2CW16_OFFSSTRT_Pos 7
924 #define GMAC_ST2CW16_OFFSSTRT_Msk (0x3u << GMAC_ST2CW16_OFFSSTRT_Pos)
925 #define GMAC_ST2CW16_OFFSSTRT(value) ((GMAC_ST2CW16_OFFSSTRT_Msk & ((value) << GMAC_ST2CW16_OFFSSTRT_Pos)))
926 #define GMAC_ST2CW16_OFFSSTRT_FRAMESTART (0x0u << 7)
927 #define GMAC_ST2CW16_OFFSSTRT_ETHERTYPE (0x1u << 7)
928 #define GMAC_ST2CW16_OFFSSTRT_IP (0x2u << 7)
929 #define GMAC_ST2CW16_OFFSSTRT_TCP_UDP (0x3u << 7)
930 /* -------- GMAC_ST2CW07 : (GMAC Offset: 0x738) Screening Type 2 Compare Word 0 Register (index = 7) -------- */
931 #define GMAC_ST2CW07_MASKVAL_Pos 0
932 #define GMAC_ST2CW07_MASKVAL_Msk (0xffffu << GMAC_ST2CW07_MASKVAL_Pos)
933 #define GMAC_ST2CW07_MASKVAL(value) ((GMAC_ST2CW07_MASKVAL_Msk & ((value) << GMAC_ST2CW07_MASKVAL_Pos)))
934 #define GMAC_ST2CW07_COMPVAL_Pos 16
935 #define GMAC_ST2CW07_COMPVAL_Msk (0xffffu << GMAC_ST2CW07_COMPVAL_Pos)
936 #define GMAC_ST2CW07_COMPVAL(value) ((GMAC_ST2CW07_COMPVAL_Msk & ((value) << GMAC_ST2CW07_COMPVAL_Pos)))
937 /* -------- GMAC_ST2CW17 : (GMAC Offset: 0x73C) Screening Type 2 Compare Word 1 Register (index = 7) -------- */
938 #define GMAC_ST2CW17_OFFSVAL_Pos 0
939 #define GMAC_ST2CW17_OFFSVAL_Msk (0x7fu << GMAC_ST2CW17_OFFSVAL_Pos)
940 #define GMAC_ST2CW17_OFFSVAL(value) ((GMAC_ST2CW17_OFFSVAL_Msk & ((value) << GMAC_ST2CW17_OFFSVAL_Pos)))
941 #define GMAC_ST2CW17_OFFSSTRT_Pos 7
942 #define GMAC_ST2CW17_OFFSSTRT_Msk (0x3u << GMAC_ST2CW17_OFFSSTRT_Pos)
943 #define GMAC_ST2CW17_OFFSSTRT(value) ((GMAC_ST2CW17_OFFSSTRT_Msk & ((value) << GMAC_ST2CW17_OFFSSTRT_Pos)))
944 #define GMAC_ST2CW17_OFFSSTRT_FRAMESTART (0x0u << 7)
945 #define GMAC_ST2CW17_OFFSSTRT_ETHERTYPE (0x1u << 7)
946 #define GMAC_ST2CW17_OFFSSTRT_IP (0x2u << 7)
947 #define GMAC_ST2CW17_OFFSSTRT_TCP_UDP (0x3u << 7)
948 /* -------- GMAC_ST2CW08 : (GMAC Offset: 0x740) Screening Type 2 Compare Word 0 Register (index = 8) -------- */
949 #define GMAC_ST2CW08_MASKVAL_Pos 0
950 #define GMAC_ST2CW08_MASKVAL_Msk (0xffffu << GMAC_ST2CW08_MASKVAL_Pos)
951 #define GMAC_ST2CW08_MASKVAL(value) ((GMAC_ST2CW08_MASKVAL_Msk & ((value) << GMAC_ST2CW08_MASKVAL_Pos)))
952 #define GMAC_ST2CW08_COMPVAL_Pos 16
953 #define GMAC_ST2CW08_COMPVAL_Msk (0xffffu << GMAC_ST2CW08_COMPVAL_Pos)
954 #define GMAC_ST2CW08_COMPVAL(value) ((GMAC_ST2CW08_COMPVAL_Msk & ((value) << GMAC_ST2CW08_COMPVAL_Pos)))
955 /* -------- GMAC_ST2CW18 : (GMAC Offset: 0x744) Screening Type 2 Compare Word 1 Register (index = 8) -------- */
956 #define GMAC_ST2CW18_OFFSVAL_Pos 0
957 #define GMAC_ST2CW18_OFFSVAL_Msk (0x7fu << GMAC_ST2CW18_OFFSVAL_Pos)
958 #define GMAC_ST2CW18_OFFSVAL(value) ((GMAC_ST2CW18_OFFSVAL_Msk & ((value) << GMAC_ST2CW18_OFFSVAL_Pos)))
959 #define GMAC_ST2CW18_OFFSSTRT_Pos 7
960 #define GMAC_ST2CW18_OFFSSTRT_Msk (0x3u << GMAC_ST2CW18_OFFSSTRT_Pos)
961 #define GMAC_ST2CW18_OFFSSTRT(value) ((GMAC_ST2CW18_OFFSSTRT_Msk & ((value) << GMAC_ST2CW18_OFFSSTRT_Pos)))
962 #define GMAC_ST2CW18_OFFSSTRT_FRAMESTART (0x0u << 7)
963 #define GMAC_ST2CW18_OFFSSTRT_ETHERTYPE (0x1u << 7)
964 #define GMAC_ST2CW18_OFFSSTRT_IP (0x2u << 7)
965 #define GMAC_ST2CW18_OFFSSTRT_TCP_UDP (0x3u << 7)
966 /* -------- GMAC_ST2CW09 : (GMAC Offset: 0x748) Screening Type 2 Compare Word 0 Register (index = 9) -------- */
967 #define GMAC_ST2CW09_MASKVAL_Pos 0
968 #define GMAC_ST2CW09_MASKVAL_Msk (0xffffu << GMAC_ST2CW09_MASKVAL_Pos)
969 #define GMAC_ST2CW09_MASKVAL(value) ((GMAC_ST2CW09_MASKVAL_Msk & ((value) << GMAC_ST2CW09_MASKVAL_Pos)))
970 #define GMAC_ST2CW09_COMPVAL_Pos 16
971 #define GMAC_ST2CW09_COMPVAL_Msk (0xffffu << GMAC_ST2CW09_COMPVAL_Pos)
972 #define GMAC_ST2CW09_COMPVAL(value) ((GMAC_ST2CW09_COMPVAL_Msk & ((value) << GMAC_ST2CW09_COMPVAL_Pos)))
973 /* -------- GMAC_ST2CW19 : (GMAC Offset: 0x74C) Screening Type 2 Compare Word 1 Register (index = 9) -------- */
974 #define GMAC_ST2CW19_OFFSVAL_Pos 0
975 #define GMAC_ST2CW19_OFFSVAL_Msk (0x7fu << GMAC_ST2CW19_OFFSVAL_Pos)
976 #define GMAC_ST2CW19_OFFSVAL(value) ((GMAC_ST2CW19_OFFSVAL_Msk & ((value) << GMAC_ST2CW19_OFFSVAL_Pos)))
977 #define GMAC_ST2CW19_OFFSSTRT_Pos 7
978 #define GMAC_ST2CW19_OFFSSTRT_Msk (0x3u << GMAC_ST2CW19_OFFSSTRT_Pos)
979 #define GMAC_ST2CW19_OFFSSTRT(value) ((GMAC_ST2CW19_OFFSSTRT_Msk & ((value) << GMAC_ST2CW19_OFFSSTRT_Pos)))
980 #define GMAC_ST2CW19_OFFSSTRT_FRAMESTART (0x0u << 7)
981 #define GMAC_ST2CW19_OFFSSTRT_ETHERTYPE (0x1u << 7)
982 #define GMAC_ST2CW19_OFFSSTRT_IP (0x2u << 7)
983 #define GMAC_ST2CW19_OFFSSTRT_TCP_UDP (0x3u << 7)
984 /* -------- GMAC_ST2CW010 : (GMAC Offset: 0x750) Screening Type 2 Compare Word 0 Register (index = 10) -------- */
985 #define GMAC_ST2CW010_MASKVAL_Pos 0
986 #define GMAC_ST2CW010_MASKVAL_Msk (0xffffu << GMAC_ST2CW010_MASKVAL_Pos)
987 #define GMAC_ST2CW010_MASKVAL(value) ((GMAC_ST2CW010_MASKVAL_Msk & ((value) << GMAC_ST2CW010_MASKVAL_Pos)))
988 #define GMAC_ST2CW010_COMPVAL_Pos 16
989 #define GMAC_ST2CW010_COMPVAL_Msk (0xffffu << GMAC_ST2CW010_COMPVAL_Pos)
990 #define GMAC_ST2CW010_COMPVAL(value) ((GMAC_ST2CW010_COMPVAL_Msk & ((value) << GMAC_ST2CW010_COMPVAL_Pos)))
991 /* -------- GMAC_ST2CW110 : (GMAC Offset: 0x754) Screening Type 2 Compare Word 1 Register (index = 10) -------- */
992 #define GMAC_ST2CW110_OFFSVAL_Pos 0
993 #define GMAC_ST2CW110_OFFSVAL_Msk (0x7fu << GMAC_ST2CW110_OFFSVAL_Pos)
994 #define GMAC_ST2CW110_OFFSVAL(value) ((GMAC_ST2CW110_OFFSVAL_Msk & ((value) << GMAC_ST2CW110_OFFSVAL_Pos)))
995 #define GMAC_ST2CW110_OFFSSTRT_Pos 7
996 #define GMAC_ST2CW110_OFFSSTRT_Msk (0x3u << GMAC_ST2CW110_OFFSSTRT_Pos)
997 #define GMAC_ST2CW110_OFFSSTRT(value) ((GMAC_ST2CW110_OFFSSTRT_Msk & ((value) << GMAC_ST2CW110_OFFSSTRT_Pos)))
998 #define GMAC_ST2CW110_OFFSSTRT_FRAMESTART (0x0u << 7)
999 #define GMAC_ST2CW110_OFFSSTRT_ETHERTYPE (0x1u << 7)
1000 #define GMAC_ST2CW110_OFFSSTRT_IP (0x2u << 7)
1001 #define GMAC_ST2CW110_OFFSSTRT_TCP_UDP (0x3u << 7)
1002 /* -------- GMAC_ST2CW011 : (GMAC Offset: 0x758) Screening Type 2 Compare Word 0 Register (index = 11) -------- */
1003 #define GMAC_ST2CW011_MASKVAL_Pos 0
1004 #define GMAC_ST2CW011_MASKVAL_Msk (0xffffu << GMAC_ST2CW011_MASKVAL_Pos)
1005 #define GMAC_ST2CW011_MASKVAL(value) ((GMAC_ST2CW011_MASKVAL_Msk & ((value) << GMAC_ST2CW011_MASKVAL_Pos)))
1006 #define GMAC_ST2CW011_COMPVAL_Pos 16
1007 #define GMAC_ST2CW011_COMPVAL_Msk (0xffffu << GMAC_ST2CW011_COMPVAL_Pos)
1008 #define GMAC_ST2CW011_COMPVAL(value) ((GMAC_ST2CW011_COMPVAL_Msk & ((value) << GMAC_ST2CW011_COMPVAL_Pos)))
1009 /* -------- GMAC_ST2CW111 : (GMAC Offset: 0x75C) Screening Type 2 Compare Word 1 Register (index = 11) -------- */
1010 #define GMAC_ST2CW111_OFFSVAL_Pos 0
1011 #define GMAC_ST2CW111_OFFSVAL_Msk (0x7fu << GMAC_ST2CW111_OFFSVAL_Pos)
1012 #define GMAC_ST2CW111_OFFSVAL(value) ((GMAC_ST2CW111_OFFSVAL_Msk & ((value) << GMAC_ST2CW111_OFFSVAL_Pos)))
1013 #define GMAC_ST2CW111_OFFSSTRT_Pos 7
1014 #define GMAC_ST2CW111_OFFSSTRT_Msk (0x3u << GMAC_ST2CW111_OFFSSTRT_Pos)
1015 #define GMAC_ST2CW111_OFFSSTRT(value) ((GMAC_ST2CW111_OFFSSTRT_Msk & ((value) << GMAC_ST2CW111_OFFSSTRT_Pos)))
1016 #define GMAC_ST2CW111_OFFSSTRT_FRAMESTART (0x0u << 7)
1017 #define GMAC_ST2CW111_OFFSSTRT_ETHERTYPE (0x1u << 7)
1018 #define GMAC_ST2CW111_OFFSSTRT_IP (0x2u << 7)
1019 #define GMAC_ST2CW111_OFFSSTRT_TCP_UDP (0x3u << 7)
1020 /* -------- GMAC_ST2CW012 : (GMAC Offset: 0x760) Screening Type 2 Compare Word 0 Register (index = 12) -------- */
1021 #define GMAC_ST2CW012_MASKVAL_Pos 0
1022 #define GMAC_ST2CW012_MASKVAL_Msk (0xffffu << GMAC_ST2CW012_MASKVAL_Pos)
1023 #define GMAC_ST2CW012_MASKVAL(value) ((GMAC_ST2CW012_MASKVAL_Msk & ((value) << GMAC_ST2CW012_MASKVAL_Pos)))
1024 #define GMAC_ST2CW012_COMPVAL_Pos 16
1025 #define GMAC_ST2CW012_COMPVAL_Msk (0xffffu << GMAC_ST2CW012_COMPVAL_Pos)
1026 #define GMAC_ST2CW012_COMPVAL(value) ((GMAC_ST2CW012_COMPVAL_Msk & ((value) << GMAC_ST2CW012_COMPVAL_Pos)))
1027 /* -------- GMAC_ST2CW112 : (GMAC Offset: 0x764) Screening Type 2 Compare Word 1 Register (index = 12) -------- */
1028 #define GMAC_ST2CW112_OFFSVAL_Pos 0
1029 #define GMAC_ST2CW112_OFFSVAL_Msk (0x7fu << GMAC_ST2CW112_OFFSVAL_Pos)
1030 #define GMAC_ST2CW112_OFFSVAL(value) ((GMAC_ST2CW112_OFFSVAL_Msk & ((value) << GMAC_ST2CW112_OFFSVAL_Pos)))
1031 #define GMAC_ST2CW112_OFFSSTRT_Pos 7
1032 #define GMAC_ST2CW112_OFFSSTRT_Msk (0x3u << GMAC_ST2CW112_OFFSSTRT_Pos)
1033 #define GMAC_ST2CW112_OFFSSTRT(value) ((GMAC_ST2CW112_OFFSSTRT_Msk & ((value) << GMAC_ST2CW112_OFFSSTRT_Pos)))
1034 #define GMAC_ST2CW112_OFFSSTRT_FRAMESTART (0x0u << 7)
1035 #define GMAC_ST2CW112_OFFSSTRT_ETHERTYPE (0x1u << 7)
1036 #define GMAC_ST2CW112_OFFSSTRT_IP (0x2u << 7)
1037 #define GMAC_ST2CW112_OFFSSTRT_TCP_UDP (0x3u << 7)
1038 /* -------- GMAC_ST2CW013 : (GMAC Offset: 0x768) Screening Type 2 Compare Word 0 Register (index = 13) -------- */
1039 #define GMAC_ST2CW013_MASKVAL_Pos 0
1040 #define GMAC_ST2CW013_MASKVAL_Msk (0xffffu << GMAC_ST2CW013_MASKVAL_Pos)
1041 #define GMAC_ST2CW013_MASKVAL(value) ((GMAC_ST2CW013_MASKVAL_Msk & ((value) << GMAC_ST2CW013_MASKVAL_Pos)))
1042 #define GMAC_ST2CW013_COMPVAL_Pos 16
1043 #define GMAC_ST2CW013_COMPVAL_Msk (0xffffu << GMAC_ST2CW013_COMPVAL_Pos)
1044 #define GMAC_ST2CW013_COMPVAL(value) ((GMAC_ST2CW013_COMPVAL_Msk & ((value) << GMAC_ST2CW013_COMPVAL_Pos)))
1045 /* -------- GMAC_ST2CW113 : (GMAC Offset: 0x76C) Screening Type 2 Compare Word 1 Register (index = 13) -------- */
1046 #define GMAC_ST2CW113_OFFSVAL_Pos 0
1047 #define GMAC_ST2CW113_OFFSVAL_Msk (0x7fu << GMAC_ST2CW113_OFFSVAL_Pos)
1048 #define GMAC_ST2CW113_OFFSVAL(value) ((GMAC_ST2CW113_OFFSVAL_Msk & ((value) << GMAC_ST2CW113_OFFSVAL_Pos)))
1049 #define GMAC_ST2CW113_OFFSSTRT_Pos 7
1050 #define GMAC_ST2CW113_OFFSSTRT_Msk (0x3u << GMAC_ST2CW113_OFFSSTRT_Pos)
1051 #define GMAC_ST2CW113_OFFSSTRT(value) ((GMAC_ST2CW113_OFFSSTRT_Msk & ((value) << GMAC_ST2CW113_OFFSSTRT_Pos)))
1052 #define GMAC_ST2CW113_OFFSSTRT_FRAMESTART (0x0u << 7)
1053 #define GMAC_ST2CW113_OFFSSTRT_ETHERTYPE (0x1u << 7)
1054 #define GMAC_ST2CW113_OFFSSTRT_IP (0x2u << 7)
1055 #define GMAC_ST2CW113_OFFSSTRT_TCP_UDP (0x3u << 7)
1056 /* -------- GMAC_ST2CW014 : (GMAC Offset: 0x770) Screening Type 2 Compare Word 0 Register (index = 14) -------- */
1057 #define GMAC_ST2CW014_MASKVAL_Pos 0
1058 #define GMAC_ST2CW014_MASKVAL_Msk (0xffffu << GMAC_ST2CW014_MASKVAL_Pos)
1059 #define GMAC_ST2CW014_MASKVAL(value) ((GMAC_ST2CW014_MASKVAL_Msk & ((value) << GMAC_ST2CW014_MASKVAL_Pos)))
1060 #define GMAC_ST2CW014_COMPVAL_Pos 16
1061 #define GMAC_ST2CW014_COMPVAL_Msk (0xffffu << GMAC_ST2CW014_COMPVAL_Pos)
1062 #define GMAC_ST2CW014_COMPVAL(value) ((GMAC_ST2CW014_COMPVAL_Msk & ((value) << GMAC_ST2CW014_COMPVAL_Pos)))
1063 /* -------- GMAC_ST2CW114 : (GMAC Offset: 0x774) Screening Type 2 Compare Word 1 Register (index = 14) -------- */
1064 #define GMAC_ST2CW114_OFFSVAL_Pos 0
1065 #define GMAC_ST2CW114_OFFSVAL_Msk (0x7fu << GMAC_ST2CW114_OFFSVAL_Pos)
1066 #define GMAC_ST2CW114_OFFSVAL(value) ((GMAC_ST2CW114_OFFSVAL_Msk & ((value) << GMAC_ST2CW114_OFFSVAL_Pos)))
1067 #define GMAC_ST2CW114_OFFSSTRT_Pos 7
1068 #define GMAC_ST2CW114_OFFSSTRT_Msk (0x3u << GMAC_ST2CW114_OFFSSTRT_Pos)
1069 #define GMAC_ST2CW114_OFFSSTRT(value) ((GMAC_ST2CW114_OFFSSTRT_Msk & ((value) << GMAC_ST2CW114_OFFSSTRT_Pos)))
1070 #define GMAC_ST2CW114_OFFSSTRT_FRAMESTART (0x0u << 7)
1071 #define GMAC_ST2CW114_OFFSSTRT_ETHERTYPE (0x1u << 7)
1072 #define GMAC_ST2CW114_OFFSSTRT_IP (0x2u << 7)
1073 #define GMAC_ST2CW114_OFFSSTRT_TCP_UDP (0x3u << 7)
1074 /* -------- GMAC_ST2CW015 : (GMAC Offset: 0x778) Screening Type 2 Compare Word 0 Register (index = 15) -------- */
1075 #define GMAC_ST2CW015_MASKVAL_Pos 0
1076 #define GMAC_ST2CW015_MASKVAL_Msk (0xffffu << GMAC_ST2CW015_MASKVAL_Pos)
1077 #define GMAC_ST2CW015_MASKVAL(value) ((GMAC_ST2CW015_MASKVAL_Msk & ((value) << GMAC_ST2CW015_MASKVAL_Pos)))
1078 #define GMAC_ST2CW015_COMPVAL_Pos 16
1079 #define GMAC_ST2CW015_COMPVAL_Msk (0xffffu << GMAC_ST2CW015_COMPVAL_Pos)
1080 #define GMAC_ST2CW015_COMPVAL(value) ((GMAC_ST2CW015_COMPVAL_Msk & ((value) << GMAC_ST2CW015_COMPVAL_Pos)))
1081 /* -------- GMAC_ST2CW115 : (GMAC Offset: 0x77C) Screening Type 2 Compare Word 1 Register (index = 15) -------- */
1082 #define GMAC_ST2CW115_OFFSVAL_Pos 0
1083 #define GMAC_ST2CW115_OFFSVAL_Msk (0x7fu << GMAC_ST2CW115_OFFSVAL_Pos)
1084 #define GMAC_ST2CW115_OFFSVAL(value) ((GMAC_ST2CW115_OFFSVAL_Msk & ((value) << GMAC_ST2CW115_OFFSVAL_Pos)))
1085 #define GMAC_ST2CW115_OFFSSTRT_Pos 7
1086 #define GMAC_ST2CW115_OFFSSTRT_Msk (0x3u << GMAC_ST2CW115_OFFSSTRT_Pos)
1087 #define GMAC_ST2CW115_OFFSSTRT(value) ((GMAC_ST2CW115_OFFSSTRT_Msk & ((value) << GMAC_ST2CW115_OFFSSTRT_Pos)))
1088 #define GMAC_ST2CW115_OFFSSTRT_FRAMESTART (0x0u << 7)
1089 #define GMAC_ST2CW115_OFFSSTRT_ETHERTYPE (0x1u << 7)
1090 #define GMAC_ST2CW115_OFFSSTRT_IP (0x2u << 7)
1091 #define GMAC_ST2CW115_OFFSSTRT_TCP_UDP (0x3u << 7)
1092 /* -------- GMAC_ST2CW016 : (GMAC Offset: 0x780) Screening Type 2 Compare Word 0 Register (index = 16) -------- */
1093 #define GMAC_ST2CW016_MASKVAL_Pos 0
1094 #define GMAC_ST2CW016_MASKVAL_Msk (0xffffu << GMAC_ST2CW016_MASKVAL_Pos)
1095 #define GMAC_ST2CW016_MASKVAL(value) ((GMAC_ST2CW016_MASKVAL_Msk & ((value) << GMAC_ST2CW016_MASKVAL_Pos)))
1096 #define GMAC_ST2CW016_COMPVAL_Pos 16
1097 #define GMAC_ST2CW016_COMPVAL_Msk (0xffffu << GMAC_ST2CW016_COMPVAL_Pos)
1098 #define GMAC_ST2CW016_COMPVAL(value) ((GMAC_ST2CW016_COMPVAL_Msk & ((value) << GMAC_ST2CW016_COMPVAL_Pos)))
1099 /* -------- GMAC_ST2CW116 : (GMAC Offset: 0x784) Screening Type 2 Compare Word 1 Register (index = 16) -------- */
1100 #define GMAC_ST2CW116_OFFSVAL_Pos 0
1101 #define GMAC_ST2CW116_OFFSVAL_Msk (0x7fu << GMAC_ST2CW116_OFFSVAL_Pos)
1102 #define GMAC_ST2CW116_OFFSVAL(value) ((GMAC_ST2CW116_OFFSVAL_Msk & ((value) << GMAC_ST2CW116_OFFSVAL_Pos)))
1103 #define GMAC_ST2CW116_OFFSSTRT_Pos 7
1104 #define GMAC_ST2CW116_OFFSSTRT_Msk (0x3u << GMAC_ST2CW116_OFFSSTRT_Pos)
1105 #define GMAC_ST2CW116_OFFSSTRT(value) ((GMAC_ST2CW116_OFFSSTRT_Msk & ((value) << GMAC_ST2CW116_OFFSSTRT_Pos)))
1106 #define GMAC_ST2CW116_OFFSSTRT_FRAMESTART (0x0u << 7)
1107 #define GMAC_ST2CW116_OFFSSTRT_ETHERTYPE (0x1u << 7)
1108 #define GMAC_ST2CW116_OFFSSTRT_IP (0x2u << 7)
1109 #define GMAC_ST2CW116_OFFSSTRT_TCP_UDP (0x3u << 7)
1110 /* -------- GMAC_ST2CW017 : (GMAC Offset: 0x788) Screening Type 2 Compare Word 0 Register (index = 17) -------- */
1111 #define GMAC_ST2CW017_MASKVAL_Pos 0
1112 #define GMAC_ST2CW017_MASKVAL_Msk (0xffffu << GMAC_ST2CW017_MASKVAL_Pos)
1113 #define GMAC_ST2CW017_MASKVAL(value) ((GMAC_ST2CW017_MASKVAL_Msk & ((value) << GMAC_ST2CW017_MASKVAL_Pos)))
1114 #define GMAC_ST2CW017_COMPVAL_Pos 16
1115 #define GMAC_ST2CW017_COMPVAL_Msk (0xffffu << GMAC_ST2CW017_COMPVAL_Pos)
1116 #define GMAC_ST2CW017_COMPVAL(value) ((GMAC_ST2CW017_COMPVAL_Msk & ((value) << GMAC_ST2CW017_COMPVAL_Pos)))
1117 /* -------- GMAC_ST2CW117 : (GMAC Offset: 0x78C) Screening Type 2 Compare Word 1 Register (index = 17) -------- */
1118 #define GMAC_ST2CW117_OFFSVAL_Pos 0
1119 #define GMAC_ST2CW117_OFFSVAL_Msk (0x7fu << GMAC_ST2CW117_OFFSVAL_Pos)
1120 #define GMAC_ST2CW117_OFFSVAL(value) ((GMAC_ST2CW117_OFFSVAL_Msk & ((value) << GMAC_ST2CW117_OFFSVAL_Pos)))
1121 #define GMAC_ST2CW117_OFFSSTRT_Pos 7
1122 #define GMAC_ST2CW117_OFFSSTRT_Msk (0x3u << GMAC_ST2CW117_OFFSSTRT_Pos)
1123 #define GMAC_ST2CW117_OFFSSTRT(value) ((GMAC_ST2CW117_OFFSSTRT_Msk & ((value) << GMAC_ST2CW117_OFFSSTRT_Pos)))
1124 #define GMAC_ST2CW117_OFFSSTRT_FRAMESTART (0x0u << 7)
1125 #define GMAC_ST2CW117_OFFSSTRT_ETHERTYPE (0x1u << 7)
1126 #define GMAC_ST2CW117_OFFSSTRT_IP (0x2u << 7)
1127 #define GMAC_ST2CW117_OFFSSTRT_TCP_UDP (0x3u << 7)
1128 /* -------- GMAC_ST2CW018 : (GMAC Offset: 0x790) Screening Type 2 Compare Word 0 Register (index = 18) -------- */
1129 #define GMAC_ST2CW018_MASKVAL_Pos 0
1130 #define GMAC_ST2CW018_MASKVAL_Msk (0xffffu << GMAC_ST2CW018_MASKVAL_Pos)
1131 #define GMAC_ST2CW018_MASKVAL(value) ((GMAC_ST2CW018_MASKVAL_Msk & ((value) << GMAC_ST2CW018_MASKVAL_Pos)))
1132 #define GMAC_ST2CW018_COMPVAL_Pos 16
1133 #define GMAC_ST2CW018_COMPVAL_Msk (0xffffu << GMAC_ST2CW018_COMPVAL_Pos)
1134 #define GMAC_ST2CW018_COMPVAL(value) ((GMAC_ST2CW018_COMPVAL_Msk & ((value) << GMAC_ST2CW018_COMPVAL_Pos)))
1135 /* -------- GMAC_ST2CW118 : (GMAC Offset: 0x794) Screening Type 2 Compare Word 1 Register (index = 18) -------- */
1136 #define GMAC_ST2CW118_OFFSVAL_Pos 0
1137 #define GMAC_ST2CW118_OFFSVAL_Msk (0x7fu << GMAC_ST2CW118_OFFSVAL_Pos)
1138 #define GMAC_ST2CW118_OFFSVAL(value) ((GMAC_ST2CW118_OFFSVAL_Msk & ((value) << GMAC_ST2CW118_OFFSVAL_Pos)))
1139 #define GMAC_ST2CW118_OFFSSTRT_Pos 7
1140 #define GMAC_ST2CW118_OFFSSTRT_Msk (0x3u << GMAC_ST2CW118_OFFSSTRT_Pos)
1141 #define GMAC_ST2CW118_OFFSSTRT(value) ((GMAC_ST2CW118_OFFSSTRT_Msk & ((value) << GMAC_ST2CW118_OFFSSTRT_Pos)))
1142 #define GMAC_ST2CW118_OFFSSTRT_FRAMESTART (0x0u << 7)
1143 #define GMAC_ST2CW118_OFFSSTRT_ETHERTYPE (0x1u << 7)
1144 #define GMAC_ST2CW118_OFFSSTRT_IP (0x2u << 7)
1145 #define GMAC_ST2CW118_OFFSSTRT_TCP_UDP (0x3u << 7)
1146 /* -------- GMAC_ST2CW019 : (GMAC Offset: 0x798) Screening Type 2 Compare Word 0 Register (index = 19) -------- */
1147 #define GMAC_ST2CW019_MASKVAL_Pos 0
1148 #define GMAC_ST2CW019_MASKVAL_Msk (0xffffu << GMAC_ST2CW019_MASKVAL_Pos)
1149 #define GMAC_ST2CW019_MASKVAL(value) ((GMAC_ST2CW019_MASKVAL_Msk & ((value) << GMAC_ST2CW019_MASKVAL_Pos)))
1150 #define GMAC_ST2CW019_COMPVAL_Pos 16
1151 #define GMAC_ST2CW019_COMPVAL_Msk (0xffffu << GMAC_ST2CW019_COMPVAL_Pos)
1152 #define GMAC_ST2CW019_COMPVAL(value) ((GMAC_ST2CW019_COMPVAL_Msk & ((value) << GMAC_ST2CW019_COMPVAL_Pos)))
1153 /* -------- GMAC_ST2CW119 : (GMAC Offset: 0x79C) Screening Type 2 Compare Word 1 Register (index = 19) -------- */
1154 #define GMAC_ST2CW119_OFFSVAL_Pos 0
1155 #define GMAC_ST2CW119_OFFSVAL_Msk (0x7fu << GMAC_ST2CW119_OFFSVAL_Pos)
1156 #define GMAC_ST2CW119_OFFSVAL(value) ((GMAC_ST2CW119_OFFSVAL_Msk & ((value) << GMAC_ST2CW119_OFFSVAL_Pos)))
1157 #define GMAC_ST2CW119_OFFSSTRT_Pos 7
1158 #define GMAC_ST2CW119_OFFSSTRT_Msk (0x3u << GMAC_ST2CW119_OFFSSTRT_Pos)
1159 #define GMAC_ST2CW119_OFFSSTRT(value) ((GMAC_ST2CW119_OFFSSTRT_Msk & ((value) << GMAC_ST2CW119_OFFSSTRT_Pos)))
1160 #define GMAC_ST2CW119_OFFSSTRT_FRAMESTART (0x0u << 7)
1161 #define GMAC_ST2CW119_OFFSSTRT_ETHERTYPE (0x1u << 7)
1162 #define GMAC_ST2CW119_OFFSSTRT_IP (0x2u << 7)
1163 #define GMAC_ST2CW119_OFFSSTRT_TCP_UDP (0x3u << 7)
1164 /* -------- GMAC_ST2CW020 : (GMAC Offset: 0x7A0) Screening Type 2 Compare Word 0 Register (index = 20) -------- */
1165 #define GMAC_ST2CW020_MASKVAL_Pos 0
1166 #define GMAC_ST2CW020_MASKVAL_Msk (0xffffu << GMAC_ST2CW020_MASKVAL_Pos)
1167 #define GMAC_ST2CW020_MASKVAL(value) ((GMAC_ST2CW020_MASKVAL_Msk & ((value) << GMAC_ST2CW020_MASKVAL_Pos)))
1168 #define GMAC_ST2CW020_COMPVAL_Pos 16
1169 #define GMAC_ST2CW020_COMPVAL_Msk (0xffffu << GMAC_ST2CW020_COMPVAL_Pos)
1170 #define GMAC_ST2CW020_COMPVAL(value) ((GMAC_ST2CW020_COMPVAL_Msk & ((value) << GMAC_ST2CW020_COMPVAL_Pos)))
1171 /* -------- GMAC_ST2CW120 : (GMAC Offset: 0x7A4) Screening Type 2 Compare Word 1 Register (index = 20) -------- */
1172 #define GMAC_ST2CW120_OFFSVAL_Pos 0
1173 #define GMAC_ST2CW120_OFFSVAL_Msk (0x7fu << GMAC_ST2CW120_OFFSVAL_Pos)
1174 #define GMAC_ST2CW120_OFFSVAL(value) ((GMAC_ST2CW120_OFFSVAL_Msk & ((value) << GMAC_ST2CW120_OFFSVAL_Pos)))
1175 #define GMAC_ST2CW120_OFFSSTRT_Pos 7
1176 #define GMAC_ST2CW120_OFFSSTRT_Msk (0x3u << GMAC_ST2CW120_OFFSSTRT_Pos)
1177 #define GMAC_ST2CW120_OFFSSTRT(value) ((GMAC_ST2CW120_OFFSSTRT_Msk & ((value) << GMAC_ST2CW120_OFFSSTRT_Pos)))
1178 #define GMAC_ST2CW120_OFFSSTRT_FRAMESTART (0x0u << 7)
1179 #define GMAC_ST2CW120_OFFSSTRT_ETHERTYPE (0x1u << 7)
1180 #define GMAC_ST2CW120_OFFSSTRT_IP (0x2u << 7)
1181 #define GMAC_ST2CW120_OFFSSTRT_TCP_UDP (0x3u << 7)
1182 /* -------- GMAC_ST2CW021 : (GMAC Offset: 0x7A8) Screening Type 2 Compare Word 0 Register (index = 21) -------- */
1183 #define GMAC_ST2CW021_MASKVAL_Pos 0
1184 #define GMAC_ST2CW021_MASKVAL_Msk (0xffffu << GMAC_ST2CW021_MASKVAL_Pos)
1185 #define GMAC_ST2CW021_MASKVAL(value) ((GMAC_ST2CW021_MASKVAL_Msk & ((value) << GMAC_ST2CW021_MASKVAL_Pos)))
1186 #define GMAC_ST2CW021_COMPVAL_Pos 16
1187 #define GMAC_ST2CW021_COMPVAL_Msk (0xffffu << GMAC_ST2CW021_COMPVAL_Pos)
1188 #define GMAC_ST2CW021_COMPVAL(value) ((GMAC_ST2CW021_COMPVAL_Msk & ((value) << GMAC_ST2CW021_COMPVAL_Pos)))
1189 /* -------- GMAC_ST2CW121 : (GMAC Offset: 0x7AC) Screening Type 2 Compare Word 1 Register (index = 21) -------- */
1190 #define GMAC_ST2CW121_OFFSVAL_Pos 0
1191 #define GMAC_ST2CW121_OFFSVAL_Msk (0x7fu << GMAC_ST2CW121_OFFSVAL_Pos)
1192 #define GMAC_ST2CW121_OFFSVAL(value) ((GMAC_ST2CW121_OFFSVAL_Msk & ((value) << GMAC_ST2CW121_OFFSVAL_Pos)))
1193 #define GMAC_ST2CW121_OFFSSTRT_Pos 7
1194 #define GMAC_ST2CW121_OFFSSTRT_Msk (0x3u << GMAC_ST2CW121_OFFSSTRT_Pos)
1195 #define GMAC_ST2CW121_OFFSSTRT(value) ((GMAC_ST2CW121_OFFSSTRT_Msk & ((value) << GMAC_ST2CW121_OFFSSTRT_Pos)))
1196 #define GMAC_ST2CW121_OFFSSTRT_FRAMESTART (0x0u << 7)
1197 #define GMAC_ST2CW121_OFFSSTRT_ETHERTYPE (0x1u << 7)
1198 #define GMAC_ST2CW121_OFFSSTRT_IP (0x2u << 7)
1199 #define GMAC_ST2CW121_OFFSSTRT_TCP_UDP (0x3u << 7)
1200 /* -------- GMAC_ST2CW022 : (GMAC Offset: 0x7B0) Screening Type 2 Compare Word 0 Register (index = 22) -------- */
1201 #define GMAC_ST2CW022_MASKVAL_Pos 0
1202 #define GMAC_ST2CW022_MASKVAL_Msk (0xffffu << GMAC_ST2CW022_MASKVAL_Pos)
1203 #define GMAC_ST2CW022_MASKVAL(value) ((GMAC_ST2CW022_MASKVAL_Msk & ((value) << GMAC_ST2CW022_MASKVAL_Pos)))
1204 #define GMAC_ST2CW022_COMPVAL_Pos 16
1205 #define GMAC_ST2CW022_COMPVAL_Msk (0xffffu << GMAC_ST2CW022_COMPVAL_Pos)
1206 #define GMAC_ST2CW022_COMPVAL(value) ((GMAC_ST2CW022_COMPVAL_Msk & ((value) << GMAC_ST2CW022_COMPVAL_Pos)))
1207 /* -------- GMAC_ST2CW122 : (GMAC Offset: 0x7B4) Screening Type 2 Compare Word 1 Register (index = 22) -------- */
1208 #define GMAC_ST2CW122_OFFSVAL_Pos 0
1209 #define GMAC_ST2CW122_OFFSVAL_Msk (0x7fu << GMAC_ST2CW122_OFFSVAL_Pos)
1210 #define GMAC_ST2CW122_OFFSVAL(value) ((GMAC_ST2CW122_OFFSVAL_Msk & ((value) << GMAC_ST2CW122_OFFSVAL_Pos)))
1211 #define GMAC_ST2CW122_OFFSSTRT_Pos 7
1212 #define GMAC_ST2CW122_OFFSSTRT_Msk (0x3u << GMAC_ST2CW122_OFFSSTRT_Pos)
1213 #define GMAC_ST2CW122_OFFSSTRT(value) ((GMAC_ST2CW122_OFFSSTRT_Msk & ((value) << GMAC_ST2CW122_OFFSSTRT_Pos)))
1214 #define GMAC_ST2CW122_OFFSSTRT_FRAMESTART (0x0u << 7)
1215 #define GMAC_ST2CW122_OFFSSTRT_ETHERTYPE (0x1u << 7)
1216 #define GMAC_ST2CW122_OFFSSTRT_IP (0x2u << 7)
1217 #define GMAC_ST2CW122_OFFSSTRT_TCP_UDP (0x3u << 7)
1218 /* -------- GMAC_ST2CW023 : (GMAC Offset: 0x7B8) Screening Type 2 Compare Word 0 Register (index = 23) -------- */
1219 #define GMAC_ST2CW023_MASKVAL_Pos 0
1220 #define GMAC_ST2CW023_MASKVAL_Msk (0xffffu << GMAC_ST2CW023_MASKVAL_Pos)
1221 #define GMAC_ST2CW023_MASKVAL(value) ((GMAC_ST2CW023_MASKVAL_Msk & ((value) << GMAC_ST2CW023_MASKVAL_Pos)))
1222 #define GMAC_ST2CW023_COMPVAL_Pos 16
1223 #define GMAC_ST2CW023_COMPVAL_Msk (0xffffu << GMAC_ST2CW023_COMPVAL_Pos)
1224 #define GMAC_ST2CW023_COMPVAL(value) ((GMAC_ST2CW023_COMPVAL_Msk & ((value) << GMAC_ST2CW023_COMPVAL_Pos)))
1225 /* -------- GMAC_ST2CW123 : (GMAC Offset: 0x7BC) Screening Type 2 Compare Word 1 Register (index = 23) -------- */
1226 #define GMAC_ST2CW123_OFFSVAL_Pos 0
1227 #define GMAC_ST2CW123_OFFSVAL_Msk (0x7fu << GMAC_ST2CW123_OFFSVAL_Pos)
1228 #define GMAC_ST2CW123_OFFSVAL(value) ((GMAC_ST2CW123_OFFSVAL_Msk & ((value) << GMAC_ST2CW123_OFFSVAL_Pos)))
1229 #define GMAC_ST2CW123_OFFSSTRT_Pos 7
1230 #define GMAC_ST2CW123_OFFSSTRT_Msk (0x3u << GMAC_ST2CW123_OFFSSTRT_Pos)
1231 #define GMAC_ST2CW123_OFFSSTRT(value) ((GMAC_ST2CW123_OFFSSTRT_Msk & ((value) << GMAC_ST2CW123_OFFSSTRT_Pos)))
1232 #define GMAC_ST2CW123_OFFSSTRT_FRAMESTART (0x0u << 7)
1233 #define GMAC_ST2CW123_OFFSSTRT_ETHERTYPE (0x1u << 7)
1234 #define GMAC_ST2CW123_OFFSSTRT_IP (0x2u << 7)
1235 #define GMAC_ST2CW123_OFFSSTRT_TCP_UDP (0x3u << 7)
1238 
1239 
1240 #endif /* _SAME70_GMAC_COMPONENT_ */
Gmac::GMAC_LFFE
__I uint32_t GMAC_LFFE
(Gmac Offset: 0x194) Length Field Frame Errors Register
Definition: component_gmac.h:135
Gmac::GMAC_TA
__O uint32_t GMAC_TA
(Gmac Offset: 0x1D8) 1588 Timer Adjust Register
Definition: component_gmac.h:149
Gmac::GMAC_TIDM4
__IO uint32_t GMAC_TIDM4
(Gmac Offset: 0x0B4) Type ID Match 4 Register
Definition: component_gmac.h:82
Gmac::GMAC_SCF
__I uint32_t GMAC_SCF
(Gmac Offset: 0x138) Single Collision Frames Register
Definition: component_gmac.h:112
Gmac::GMAC_UR
__IO uint32_t GMAC_UR
(Gmac Offset: 0x00C) User Register
Definition: component_gmac.h:59
Gmac::GMAC_DCFGR
__IO uint32_t GMAC_DCFGR
(Gmac Offset: 0x010) DMA Configuration Register
Definition: component_gmac.h:60
Gmac::GMAC_OFR
__I uint32_t GMAC_OFR
(Gmac Offset: 0x188) Oversize Frames Received Register
Definition: component_gmac.h:132
Gmac::GMAC_TIDM3
__IO uint32_t GMAC_TIDM3
(Gmac Offset: 0x0B0) Type ID Match 3 Register
Definition: component_gmac.h:81
Gmac::GMAC_RJFML
__IO uint32_t GMAC_RJFML
(Gmac Offset: 0x048) RX Jumbo Frame Max Length Register
Definition: component_gmac.h:74
Gmac::GMAC_RSE
__I uint32_t GMAC_RSE
(Gmac Offset: 0x198) Receive Symbol Errors Register
Definition: component_gmac.h:136
Gmac::GMAC_RRE
__I uint32_t GMAC_RRE
(Gmac Offset: 0x1A0) Receive Resource Errors Register
Definition: component_gmac.h:138
Gmac::GMAC_EFRN
__I uint32_t GMAC_EFRN
(Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register
Definition: component_gmac.h:154
Gmac
Definition: component_gmac.h:55
Gmac::GMAC_EC
__I uint32_t GMAC_EC
(Gmac Offset: 0x140) Excessive Collisions Register
Definition: component_gmac.h:114
Gmac::GMAC_MCF
__I uint32_t GMAC_MCF
(Gmac Offset: 0x13C) Multiple Collision Frames Register
Definition: component_gmac.h:113
Gmac::GMAC_TBFR127
__I uint32_t GMAC_TBFR127
(Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register
Definition: component_gmac.h:125
Gmac::GMAC_TBFR255
__I uint32_t GMAC_TBFR255
(Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register
Definition: component_gmac.h:126
Gmac::GMAC_CBSISQB
__IO uint32_t GMAC_CBSISQB
(Gmac Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B
Definition: component_gmac.h:170
Gmac::GMAC_IDR
__O uint32_t GMAC_IDR
(Gmac Offset: 0x02C) Interrupt Disable Register
Definition: component_gmac.h:67
__IO
#define __IO
Definition: core_cm7.h:287
Gmac::GMAC_PEFRSH
__I uint32_t GMAC_PEFRSH
(Gmac Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register
Definition: component_gmac.h:96
Gmac::GMAC_OTLO
__I uint32_t GMAC_OTLO
(Gmac Offset: 0x100) Octets Transmitted Low Register
Definition: component_gmac.h:98
Gmac::GMAC_CSE
__I uint32_t GMAC_CSE
(Gmac Offset: 0x14C) Carrier Sense Errors Register
Definition: component_gmac.h:117
Gmac::GMAC_PEFRN
__I uint32_t GMAC_PEFRN
(Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register
Definition: component_gmac.h:158
Gmac::GMAC_TBFT511
__I uint32_t GMAC_TBFT511
(Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register
Definition: component_gmac.h:107
__O
#define __O
Definition: core_cm7.h:286
Gmac::GMAC_TISUBN
__IO uint32_t GMAC_TISUBN
(Gmac Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register
Definition: component_gmac.h:144
Gmac::GMAC_TN
__IO uint32_t GMAC_TN
(Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register
Definition: component_gmac.h:148
Gmac::GMAC_MFT
__I uint32_t GMAC_MFT
(Gmac Offset: 0x110) Multicast Frames Transmitted Register
Definition: component_gmac.h:102
Gmac::GMAC_TBFT1023
__I uint32_t GMAC_TBFT1023
(Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register
Definition: component_gmac.h:108
Gmac::GMAC_EFTN
__I uint32_t GMAC_EFTN
(Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register
Definition: component_gmac.h:152
Gmac::GMAC_TPFCP
__IO uint32_t GMAC_TPFCP
(Gmac Offset: 0x0C4) Transmit PFC Pause Register
Definition: component_gmac.h:86
Gmac::GMAC_PEFRSL
__I uint32_t GMAC_PEFRSL
(Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register
Definition: component_gmac.h:157
Gmac::GMAC_TSL
__IO uint32_t GMAC_TSL
(Gmac Offset: 0x1D0) 1588 Timer Seconds Low Register
Definition: component_gmac.h:147
Gmac::GMAC_NSC
__IO uint32_t GMAC_NSC
(Gmac Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register
Definition: component_gmac.h:90
Gmac::GMAC_TBFT255
__I uint32_t GMAC_TBFT255
(Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register
Definition: component_gmac.h:106
Gmac::GMAC_SCH
__IO uint32_t GMAC_SCH
(Gmac Offset: 0x0E4) 1588 Timer Second Comparison High Register
Definition: component_gmac.h:92
Gmac::GMAC_PFT
__I uint32_t GMAC_PFT
(Gmac Offset: 0x114) Pause Frames Transmitted Register
Definition: component_gmac.h:103
Gmac::GMAC_TBFR1023
__I uint32_t GMAC_TBFR1023
(Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register
Definition: component_gmac.h:128
Gmac::GMAC_PFR
__I uint32_t GMAC_PFR
(Gmac Offset: 0x164) Pause Frames Received Register
Definition: component_gmac.h:123
Gmac::GMAC_NCR
__IO uint32_t GMAC_NCR
(Gmac Offset: 0x000) Network Control Register
Definition: component_gmac.h:56
Gmac::GMAC_TBFT127
__I uint32_t GMAC_TBFT127
(Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register
Definition: component_gmac.h:105
Gmac::GMAC_SCL
__IO uint32_t GMAC_SCL
(Gmac Offset: 0x0E0) 1588 Timer Second Comparison Low Register
Definition: component_gmac.h:91
GmacSt2Compare::GMAC_ST2COM0
__IO uint32_t GMAC_ST2COM0
31:16 - Compare Value. 15:0 - Mask Value.
Definition: component_gmac.h:48
Gmac::GMAC_TCE
__I uint32_t GMAC_TCE
(Gmac Offset: 0x1AC) TCP Checksum Errors Register
Definition: component_gmac.h:141
GmacSa::GMAC_SAB
__IO uint32_t GMAC_SAB
(GmacSa Offset: 0x0) Specific Address 1 Bottom Register
Definition: component_gmac.h:42
Gmac::GMAC_JR
__I uint32_t GMAC_JR
(Gmac Offset: 0x18C) Jabbers Received Register
Definition: component_gmac.h:133
Gmac::GMAC_TBFR511
__I uint32_t GMAC_TBFR511
(Gmac Offset: 0x174) 256 to 511 Byte Frames Received Register
Definition: component_gmac.h:127
Gmac::GMAC_TSH
__IO uint32_t GMAC_TSH
(Gmac Offset: 0x1C0) 1588 Timer Seconds High Register
Definition: component_gmac.h:145
Gmac::GMAC_NSR
__I uint32_t GMAC_NSR
(Gmac Offset: 0x008) Network Status Register
Definition: component_gmac.h:58
Gmac::GMAC_TMXBFR
__I uint32_t GMAC_TMXBFR
(Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register
Definition: component_gmac.h:130
Gmac::GMAC_FT
__I uint32_t GMAC_FT
(Gmac Offset: 0x108) Frames Transmitted Register
Definition: component_gmac.h:100
Gmac::GMAC_DTF
__I uint32_t GMAC_DTF
(Gmac Offset: 0x148) Deferred Transmission Frames Register
Definition: component_gmac.h:116
Gmac::GMAC_TIDM1
__IO uint32_t GMAC_TIDM1
(Gmac Offset: 0x0A8) Type ID Match 1 Register
Definition: component_gmac.h:79
Gmac::GMAC_TI
__IO uint32_t GMAC_TI
(Gmac Offset: 0x1DC) 1588 Timer Increment Register
Definition: component_gmac.h:150
GmacSa::GMAC_SAT
__IO uint32_t GMAC_SAT
(GmacSa Offset: 0x4) Specific Address 1 Top Register
Definition: component_gmac.h:43
Gmac::GMAC_TPQ
__IO uint32_t GMAC_TPQ
(Gmac Offset: 0x03C) Transmit Pause Quantum Register
Definition: component_gmac.h:71
Gmac::GMAC_RSR
__IO uint32_t GMAC_RSR
(Gmac Offset: 0x020) Receive Status Register
Definition: component_gmac.h:64
Gmac::GMAC_RPQ
__I uint32_t GMAC_RPQ
(Gmac Offset: 0x038) Received Pause Quantum Register
Definition: component_gmac.h:70
Gmac::GMAC_HRT
__IO uint32_t GMAC_HRT
(Gmac Offset: 0x084) Hash Register Top
Definition: component_gmac.h:77
GMACSA_NUMBER
#define GMACSA_NUMBER
Gmac hardware registers.
Definition: component_gmac.h:53
Gmac::GMAC_LC
__I uint32_t GMAC_LC
(Gmac Offset: 0x144) Late Collisions Register
Definition: component_gmac.h:115
Gmac::GMAC_RPSF
__IO uint32_t GMAC_RPSF
(Gmac Offset: 0x044) RX Partial Store and Forward Register
Definition: component_gmac.h:73
Gmac::GMAC_IMR
__IO uint32_t GMAC_IMR
(Gmac Offset: 0x030) Interrupt Mask Register
Definition: component_gmac.h:68
Gmac::GMAC_FR
__I uint32_t GMAC_FR
(Gmac Offset: 0x158) Frames Received Register
Definition: component_gmac.h:120
Gmac::GMAC_AE
__I uint32_t GMAC_AE
(Gmac Offset: 0x19C) Alignment Errors Register
Definition: component_gmac.h:137
Gmac::GMAC_TIDM2
__IO uint32_t GMAC_TIDM2
(Gmac Offset: 0x0AC) Type ID Match 2 Register
Definition: component_gmac.h:80
Gmac::GMAC_OTHI
__I uint32_t GMAC_OTHI
(Gmac Offset: 0x104) Octets Transmitted High Register
Definition: component_gmac.h:99
Gmac::GMAC_EFRSL
__I uint32_t GMAC_EFRSL
(Gmac Offset: 0x1E8) PTP Event Frame Received Seconds Low Register
Definition: component_gmac.h:153
Gmac::GMAC_TUR
__I uint32_t GMAC_TUR
(Gmac Offset: 0x134) Transmit Underruns Register
Definition: component_gmac.h:111
GmacSa
GmacSa hardware registers.
Definition: component_gmac.h:41
Gmac::GMAC_SAMT1
__IO uint32_t GMAC_SAMT1
(Gmac Offset: 0x0CC) Specific Address 1 Mask Top Register
Definition: component_gmac.h:88
Gmac::GMAC_WOL
__IO uint32_t GMAC_WOL
(Gmac Offset: 0x0B8) Wake on LAN Register
Definition: component_gmac.h:83
Gmac::GMAC_UCE
__I uint32_t GMAC_UCE
(Gmac Offset: 0x1B0) UDP Checksum Errors Register
Definition: component_gmac.h:142
Gmac::GMAC_EFTSL
__I uint32_t GMAC_EFTSL
(Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register
Definition: component_gmac.h:151
Gmac::GMAC_SAMB1
__IO uint32_t GMAC_SAMB1
(Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom Register
Definition: component_gmac.h:87
Gmac::GMAC_BFT64
__I uint32_t GMAC_BFT64
(Gmac Offset: 0x118) 64 Byte Frames Transmitted Register
Definition: component_gmac.h:104
Gmac::GMAC_UFR
__I uint32_t GMAC_UFR
(Gmac Offset: 0x184) Undersize Frames Received Register
Definition: component_gmac.h:131
Gmac::GMAC_ORLO
__I uint32_t GMAC_ORLO
(Gmac Offset: 0x150) Octets Received Low Received Register
Definition: component_gmac.h:118
Gmac::GMAC_RBQB
__IO uint32_t GMAC_RBQB
(Gmac Offset: 0x018) Receive Buffer Queue Base Address Register
Definition: component_gmac.h:62
Gmac::GMAC_BCFR
__I uint32_t GMAC_BCFR
(Gmac Offset: 0x15C) Broadcast Frames Received Register
Definition: component_gmac.h:121
Gmac::GMAC_PEFTN
__I uint32_t GMAC_PEFTN
(Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register
Definition: component_gmac.h:156
Gmac::GMAC_CBSISQA
__IO uint32_t GMAC_CBSISQA
(Gmac Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A
Definition: component_gmac.h:169
Gmac::GMAC_TPSF
__IO uint32_t GMAC_TPSF
(Gmac Offset: 0x040) TX Partial Store and Forward Register
Definition: component_gmac.h:72
Gmac::GMAC_TBFT1518
__I uint32_t GMAC_TBFT1518
(Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register
Definition: component_gmac.h:109
Gmac::GMAC_IER
__O uint32_t GMAC_IER
(Gmac Offset: 0x028) Interrupt Enable Register
Definition: component_gmac.h:66
Gmac::GMAC_CBSCR
__IO uint32_t GMAC_CBSCR
(Gmac Offset: 0x4BC) Credit-Based Shaping Control Register
Definition: component_gmac.h:168
Gmac::GMAC_NCFGR
__IO uint32_t GMAC_NCFGR
(Gmac Offset: 0x004) Network Configuration Register
Definition: component_gmac.h:57
Gmac::GMAC_MFR
__I uint32_t GMAC_MFR
(Gmac Offset: 0x160) Multicast Frames Received Register
Definition: component_gmac.h:122
Gmac::GMAC_IPGS
__IO uint32_t GMAC_IPGS
(Gmac Offset: 0x0BC) IPG Stretch Register
Definition: component_gmac.h:84
Gmac::GMAC_HRB
__IO uint32_t GMAC_HRB
(Gmac Offset: 0x080) Hash Register Bottom
Definition: component_gmac.h:76
Gmac::GMAC_PEFTSL
__I uint32_t GMAC_PEFTSL
(Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register
Definition: component_gmac.h:155
Gmac::GMAC_GTBFT1518
__I uint32_t GMAC_GTBFT1518
(Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register
Definition: component_gmac.h:110
Gmac::GMAC_EFTSH
__I uint32_t GMAC_EFTSH
(Gmac Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register
Definition: component_gmac.h:93
Gmac::GMAC_BFR64
__I uint32_t GMAC_BFR64
(Gmac Offset: 0x168) 64 Byte Frames Received Register
Definition: component_gmac.h:124
Gmac::GMAC_BCFT
__I uint32_t GMAC_BCFT
(Gmac Offset: 0x10C) Broadcast Frames Transmitted Register
Definition: component_gmac.h:101
Gmac::GMAC_ISR
__I uint32_t GMAC_ISR
(Gmac Offset: 0x024) Interrupt Status Register
Definition: component_gmac.h:65
Gmac::GMAC_TBQB
__IO uint32_t GMAC_TBQB
(Gmac Offset: 0x01C) Transmit Buffer Queue Base Address Register
Definition: component_gmac.h:63
Gmac::GMAC_FCSE
__I uint32_t GMAC_FCSE
(Gmac Offset: 0x190) Frame Check Sequence Errors Register
Definition: component_gmac.h:134
Gmac::GMAC_SVLAN
__IO uint32_t GMAC_SVLAN
(Gmac Offset: 0x0C0) Stacked VLAN Register
Definition: component_gmac.h:85
Gmac::GMAC_ORHI
__I uint32_t GMAC_ORHI
(Gmac Offset: 0x154) Octets Received High Received Register
Definition: component_gmac.h:119
GmacSt2Compare
GmacSt2Compare hardware registers.
Definition: component_gmac.h:47
Gmac::GMAC_ROE
__I uint32_t GMAC_ROE
(Gmac Offset: 0x1A4) Receive Overrun Register
Definition: component_gmac.h:139
Gmac::GMAC_TBFR1518
__I uint32_t GMAC_TBFR1518
(Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register
Definition: component_gmac.h:129
Gmac::GMAC_EFRSH
__I uint32_t GMAC_EFRSH
(Gmac Offset: 0x0EC) PTP Event Frame Received Seconds High Register
Definition: component_gmac.h:94
Gmac::GMAC_IHCE
__I uint32_t GMAC_IHCE
(Gmac Offset: 0x1A8) IP Header Checksum Errors Register
Definition: component_gmac.h:140
Gmac::GMAC_PEFTSH
__I uint32_t GMAC_PEFTSH
(Gmac Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register
Definition: component_gmac.h:95
Gmac::GMAC_TSR
__IO uint32_t GMAC_TSR
(Gmac Offset: 0x014) Transmit Status Register
Definition: component_gmac.h:61
GmacSt2Compare::GMAC_ST2COM1
__IO uint32_t GMAC_ST2COM1
31:9 - Reserved; 8:7 - Offset location in frame; 6:0 Offset value in bytes
Definition: component_gmac.h:49
__I
#define __I
Definition: core_cm7.h:284
Gmac::GMAC_MAN
__IO uint32_t GMAC_MAN
(Gmac Offset: 0x034) PHY Maintenance Register
Definition: component_gmac.h:69
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