component_chipid.h

/* ---------------------------------------------------------------------------- */
/*                  Atmel Microcontroller Software Support                      */
/*                       SAM Software Package License                           */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) 2015, Atmel Corporation                                        */
/*                                                                              */
/* All rights reserved.                                                         */
/*                                                                              */
/* Redistribution and use in source and binary forms, with or without           */
/* modification, are permitted provided that the following condition is met:    */
/*                                                                              */
/* - Redistributions of source code must retain the above copyright notice,     */
/* this list of conditions and the disclaimer below.                            */
/*                                                                              */
/* Atmel's name may not be used to endorse or promote products derived from     */
/* this software without specific prior written permission.                     */
/*                                                                              */
/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
/* ---------------------------------------------------------------------------- */

#ifndef _SAME70_CHIPID_COMPONENT_
#define _SAME70_CHIPID_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  __I uint32_t CHIPID_CIDR; 
  __I uint32_t CHIPID_EXID; 
} Chipid;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
#define CHIPID_CIDR_VERSION_Pos 0
#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) 
#define CHIPID_CIDR_EPROC_Pos 5
#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) 
#define   CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5) 
#define   CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) 
#define   CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) 
#define   CHIPID_CIDR_EPROC_CM3 (0x3u << 5) 
#define   CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) 
#define   CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) 
#define   CHIPID_CIDR_EPROC_CA5 (0x6u << 5) 
#define   CHIPID_CIDR_EPROC_CM4 (0x7u << 5) 
#define CHIPID_CIDR_NVPSIZ_Pos 8
#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) 
#define   CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) 
#define   CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) 
#define   CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) 
#define   CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) 
#define   CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) 
#define   CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) 
#define   CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) 
#define   CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) 
#define   CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) 
#define   CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) 
#define   CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) 
#define CHIPID_CIDR_NVPSIZ2_Pos 12
#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) 
#define   CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) 
#define   CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) 
#define   CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) 
#define   CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) 
#define   CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) 
#define   CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) 
#define   CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) 
#define   CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) 
#define   CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) 
#define   CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) 
#define CHIPID_CIDR_SRAMSIZ_Pos 16
#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) 
#define   CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) 
#define   CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) 
#define   CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) 
#define   CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) 
#define   CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) 
#define   CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) 
#define   CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) 
#define   CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) 
#define   CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) 
#define   CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) 
#define   CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) 
#define   CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) 
#define   CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) 
#define   CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) 
#define   CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) 
#define   CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) 
#define CHIPID_CIDR_ARCH_Pos 20
#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) 
#define   CHIPID_CIDR_ARCH_SAME70 (0x10u << 20) 
#define   CHIPID_CIDR_ARCH_SAMS70 (0x11u << 20) 
#define   CHIPID_CIDR_ARCH_SAMV71 (0x12u << 20) 
#define   CHIPID_CIDR_ARCH_SAMV70 (0x13u << 20) 
#define CHIPID_CIDR_NVPTYP_Pos 28
#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) 
#define   CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) 
#define   CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) 
#define   CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) 
#define   CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) 
#define   CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) 
#define CHIPID_CIDR_EXT (0x1u << 31) 
/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
#define CHIPID_EXID_EXID_Pos 0
#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) 


#endif /* _SAME70_CHIPID_COMPONENT_ */