RTEMS  5.1
regs-edma.h
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1 
7 /*
8  * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
9  *
10  * embedded brains GmbH
11  * Obere Lagerstr. 30
12  * 82178 Puchheim
13  * Germany
14  * <rtems@embedded-brains.de>
15  *
16  * The license and distribution terms for this file may be
17  * found in the file LICENSE in this distribution or at
18  * http://www.rtems.org/license/LICENSE.
19  */
20 
21 /*********************************************************************
22  *
23  * Copyright:
24  * Freescale Semiconductor, INC. All Rights Reserved.
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30  * otherwise under any patents or trademarks of Freescale
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51 
52 #ifndef LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H
53 #define LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H
54 
55 #include <stdint.h>
56 
57 #include <bspopts.h>
58 
59 #ifdef __cplusplus
60 extern "C" {
61 #endif
62 
63 /****************************************************************************/
64 /* MODULE : eDMA */
65 /****************************************************************************/
66  struct EDMA_tag {
67  union EDMA_CR_tag {
68  uint32_t R;
69  struct {
70 #if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
71  uint32_t:14;
72  uint32_t CX:1;
73  uint32_t ECX:1;
74 #else
75  uint32_t:16;
76 #endif
77  uint32_t GRP3PRI:2;
78  uint32_t GRP2PRI:2;
79  uint32_t GRP1PRI:2;
80  uint32_t GRP0PRI:2;
81 #if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
82  uint32_t EMLM:1;
83  uint32_t CLM:1;
84  uint32_t HALT:1;
85  uint32_t HOE:1;
86 #else
87  uint32_t:4;
88 #endif
89  uint32_t ERGA:1;
90  uint32_t ERCA:1;
91  uint32_t EDBG:1;
92  uint32_t EBW:1;
93  } B;
94  } CR; /* Control Register */
95 
96  union {
97  uint32_t R;
98  struct {
99  uint32_t VLD:1;
100 #if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
101  uint32_t:14;
102  uint32_t ECX:1;
103 #else
104  uint32_t:15;
105 #endif
106  uint32_t GPE:1;
107  uint32_t CPE:1;
108  uint32_t ERRCHN:6;
109  uint32_t SAE:1;
110  uint32_t SOE:1;
111  uint32_t DAE:1;
112  uint32_t DOE:1;
113  uint32_t NCE:1;
114  uint32_t SGE:1;
115  uint32_t SBE:1;
116  uint32_t DBE:1;
117  } B;
118  } ESR; /* Error Status Register */
119 
120  union {
121  uint32_t R;
122  struct {
123  uint32_t ERQ63:1;
124  uint32_t ERQ62:1;
125  uint32_t ERQ61:1;
126  uint32_t ERQ60:1;
127  uint32_t ERQ59:1;
128  uint32_t ERQ58:1;
129  uint32_t ERQ57:1;
130  uint32_t ERQ56:1;
131  uint32_t ERQ55:1;
132  uint32_t ERQ54:1;
133  uint32_t ERQ53:1;
134  uint32_t ERQ52:1;
135  uint32_t ERQ51:1;
136  uint32_t ERQ50:1;
137  uint32_t ERQ49:1;
138  uint32_t ERQ48:1;
139  uint32_t ERQ47:1;
140  uint32_t ERQ46:1;
141  uint32_t ERQ45:1;
142  uint32_t ERQ44:1;
143  uint32_t ERQ43:1;
144  uint32_t ERQ42:1;
145  uint32_t ERQ41:1;
146  uint32_t ERQ40:1;
147  uint32_t ERQ39:1;
148  uint32_t ERQ38:1;
149  uint32_t ERQ37:1;
150  uint32_t ERQ36:1;
151  uint32_t ERQ35:1;
152  uint32_t ERQ34:1;
153  uint32_t ERQ33:1;
154  uint32_t ERQ32:1;
155  } B;
156  } ERQRH; /* DMA Enable Request Register High */
157 
158  union {
159  uint32_t R;
160  struct {
161  uint32_t ERQ31:1;
162  uint32_t ERQ30:1;
163  uint32_t ERQ29:1;
164  uint32_t ERQ28:1;
165  uint32_t ERQ27:1;
166  uint32_t ERQ26:1;
167  uint32_t ERQ25:1;
168  uint32_t ERQ24:1;
169  uint32_t ERQ23:1;
170  uint32_t ERQ22:1;
171  uint32_t ERQ21:1;
172  uint32_t ERQ20:1;
173  uint32_t ERQ19:1;
174  uint32_t ERQ18:1;
175  uint32_t ERQ17:1;
176  uint32_t ERQ16:1;
177  uint32_t ERQ15:1;
178  uint32_t ERQ14:1;
179  uint32_t ERQ13:1;
180  uint32_t ERQ12:1;
181  uint32_t ERQ11:1;
182  uint32_t ERQ10:1;
183  uint32_t ERQ09:1;
184  uint32_t ERQ08:1;
185  uint32_t ERQ07:1;
186  uint32_t ERQ06:1;
187  uint32_t ERQ05:1;
188  uint32_t ERQ04:1;
189  uint32_t ERQ03:1;
190  uint32_t ERQ02:1;
191  uint32_t ERQ01:1;
192  uint32_t ERQ00:1;
193  } B;
194  } ERQRL; /* DMA Enable Request Register Low */
195 
196  union {
197  uint32_t R;
198  struct {
199  uint32_t EEI63:1;
200  uint32_t EEI62:1;
201  uint32_t EEI61:1;
202  uint32_t EEI60:1;
203  uint32_t EEI59:1;
204  uint32_t EEI58:1;
205  uint32_t EEI57:1;
206  uint32_t EEI56:1;
207  uint32_t EEI55:1;
208  uint32_t EEI54:1;
209  uint32_t EEI53:1;
210  uint32_t EEI52:1;
211  uint32_t EEI51:1;
212  uint32_t EEI50:1;
213  uint32_t EEI49:1;
214  uint32_t EEI48:1;
215  uint32_t EEI47:1;
216  uint32_t EEI46:1;
217  uint32_t EEI45:1;
218  uint32_t EEI44:1;
219  uint32_t EEI43:1;
220  uint32_t EEI42:1;
221  uint32_t EEI41:1;
222  uint32_t EEI40:1;
223  uint32_t EEI39:1;
224  uint32_t EEI38:1;
225  uint32_t EEI37:1;
226  uint32_t EEI36:1;
227  uint32_t EEI35:1;
228  uint32_t EEI34:1;
229  uint32_t EEI33:1;
230  uint32_t EEI32:1;
231  } B;
232  } EEIRH; /* DMA Enable Error Interrupt Register High */
233 
234  union {
235  uint32_t R;
236  struct {
237  uint32_t EEI31:1;
238  uint32_t EEI30:1;
239  uint32_t EEI29:1;
240  uint32_t EEI28:1;
241  uint32_t EEI27:1;
242  uint32_t EEI26:1;
243  uint32_t EEI25:1;
244  uint32_t EEI24:1;
245  uint32_t EEI23:1;
246  uint32_t EEI22:1;
247  uint32_t EEI21:1;
248  uint32_t EEI20:1;
249  uint32_t EEI19:1;
250  uint32_t EEI18:1;
251  uint32_t EEI17:1;
252  uint32_t EEI16:1;
253  uint32_t EEI15:1;
254  uint32_t EEI14:1;
255  uint32_t EEI13:1;
256  uint32_t EEI12:1;
257  uint32_t EEI11:1;
258  uint32_t EEI10:1;
259  uint32_t EEI09:1;
260  uint32_t EEI08:1;
261  uint32_t EEI07:1;
262  uint32_t EEI06:1;
263  uint32_t EEI05:1;
264  uint32_t EEI04:1;
265  uint32_t EEI03:1;
266  uint32_t EEI02:1;
267  uint32_t EEI01:1;
268  uint32_t EEI00:1;
269  } B;
270  } EEIRL; /* DMA Enable Error Interrupt Register Low */
271 
272  union { /* DMA Set Enable Request Register */
273  uint8_t R;
274  struct {
275  uint8_t NOP:1;
276  uint8_t SERQ:7;
277  } B;
278  } SERQR;
279 
280  union { /* DMA Clear Enable Request Register */
281  uint8_t R;
282  struct {
283  uint8_t NOP:1;
284  uint8_t CERQ:7;
285  } B;
286  } CERQR;
287 
288  union { /* DMA Set Enable Error Interrupt Register */
289  uint8_t R;
290  struct {
291  uint8_t NOP:1;
292  uint8_t SEEI:7;
293  } B;
294  } SEEIR;
295 
296  union { /* DMA Clear Enable Error Interrupt Register */
297  uint8_t R;
298  struct {
299  uint8_t NOP:1;
300  uint8_t CEEI:7;
301  } B;
302  } CEEIR;
303 
304  union { /* DMA Clear Interrupt Request Register */
305  uint8_t R;
306  struct {
307  uint8_t NOP:1;
308  uint8_t CINT:7;
309  } B;
310  } CIRQR;
311 
312  union { /* DMA Clear error Register */
313  uint8_t R;
314  struct {
315  uint8_t NOP:1;
316  uint8_t CERR:7;
317  } B;
318  } CER;
319 
320  union { /* Set Start Bit Register */
321  uint8_t R;
322  struct {
323  uint8_t NOP:1;
324  uint8_t SSB:7;
325  } B;
326  } SSBR;
327 
328  union { /* Clear Done Status Bit Register */
329  uint8_t R;
330  struct {
331  uint8_t NOP:1;
332  uint8_t CDSB:7;
333  } B;
334  } CDSBR;
335 
336  union {
337  uint32_t R;
338  struct {
339  uint32_t INT63:1;
340  uint32_t INT62:1;
341  uint32_t INT61:1;
342  uint32_t INT60:1;
343  uint32_t INT59:1;
344  uint32_t INT58:1;
345  uint32_t INT57:1;
346  uint32_t INT56:1;
347  uint32_t INT55:1;
348  uint32_t INT54:1;
349  uint32_t INT53:1;
350  uint32_t INT52:1;
351  uint32_t INT51:1;
352  uint32_t INT50:1;
353  uint32_t INT49:1;
354  uint32_t INT48:1;
355  uint32_t INT47:1;
356  uint32_t INT46:1;
357  uint32_t INT45:1;
358  uint32_t INT44:1;
359  uint32_t INT43:1;
360  uint32_t INT42:1;
361  uint32_t INT41:1;
362  uint32_t INT40:1;
363  uint32_t INT39:1;
364  uint32_t INT38:1;
365  uint32_t INT37:1;
366  uint32_t INT36:1;
367  uint32_t INT35:1;
368  uint32_t INT34:1;
369  uint32_t INT33:1;
370  uint32_t INT32:1;
371  } B;
372  } IRQRH; /* DMA Interrupt Request High */
373 
374  union {
375  uint32_t R;
376  struct {
377  uint32_t INT31:1;
378  uint32_t INT30:1;
379  uint32_t INT29:1;
380  uint32_t INT28:1;
381  uint32_t INT27:1;
382  uint32_t INT26:1;
383  uint32_t INT25:1;
384  uint32_t INT24:1;
385  uint32_t INT23:1;
386  uint32_t INT22:1;
387  uint32_t INT21:1;
388  uint32_t INT20:1;
389  uint32_t INT19:1;
390  uint32_t INT18:1;
391  uint32_t INT17:1;
392  uint32_t INT16:1;
393  uint32_t INT15:1;
394  uint32_t INT14:1;
395  uint32_t INT13:1;
396  uint32_t INT12:1;
397  uint32_t INT11:1;
398  uint32_t INT10:1;
399  uint32_t INT09:1;
400  uint32_t INT08:1;
401  uint32_t INT07:1;
402  uint32_t INT06:1;
403  uint32_t INT05:1;
404  uint32_t INT04:1;
405  uint32_t INT03:1;
406  uint32_t INT02:1;
407  uint32_t INT01:1;
408  uint32_t INT00:1;
409  } B;
410  } IRQRL; /* DMA Interrupt Request Low */
411 
412  union {
413  uint32_t R;
414  struct {
415  uint32_t ERR63:1;
416  uint32_t ERR62:1;
417  uint32_t ERR61:1;
418  uint32_t ERR60:1;
419  uint32_t ERR59:1;
420  uint32_t ERR58:1;
421  uint32_t ERR57:1;
422  uint32_t ERR56:1;
423  uint32_t ERR55:1;
424  uint32_t ERR54:1;
425  uint32_t ERR53:1;
426  uint32_t ERR52:1;
427  uint32_t ERR51:1;
428  uint32_t ERR50:1;
429  uint32_t ERR49:1;
430  uint32_t ERR48:1;
431  uint32_t ERR47:1;
432  uint32_t ERR46:1;
433  uint32_t ERR45:1;
434  uint32_t ERR44:1;
435  uint32_t ERR43:1;
436  uint32_t ERR42:1;
437  uint32_t ERR41:1;
438  uint32_t ERR40:1;
439  uint32_t ERR39:1;
440  uint32_t ERR38:1;
441  uint32_t ERR37:1;
442  uint32_t ERR36:1;
443  uint32_t ERR35:1;
444  uint32_t ERR34:1;
445  uint32_t ERR33:1;
446  uint32_t ERR32:1;
447  } B;
448  } ERH; /* DMA Error High */
449 
450  union {
451  uint32_t R;
452  struct {
453  uint32_t ERR31:1;
454  uint32_t ERR30:1;
455  uint32_t ERR29:1;
456  uint32_t ERR28:1;
457  uint32_t ERR27:1;
458  uint32_t ERR26:1;
459  uint32_t ERR25:1;
460  uint32_t ERR24:1;
461  uint32_t ERR23:1;
462  uint32_t ERR22:1;
463  uint32_t ERR21:1;
464  uint32_t ERR20:1;
465  uint32_t ERR19:1;
466  uint32_t ERR18:1;
467  uint32_t ERR17:1;
468  uint32_t ERR16:1;
469  uint32_t ERR15:1;
470  uint32_t ERR14:1;
471  uint32_t ERR13:1;
472  uint32_t ERR12:1;
473  uint32_t ERR11:1;
474  uint32_t ERR10:1;
475  uint32_t ERR09:1;
476  uint32_t ERR08:1;
477  uint32_t ERR07:1;
478  uint32_t ERR06:1;
479  uint32_t ERR05:1;
480  uint32_t ERR04:1;
481  uint32_t ERR03:1;
482  uint32_t ERR02:1;
483  uint32_t ERR01:1;
484  uint32_t ERR00:1;
485  } B;
486  } ERL; /* DMA Error Low */
487 
488 #if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
489  union { /* hardware request status high */
490  uint32_t R;
491  struct {
492  uint32_t HRS63:1;
493  uint32_t HRS62:1;
494  uint32_t HRS61:1;
495  uint32_t HRS60:1;
496  uint32_t HRS59:1;
497  uint32_t HRS58:1;
498  uint32_t HRS57:1;
499  uint32_t HRS56:1;
500  uint32_t HRS55:1;
501  uint32_t HRS54:1;
502  uint32_t HRS53:1;
503  uint32_t HRS52:1;
504  uint32_t HRS51:1;
505  uint32_t HRS50:1;
506  uint32_t HRS49:1;
507  uint32_t HRS48:1;
508  uint32_t HRS47:1;
509  uint32_t HRS46:1;
510  uint32_t HRS45:1;
511  uint32_t HRS44:1;
512  uint32_t HRS43:1;
513  uint32_t HRS42:1;
514  uint32_t HRS41:1;
515  uint32_t HRS40:1;
516  uint32_t HRS39:1;
517  uint32_t HRS38:1;
518  uint32_t HRS37:1;
519  uint32_t HRS36:1;
520  uint32_t HRS35:1;
521  uint32_t HRS34:1;
522  uint32_t HRS33:1;
523  uint32_t HRS32:1;
524  } B;
525  } HRSH;
526 
527  union { /* hardware request status low */
528  uint32_t R;
529  struct {
530  uint32_t HRS31:1;
531  uint32_t HRS30:1;
532  uint32_t HRS29:1;
533  uint32_t HRS28:1;
534  uint32_t HRS27:1;
535  uint32_t HRS26:1;
536  uint32_t HRS25:1;
537  uint32_t HRS24:1;
538  uint32_t HRS23:1;
539  uint32_t HRS22:1;
540  uint32_t HRS21:1;
541  uint32_t HRS20:1;
542  uint32_t HRS19:1;
543  uint32_t HRS18:1;
544  uint32_t HRS17:1;
545  uint32_t HRS16:1;
546  uint32_t HRS15:1;
547  uint32_t HRS14:1;
548  uint32_t HRS13:1;
549  uint32_t HRS12:1;
550  uint32_t HRS11:1;
551  uint32_t HRS10:1;
552  uint32_t HRS09:1;
553  uint32_t HRS08:1;
554  uint32_t HRS07:1;
555  uint32_t HRS06:1;
556  uint32_t HRS05:1;
557  uint32_t HRS04:1;
558  uint32_t HRS03:1;
559  uint32_t HRS02:1;
560  uint32_t HRS01:1;
561  uint32_t HRS00:1;
562  } B;
563  } HRSL;
564 
565  uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */
566 #else
567  uint32_t edma_reserved1[52];
568 #endif
569 
570  union {
571  uint8_t R;
572  struct {
573  uint8_t ECP:1;
574 #if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
575  uint8_t DPA:1;
576 #else
577  uint8_t:1;
578 #endif
579  uint8_t GRPPRI:2;
580  uint8_t CHPRI:4;
581  } B;
582  } CPR[64];
583 
584  uint32_t edma_reserved2[944];
585 
586 /****************************************************************************/
587 /* DMA2 Transfer Control Descriptor */
588 /****************************************************************************/
589  struct tcd_t {
590  uint32_t SADDR; /* source address */
591 
592  /* Source and destination fields */
593  union tcd_SDF_tag {
594  uint32_t R;
595  struct {
596  uint16_t SMOD:5; /* source address modulo */
597  uint16_t SSIZE:3; /* source transfer size */
598  uint16_t DMOD:5; /* destination address modulo */
599  uint16_t DSIZE:3; /* destination transfer size */
600  int16_t SOFF; /* signed source address offset */
601  } B;
602  } SDF;
603 
604  uint32_t NBYTES; /* inner (“minor”) byte count */
605 
606  int32_t SLAST; /* last destination address adjustment, or
607  scatter/gather address (if e_sg = 1) */
608 
609  uint32_t DADDR; /* destination address */
610 
611  /* CITER and destination fields */
612  union tcd_CDF_tag {
613  uint32_t R;
614  struct {
615  uint16_t CITERE_LINK:1;
616  uint16_t CITER:15;
617  int16_t DOFF; /* signed destination address offset */
618  } B;
619  struct {
620  uint16_t CITERE_LINK:1;
621  uint16_t CITERLINKCH:6;
622  uint16_t CITER:9;
623  int16_t DOFF;
624  } B_ALT;
625  struct {
626  uint16_t CITER;
627  int16_t DOFF;
628  } B_NOLINK;
629  } CDF;
630 
631  int32_t DLAST_SGA;
632 
633  /* BITER and misc fields */
634  union tcd_BMF_tag {
635  uint32_t R;
636  struct {
637  uint32_t BITERE_LINK:1; /* beginning ("major") iteration count */
638  uint32_t BITER:15;
639  uint32_t BWC:2; /* bandwidth control */
640  uint32_t MAJORLINKCH:6; /* enable channel-to-channel link */
641  uint32_t DONE:1; /* channel done */
642  uint32_t ACTIVE:1; /* channel active */
643  uint32_t MAJORE_LINK:1; /* enable channel-to-channel link */
644  uint32_t E_SG:1; /* enable scatter/gather descriptor */
645  uint32_t D_REQ:1; /* disable ipd_req when done */
646  uint32_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
647  uint32_t INT_MAJ:1; /* interrupt on major loop completion */
648  uint32_t START:1; /* explicit channel start */
649  } B;
650  struct {
651  uint32_t BITERE_LINK:1;
652  uint32_t BITERLINKCH:6;
653  uint32_t BITER:9;
654  uint32_t BWC:2;
655  uint32_t MAJORLINKCH:6;
656  uint32_t DONE:1;
657  uint32_t ACTIVE:1;
658  uint32_t MAJORE_LINK:1;
659  uint32_t E_SG:1;
660  uint32_t D_REQ:1;
661  uint32_t INT_HALF:1;
662  uint32_t INT_MAJ:1;
663  uint32_t START:1;
664  } B_ALT;
665  struct {
666  uint16_t BITER;
667  uint16_t BWC:2;
668  uint16_t MAJORLINKCH:6;
669  uint16_t DONE:1;
670  uint16_t ACTIVE:1;
671  uint16_t MAJORE_LINK:1;
672  uint16_t E_SG:1;
673  uint16_t D_REQ:1;
674  uint16_t INT_HALF:1;
675  uint16_t INT_MAJ:1;
676  uint16_t START:1;
677  } B_NOLINK;
678  } BMF;
679  } TCD[64]; /* transfer_control_descriptor */
680  };
681 
682 #ifndef __cplusplus
683  static const struct tcd_t EDMA_TCD_DEFAULT = {
684  .SADDR = 0,
685  .SDF = { .R = 0 },
686  .NBYTES = 0,
687  .SLAST = 0,
688  .DADDR = 0,
689  .CDF = { .R = 0 },
690  .DLAST_SGA = 0,
691  .BMF = { .R = 0 }
692  };
693 #endif /* __cplusplus */
694 
695 #define EDMA_TCD_BITER_MASK 0x7fff
696 
697 #define EDMA_TCD_BITER_SIZE (EDMA_TCD_BITER_MASK + 1)
698 
699 #define EDMA_TCD_BITER_LINKED_MASK 0x1ff
700 
701 #define EDMA_TCD_BITER_LINKED_SIZE (EDMA_TCD_BITER_LINKED_MASK + 1)
702 
703 #define EDMA_TCD_LINK_AND_BITER(link, biter) \
704  (((link) << 9) + ((biter) & EDMA_TCD_BITER_LINKED_MASK))
705 
706 #ifdef __cplusplus
707 }
708 #endif /* __cplusplus */
709 
710 #endif /* LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H */
EDMA_tag::EDMA_CR_tag
Definition: regs-edma.h:67
EDMA_tag::tcd_t::tcd_BMF_tag
Definition: regs-edma.h:634
EDMA_tag::tcd_t
Definition: regs-edma.h:589
EDMA_tag
Definition: regs-edma.h:66
EDMA_tag::tcd_t::tcd_SDF_tag
Definition: regs-edma.h:593
EDMA_tag::tcd_t::tcd_CDF_tag
Definition: regs-edma.h:612
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