RTEMS  5.1
reg_sys.h
1 /* The header file is generated by make_header.py from SYS.json */
2 /* Current script's version can be found at: */
3 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4 
5 /*
6  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7  *
8  * Czech Technical University in Prague
9  * Zikova 1903/4
10  * 166 36 Praha 6
11  * Czech Republic
12  *
13  * All rights reserved.
14  *
15  * Redistribution and use in source and binary forms, with or without
16  * modification, are permitted provided that the following conditions are met:
17  *
18  * 1. Redistributions of source code must retain the above copyright notice, this
19  * list of conditions and the following disclaimer.
20  * 2. Redistributions in binary form must reproduce the above copyright notice,
21  * this list of conditions and the following disclaimer in the documentation
22  * and/or other materials provided with the distribution.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  *
35  * The views and conclusions contained in the software and documentation are those
36  * of the authors and should not be interpreted as representing official policies,
37  * either expressed or implied, of the FreeBSD Project.
38 */
39 #ifndef LIBBSP_ARM_TMS570_SYS1
40 #define LIBBSP_ARM_TMS570_SYS1
41 
42 #include <bsp/utility.h>
43 
44 typedef struct{
45  uint32_t SYSPC1; /*SYS Pin Control Register 1*/
46  uint32_t SYSPC2; /*SYS Pin Control Register 2*/
47  uint32_t SYSPC3; /*SYS Pin Control Register 3*/
48  uint32_t SYSPC4; /*SYS Pin Control Register 4*/
49  uint32_t SYSPC5; /*SYS Pin Control Register 5*/
50  uint32_t SYSPC6; /*SYS Pin Control Register 6*/
51  uint32_t SYSPC7; /*SYS Pin Control Register 7*/
52  uint32_t SYSPC8; /*SYS Pin Control Register 8*/
53  uint32_t SYSPC9; /*SYS Pin Control Register 9*/
54  uint8_t reserved1 [12];
55  uint32_t CSDIS; /*Clock Source Disable Register*/
56  uint32_t CSDISSET; /*Clock Source Disable Set Register*/
57  uint32_t CSDISCLR; /*Clock Source Disable Clear Register*/
58  uint32_t CDDIS; /*Clock Domain Disable Register*/
59  uint32_t CDDISSET; /*Clock Domain Disable Set Register*/
60  uint32_t CDDISCLR; /*Clock Domain Disable Clear Register*/
61  uint32_t GHVSRC; /*GCLK, HCLK, VCLK, and VCLK2 Source Register*/
62  uint32_t VCLKASRC; /*Peripheral Asynchronous Clock Source Register*/
63  uint32_t RCLKSRC; /*RTI Clock Source Register*/
64  uint32_t CSVSTAT; /*Clock Source Valid Status Register*/
65  uint32_t MSTGCR; /*Memory Self-Test Global Control Register*/
66  uint32_t MINITGCR; /*Memory Hardware Initialization Global Control Register*/
67  uint32_t MSIENA; /*Memory Self-Test/Initialization Enable Register*/
68  uint8_t reserved2 [4];
69  uint32_t MSTCGSTAT; /*MSTC Global Status Register*/
70  uint32_t MINISTAT; /*Memory Hardware Initialization Status Register*/
71  uint32_t PLLCTL1; /*PLL Control Register 1*/
72  uint32_t PLLCTL2; /*PLL Control Register 2*/
73  uint32_t SYSPC10; /*SYS Pin Control Register 10*/
74  uint32_t DIEIDL; /*Die Identification Register, Lower Word*/
75  uint32_t DIEIDH; /*Die Identification Register, Upper Word*/
76  uint8_t reserved3 [4];
77  uint32_t LPOMONCTL; /*LPO/Clock Monitor Control Register*/
78  uint32_t CLKTEST; /*Clock Test Register*/
79  uint32_t DFTCTRLREG1; /*DFT Control Register*/
80  uint32_t DFTCTRLREG2; /*DFT Control Register 2*/
81  uint8_t reserved4 [8];
82  uint32_t GPREG1; /*General Purpose Register*/
83  uint8_t reserved5 [4];
84  uint32_t IMPFASTS; /*Imprecise Fault Status Register*/
85  uint32_t IMPFTADD; /*Imprecise Fault Write Address Register*/
86  uint32_t SSIR1; /*System Software Interrupt Request 1 Register*/
87  uint32_t SSIR2; /*System Software Interrupt Request 2 Register*/
88  uint32_t SSIR3; /*System Software Interrupt Request 3 Register*/
89  uint32_t SSIR4; /*System Software Interrupt Request 4 Register*/
90  uint32_t RAMGCR; /*RAM Control Register*/
91  uint32_t BMMCR1; /*Bus Matrix Module Control Register 1*/
92  uint8_t reserved6 [4];
93  uint32_t CPURSTCR; /*CPU Reset Control Register*/
94  uint32_t CLKCNTL; /*Clock Control Register*/
95  uint32_t ECPCNTL; /*ECP Control Register*/
96  uint8_t reserved7 [4];
97  uint32_t DEVCR1; /*DEV Parity Control Register 1*/
98  uint32_t SYSECR; /*System Exception Control Register*/
99  uint32_t SYSESR; /*System Exception Status Register*/
100  uint32_t SYSTASR; /*System Test Abort Status Register*/
101  uint32_t GLBSTAT; /*Global Status Register*/
102  uint32_t DEVID; /*Device Identification Register*/
103  uint32_t SSIVEC; /*Software Interrupt Vector Register*/
104  uint32_t SSIF; /*System Software Interrupt Flag Register*/
105 } tms570_sys1_t;
106 
107 
108 /*---------------------TMS570_SYS1_SYSPCx---------------------*/
109 /* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */
110 #define TMS570_SYS1_SYSPCx_ECPCLKFUN BSP_BIT32(0)
111 
112 
113 /*---------------------TMS570_SYS1_CSDIS---------------------*/
114 /* field: CLKSROFF - Clock source[7-0] off. 2 reserved */
115 #define TMS570_SYS1_CSDIS_CLKSROFF(val) BSP_FLD32(val,0, 7)
116 #define TMS570_SYS1_CSDIS_CLKSROFF_GET(reg) BSP_FLD32GET(reg,0, 7)
117 #define TMS570_SYS1_CSDIS_CLKSROFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
118 
119 /* Clock Source 0 Oscillator */
120 #define TMS570_SYS1_CSDIS_CLKSR_OSC_NUM 0
121 #define TMS570_SYS1_CSDIS_CLKSROFF_OSC BSP_BIT32(0)
122 
123 /* Clock Source 1 PLL1 */
124 #define TMS570_SYS1_CSDIS_CLKSR_PLL1_NUM 1
125 #define TMS570_SYS1_CSDIS_CLKSROFF_PLL1 BSP_BIT32(1)
126 
127 /* Clock Source 3 EXTCLKIN */
128 #define TMS570_SYS1_CSDIS_CLKSR_EXTCLKIN_NUM 3
129 #define TMS570_SYS1_CSDIS_CLKSROFF_EXTCLKIN BSP_BIT32(3)
130 
131 /* Clock Source 4 Low Frequency LPO (Low Power Oscillator) clock */
132 #define TMS570_SYS1_CSDIS_CLKSR_LPO_NUM 4
133 #define TMS570_SYS1_CSDIS_CLKSROFF_LPO BSP_BIT32(4)
134 
135 /* Clock Source 5 High Frequency LPO (Low Power Oscillator) clock */
136 #define TMS570_SYS1_CSDIS_CLKSR_HPO_NUM 5
137 #define TMS570_SYS1_CSDIS_CLKSROFF_HPO BSP_BIT32(5)
138 
139 /* Clock Source 6 PLL2 */
140 #define TMS570_SYS1_CSDIS_CLKSR_PLL2_NUM 6
141 #define TMS570_SYS1_CSDIS_CLKSROFF_PLL2 BSP_BIT32(6)
142 
143 /* Clock Source 7 EXTCLKIN2 */
144 #define TMS570_SYS1_CSDIS_CLKSR_EXTCLKIN2_NUM 7
145 #define TMS570_SYS1_CSDIS_CLKSROFF_EXTCLKIN2 BSP_BIT32(7)
146 
147 /*--------------------TMS570_SYS1_CSDISSET--------------------*/
148 /* field: SETCLKSR_OFF - Set clock source[7-0] to the disabled state. */
149 #define TMS570_SYS1_CSDISSET_SETCLKSR_OFF(val) BSP_FLD32(val,0, 7)
150 #define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 7)
151 #define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
152 
153 /*--------------------TMS570_SYS1_CSDISCLR--------------------*/
154 /* field: CLRCLKSR_OFF - Enables clock source[7-0] */
155 #define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF(val) BSP_FLD32(val,0, 7)
156 #define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 7)
157 #define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
158 
159 /*---------------------TMS570_SYS1_CDDIS---------------------*/
160 /* field: VCLKAOFF - VCLKA4 domain off. */
161 #define TMS570_SYS1_CDDIS_VCLKAOFF4 BSP_BIT32(11)
162 
163 /* field: VCLKAOFF - VCLKA3 domain off. */
164 #define TMS570_SYS1_CDDIS_VCLKAOFF3 BSP_BIT32(10)
165 
166 /* field: VCLK3OFF - VCLK3 domain off. */
167 #define TMS570_SYS1_CDDIS_VCLK3OFF BSP_BIT32(8)
168 
169 /* field: RTICLK1OFF - RTICLK1 domain off. */
170 #define TMS570_SYS1_CDDIS_RTICLK1OFF BSP_BIT32(6)
171 
172 /* field: VCLKAOFF - VCLKA2 domain off. */
173 #define TMS570_SYS1_CDDIS_VCLKAOFF2 BSP_BIT32(5)
174 
175 /* field: VCLKAOFF - VCLKA1 domain off. */
176 #define TMS570_SYS1_CDDIS_VCLKAOFF1 BSP_BIT32(4)
177 
178 /* field: VCLK2OFF - VCLK2 domain off. */
179 #define TMS570_SYS1_CDDIS_VCLK2OFF BSP_BIT32(3)
180 
181 /* field: VCLKPOFF - VCLK_periph domain off. */
182 #define TMS570_SYS1_CDDIS_VCLKPOFF BSP_BIT32(2)
183 
184 /* field: HCLKOFF - HCLK and VCLK_sys domains off. */
185 #define TMS570_SYS1_CDDIS_HCLKOFF BSP_BIT32(1)
186 
187 /* field: GCLKOFF - GCLK domain off. */
188 #define TMS570_SYS1_CDDIS_GCLKOFF BSP_BIT32(0)
189 
190 
191 /*--------------------TMS570_SYS1_CDDISSET--------------------*/
192 /* field: SETVCLKA_OFF - Set VCLKA[4-3] domain. */
193 #define TMS570_SYS1_CDDISSET_SETVCLKA_OFF(val) BSP_FLD32(val,10, 11)
194 #define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_GET(reg) BSP_FLD32GET(reg,10, 11)
195 #define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
196 
197 /* field: SETVCLK3OFF - Set VCLK3 domain. */
198 #define TMS570_SYS1_CDDISSET_SETVCLK3OFF BSP_BIT32(8)
199 
200 /* field: SETRTI1CLKOFF - Set RTICLK1 domain. */
201 #define TMS570_SYS1_CDDISSET_SETRTI1CLKOFF BSP_BIT32(6)
202 
203 /* field: SETTVCLKA2OFF - Set VCLKA2 domain. */
204 #define TMS570_SYS1_CDDISSET_SETTVCLKA2OFF BSP_BIT32(5)
205 
206 /* field: SETVCLKA1OFF - Set VCLKA1 domain. */
207 #define TMS570_SYS1_CDDISSET_SETVCLKA1OFF BSP_BIT32(4)
208 
209 /* field: SETVCLK2OFF - Set VCLK2 domain. */
210 #define TMS570_SYS1_CDDISSET_SETVCLK2OFF BSP_BIT32(3)
211 
212 /* field: SETVCLKPOFF - Set VCLK_periph domain. */
213 #define TMS570_SYS1_CDDISSET_SETVCLKPOFF BSP_BIT32(2)
214 
215 /* field: SETHCLKOFF - Set HCLK and VCLK_sys domains. */
216 #define TMS570_SYS1_CDDISSET_SETHCLKOFF BSP_BIT32(1)
217 
218 /* field: SETGCLKOFF - Set GCLK domain. */
219 #define TMS570_SYS1_CDDISSET_SETGCLKOFF BSP_BIT32(0)
220 
221 
222 /*--------------------TMS570_SYS1_CDDISCLR--------------------*/
223 /* field: CLRVCLKAOFF - Clear VCLKA[4-3] domain. */
224 #define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF(val) BSP_FLD32(val,10, 11)
225 #define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11)
226 #define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
227 
228 /* field: Reserved - Reserved */
229 #define TMS570_SYS1_CDDISCLR_Reserved BSP_BIT32(9)
230 
231 /* field: CLRVCLK3OFF - Clear VCLK3 domain. */
232 #define TMS570_SYS1_CDDISCLR_CLRVCLK3OFF BSP_BIT32(8)
233 
234 /* field: CLRRTI1CLKOFF - Clear RTICLK1 domain. */
235 #define TMS570_SYS1_CDDISCLR_CLRRTI1CLKOFF BSP_BIT32(6)
236 
237 /* field: CLRTVCLKA2OFF - Clear VCLKA2 domain. */
238 #define TMS570_SYS1_CDDISCLR_CLRTVCLKA2OFF BSP_BIT32(5)
239 
240 /* field: CLRVCLKA1OFF - Clear VCLKA1 domain. */
241 #define TMS570_SYS1_CDDISCLR_CLRVCLKA1OFF BSP_BIT32(4)
242 
243 /* field: CLRVCLK2OFF - Clear VCLK2 domain. */
244 #define TMS570_SYS1_CDDISCLR_CLRVCLK2OFF BSP_BIT32(3)
245 
246 /* field: CLRVCLKPOFF - CLRVCLKPOFF */
247 #define TMS570_SYS1_CDDISCLR_CLRVCLKPOFF BSP_BIT32(2)
248 
249 /* field: CLRHCLKOFF - Clear HCLK and VCLK_sys domains. */
250 #define TMS570_SYS1_CDDISCLR_CLRHCLKOFF BSP_BIT32(1)
251 
252 /* field: CLRGCLKOFF - Clear GCLK domain. */
253 #define TMS570_SYS1_CDDISCLR_CLRGCLKOFF BSP_BIT32(0)
254 
255 
256 /*---------------------TMS570_SYS1_GHVSRC---------------------*/
257 /* field: GHVWAKE - GCLK, HCLK, VCLK, VCLK2 source on wakeup. */
258 #define TMS570_SYS1_GHVSRC_GHVWAKE(val) BSP_FLD32(val,24, 27)
259 #define TMS570_SYS1_GHVSRC_GHVWAKE_GET(reg) BSP_FLD32GET(reg,24, 27)
260 #define TMS570_SYS1_GHVSRC_GHVWAKE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
261 
262 /* field: HVLPM - HCLK, VCLK, VCLK2 source on wakeup when GCLK is turned off. */
263 #define TMS570_SYS1_GHVSRC_HVLPM(val) BSP_FLD32(val,16, 19)
264 #define TMS570_SYS1_GHVSRC_HVLPM_GET(reg) BSP_FLD32GET(reg,16, 19)
265 #define TMS570_SYS1_GHVSRC_HVLPM_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
266 
267 /* field: GHVSRC - GCLK, HCLK, VCLK, VCLK2 current source. */
268 #define TMS570_SYS1_GHVSRC_GHVSRC(val) BSP_FLD32(val,0, 3)
269 #define TMS570_SYS1_GHVSRC_GHVSRC_GET(reg) BSP_FLD32GET(reg,0, 3)
270 #define TMS570_SYS1_GHVSRC_GHVSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
271 
272 
273 /*--------------------TMS570_SYS1_VCLKASRC--------------------*/
274 /* field: VCLKA2S - Peripheral asynchronous clock2 source. */
275 #define TMS570_SYS1_VCLKASRC_VCLKA2S(val) BSP_FLD32(val,8, 11)
276 #define TMS570_SYS1_VCLKASRC_VCLKA2S_GET(reg) BSP_FLD32GET(reg,8, 11)
277 #define TMS570_SYS1_VCLKASRC_VCLKA2S_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
278 
279 /* field: VCLKA1S - Peripheral asynchronous clock1 source. */
280 #define TMS570_SYS1_VCLKASRC_VCLKA1S(val) BSP_FLD32(val,0, 3)
281 #define TMS570_SYS1_VCLKASRC_VCLKA1S_GET(reg) BSP_FLD32GET(reg,0, 3)
282 #define TMS570_SYS1_VCLKASRC_VCLKA1S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
283 
284 
285 /*--------------------TMS570_SYS1_RCLKSRC--------------------*/
286 /* field: RTI1DIV - RTI clock1 Divider. */
287 #define TMS570_SYS1_RCLKSRC_RTI1DIV(val) BSP_FLD32(val,8, 9)
288 #define TMS570_SYS1_RCLKSRC_RTI1DIV_GET(reg) BSP_FLD32GET(reg,8, 9)
289 #define TMS570_SYS1_RCLKSRC_RTI1DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
290 
291 /* field: RTI1SRC - RTI clock1 source. */
292 #define TMS570_SYS1_RCLKSRC_RTI1SRC(val) BSP_FLD32(val,0, 3)
293 #define TMS570_SYS1_RCLKSRC_RTI1SRC_GET(reg) BSP_FLD32GET(reg,0, 3)
294 #define TMS570_SYS1_RCLKSRC_RTI1SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
295 
296 
297 /*--------------------TMS570_SYS1_CSVSTAT--------------------*/
298 /* field: CLKSRV - Clock source[7-0] valid. */
299 #define TMS570_SYS1_CSVSTAT_CLKSRV(val) BSP_FLD32(val,3, 7)
300 #define TMS570_SYS1_CSVSTAT_CLKSRV_GET(reg) BSP_FLD32GET(reg,3, 7)
301 #define TMS570_SYS1_CSVSTAT_CLKSRV_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
302 
303 /* field: CLKSR - Clock source[1-0] valid. */
304 #define TMS570_SYS1_CSVSTAT_CLKSR(val) BSP_FLD32(val,0, 1)
305 #define TMS570_SYS1_CSVSTAT_CLKSR_GET(reg) BSP_FLD32GET(reg,0, 1)
306 #define TMS570_SYS1_CSVSTAT_CLKSR_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
307 
308 
309 /*---------------------TMS570_SYS1_MSTGCR---------------------*/
310 /* field: ROM_DIV - Prescaler divider bits for ROM clock source. */
311 #define TMS570_SYS1_MSTGCR_ROM_DIV(val) BSP_FLD32(val,8, 9)
312 #define TMS570_SYS1_MSTGCR_ROM_DIV_GET(reg) BSP_FLD32GET(reg,8, 9)
313 #define TMS570_SYS1_MSTGCR_ROM_DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
314 
315 /* field: MSTGENA - Memory self-test controller global enable key */
316 #define TMS570_SYS1_MSTGCR_MSTGENA(val) BSP_FLD32(val,0, 3)
317 #define TMS570_SYS1_MSTGCR_MSTGENA_GET(reg) BSP_FLD32GET(reg,0, 3)
318 #define TMS570_SYS1_MSTGCR_MSTGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
319 
320 
321 /*--------------------TMS570_SYS1_MINITGCR--------------------*/
322 /* field: MINITGENA - Memory hardware initialization global enable key. */
323 #define TMS570_SYS1_MINITGCR_MINITGENA(val) BSP_FLD32(val,0, 3)
324 #define TMS570_SYS1_MINITGCR_MINITGENA_GET(reg) BSP_FLD32GET(reg,0, 3)
325 #define TMS570_SYS1_MINITGCR_MINITGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
326 
327 
328 /*---------------------TMS570_SYS1_MSIENA---------------------*/
329 /* field: MSIENA - PBIST controller and memory initialization enable register. */
330 /* Whole 32 bits */
331 
332 /*-------------------TMS570_SYS1_MSTCGSTAT-------------------*/
333 /* field: MINIDONE - Memory hardware initialization complete status. */
334 #define TMS570_SYS1_MSTCGSTAT_MINIDONE BSP_BIT32(8)
335 
336 /* field: MSTDONE - Memory self-test run complete status. */
337 #define TMS570_SYS1_MSTCGSTAT_MSTDONE BSP_BIT32(0)
338 
339 
340 /*--------------------TMS570_SYS1_MINISTAT--------------------*/
341 /* field: MIDONE - Memory hardware initialization status bit. */
342 /* Whole 32 bits */
343 
344 /*--------------------TMS570_SYS1_PLLCTL1--------------------*/
345 /* field: ROS - Reset on PLL Slip */
346 #define TMS570_SYS1_PLLCTL1_ROS BSP_BIT32(31)
347 
348 /* field: MASK_SLIP - Mask detection of PLL slip */
349 #define TMS570_SYS1_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
350 #define TMS570_SYS1_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30)
351 #define TMS570_SYS1_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
352 
353 /* field: PLLDIV - PLL Output Clock Divider */
354 #define TMS570_SYS1_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28)
355 #define TMS570_SYS1_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28)
356 #define TMS570_SYS1_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
357 
358 /* field: ROF - Reset on Oscillator Fail */
359 #define TMS570_SYS1_PLLCTL1_ROF BSP_BIT32(23)
360 
361 /* field: REFCLKDIV - Reference Clock Divider */
362 #define TMS570_SYS1_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21)
363 #define TMS570_SYS1_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21)
364 #define TMS570_SYS1_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
365 
366 /* field: PLLMUL - PLL Multiplication Factor */
367 #define TMS570_SYS1_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15)
368 #define TMS570_SYS1_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15)
369 #define TMS570_SYS1_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
370 
371 
372 /*--------------------TMS570_SYS1_PLLCTL2--------------------*/
373 /* field: FMENA - Frequency Modulation Enable. */
374 #define TMS570_SYS1_PLLCTL2_FMENA BSP_BIT32(31)
375 
376 /* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */
377 #define TMS570_SYS1_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30)
378 #define TMS570_SYS1_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30)
379 #define TMS570_SYS1_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30)
380 
381 /* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */
382 #define TMS570_SYS1_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20)
383 #define TMS570_SYS1_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20)
384 #define TMS570_SYS1_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20)
385 
386 /* field: ODPLL - Internal PLL Output Divider. */
387 #define TMS570_SYS1_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11)
388 #define TMS570_SYS1_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11)
389 #define TMS570_SYS1_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
390 
391 /* field: SPR_AMOUNT - Spreading Amount. */
392 #define TMS570_SYS1_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8)
393 #define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8)
394 #define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
395 
396 
397 /*--------------------TMS570_SYS1_SYSPC10--------------------*/
398 /* field: ECPCLK_SLEW - ECPCLK slew control. This bit controls between the fast or slow slew mode. */
399 #define TMS570_SYS1_SYSPC10_ECPCLK_SLEW BSP_BIT32(0)
400 
401 
402 /*---------------------TMS570_SYS1_DIEIDL---------------------*/
403 /* field: LOT - These read only bits contain the lower 10 bits of the device lot number. */
404 #define TMS570_SYS1_DIEIDL_LOT(val) BSP_FLD32(val,22, 31)
405 #define TMS570_SYS1_DIEIDL_LOT_GET(reg) BSP_FLD32GET(reg,22, 31)
406 #define TMS570_SYS1_DIEIDL_LOT_SET(reg,val) BSP_FLD32SET(reg, val,22, 31)
407 
408 /* field: WAFER - These read only bits contain the wafer number of the device. */
409 #define TMS570_SYS1_DIEIDL_WAFER(val) BSP_FLD32(val,16, 21)
410 #define TMS570_SYS1_DIEIDL_WAFER_GET(reg) BSP_FLD32GET(reg,16, 21)
411 #define TMS570_SYS1_DIEIDL_WAFER_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
412 
413 /* field: Y_WAFER_COORDINATE - These read only bits contain the Y wafer coordinate of the device */
414 #define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE(val) BSP_FLD32(val,8, 15)
415 #define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,8, 15)
416 #define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
417 
418 /* field: X_WAFER_COORDINATE - These read only bits contain the X wafer coordinate of the device */
419 #define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE(val) BSP_FLD32(val,0, 7)
420 #define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,0, 7)
421 #define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
422 
423 
424 /*---------------------TMS570_SYS1_DIEIDH---------------------*/
425 /* field: LOT - This read-only register contains the upper 14 bits of the device lot number. */
426 #define TMS570_SYS1_DIEIDH_LOT(val) BSP_FLD32(val,0, 13)
427 #define TMS570_SYS1_DIEIDH_LOT_GET(reg) BSP_FLD32GET(reg,0, 13)
428 #define TMS570_SYS1_DIEIDH_LOT_SET(reg,val) BSP_FLD32SET(reg, val,0, 13)
429 
430 
431 /*-------------------TMS570_SYS1_LPOMONCTL-------------------*/
432 /* field: BIAS_ENABLE - Bias enable. */
433 #define TMS570_SYS1_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24)
434 
435 /* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */
436 #define TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16)
437 
438 /* field: HFTRIM - High frequency oscillator trim value. */
439 #define TMS570_SYS1_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12)
440 #define TMS570_SYS1_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12)
441 #define TMS570_SYS1_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
442 
443 
444 /*--------------------TMS570_SYS1_CLKTEST--------------------*/
445 /* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */
446 #define TMS570_SYS1_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26)
447 
448 /* field: RANGEDETCTRL - Range detection control. */
449 #define TMS570_SYS1_CLKTEST_RANGEDETCTRL BSP_BIT32(25)
450 
451 /* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */
452 #define TMS570_SYS1_CLKTEST_RANGEDETENASSEL BSP_BIT32(24)
453 
454 /* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */
455 #define TMS570_SYS1_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19)
456 #define TMS570_SYS1_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
457 #define TMS570_SYS1_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
458 
459 /* field: SEL_GIO_PIN - GIOB[0] pin clock source valid, clock source select */
460 #define TMS570_SYS1_CLKTEST_SEL_GIO_PIN(val) BSP_FLD32(val,8, 11)
461 #define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_GET(reg) BSP_FLD32GET(reg,8, 11)
462 #define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
463 
464 /* field: SEL_ECP_PIN - ECLK pin clock source select */
465 #define TMS570_SYS1_CLKTEST_SEL_ECP_PIN(val) BSP_FLD32(val,0, 3)
466 #define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_GET(reg) BSP_FLD32GET(reg,0, 3)
467 #define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
468 
469 
470 /*------------------TMS570_SYS1_DFTCTRLREG1------------------*/
471 /* field: DFTWRITE - DFT logic access. */
472 #define TMS570_SYS1_DFTCTRLREG1_DFTWRITE(val) BSP_FLD32(val,12, 13)
473 #define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_GET(reg) BSP_FLD32GET(reg,12, 13)
474 #define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_SET(reg,val) BSP_FLD32SET(reg, val,12, 13)
475 
476 /* field: DFTREAD - DFT logic access. */
477 #define TMS570_SYS1_DFTCTRLREG1_DFTREAD(val) BSP_FLD32(val,8, 9)
478 #define TMS570_SYS1_DFTCTRLREG1_DFTREAD_GET(reg) BSP_FLD32GET(reg,8, 9)
479 #define TMS570_SYS1_DFTCTRLREG1_DFTREAD_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
480 
481 /* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */
482 #define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3)
483 #define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
484 #define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
485 
486 
487 /*------------------TMS570_SYS1_DFTCTRLREG2------------------*/
488 /* field: IMPDF - DFT Implementation defined bits. */
489 #define TMS570_SYS1_DFTCTRLREG2_IMPDF(val) BSP_FLD32(val,4, 31)
490 #define TMS570_SYS1_DFTCTRLREG2_IMPDF_GET(reg) BSP_FLD32GET(reg,4, 31)
491 #define TMS570_SYS1_DFTCTRLREG2_IMPDF_SET(reg,val) BSP_FLD32SET(reg, val,4, 31)
492 
493 /* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */
494 #define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3)
495 #define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
496 #define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
497 
498 
499 /*---------------------TMS570_SYS1_GPREG1---------------------*/
500 /* field: EMIF_FUNC - Enable EMIF functions to be output. */
501 #define TMS570_SYS1_GPREG1_EMIF_FUNC BSP_BIT32(31)
502 
503 /* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */
504 #define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25)
505 #define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25)
506 #define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
507 
508 /* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */
509 #define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19)
510 #define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19)
511 #define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
512 
513 /* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */
514 #define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15)
515 #define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15)
516 #define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
517 
518 
519 /*--------------------TMS570_SYS1_IMPFASTS--------------------*/
520 /* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */
521 #define TMS570_SYS1_IMPFASTS_ECPCLKFUN BSP_BIT32(0)
522 
523 
524 /*--------------------TMS570_SYS1_IMPFTADD--------------------*/
525 /* field: IMPFTADD - These bits contain the fault address when an imprecise abort occurs. */
526 /* Whole 32 bits */
527 
528 /*---------------------TMS570_SYS1_SSIRx---------------------*/
529 /* field: SSKEY1 - System software interrupt request key. A 075h written to these bits initiates IRQ/FIQ interrupts. */
530 #define TMS570_SYS1_SSIRx_SSKEY1(val) BSP_FLD32(val,8, 15)
531 #define TMS570_SYS1_SSIRx_SSKEY1_GET(reg) BSP_FLD32GET(reg,8, 15)
532 #define TMS570_SYS1_SSIRx_SSKEY1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
533 
534 /* field: SSDATA1 - System software interrupt data. These bits contain user read/write register bits. */
535 #define TMS570_SYS1_SSIRx_SSDATA1(val) BSP_FLD32(val,0, 7)
536 #define TMS570_SYS1_SSIRx_SSDATA1_GET(reg) BSP_FLD32GET(reg,0, 7)
537 #define TMS570_SYS1_SSIRx_SSDATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
538 
539 
540 /*---------------------TMS570_SYS1_RAMGCR---------------------*/
541 /* field: RAM_DFT_EN - Functional mode RAM DFT (Design For Test) port enable key. */
542 #define TMS570_SYS1_RAMGCR_RAM_DFT_EN(val) BSP_FLD32(val,16, 19)
543 #define TMS570_SYS1_RAMGCR_RAM_DFT_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
544 #define TMS570_SYS1_RAMGCR_RAM_DFT_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
545 
546 /* field: WST_AENA0 - eSRAM data phase wait state enable bit. */
547 #define TMS570_SYS1_RAMGCR_WST_AENA0 BSP_BIT32(2)
548 
549 /* field: WST_DENA0 - eSRAM data phase wait state enable bit. */
550 #define TMS570_SYS1_RAMGCR_WST_DENA0 BSP_BIT32(0)
551 
552 
553 /*---------------------TMS570_SYS1_BMMCR1---------------------*/
554 /* field: MEMSW - Memory swap key. */
555 #define TMS570_SYS1_BMMCR1_MEMSW(val) BSP_FLD32(val,0, 3)
556 #define TMS570_SYS1_BMMCR1_MEMSW_GET(reg) BSP_FLD32GET(reg,0, 3)
557 #define TMS570_SYS1_BMMCR1_MEMSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
558 
559 
560 /*--------------------TMS570_SYS1_CPURSTCR--------------------*/
561 /* field: CPU_RESET - CPU Reset. */
562 #define TMS570_SYS1_CPURSTCR_CPU_RESET BSP_BIT32(0)
563 
564 
565 /*--------------------TMS570_SYS1_CLKCNTL--------------------*/
566 /* field: VCLK2R - VBUS clock2 ratio. */
567 #define TMS570_SYS1_CLKCNTL_VCLK2R(val) BSP_FLD32(val,24, 27)
568 #define TMS570_SYS1_CLKCNTL_VCLK2R_GET(reg) BSP_FLD32GET(reg,24, 27)
569 #define TMS570_SYS1_CLKCNTL_VCLK2R_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
570 
571 /* field: VCLKR - VBUS clock ratio. */
572 #define TMS570_SYS1_CLKCNTL_VCLKR(val) BSP_FLD32(val,16, 19)
573 #define TMS570_SYS1_CLKCNTL_VCLKR_GET(reg) BSP_FLD32GET(reg,16, 19)
574 #define TMS570_SYS1_CLKCNTL_VCLKR_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
575 
576 /* field: PENA - Peripheral enable bit. */
577 #define TMS570_SYS1_CLKCNTL_PENA BSP_BIT32(8)
578 
579 
580 /*--------------------TMS570_SYS1_ECPCNTL--------------------*/
581 /* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */
582 #define TMS570_SYS1_ECPCNTL_ECPSSEL BSP_BIT32(24)
583 
584 /* field: ECPCOS - ECP continue on suspend. */
585 #define TMS570_SYS1_ECPCNTL_ECPCOS BSP_BIT32(23)
586 
587 /* field: ECPINSEL - Select ECP input clock source. */
588 #define TMS570_SYS1_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17)
589 #define TMS570_SYS1_ECPCNTL_ECPINSEL_GET(reg) BSP_FLD32GET(reg,6, 17)
590 #define TMS570_SYS1_ECPCNTL_ECPINSEL_SET(reg,val) BSP_FLD32SET(reg, val,6, 17)
591 
592 /* field: ECPDIV - ECP divider value. */
593 #define TMS570_SYS1_ECPCNTL_ECPDIV(val) BSP_FLD32(val,0, 15)
594 #define TMS570_SYS1_ECPCNTL_ECPDIV_GET(reg) BSP_FLD32GET(reg,0, 15)
595 #define TMS570_SYS1_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
596 
597 
598 /*---------------------TMS570_SYS1_DEVCR1---------------------*/
599 /* field: DEVPARSEL - Device parity select bit key. */
600 #define TMS570_SYS1_DEVCR1_DEVPARSEL(val) BSP_FLD32(val,0, 3)
601 #define TMS570_SYS1_DEVCR1_DEVPARSEL_GET(reg) BSP_FLD32GET(reg,0, 3)
602 #define TMS570_SYS1_DEVCR1_DEVPARSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
603 
604 
605 /*---------------------TMS570_SYS1_SYSECR---------------------*/
606 /* field: RESET - Software reset bits. Setting RESET1 or clearing RESET0 causes a system software reset. */
607 #define TMS570_SYS1_SYSECR_RESET(val) BSP_FLD32(val,14, 15)
608 #define TMS570_SYS1_SYSECR_RESET_GET(reg) BSP_FLD32GET(reg,14, 15)
609 #define TMS570_SYS1_SYSECR_RESET_SET(reg,val) BSP_FLD32SET(reg, val,14, 15)
610 
611 
612 /*---------------------TMS570_SYS1_SYSESR---------------------*/
613 /* field: PORST - Power-up reset. This bit is set when VCCOR (VCC Out of Range) is detected. */
614 #define TMS570_SYS1_SYSESR_PORST BSP_BIT32(15)
615 
616 /* field: OSCRST - Reset caused by an oscillator failure or PLL cycle slip. */
617 #define TMS570_SYS1_SYSESR_OSCRST BSP_BIT32(14)
618 
619 /* field: WDRST - Watchdog reset flag. */
620 #define TMS570_SYS1_SYSESR_WDRST BSP_BIT32(13)
621 
622 /* field: CPURST - CPU reset flag. This bit is set when the CPU is reset. */
623 #define TMS570_SYS1_SYSESR_CPURST BSP_BIT32(5)
624 
625 /* field: SWRST - Software reset flag. This bit is set when a software system reset has occurred. */
626 #define TMS570_SYS1_SYSESR_SWRST BSP_BIT32(4)
627 
628 /* field: EXTRST - External reset flag. This bit is set when a reset is caused by the external reset pin nRST. */
629 #define TMS570_SYS1_SYSESR_EXTRST BSP_BIT32(3)
630 
631 /* field: MPMODE - This indicates the current memory protection unit (MPU) mode. */
632 #define TMS570_SYS1_SYSESR_MPMODE BSP_BIT32(0)
633 
634 
635 /*--------------------TMS570_SYS1_SYSTASR--------------------*/
636 /* field: EFUSE_Abort - Test Abort status flag. */
637 #define TMS570_SYS1_SYSTASR_EFUSE_Abort(val) BSP_FLD32(val,0, 4)
638 #define TMS570_SYS1_SYSTASR_EFUSE_Abort_GET(reg) BSP_FLD32GET(reg,0, 4)
639 #define TMS570_SYS1_SYSTASR_EFUSE_Abort_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
640 
641 
642 /*--------------------TMS570_SYS1_GLBSTAT--------------------*/
643 /* field: FBSLIP - PLL over cycle slip detection. */
644 #define TMS570_SYS1_GLBSTAT_FBSLIP BSP_BIT32(9)
645 
646 /* field: RFSLIP - PLL under cycle slip detection. */
647 #define TMS570_SYS1_GLBSTAT_RFSLIP BSP_BIT32(8)
648 
649 /* field: OSCFAIL - Oscillator fail flag bit. */
650 #define TMS570_SYS1_GLBSTAT_OSCFAIL BSP_BIT32(0)
651 
652 
653 /*---------------------TMS570_SYS1_DEVID---------------------*/
654 /* field: CP15 - CP15 CPU. This bit indicates whether the CPU has a coprocessor 15 (CP15). */
655 #define TMS570_SYS1_DEVID_CP15 BSP_BIT32(31)
656 
657 /* field: TECH - These bits define the process technology by which the device was manufactured. */
658 #define TMS570_SYS1_DEVID_TECH(val) BSP_FLD32(val,13, 16)
659 #define TMS570_SYS1_DEVID_TECH_GET(reg) BSP_FLD32GET(reg,13, 16)
660 #define TMS570_SYS1_DEVID_TECH_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
661 
662 /* field: I_O_VOLTAGE - Input/output voltage. This bit defines the I/O voltage of the device. */
663 #define TMS570_SYS1_DEVID_I_O_VOLTAGE BSP_BIT32(12)
664 
665 /* field: PERIPHERAL_PARITY - The peripheral memories have no parity. */
666 #define TMS570_SYS1_DEVID_PERIPHERAL_PARITY BSP_BIT32(11)
667 
668 /* field: FLASH_ECC - These bits indicate which parity is present for the program memory. */
669 #define TMS570_SYS1_DEVID_FLASH_ECC(val) BSP_FLD32(val,9, 10)
670 #define TMS570_SYS1_DEVID_FLASH_ECC_GET(reg) BSP_FLD32GET(reg,9, 10)
671 #define TMS570_SYS1_DEVID_FLASH_ECC_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
672 
673 /* field: RAM_ECC - RAM ECC. This bit indicates whether or not RAM memory ECC is present. */
674 #define TMS570_SYS1_DEVID_RAM_ECC BSP_BIT32(8)
675 
676 /* field: VERSION - Version. These bits provide the revision of the device. */
677 #define TMS570_SYS1_DEVID_VERSION(val) BSP_FLD32(val,3, 7)
678 #define TMS570_SYS1_DEVID_VERSION_GET(reg) BSP_FLD32GET(reg,3, 7)
679 #define TMS570_SYS1_DEVID_VERSION_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
680 
681 /* field: PLATFORM_ID - The device is part of the TMS570Px family. The TMS570Px ID is always 5h. */
682 #define TMS570_SYS1_DEVID_PLATFORM_ID(val) BSP_FLD32(val,0, 2)
683 #define TMS570_SYS1_DEVID_PLATFORM_ID_GET(reg) BSP_FLD32GET(reg,0, 2)
684 #define TMS570_SYS1_DEVID_PLATFORM_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
685 
686 
687 /*---------------------TMS570_SYS1_SSIVEC---------------------*/
688 /* field: SSIDATA - System software interrupt data key. */
689 #define TMS570_SYS1_SSIVEC_SSIDATA(val) BSP_FLD32(val,8, 15)
690 #define TMS570_SYS1_SSIVEC_SSIDATA_GET(reg) BSP_FLD32GET(reg,8, 15)
691 #define TMS570_SYS1_SSIVEC_SSIDATA_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
692 
693 /* field: SSIVECT - These bits contain the source for the system software interrupt. */
694 #define TMS570_SYS1_SSIVEC_SSIVECT(val) BSP_FLD32(val,0, 7)
695 #define TMS570_SYS1_SSIVEC_SSIVECT_GET(reg) BSP_FLD32GET(reg,0, 7)
696 #define TMS570_SYS1_SSIVEC_SSIVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
697 
698 
699 /*----------------------TMS570_SYS1_SSIF----------------------*/
700 /* field: SSI_FLAG - System software interrupt flag[4-1]. */
701 #define TMS570_SYS1_SSIF_SSI_FLAG(val) BSP_FLD32(val,0, 3)
702 #define TMS570_SYS1_SSIF_SSI_FLAG_GET(reg) BSP_FLD32GET(reg,0, 3)
703 #define TMS570_SYS1_SSIF_SSI_FLAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
704 
705 
706 
707 #endif /* LIBBSP_ARM_TMS570_SYS1 */
tms570_sys1_t
Definition: reg_sys.h:44
utility.h
Utility macros.
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