RTEMS  5.1
reg_dmm.h
1 /* The header file is generated by make_header.py from DMM.json */
2 /* Current script's version can be found at: */
3 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4 
5 /*
6  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7  *
8  * Czech Technical University in Prague
9  * Zikova 1903/4
10  * 166 36 Praha 6
11  * Czech Republic
12  *
13  * All rights reserved.
14  *
15  * Redistribution and use in source and binary forms, with or without
16  * modification, are permitted provided that the following conditions are met:
17  *
18  * 1. Redistributions of source code must retain the above copyright notice, this
19  * list of conditions and the following disclaimer.
20  * 2. Redistributions in binary form must reproduce the above copyright notice,
21  * this list of conditions and the following disclaimer in the documentation
22  * and/or other materials provided with the distribution.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  *
35  * The views and conclusions contained in the software and documentation are those
36  * of the authors and should not be interpreted as representing official policies,
37  * either expressed or implied, of the FreeBSD Project.
38 */
39 #ifndef LIBBSP_ARM_TMS570_DMM
40 #define LIBBSP_ARM_TMS570_DMM
41 
42 #include <bsp/utility.h>
43 
44 typedef struct{
45  uint32_t GLBCTRL; /*DMM Global Control Register*/
46  uint32_t INTSET; /*DMM Interrupt Set Register*/
47  uint32_t INTCLR; /*DMM Interrupt Clear Register*/
48  uint32_t INTLVL; /*DMM Interrupt Level Register*/
49  uint32_t INTFLG; /*DMM Interrupt Flag Register*/
50  uint32_t OFF1; /*DMM Interrupt Offset 1 Register*/
51  uint32_t OFF2; /*DMM Interrupt Offset 2 Register*/
52  uint32_t DDMDEST; /*DMM Direct Data Mode Destination Register*/
53  uint32_t DDMBL; /*DMM Direct Data Mode Blocksize Register*/
54  uint32_t DDMPT; /*DMM Direct Data Mode Pointer Register*/
55  uint32_t INTPT; /*DMM Direct Data Mode Interrupt Pointer Register*/
56  uint32_t DEST0REG1; /*DMM Destination 0 Region 1*/
57  uint32_t DEST0BL1; /*DMM Destination 0 Blocksize 1*/
58  uint32_t DEST0REG2; /*DMM Destination 0 Region 2*/
59  uint32_t DEST0BL2; /*DMM Destination 0 Blocksize 2*/
60  uint32_t DEST1REG1; /*DMM Destination 1 Region 1*/
61  uint32_t DEST1BL1; /*DMM Destination 1 Blocksize 1*/
62  uint32_t DEST1REG2; /*DMM Destination 1 Region 2*/
63  uint32_t DEST1BL2; /*DMM Destination 1 Blocksize 2*/
64  uint32_t DEST2REG1; /*DMM Destination 2 Region 1*/
65  uint32_t DEST2BL1; /*DMM Destination 2 Blocksize 1*/
66  uint32_t DEST2REG2; /*DMM Destination 2 Region 2*/
67  uint32_t DEST2BL2; /*DMM Destination 2 Blocksize 2*/
68  uint32_t DEST3REG1; /*DMM Destination 3 Region 1*/
69  uint32_t DEST3BL1; /*DMM Destination 3 Blocksize 1*/
70  uint32_t DEST3REG2; /*DMM Destination 3 Region 2*/
71  uint32_t DEST3BL2; /*DMM Destination 3 Blocksize 2*/
72  uint32_t PC0; /*DMM Pin Control 0*/
73  uint32_t PC1; /*DMM Pin Control 1*/
74  uint32_t PC2; /*DMM Pin Control 2*/
75  uint32_t PC3; /*DMM Pin Control 3*/
76  uint32_t PC4; /*DMM Pin Control 4*/
77  uint32_t PC5; /*DMM Pin Control 5*/
78  uint32_t PC6; /*DMM Pin Control 6*/
79  uint32_t PC7; /*DMM Pin Control 7*/
80  uint32_t PC8; /*DMM Pin Control 8*/
81 } tms570_dmm_t;
82 
83 
84 /*---------------------TMS570_DMM_GLBCTRL---------------------*/
85 /* field: BUSY - Busy indicator. */
86 #define TMS570_DMM_GLBCTRL_BUSY BSP_BIT32(24)
87 
88 /* field: CONTCLK - Continuous DMMCLK input. */
89 #define TMS570_DMM_GLBCTRL_CONTCLK BSP_BIT32(18)
90 
91 /* field: COS - Continue on suspend. Influences behavior of module while in debug mode. */
92 #define TMS570_DMM_GLBCTRL_COS BSP_BIT32(17)
93 
94 /* field: RESET - Reset. */
95 #define TMS570_DMM_GLBCTRL_RESET BSP_BIT32(16)
96 
97 /* field: DDM_WIDTH - Packet Width in direct data mode. */
98 #define TMS570_DMM_GLBCTRL_DDM_WIDTH(val) BSP_FLD32(val,9, 10)
99 #define TMS570_DMM_GLBCTRL_DDM_WIDTH_GET(reg) BSP_FLD32GET(reg,9, 10)
100 #define TMS570_DMM_GLBCTRL_DDM_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
101 
102 /* field: TM_DMM - Packet Format. */
103 #define TMS570_DMM_GLBCTRL_TM_DMM BSP_BIT32(8)
104 
105 /* field: ON_OFF - Switch module on or off */
106 #define TMS570_DMM_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3)
107 #define TMS570_DMM_GLBCTRL_ON_OFF_GET(reg) BSP_FLD32GET(reg,0, 3)
108 #define TMS570_DMM_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
109 
110 
111 /*---------------------TMS570_DMM_INTSET---------------------*/
112 /* field: PROG_BUFF - Programmable Buffer Interrupt Set. */
113 #define TMS570_DMM_INTSET_PROG_BUFF BSP_BIT32(17)
114 
115 /* field: EO_BUFF - EO_BUFF */
116 #define TMS570_DMM_INTSET_EO_BUFF BSP_BIT32(16)
117 
118 /* field: DEST3REG2 - Destination 3 Region 2 Interrupt Set. */
119 #define TMS570_DMM_INTSET_DEST3REG2 BSP_BIT32(15)
120 
121 /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */
122 #define TMS570_DMM_INTSET_DEST3REG1 BSP_BIT32(14)
123 
124 /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */
125 #define TMS570_DMM_INTSET_DEST2REG2 BSP_BIT32(13)
126 
127 /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */
128 #define TMS570_DMM_INTSET_DEST2REG1 BSP_BIT32(12)
129 
130 /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */
131 #define TMS570_DMM_INTSET_DEST1REG2 BSP_BIT32(11)
132 
133 /* field: DEST1REG1 - DEST1REG1 */
134 #define TMS570_DMM_INTSET_DEST1REG1 BSP_BIT32(10)
135 
136 /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */
137 #define TMS570_DMM_INTSET_DEST0REG2 BSP_BIT32(9)
138 
139 /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */
140 #define TMS570_DMM_INTSET_DEST0REG1 BSP_BIT32(8)
141 
142 /* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */
143 #define TMS570_DMM_INTSET_BUSERROR BSP_BIT32(7)
144 
145 /* field: BUFF_OVF - Buffer Overflow. */
146 #define TMS570_DMM_INTSET_BUFF_OVF BSP_BIT32(6)
147 
148 /* field: SRC_OVF - Source Overflow. */
149 #define TMS570_DMM_INTSET_SRC_OVF BSP_BIT32(5)
150 
151 /* field: DEST3_ERR - Destination 3 Error. */
152 #define TMS570_DMM_INTSET_DEST3_ERR BSP_BIT32(4)
153 
154 /* field: DEST2_ERR - Destination 2 Error Interrupt Set. */
155 #define TMS570_DMM_INTSET_DEST2_ERR BSP_BIT32(3)
156 
157 /* field: DEST1_ERR - Destination 1 Error Interrupt Set. */
158 #define TMS570_DMM_INTSET_DEST1_ERR BSP_BIT32(2)
159 
160 /* field: DEST0_ERR - Destination 0 Error Interrupt Set. */
161 #define TMS570_DMM_INTSET_DEST0_ERR BSP_BIT32(1)
162 
163 /* field: PACKET_ERR_INT - Packet Error. */
164 #define TMS570_DMM_INTSET_PACKET_ERR_INT BSP_BIT32(0)
165 
166 
167 /*---------------------TMS570_DMM_INTCLR---------------------*/
168 /* field: PROG_BUFF - Programmable Buffer Interrupt Set. */
169 #define TMS570_DMM_INTCLR_PROG_BUFF BSP_BIT32(17)
170 
171 /* field: EO_BUFF - End of Buffer Interrupt Set. */
172 #define TMS570_DMM_INTCLR_EO_BUFF BSP_BIT32(16)
173 
174 /* field: DEST3REG2 - was accessed at the startaddress of Destination 3 Region 2. */
175 #define TMS570_DMM_INTCLR_DEST3REG2 BSP_BIT32(15)
176 
177 /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */
178 #define TMS570_DMM_INTCLR_DEST3REG1 BSP_BIT32(14)
179 
180 /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */
181 #define TMS570_DMM_INTCLR_DEST2REG2 BSP_BIT32(13)
182 
183 /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */
184 #define TMS570_DMM_INTCLR_DEST2REG1 BSP_BIT32(12)
185 
186 /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */
187 #define TMS570_DMM_INTCLR_DEST1REG2 BSP_BIT32(11)
188 
189 /* field: DEST1REG1 - Destination 1 Region 1 Interrupt Set. */
190 #define TMS570_DMM_INTCLR_DEST1REG1 BSP_BIT32(10)
191 
192 /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */
193 #define TMS570_DMM_INTCLR_DEST0REG2 BSP_BIT32(9)
194 
195 /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */
196 #define TMS570_DMM_INTCLR_DEST0REG1 BSP_BIT32(8)
197 
198 /* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */
199 #define TMS570_DMM_INTCLR_BUSERROR BSP_BIT32(7)
200 
201 /* field: BUFF_OVF - Buffer Overflow. */
202 #define TMS570_DMM_INTCLR_BUFF_OVF BSP_BIT32(6)
203 
204 /* field: SRC_OVF - Source Overflow. */
205 #define TMS570_DMM_INTCLR_SRC_OVF BSP_BIT32(5)
206 
207 /* field: DEST3_ERR - Destination 3 Error. */
208 #define TMS570_DMM_INTCLR_DEST3_ERR BSP_BIT32(4)
209 
210 /* field: DEST2_ERR - Destination 2 Error Interrupt Set. */
211 #define TMS570_DMM_INTCLR_DEST2_ERR BSP_BIT32(3)
212 
213 /* field: DEST1_ERR - Destination 1 Error Interrupt Set. */
214 #define TMS570_DMM_INTCLR_DEST1_ERR BSP_BIT32(2)
215 
216 /* field: DEST0_ERR - Destination 0 Error Interrupt Set. */
217 #define TMS570_DMM_INTCLR_DEST0_ERR BSP_BIT32(1)
218 
219 /* field: PACKET_ERR_INT - Packet Error. */
220 #define TMS570_DMM_INTCLR_PACKET_ERR_INT BSP_BIT32(0)
221 
222 
223 /*---------------------TMS570_DMM_INTLVL---------------------*/
224 /* field: PROG_BUFF - Programmable Buffer Interrupt Level */
225 #define TMS570_DMM_INTLVL_PROG_BUFF BSP_BIT32(17)
226 
227 /* field: EO_BUFF - End of Buffer Interrupt Level */
228 #define TMS570_DMM_INTLVL_EO_BUFF BSP_BIT32(16)
229 
230 /* field: DEST3REG2 - Destination 3 Region 2 Interrupt Level */
231 #define TMS570_DMM_INTLVL_DEST3REG2 BSP_BIT32(15)
232 
233 /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Level */
234 #define TMS570_DMM_INTLVL_DEST3REG1 BSP_BIT32(14)
235 
236 /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Level */
237 #define TMS570_DMM_INTLVL_DEST2REG2 BSP_BIT32(13)
238 
239 /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Level */
240 #define TMS570_DMM_INTLVL_DEST2REG1 BSP_BIT32(12)
241 
242 /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Level */
243 #define TMS570_DMM_INTLVL_DEST1REG2 BSP_BIT32(11)
244 
245 /* field: DEST1REG1 - Destination 1 Region 1 Interrupt Level */
246 #define TMS570_DMM_INTLVL_DEST1REG1 BSP_BIT32(10)
247 
248 /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Level */
249 #define TMS570_DMM_INTLVL_DEST0REG2 BSP_BIT32(9)
250 
251 /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Level */
252 #define TMS570_DMM_INTLVL_DEST0REG1 BSP_BIT32(8)
253 
254 /* field: BUSERROR - BMM Bus Error Response */
255 #define TMS570_DMM_INTLVL_BUSERROR BSP_BIT32(7)
256 
257 /* field: BUFF_OVF - Write Buffer Overflow Interrupt Level */
258 #define TMS570_DMM_INTLVL_BUFF_OVF BSP_BIT32(6)
259 
260 /* field: SRC_OVF - Source Overflow Interrupt Level */
261 #define TMS570_DMM_INTLVL_SRC_OVF BSP_BIT32(5)
262 
263 /* field: DEST3_ERR - Destination 3 Error Interrupt Level */
264 #define TMS570_DMM_INTLVL_DEST3_ERR BSP_BIT32(4)
265 
266 /* field: DEST2_ERR - Destination 2 Error Interrupt Level */
267 #define TMS570_DMM_INTLVL_DEST2_ERR BSP_BIT32(3)
268 
269 /* field: DEST1_ERR - Destination 1 Error Interrupt Level */
270 #define TMS570_DMM_INTLVL_DEST1_ERR BSP_BIT32(2)
271 
272 /* field: DEST0_ERR - Destination 0 Error Interrupt Level */
273 #define TMS570_DMM_INTLVL_DEST0_ERR BSP_BIT32(1)
274 
275 /* field: PACKET_ERR_INT - Packet Error Interrupt Level */
276 #define TMS570_DMM_INTLVL_PACKET_ERR_INT BSP_BIT32(0)
277 
278 
279 /*---------------------TMS570_DMM_INTFLG---------------------*/
280 /* field: PROG_BUFF - Programmable Buffer Interrupt Flag */
281 #define TMS570_DMM_INTFLG_PROG_BUFF BSP_BIT32(17)
282 
283 /* field: EO_BUFF - End of Buffer Interrupt Flag */
284 #define TMS570_DMM_INTFLG_EO_BUFF BSP_BIT32(16)
285 
286 /* field: DEST3REG2 - Destination 3 Region 2 Interrupt Flag */
287 #define TMS570_DMM_INTFLG_DEST3REG2 BSP_BIT32(15)
288 
289 /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Flag */
290 #define TMS570_DMM_INTFLG_DEST3REG1 BSP_BIT32(14)
291 
292 /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Flag */
293 #define TMS570_DMM_INTFLG_DEST2REG2 BSP_BIT32(13)
294 
295 /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Flag */
296 #define TMS570_DMM_INTFLG_DEST2REG1 BSP_BIT32(12)
297 
298 /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Flag */
299 #define TMS570_DMM_INTFLG_DEST1REG2 BSP_BIT32(11)
300 
301 /* field: DEST1REG1 - Destination 1 Region 1 Interrupt Flag */
302 #define TMS570_DMM_INTFLG_DEST1REG1 BSP_BIT32(10)
303 
304 /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Flag */
305 #define TMS570_DMM_INTFLG_DEST0REG2 BSP_BIT32(9)
306 
307 /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Flag */
308 #define TMS570_DMM_INTFLG_DEST0REG1 BSP_BIT32(8)
309 
310 /* field: BUSERROR - BMM Bus Error Response. */
311 #define TMS570_DMM_INTFLG_BUSERROR BSP_BIT32(7)
312 
313 /* field: BUFF_OVF - Write Buffer Overflow Interrupt Flag */
314 #define TMS570_DMM_INTFLG_BUFF_OVF BSP_BIT32(6)
315 
316 /* field: SRC_OVF - Source Overflow Interrupt Flag */
317 #define TMS570_DMM_INTFLG_SRC_OVF BSP_BIT32(5)
318 
319 /* field: DEST3_ERR - Destination 3 Error Interrupt Flag */
320 #define TMS570_DMM_INTFLG_DEST3_ERR BSP_BIT32(4)
321 
322 /* field: DEST2_ERR - Destination 2 Error Interrupt Flag */
323 #define TMS570_DMM_INTFLG_DEST2_ERR BSP_BIT32(3)
324 
325 /* field: DEST1_ERR - Destination 1 Error Interrupt Flag */
326 #define TMS570_DMM_INTFLG_DEST1_ERR BSP_BIT32(2)
327 
328 /* field: DEST0_ERR - Destination 0 Error Interrupt Flag */
329 #define TMS570_DMM_INTFLG_DEST0_ERR BSP_BIT32(1)
330 
331 /* field: PACKET_ERR_INT - Packet Error Interrupt Flag */
332 #define TMS570_DMM_INTFLG_PACKET_ERR_INT BSP_BIT32(0)
333 
334 
335 /*----------------------TMS570_DMM_OFF1----------------------*/
336 /* field: OFFSET - User and privilege mode (read): */
337 #define TMS570_DMM_OFF1_OFFSET(val) BSP_FLD32(val,0, 4)
338 #define TMS570_DMM_OFF1_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4)
339 #define TMS570_DMM_OFF1_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
340 
341 
342 /*----------------------TMS570_DMM_OFF2----------------------*/
343 /* field: OFFSET - User and privilege mode (read): */
344 #define TMS570_DMM_OFF2_OFFSET(val) BSP_FLD32(val,0, 4)
345 #define TMS570_DMM_OFF2_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4)
346 #define TMS570_DMM_OFF2_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
347 
348 
349 /*---------------------TMS570_DMM_DDMDEST---------------------*/
350 /* field: STARTADDR - These bits define the starting address of the buffer. */
351 /* Whole 32 bits */
352 
353 /*----------------------TMS570_DMM_DDMBL----------------------*/
354 /* field: BLOCKSIZE - These bits define the size of the buffer region */
355 #define TMS570_DMM_DDMBL_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
356 #define TMS570_DMM_DDMBL_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
357 #define TMS570_DMM_DDMBL_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
358 
359 
360 /*----------------------TMS570_DMM_DDMPT----------------------*/
361 /* field: POINTER - These bits hold the pointer to the next entry to be written in the buffer. */
362 #define TMS570_DMM_DDMPT_POINTER(val) BSP_FLD32(val,0, 14)
363 #define TMS570_DMM_DDMPT_POINTER_GET(reg) BSP_FLD32GET(reg,0, 14)
364 #define TMS570_DMM_DDMPT_POINTER_SET(reg,val) BSP_FLD32SET(reg, val,0, 14)
365 
366 
367 /*----------------------TMS570_DMM_INTPT----------------------*/
368 /* field: INTPT - Interrupt Pointer. When the buffer pointer (Section 30.3. */
369 #define TMS570_DMM_INTPT_INTPT(val) BSP_FLD32(val,0, 14)
370 #define TMS570_DMM_INTPT_INTPT_GET(reg) BSP_FLD32GET(reg,0, 14)
371 #define TMS570_DMM_INTPT_INTPT_SET(reg,val) BSP_FLD32SET(reg, val,0, 14)
372 
373 
374 /*--------------------TMS570_DMM_DESTxREG1--------------------*/
375 /* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */
376 #define TMS570_DMM_DESTxREG1_BASEADDR(val) BSP_FLD32(val,18, 31)
377 #define TMS570_DMM_DESTxREG1_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
378 #define TMS570_DMM_DESTxREG1_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
379 
380 /* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */
381 #define TMS570_DMM_DESTxREG1_BLOCKADDR(val) BSP_FLD32(val,0, 17)
382 #define TMS570_DMM_DESTxREG1_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
383 #define TMS570_DMM_DESTxREG1_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
384 
385 
386 /*--------------------TMS570_DMM_DESTxBL1--------------------*/
387 /* field: BLOCKSIZE - These bits define the length of the buffer region. */
388 #define TMS570_DMM_DESTxBL1_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
389 #define TMS570_DMM_DESTxBL1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
390 #define TMS570_DMM_DESTxBL1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
391 
392 
393 /*--------------------TMS570_DMM_DESTxREG2--------------------*/
394 /* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */
395 #define TMS570_DMM_DESTxREG2_BASEADDR(val) BSP_FLD32(val,18, 31)
396 #define TMS570_DMM_DESTxREG2_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
397 #define TMS570_DMM_DESTxREG2_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
398 
399 /* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */
400 #define TMS570_DMM_DESTxREG2_BLOCKADDR(val) BSP_FLD32(val,0, 17)
401 #define TMS570_DMM_DESTxREG2_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
402 #define TMS570_DMM_DESTxREG2_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
403 
404 
405 /*--------------------TMS570_DMM_DESTxBL2--------------------*/
406 /* field: BLOCKSIZE - These bits define the length of the buffer region. */
407 #define TMS570_DMM_DESTxBL2_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
408 #define TMS570_DMM_DESTxBL2_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
409 #define TMS570_DMM_DESTxBL2_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
410 
411 
412 /*-----------------------TMS570_DMM_PC0-----------------------*/
413 /* field: ENAFUNC - Functional mode of DMMENA pin. */
414 #define TMS570_DMM_PC0_ENAFUNC BSP_BIT32(18)
415 
416 /* field: DATAxFUNC - Functional mode of DMMDATA[x] pin. */
417 #define TMS570_DMM_PC0_DATAxFUNC(val) BSP_FLD32(val,2, 17)
418 #define TMS570_DMM_PC0_DATAxFUNC_GET(reg) BSP_FLD32GET(reg,2, 17)
419 #define TMS570_DMM_PC0_DATAxFUNC_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
420 
421 /* field: CLKFUNC - Functional mode of DMMCLK pin. */
422 #define TMS570_DMM_PC0_CLKFUNC BSP_BIT32(1)
423 
424 /* field: SYNCFUNC - Functional mode of DMMSYNC pin. */
425 #define TMS570_DMM_PC0_SYNCFUNC BSP_BIT32(0)
426 
427 
428 /*-----------------------TMS570_DMM_PC1-----------------------*/
429 /* field: ENADIR - Direction of DMMENA pin. */
430 #define TMS570_DMM_PC1_ENADIR BSP_BIT32(18)
431 
432 /* field: DATAxDIR - Direction of DMMDATA[x] pin. */
433 #define TMS570_DMM_PC1_DATAxDIR(val) BSP_FLD32(val,2, 17)
434 #define TMS570_DMM_PC1_DATAxDIR_GET(reg) BSP_FLD32GET(reg,2, 17)
435 #define TMS570_DMM_PC1_DATAxDIR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
436 
437 /* field: CLKDIR - Direction of DMMCLK pin. */
438 #define TMS570_DMM_PC1_CLKDIR BSP_BIT32(1)
439 
440 /* field: SYNCDIR - Direction of DMMSYNC pin. */
441 #define TMS570_DMM_PC1_SYNCDIR BSP_BIT32(0)
442 
443 
444 /*-----------------------TMS570_DMM_PC2-----------------------*/
445 /* field: ENAIN - DMMENA input. This bit reflects the state of the pin in all modes. */
446 #define TMS570_DMM_PC2_ENAIN BSP_BIT32(18)
447 
448 /* field: DATAxIN - DMMDATA[x] input. This bit reflects the state of the pin in all modes. */
449 #define TMS570_DMM_PC2_DATAxIN(val) BSP_FLD32(val,2, 17)
450 #define TMS570_DMM_PC2_DATAxIN_GET(reg) BSP_FLD32GET(reg,2, 17)
451 #define TMS570_DMM_PC2_DATAxIN_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
452 
453 /* field: CLKIN - DMMCLK input. This bit reflects the state of the pin in all modes. */
454 #define TMS570_DMM_PC2_CLKIN BSP_BIT32(1)
455 
456 /* field: SYNCIN - DMMSYNC input. */
457 #define TMS570_DMM_PC2_SYNCIN BSP_BIT32(0)
458 
459 
460 /*-----------------------TMS570_DMM_PC3-----------------------*/
461 /* field: ENAOUT - Output state of DMMENA pin. */
462 #define TMS570_DMM_PC3_ENAOUT BSP_BIT32(18)
463 
464 /* field: DATAxOUT - Output state of DMMDATA[x] pin. This bit sets the pin to logic low or high level. */
465 #define TMS570_DMM_PC3_DATAxOUT(val) BSP_FLD32(val,2, 17)
466 #define TMS570_DMM_PC3_DATAxOUT_GET(reg) BSP_FLD32GET(reg,2, 17)
467 #define TMS570_DMM_PC3_DATAxOUT_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
468 
469 /* field: CLKOUT - Output state of DMMCLK pin. */
470 #define TMS570_DMM_PC3_CLKOUT BSP_BIT32(1)
471 
472 /* field: SYNCOUT - Output state of DMMSYNC pin. This bit sets the pin to logic low or high level. */
473 #define TMS570_DMM_PC3_SYNCOUT BSP_BIT32(0)
474 
475 
476 /*-----------------------TMS570_DMM_PC4-----------------------*/
477 /* field: ENASET - control register bit to 1 regardless of the current value in the ENAOUT bit. */
478 #define TMS570_DMM_PC4_ENASET BSP_BIT32(18)
479 
480 /* field: DATAxSET - Sets output state of DMMDATA[x] pin to logic high. */
481 #define TMS570_DMM_PC4_DATAxSET(val) BSP_FLD32(val,2, 17)
482 #define TMS570_DMM_PC4_DATAxSET_GET(reg) BSP_FLD32GET(reg,2, 17)
483 #define TMS570_DMM_PC4_DATAxSET_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
484 
485 /* field: CLKSET - Sets output state of DMMCLK pin to logic high. */
486 #define TMS570_DMM_PC4_CLKSET BSP_BIT32(1)
487 
488 /* field: SYNCSET - Sets output state of DMMSYNC pin logic high. */
489 #define TMS570_DMM_PC4_SYNCSET BSP_BIT32(0)
490 
491 
492 /*-----------------------TMS570_DMM_PC5-----------------------*/
493 /* field: ENACLR - Sets output state of DMMENA pin to logic low. */
494 #define TMS570_DMM_PC5_ENACLR BSP_BIT32(18)
495 
496 /* field: DATAxCLR - Sets output state of DMMDATA[x] pin to logic low. */
497 #define TMS570_DMM_PC5_DATAxCLR(val) BSP_FLD32(val,2, 17)
498 #define TMS570_DMM_PC5_DATAxCLR_GET(reg) BSP_FLD32GET(reg,2, 17)
499 #define TMS570_DMM_PC5_DATAxCLR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
500 
501 /* field: CLKCLR - Sets output state of DMMCLK pin to logic low. */
502 #define TMS570_DMM_PC5_CLKCLR BSP_BIT32(1)
503 
504 /* field: SYNCCLR - Sets output state of DMMSYNC pin to logic low. */
505 #define TMS570_DMM_PC5_SYNCCLR BSP_BIT32(0)
506 
507 
508 /*-----------------------TMS570_DMM_PC6-----------------------*/
509 /* field: ENAPDR - Open Drain enable. */
510 #define TMS570_DMM_PC6_ENAPDR BSP_BIT32(18)
511 
512 /* field: DATAxPDR - Open Drain enable. */
513 #define TMS570_DMM_PC6_DATAxPDR(val) BSP_FLD32(val,2, 17)
514 #define TMS570_DMM_PC6_DATAxPDR_GET(reg) BSP_FLD32GET(reg,2, 17)
515 #define TMS570_DMM_PC6_DATAxPDR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
516 
517 /* field: CLKPDR - Open Drain enable. */
518 #define TMS570_DMM_PC6_CLKPDR BSP_BIT32(1)
519 
520 /* field: SYNCPDR - Open Drain enable. */
521 #define TMS570_DMM_PC6_SYNCPDR BSP_BIT32(0)
522 
523 
524 /*-----------------------TMS570_DMM_PC7-----------------------*/
525 /* field: ENAPDIS - Pull disable. */
526 #define TMS570_DMM_PC7_ENAPDIS BSP_BIT32(18)
527 
528 /* field: DATAxPDIS - Pull disable. */
529 #define TMS570_DMM_PC7_DATAxPDIS(val) BSP_FLD32(val,2, 17)
530 #define TMS570_DMM_PC7_DATAxPDIS_GET(reg) BSP_FLD32GET(reg,2, 17)
531 #define TMS570_DMM_PC7_DATAxPDIS_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
532 
533 /* field: CLKPDIS - Pull disable. */
534 #define TMS570_DMM_PC7_CLKPDIS BSP_BIT32(1)
535 
536 /* field: SYNCPDIS - Pull disable. */
537 #define TMS570_DMM_PC7_SYNCPDIS BSP_BIT32(0)
538 
539 
540 /*-----------------------TMS570_DMM_PC8-----------------------*/
541 /* field: ENAPSEL - Pull disable. */
542 #define TMS570_DMM_PC8_ENAPSEL BSP_BIT32(18)
543 
544 /* field: DATAxPSEL - Pull disable. */
545 #define TMS570_DMM_PC8_DATAxPSEL(val) BSP_FLD32(val,2, 17)
546 #define TMS570_DMM_PC8_DATAxPSEL_GET(reg) BSP_FLD32GET(reg,2, 17)
547 #define TMS570_DMM_PC8_DATAxPSEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
548 
549 /* field: CLKPSEL - Pull disable. */
550 #define TMS570_DMM_PC8_CLKPSEL BSP_BIT32(1)
551 
552 /* field: SYNCPSEL - Pull disable. */
553 #define TMS570_DMM_PC8_SYNCPSEL BSP_BIT32(0)
554 
555 
556 
557 #endif /* LIBBSP_ARM_TMS570_DMM */
utility.h
Utility macros.
tms570_dmm_t
Definition: reg_dmm.h:44
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