RTEMS  5.1
reg_dma.h
1 /* The header file is generated by make_header.py from DMA.json */
2 /* Current script's version can be found at: */
3 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4 
5 /*
6  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7  *
8  * Czech Technical University in Prague
9  * Zikova 1903/4
10  * 166 36 Praha 6
11  * Czech Republic
12  *
13  * All rights reserved.
14  *
15  * Redistribution and use in source and binary forms, with or without
16  * modification, are permitted provided that the following conditions are met:
17  *
18  * 1. Redistributions of source code must retain the above copyright notice, this
19  * list of conditions and the following disclaimer.
20  * 2. Redistributions in binary form must reproduce the above copyright notice,
21  * this list of conditions and the following disclaimer in the documentation
22  * and/or other materials provided with the distribution.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  *
35  * The views and conclusions contained in the software and documentation are those
36  * of the authors and should not be interpreted as representing official policies,
37  * either expressed or implied, of the FreeBSD Project.
38 */
39 #ifndef LIBBSP_ARM_TMS570_DMA
40 #define LIBBSP_ARM_TMS570_DMA
41 
42 #include <bsp/utility.h>
43 
44 typedef struct{
45  uint32_t STARTADD; /*DMA Memory Protection Region start Address Register*/
46  uint32_t ENDADD; /*DMA Memory Protection Region End Address Register*/
47 } tms570_memory_prot_t;
48 
49 typedef struct{
50  uint32_t GCTRL; /*Global Control Register*/
51  uint32_t PEND; /*Channel Pending Register*/
52  uint8_t reserved1 [4];
53  uint32_t DMASTAT; /*DMA Status Register*/
54  uint8_t reserved2 [4];
55  uint32_t HWCHENAS; /*HW Channel Enable Set and Status Register*/
56  uint8_t reserved3 [4];
57  uint32_t HWCHENAR; /*HW Channel Enable Reset and Status Register*/
58  uint8_t reserved4 [4];
59  uint32_t SWCHENAS; /*SW Channel Enable Set and Status Register*/
60  uint8_t reserved5 [4];
61  uint32_t SWCHENAR; /*SW Channel Enable Reset and Status Register*/
62  uint8_t reserved6 [4];
63  uint32_t CHPRIOS; /*Channel Priority Set Register*/
64  uint8_t reserved7 [4];
65  uint32_t CHPRIOR; /*Channel Priority Reset Register*/
66  uint8_t reserved8 [4];
67  uint32_t GCHIENAS; /*Global Channel Interrupt Enable Set Register*/
68  uint8_t reserved9 [4];
69  uint32_t GCHIENAR; /*Global Channel Interrupt Enable Reset Register*/
70  uint8_t reserved10 [4];
71  uint32_t DREQASI[4]; /*DMA Request Assignment Register 0*/
72  uint8_t reserved11 [48];
73  uint32_t PAR0; /*Port Assignment Register 0*/
74  uint32_t PAR1; /*Port Assignment Register 1*/
75  uint8_t reserved12 [24];
76  uint32_t FTCMAP; /*FTC Interrupt Mapping Register*/
77  uint8_t reserved13 [4];
78  uint32_t LFSMAP; /*LFS Interrupt Mapping Register*/
79  uint8_t reserved14 [4];
80  uint32_t HBCMAP; /*HBC Interrupt Mapping Register*/
81  uint8_t reserved15 [4];
82  uint32_t BTCMAP; /*BTC Interrupt Mapping Register*/
83  uint8_t reserved16 [4];
84  uint32_t BERMAP; /*BER Interrupt Mapping Register*/
85  uint8_t reserved17 [4];
86  uint32_t FTCINTENAS; /*FTC Interrupt Enable Set*/
87  uint8_t reserved18 [4];
88  uint32_t FTCINTENAR; /*FTC Interrupt Enable Reset*/
89  uint8_t reserved19 [4];
90  uint32_t LFSINTENAS; /*LFS Interrupt Enable Set*/
91  uint8_t reserved20 [4];
92  uint32_t LFSINTENAR; /*LFS Interrupt Enable Reset*/
93  uint8_t reserved21 [4];
94  uint32_t HBCINTENAS; /*HBC Interrupt Enable Set*/
95  uint8_t reserved22 [4];
96  uint32_t HBCINTENAR; /*HBC Interrupt Enable Reset*/
97  uint8_t reserved23 [4];
98  uint32_t BTCINTENAS; /*BTC Interrupt Enable Set*/
99  uint8_t reserved24 [4];
100  uint32_t BTCINTENAR; /*BTC Interrupt Enable Reset*/
101  uint8_t reserved25 [4];
102  uint32_t GINTFLAG; /*Global Interrupt Flag Register*/
103  uint8_t reserved26 [4];
104  uint32_t FTCFLAG; /*FTC Interrupt Flag Register*/
105  uint8_t reserved27 [4];
106  uint32_t LFSFLAG; /*LFS Interrupt Flag Register*/
107  uint8_t reserved28 [4];
108  uint32_t HBCFLAG; /*HBC Interrupt Flag Register*/
109  uint8_t reserved29 [4];
110  uint32_t BTCFLAG; /*BTC Interrupt Flag Register*/
111  uint8_t reserved30 [4];
112  uint32_t BERFLAG; /*BER Interrupt Flag Register*/
113  uint8_t reserved31 [4];
114  uint32_t FTCAOFFSET; /*FTCA Interrupt Channel Offset Register*/
115  uint32_t LFSAOFFSET; /*LFSA Interrupt Channel Offset Register*/
116  uint32_t HBCAOFFSET; /*HBCA Interrupt Channel Offset Register*/
117  uint32_t BTCAOFFSET; /*BTCA Interrupt Channel Offset Register*/
118  uint32_t BERAOFFSET; /*BERA Interrupt Channel Offset Register*/
119  uint32_t FTCBOFFSET; /*FTCB Interrupt Channel Offset Register*/
120  uint32_t LFSBOFFSET; /*LFSB Interrupt Channel Offset Register*/
121  uint32_t HBCBOFFSET; /*HBCB Interrupt Channel Offset Register*/
122  uint32_t BTCBOFFSET; /*BTCB Interrupt Channel Offset Register*/
123  uint32_t BERBOFFSET; /*BERB Interrupt Channel Offset Register*/
124  uint8_t reserved32 [4];
125  uint32_t PTCRL; /*Port Control Register*/
126  uint32_t RTCTRL; /*RAM Test Control Register*/
127  uint32_t DCTRL; /*Debug Control*/
128  uint32_t WPR; /*Watch Point Register*/
129  uint32_t WMR; /*Watch Mask Register*/
130  uint8_t reserved33 [12];
131  uint32_t PBACSADDR; /*Port B Active Channel Source Address Register*/
132  uint32_t PBACDADDR; /*Port B Active Channel Destination Address Register*/
133  uint32_t PBACTC; /*Port B Active Channel Transfer Count Register*/
134  uint8_t reserved34 [4];
135  uint32_t DMAPCR; /*Parity Control Register*/
136  uint32_t DMAPAR; /*DMA Parity Error Address Register*/
137  uint32_t DMAMPCTRL; /*DMA Memory Protection Control Register*/
138  uint32_t DMAMPST; /*DMA Memory Protection Status Register*/
139  tms570_memory_prot_t DMAMPROS[4];/*DMA Memory Protection Regions*/
140 } tms570_dma_t;
141 
142 
143 /*--------------------TMS570_DMA_STARTADD--------------------*/
144 /* field: STARTADDRESS - Start Address defines the address at which the region begins. */
145 /* Whole 32 bits */
146 
147 /*---------------------TMS570_DMA_ENDADD---------------------*/
148 /* field: ENDADDRESS - End Address defines the address at which the region ends. */
149 /* Whole 32 bits */
150 
151 /*----------------------TMS570_DMA_GCTRL----------------------*/
152 /* field: DMA_EN - DMA enable bit. */
153 #define TMS570_DMA_GCTRL_DMA_EN BSP_BIT32(16)
154 
155 /* field: BUS_BUSY - This bit indicates status of DMA external AHB bus status. */
156 #define TMS570_DMA_GCTRL_BUS_BUSY BSP_BIT32(14)
157 
158 /* field: DEBUG_MODE - Debug Mode. */
159 #define TMS570_DMA_GCTRL_DEBUG_MODE(val) BSP_FLD32(val,8, 9)
160 #define TMS570_DMA_GCTRL_DEBUG_MODE_GET(reg) BSP_FLD32GET(reg,8, 9)
161 #define TMS570_DMA_GCTRL_DEBUG_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
162 
163 /* field: DMA_RES - DMA software reset */
164 #define TMS570_DMA_GCTRL_DMA_RES BSP_BIT32(0)
165 
166 
167 /*----------------------TMS570_DMA_PEND----------------------*/
168 /* field: PEND - Channel pending register. */
169 #define TMS570_DMA_PEND_PEND(val) BSP_FLD32(val,0, 15)
170 #define TMS570_DMA_PEND_PEND_GET(reg) BSP_FLD32GET(reg,0, 15)
171 #define TMS570_DMA_PEND_PEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
172 
173 
174 /*---------------------TMS570_DMA_DMASTAT---------------------*/
175 /* field: STCH - Status of DMA channels. */
176 #define TMS570_DMA_DMASTAT_STCH(val) BSP_FLD32(val,0, 15)
177 #define TMS570_DMA_DMASTAT_STCH_GET(reg) BSP_FLD32GET(reg,0, 15)
178 #define TMS570_DMA_DMASTAT_STCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
179 
180 
181 /*--------------------TMS570_DMA_HWCHENAS--------------------*/
182 /* field: HWCHENA - Hardware channel enable bit. */
183 #define TMS570_DMA_HWCHENAS_HWCHENA(val) BSP_FLD32(val,0, 15)
184 #define TMS570_DMA_HWCHENAS_HWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15)
185 #define TMS570_DMA_HWCHENAS_HWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
186 
187 
188 /*--------------------TMS570_DMA_HWCHENAR--------------------*/
189 /* field: HWCHDIS - HW channel disable bit. */
190 #define TMS570_DMA_HWCHENAR_HWCHDIS(val) BSP_FLD32(val,0, 15)
191 #define TMS570_DMA_HWCHENAR_HWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
192 #define TMS570_DMA_HWCHENAR_HWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
193 
194 
195 /*--------------------TMS570_DMA_SWCHENAS--------------------*/
196 /* field: SWCHENA - SW channel enable bit. */
197 #define TMS570_DMA_SWCHENAS_SWCHENA(val) BSP_FLD32(val,0, 15)
198 #define TMS570_DMA_SWCHENAS_SWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15)
199 #define TMS570_DMA_SWCHENAS_SWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
200 
201 
202 /*--------------------TMS570_DMA_SWCHENAR--------------------*/
203 /* field: SWCHDIS - SW channel disable bit. */
204 #define TMS570_DMA_SWCHENAR_SWCHDIS(val) BSP_FLD32(val,0, 15)
205 #define TMS570_DMA_SWCHENAR_SWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
206 #define TMS570_DMA_SWCHENAR_SWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
207 
208 
209 /*---------------------TMS570_DMA_CHPRIOS---------------------*/
210 /* field: CPS - Channel priority set bit. */
211 #define TMS570_DMA_CHPRIOS_CPS(val) BSP_FLD32(val,0, 15)
212 #define TMS570_DMA_CHPRIOS_CPS_GET(reg) BSP_FLD32GET(reg,0, 15)
213 #define TMS570_DMA_CHPRIOS_CPS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
214 
215 
216 /*---------------------TMS570_DMA_CHPRIOR---------------------*/
217 /* field: CPR - Channel priority reset bit. */
218 #define TMS570_DMA_CHPRIOR_CPR(val) BSP_FLD32(val,0, 15)
219 #define TMS570_DMA_CHPRIOR_CPR_GET(reg) BSP_FLD32GET(reg,0, 15)
220 #define TMS570_DMA_CHPRIOR_CPR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
221 
222 
223 /*--------------------TMS570_DMA_GCHIENAS--------------------*/
224 /* field: GCHIE - Global channel interrupt enable bit. */
225 #define TMS570_DMA_GCHIENAS_GCHIE(val) BSP_FLD32(val,0, 15)
226 #define TMS570_DMA_GCHIENAS_GCHIE_GET(reg) BSP_FLD32GET(reg,0, 15)
227 #define TMS570_DMA_GCHIENAS_GCHIE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
228 
229 
230 /*--------------------TMS570_DMA_GCHIENAR--------------------*/
231 /* field: GCHID - Global channel interrupt disable bit. */
232 #define TMS570_DMA_GCHIENAR_GCHID(val) BSP_FLD32(val,0, 15)
233 #define TMS570_DMA_GCHIENAR_GCHID_GET(reg) BSP_FLD32GET(reg,0, 15)
234 #define TMS570_DMA_GCHIENAR_GCHID_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
235 
236 
237 /*---------------------TMS570_DMA_DREQASI---------------------*/
238 /* field: CH0ASI - Channel 0 assignment. This bit field chooses the DMA request assignment for channel 0. */
239 #define TMS570_DMA_DREQASI_CH0ASI(val) BSP_FLD32(val,24, 29)
240 #define TMS570_DMA_DREQASI_CH0ASI_GET(reg) BSP_FLD32GET(reg,24, 29)
241 #define TMS570_DMA_DREQASI_CH0ASI_SET(reg,val) BSP_FLD32SET(reg, val,24, 29)
242 
243 /* field: CH1ASI - Channel 1 assignment. This bit field chooses the DMA request assignment for channel 1. */
244 #define TMS570_DMA_DREQASI_CH1ASI(val) BSP_FLD32(val,16, 21)
245 #define TMS570_DMA_DREQASI_CH1ASI_GET(reg) BSP_FLD32GET(reg,16, 21)
246 #define TMS570_DMA_DREQASI_CH1ASI_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
247 
248 /* field: CH2ASI - Channel 2 assignment. This bit field chooses the DMA request assignment for channel 2. */
249 #define TMS570_DMA_DREQASI_CH2ASI(val) BSP_FLD32(val,8, 13)
250 #define TMS570_DMA_DREQASI_CH2ASI_GET(reg) BSP_FLD32GET(reg,8, 13)
251 #define TMS570_DMA_DREQASI_CH2ASI_SET(reg,val) BSP_FLD32SET(reg, val,8, 13)
252 
253 /* field: CH3ASI - Channel 3 assignment. This bit field chooses the DMA request assignment for channel 3. */
254 #define TMS570_DMA_DREQASI_CH3ASI(val) BSP_FLD32(val,0, 5)
255 #define TMS570_DMA_DREQASI_CH3ASI_GET(reg) BSP_FLD32GET(reg,0, 5)
256 #define TMS570_DMA_DREQASI_CH3ASI_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
257 
258 
259 /*----------------------TMS570_DMA_PAR0----------------------*/
260 /* field: CH0PA - These bit fields determine to which port channel 0 is assigned. */
261 #define TMS570_DMA_PAR0_CH0PA(val) BSP_FLD32(val,28, 30)
262 #define TMS570_DMA_PAR0_CH0PA_GET(reg) BSP_FLD32GET(reg,28, 30)
263 #define TMS570_DMA_PAR0_CH0PA_SET(reg,val) BSP_FLD32SET(reg, val,28, 30)
264 
265 /* field: CH1PA - These bit fields determine to which port channel 1 is assigned. */
266 #define TMS570_DMA_PAR0_CH1PA(val) BSP_FLD32(val,24, 26)
267 #define TMS570_DMA_PAR0_CH1PA_GET(reg) BSP_FLD32GET(reg,24, 26)
268 #define TMS570_DMA_PAR0_CH1PA_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
269 
270 /* field: CH2PA - These bit fields determine to which port channel 2 is assigned. */
271 #define TMS570_DMA_PAR0_CH2PA(val) BSP_FLD32(val,20, 22)
272 #define TMS570_DMA_PAR0_CH2PA_GET(reg) BSP_FLD32GET(reg,20, 22)
273 #define TMS570_DMA_PAR0_CH2PA_SET(reg,val) BSP_FLD32SET(reg, val,20, 22)
274 
275 /* field: CH3PA - These bit fields determine to which port channel 3 is assigned. */
276 #define TMS570_DMA_PAR0_CH3PA(val) BSP_FLD32(val,16, 18)
277 #define TMS570_DMA_PAR0_CH3PA_GET(reg) BSP_FLD32GET(reg,16, 18)
278 #define TMS570_DMA_PAR0_CH3PA_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
279 
280 /* field: CH4PA - These bit fields determine to which port channel 4 is assigned. */
281 #define TMS570_DMA_PAR0_CH4PA(val) BSP_FLD32(val,12, 14)
282 #define TMS570_DMA_PAR0_CH4PA_GET(reg) BSP_FLD32GET(reg,12, 14)
283 #define TMS570_DMA_PAR0_CH4PA_SET(reg,val) BSP_FLD32SET(reg, val,12, 14)
284 
285 /* field: CH5PA - These bit fields determine to which port channel 5 is assigned. */
286 #define TMS570_DMA_PAR0_CH5PA(val) BSP_FLD32(val,8, 10)
287 #define TMS570_DMA_PAR0_CH5PA_GET(reg) BSP_FLD32GET(reg,8, 10)
288 #define TMS570_DMA_PAR0_CH5PA_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
289 
290 /* field: CH6PA - These bit fields determine to which port channel 6 is assigned. */
291 #define TMS570_DMA_PAR0_CH6PA(val) BSP_FLD32(val,4, 6)
292 #define TMS570_DMA_PAR0_CH6PA_GET(reg) BSP_FLD32GET(reg,4, 6)
293 #define TMS570_DMA_PAR0_CH6PA_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
294 
295 /* field: CH7PA - These bit fields determine to which port channel 7 is assigned. */
296 #define TMS570_DMA_PAR0_CH7PA(val) BSP_FLD32(val,0, 2)
297 #define TMS570_DMA_PAR0_CH7PA_GET(reg) BSP_FLD32GET(reg,0, 2)
298 #define TMS570_DMA_PAR0_CH7PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
299 
300 
301 /*----------------------TMS570_DMA_PAR1----------------------*/
302 /* field: CH8PA - These bit fields determine to which port channel 8 is assigned. */
303 #define TMS570_DMA_PAR1_CH8PA(val) BSP_FLD32(val,28, 30)
304 #define TMS570_DMA_PAR1_CH8PA_GET(reg) BSP_FLD32GET(reg,28, 30)
305 #define TMS570_DMA_PAR1_CH8PA_SET(reg,val) BSP_FLD32SET(reg, val,28, 30)
306 
307 /* field: CH9PA - These bit fields determine to which port channel 9 is assigned. */
308 #define TMS570_DMA_PAR1_CH9PA(val) BSP_FLD32(val,24, 26)
309 #define TMS570_DMA_PAR1_CH9PA_GET(reg) BSP_FLD32GET(reg,24, 26)
310 #define TMS570_DMA_PAR1_CH9PA_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
311 
312 /* field: CH10PA - These bit fields determine to which port channel 10 is assigned. */
313 #define TMS570_DMA_PAR1_CH10PA(val) BSP_FLD32(val,20, 22)
314 #define TMS570_DMA_PAR1_CH10PA_GET(reg) BSP_FLD32GET(reg,20, 22)
315 #define TMS570_DMA_PAR1_CH10PA_SET(reg,val) BSP_FLD32SET(reg, val,20, 22)
316 
317 /* field: CH11PA - These bit fields determine to which port channel 11 is assigned. */
318 #define TMS570_DMA_PAR1_CH11PA(val) BSP_FLD32(val,16, 18)
319 #define TMS570_DMA_PAR1_CH11PA_GET(reg) BSP_FLD32GET(reg,16, 18)
320 #define TMS570_DMA_PAR1_CH11PA_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
321 
322 /* field: CH12PA - These bit fields determine to which port channel 12 is assigned. */
323 #define TMS570_DMA_PAR1_CH12PA(val) BSP_FLD32(val,12, 14)
324 #define TMS570_DMA_PAR1_CH12PA_GET(reg) BSP_FLD32GET(reg,12, 14)
325 #define TMS570_DMA_PAR1_CH12PA_SET(reg,val) BSP_FLD32SET(reg, val,12, 14)
326 
327 /* field: CH13PA - These bit fields determine to which port channel 13 is assigned. */
328 #define TMS570_DMA_PAR1_CH13PA(val) BSP_FLD32(val,8, 10)
329 #define TMS570_DMA_PAR1_CH13PA_GET(reg) BSP_FLD32GET(reg,8, 10)
330 #define TMS570_DMA_PAR1_CH13PA_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
331 
332 /* field: CH14PA - These bit fields determine to which port channel 14 is assigned. */
333 #define TMS570_DMA_PAR1_CH14PA(val) BSP_FLD32(val,4, 6)
334 #define TMS570_DMA_PAR1_CH14PA_GET(reg) BSP_FLD32GET(reg,4, 6)
335 #define TMS570_DMA_PAR1_CH14PA_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
336 
337 /* field: CH15PA - These bit fields determine to which port channel 15 is assigned. */
338 #define TMS570_DMA_PAR1_CH15PA(val) BSP_FLD32(val,0, 2)
339 #define TMS570_DMA_PAR1_CH15PA_GET(reg) BSP_FLD32GET(reg,0, 2)
340 #define TMS570_DMA_PAR1_CH15PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
341 
342 
343 /*---------------------TMS570_DMA_FTCMAP---------------------*/
344 /* field: FTCAB - Frame transfer complete (FTC) interrupt to Group A or Group B. */
345 #define TMS570_DMA_FTCMAP_FTCAB(val) BSP_FLD32(val,0, 15)
346 #define TMS570_DMA_FTCMAP_FTCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
347 #define TMS570_DMA_FTCMAP_FTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
348 
349 
350 /*---------------------TMS570_DMA_LFSMAP---------------------*/
351 /* field: LFSAB - Last frame started (LFS) interrupt to Group A or Group B. */
352 #define TMS570_DMA_LFSMAP_LFSAB(val) BSP_FLD32(val,0, 15)
353 #define TMS570_DMA_LFSMAP_LFSAB_GET(reg) BSP_FLD32GET(reg,0, 15)
354 #define TMS570_DMA_LFSMAP_LFSAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
355 
356 
357 /*---------------------TMS570_DMA_HBCMAP---------------------*/
358 /* field: HBCAB - Half block complete (HBC) interrupt to Group A or Group B. */
359 #define TMS570_DMA_HBCMAP_HBCAB(val) BSP_FLD32(val,0, 15)
360 #define TMS570_DMA_HBCMAP_HBCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
361 #define TMS570_DMA_HBCMAP_HBCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
362 
363 
364 /*---------------------TMS570_DMA_BTCMAP---------------------*/
365 /* field: BTCAB - Block transfer complete (BTC) interrupt to Group A or Group B */
366 #define TMS570_DMA_BTCMAP_BTCAB(val) BSP_FLD32(val,0, 15)
367 #define TMS570_DMA_BTCMAP_BTCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
368 #define TMS570_DMA_BTCMAP_BTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
369 
370 
371 /*---------------------TMS570_DMA_BERMAP---------------------*/
372 /* field: BERAB - Bus error (BER) interrupt to Group A or Group B. */
373 #define TMS570_DMA_BERMAP_BERAB(val) BSP_FLD32(val,0, 15)
374 #define TMS570_DMA_BERMAP_BERAB_GET(reg) BSP_FLD32GET(reg,0, 15)
375 #define TMS570_DMA_BERMAP_BERAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
376 
377 
378 /*-------------------TMS570_DMA_FTCINTENAS-------------------*/
379 /* field: FTCINTENA - Frame transfer complete (FTC) interrupt enable. */
380 #define TMS570_DMA_FTCINTENAS_FTCINTENA(val) BSP_FLD32(val,0, 15)
381 #define TMS570_DMA_FTCINTENAS_FTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
382 #define TMS570_DMA_FTCINTENAS_FTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
383 
384 
385 /*-------------------TMS570_DMA_FTCINTENAR-------------------*/
386 /* field: FTCINTDIS - Frame transfer complete (FTC) interrupt disable. */
387 #define TMS570_DMA_FTCINTENAR_FTCINTDIS(val) BSP_FLD32(val,0, 15)
388 #define TMS570_DMA_FTCINTENAR_FTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
389 #define TMS570_DMA_FTCINTENAR_FTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
390 
391 
392 /*-------------------TMS570_DMA_LFSINTENAS-------------------*/
393 /* field: LFSINTENA - Last frame started (LFS) interrupt enable. */
394 #define TMS570_DMA_LFSINTENAS_LFSINTENA(val) BSP_FLD32(val,0, 15)
395 #define TMS570_DMA_LFSINTENAS_LFSINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
396 #define TMS570_DMA_LFSINTENAS_LFSINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
397 
398 
399 /*-------------------TMS570_DMA_LFSINTENAR-------------------*/
400 /* field: LFSINTDIS - Last frame started (LFS) interrupt disable. */
401 #define TMS570_DMA_LFSINTENAR_LFSINTDIS(val) BSP_FLD32(val,0, 15)
402 #define TMS570_DMA_LFSINTENAR_LFSINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
403 #define TMS570_DMA_LFSINTENAR_LFSINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
404 
405 
406 /*-------------------TMS570_DMA_HBCINTENAS-------------------*/
407 /* field: HBCINTENA - Half block complete (HBC) interrupt enable. */
408 #define TMS570_DMA_HBCINTENAS_HBCINTENA(val) BSP_FLD32(val,0, 15)
409 #define TMS570_DMA_HBCINTENAS_HBCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
410 #define TMS570_DMA_HBCINTENAS_HBCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
411 
412 
413 /*-------------------TMS570_DMA_HBCINTENAR-------------------*/
414 /* field: HBCINTDIS - Half block complete (HBC) interrupt disable. */
415 #define TMS570_DMA_HBCINTENAR_HBCINTDIS(val) BSP_FLD32(val,0, 15)
416 #define TMS570_DMA_HBCINTENAR_HBCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
417 #define TMS570_DMA_HBCINTENAR_HBCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
418 
419 
420 /*-------------------TMS570_DMA_BTCINTENAS-------------------*/
421 /* field: BTCINTENA - Block transfer complete (BTC) interrupt enable. */
422 #define TMS570_DMA_BTCINTENAS_BTCINTENA(val) BSP_FLD32(val,0, 15)
423 #define TMS570_DMA_BTCINTENAS_BTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
424 #define TMS570_DMA_BTCINTENAS_BTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
425 
426 
427 /*-------------------TMS570_DMA_BTCINTENAR-------------------*/
428 /* field: BTCINTDIS - Block transfer complete (BTC) interurpt disable. */
429 #define TMS570_DMA_BTCINTENAR_BTCINTDIS(val) BSP_FLD32(val,0, 15)
430 #define TMS570_DMA_BTCINTENAR_BTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
431 #define TMS570_DMA_BTCINTENAR_BTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
432 
433 
434 /*--------------------TMS570_DMA_GINTFLAG--------------------*/
435 /* field: GINT - Global interrupt flags. */
436 #define TMS570_DMA_GINTFLAG_GINT(val) BSP_FLD32(val,0, 15)
437 #define TMS570_DMA_GINTFLAG_GINT_GET(reg) BSP_FLD32GET(reg,0, 15)
438 #define TMS570_DMA_GINTFLAG_GINT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
439 
440 
441 /*---------------------TMS570_DMA_FTCFLAG---------------------*/
442 /* field: FTCI - Frame transfer complete (FTC) flags. */
443 #define TMS570_DMA_FTCFLAG_FTCI(val) BSP_FLD32(val,0, 15)
444 #define TMS570_DMA_FTCFLAG_FTCI_GET(reg) BSP_FLD32GET(reg,0, 15)
445 #define TMS570_DMA_FTCFLAG_FTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
446 
447 
448 /*---------------------TMS570_DMA_LFSFLAG---------------------*/
449 /* field: LFSI - Last frame started (LFS) flags. */
450 #define TMS570_DMA_LFSFLAG_LFSI(val) BSP_FLD32(val,0, 15)
451 #define TMS570_DMA_LFSFLAG_LFSI_GET(reg) BSP_FLD32GET(reg,0, 15)
452 #define TMS570_DMA_LFSFLAG_LFSI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
453 
454 
455 /*---------------------TMS570_DMA_HBCFLAG---------------------*/
456 /* field: HBCI - Half block transfer (HBC) complete flags. */
457 #define TMS570_DMA_HBCFLAG_HBCI(val) BSP_FLD32(val,0, 15)
458 #define TMS570_DMA_HBCFLAG_HBCI_GET(reg) BSP_FLD32GET(reg,0, 15)
459 #define TMS570_DMA_HBCFLAG_HBCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
460 
461 
462 /*---------------------TMS570_DMA_BTCFLAG---------------------*/
463 /* field: BTCI - Block transfer complete (BTC) flags. */
464 #define TMS570_DMA_BTCFLAG_BTCI(val) BSP_FLD32(val,0, 15)
465 #define TMS570_DMA_BTCFLAG_BTCI_GET(reg) BSP_FLD32GET(reg,0, 15)
466 #define TMS570_DMA_BTCFLAG_BTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
467 
468 
469 /*---------------------TMS570_DMA_BERFLAG---------------------*/
470 /* field: BERI - Bus error (BER) flags. */
471 #define TMS570_DMA_BERFLAG_BERI(val) BSP_FLD32(val,0, 15)
472 #define TMS570_DMA_BERFLAG_BERI_GET(reg) BSP_FLD32GET(reg,0, 15)
473 #define TMS570_DMA_BERFLAG_BERI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
474 
475 
476 /*-------------------TMS570_DMA_FTCAOFFSET-------------------*/
477 /* field: sbz - These bits should always be programmed as zero. */
478 #define TMS570_DMA_FTCAOFFSET_sbz(val) BSP_FLD32(val,6, 7)
479 #define TMS570_DMA_FTCAOFFSET_sbz_GET(reg) BSP_FLD32GET(reg,6, 7)
480 #define TMS570_DMA_FTCAOFFSET_sbz_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
481 
482 /* field: FTCA - Channel causing FTC interrupt Group A. */
483 #define TMS570_DMA_FTCAOFFSET_FTCA(val) BSP_FLD32(val,0, 5)
484 #define TMS570_DMA_FTCAOFFSET_FTCA_GET(reg) BSP_FLD32GET(reg,0, 5)
485 #define TMS570_DMA_FTCAOFFSET_FTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
486 
487 
488 /*-------------------TMS570_DMA_LFSAOFFSET-------------------*/
489 /* field: LFSA - Channel causing LFS interrupt Group A. */
490 #define TMS570_DMA_LFSAOFFSET_LFSA(val) BSP_FLD32(val,0, 5)
491 #define TMS570_DMA_LFSAOFFSET_LFSA_GET(reg) BSP_FLD32GET(reg,0, 5)
492 #define TMS570_DMA_LFSAOFFSET_LFSA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
493 
494 
495 /*-------------------TMS570_DMA_HBCAOFFSET-------------------*/
496 /* field: HBCA - Channel causing HBC interrupt Group A. */
497 #define TMS570_DMA_HBCAOFFSET_HBCA(val) BSP_FLD32(val,0, 5)
498 #define TMS570_DMA_HBCAOFFSET_HBCA_GET(reg) BSP_FLD32GET(reg,0, 5)
499 #define TMS570_DMA_HBCAOFFSET_HBCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
500 
501 
502 /*-------------------TMS570_DMA_BTCAOFFSET-------------------*/
503 /* field: BTCA - Channel causing BTC interrupt Group A. */
504 #define TMS570_DMA_BTCAOFFSET_BTCA(val) BSP_FLD32(val,0, 5)
505 #define TMS570_DMA_BTCAOFFSET_BTCA_GET(reg) BSP_FLD32GET(reg,0, 5)
506 #define TMS570_DMA_BTCAOFFSET_BTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
507 
508 
509 /*-------------------TMS570_DMA_BERAOFFSET-------------------*/
510 /* field: BERA - Channel causing BER interrupt Group A. */
511 #define TMS570_DMA_BERAOFFSET_BERA(val) BSP_FLD32(val,0, 5)
512 #define TMS570_DMA_BERAOFFSET_BERA_GET(reg) BSP_FLD32GET(reg,0, 5)
513 #define TMS570_DMA_BERAOFFSET_BERA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
514 
515 
516 /*-------------------TMS570_DMA_FTCBOFFSET-------------------*/
517 /* field: FTCB - Channel causing FTC interrupt Group B. */
518 #define TMS570_DMA_FTCBOFFSET_FTCB(val) BSP_FLD32(val,0, 5)
519 #define TMS570_DMA_FTCBOFFSET_FTCB_GET(reg) BSP_FLD32GET(reg,0, 5)
520 #define TMS570_DMA_FTCBOFFSET_FTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
521 
522 
523 /*-------------------TMS570_DMA_LFSBOFFSET-------------------*/
524 /* field: LFSB - Channel causing LFS interrupt Group B. */
525 #define TMS570_DMA_LFSBOFFSET_LFSB(val) BSP_FLD32(val,0, 5)
526 #define TMS570_DMA_LFSBOFFSET_LFSB_GET(reg) BSP_FLD32GET(reg,0, 5)
527 #define TMS570_DMA_LFSBOFFSET_LFSB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
528 
529 
530 /*-------------------TMS570_DMA_HBCBOFFSET-------------------*/
531 /* field: HBCB - Channel causing HBC interrupt Group B. */
532 #define TMS570_DMA_HBCBOFFSET_HBCB(val) BSP_FLD32(val,0, 5)
533 #define TMS570_DMA_HBCBOFFSET_HBCB_GET(reg) BSP_FLD32GET(reg,0, 5)
534 #define TMS570_DMA_HBCBOFFSET_HBCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
535 
536 
537 /*-------------------TMS570_DMA_BTCBOFFSET-------------------*/
538 /* field: BTCB - interrupt for Group B if the corresponding interrupt enable is set. */
539 #define TMS570_DMA_BTCBOFFSET_BTCB(val) BSP_FLD32(val,0, 5)
540 #define TMS570_DMA_BTCBOFFSET_BTCB_GET(reg) BSP_FLD32GET(reg,0, 5)
541 #define TMS570_DMA_BTCBOFFSET_BTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
542 
543 
544 /*-------------------TMS570_DMA_BERBOFFSET-------------------*/
545 /* field: BERB - Channel causing BER interrupt Group B. */
546 #define TMS570_DMA_BERBOFFSET_BERB(val) BSP_FLD32(val,0, 5)
547 #define TMS570_DMA_BERBOFFSET_BERB_GET(reg) BSP_FLD32GET(reg,0, 5)
548 #define TMS570_DMA_BERBOFFSET_BERB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
549 
550 
551 /*----------------------TMS570_DMA_PTCRL----------------------*/
552 /* field: PENDB - Transfers pending for Port B. This flag determines if transfers are ongoing on port B. */
553 #define TMS570_DMA_PTCRL_PENDB BSP_BIT32(24)
554 
555 /* field: BYB - Bypass FIFO B. */
556 #define TMS570_DMA_PTCRL_BYB BSP_BIT32(18)
557 
558 /* field: PSFRHQPB - Priority scheme fix or rotate for high priority queue of Port B. */
559 #define TMS570_DMA_PTCRL_PSFRHQPB BSP_BIT32(17)
560 
561 /* field: PSFRLQPB - Priority scheme fix or rotate for low priority queue of Port B. */
562 #define TMS570_DMA_PTCRL_PSFRLQPB BSP_BIT32(16)
563 
564 
565 /*---------------------TMS570_DMA_RTCTRL---------------------*/
566 /* field: RTC - RAM Test Control. */
567 #define TMS570_DMA_RTCTRL_RTC BSP_BIT32(0)
568 
569 
570 /*----------------------TMS570_DMA_DCTRL----------------------*/
571 /* field: CHNUM - Channel Number. */
572 #define TMS570_DMA_DCTRL_CHNUM(val) BSP_FLD32(val,24, 28)
573 #define TMS570_DMA_DCTRL_CHNUM_GET(reg) BSP_FLD32GET(reg,24, 28)
574 #define TMS570_DMA_DCTRL_CHNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
575 
576 /* field: DMADBGS - DMA debug status. */
577 #define TMS570_DMA_DCTRL_DMADBGS BSP_BIT32(16)
578 
579 /* field: DBGEN - Debug Enable. */
580 #define TMS570_DMA_DCTRL_DBGEN BSP_BIT32(0)
581 
582 
583 /*-----------------------TMS570_DMA_WPR-----------------------*/
584 /* field: WP - Watch point. */
585 /* Whole 32 bits */
586 
587 /*-----------------------TMS570_DMA_WMR-----------------------*/
588 /* field: WM - Watch mask. */
589 /* Whole 32 bits */
590 
591 /*--------------------TMS570_DMA_PBACSADDR--------------------*/
592 /* field: PBACSA - Port B Active Channel Source Address. */
593 /* Whole 32 bits */
594 
595 /*--------------------TMS570_DMA_PBACDADDR--------------------*/
596 /* field: PBACDA - address of the active channel as broadcasted in Section 16.3.1.3 for Port B. */
597 /* Whole 32 bits */
598 
599 /*---------------------TMS570_DMA_PBACTC---------------------*/
600 /* field: PBFTCOUNT - Port B active channel frame count. */
601 #define TMS570_DMA_PBACTC_PBFTCOUNT(val) BSP_FLD32(val,16, 28)
602 #define TMS570_DMA_PBACTC_PBFTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 28)
603 #define TMS570_DMA_PBACTC_PBFTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 28)
604 
605 /* field: PBETCOUNT - Port B active channel element count. */
606 #define TMS570_DMA_PBACTC_PBETCOUNT(val) BSP_FLD32(val,0, 12)
607 #define TMS570_DMA_PBACTC_PBETCOUNT_GET(reg) BSP_FLD32GET(reg,0, 12)
608 #define TMS570_DMA_PBACTC_PBETCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
609 
610 
611 /*---------------------TMS570_DMA_DMAPCR---------------------*/
612 /* field: ERRA - Error action. */
613 #define TMS570_DMA_DMAPCR_ERRA BSP_BIT32(16)
614 
615 /* field: TEST - When this bit is set, the parity bits are memory mapped to make them accessible by the CPU. */
616 #define TMS570_DMA_DMAPCR_TEST BSP_BIT32(8)
617 
618 /* field: PARITY_ENA - Parity error detection enable. */
619 #define TMS570_DMA_DMAPCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
620 #define TMS570_DMA_DMAPCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
621 #define TMS570_DMA_DMAPCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
622 
623 
624 /*---------------------TMS570_DMA_DMAPAR---------------------*/
625 /* field: EDFLAG - Parity Error Detection Flag. */
626 #define TMS570_DMA_DMAPAR_EDFLAG BSP_BIT32(24)
627 
628 /* field: ERRORADDRESS - Error address. These bits hold the address of the first parity error generated in the RAM. */
629 #define TMS570_DMA_DMAPAR_ERRORADDRESS(val) BSP_FLD32(val,0, 11)
630 #define TMS570_DMA_DMAPAR_ERRORADDRESS_GET(reg) BSP_FLD32GET(reg,0, 11)
631 #define TMS570_DMA_DMAPAR_ERRORADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
632 
633 
634 /*--------------------TMS570_DMA_DMAMPCTRL--------------------*/
635 /* field: INT3AB - Interrupt assignment of region 3 to Group A or Group B. */
636 #define TMS570_DMA_DMAMPCTRL_INT3AB BSP_BIT32(28)
637 
638 /* field: INT3ENA - Interrupt enable of region 3. */
639 #define TMS570_DMA_DMAMPCTRL_INT3ENA BSP_BIT32(27)
640 
641 /* field: REG3AP - Region 3 access permission. */
642 #define TMS570_DMA_DMAMPCTRL_REG3AP(val) BSP_FLD32(val,25, 26)
643 #define TMS570_DMA_DMAMPCTRL_REG3AP_GET(reg) BSP_FLD32GET(reg,25, 26)
644 #define TMS570_DMA_DMAMPCTRL_REG3AP_SET(reg,val) BSP_FLD32SET(reg, val,25, 26)
645 
646 /* field: REG3ENA - Region 3 enable. */
647 #define TMS570_DMA_DMAMPCTRL_REG3ENA BSP_BIT32(24)
648 
649 /* field: INT2AB - Interrupt assignment of region 2 to Group A or Group B. */
650 #define TMS570_DMA_DMAMPCTRL_INT2AB BSP_BIT32(20)
651 
652 /* field: INT2ENA - Interrupt enable of region 2. */
653 #define TMS570_DMA_DMAMPCTRL_INT2ENA BSP_BIT32(19)
654 
655 /* field: REG2AP - Region 2 access permission. These bits determine the access permission for region 2. */
656 #define TMS570_DMA_DMAMPCTRL_REG2AP(val) BSP_FLD32(val,17, 18)
657 #define TMS570_DMA_DMAMPCTRL_REG2AP_GET(reg) BSP_FLD32GET(reg,17, 18)
658 #define TMS570_DMA_DMAMPCTRL_REG2AP_SET(reg,val) BSP_FLD32SET(reg, val,17, 18)
659 
660 /* field: REG2ENA - Region 2 enable. */
661 #define TMS570_DMA_DMAMPCTRL_REG2ENA BSP_BIT32(16)
662 
663 /* field: INT1AB - Interrupt assignment of region 1 to Group A or Group B. */
664 #define TMS570_DMA_DMAMPCTRL_INT1AB BSP_BIT32(12)
665 
666 /* field: INT1ENA - Interrupt enable of region 1. */
667 #define TMS570_DMA_DMAMPCTRL_INT1ENA BSP_BIT32(11)
668 
669 /* field: REG1AP - Region 1 access permission. */
670 #define TMS570_DMA_DMAMPCTRL_REG1AP(val) BSP_FLD32(val,9, 10)
671 #define TMS570_DMA_DMAMPCTRL_REG1AP_GET(reg) BSP_FLD32GET(reg,9, 10)
672 #define TMS570_DMA_DMAMPCTRL_REG1AP_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
673 
674 /* field: REG1ENA - Region 1 enable. */
675 #define TMS570_DMA_DMAMPCTRL_REG1ENA BSP_BIT32(8)
676 
677 /* field: INT0AB - Interrupt assignment of region 0 to Group A or Group B. */
678 #define TMS570_DMA_DMAMPCTRL_INT0AB BSP_BIT32(4)
679 
680 /* field: INT0ENA - Interrupt enable of region 0. */
681 #define TMS570_DMA_DMAMPCTRL_INT0ENA BSP_BIT32(3)
682 
683 /* field: REG0AP - Region 0 access permission. These bits determine the access permission for region 0. */
684 #define TMS570_DMA_DMAMPCTRL_REG0AP(val) BSP_FLD32(val,1, 2)
685 #define TMS570_DMA_DMAMPCTRL_REG0AP_GET(reg) BSP_FLD32GET(reg,1, 2)
686 #define TMS570_DMA_DMAMPCTRL_REG0AP_SET(reg,val) BSP_FLD32SET(reg, val,1, 2)
687 
688 /* field: REG0ENA - Region 0 enable. */
689 #define TMS570_DMA_DMAMPCTRL_REG0ENA BSP_BIT32(0)
690 
691 
692 /*---------------------TMS570_DMA_DMAMPST---------------------*/
693 /* field: REG3FT - Region 3 fault. */
694 #define TMS570_DMA_DMAMPST_REG3FT BSP_BIT32(24)
695 
696 /* field: REG2FT - Region 2 fault. */
697 #define TMS570_DMA_DMAMPST_REG2FT BSP_BIT32(16)
698 
699 /* field: REG1FT - Region 1 fault. */
700 #define TMS570_DMA_DMAMPST_REG1FT BSP_BIT32(8)
701 
702 /* field: REG0FT - Region 0 fault. */
703 #define TMS570_DMA_DMAMPST_REG0FT BSP_BIT32(0)
704 
705 
706 /*--------------------TMS570_DMA_DMAMPROS--------------------*/
707 /* field: STARTADDRESS - Start Address defines the address at which the region begins. */
708 /* Whole 32 bits */
709 
710 
711 #endif /* LIBBSP_ARM_TMS570_DMA */
tms570_dma_t
Definition: reg_dma.h:49
utility.h
Utility macros.
tms570_memory_prot_t
Definition: reg_dma.h:44
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