RTEMS  5.1
reg_adc.h
1 /* The header file is generated by make_header.py from ADC.json */
2 /* Current script's version can be found at: */
3 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4 
5 /*
6  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7  *
8  * Czech Technical University in Prague
9  * Zikova 1903/4
10  * 166 36 Praha 6
11  * Czech Republic
12  *
13  * All rights reserved.
14  *
15  * Redistribution and use in source and binary forms, with or without
16  * modification, are permitted provided that the following conditions are met:
17  *
18  * 1. Redistributions of source code must retain the above copyright notice, this
19  * list of conditions and the following disclaimer.
20  * 2. Redistributions in binary form must reproduce the above copyright notice,
21  * this list of conditions and the following disclaimer in the documentation
22  * and/or other materials provided with the distribution.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  *
35  * The views and conclusions contained in the software and documentation are those
36  * of the authors and should not be interpreted as representing official policies,
37  * either expressed or implied, of the FreeBSD Project.
38 */
39 #ifndef LIBBSP_ARM_TMS570_ADC
40 #define LIBBSP_ARM_TMS570_ADC
41 
42 #include <bsp/utility.h>
43 
44 typedef struct{
45  uint32_t BUF0; /*Group 0-2 result buffer 0 register*/
46  uint32_t BUF1; /*Group 0-2 result buffer 1 register*/
47  uint32_t BUF2; /*Group 0-2 result buffer 2 register*/
48  uint32_t BUF3; /*Group 0-2 result buffer 3 register*/
49  uint32_t BUF4; /*Group 0-2 result buffer 4 register*/
50  uint32_t BUF5; /*Group 0-2 result buffer 5 register*/
51  uint32_t BUF6; /*Group 0-2 result buffer 6 register*/
52  uint32_t BUF7; /*Group 0-2 result buffer 7 register*/
53 } tms570_gxbuf_t;
54 
55 typedef struct{
56  uint32_t RSTCR; /*ADC Reset Control Register*/
57  uint32_t OPMODECR; /*ADC Operating Mode Control Register*/
58  uint32_t CLOCKCR; /*ADC Clock Control Register*/
59  uint32_t CALCR; /*ADC Calibration Mode Control Register*/
60  uint32_t GxMODECR[3]; /*ADC Event Group Operating Mode Control Register*/
61  uint32_t EVSRC; /*ADC Trigger Source Select Register*/
62  uint32_t G1SRC; /*ADC Group1 Trigger Source Select Register*/
63  uint32_t G2SRC; /*ADC Group2 Trigger Source Select Register*/
64  uint32_t GxINTENA[3]; /*ADC Event Interrupt Enable Control Register*/
65  uint32_t GxINTFLG[3]; /*ADC Event Group Interrupt Flag Register*/
66  uint32_t GxINTCR[3]; /*ADC Event Group Threshold Interrupt Control Register*/
67  uint32_t EVDMACR; /*ADC Event Group DMA Control Register*/
68  uint32_t G1DMACR; /*ADC Group1 DMA Control Register*/
69  uint32_t G2DMACR; /*ADC Group2 DMA Control Register*/
70  uint32_t BNDCR; /*ADC Results Memory Configuration Register*/
71  uint32_t BNDEND; /*ADC Results Memory Size Configuration Register*/
72  uint32_t EVSAMP; /*ADC Event Group Sampling Time Configuration Register*/
73  uint32_t G1SAMP; /*ADC Group1 Sampling Time Configuration Register()*/
74  uint32_t G2SAMP; /*ADC Group2 Sampling Time Configuration Register*/
75  uint32_t EVSR; /*ADC Event Group Status Register*/
76  uint32_t G1SR; /*ADC Group1 Status Register*/
77  uint32_t G2SR; /*ADC Group2 Status Register*/
78  uint32_t GxSEL[3]; /*ADC Event Group Channel Select Register*/
79  uint32_t CALR; /*ADC Calibration and Error Offset Correction Register*/
80  uint32_t SMSTATE; /*ADC State Machine Status Register*/
81  uint32_t LASTCONV; /*ADC Channel Last Conversion Value Register*/
82  tms570_gxbuf_t GxBUF[3]; /*ADC Event Group Results Emulation FIFO Register*/
83  uint32_t EVEMUBUFFER; /*ADC Event Group Results Emulation FIFO Register*/
84  uint32_t G1EMUBUFFER; /*ADC Group1 Results Emulation FIFO Register*/
85  uint32_t G2EMUBUFFER; /*ADC Group2 Results Emulation FIFO Register*/
86  uint32_t EVTDIR; /*ADC ADEVT Pin Direction Control Register*/
87  uint32_t EVTOUT; /*ADC ADEVT Pin Output Value Control Register*/
88  uint32_t EVTIN; /*ADC ADEVT Pin Input Value Register*/
89  uint32_t EVTSET; /*ADC ADEVT Pin Set Register*/
90  uint32_t EVTCLR; /*ADC ADEVT Pin Clear Register*/
91  uint32_t EVTPDR; /*ADC ADEVT Pin Open Drain Enable Register*/
92  uint32_t EVTPDIS; /*ADC ADEVT Pin Pull Control Disable Register*/
93  uint32_t EVTPSEL; /*ADC ADEVT Pin Pull Control Select Register*/
94  uint32_t EVSAMPDISEN; /*ADC Event Group Sample Cap Discharge Control Register*/
95  uint32_t G1SAMPDISEN; /*ADC Group1 Sample Cap Discharge Control Register*/
96  uint32_t G2SAMPDISEN; /*ADC Group2 Sample Cap Discharge Control Register*/
97  uint32_t MAGINTCR1; /*ADC Magnitude Compare Interrupt Control Register 2*/
98  uint32_t MAGINT1MASK; /*ADC Magnitude Compare Mask Register 0*/
99  uint32_t MAGINTCR2; /*ADC Magnitude Compare Interrupt Control Register 2*/
100  uint32_t MAGINT2MASK; /*ADC Magnitude Compare Mask Register 0*/
101  uint32_t MAGINTCR3; /*ADC Magnitude Compare Interrupt Control Register 2*/
102  uint32_t MAGINT3MASK; /*ADC Magnitude Compare Mask Register 0*/
103  uint8_t reserved1 [24];
104  uint32_t MAGTHRINTENASET; /*ADC Magnitude Compare Interrupt Enable Set Register*/
105  uint32_t MAGTHRINTENACLR; /*ADC Magnitude Compare Interrupt Enable Clear Register*/
106  uint32_t MAGTHRINTFLG; /*ADC Magnitude Compare Interrupt Flag Register*/
107  uint32_t MAGTHRINTOFFSET; /*ADC Magnitude Compare Interrupt Offset Register*/
108  uint32_t GxFIFORESETCR[3]; /*ADC Event Group FIFO Reset Control Register*/
109  uint32_t EVRAMWRADDR; /*ADC Event Group RAM Write Address Register*/
110  uint32_t G1RAMWRADDR; /*ADC Group1 RAM Write Address Register*/
111  uint32_t G2RAMWRADDR; /*ADC Group2 RAM Write Address Register*/
112  uint32_t PARCR; /*ADC Parity Control Register*/
113  uint32_t PARADDR; /*ADC Parity Error Address Register*/
114  uint32_t PWRUPDLYCTRL; /*ADC Power-Up Delay Control Register*/
115 } tms570_adc_t;
116 
117 
118 /*----------------------TMS570_ADC_BUFx----------------------*/
119 /* field: G2_EMPTY_10bit_mode - Group2 FIFO Empty. */
120 #define TMS570_ADC_BUFx_G2_EMPTY_10bit_mode BSP_BIT32(15)
121 
122 /* field: G2_CHID_10bit_mode - Group2 Channel Id. */
123 #define TMS570_ADC_BUFx_G2_CHID_10bit_mode(val) BSP_FLD32(val,10, 14)
124 #define TMS570_ADC_BUFx_G2_CHID_10bit_mode_GET(reg) BSP_FLD32GET(reg,10, 14)
125 #define TMS570_ADC_BUFx_G2_CHID_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,10, 14)
126 
127 /* field: G2_DR_10bit_mode - Group2 Digital Conversion Result. */
128 #define TMS570_ADC_BUFx_G2_DR_10bit_mode(val) BSP_FLD32(val,0, 9)
129 #define TMS570_ADC_BUFx_G2_DR_10bit_mode_GET(reg) BSP_FLD32GET(reg,0, 9)
130 #define TMS570_ADC_BUFx_G2_DR_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
131 
132 /* field: G2_EMPTY_12bit_mode - Group2 FIFO Empty. */
133 #define TMS570_ADC_BUFx_G2_EMPTY_12bit_mode BSP_BIT32(31)
134 
135 /* field: G2_CHID_12bit_mode - Group2 Channel Id. */
136 #define TMS570_ADC_BUFx_G2_CHID_12bit_mode(val) BSP_FLD32(val,16, 20)
137 #define TMS570_ADC_BUFx_G2_CHID_12bit_mode_GET(reg) BSP_FLD32GET(reg,16, 20)
138 #define TMS570_ADC_BUFx_G2_CHID_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
139 
140 /* field: G2_DR_12bit_mode - Group2 Digital Conversion Result. */
141 #define TMS570_ADC_BUFx_G2_DR_12bit_mode(val) BSP_FLD32(val,0, 11)
142 #define TMS570_ADC_BUFx_G2_DR_12bit_mode_GET(reg) BSP_FLD32GET(reg,0, 11)
143 #define TMS570_ADC_BUFx_G2_DR_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
144 
145 
146 /*----------------------TMS570_ADC_RSTCR----------------------*/
147 /* field: RESET - This bit is used to reset the ADC internal state machines and control/status registers. */
148 #define TMS570_ADC_RSTCR_RESET BSP_BIT32(0)
149 
150 
151 /*--------------------TMS570_ADC_OPMODECR--------------------*/
152 /* field: 10_12_BIT - This bit controls the resolution of the ADC core. */
153 #define TMS570_ADC_OPMODECR_10_12_BIT BSP_BIT32(31)
154 
155 
156 /*---------------------TMS570_ADC_CLOCKCR---------------------*/
157 /* field: PS - ADC Clock Prescaler. These bits define the prescaler value for the ADC core clock (ADCLK). */
158 #define TMS570_ADC_CLOCKCR_PS(val) BSP_FLD32(val,0, 4)
159 #define TMS570_ADC_CLOCKCR_PS_GET(reg) BSP_FLD32GET(reg,0, 4)
160 #define TMS570_ADC_CLOCKCR_PS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
161 
162 
163 /*----------------------TMS570_ADC_CALCR----------------------*/
164 /* field: SELF_TEST - ADC Self Test Enable. */
165 #define TMS570_ADC_CALCR_SELF_TEST BSP_BIT32(24)
166 
167 /* field: CAL_ST - ADC Calibration Conversion Start. */
168 #define TMS570_ADC_CALCR_CAL_ST BSP_BIT32(16)
169 
170 /* field: BRIDGE_EN - Bridge Enable. */
171 #define TMS570_ADC_CALCR_BRIDGE_EN BSP_BIT32(9)
172 
173 /* field: HILO - ADC Self Test mode and Calibration Mode Reference Source Selection. */
174 #define TMS570_ADC_CALCR_HILO BSP_BIT32(8)
175 
176 /* field: CAL_EN - ADC Calibration Enable. */
177 #define TMS570_ADC_CALCR_CAL_EN BSP_BIT32(0)
178 
179 
180 /*--------------------TMS570_ADC_GxMODECR--------------------*/
181 /* field: No_Reset_on_ChnSel - No Event Group Results Memory Reset on New Channel Select. */
182 #define TMS570_ADC_GxMODECR_No_Reset_on_ChnSel BSP_BIT32(16)
183 
184 /* field: EV_DATA_FMT - Event Group Read Data Format. */
185 #define TMS570_ADC_GxMODECR_EV_DATA_FMT(val) BSP_FLD32(val,8, 9)
186 #define TMS570_ADC_GxMODECR_EV_DATA_FMT_GET(reg) BSP_FLD32GET(reg,8, 9)
187 #define TMS570_ADC_GxMODECR_EV_DATA_FMT_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
188 
189 
190 /*----------------------TMS570_ADC_EVSRC----------------------*/
191 /* field: EV_EDG_BOTH - rising and falling edge detected on the selected trigger source. */
192 #define TMS570_ADC_EVSRC_EV_EDG_BOTH BSP_BIT32(4)
193 
194 /* field: EV_EDG_SEL - Event Group Trigger Edge Polarity Select. */
195 #define TMS570_ADC_EVSRC_EV_EDG_SEL BSP_BIT32(3)
196 
197 /* field: EV_SRC - Event Group Trigger Source. */
198 #define TMS570_ADC_EVSRC_EV_SRC(val) BSP_FLD32(val,0, 2)
199 #define TMS570_ADC_EVSRC_EV_SRC_GET(reg) BSP_FLD32GET(reg,0, 2)
200 #define TMS570_ADC_EVSRC_EV_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
201 
202 
203 /*----------------------TMS570_ADC_G1SRC----------------------*/
204 /* field: GI_EDG_BOTH - Group1 Trigger Edge Polarity Select. */
205 #define TMS570_ADC_G1SRC_GI_EDG_BOTH BSP_BIT32(4)
206 
207 /* field: G1_EDG_SEL - Group1 Trigger Edge Polarity Select. */
208 #define TMS570_ADC_G1SRC_G1_EDG_SEL BSP_BIT32(3)
209 
210 /* field: G1_SRC - Group1 Trigger Source. */
211 #define TMS570_ADC_G1SRC_G1_SRC(val) BSP_FLD32(val,0, 2)
212 #define TMS570_ADC_G1SRC_G1_SRC_GET(reg) BSP_FLD32GET(reg,0, 2)
213 #define TMS570_ADC_G1SRC_G1_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
214 
215 
216 /*----------------------TMS570_ADC_G2SRC----------------------*/
217 /* field: G2_EDG_BOTH - Group2 Trigger Edge Polarity Select. */
218 #define TMS570_ADC_G2SRC_G2_EDG_BOTH BSP_BIT32(4)
219 
220 /* field: G2_EDG_SEL - Group2 Trigger Edge Polarity Select. */
221 #define TMS570_ADC_G2SRC_G2_EDG_SEL BSP_BIT32(3)
222 
223 /* field: G2_SRC - Group2 Trigger Source. */
224 #define TMS570_ADC_G2SRC_G2_SRC(val) BSP_FLD32(val,0, 2)
225 #define TMS570_ADC_G2SRC_G2_SRC_GET(reg) BSP_FLD32GET(reg,0, 2)
226 #define TMS570_ADC_G2SRC_G2_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
227 
228 
229 /*--------------------TMS570_ADC_GxINTENA--------------------*/
230 /* field: EV_END_INT_EN - Event Group Conversion End Interrupt Enable. Please refer to Section 19.5. */
231 #define TMS570_ADC_GxINTENA_EV_END_INT_EN BSP_BIT32(3)
232 
233 /* field: EV_OVR_INT_EN - write a new conversion result to the Event Group results memory which is already full. */
234 #define TMS570_ADC_GxINTENA_EV_OVR_INT_EN BSP_BIT32(1)
235 
236 /* field: EV_THR_INT_EN - Event Group Threshold Interrupt Enable. */
237 #define TMS570_ADC_GxINTENA_EV_THR_INT_EN BSP_BIT32(0)
238 
239 
240 /*--------------------TMS570_ADC_GxINTFLG--------------------*/
241 /* field: EV_END - Event Group Conversion End. */
242 #define TMS570_ADC_GxINTFLG_EV_END BSP_BIT32(3)
243 
244 /* field: EV_MEM_EMPTY - Event Group Results Memory Empty. This is a read-only bit; writes have no effect. It is not asource of an interrupt from the ADC module. */
245 #define TMS570_ADC_GxINTFLG_EV_MEM_EMPTY BSP_BIT32(2)
246 
247 /* field: EV_MEM_OVERRUN - Event Group Memory Overrun. This is a read-only bit; writes have no effect. */
248 #define TMS570_ADC_GxINTFLG_EV_MEM_OVERRUN BSP_BIT32(1)
249 
250 /* field: EV_THR_INT_FLG - Event Group Threshold Interrupt Flag. */
251 #define TMS570_ADC_GxINTFLG_EV_THR_INT_FLG BSP_BIT32(0)
252 
253 
254 /*---------------------TMS570_ADC_GxINTCR---------------------*/
255 /* field: Sign_Extension - These bits always read the same as the bit 8 of this register. */
256 #define TMS570_ADC_GxINTCR_Sign_Extension(val) BSP_FLD32(val,9, 15)
257 #define TMS570_ADC_GxINTCR_Sign_Extension_GET(reg) BSP_FLD32GET(reg,9, 15)
258 #define TMS570_ADC_GxINTCR_Sign_Extension_SET(reg,val) BSP_FLD32SET(reg, val,9, 15)
259 
260 /* field: EV_THR - Event Group Threshold Counter. */
261 #define TMS570_ADC_GxINTCR_EV_THR(val) BSP_FLD32(val,0, 8)
262 #define TMS570_ADC_GxINTCR_EV_THR_GET(reg) BSP_FLD32GET(reg,0, 8)
263 #define TMS570_ADC_GxINTCR_EV_THR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
264 
265 
266 /*---------------------TMS570_ADC_EVDMACR---------------------*/
267 /* field: EV_BLOCKS - Number of Event Group Result buffers to be transferred using DMA if the ADC module is */
268 #define TMS570_ADC_EVDMACR_EV_BLOCKS(val) BSP_FLD32(val,16, 24)
269 #define TMS570_ADC_EVDMACR_EV_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
270 #define TMS570_ADC_EVDMACR_EV_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
271 
272 /* field: DMA_EV_END - Event Group Conversion End DMA Transfer Enable. */
273 #define TMS570_ADC_EVDMACR_DMA_EV_END BSP_BIT32(3)
274 
275 /* field: EV_BLK_XFER - Event Group Block DMA Transfer Enable. */
276 #define TMS570_ADC_EVDMACR_EV_BLK_XFER BSP_BIT32(2)
277 
278 /* field: EV_DMA_EN - Event Group DMA Transfer Enable. */
279 #define TMS570_ADC_EVDMACR_EV_DMA_EN BSP_BIT32(0)
280 
281 
282 /*---------------------TMS570_ADC_G1DMACR---------------------*/
283 /* field: G1_BLOCKS - Number of Group1 Result buffers to be transferred using DMA if the ADC module is configured */
284 #define TMS570_ADC_G1DMACR_G1_BLOCKS(val) BSP_FLD32(val,16, 24)
285 #define TMS570_ADC_G1DMACR_G1_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
286 #define TMS570_ADC_G1DMACR_G1_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
287 
288 /* field: DMA_G1_END - Group1 Conversion End DMA Transfer Enable. */
289 #define TMS570_ADC_G1DMACR_DMA_G1_END BSP_BIT32(3)
290 
291 /* field: G1_BLK_XFER - Group1 Block DMA Transfer Enable. */
292 #define TMS570_ADC_G1DMACR_G1_BLK_XFER BSP_BIT32(2)
293 
294 /* field: G1_DMA_EN - Group1 DMA Transfer Enable. */
295 #define TMS570_ADC_G1DMACR_G1_DMA_EN BSP_BIT32(0)
296 
297 
298 /*---------------------TMS570_ADC_G2DMACR---------------------*/
299 /* field: G2_BLOCKS - Number of Group2 Result buffers to be transferred using DMA if the ADC module is configured */
300 #define TMS570_ADC_G2DMACR_G2_BLOCKS(val) BSP_FLD32(val,16, 24)
301 #define TMS570_ADC_G2DMACR_G2_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
302 #define TMS570_ADC_G2DMACR_G2_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
303 
304 /* field: DMA_G2_END - Group2 Conversion End DMA Transfer Enable. */
305 #define TMS570_ADC_G2DMACR_DMA_G2_END BSP_BIT32(3)
306 
307 /* field: G2_BLK_XFER - Group2 Block DMA Transfer Enable. */
308 #define TMS570_ADC_G2DMACR_G2_BLK_XFER BSP_BIT32(2)
309 
310 /* field: G2_DMA_EN - Group2 DMA Transfer Enable. */
311 #define TMS570_ADC_G2DMACR_G2_DMA_EN BSP_BIT32(0)
312 
313 
314 /*----------------------TMS570_ADC_BNDCR----------------------*/
315 /* field: BNDA - Buffer Boundary A. */
316 #define TMS570_ADC_BNDCR_BNDA(val) BSP_FLD32(val,16, 24)
317 #define TMS570_ADC_BNDCR_BNDA_GET(reg) BSP_FLD32GET(reg,16, 24)
318 #define TMS570_ADC_BNDCR_BNDA_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
319 
320 /* field: BNDB - Buffer Boundary B. */
321 #define TMS570_ADC_BNDCR_BNDB(val) BSP_FLD32(val,0, 8)
322 #define TMS570_ADC_BNDCR_BNDB_GET(reg) BSP_FLD32GET(reg,0, 8)
323 #define TMS570_ADC_BNDCR_BNDB_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
324 
325 
326 /*---------------------TMS570_ADC_BNDEND---------------------*/
327 /* field: BUF_INIT_ACTIVE - ADC Results Memory Auto-initialization Status. */
328 #define TMS570_ADC_BNDEND_BUF_INIT_ACTIVE BSP_BIT32(16)
329 
330 /* field: BNDEND - Buffer Boundary End. */
331 #define TMS570_ADC_BNDEND_BNDEND(val) BSP_FLD32(val,0, 2)
332 #define TMS570_ADC_BNDEND_BNDEND_GET(reg) BSP_FLD32GET(reg,0, 2)
333 #define TMS570_ADC_BNDEND_BNDEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
334 
335 
336 /*---------------------TMS570_ADC_EVSAMP---------------------*/
337 /* field: EV_ACQ - Event Group Acquisition Time. */
338 #define TMS570_ADC_EVSAMP_EV_ACQ(val) BSP_FLD32(val,0, 11)
339 #define TMS570_ADC_EVSAMP_EV_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
340 #define TMS570_ADC_EVSAMP_EV_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
341 
342 
343 /*---------------------TMS570_ADC_G1SAMP---------------------*/
344 /* field: G1_ACQ - Group1 Acquisition Time. These bits define the sampling window (SW) for the Group1 conversions. */
345 #define TMS570_ADC_G1SAMP_G1_ACQ(val) BSP_FLD32(val,0, 11)
346 #define TMS570_ADC_G1SAMP_G1_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
347 #define TMS570_ADC_G1SAMP_G1_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
348 
349 
350 /*---------------------TMS570_ADC_G2SAMP---------------------*/
351 /* field: G2_ACQ - Group2 Acquisition Time. These bits define the sampling window (SW) for the Group2 conversions. */
352 #define TMS570_ADC_G2SAMP_G2_ACQ(val) BSP_FLD32(val,0, 11)
353 #define TMS570_ADC_G2SAMP_G2_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
354 #define TMS570_ADC_G2SAMP_G2_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
355 
356 
357 /*----------------------TMS570_ADC_EVSR----------------------*/
358 /* field: EV_MEM_EMPTY - Event Group Results Memory Empty. */
359 #define TMS570_ADC_EVSR_EV_MEM_EMPTY BSP_BIT32(3)
360 
361 /* field: EV_BUSY - Event Group Conversion Busy. */
362 #define TMS570_ADC_EVSR_EV_BUSY BSP_BIT32(2)
363 
364 /* field: EV_STOP - Event Group Conversion Stopped. */
365 #define TMS570_ADC_EVSR_EV_STOP BSP_BIT32(1)
366 
367 /* field: EV_END - Event Group Conversions Ended. */
368 #define TMS570_ADC_EVSR_EV_END BSP_BIT32(0)
369 
370 
371 /*----------------------TMS570_ADC_G1SR----------------------*/
372 /* field: G1_MEM_EMPTY - Group1 Results Memory Empty. */
373 #define TMS570_ADC_G1SR_G1_MEM_EMPTY BSP_BIT32(3)
374 
375 /* field: G1_BUSY - Group1 Conversion Busy. */
376 #define TMS570_ADC_G1SR_G1_BUSY BSP_BIT32(2)
377 
378 /* field: G1_STOP - Group1 Conversion Stopped. */
379 #define TMS570_ADC_G1SR_G1_STOP BSP_BIT32(1)
380 
381 /* field: G1_END - Group1 Conversions Ended. */
382 #define TMS570_ADC_G1SR_G1_END BSP_BIT32(0)
383 
384 
385 /*----------------------TMS570_ADC_G2SR----------------------*/
386 /* field: G2_MEM_EMPTY - Group2 Results Memory Empty. */
387 #define TMS570_ADC_G2SR_G2_MEM_EMPTY BSP_BIT32(3)
388 
389 /* field: G2_BUSY - Group2 Conversion Busy. */
390 #define TMS570_ADC_G2SR_G2_BUSY BSP_BIT32(2)
391 
392 /* field: G2_STOP - Group2 Conversion Stopped. */
393 #define TMS570_ADC_G2SR_G2_STOP BSP_BIT32(1)
394 
395 /* field: G2_END - Group2 Conversions Ended. */
396 #define TMS570_ADC_G2SR_G2_END BSP_BIT32(0)
397 
398 
399 /*----------------------TMS570_ADC_GxSEL----------------------*/
400 /* field: EV_SEL - Event Group channels selected. */
401 #define TMS570_ADC_GxSEL_EV_SEL(val) BSP_FLD32(val,0, 15)
402 #define TMS570_ADC_GxSEL_EV_SEL_GET(reg) BSP_FLD32GET(reg,0, 15)
403 #define TMS570_ADC_GxSEL_EV_SEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
404 
405 
406 /*----------------------TMS570_ADC_CALR----------------------*/
407 /* field: ADCALR - ADC Calibration Result and Offset Error Correction Value. */
408 #define TMS570_ADC_CALR_ADCALR(val) BSP_FLD32(val,0, 11)
409 #define TMS570_ADC_CALR_ADCALR_GET(reg) BSP_FLD32GET(reg,0, 11)
410 #define TMS570_ADC_CALR_ADCALR_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
411 
412 
413 /*---------------------TMS570_ADC_SMSTATE---------------------*/
414 /* field: LAST_CONV - ADC Input Channel's Last Converted Value. */
415 #define TMS570_ADC_SMSTATE_LAST_CONV(val) BSP_FLD32(val,0, 23)
416 #define TMS570_ADC_SMSTATE_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23)
417 #define TMS570_ADC_SMSTATE_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
418 
419 
420 /*--------------------TMS570_ADC_LASTCONV--------------------*/
421 /* field: LAST_CONV - ADC Input Channel's Last Converted Value. */
422 #define TMS570_ADC_LASTCONV_LAST_CONV(val) BSP_FLD32(val,0, 23)
423 #define TMS570_ADC_LASTCONV_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23)
424 #define TMS570_ADC_LASTCONV_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
425 
426 
427 /*----------------------TMS570_ADC_GxBUF----------------------*/
428 /* field: ADEVT_DIR - ADEVT Pin Direction. */
429 #define TMS570_ADC_GxBUF_ADEVT_DIR BSP_BIT32(0)
430 
431 
432 /*-------------------TMS570_ADC_EVEMUBUFFER-------------------*/
433 /* field: ADEVT_DIR - ADEVT Pin Direction. */
434 #define TMS570_ADC_EVEMUBUFFER_ADEVT_DIR BSP_BIT32(0)
435 
436 
437 /*-------------------TMS570_ADC_G1EMUBUFFER-------------------*/
438 /* field: ADEVT_DIR - ADEVT Pin Direction. */
439 #define TMS570_ADC_G1EMUBUFFER_ADEVT_DIR BSP_BIT32(0)
440 
441 
442 /*-------------------TMS570_ADC_G2EMUBUFFER-------------------*/
443 /* field: ADEVT_DIR - ADEVT Pin Direction. */
444 #define TMS570_ADC_G2EMUBUFFER_ADEVT_DIR BSP_BIT32(0)
445 
446 
447 /*---------------------TMS570_ADC_EVTDIR---------------------*/
448 /* field: ADEVT_DIR - ADEVT Pin Direction. */
449 #define TMS570_ADC_EVTDIR_ADEVT_DIR BSP_BIT32(0)
450 
451 
452 /*---------------------TMS570_ADC_EVTOUT---------------------*/
453 /* field: ADEVT_OUT - ADEVT Pin Output Value. */
454 #define TMS570_ADC_EVTOUT_ADEVT_OUT BSP_BIT32(0)
455 
456 
457 /*----------------------TMS570_ADC_EVTIN----------------------*/
458 /* field: ADEVT_IN - ADEVT Pin Input Value. This is a read-only bit which reflects the logic level on the ADEVT pin. */
459 #define TMS570_ADC_EVTIN_ADEVT_IN BSP_BIT32(0)
460 
461 
462 /*---------------------TMS570_ADC_EVTSET---------------------*/
463 /* field: ADEVT_SET - ADEVT Pin Set. This bit drives the output of the ADEVT pin high. */
464 #define TMS570_ADC_EVTSET_ADEVT_SET BSP_BIT32(0)
465 
466 
467 /*---------------------TMS570_ADC_EVTCLR---------------------*/
468 /* field: ADEVT_CLR - ADEVT Pin Clear. A read from this bit always returns the current state of the ADEVT pin. */
469 #define TMS570_ADC_EVTCLR_ADEVT_CLR BSP_BIT32(0)
470 
471 
472 /*---------------------TMS570_ADC_EVTPDR---------------------*/
473 /* field: ADEVT_PDR - ADEVT Pin Open Drain Enable. */
474 #define TMS570_ADC_EVTPDR_ADEVT_PDR BSP_BIT32(0)
475 
476 
477 /*---------------------TMS570_ADC_EVTPDIS---------------------*/
478 /* field: ADEVT_PDIS - ADEVT Pin Pull Control Disable. */
479 #define TMS570_ADC_EVTPDIS_ADEVT_PDIS BSP_BIT32(0)
480 
481 
482 /*---------------------TMS570_ADC_EVTPSEL---------------------*/
483 /* field: ADEVT_PSEL - ADEVT Pin Pull Control Select. */
484 #define TMS570_ADC_EVTPSEL_ADEVT_PSEL BSP_BIT32(0)
485 
486 
487 /*-------------------TMS570_ADC_EVSAMPDISEN-------------------*/
488 /* field: EV_SAMP_DIS_CYC - Event Group sample cap discharge cycles. */
489 #define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
490 #define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
491 #define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
492 
493 /* field: EV_SAMP_DIS_EN - Event Group sample cap discharge enable. */
494 #define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_EN BSP_BIT32(0)
495 
496 
497 /*-------------------TMS570_ADC_G1SAMPDISEN-------------------*/
498 /* field: G1_SAMP_DIS_CYC - Group1 sample cap discharge cycles. */
499 #define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
500 #define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
501 #define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
502 
503 /* field: G1_SAMP_DIS_EN - Group1 sample cap discharge enable. */
504 #define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_EN BSP_BIT32(0)
505 
506 
507 /*-------------------TMS570_ADC_G2SAMPDISEN-------------------*/
508 /* field: G2_SAMP_DIS_CYC - for which the ADC internal sampling capacitor is allowed to discharge before sampling the input */
509 #define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
510 #define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
511 #define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
512 
513 /* field: G2_SAMP_DIS_EN - Group2 sample cap discharge enable. */
514 #define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_EN BSP_BIT32(0)
515 
516 
517 /*--------------------TMS570_ADC_MAGINTCRx--------------------*/
518 /* field: MAG_CHID2 - These bits specify the channel number from 0 to 31 for which the conversion result needs to be */
519 #define TMS570_ADC_MAGINTCRx_MAG_CHID2(val) BSP_FLD32(val,26, 30)
520 #define TMS570_ADC_MAGINTCRx_MAG_CHID2_GET(reg) BSP_FLD32GET(reg,26, 30)
521 #define TMS570_ADC_MAGINTCRx_MAG_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,26, 30)
522 
523 /* field: MAG_THR2 - These bits specify the 10-bit compare value which the ADC will use for the comparison with the */
524 #define TMS570_ADC_MAGINTCRx_MAG_THR2(val) BSP_FLD32(val,16, 25)
525 #define TMS570_ADC_MAGINTCRx_MAG_THR2_GET(reg) BSP_FLD32GET(reg,16, 25)
526 #define TMS570_ADC_MAGINTCRx_MAG_THR2_SET(reg,val) BSP_FLD32SET(reg, val,16, 25)
527 
528 /* field: COMP_CHID2 - These bits specify the channel number from 0 to 31 whose last conversion result is compared */
529 #define TMS570_ADC_MAGINTCRx_COMP_CHID2(val) BSP_FLD32(val,8, 12)
530 #define TMS570_ADC_MAGINTCRx_COMP_CHID2_GET(reg) BSP_FLD32GET(reg,8, 12)
531 #define TMS570_ADC_MAGINTCRx_COMP_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
532 
533 /* field: CHN_THR_COMP2 - Channel OR Threshold comparison. */
534 #define TMS570_ADC_MAGINTCRx_CHN_THR_COMP2 BSP_BIT32(1)
535 
536 /* field: CMP_GE_LT2 - Greater than or equal to OR Less than comparison operator. */
537 #define TMS570_ADC_MAGINTCRx_CMP_GE_LT2 BSP_BIT32(0)
538 
539 
540 /*-------------------TMS570_ADC_MAGINTxMASK-------------------*/
541 /* field: MAG_INT0_MASK - These bits specify the mask for the comparison in order to generate the magnitude compare */
542 #define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK(val) BSP_FLD32(val,0, 9)
543 #define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_GET(reg) BSP_FLD32GET(reg,0, 9)
544 #define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
545 
546 
547 /*-----------------TMS570_ADC_MAGTHRINTENASET-----------------*/
548 /* field: MAG_INT_ENA_SET - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */
549 #define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET(val) BSP_FLD32(val,0, 2)
550 #define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_GET(reg) BSP_FLD32GET(reg,0, 2)
551 #define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
552 
553 
554 /*-----------------TMS570_ADC_MAGTHRINTENACLR-----------------*/
555 /* field: MAG_INT_ENA_CLR - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */
556 #define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR(val) BSP_FLD32(val,0, 2)
557 #define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_GET(reg) BSP_FLD32GET(reg,0, 2)
558 #define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
559 
560 
561 /*------------------TMS570_ADC_MAGTHRINTFLG------------------*/
562 /* field: MAG_INT_FLG - Magnitude Compare Interrupt Flags. */
563 #define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG(val) BSP_FLD32(val,0, 2)
564 #define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_GET(reg) BSP_FLD32GET(reg,0, 2)
565 #define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
566 
567 
568 /*-----------------TMS570_ADC_MAGTHRINTOFFSET-----------------*/
569 /* field: MAG_INT_OFF - Magnitude Compare Interrupt Offset. */
570 #define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF(val) BSP_FLD32(val,0, 3)
571 #define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_GET(reg) BSP_FLD32GET(reg,0, 3)
572 #define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
573 
574 
575 /*------------------TMS570_ADC_GxFIFORESETCR------------------*/
576 /* field: EV_FIFO_RESET - allows the ADC module to overwrite the contents of the Event Group results memory starting from */
577 #define TMS570_ADC_GxFIFORESETCR_EV_FIFO_RESET BSP_BIT32(0)
578 
579 
580 /*-------------------TMS570_ADC_EVRAMWRADDR-------------------*/
581 /* field: G1_RAM_ADDR - Group1 results memory write pointer. */
582 #define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8)
583 #define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
584 #define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
585 
586 
587 /*-------------------TMS570_ADC_G1RAMWRADDR-------------------*/
588 /* field: G1_RAM_ADDR - Group1 results memory write pointer. */
589 #define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8)
590 #define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
591 #define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
592 
593 
594 /*-------------------TMS570_ADC_G2RAMWRADDR-------------------*/
595 /* field: G2_RAM_ADDR - Group2 results memory write pointer. */
596 #define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR(val) BSP_FLD32(val,0, 8)
597 #define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
598 #define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
599 
600 
601 /*----------------------TMS570_ADC_PARCR----------------------*/
602 /* field: TEST - This bit maps the parity bits into the ADC results' RAM frame so that the application can access */
603 #define TMS570_ADC_PARCR_TEST BSP_BIT32(8)
604 
605 /* field: PARITY_ENA - PARITY ENA */
606 #define TMS570_ADC_PARCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
607 #define TMS570_ADC_PARCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
608 #define TMS570_ADC_PARCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
609 
610 
611 /*---------------------TMS570_ADC_PARADDR---------------------*/
612 /* field: ERROR_ADDRESS - These bits hold the address of the first parity error generated in the ADC results' RAM. */
613 #define TMS570_ADC_PARADDR_ERROR_ADDRESS(val) BSP_FLD32(val,2, 11)
614 #define TMS570_ADC_PARADDR_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,2, 11)
615 #define TMS570_ADC_PARADDR_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,2, 11)
616 
617 
618 /*------------------TMS570_ADC_PWRUPDLYCTRL------------------*/
619 /* field: PWRUP_DLY - This register defines the number of VCLK cycles that the ADC state machine has to wait after */
620 #define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY(val) BSP_FLD32(val,0, 9)
621 #define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY_GET(reg) BSP_FLD32GET(reg,0, 9)
622 #define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
623 
624 
625 
626 #endif /* LIBBSP_ARM_TMS570_ADC */
tms570_gxbuf_t
Definition: reg_adc.h:44
utility.h
Utility macros.
tms570_adc_t
Definition: reg_adc.h:55
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