RTEMS  5.1
pxa255.h
1 /*
2  * By Yang Xi <hiyangxi@gmail.com>.
3  *
4  * The license and distribution terms for this file may be
5  * found in the file LICENSE in this distribution or at
6  * http://www.rtems.org/license/LICENSE.
7  */
8 
9 #ifndef __PXA_255_H__
10 #define __PXA_255_H__
11 
12 typedef unsigned int word_t;
13 
14 /*Interrupt*/
15 
16 #define PRIMARY_IRQS 32
17 #define GPIO_IRQS (85 - 2) /* The first two IRQs have level
18  one interrupts */
19 #define GPIO_IRQ 10
20 
21 #define IRQS (PRIMARY_IRQS + GPIO_IRQS)
22 
23 /* Interrupt Controller */
24 #define INTERRUPT_OFFSET 0xd00000
25 #define XSCALE_IRQ_OS_TIMER 26
26 #define XSCALE_IRQ_PMU 12
27 #define XSCALE_IRQ_STUART 20
28 #define XSCALE_IRQ_NETWORK 16
29 
30 #define PMU_IRQ 12
31 #define CCNT_IRQ_ENABLE 1UL << 6
32 #define PMN1_IRQ_ENABLE 1UL << 5
33 #define PMN0_IRQ_ENABLE 1UL << 4
34 
35 #define IODEVICE_VADDR 0x40000000
36 #define XSCALE_INT (IODEVICE_VADDR + INTERRUPT_OFFSET)
37 
38 #define XSCALE_INT_ICMR (*(volatile word_t *)(XSCALE_INT + 0x04)) /* Mask register */
39 #define XSCALE_INT_ICLR (*(volatile word_t *)(XSCALE_INT + 0x08)) /* FIQ / IRQ selection */
40 #define XSCALE_INT_ICCR (*(volatile word_t *)(XSCALE_INT + 0x14)) /* Control register */
41 #define XSCALE_INT_ICIP (*(volatile word_t *)(XSCALE_INT + 0x00)) /* IRQ pending */
42 #define XSCALE_INT_ICFP (*(volatile word_t *)(XSCALE_INT + 0x0c)) /* FIQ pending */
43 #define XSCALE_INT_ICPR (*(volatile word_t *)(XSCALE_INT + 0x10)) /* Pending (unmasked) */
44 
45 /* GPIO */
46 #define GPIO_OFFSET 0xe00000
47 #define PXA_GPIO (IODEVICE_VADDR + GPIO_OFFSET)
48 
49 #define PXA_GEDR0 (*(volatile word_t *)(PXA_GPIO + 0x48)) /* GPIO edge detect 0 */
50 #define PXA_GEDR1 (*(volatile word_t *)(PXA_GPIO + 0x4C)) /* GPIO edge detect 1 */
51 #define PXA_GEDR2 (*(volatile word_t *)(PXA_GPIO + 0x50)) /* GPIO edge detect 2 */
52 
53 
54 /* PXA2XX Timer */
55 
56 #define TIMER_OFFSET 0x0a00000
57 #define CLOCKS_OFFSET 0x1300000
58 /*I change the TIMER_RATE to 36864,because when I use 3686400, the period will be calculate
59  to 30000*/
60 #define TIMER_RATE 36864
61 
62 #define XSCALE_TIMERS (IODEVICE_VADDR + TIMER_OFFSET)
63 
64 /* Match registers */
65 #define XSCALE_OS_TIMER_MR0 (*(volatile word_t *)(XSCALE_TIMERS + 0x00))
66 #define XSCALE_OS_TIMER_MR1 (*(volatile word_t *)(XSCALE_TIMERS + 0x04))
67 #define XSCALE_OS_TIMER_MR2 (*(volatile word_t *)(XSCALE_TIMERS + 0x08))
68 #define XSCALE_OS_TIMER_MR3 (*(volatile word_t *)(XSCALE_TIMERS + 0x0c))
69 
70 /* Interrupt enable register */
71 #define XSCALE_OS_TIMER_IER (*(volatile word_t *)(XSCALE_TIMERS + 0x1c))
72 /* Watchdog match enable register */
73 #define XSCALE_OS_TIMER_WMER (*(volatile word_t *)(XSCALE_TIMERS + 0x18))
74 /* Timer count register */
75 #define XSCALE_OS_TIMER_TCR (*(volatile word_t *)(XSCALE_TIMERS + 0x10))
76 /* Timer status register */
77 #define XSCALE_OS_TIMER_TSR (*(volatile word_t *)(XSCALE_TIMERS + 0x14))
78 
79 #define XSCALE_CLOCKS (IODEVICE_VADDR + CLOCKS_VOFFSET)
80 
81 #define XSCALE_CLOCKS_CCCR (*(volatile word_t *)(XSCALE_CLOCKS + 0x00))
82 
83 /*Use ffuart port as the console*/
84 #define FFUART_BASE 0x40100000
85 
86 /*Write to SKYEYE_MAGIC_ADDRESS to make SKYEYE exit*/
87 
88 #define SKYEYE_MAGIC_ADDRESS (*(volatile word_t *)(0xb0000000))
89 #define SKYEYE_MAGIC_NUMBER (0xf0f0f0f0)
90 
91 /*PMC*/
92 #define PMC_PMNC 0
93 #define PMC_CCNT 1
94 #define PMC_INTEN 2
95 #define PMC_FLAG 3
96 #define PMC_EVTSEL 4
97 #define PMC_PMN0 5
98 #define PMC_PMN1 6
99 #define PMC_PMN2 7
100 #define PMC_PMN3 8
101 
102 #define PMC_PMNC_E (0x01)
103 #define PMC_PMNC_PCR (0x01 << 1)
104 #define PMC_PMNC_CCR (0x01 << 2)
105 #define PMC_PMNC_CCD (0x01 << 3)
106 #define PMC_PMNC_PCD (0x01 << 4)
107 
108 /*LCD*/
109 #define LCCR0 (*(volatile word_t *)(0x44000000))
110 #define LCCR1 (*(volatile word_t *)(0x44000004))
111 #define LCCR2 (*(volatile word_t *)(0x44000008))
112 #define LCCR3 (*(volatile word_t *)(0x4400000C))
113 
114 #define FDADR0 (*(volatile word_t *)(0x44000200))
115 #define FSADR0 (*(volatile word_t *)(0x44000204))
116 #define FIDR0 (*(volatile word_t *)(0x44000208))
117 #define LDCMD0 (*(volatile word_t *)(0x4400020C))
118 
119 #define FDADR1 (*(volatile word_t *)(0x44000210))
120 #define FSADR1 (*(volatile word_t *)(0x44000214))
121 #define FIDR1 (*(volatile word_t *)(0x44000218))
122 #define LDCMD1 (*(volatile word_t *)(0x4400021C))
123 
124 #define LCCR0_ENB 0x00000001
125 #define LCCR1_PPL 0x000003FF
126 #define LCCR2_LPP 0x000003FF
127 #define LCCR3_BPP 0x07000000
128 #endif
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