RTEMS  5.1
pic.h
1 /*
2  * Copyright (c) 2018.
3  * Amaan Cheval <amaan.cheval@gmail.com>
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #ifndef _AMD64_PIC_H
28 #define _AMD64_PIC_H
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
34 #define PIC1 0x20 /* IO base address for master PIC */
35 #define PIC2 0xA0 /* IO base address for slave PIC */
36 #define PIC1_COMMAND PIC1
37 #define PIC1_DATA (PIC1+1)
38 #define PIC2_COMMAND PIC2
39 #define PIC2_DATA (PIC2+1)
40 
41 /* reinitialize the PIC controllers, giving them specified vector offsets
42  rather than 8h and 70h, as configured by default */
43 
44 #define PIC_ICW1_ICW4 0x01 /* ICW4 (not) needed */
45 #define PIC_ICW1_SINGLE 0x02 /* Single (cascade) mode */
46 #define PIC_ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */
47 #define PIC_ICW1_LEVEL 0x08 /* Level triggered (edge) mode */
48 #define PIC_ICW1_INIT 0x10 /* Initialization - required! */
49 
50 #define PIC_ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */
51 #define PIC_ICW4_AUTO 0x02 /* Auto (normal) EOI */
52 #define PIC_ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */
53 #define PIC_ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
54 #define PIC_ICW4_SFNM 0x10 /* Special fully nested (not) */
55 
56 /* This remaps IRQ0 to vector number 0x20 and so on (i.e. IDT[32]) */
57 #define PIC1_REMAP_DEST 0x20
58 #define PIC2_REMAP_DEST 0x28
59 
60 /* Remap PIC1's interrupts to offset1 and PIC2's to offset2 */
61 void pic_remap(uint8_t offset1, uint8_t offset2);
62 
69 void pic_disable(void);
70 
71 #ifdef __cplusplus
72 }
73 #endif
74 
75 #endif /* _AMD64_PIC_H */
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