RTEMS  5.1
pcf8563.h
1 /*===============================================================*\
2 | Project: RTEMS generic MPC5200 BSP |
3 +-----------------------------------------------------------------+
4 | Partially based on the code references which are named below. |
5 | Adaptions, modifications, enhancements and any recent parts of |
6 | the code are: |
7 | Copyright (c) 2005 |
8 | Embedded Brains GmbH |
9 | Obere Lagerstr. 30 |
10 | D-82178 Puchheim |
11 | Germany |
12 | rtems@embedded-brains.de |
13 +-----------------------------------------------------------------+
14 | The license and distribution terms for this file may be |
15 | found in the file LICENSE in this distribution or at |
16 | |
17 | http://www.rtems.org/license/LICENSE. |
18 | |
19 +-----------------------------------------------------------------+
20 | this file contains declarations for the pcf8563 RTC driver |
21 \*===============================================================*/
22 /*
23  * This file contains the definitions for Dallas Semiconductor
24  * DS1307/DS1308 serial real-time clock/NVRAM.
25  *
26  * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
27  * Author: Victor V. Vengerov <vvv@oktet.ru>
28  *
29  * The license and distribution terms for this file may be
30  * found in the file LICENSE in this distribution or at
31  *
32  * http://www.rtems.org/license/LICENSE.
33  */
34 
35 #ifndef __RTC_PCF8563__
36 #define __RTC_PCF8563__
37 
38 #define PCF8563_I2C_ADDRESS (0xA2) /* I2C bus address assigned to PCF8563 */
39 
40 #define PCF8563_CONTROL1_ADR (0x00)
41 #define PCF8563_CONTROL1_TEST1 (0x80) /* EXT_CLK test mode */
42 #define PCF8563_CONTROL1_STOP (0x20) /* stop RTC source clock, clear divider*/
43 #define PCF8563_CONTROL1_TESTC (0x08) /* enable power-on reset override */
44  /***********/
45 #define PCF8563_CONTROL2_ADR (0x01)
46 #define PCF8563_CONTROL2_TITP (0x10) /* 0: int output is level */
47 #define PCF8563_CONTROL2_AF (0x08) /* alarm flag */
48 #define PCF8563_CONTROL2_TF (0x04) /* timer flag */
49 #define PCF8563_CONTROL2_AIE (0x02) /* alarm interrupt enable */
50 #define PCF8563_CONTROL2_TIE (0x01) /* timer interrupt enable */
51  /***********/
52 
53 #define PCF8563_SECOND_ADR (0x02)
54 #define PCF8563_SECOND_VL (0x80) /* clock integrity no longer guaranteed */
55 #define PCF8563_SECOND_MASK (0x7f)
56  /***********/
57 
58 #define PCF8563_MINUTE_ADR (0x03)
59 #define PCF8563_MINUTE_MASK (0x7f)
60  /***********/
61 
62 #define PCF8563_HOUR_ADR (0x04)
63 #define PCF8563_HOUR_MASK (0x3f)
64  /***********/
65 
66 #define PCF8563_DAY_ADR (0x05)
67 #define PCF8563_DAY_MASK (0x3f)
68 
69 #define PCF8563_DAY_OF_WEEK_ADR (0x06)
70 #define PCF8563_DAY_OF_WEEK_MASK (0x07)
71 
72 #define PCF8563_MONTH_ADR (0x07)
73 #define PCF8563_MONTH_MASK (0x1f)
74 #define PCF8563_MONTH_CENTURY (0x80)
75  /***********/
76 
77 #define PCF8563_YEAR_ADR (0x08)
78 #define PCF8563_YEAR_MASK (0xff)
79 
80 #define PCF8563_MINUTE_ALARM_ADR (0x09)
81 #define PCF8563_HOUR_ALARM_ADR (0x0A)
82 #define PCF8563_DAY_ALARM_ADR (0x0B)
83 #define PCF8563_DAY_OF_WEEK_ALARM_ADR (0x0C)
84 #define PCF8563_XXX_ALARM_AE (0x80)
85  /***********/
86 
87 #define PCF8563_CLKOUTCTL_ADR (0x0D)
88 #define PCF8563_CLKOUTCTL_FE (0x80) /* */
89 #define PCF8563_CLKOUTCTL_FD (0x03) /* */
90  /***********/
91 
92 #define PCF8563_TIMERCTL_ADR (0x0E)
93 #define PCF8563_TIMERCTL_FE (0x80) /* */
94 #define PCF8563_TIMERCTL_FD (0x03) /* */
95  /***********/
96 
97 #define PCF8563_TIMER_ADR (0x0F)
98 
99 #endif /* __RTC_PCF8563__ */
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